diff --git a/.project b/.project deleted file mode 100644 index 0b76a40ba..000000000 --- a/.project +++ /dev/null @@ -1,17 +0,0 @@ - - - processing-head - - - - - - org.eclipse.jdt.core.javabuilder - - - - - - org.eclipse.jdt.core.javanature - - diff --git a/app/.classpath b/app/.classpath index 26775c499..4589f3f47 100644 --- a/app/.classpath +++ b/app/.classpath @@ -2,19 +2,11 @@ - - - - - - - - - - - + + + diff --git a/app/src/processing/app/debug/AvrdudeUploader.java b/app/src/processing/app/debug/AvrdudeUploader.java old mode 100755 new mode 100644 diff --git a/app/src/processing/app/debug/BossaCUploader.java b/app/src/processing/app/debug/BossaCUploader.java new file mode 100644 index 000000000..d91e771e0 --- /dev/null +++ b/app/src/processing/app/debug/BossaCUploader.java @@ -0,0 +1,104 @@ +/* -*- mode: jde; c-basic-offset: 2; indent-tabs-mode: nil -*- */ + +/* + AvrdudeUploader - uploader implementation using avrdude + Part of the Arduino project - http://www.arduino.cc/ + + Copyright (c) 2011 Cristian Maglie + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + $Id$ + */ + +package processing.app.debug; + +import java.io.File; +import java.util.ArrayList; +import java.util.Collection; +import java.util.List; + +import processing.app.Base; +import processing.app.Preferences; +import processing.app.SerialException; + +public class BossaCUploader extends Uploader { + + public boolean uploadUsingPreferences(String buildPath, String className, + boolean usingProgrammer) + throws RunnerException, SerialException { + List commandDownloader = new ArrayList(); + String port = Preferences.get("serial.port"); + if (port.startsWith("/dev/")) + port = port.substring(5); + commandDownloader.add("--port=" + port); + commandDownloader.add("-e"); + commandDownloader.add("-w"); + commandDownloader.add("-v"); + commandDownloader.add("-b"); + commandDownloader.add(buildPath + File.separator + className + ".bin"); + + return bossac(commandDownloader); + } + + public boolean burnBootloader() { + return true; + } + + public boolean bossac(Collection params) throws RunnerException { + List commandDownloader = new ArrayList(); + commandDownloader.add("bossac"); + + if (verbose || Preferences.getBoolean("upload.verbose")) { + commandDownloader.add("-i"); + commandDownloader.add("-d"); + } + commandDownloader.addAll(params); + + return executeUploadCommand(commandDownloader); + } + + protected boolean executeUploadCommand(List cmdParams) + throws RunnerException { + + try { + String avrBasePath = Base.getHardwarePath() + "/tools/"; + + String[] cmdArray = cmdParams.toArray(new String[0]); + cmdArray[0] = avrBasePath + cmdArray[0]; + + if (verbose || Preferences.getBoolean("upload.verbose")) { + for (String cmd : cmdArray) + System.out.print(cmd + " "); + System.out.println(); + } + + Process bossac = Runtime.getRuntime().exec(cmdArray); + new MessageSiphon(bossac.getInputStream(), this); + new MessageSiphon(bossac.getErrorStream(), this); + + // wait for the process to finish. if interrupted + // before waitFor returns, continue waiting + int result = bossac.waitFor(); + if (result != 0) + return false; + return true; + } catch (Exception e) { + e.printStackTrace(); + return false; + } + } + +} diff --git a/app/src/processing/app/debug/Sizer.java b/app/src/processing/app/debug/Sizer.java index d67728a3c..2b4dfd80f 100644 --- a/app/src/processing/app/debug/Sizer.java +++ b/app/src/processing/app/debug/Sizer.java @@ -1,67 +1,77 @@ /* -*- mode: jde; c-basic-offset: 2; indent-tabs-mode: nil -*- */ /* - Sizer - computes the size of a .hex file - Part of the Arduino project - http://www.arduino.cc/ + Sizer - computes the size of a .hex file + Part of the Arduino project - http://www.arduino.cc/ - Copyright (c) 2006 David A. Mellis + Copyright (c) 2006 David A. Mellis - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software Foundation, - Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - $Id$ -*/ + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + $Id$ + */ package processing.app.debug; -import processing.app.Base; - -import java.io.*; -import java.util.*; +import java.io.File; +import java.text.MessageFormat; +import java.util.Map; +import java.util.NoSuchElementException; +import java.util.StringTokenizer; public class Sizer implements MessageConsumer { private String buildPath, sketchName; + private String firstLine; + private long size; + private RunnerException exception; - public Sizer(String buildPath, String sketchName) { + private Map prefs; + + public Sizer(String buildPath, String sketchName, + Map prefs) { this.buildPath = buildPath; this.sketchName = sketchName; + this.prefs = prefs; } - + public long computeSize() throws RunnerException { - String avrBasePath = Base.getAvrBasePath(); - String commandSize[] = new String[] { - avrBasePath + "avr-size", - " " - }; - - commandSize[1] = buildPath + File.separator + sketchName + ".hex"; + String args[] = new String[3]; + args[0] = prefs.get("compiler.path"); + args[1] = prefs.get("compiler.size.cmd"); + args[2] = buildPath + File.separator + sketchName; + + String recipe = prefs.get("recipe.size.pattern"); + MessageFormat compileFormat = new MessageFormat(recipe); + String command = compileFormat.format(args); + String[] commandArray = command.split("\\|"); int r = 0; try { exception = null; size = -1; firstLine = null; - Process process = Runtime.getRuntime().exec(commandSize); + Process process = Runtime.getRuntime().exec(commandArray); MessageSiphon in = new MessageSiphon(process.getInputStream(), this); MessageSiphon err = new MessageSiphon(process.getErrorStream(), this); boolean running = true; - while(running) { + while (running) { try { if (in.thread != null) in.thread.join(); @@ -69,25 +79,28 @@ public class Sizer implements MessageConsumer { err.thread.join(); r = process.waitFor(); running = false; - } catch (InterruptedException intExc) { } + } catch (InterruptedException intExc) { + } } } catch (Exception e) { // The default Throwable.toString() never returns null, but apparently // some sub-class has overridden it to do so, thus we need to check for - // it. See: http://www.arduino.cc/cgi-bin/yabb2/YaBB.pl?num=1166589459 - exception = new RunnerException( - (e.toString() == null) ? e.getClass().getName() + r : e.toString() + r); + // it. See: http://www.arduino.cc/cgi-bin/yabb2/YaBB.pl?num=1166589459 + if (e.toString() == null) + exception = new RunnerException(e.getClass().getName() + r); + else + exception = new RunnerException(e.toString() + r); } - + if (exception != null) throw exception; - + if (size == -1) throw new RunnerException(firstLine); - + return size; } - + public void message(String s) { if (firstLine == null) firstLine = s; diff --git a/app/src/processing/app/debug/Uploader.java b/app/src/processing/app/debug/Uploader.java old mode 100755 new mode 100644 diff --git a/build/linux/dist/tools/bossac b/build/linux/dist/tools/bossac new file mode 100755 index 000000000..bba40b71c Binary files /dev/null and b/build/linux/dist/tools/bossac differ diff --git a/build/linux/dist/tools/bossac64 b/build/linux/dist/tools/bossac64 new file mode 100755 index 000000000..b75546546 Binary files /dev/null and b/build/linux/dist/tools/bossac64 differ diff --git a/build/macosx/dist/CodeSourcery_arm.zip b/build/macosx/dist/CodeSourcery_arm.zip new file mode 100644 index 000000000..032c42943 Binary files /dev/null and b/build/macosx/dist/CodeSourcery_arm.zip differ diff --git a/build/macosx/dist/bossac b/build/macosx/dist/bossac new file mode 100755 index 000000000..18cb43eb7 Binary files /dev/null and b/build/macosx/dist/bossac differ diff --git a/build/macosx/template.dmg.gz b/build/macosx/template.dmg.gz index 70405c676..cb966b320 100644 Binary files a/build/macosx/template.dmg.gz and b/build/macosx/template.dmg.gz differ diff --git a/build/windows/CodeSourcery_arm.zip b/build/windows/CodeSourcery_arm.zip new file mode 100644 index 000000000..56ae4546b Binary files /dev/null and b/build/windows/CodeSourcery_arm.zip differ diff --git a/build/windows/bossac.exe b/build/windows/bossac.exe new file mode 100644 index 000000000..2e9530e01 Binary files /dev/null and b/build/windows/bossac.exe differ diff --git a/build/windows/dist/drivers/bossa.inf b/build/windows/dist/drivers/bossa.inf new file mode 100755 index 000000000..1722074f3 --- /dev/null +++ b/build/windows/dist/drivers/bossa.inf @@ -0,0 +1,48 @@ +[Version] ; Version section +Signature="$Chicago$" ; All Windows versions +Class=Ports ; This is a serial port driver +ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318} ; Associated GUID +Provider=%SHUMATECH% ; Driver is provided by SHUMATECH +DriverVer=05/18/2011,1.0 ; Driver version + +[DestinationDirs] ; DestinationDirs section +DefaultDestDir=12 ; Default install directory is \drivers or \IOSubSys + +[Manufacturer] ; Manufacturer section +%SHUMATECH%=ShumaTech,NTamd64 ; Only one manufacturer (SHUMATECH), models section is named + ; ShumaTech + +[ShumaTech] ; Models section corresponding to SHUMATECH +%BOSSA%=BOSSA.Install,USB\VID_03EB&PID_6124 ; Identifies a device with Vendor ID (03EBh) and + ; Product ID equal to 6124h. Corresponding Install section + ; is named BOSSA.Install + +[ShumaTech.NTamd64] ; Models section corresponding to SHUMATECH +%BOSSA%=BOSSA.Install,USB\VID_03EB&PID_6124 ; Identifies a device with Vendor ID (03EBh) and + ; Product ID equal to 6124h. Corresponding Install section + ; is named BOSSA.Install + +[BOSSA.Install] ; Install section +include=mdmcpq.inf +CopyFiles=FakeModemCopyFileSection +AddReg=BOSSA.AddReg ; Registry keys to add are listed in BOSSA.AddReg + +[BOSSA.AddReg] ; AddReg section +HKR,,DevLoader,,*ntkern +HKR,,NTMPDriver,,usbser.sys +HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" + +[BOSSA.Install.Services] ; Services section +AddService=usbser,0x00000002,BOSSA.AddService ; Assign usbser as the PnP driver for the device + +[BOSSA.AddService] ; Service install section +DisplayName=%USBSer% ; Name of the serial driver +ServiceType=1 ; Service kernel driver +StartType=3 ; Driver is started by the PnP manager +ErrorControl=1 ; Warn about errors +ServiceBinary=%12%\usbser.sys ; Driver filename + +[Strings] ; Strings section +SHUMATECH="ShumaTech" ; String value for the SHUMATECH symbol +BOSSA="BOSSA Program Port" ; String value for the BOSSA symbol +USBSer="USB Serial Driver" ; String value for the USBSer symbol diff --git a/hardware/sam/boards.txt b/hardware/sam/boards.txt new file mode 100644 index 000000000..ec43dd61b --- /dev/null +++ b/hardware/sam/boards.txt @@ -0,0 +1,54 @@ +############################################################## + +sam3s_ek.name=Atmel SAM3S-EK +sam3s_ek.platform=sam +sam3s_ek.upload.protocol=sam-ba +sam3s_ek.upload.maximum_size=49152 +sam3s_ek.upload.speed=115200 +sam3s_ek.bootloader.path=sam3s_boot +sam3s_ek.bootloader.file=sam3s_boot.bin +sam3s_ek.build.mcu=cortex-m3 +sam3s_ek.build.f_cpu=64000000L +sam3s_ek.build.core=sam +sam3s_ek.build.pins=sam3s_ek + +############################################################## + +sam3u_ek.name=Atmel SAM3U-EK +sam3u_ek.platform=sam +sam3u_ek.upload.protocol=sam-ba +sam3u_ek.upload.maximum_size=49152 +sam3u_ek.upload.speed=115200 +sam3u_ek.bootloader.path=sam3u_boot +sam3u_ek.bootloader.file=sam3u_boot.bin +sam3u_ek.build.mcu=cortex-m3 +sam3u_ek.build.f_cpu=96000000L +sam3u_ek.build.core=sam +sam3u_ek.build.pins=sam3u_ek + +############################################################## + +arduino_due.name=Arduino Due +arduino_due.platform=sam +arduino_due.uploader=bossac +arduino_due.upload.maximum_size=49152 +arduino_due.upload.speed=115200 +#arduino_due.bootloader.path=sam3u_boot +#arduino_due.bootloader.file=sam3u_boot.bin +arduino_due.build.mcu=cortex-m3 +arduino_due.build.f_cpu=96000000L +arduino_due.build.core=sam +arduino_due.build.pins=arduino_due +arduino_due.build.extra_flags=-D__SAM3U4E__ +arduino_due.build.extra_include_dirs=system/libsam|system/libsam/include|system/CMSIS/Include|system/libsam/cmsis/sam3u/source/templates|system/libsam/cmsis/sam3u/include +arduino_due.core.extra_source_dirs=sam +arduino_due.system.extra_source_dirs=libsam/source|libsam/cmsis/sam3u/source/templates|libsam/cmsis/sam3u/source/templates/gcc +arduino_due.variants.extra_source_dirs=arduino_due|common +#hardware/sam/system/libsam/source/ +#hardware/sam/system/libsam/cmsis/sam3u/source/ +#hardware/sam/variants/arduino_due +#hardware/sam/variants/common +#hardware/sam/cores/sam +arduino_due.build.ldscript=linker_scripts/gcc/flash.ld + + diff --git a/hardware/sam/bootloaders/sam3_samba/linker_script/flash.ld b/hardware/sam/bootloaders/sam3_samba/linker_script/flash.ld new file mode 100644 index 000000000..c47a2c508 --- /dev/null +++ b/hardware/sam/bootloaders/sam3_samba/linker_script/flash.ld @@ -0,0 +1,140 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2009, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAM3S4 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash, 256K */ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x0000c000 /* sram, 48K */ +} + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + *(.stack .stack.*) + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/hardware/sam/cores/sam/Arduino.h b/hardware/sam/cores/sam/Arduino.h new file mode 100644 index 000000000..e0b11199e --- /dev/null +++ b/hardware/sam/cores/sam/Arduino.h @@ -0,0 +1,180 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef Arduino_h +#define Arduino_h + +#include +#include +#include +#include + +#include "binary.h" + +#ifdef __cplusplus +extern "C"{ +#endif // __cplusplus + +#include "libsam/chip.h" +#include "wiring_constants.h" + +#define clockCyclesPerMicrosecond() ( SystemCoreClock / 1000000L ) +#define clockCyclesToMicroseconds(a) ( ((a) * 1000L) / (SystemCoreClock / 1000L) ) +#define microsecondsToClockCycles(a) ( (a) * (SystemCoreClock / 1000000L) ) + + +#include "wiring.h" +#include "wiring_digital.h" +#include "wiring_analog.h" +#include "wiring_shift.h" +#include "WInterrupts.h" + +/* sketch */ +extern void setup( void ) ; +extern void loop( void ) ; + +// Get the bit location within the hardware port of the given virtual pin. +// This comes from the pins_*.c file for the active board configuration. +// +// These perform slightly better as macros compared to inline functions +// +#define digitalPinToPort( ulPin ) ( g_APinDescription[ulPin]->pPort->PIO_PDSR ) +#define digitalPinToBitMask( ulPin ) ( g_APinDescription[ulPin]->dwPin ) +#define digitalPinToTimer( P ) ( ) +#define analogInPinToBit( P ) ( P ) +#define portOutputRegister( P ) ( ) +#define portInputRegister( P ) ( ) +#define portModeRegister( P ) ( ) + +//#define NOT_A_PIN 0 // defined in pio.h/EPioType +#define NOT_A_PORT 0 + +#define NOT_ON_TIMER 0 +#define TIMER0 1 + +typedef enum _EExt_Interrupts +{ + EXTERNAL_INT_0=0, + EXTERNAL_INT_1=1, + EXTERNAL_INT_2=2, + EXTERNAL_INT_3=3, + EXTERNAL_INT_4=4, + EXTERNAL_INT_5=5, + EXTERNAL_INT_6=6, + EXTERNAL_INT_7=7, + EXTERNAL_NUM_INTERRUPTS +} EExt_Interrupts ; + +typedef void (*voidFuncPtr)( void ) ; + +/* Define attribute */ +#if defined ( __CC_ARM ) /* Keil uVision 4 */ + #define WEAK (__attribute__ ((weak))) +#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */ + #define WEAK __weak +#elif defined ( __GNUC__ ) /* GCC CS */ + #define WEAK __attribute__ ((weak)) +#endif + +/* Definitions and types for pins */ +typedef enum _EAnalogChannel +{ + NO_ADC=-1, + ADC0=0, + ADC1, + ADC2, + ADC3, + ADC4, + ADC5, + ADC6, + ADC7, + ADC8, + ADC9, + ADC10, + ADC11, + ADC12, + ADC13, + ADC14, + ADC15, + DAC0, + DAC1 +} EAnalogChannel ; + +#define ADC_CHANNEL_NUMBER_NONE 0xffffffff + +// Definitions for PWM channels +typedef enum _EPWMChannel +{ + NO_PWM=-1, + PWM_CH0=0, + PWM_CH1, + PWM_CH2, + PWM_CH3 +} EPWMChannel ; + +// Definitions for TC channels +typedef enum _ETCChannel +{ + NO_TC=-1, + TC0_CHA0=0, + TC0_CHB0, + TC0_CHA1, + TC0_CHB1, + TC0_CHA2, + TC0_CHB2 +} ETCChannel ; + +/** + * Pin Attributes to be OR-ed + */ +#define PIN_ATTR_COMBO (1UL<<0) +#define PIN_ATTR_ANALOG (1UL<<1) +#define PIN_ATTR_DIGITAL (1UL<<2) +#define PIN_ATTR_PWM (1UL<<3) +#define PIN_ATTR_TIMER (1UL<<4) + +/* Types used for the tables below */ +typedef struct _PinDescription +{ + Pio* pPort ; + uint32_t ulPin ; + uint32_t ulPeripheralId ; + EPioType ulPinType ; + uint32_t ulPinConfiguration ; + uint32_t ulPinAttribute ; + EAnalogChannel ulAnalogChannel ; /* Describe which Analog pin is linked to a MCU pin */ + EAnalogChannel ulADCChannelNumber ; /* We use the same enum than for ADC pins to describe the ADC channel in use on this pin */ + EPWMChannel ulPWMChannel ; + ETCChannel ulTCChannel ; +} PinDescription ; + +/* Pins table to be instanciated into variant.cpp */ +extern const PinDescription g_APinDescription[] ; + +#ifdef __cplusplus +} // extern "C" + +#include "WCharacter.h" +#include "WString.h" +#include "Tone.h" +#include "WMath.h" +#include "HardwareSerial.h" +#include "wiring_pulse.h" +#endif // __cplusplus + +#endif // Arduino_h diff --git a/hardware/sam/cores/sam/CDC.cpp b/hardware/sam/cores/sam/CDC.cpp new file mode 100644 index 000000000..fb980ab75 --- /dev/null +++ b/hardware/sam/cores/sam/CDC.cpp @@ -0,0 +1,174 @@ + + +/* Copyright (c) 2011, Peter Barrett +** +** Permission to use, copy, modify, and/or distribute this software for +** any purpose with or without fee is hereby granted, provided that the +** above copyright notice and this permission notice appear in all copies. +** +** THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL +** WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR +** BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES +** OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +** WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +** ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +** SOFTWARE. +*/ + +#include "Platform.h" +#include "USBAPI.h" + +#if defined(USBCON) +#ifdef CDC_ENABLED + +void Reboot() +{ + USB.detach(); + cli(); + asm volatile("jmp 0x7800"); // jump to bootloader - DiskLoader takes up last 2 kB +} + +typedef struct +{ + u32 dwDTERate; + u8 bCharFormat; + u8 bParityType; + u8 bDataBits; + u8 lineState; +} LineInfo; + +static volatile LineInfo _usbLineInfo = { 57600, 0x00, 0x00, 0x00, 0x00 }; + +#define WEAK __attribute__ ((weak)) + +extern const CDCDescriptor _cdcInterface PROGMEM; +const CDCDescriptor _cdcInterface = +{ + D_IAD(0,2,CDC_COMMUNICATION_INTERFACE_CLASS,CDC_ABSTRACT_CONTROL_MODEL,1), + + // CDC communication interface + D_INTERFACE(CDC_ACM_INTERFACE,1,CDC_COMMUNICATION_INTERFACE_CLASS,CDC_ABSTRACT_CONTROL_MODEL,0), + D_CDCCS(CDC_HEADER,0x10,0x01), // Header (1.10 bcd) + D_CDCCS(CDC_CALL_MANAGEMENT,1,1), // Device handles call management (not) + D_CDCCS4(CDC_ABSTRACT_CONTROL_MANAGEMENT,6), // SET_LINE_CODING, GET_LINE_CODING, SET_CONTROL_LINE_STATE supported + D_CDCCS(CDC_UNION,CDC_ACM_INTERFACE,CDC_DATA_INTERFACE), // Communication interface is master, data interface is slave 0 + D_ENDPOINT(USB_ENDPOINT_IN (CDC_ENDPOINT_ACM),USB_ENDPOINT_TYPE_INTERRUPT,0x10,0x40), + + // CDC data interface + D_INTERFACE(CDC_DATA_INTERFACE,2,CDC_DATA_INTERFACE_CLASS,0,0), + D_ENDPOINT(USB_ENDPOINT_OUT(CDC_ENDPOINT_OUT),USB_ENDPOINT_TYPE_BULK,0x40,0), + D_ENDPOINT(USB_ENDPOINT_IN (CDC_ENDPOINT_IN ),USB_ENDPOINT_TYPE_BULK,0x40,0) +}; + +int WEAK CDC_GetInterface(u8* interfaceNum) +{ + interfaceNum[0] += 2; // uses 2 + return USB_SendControl(TRANSFER_PGM,&_cdcInterface,sizeof(_cdcInterface)); +} + +bool WEAK CDC_Setup(Setup& setup) +{ + u8 r = setup.bRequest; + u8 requestType = setup.bmRequestType; + + if (REQUEST_DEVICETOHOST_CLASS_INTERFACE == requestType) + { + if (CDC_GET_LINE_CODING == r) + { + USB_SendControl(0,(void*)&_usbLineInfo,7); + return true; + } + } + + if (REQUEST_HOSTTODEVICE_CLASS_INTERFACE == requestType) + { + if (CDC_SET_LINE_CODING == r) + { + USB_RecvControl((void*)&_usbLineInfo,7); + return true; + } + + if (CDC_SET_CONTROL_LINE_STATE == r) + { + if (0 != _usbLineInfo.lineState && 1200 == _usbLineInfo.dwDTERate) // auto-reset is triggered when the port, already open at 1200 bps, is closed + Reboot(); + _usbLineInfo.lineState = setup.wValueL; + return true; + } + } + return false; +} + + +int _serialPeek = -1; +void Serial_::begin(uint16_t baud_count) +{ +} + +void Serial_::end(void) +{ +} + +int Serial_::available(void) +{ + u8 avail = USB_Available(CDC_RX); + if (_serialPeek != -1) + avail++; + return avail; +} + +// peek is nasty +int Serial_::peek(void) +{ + if (_serialPeek == -1) + _serialPeek = read(); + return _serialPeek; +} + +int Serial_::read(void) +{ + int c; + if (_serialPeek != -1) + { + c = _serialPeek; + _serialPeek = -1; + } else { + c = USB_Recv(CDC_RX); + } + return c; +} + +void Serial_::flush(void) +{ + USB_Flush(CDC_TX); +} + +size_t Serial_::write(uint8_t c) +{ + /* only try to send bytes if the high-level CDC connection itself + is open (not just the pipe) - the OS should set lineState when the port + is opened and clear lineState when the port is closed. + bytes sent before the user opens the connection or after + the connection is closed are lost - just like with a UART. */ + + // TODO - ZE - check behavior on different OSes and test what happens if an + // open connection isn't broken cleanly (cable is yanked out, host dies + // or locks up, or host virtual serial port hangs) + if (_usbLineInfo.lineState > 0) { + int r = USB_Send(CDC_TX,&c,1); + if (r > 0) { + return r; + } else { + setWriteError(); + return 0; + } + } + setWriteError(); + return 0; +} + +Serial_ Serial; + +#endif +#endif /* if defined(USBCON) */ diff --git a/hardware/sam/cores/sam/HID.cpp b/hardware/sam/cores/sam/HID.cpp new file mode 100644 index 000000000..8ed156666 --- /dev/null +++ b/hardware/sam/cores/sam/HID.cpp @@ -0,0 +1,446 @@ + + +/* Copyright (c) 2011, Peter Barrett +** +** Permission to use, copy, modify, and/or distribute this software for +** any purpose with or without fee is hereby granted, provided that the +** above copyright notice and this permission notice appear in all copies. +** +** THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL +** WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR +** BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES +** OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +** WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +** ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +** SOFTWARE. +*/ + +#include "Platform.h" +#include "USBAPI.h" +#include "USBDesc.h" + +#if defined(USBCON) +#ifdef HID_ENABLED + +//#define RAWHID_ENABLED + +// Singletons for mouse and keyboard + +Mouse_ Mouse; +Keyboard_ Keyboard; + +//================================================================================ +//================================================================================ + +// HID report descriptor + +#define LSB(_x) ((_x) & 0xFF) +#define MSB(_x) ((_x) >> 8) + +#define RAWHID_USAGE_PAGE 0xFFC0 +#define RAWHID_USAGE 0x0C00 +#define RAWHID_TX_SIZE 64 +#define RAWHID_RX_SIZE 64 + +extern const u8 _hidReportDescriptor[] PROGMEM; +const u8 _hidReportDescriptor[] = { + + // Mouse + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) // 54 + 0x09, 0x02, // USAGE (Mouse) + 0xa1, 0x01, // COLLECTION (Application) + 0x09, 0x01, // USAGE (Pointer) + 0xa1, 0x00, // COLLECTION (Physical) + 0x85, 0x01, // REPORT_ID (1) + 0x05, 0x09, // USAGE_PAGE (Button) + 0x19, 0x01, // USAGE_MINIMUM (Button 1) + 0x29, 0x03, // USAGE_MAXIMUM (Button 3) + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0x01, // LOGICAL_MAXIMUM (1) + 0x95, 0x03, // REPORT_COUNT (3) + 0x75, 0x01, // REPORT_SIZE (1) + 0x81, 0x02, // INPUT (Data,Var,Abs) + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x05, // REPORT_SIZE (5) + 0x81, 0x03, // INPUT (Cnst,Var,Abs) + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x30, // USAGE (X) + 0x09, 0x31, // USAGE (Y) + 0x09, 0x38, // USAGE (Wheel) + 0x15, 0x81, // LOGICAL_MINIMUM (-127) + 0x25, 0x7f, // LOGICAL_MAXIMUM (127) + 0x75, 0x08, // REPORT_SIZE (8) + 0x95, 0x03, // REPORT_COUNT (3) + 0x81, 0x06, // INPUT (Data,Var,Rel) + 0xc0, // END_COLLECTION + 0xc0, // END_COLLECTION + + // Keyboard + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) // 47 + 0x09, 0x06, // USAGE (Keyboard) + 0xa1, 0x01, // COLLECTION (Application) + 0x85, 0x02, // REPORT_ID (2) + 0x05, 0x07, // USAGE_PAGE (Keyboard) + + 0x19, 0xe0, // USAGE_MINIMUM (Keyboard LeftControl) + 0x29, 0xe7, // USAGE_MAXIMUM (Keyboard Right GUI) + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0x01, // LOGICAL_MAXIMUM (1) + 0x75, 0x01, // REPORT_SIZE (1) + + 0x95, 0x08, // REPORT_COUNT (8) + 0x81, 0x02, // INPUT (Data,Var,Abs) + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x08, // REPORT_SIZE (8) + 0x81, 0x03, // INPUT (Cnst,Var,Abs) + + 0x95, 0x06, // REPORT_COUNT (6) + 0x75, 0x08, // REPORT_SIZE (8) + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0x65, // LOGICAL_MAXIMUM (101) + 0x05, 0x07, // USAGE_PAGE (Keyboard) + + 0x19, 0x00, // USAGE_MINIMUM (Reserved (no event indicated)) + 0x29, 0x65, // USAGE_MAXIMUM (Keyboard Application) + 0x81, 0x00, // INPUT (Data,Ary,Abs) + 0xc0, // END_COLLECTION + +#if RAWHID_ENABLED + // RAW HID + 0x06, LSB(RAWHID_USAGE_PAGE), MSB(RAWHID_USAGE_PAGE), // 30 + 0x0A, LSB(RAWHID_USAGE), MSB(RAWHID_USAGE), + + 0xA1, 0x01, // Collection 0x01 + 0x85, 0x03, // REPORT_ID (3) + 0x75, 0x08, // report size = 8 bits + 0x15, 0x00, // logical minimum = 0 + 0x26, 0xFF, 0x00, // logical maximum = 255 + + 0x95, 64, // report count TX + 0x09, 0x01, // usage + 0x81, 0x02, // Input (array) + + 0x95, 64, // report count RX + 0x09, 0x02, // usage + 0x91, 0x02, // Output (array) + 0xC0 // end collection +#endif +}; + +extern const HIDDescriptor _hidInterface PROGMEM; +const HIDDescriptor _hidInterface = +{ + D_INTERFACE(HID_INTERFACE,1,3,0,0), + D_HIDREPORT(sizeof(_hidReportDescriptor)), + D_ENDPOINT(USB_ENDPOINT_IN (HID_ENDPOINT_INT),USB_ENDPOINT_TYPE_INTERRUPT,0x40,0x01) +}; + +//================================================================================ +//================================================================================ +// Driver + +u8 _hid_protocol = 1; +u8 _hid_idle = 1; + +#define WEAK __attribute__ ((weak)) +#define WEAK + +int WEAK HID_GetInterface(u8* interfaceNum) +{ + interfaceNum[0] += 1; // uses 1 + return USB_SendControl(TRANSFER_PGM,&_hidInterface,sizeof(_hidInterface)); +} + +int WEAK HID_GetDescriptor(int i) +{ + return USB_SendControl(TRANSFER_PGM,_hidReportDescriptor,sizeof(_hidReportDescriptor)); +} + +void WEAK HID_SendReport(u8 id, const void* data, int len) +{ + USB_Send(HID_TX, &id, 1); + USB_Send(HID_TX | TRANSFER_RELEASE,data,len); +} + +bool WEAK HID_Setup(Setup& setup) +{ + u8 r = setup.bRequest; + u8 requestType = setup.bmRequestType; + if (REQUEST_DEVICETOHOST_CLASS_INTERFACE == requestType) + { + if (HID_GET_REPORT == r) + { + //HID_GetReport(); + return true; + } + if (HID_GET_PROTOCOL == r) + { + //Send8(_hid_protocol); // TODO + return true; + } + } + + if (REQUEST_HOSTTODEVICE_CLASS_INTERFACE == requestType) + { + if (HID_SET_PROTOCOL == r) + { + _hid_protocol = setup.wValueL; + return true; + } + + if (HID_SET_IDLE == r) + { + _hid_idle = setup.wValueL; + return true; + } + } + return false; +} + +//================================================================================ +//================================================================================ +// Mouse + +Mouse_::Mouse_() : _buttons(0) +{ +} + +void Mouse_::click(uint8_t b) +{ + _buttons = b; + move(0,0,0); + _buttons = 0; + move(0,0,0); +} + +void Mouse_::move(signed char x, signed char y, signed char wheel) +{ + u8 m[4]; + m[0] = _buttons; + m[1] = x; + m[2] = y; + m[3] = wheel; + HID_SendReport(1,m,4); +} + +void Mouse_::buttons(uint8_t b) +{ + if (b != _buttons) + { + _buttons = b; + move(0,0,0); + } +} + +void Mouse_::press(uint8_t b) +{ + buttons(_buttons | b); +} + +void Mouse_::release(uint8_t b) +{ + buttons(_buttons & ~b); +} + +bool Mouse_::isPressed(uint8_t b) +{ + if (b & _buttons > 0) + return true; + return false; +} + +//================================================================================ +//================================================================================ +// Keyboard + +Keyboard_::Keyboard_() : _keyMap(0) +{ +} + +void Keyboard_::sendReport(KeyReport* keys) +{ + HID_SendReport(2,keys,sizeof(KeyReport)); +} + +void Keyboard_::setKeyMap(KeyMap* keyMap) +{ + _keyMap = keyMap; +} + +extern +const uint8_t _asciimap[128] PROGMEM; + +#define SHIFT 0x80 +const uint8_t _asciimap[128] = +{ + 0x00, // NUL + 0x00, // SOH + 0x00, // STX + 0x00, // ETX + 0x00, // EOT + 0x00, // ENQ + 0x00, // ACK + 0x00, // BEL + 0x2a, // BS Backspace + 0x2b, // TAB Tab + 0x28, // LF Enter + 0x00, // VT + 0x00, // FF + 0x00, // CR + 0x00, // SO + 0x00, // SI + 0x00, // DEL + 0x00, // DC1 + 0x00, // DC2 + 0x00, // DC3 + 0x00, // DC4 + 0x00, // NAK + 0x00, // SYN + 0x00, // ETB + 0x00, // CAN + 0x00, // EM + 0x00, // SUB + 0x00, // ESC + 0x00, // FS + 0x00, // GS + 0x00, // RS + 0x00, // US + + 0x2c, // ' ' + 0x1e|SHIFT, // ! + 0x34|SHIFT, // " + 0x20|SHIFT, // # + 0x21|SHIFT, // $ + 0x22|SHIFT, // % + 0x24|SHIFT, // & + 0x34, // ' + 0x26|SHIFT, // ( + 0x27|SHIFT, // ) + 0x25|SHIFT, // * + 0x2e|SHIFT, // + + 0x36, // , + 0x2d, // - + 0x37, // . + 0x38, // / + 0x27, // 0 + 0x1e, // 1 + 0x1f, // 2 + 0x20, // 3 + 0x21, // 4 + 0x22, // 5 + 0x23, // 6 + 0x24, // 7 + 0x25, // 8 + 0x26, // 9 + 0x33|SHIFT, // : + 0x33, // ; + 0x36|SHIFT, // < + 0x2e, // = + 0x37|SHIFT, // > + 0x38|SHIFT, // ? + 0x1f|SHIFT, // @ + 0x04|SHIFT, // A + 0x05|SHIFT, // B + 0x06|SHIFT, // C + 0x07|SHIFT, // D + 0x08|SHIFT, // E + 0x09|SHIFT, // F + 0x0a|SHIFT, // G + 0x0b|SHIFT, // H + 0x0c|SHIFT, // I + 0x0d|SHIFT, // J + 0x0e|SHIFT, // K + 0x0f|SHIFT, // L + 0x10|SHIFT, // M + 0x11|SHIFT, // N + 0x12|SHIFT, // O + 0x13|SHIFT, // P + 0x14|SHIFT, // Q + 0x15|SHIFT, // R + 0x16|SHIFT, // S + 0x17|SHIFT, // T + 0x18|SHIFT, // U + 0x19|SHIFT, // V + 0x1a|SHIFT, // W + 0x1b|SHIFT, // X + 0x1c|SHIFT, // Y + 0x1d|SHIFT, // Z + 0x2f, // [ + 0x31, // bslash + 0x30, // ] + 0x23|SHIFT, // ^ + 0x2d|SHIFT, // _ + 0x35, // ` + 0x04, // a + 0x05, // b + 0x06, // c + 0x07, // d + 0x08, // e + 0x09, // f + 0x0a, // g + 0x0b, // h + 0x0c, // i + 0x0d, // j + 0x0e, // k + 0x0f, // l + 0x10, // m + 0x11, // n + 0x12, // o + 0x13, // p + 0x14, // q + 0x15, // r + 0x16, // s + 0x17, // t + 0x18, // u + 0x19, // v + 0x1a, // w + 0x1b, // x + 0x1c, // y + 0x1d, // z + 0x2f|SHIFT, // + 0x31|SHIFT, // | + 0x30|SHIFT, // } + 0x35|SHIFT, // ~ + 0 // DEL +}; + +uint8_t USBPutChar(uint8_t c); +size_t Keyboard_::write(uint8_t c) +{ + // Keydown + { + KeyReport keys = {0}; + if (_keyMap) + _keyMap->charToKey(c,&keys); + else + { + if (c >= 128) { + setWriteError(); + return 0; + } + c = pgm_read_byte(_asciimap + c); + if (!c) { + setWriteError(); + return 0; + } + if (c & 0x80) + { + keys.modifiers |= KEY_MODIFIER_LEFT_SHIFT; + c &= 0x7F; + } + keys.keys[0] = c; + } + sendReport(&keys); + } + // Keyup + { + KeyReport keys = {0}; + sendReport(&keys); + } + return 1; +} + +#endif + +#endif /* if defined(USBCON) */ \ No newline at end of file diff --git a/hardware/sam/cores/sam/HOWTO - compiling a project.txt b/hardware/sam/cores/sam/HOWTO - compiling a project.txt new file mode 100644 index 000000000..2f60ef42b --- /dev/null +++ b/hardware/sam/cores/sam/HOWTO - compiling a project.txt @@ -0,0 +1,55 @@ + +1- Path to GCC ARM toolchain + +Set into environment variables the ARM_GCC_TOOLCHAIN variable: +ex: +ARM_GCC_TOOLCHAIN=C:\CodeSourcery_2011.03-42\bin + +2- Compile libsam (at91sam peripheral drivers) + +Go to hardware/sam/system/libsam/build_gcc + +run the command: 'cs-make' + +This will compile the libsam library and deliver to main Arduino folder the files: + +hardware/sam/cores/sam/libsam_sam3s4c_gcc_dbg.a +hardware/sam/cores/sam/libsam_sam3s4c_gcc_dbg.a.txt (result of nm) + +3- Compile libarduino (Arduino API) + +Go to hardware/sam/cores/sam/build_gcc + +run the command: 'cs-make' + +This will compile the libarduino library and deliver to main Arduino folder the files: + +hardware/sam/cores/sam/libarduino_sam3s_ek_gcc_dbg.a +hardware/sam/cores/sam/libarduino_sam3s_ek_gcc_dbg.a.txt (result of nm) + +4- Compile libvariant (variant specific library, use Arduino API and libsam) + +Go to hardware/sam/variants/sam3s-ek/build_gcc + +run the command: 'cs-make' + +This will compile the libvariant library and deliver to main Arduino folder the files: + +hardware/sam/cores/sam/libvariant_sam3s_ek_gcc_dbg.a +hardware/sam/cores/sam/libvariant_sam3s_ek_gcc_dbg.a.txt (result of nm) + +5- Compile test application + +Go to hardware/sam/cores/sam/validation/build_gcc + +run the command: 'cs-make' + +This will compile the test application and deliver the binary into: + +hardware/sam/cores/sam/validation/debug_sam3s_ek/test_gcc_dbg.elf +hardware/sam/cores/sam/validation/debug_sam3s_ek/test_gcc_dbg.bin +hardware/sam/cores/sam/validation/debug_sam3s_ek/test_gcc_dbg.map (mapping matching linker script) +hardware/sam/cores/sam/validation/debug_sam3s_ek/test_gcc_dbg.elf.txt (result of nm) + + + diff --git a/hardware/sam/cores/sam/HardwareSerial.h b/hardware/sam/cores/sam/HardwareSerial.h new file mode 100644 index 000000000..b76f2efbd --- /dev/null +++ b/hardware/sam/cores/sam/HardwareSerial.h @@ -0,0 +1,46 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef HardwareSerial_h +#define HardwareSerial_h + +#include +#include "Stream.h" +#include "RingBuffer.h" + +class HardwareSerial : public Stream +{ + protected: + RingBuffer *_rx_buffer ; + RingBuffer *_tx_buffer ; + + public: + virtual void begin( const uint32_t dwBaudRate ) =0 ; + virtual void end( void ) =0 ; + virtual int available( void ) =0 ; + virtual int peek( void ) =0 ; + virtual int read( void ) =0 ; + virtual void flush( void ) =0 ; + virtual void write( const uint8_t c ) =0 ; + +// virtual void write( const char *str ) ; +// virtual void write( const uint8_t *buffer, size_t size ) ; + using Print::write ; // pull in write(str) and write(buf, size) from Print +} ; + +#endif // HardwareSerial_h diff --git a/hardware/sam/cores/sam/Platform.h b/hardware/sam/cores/sam/Platform.h new file mode 100644 index 000000000..e334dcad1 --- /dev/null +++ b/hardware/sam/cores/sam/Platform.h @@ -0,0 +1,19 @@ + +#ifndef __PLATFORM_H__ +#define __PLATFORM_H__ + +#include + +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned long u32; + +#include "Arduino.h" + +#if defined(USBCON) + #include "USBDesc.h" + #include "USBCore.h" + #include "USBAPI.h" +#endif /* if defined(USBCON) */ + +#endif diff --git a/hardware/sam/cores/sam/Print.cpp b/hardware/sam/cores/sam/Print.cpp new file mode 100644 index 000000000..ff9604cbb --- /dev/null +++ b/hardware/sam/cores/sam/Print.cpp @@ -0,0 +1,219 @@ +/* + Print.cpp - Base class that provides print() and println() + Copyright (c) 2008 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 23 November 2006 by David A. Mellis + */ + +#include +#include +#include +#include +#include "Arduino.h" + +#include "Print.h" + +// Public Methods ////////////////////////////////////////////////////////////// + +/* default implementation: may be overridden */ +void Print::write(const char *str) +{ + while (*str) + write(*str++); +} + +/* default implementation: may be overridden */ +void Print::write(const uint8_t *buffer, size_t size) +{ + while (size--) + write(*buffer++); +} + +void Print::print( const String &s ) +{ + for ( int i = 0 ; i < (int)s.length() ; i++ ) + { + write( s[i] ) ; + } +} + +void Print::print(const char str[]) +{ + write(str); +} + +void Print::print(char c) +{ + write(c); +} + +void Print::print(unsigned char b, int base) +{ + print((unsigned long) b, base); +} + +void Print::print(int n, int base) +{ + print((long) n, base); +} + +void Print::print(unsigned int n, int base) +{ + print((unsigned long) n, base); +} + +void Print::print(long n, int base) +{ + if (base == 0) { + write(n); + } else if (base == 10) { + if (n < 0) { + print('-'); + n = -n; + } + printNumber(n, 10); + } else { + printNumber(n, base); + } +} + +void Print::print(unsigned long n, int base) +{ + if (base == 0) write(n); + else printNumber(n, base); +} + +void Print::print(double n, int digits) +{ + printFloat(n, digits); +} + +void Print::println(void) +{ + print('\r'); + print('\n'); +} + +void Print::println(const String &s) +{ + print(s); + println(); +} + +void Print::println(const char c[]) +{ + print(c); + println(); +} + +void Print::println(char c) +{ + print(c); + println(); +} + +void Print::println(unsigned char b, int base) +{ + print(b, base); + println(); +} + +void Print::println(int n, int base) +{ + print(n, base); + println(); +} + +void Print::println(unsigned int n, int base) +{ + print(n, base); + println(); +} + +void Print::println(long n, int base) +{ + print(n, base); + println(); +} + +void Print::println(unsigned long n, int base) +{ + print(n, base); + println(); +} + +void Print::println(double n, int digits) +{ + print(n, digits); + println(); +} + +// Private Methods ///////////////////////////////////////////////////////////// + +void Print::printNumber(unsigned long n, uint8_t base) { + char buf[8 * sizeof(long) + 1]; // Assumes 8-bit chars plus zero byte. + char *str = &buf[sizeof(buf) - 1]; + + *str = '\0'; + + // prevent crash if called with base == 1 + if (base < 2) base = 10; + + do { + unsigned long m = n; + n /= base; + char c = m - base * n; + *--str = c < 10 ? c + '0' : c + 'A' - 10; + } while(n); + + write(str); +} + +void Print::printFloat(double number, uint8_t digits) +{ + // Handle negative numbers + if (number < 0.0) + { + print('-'); + number = -number; + } + + // Round correctly so that print(1.999, 2) prints as "2.00" + double rounding = 0.5; + for (uint8_t i=0; i 0) + print("."); + + // Extract digits from the remainder one at a time + while (digits-- > 0) + { + remainder *= 10.0; + int toPrint = int(remainder); + print(toPrint); + remainder -= toPrint; + } +} diff --git a/hardware/sam/cores/sam/Print.h b/hardware/sam/cores/sam/Print.h new file mode 100644 index 000000000..7885617ed --- /dev/null +++ b/hardware/sam/cores/sam/Print.h @@ -0,0 +1,65 @@ +/* + Print.h - Base class that provides print() and println() + Copyright (c) 2008 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef Print_h +#define Print_h + +#include +#include // for size_t + +#include "WString.h" + +#define DEC 10 +#define HEX 16 +#define OCT 8 +#define BIN 2 + +class Print +{ + private: + void printNumber(unsigned long, uint8_t); + void printFloat(double, uint8_t); + public: + virtual void write(uint8_t) = 0; + virtual void write(const char *str); + virtual void write(const uint8_t *buffer, size_t size); + + void print(const String &); + void print(const char[]); + void print(char); + void print(unsigned char, int = DEC); + void print(int, int = DEC); + void print(unsigned int, int = DEC); + void print(long, int = DEC); + void print(unsigned long, int = DEC); + void print(double, int = 2); + + void println(const String &s); + void println(const char[]); + void println(char); + void println(unsigned char, int = DEC); + void println(int, int = DEC); + void println(unsigned int, int = DEC); + void println(long, int = DEC); + void println(unsigned long, int = DEC); + void println(double, int = 2); + void println(void); +}; + +#endif diff --git a/hardware/sam/cores/sam/RingBuffer.cpp b/hardware/sam/cores/sam/RingBuffer.cpp new file mode 100644 index 000000000..f0b3ed1df --- /dev/null +++ b/hardware/sam/cores/sam/RingBuffer.cpp @@ -0,0 +1,43 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "RingBuffer.h" +#include + +RingBuffer::RingBuffer( void ) +{ + memset( _aucBuffer, 0, SERIAL_BUFFER_SIZE ) ; + _iHead=0 ; + _iTail=0 ; +} + +void RingBuffer::store_char( uint8_t c ) +{ + int i = (uint32_t)(_iHead + 1) % SERIAL_BUFFER_SIZE ; + + // if we should be storing the received character into the location + // just before the tail (meaning that the head would advance to the + // current location of the tail), we're about to overflow the buffer + // and so we don't write the character or advance the head. + if ( i != _iTail ) + { + _aucBuffer[_iHead] = c ; + _iHead = i ; + } +} + diff --git a/hardware/sam/cores/sam/RingBuffer.h b/hardware/sam/cores/sam/RingBuffer.h new file mode 100644 index 000000000..28309df45 --- /dev/null +++ b/hardware/sam/cores/sam/RingBuffer.h @@ -0,0 +1,42 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _RING_BUFFER_ +#define _RING_BUFFER_ + +#include + +// Define constants and variables for buffering incoming serial data. We're +// using a ring buffer (I think), in which head is the index of the location +// to which to write the next incoming character and tail is the index of the +// location from which to read. +#define SERIAL_BUFFER_SIZE 64 + +class RingBuffer +{ + public: + uint8_t _aucBuffer[SERIAL_BUFFER_SIZE] ; + int _iHead ; + int _iTail ; + + public: + RingBuffer( void ) ; + void store_char( uint8_t c ) ; +} ; + +#endif /* _RING_BUFFER_ */ diff --git a/hardware/sam/cores/sam/Stream.h b/hardware/sam/cores/sam/Stream.h new file mode 100644 index 000000000..aaa189f4d --- /dev/null +++ b/hardware/sam/cores/sam/Stream.h @@ -0,0 +1,35 @@ +/* + Stream.h - base class for character-based streams. + Copyright (c) 2010 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef Stream_h +#define Stream_h + +#include +#include "Print.h" + +class Stream : public Print +{ + public: + virtual int available() = 0; + virtual int read() = 0; + virtual int peek() = 0; + virtual void flush() = 0; +}; + +#endif diff --git a/hardware/sam/cores/sam/Tone.cpp.disabled b/hardware/sam/cores/sam/Tone.cpp.disabled new file mode 100644 index 000000000..20eed3f48 --- /dev/null +++ b/hardware/sam/cores/sam/Tone.cpp.disabled @@ -0,0 +1,601 @@ +/* Tone.cpp + + A Tone Generator Library + + Written by Brett Hagman + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +Version Modified By Date Comments +------- ----------- -------- -------- +0001 B Hagman 09/08/02 Initial coding +0002 B Hagman 09/08/18 Multiple pins +0003 B Hagman 09/08/18 Moved initialization from constructor to begin() +0004 B Hagman 09/09/26 Fixed problems with ATmega8 +0005 B Hagman 09/11/23 Scanned prescalars for best fit on 8 bit timers + 09/11/25 Changed pin toggle method to XOR + 09/11/25 Fixed timer0 from being excluded +0006 D Mellis 09/12/29 Replaced objects with functions +0007 M Sproul 10/08/29 Changed #ifdefs from cpu to register +*************************************************/ + +#include +#include +#include "Arduino.h" +#include "pins_arduino.h" + +#if defined(__AVR_ATmega8__) || defined(__AVR_ATmega128__) +#define TCCR2A TCCR2 +#define TCCR2B TCCR2 +#define COM2A1 COM21 +#define COM2A0 COM20 +#define OCR2A OCR2 +#define TIMSK2 TIMSK +#define OCIE2A OCIE2 +#define TIMER2_COMPA_vect TIMER2_COMP_vect +#define TIMSK1 TIMSK +#endif + +// timerx_toggle_count: +// > 0 - duration specified +// = 0 - stopped +// < 0 - infinitely (until stop() method called, or new play() called) + +#if !defined(__AVR_ATmega8__) +volatile long timer0_toggle_count; +volatile uint8_t *timer0_pin_port; +volatile uint8_t timer0_pin_mask; +#endif + +volatile long timer1_toggle_count; +volatile uint8_t *timer1_pin_port; +volatile uint8_t timer1_pin_mask; +volatile long timer2_toggle_count; +volatile uint8_t *timer2_pin_port; +volatile uint8_t timer2_pin_mask; + +#if defined(TIMSK3) +volatile long timer3_toggle_count; +volatile uint8_t *timer3_pin_port; +volatile uint8_t timer3_pin_mask; +#endif + +#if defined(TIMSK4) +volatile long timer4_toggle_count; +volatile uint8_t *timer4_pin_port; +volatile uint8_t timer4_pin_mask; +#endif + +#if defined(TIMSK5) +volatile long timer5_toggle_count; +volatile uint8_t *timer5_pin_port; +volatile uint8_t timer5_pin_mask; +#endif + + +// MLS: This does not make sense, the 3 options are the same +#if defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__) + +#define AVAILABLE_TONE_PINS 1 + +const uint8_t PROGMEM tone_pin_to_timer_PGM[] = { 2 /*, 3, 4, 5, 1, 0 */ }; +static uint8_t tone_pins[AVAILABLE_TONE_PINS] = { 255 /*, 255, 255, 255, 255, 255 */ }; + +#elif defined(__AVR_ATmega8__) + +#define AVAILABLE_TONE_PINS 1 + +const uint8_t PROGMEM tone_pin_to_timer_PGM[] = { 2 /*, 1 */ }; +static uint8_t tone_pins[AVAILABLE_TONE_PINS] = { 255 /*, 255 */ }; + +#else + +#define AVAILABLE_TONE_PINS 1 + +// Leave timer 0 to last. +const uint8_t PROGMEM tone_pin_to_timer_PGM[] = { 2 /*, 1, 0 */ }; +static uint8_t tone_pins[AVAILABLE_TONE_PINS] = { 255 /*, 255, 255 */ }; + +#endif + + + +static int8_t toneBegin(uint8_t _pin) +{ + int8_t _timer = -1; + + // if we're already using the pin, the timer should be configured. + for (int i = 0; i < AVAILABLE_TONE_PINS; i++) { + if (tone_pins[i] == _pin) { + return pgm_read_byte(tone_pin_to_timer_PGM + i); + } + } + + // search for an unused timer. + for (int i = 0; i < AVAILABLE_TONE_PINS; i++) { + if (tone_pins[i] == 255) { + tone_pins[i] = _pin; + _timer = pgm_read_byte(tone_pin_to_timer_PGM + i); + break; + } + } + + if (_timer != -1) + { + // Set timer specific stuff + // All timers in CTC mode + // 8 bit timers will require changing prescalar values, + // whereas 16 bit timers are set to either ck/1 or ck/64 prescalar + switch (_timer) + { + #if defined(TCCR0A) && defined(TCCR0B) + case 0: + // 8 bit timer + TCCR0A = 0; + TCCR0B = 0; + bitWrite(TCCR0A, WGM01, 1); + bitWrite(TCCR0B, CS00, 1); + timer0_pin_port = portOutputRegister(digitalPinToPort(_pin)); + timer0_pin_mask = digitalPinToBitMask(_pin); + break; + #endif + + #if defined(TCCR1A) && defined(TCCR1B) && defined(WGM12) + case 1: + // 16 bit timer + TCCR1A = 0; + TCCR1B = 0; + bitWrite(TCCR1B, WGM12, 1); + bitWrite(TCCR1B, CS10, 1); + timer1_pin_port = portOutputRegister(digitalPinToPort(_pin)); + timer1_pin_mask = digitalPinToBitMask(_pin); + break; + #endif + + #if defined(TCCR2A) && defined(TCCR2B) + case 2: + // 8 bit timer + TCCR2A = 0; + TCCR2B = 0; + bitWrite(TCCR2A, WGM21, 1); + bitWrite(TCCR2B, CS20, 1); + timer2_pin_port = portOutputRegister(digitalPinToPort(_pin)); + timer2_pin_mask = digitalPinToBitMask(_pin); + break; + #endif + + #if defined(TCCR3A) && defined(TCCR3B) && defined(TIMSK3) + case 3: + // 16 bit timer + TCCR3A = 0; + TCCR3B = 0; + bitWrite(TCCR3B, WGM32, 1); + bitWrite(TCCR3B, CS30, 1); + timer3_pin_port = portOutputRegister(digitalPinToPort(_pin)); + timer3_pin_mask = digitalPinToBitMask(_pin); + break; + #endif + + #if defined(TCCR4A) && defined(TCCR4B) && defined(TIMSK4) + case 4: + // 16 bit timer + TCCR4A = 0; + TCCR4B = 0; + #if defined(WGM42) + bitWrite(TCCR4B, WGM42, 1); + #elif defined(CS43) + #warning this may not be correct + // atmega32u4 + bitWrite(TCCR4B, CS43, 1); + #endif + bitWrite(TCCR4B, CS40, 1); + timer4_pin_port = portOutputRegister(digitalPinToPort(_pin)); + timer4_pin_mask = digitalPinToBitMask(_pin); + break; + #endif + + #if defined(TCCR5A) && defined(TCCR5B) && defined(TIMSK5) + case 5: + // 16 bit timer + TCCR5A = 0; + TCCR5B = 0; + bitWrite(TCCR5B, WGM52, 1); + bitWrite(TCCR5B, CS50, 1); + timer5_pin_port = portOutputRegister(digitalPinToPort(_pin)); + timer5_pin_mask = digitalPinToBitMask(_pin); + break; + #endif + } + } + + return _timer; +} + + + +// frequency (in hertz) and duration (in milliseconds). + +void tone(uint8_t _pin, unsigned int frequency, unsigned long duration) +{ + uint8_t prescalarbits = 0b001; + long toggle_count = 0; + uint32_t ocr = 0; + int8_t _timer; + + _timer = toneBegin(_pin); + + if (_timer >= 0) + { + // Set the pinMode as OUTPUT + pinMode(_pin, OUTPUT); + + // if we are using an 8 bit timer, scan through prescalars to find the best fit + if (_timer == 0 || _timer == 2) + { + ocr = F_CPU / frequency / 2 - 1; + prescalarbits = 0b001; // ck/1: same for both timers + if (ocr > 255) + { + ocr = F_CPU / frequency / 2 / 8 - 1; + prescalarbits = 0b010; // ck/8: same for both timers + + if (_timer == 2 && ocr > 255) + { + ocr = F_CPU / frequency / 2 / 32 - 1; + prescalarbits = 0b011; + } + + if (ocr > 255) + { + ocr = F_CPU / frequency / 2 / 64 - 1; + prescalarbits = _timer == 0 ? 0b011 : 0b100; + + if (_timer == 2 && ocr > 255) + { + ocr = F_CPU / frequency / 2 / 128 - 1; + prescalarbits = 0b101; + } + + if (ocr > 255) + { + ocr = F_CPU / frequency / 2 / 256 - 1; + prescalarbits = _timer == 0 ? 0b100 : 0b110; + if (ocr > 255) + { + // can't do any better than /1024 + ocr = F_CPU / frequency / 2 / 1024 - 1; + prescalarbits = _timer == 0 ? 0b101 : 0b111; + } + } + } + } + +#if defined(TCCR0B) + if (_timer == 0) + { + TCCR0B = prescalarbits; + } + else +#endif +#if defined(TCCR2B) + { + TCCR2B = prescalarbits; + } +#else + { + // dummy place holder to make the above ifdefs work + } +#endif + } + else + { + // two choices for the 16 bit timers: ck/1 or ck/64 + ocr = F_CPU / frequency / 2 - 1; + + prescalarbits = 0b001; + if (ocr > 0xffff) + { + ocr = F_CPU / frequency / 2 / 64 - 1; + prescalarbits = 0b011; + } + + if (_timer == 1) + { +#if defined(TCCR1B) + TCCR1B = (TCCR1B & 0b11111000) | prescalarbits; +#endif + } +#if defined(TCCR3B) + else if (_timer == 3) + TCCR3B = (TCCR3B & 0b11111000) | prescalarbits; +#endif +#if defined(TCCR4B) + else if (_timer == 4) + TCCR4B = (TCCR4B & 0b11111000) | prescalarbits; +#endif +#if defined(TCCR5B) + else if (_timer == 5) + TCCR5B = (TCCR5B & 0b11111000) | prescalarbits; +#endif + + } + + + // Calculate the toggle count + if (duration > 0) + { + toggle_count = 2 * frequency * duration / 1000; + } + else + { + toggle_count = -1; + } + + // Set the OCR for the given timer, + // set the toggle count, + // then turn on the interrupts + switch (_timer) + { + +#if defined(OCR0A) && defined(TIMSK0) && defined(OCIE0A) + case 0: + OCR0A = ocr; + timer0_toggle_count = toggle_count; + bitWrite(TIMSK0, OCIE0A, 1); + break; +#endif + + case 1: +#if defined(OCR1A) && defined(TIMSK1) && defined(OCIE1A) + OCR1A = ocr; + timer1_toggle_count = toggle_count; + bitWrite(TIMSK1, OCIE1A, 1); +#elif defined(OCR1A) && defined(TIMSK) && defined(OCIE1A) + // this combination is for at least the ATmega32 + OCR1A = ocr; + timer1_toggle_count = toggle_count; + bitWrite(TIMSK, OCIE1A, 1); +#endif + break; + +#if defined(OCR2A) && defined(TIMSK2) && defined(OCIE2A) + case 2: + OCR2A = ocr; + timer2_toggle_count = toggle_count; + bitWrite(TIMSK2, OCIE2A, 1); + break; +#endif + +#if defined(TIMSK3) + case 3: + OCR3A = ocr; + timer3_toggle_count = toggle_count; + bitWrite(TIMSK3, OCIE3A, 1); + break; +#endif + +#if defined(TIMSK4) + case 4: + OCR4A = ocr; + timer4_toggle_count = toggle_count; + bitWrite(TIMSK4, OCIE4A, 1); + break; +#endif + +#if defined(OCR5A) && defined(TIMSK5) && defined(OCIE5A) + case 5: + OCR5A = ocr; + timer5_toggle_count = toggle_count; + bitWrite(TIMSK5, OCIE5A, 1); + break; +#endif + + } + } +} + + +// XXX: this function only works properly for timer 2 (the only one we use +// currently). for the others, it should end the tone, but won't restore +// proper PWM functionality for the timer. +void disableTimer(uint8_t _timer) +{ + switch (_timer) + { + case 0: + #if defined(TIMSK0) + TIMSK0 = 0; + #elif defined(TIMSK) + TIMSK = 0; // atmega32 + #endif + break; + +#if defined(TIMSK1) && defined(OCIE1A) + case 1: + bitWrite(TIMSK1, OCIE1A, 0); + break; +#endif + + case 2: + #if defined(TIMSK2) && defined(OCIE2A) + bitWrite(TIMSK2, OCIE2A, 0); // disable interrupt + #endif + #if defined(TCCR2A) && defined(WGM20) + TCCR2A = (1 << WGM20); + #endif + #if defined(TCCR2B) && defined(CS22) + TCCR2B = (TCCR2B & 0b11111000) | (1 << CS22); + #endif + #if defined(OCR2A) + OCR2A = 0; + #endif + break; + +#if defined(TIMSK3) + case 3: + TIMSK3 = 0; + break; +#endif + +#if defined(TIMSK4) + case 4: + TIMSK4 = 0; + break; +#endif + +#if defined(TIMSK5) + case 5: + TIMSK5 = 0; + break; +#endif + } +} + + +void noTone(uint8_t _pin) +{ + int8_t _timer = -1; + + for (int i = 0; i < AVAILABLE_TONE_PINS; i++) { + if (tone_pins[i] == _pin) { + _timer = pgm_read_byte(tone_pin_to_timer_PGM + i); + tone_pins[i] = 255; + } + } + + disableTimer(_timer); + + digitalWrite(_pin, 0); +} + +#if 0 +#if !defined(__AVR_ATmega8__) +ISR(TIMER0_COMPA_vect) +{ + if (timer0_toggle_count != 0) + { + // toggle the pin + *timer0_pin_port ^= timer0_pin_mask; + + if (timer0_toggle_count > 0) + timer0_toggle_count--; + } + else + { + disableTimer(0); + *timer0_pin_port &= ~(timer0_pin_mask); // keep pin low after stop + } +} +#endif + + +ISR(TIMER1_COMPA_vect) +{ + if (timer1_toggle_count != 0) + { + // toggle the pin + *timer1_pin_port ^= timer1_pin_mask; + + if (timer1_toggle_count > 0) + timer1_toggle_count--; + } + else + { + disableTimer(1); + *timer1_pin_port &= ~(timer1_pin_mask); // keep pin low after stop + } +} +#endif + + +ISR(TIMER2_COMPA_vect) +{ + + if (timer2_toggle_count != 0) + { + // toggle the pin + *timer2_pin_port ^= timer2_pin_mask; + + if (timer2_toggle_count > 0) + timer2_toggle_count--; + } + else + { + // need to call noTone() so that the tone_pins[] entry is reset, so the + // timer gets initialized next time we call tone(). + // XXX: this assumes timer 2 is always the first one used. + noTone(tone_pins[0]); +// disableTimer(2); +// *timer2_pin_port &= ~(timer2_pin_mask); // keep pin low after stop + } +} + + + +//#if defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__) +#if 0 + +ISR(TIMER3_COMPA_vect) +{ + if (timer3_toggle_count != 0) + { + // toggle the pin + *timer3_pin_port ^= timer3_pin_mask; + + if (timer3_toggle_count > 0) + timer3_toggle_count--; + } + else + { + disableTimer(3); + *timer3_pin_port &= ~(timer3_pin_mask); // keep pin low after stop + } +} + +ISR(TIMER4_COMPA_vect) +{ + if (timer4_toggle_count != 0) + { + // toggle the pin + *timer4_pin_port ^= timer4_pin_mask; + + if (timer4_toggle_count > 0) + timer4_toggle_count--; + } + else + { + disableTimer(4); + *timer4_pin_port &= ~(timer4_pin_mask); // keep pin low after stop + } +} + +ISR(TIMER5_COMPA_vect) +{ + if (timer5_toggle_count != 0) + { + // toggle the pin + *timer5_pin_port ^= timer5_pin_mask; + + if (timer5_toggle_count > 0) + timer5_toggle_count--; + } + else + { + disableTimer(5); + *timer5_pin_port &= ~(timer5_pin_mask); // keep pin low after stop + } +} + +#endif diff --git a/hardware/sam/cores/sam/Tone.h b/hardware/sam/cores/sam/Tone.h new file mode 100644 index 000000000..5789b082d --- /dev/null +++ b/hardware/sam/cores/sam/Tone.h @@ -0,0 +1,23 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _WIRING_TONE_ +#define _WIRING_TONE_ + + +#endif /* _WIRING_TONE_ */ diff --git a/hardware/sam/cores/sam/UARTClass.cpp b/hardware/sam/cores/sam/UARTClass.cpp new file mode 100644 index 000000000..2ef23a7e1 --- /dev/null +++ b/hardware/sam/cores/sam/UARTClass.cpp @@ -0,0 +1,136 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include +#include +#include +#include "UARTClass.h" + +// Constructors //////////////////////////////////////////////////////////////// + +UARTClass::UARTClass( Uart* pUart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer ) +{ + _rx_buffer = pRx_buffer ; + + _pUart=pUart ; + _dwIrq=dwIrq ; + _dwId=dwId ; +} + +// Public Methods ////////////////////////////////////////////////////////////// + +void UARTClass::begin( const uint32_t dwBaudRate ) +{ + // Configure PMC + PMC_EnablePeripheral( _dwId ) ; + + // Disable PDC channel + _pUart->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS ; + + // Reset and disable receiver and transmitter + _pUart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | UART_CR_TXDIS ; + + // Configure mode + _pUart->UART_MR = UART_MR_PAR_NO | UART_MR_CHMODE_NORMAL ; + + // Configure baudrate (asynchronous, no oversampling) + _pUart->UART_BRGR = (SystemCoreClock / dwBaudRate) >> 4 ; + + // Configure interrupts + _pUart->UART_IDR = 0xFFFFFFFF; + _pUart->UART_IER = UART_IER_RXRDY | UART_IER_OVRE | UART_IER_FRAME; + + // Enable UART interrupt in NVIC + NVIC_EnableIRQ(_dwIrq); + + // Enable receiver and transmitter + _pUart->UART_CR = UART_CR_RXEN | UART_CR_TXEN ; +} + +void UARTClass::end( void ) +{ + // clear any received data + _rx_buffer->_iHead = _rx_buffer->_iTail ; + + // Disable UART interrupt in NVIC + NVIC_DisableIRQ( _dwIrq ) ; + + // Wait for any outstanding data to be sent + flush(); + + PMC_DisablePeripheral( _dwId ) ; +} + +int UARTClass::available( void ) +{ + return (uint32_t)(SERIAL_BUFFER_SIZE + _rx_buffer->_iHead - _rx_buffer->_iTail) % SERIAL_BUFFER_SIZE ; +} + +int UARTClass::peek( void ) +{ + if ( _rx_buffer->_iHead == _rx_buffer->_iTail ) + return -1 ; + + return _rx_buffer->_aucBuffer[_rx_buffer->_iTail] ; +} + +int UARTClass::read( void ) +{ + // if the head isn't ahead of the tail, we don't have any characters + if ( _rx_buffer->_iHead == _rx_buffer->_iTail ) + return -1 ; + + uint8_t uc = _rx_buffer->_aucBuffer[_rx_buffer->_iTail] ; + _rx_buffer->_iTail = (unsigned int)(_rx_buffer->_iTail + 1) % SERIAL_BUFFER_SIZE ; + return uc ; +} + +void UARTClass::flush( void ) +{ + // Wait for transmission to complete + while ((_pUart->UART_SR & UART_SR_TXRDY) != UART_SR_TXRDY) + ; +} + +void UARTClass::write( const uint8_t uc_data ) +{ + // Check if the transmitter is ready + while ((_pUart->UART_SR & UART_SR_TXRDY) != UART_SR_TXRDY) + ; + + // Send character + _pUart->UART_THR = uc_data; +} + +void UARTClass::IrqHandler( void ) +{ + uint32_t status = _pUart->UART_SR; + + // Did we receive data ? + if ((status & UART_SR_RXRDY) == UART_SR_RXRDY) + _rx_buffer->store_char(_pUart->UART_RHR); + + // Acknowledge errors + if ((status & UART_SR_OVRE) == UART_SR_OVRE || + (status & UART_SR_FRAME) == UART_SR_FRAME) + { + // TODO: error reporting outside ISR + _pUart->UART_CR |= UART_CR_RSTSTA; + } +} + diff --git a/hardware/sam/cores/sam/UARTClass.h b/hardware/sam/cores/sam/UARTClass.h new file mode 100644 index 000000000..0ce9d714c --- /dev/null +++ b/hardware/sam/cores/sam/UARTClass.h @@ -0,0 +1,55 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _UART_CLASS_ +#define _UART_CLASS_ + +#include "Arduino.h" + +class UARTClass : public HardwareSerial +{ + protected: + RingBuffer *_rx_buffer ; + + protected: + Uart* _pUart ; + IRQn_Type _dwIrq ; + uint32_t _dwId ; + + public: + UARTClass( Uart* pUart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer ) ; + + void begin( const uint32_t dwBaudRate ) ; + void end( void ) ; + int available( void ) ; + int peek( void ) ; + int read( void ) ; + void flush( void ) ; + void write( const uint8_t c ) ; + + void IrqHandler( void ) ; + +#if defined __GNUC__ /* GCC CS3 */ + using Print::write ; // pull in write(str) and write(buf, size) from Print +#elif defined __ICCARM__ /* IAR Ewarm 5.41+ */ +// virtual void write( const char *str ) ; +// virtual void write( const uint8_t *buffer, size_t size ) ; +#endif +}; + +#endif // _UART_CLASS_ diff --git a/hardware/sam/cores/sam/USARTClass.cpp b/hardware/sam/cores/sam/USARTClass.cpp new file mode 100644 index 000000000..a1b511a72 --- /dev/null +++ b/hardware/sam/cores/sam/USARTClass.cpp @@ -0,0 +1,137 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include +#include +#include +#include "USARTClass.h" + +// Constructors //////////////////////////////////////////////////////////////// + +USARTClass::USARTClass( Usart* pUsart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer ) +{ + _rx_buffer = pRx_buffer ; + + _pUsart=pUsart ; + _dwIrq=dwIrq ; + _dwId=dwId ; +} + +// Public Methods ////////////////////////////////////////////////////////////// + +void USARTClass::begin( const uint32_t dwBaudRate ) +{ + // Configure PMC + PMC_EnablePeripheral( _dwId ) ; + + // Disable PDC channel + _pUsart->US_PTCR = US_PTCR_RXTDIS | US_PTCR_TXTDIS ; + + // Reset and disable receiver and transmitter + _pUsart->US_CR = US_CR_RSTRX | US_CR_RSTTX | US_CR_RXDIS | US_CR_TXDIS ; + + // Configure mode + _pUsart->US_MR = US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_8_BIT | US_MR_PAR_NO | + US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL; + + // Configure baudrate, asynchronous no oversampling + _pUsart->US_BRGR = (SystemCoreClock / dwBaudRate) / 16 ; + + // Configure interrupts + _pUsart->US_IDR = 0xFFFFFFFF; + _pUsart->US_IER = US_IER_RXRDY | US_IER_OVRE | US_IER_FRAME; + + // Enable UART interrupt in NVIC + NVIC_EnableIRQ( _dwIrq ) ; + + // Enable receiver and transmitter + _pUsart->US_CR = US_CR_RXEN | US_CR_TXEN ; +} + +void USARTClass::end( void ) +{ + // clear any received data + _rx_buffer->_iHead = _rx_buffer->_iTail ; + + // Disable UART interrupt in NVIC + NVIC_DisableIRQ( _dwIrq ) ; + + // Wait for any outstanding data to be sent + flush(); + + PMC_DisablePeripheral( _dwId ) ; +} + +int USARTClass::available( void ) +{ + return (uint32_t)(SERIAL_BUFFER_SIZE + _rx_buffer->_iHead - _rx_buffer->_iTail) % SERIAL_BUFFER_SIZE ; +} + +int USARTClass::peek( void ) +{ + if ( _rx_buffer->_iHead == _rx_buffer->_iTail ) + return -1 ; + + return _rx_buffer->_aucBuffer[_rx_buffer->_iTail] ; +} + +int USARTClass::read( void ) +{ + // if the head isn't ahead of the tail, we don't have any characters + if ( _rx_buffer->_iHead == _rx_buffer->_iTail ) + return -1 ; + + uint8_t uc = _rx_buffer->_aucBuffer[_rx_buffer->_iTail] ; + _rx_buffer->_iTail = (unsigned int)(_rx_buffer->_iTail + 1) % SERIAL_BUFFER_SIZE ; + return uc ; +} + +void USARTClass::flush( void ) +{ + // Wait for transmission to complete + while ((_pUsart->US_CSR & US_CSR_TXRDY) != US_CSR_TXRDY) + ; +} + +void USARTClass::write( const uint8_t uc_data ) +{ + // Check if the transmitter is ready + while ((_pUsart->US_CSR & US_CSR_TXRDY) != US_CSR_TXRDY) + ; + + // Send character + _pUsart->US_THR = uc_data ; +} + +void USARTClass::IrqHandler( void ) +{ + uint32_t status = _pUsart->US_CSR; + + // Did we receive data ? + if ((status & US_CSR_RXRDY) == US_CSR_RXRDY) + _rx_buffer->store_char( _pUsart->US_RHR ) ; + + // Acknowledge errors + if ((status & US_CSR_OVRE) == US_CSR_OVRE || + (status & US_CSR_FRAME) == US_CSR_FRAME) + { + // TODO: error reporting outside ISR + _pUsart->US_CR |= US_CR_RSTSTA; + } +} + diff --git a/hardware/sam/cores/sam/USARTClass.h b/hardware/sam/cores/sam/USARTClass.h new file mode 100644 index 000000000..1b85b27b6 --- /dev/null +++ b/hardware/sam/cores/sam/USARTClass.h @@ -0,0 +1,55 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _USART_CLASS_ +#define _USART_CLASS_ + +#include "Arduino.h" + +class USARTClass : public HardwareSerial +{ + protected: + RingBuffer *_rx_buffer ; + + protected: + Usart* _pUsart ; + IRQn_Type _dwIrq ; + uint32_t _dwId ; + + public: + USARTClass( Usart* pUsart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer ) ; + + void begin( const uint32_t dwBaudRate ) ; + void end( void ) ; + int available( void ) ; + int peek( void ) ; + int read( void ) ; + void flush( void ) ; + void write( const uint8_t c ) ; + + void IrqHandler( void ) ; + +#if defined __GNUC__ /* GCC CS3 */ + using Print::write ; // pull in write(str) and write(buf, size) from Print +#elif defined __ICCARM__ /* IAR Ewarm 5.41+ */ +// virtual void write( const char *str ) ; +// virtual void write( const uint8_t *buffer, size_t size ) ; +#endif +}; + +#endif // _USART_CLASS_ diff --git a/hardware/sam/cores/sam/USBAPI.h b/hardware/sam/cores/sam/USBAPI.h new file mode 100644 index 000000000..fdf4cd4fd --- /dev/null +++ b/hardware/sam/cores/sam/USBAPI.h @@ -0,0 +1,166 @@ + + +#ifndef __USBAPI__ +#define __USBAPI__ + +#if defined(USBCON) + +//================================================================================ +//================================================================================ +// USB + +class USB_ +{ +public: + USB_(); + bool configured(); + + void attach(); + void detach(); // Serial port goes down too... + void poll(); +}; +extern USB_ USB; + +//================================================================================ +//================================================================================ +// Serial over CDC (Serial1 is the physical port) + +class Serial_ : public Stream +{ +public: + void begin(uint16_t baud_count); + void end(void); + + virtual int available(void); + virtual int peek(void); + virtual int read(void); + virtual void flush(void); + virtual void write(uint8_t); +}; +extern Serial_ Serial; + +//================================================================================ +//================================================================================ +// Mouse + +#define MOUSE_LEFT 1 +#define MOUSE_RIGHT 2 +#define MOUSE_MIDDLE 4 +#define MOUSE_ALL (MOUSE_LEFT | MOUSE_RIGHT | MOUSE_MIDDLE) + +class Mouse_ +{ +private: + uint8_t _buttons; + void buttons(uint8_t b); +public: + Mouse_(); + void click(uint8_t b = MOUSE_LEFT); + void move(signed char x, signed char y, signed char wheel = 0); + void press(uint8_t b = MOUSE_LEFT); // press LEFT by default + void release(uint8_t b = MOUSE_LEFT); // release LEFT by default + bool isPressed(uint8_t b = MOUSE_ALL); // check all buttons by default +}; +extern Mouse_ Mouse; + +//================================================================================ +//================================================================================ +// Keyboard + +#define KEY_MODIFIER_LEFT_CTRL 0x01 +#define KEY_MODIFIER_LEFT_SHIFT 0x02 +#define KEY_MODIFIER_LEFT_ALT 0x04 +#define KEY_MODIFIER_LEFT_GUI 0x08 +#define KEY_MODIFIER_RIGHT_CTRL 0x010 +#define KEY_MODIFIER_RIGHT_SHIFT 0x020 +#define KEY_MODIFIER_RIGHT_ALT 0x040 +#define KEY_MODIFIER_RIGHT_GUI 0x080 + +// Low level key report: up to 6 keys and shift, ctrl etc at once +typedef struct +{ + uint8_t modifiers; + uint8_t reserved; + uint8_t keys[6]; +} KeyReport; + +// Map a character into a key report +// Called from Print to map text to keycodes +class KeyMap +{ +public: + virtual void charToKey(int c, KeyReport* keyReport) = 0; +}; + +// +class Keyboard_ : public Print +{ +private: + KeyMap* _keyMap; + void sendReport(KeyReport* keys); + void setKeyMap(KeyMap* keyMap); +public: + Keyboard_(); + virtual void write(uint8_t); +}; +extern Keyboard_ Keyboard; + +//================================================================================ +//================================================================================ +// Low level API + +typedef struct +{ + uint8_t bmRequestType; + uint8_t bRequest; + uint8_t wValueL; + uint8_t wValueH; + uint16_t wIndex; + uint16_t wLength; +} Setup; + +//================================================================================ +//================================================================================ +// HID 'Driver' + +int HID_GetInterface(uint8_t* interfaceNum); +int HID_GetDescriptor(int i); +bool HID_Setup(Setup& setup); +void HID_SendReport(uint8_t id, const void* data, int len); + +//================================================================================ +//================================================================================ +// MSC 'Driver' + +int MSC_GetInterface(uint8_t* interfaceNum); +int MSC_GetDescriptor(int i); +bool MSC_Setup(Setup& setup); +bool MSC_Data(uint8_t rx,uint8_t tx); + +//================================================================================ +//================================================================================ +// CSC 'Driver' + +int CDC_GetInterface(uint8_t* interfaceNum); +int CDC_GetDescriptor(int i); +bool CDC_Setup(Setup& setup); + +//================================================================================ +//================================================================================ + +#define TRANSFER_PGM 0x80 +#define TRANSFER_RELEASE 0x40 +#define TRANSFER_ZERO 0x20 + +int USB_SendControl(uint8_t flags, const void* d, int len); +int USB_RecvControl(void* d, int len); + +uint8_t USB_Available(uint8_t ep); +int USB_Send(uint8_t ep, const void* data, int len); // blocking +int USB_Recv(uint8_t ep, void* data, int len); // non-blocking +int USB_Recv(uint8_t ep); // non-blocking +void USB_Flush(uint8_t ep); + +#endif + +#endif /* if defined(USBCON) */ diff --git a/hardware/sam/cores/sam/USBCore.cpp b/hardware/sam/cores/sam/USBCore.cpp new file mode 100644 index 000000000..49cfe1d4c --- /dev/null +++ b/hardware/sam/cores/sam/USBCore.cpp @@ -0,0 +1,910 @@ + + +/* Copyright (c) 2010, Peter Barrett +** +** Permission to use, copy, modify, and/or distribute this software for +** any purpose with or without fee is hereby granted, provided that the +** above copyright notice and this permission notice appear in all copies. +** +** THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL +** WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR +** BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES +** OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +** WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +** ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +** SOFTWARE. +*/ +#define USBCON +#include "Platform.h" +#include "USBAPI.h" +#include "USBDesc.h" +#include "USBCore.h" + +#if 0 + +#if defined(USBCON) + +#define NUM_IT_MAX 3 + +#define EP_SINGLE_64 0x32 // EP0 +#define EP_DOUBLE_64 0x36 // Other endpoints + + +// Endpoiont 0: +#define EP_TYPE_CONTROL UDPHS_EPTCFG_EPT_SIZE_64 \ + | UDPHS_EPTCFG_EPT_TYPE_CTRL8 \ + | UDPHS_EPTCFG_BK_NUMBER_1 +#ifdef CDC_ENABLED +#define EP_TYPE_BULK_IN UDPHS_EPTCFG_EPT_SIZE_512 \ + | UDPHS_EPTCFG_EPT_DIR \ + | UDPHS_EPTCFG_EPT_TYPE_BULK \ + | UDPHS_EPTCFG_BK_NUMBER_2 +#define EP_TYPE_BULK_OUT UDPHS_EPTCFG_EPT_SIZE_512 \ + | UDPHS_EPTCFG_EPT_TYPE_BULK \ + | UDPHS_EPTCFG_BK_NUMBER_2 +#define EP_TYPE_INTERRUPT_IN UDPHS_EPTCFG_EPT_SIZE_64 \ + | UDPHS_EPTCFG_EPT_DIR \ + | UDPHS_EPTCFG_EPT_TYPE_INT \ + | UDPHS_EPTCFG_BK_NUMBER_2 +#endif + +#ifdef HID_ENABLED +#define EP_TYPE_INTERRUPT_IN_HID UDPHS_EPTCFG_EPT_SIZE_64 \ + | UDPHS_EPTCFG_EPT_DIR \ + | UDPHS_EPTCFG_EPT_TYPE_INT \ + | UDPHS_EPTCFG_BK_NUMBER_2 +#endif + +#define EP_TYPE_INTERRUPT_OUT UDPHS_EPTCFG_EPT_SIZE_64 \ + | UDPHS_EPTCFG_EPT_TYPE_INT \ + | UDPHS_EPTCFG_EPT_TYPE_INT \ + | UDPHS_EPTCFG_BK_NUMBER_1 +#define EP_TYPE_ISOCHRONOUS_IN UDPHS_EPTCFG_EPT_SIZE_1024 \ + | UDPHS_EPTCFG_EPT_DIR \ + | UDPHS_EPTCFG_EPT_TYPE_ISO \ + | UDPHS_EPTCFG_BK_NUMBER_3 +#define EP_TYPE_ISOCHRONOUS_OUT UDPHS_EPTCFG_EPT_SIZE_1024 \ + | UDPHS_EPTCFG_EPT_TYPE_ISO \ + | UDPHS_EPTCFG_BK_NUMBER_3 + +extern const u8 _initEndpoints[] ; +const u8 _initEndpoints[] = +{ + 0, + +#ifdef CDC_ENABLED + EP_TYPE_BULK_IN, // CDC_ENDPOINT_IN + EP_TYPE_BULK_OUT, // CDC_ENDPOINT_OUT + EP_TYPE_INTERRUPT_IN, // CDC_ENDPOINT_ACM +#endif + +#ifdef HID_ENABLED + EP_TYPE_INTERRUPT_IN // HID_ENDPOINT_INT +#endif +}; + +/** Pulse generation counters to keep track of the number of milliseconds remaining for each pulse type */ +#define TX_RX_LED_PULSE_MS 100 +volatile u8 TxLEDPulse; /**< Milliseconds remaining for data Tx LED pulse */ +volatile u8 RxLEDPulse; /**< Milliseconds remaining for data Rx LED pulse */ + +//================================================================== +//================================================================== + +extern const u16 STRING_LANGUAGE[] ; +extern const u16 STRING_IPRODUCT[] ; +extern const u16 STRING_IMANUFACTURER[] ; +extern const DeviceDescriptor USB_DeviceDescriptor ; +extern const DeviceDescriptor USB_DeviceDescriptorA ; + +const u16 STRING_LANGUAGE[2] = { + (3<<8) | (2+2), + 0x0409 // English +}; + +const u16 STRING_IPRODUCT[17] = { + (3<<8) | (2+2*16), +#if USB_PID == USB_PID_LEONARDO + 'A','r','d','u','i','n','o',' ','L','e','o','n','a','r','d','o' +#elif USB_PID == USB_PID_MICRO + 'A','r','d','u','i','n','o',' ','M','i','c','r','o',' ',' ',' ' +#elif USB_PID == ARDUINO_MODEL_USB_PID + 'A','r','d','u','i','n','o',' ','D','u','e',' ',' ',' ',' ',' ' +#else +#error "Need an USB PID" +#endif +}; + +const u16 STRING_IMANUFACTURER[12] = { + (3<<8) | (2+2*11), + 'A','r','d','u','i','n','o',' ','L','L','C' +}; + +#ifdef CDC_ENABLED +#define DEVICE_CLASS 0x02 +#else +#define DEVICE_CLASS 0x00 +#endif + +// DEVICE DESCRIPTOR +const DeviceDescriptor USB_DeviceDescriptor = + D_DEVICE(0x00,0x00,0x00,64,USB_VID,USB_PID,0x100,IMANUFACTURER,IPRODUCT,0,1); + +const DeviceDescriptor USB_DeviceDescriptorA = + D_DEVICE(DEVICE_CLASS,0x00,0x00,64,USB_VID,USB_PID,0x100,IMANUFACTURER,IPRODUCT,0,1); + +//================================================================== +//================================================================== + +volatile u8 _usbConfiguration = 0; +// Global variable for endpoint number +unsigned int NumEndpoint=0; + + +#include "../../../system/libsam/cmsis/sam3u/include/sam3u.h" + +#ifndef TXLED1 +#define TXLED0 +#define RXLED0 +#define TXLED1 +#define RXLED1 +#endif + + +/// Max size of the FMA FIFO +#define EPT_VIRTUAL_SIZE 16384 +#define SHIFT_INTERUPT 8 + +static inline void WaitIN(void) +{ +// while (!(UEINTX & (1<UDPHS_EPT[0].UDPHS_EPTSTA & UDPHS_EPTSTA_TX_PK_RDY)); +} + +static inline void ClearIN(void) +{ +// UEINTX = ~(1<UDPHS_EPT[NumEndpoint].UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_TX_COMPLT; +} + +static inline void WaitOUT(void) +{ +// while (!(UEINTX & (1<UDPHS_EPT[NumEndpoint].UDPHS_EPTSTA & UDPHS_EPTSTA_RX_BK_RDY)); +} + +static inline u8 WaitForINOrOUT() +{ +// while (!(UEINTX & ((1<UDPHS_EPT[NumEndpoint].UDPHS_EPTSTA & (UDPHS_EPTSTA_RX_BK_RDY | UDPHS_EPTSTA_TX_PK_RDY))); + return (UDPHS->UDPHS_EPT[NumEndpoint].UDPHS_EPTSTA & UDPHS_EPTSTA_RX_BK_RDY) == 0; +} + +static inline void ClearOUT(void) +{ +// UEINTX = ~(1<UDPHS_EPT[NumEndpoint].UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_RX_BK_RDY; +} + +/* +static void UDPHS_ClearRxFlag( unsigned char bEndpoint ) +{ + UDPHS->UDPHS_EPT[NumEndpoint].UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_RX_BK_RDY; +} +*/ + +#define UDPHS_EPTFIFO (0x20180000) // (UDPHS_EPTFIFO) Base Address + +static void Recv(volatile u8* data, u8 count) +{ + u8 *pFifo; + + pFifo = (u8*)((u32 *)UDPHS_EPTFIFO + (EPT_VIRTUAL_SIZE * NumEndpoint)); + + while (count--) + *data++ = pFifo[0]; // UEDATX; + + RXLED1; // light the RX LED + RxLEDPulse = TX_RX_LED_PULSE_MS; +} + + +static inline u8 Recv8() +{ + u8 *pFifo; + + RXLED1; // light the RX LED + RxLEDPulse = TX_RX_LED_PULSE_MS; + + pFifo = (u8*)((u32 *)UDPHS_EPTFIFO + (EPT_VIRTUAL_SIZE * NumEndpoint)); + +// return UEDATX; + return (pFifo[0]); +} + +static inline void Send8(u8 d) +{ + u8 *pFifo; + pFifo = (u8*)((u32 *)UDPHS_EPTFIFO + (EPT_VIRTUAL_SIZE * NumEndpoint)); +// UEDATX = d; + pFifo[0] =d; +} + +static inline void SetEP(u8 ep) +{ +// UENUM = ep; + NumEndpoint = ep & 7; +} + +static inline u16 FifoByteCount() +{ +// return UEBCLX; + // SAM3X + //return ((UOTGHS->UOTGHS_DEVEPTISR[ep] & UOTGHS_DEVEPTISR_BYCT_Msk) >> UOTGHS_DEVEPTISR_BYCT_Pos); + // SAM3U //AT91C_UDPHS_BYTE_COUNT (0x7FF << 20) + return ((UDPHS->UDPHS_EPT[NumEndpoint].UDPHS_EPTSTA & (0x7FF << 20)) >> 20); +} + +static inline u8 ReceivedSetupInt() +{ +// return UEINTX & (1<UDPHS_EPT[NumEndpoint].UDPHS_EPTSTA & UDPHS_EPTSTA_RX_SETUP) ); +} + +static inline void ClearSetupInt() +{ +// UEINTX = ~((1<UDPHS_EPT[NumEndpoint].UDPHS_EPTCLRSTA = UDPHS_EPTSTA_RX_SETUP | UDPHS_EPTCLRSTA_RX_BK_RDY | UDPHS_EPTCLRSTA_TX_COMPLT; +} + +static inline void Stall() +{ +// UECONX = (1<UDPHS_EPT[NumEndpoint].UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_FRCESTALL; +} + +static inline u8 ReadWriteAllowed() +{ + //return UEINTX & (1<UDPHS_EPT[NumEndpoint].UDPHS_EPTSTA & UDPHS_EPTSTA_FRCESTALL)); +} + +static inline u8 FifoFree() +{ +// return UEINTX & (1<UDPHS_EPT[NumEndpoint].UDPHS_EPTSTA & UDPHS_EPTSTA_TX_PK_RDY )); +} + +//static inline void ReleaseRX() +//{ +// UEINTX = 0x6B; // FIFOCON=0 NAKINI=1 RWAL=1 NAKOUTI=0 RXSTPI=1 RXOUTI=0 STALLEDI=1 TXINI=1 +//} + +//static inline void ReleaseTX() +//{ +// UEINTX = 0x3A; // FIFOCON=0 NAKINI=0 RWAL=1 NAKOUTI=1 RXSTPI=1 RXOUTI=0 STALLEDI=1 TXINI=0 +//} +#define UDFNUML ((UDPHS->UDPHS_FNUM & UDPHS_FNUM_FRAME_NUMBER_Msk)>>3) + +static inline u8 FrameNumber() +{ + return UDFNUML; +} + +//================================================================== +//================================================================== + +u8 USBGetConfiguration(void) +{ + return _usbConfiguration; +} + +#define USB_RECV_TIMEOUT + +// Number of bytes, assumes a rx endpoint +u8 USB_Available(u8 ep) +{ + SetEP(ep); + return FifoByteCount(); +} + +// Non Blocking receive +// Return number of bytes read +int USB_Recv(u8 ep, void* d, int len) +{ + if (!_usbConfiguration || len < 0) + return -1; + + SetEP(ep); + u8 n = FifoByteCount(); + len = min(n,len); + n = len; + u8* dst = (u8*)d; + while (n--) + *dst++ = Recv8(); +// if (len && !FifoByteCount()) // release empty buffer +// ReleaseRX(); + + return len; +} + +// Recv 1 byte if ready +int USB_Recv(u8 ep) +{ + u8 c; + if (USB_Recv(ep,&c,1) != 1) + return -1; + return c; +} + +// Space in send EP +u8 USB_SendSpace(u8 ep) +{ + SetEP(ep); + if (!ReadWriteAllowed()) + return 0; + return 64 - FifoByteCount(); +} + +// Blocking Send of data to an endpoint +int USB_Send(u8 ep, const void* d, int len) +{ + if (!_usbConfiguration) + return -1; + + int r = len; + const u8* data = (const u8*)d; + u8 zero = ep & TRANSFER_ZERO; + u8 timeout = 250; // 250ms timeout on send? TODO + while (len) + { + u8 n = USB_SendSpace(ep); + if (n == 0) + { + if (!(--timeout)) + return -1; + delay(1); + continue; + } + + if (n > len) + n = len; + len -= n; + { + SetEP(ep); + if (ep & TRANSFER_ZERO) + { + while (n--) + Send8(0); + } + else if (ep & TRANSFER_PGM) + { + while (n--) + Send8(*data++); + } + else + { + while (n--) + Send8(*data++); + } +// if (!ReadWriteAllowed() || ((len == 0) && (ep & TRANSFER_RELEASE))) // Release full buffer +// ReleaseTX(); + } + } + TXLED1; // light the TX LED + TxLEDPulse = TX_RX_LED_PULSE_MS; + return r; +} + + +//static +//void InitEP(u8 index, u8 type, u8 size) +//{ +// UENUM = index; +// UECONX = 1; +// UECFG0X = type; +// UECFG1X = size; +//} + + +static +void InitEndpoints() +{ + for (u8 i = 1; i < sizeof(_initEndpoints); i++) + { + // Reset Endpoint Fifos + UDPHS->UDPHS_EPT[i].UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_TOGGLESQ | UDPHS_EPTCLRSTA_FRCESTALL; + UDPHS->UDPHS_EPTRST = 1<UDPHS_EPT[i].UDPHS_EPTCFG = _initEndpoints[i]; + + while( (signed int)UDPHS_EPTCFG_EPT_MAPD != (signed int)((UDPHS->UDPHS_EPT[i].UDPHS_EPTCFG) & (unsigned int)UDPHS_EPTCFG_EPT_MAPD) ) + ; + UDPHS->UDPHS_EPT[i].UDPHS_EPTCTLENB = UDPHS_EPTCTLENB_EPT_ENABL; + + // UECFG1X = EP_DOUBLE_64; + } +///\// UERST = 0x7E; // And reset them +///\// UERST = 0; +} + +// Handle CLASS_INTERFACE requests +static +bool ClassInterfaceRequest(Setup& setup) +{ + u8 i = setup.wIndex; + +#ifdef CDC_ENABLED + if (CDC_ACM_INTERFACE == i) + return CDC_Setup(setup); +#endif + +#ifdef HID_ENABLED + if (HID_INTERFACE == i) + return HID_Setup(setup); +#endif + return false; +} + +int _cmark; +int _cend; +void InitControl(int end) +{ + SetEP(0); + UDPHS->UDPHS_EPT[0].UDPHS_EPTCFG = _initEndpoints[0]; + while( (signed int)UDPHS_EPTCFG_EPT_MAPD != (signed int)((UDPHS->UDPHS_EPT[0].UDPHS_EPTCFG) & (unsigned int)UDPHS_EPTCFG_EPT_MAPD) ) + ; + UDPHS->UDPHS_EPT[0].UDPHS_EPTCTLENB = UDPHS_EPTCTLENB_RX_BK_RDY + | UDPHS_EPTCTLENB_RX_SETUP + | UDPHS_EPTCTLENB_EPT_ENABL; + + _cmark = 0; + _cend = end; +} + +static +bool SendControl(u8 d) +{ + if (_cmark < _cend) + { + if (!WaitForINOrOUT()) + return false; + Send8(d); + if (!((_cmark + 1) & 0x3F)) + ClearIN(); // Fifo is full, release this packet + } + _cmark++; + return true; +}; + +// Clipped by _cmark/_cend +int USB_SendControl(u8 flags, const void* d, int len) +{ + int sent = len; + const u8* data = (const u8*)d; + bool pgm = flags & TRANSFER_PGM; + while (len--) + { + u8 c = pgm ? *data++ : *data++; + if (!SendControl(c)) + return -1; + } + return sent; +} + +// Does not timeout or cross fifo boundaries +// Will only work for transfers <= 64 bytes +// TODO +int USB_RecvControl(void* d, int len) +{ + WaitOUT(); + Recv((u8*)d,len); + ClearOUT(); + return len; +} + +int SendInterfaces() +{ + int total = 0; + u8 interfaces = 0; + +#ifdef CDC_ENABLED + total = CDC_GetInterface(&interfaces); +#endif + +#ifdef HID_ENABLED + total += HID_GetInterface(&interfaces); +#endif + + return interfaces; +} + +// Construct a dynamic configuration descriptor +// This really needs dynamic endpoint allocation etc +// TODO +static +bool SendConfiguration(int maxlen) +{ + // Count and measure interfaces + InitControl(0); + int interfaces = SendInterfaces(); + ConfigDescriptor config = D_CONFIG(_cmark + sizeof(ConfigDescriptor),interfaces); + + // Now send them + InitControl(maxlen); + USB_SendControl(0,&config,sizeof(ConfigDescriptor)); + SendInterfaces(); + return true; +} + +u8 _cdcComposite = 0; + +static +bool SendDescriptor(Setup& setup) +{ + u8 t = setup.wValueH; + if (USB_CONFIGURATION_DESCRIPTOR_TYPE == t) + return SendConfiguration(setup.wLength); + + InitControl(setup.wLength); +#ifdef HID_ENABLED + if (HID_REPORT_DESCRIPTOR_TYPE == t) + return HID_GetDescriptor(t); +#endif + + u8 desc_length = 0; + const u8* desc_addr = 0; + if (USB_DEVICE_DESCRIPTOR_TYPE == t) + { + if (setup.wLength == 8) + _cdcComposite = 1; + desc_addr = _cdcComposite ? (const u8*)&USB_DeviceDescriptorA : (const u8*)&USB_DeviceDescriptor; + } + else if (USB_STRING_DESCRIPTOR_TYPE == t) + { + if (setup.wValueL == 0) + desc_addr = (const u8*)&STRING_LANGUAGE; + else if (setup.wValueL == IPRODUCT) + desc_addr = (const u8*)&STRING_IPRODUCT; + else if (setup.wValueL == IMANUFACTURER) + desc_addr = (const u8*)&STRING_IMANUFACTURER; + else + return false; + } + + if (desc_addr == 0) + return false; + if (desc_length == 0) + desc_length = *desc_addr; + + USB_SendControl(TRANSFER_PGM,desc_addr,desc_length); + return true; +} + +// Endpoint 0 interrupt +//ISR(USB_COM_vect) +void USB_ISR() +{ + SetEP(0); + if (!ReceivedSetupInt()) + return; + + Setup setup; + Recv((u8*)&setup,8); + ClearSetupInt(); + + u8 requestType = setup.bmRequestType; + if (requestType & REQUEST_DEVICETOHOST) + WaitIN(); + else + ClearIN(); + + bool ok = true; + if (REQUEST_STANDARD == (requestType & REQUEST_TYPE)) + { + // Standard Requests + u8 r = setup.bRequest; + if (GET_STATUS == r) + { + Send8(0); // TODO + Send8(0); + } + else if (CLEAR_FEATURE == r) + { + } + else if (SET_FEATURE == r) + { + } + else if (SET_ADDRESS == r) + { + WaitIN(); + UDPHS->UDPHS_CTRL |= UDPHS_CTRL_DEV_ADDR(setup.wValueL) | UDPHS_CTRL_FADDR_EN; + } + else if (GET_DESCRIPTOR == r) + { + ok = SendDescriptor(setup); + } + else if (SET_DESCRIPTOR == r) + { + ok = false; + } + else if (GET_CONFIGURATION == r) + { + Send8(1); + } + else if (SET_CONFIGURATION == r) + { + if (REQUEST_DEVICE == (requestType & REQUEST_RECIPIENT)) + { + InitEndpoints(); + _usbConfiguration = setup.wValueL; + } else + ok = false; + } + else if (GET_INTERFACE == r) + { + } + else if (SET_INTERFACE == r) + { + } + } + else + { + InitControl(setup.wLength); // Max length of transfer + ok = ClassInterfaceRequest(setup); + } + + if (ok) + ClearIN(); + else + { + Stall(); + } +} + +void USB_Flush(u8 ep) +{ + SetEP(ep); +// if (FifoByteCount()) +// ReleaseTX(); +} + +// General interrupt +// USB device interrupt handler +/* +// Manages device resume, suspend, end of bus reset. +// Forwards endpoint interrupts to the appropriate handler. +// General interrupt +ISR(USB_GEN_vect) +{ + u8 udint = UDINT; + UDINT = 0; + + // End of Reset + if (udint & (1<UDPHS_INTSTA & UDPHS->UDPHS_IEN; + + // Handle all UDPHS interrupts + while (status != 0) { + + // Start of Frame - happens every millisecond so we use it for TX and RX LED one-shot timing, too + if ((status & UDPHS_IEN_INT_SOF) != 0) { + +#ifdef CDC_ENABLED + USB_Flush(CDC_TX); // Send a tx frame if found +#endif + + // check whether the one-shot period has elapsed. if so, turn off the LED + if (TxLEDPulse && !(--TxLEDPulse)) + TXLED0; + if (RxLEDPulse && !(--RxLEDPulse)) + RXLED0; + + // Acknowledge interrupt + UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_INT_SOF; + status &= ~UDPHS_IEN_INT_SOF; + } + // Suspend + // This interrupt is always treated last (hence the '==') + else if (status == UDPHS_IEN_DET_SUSPD) { + + //UDPHS_DisableBIAS(); + + // Enable wakeup + UDPHS->UDPHS_IEN |= UDPHS_IEN_WAKE_UP | UDPHS_IEN_ENDOFRSM; + UDPHS->UDPHS_IEN &= ~UDPHS_IEN_DET_SUSPD; + + // Acknowledge interrupt + UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_DET_SUSPD | UDPHS_CLRINT_WAKE_UP; + + //UDPHS_DisableUsbClock(); + + } + // Resume + else if( ((status & UDPHS_IEN_WAKE_UP) != 0) // line activity + || ((status & UDPHS_IEN_ENDOFRSM) != 0)) { // pc wakeup + { + + //UDPHS_EnableUsbClock(); + //UDPHS_EnableBIAS(); + + UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_WAKE_UP | UDPHS_CLRINT_ENDOFRSM + | UDPHS_CLRINT_DET_SUSPD; + + UDPHS->UDPHS_IEN |= UDPHS_IEN_ENDOFRSM | UDPHS_IEN_DET_SUSPD; + UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_WAKE_UP | UDPHS_CLRINT_ENDOFRSM; + UDPHS->UDPHS_IEN &= ~UDPHS_IEN_WAKE_UP; + } + } + // End of Reset + else if ((status & UDPHS_IEN_ENDRESET) == UDPHS_IEN_ENDRESET) { + + InitControl(0); // init ep0 + _usbConfiguration = 0; // not configured yet + //UEIENX = 1 << RXSTPE; // Enable interrupts for ep0 + + //UDPHS_ResetEndpoints(); + //UDPHS_DisableEndpoints(); + //USBD_ConfigureEndpoint(0); + UDPHS->UDPHS_IEN |= (1<UDPHS_CLRINT = UDPHS_CLRINT_WAKE_UP | UDPHS_CLRINT_DET_SUSPD; + + //// Enable the Start Of Frame (SOF) interrupt if needed + UDPHS->UDPHS_IEN |= UDPHS_IEN_INT_SOF; + + // Acknowledge end of bus reset interrupt + UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_ENDRESET; + + UDPHS->UDPHS_IEN |= UDPHS_IEN_DET_SUSPD; + } + // Handle upstream resume interrupt + else if (status & UDPHS_IEN_UPSTR_RES) { + + // - Acknowledge the IT + UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_UPSTR_RES; + } + // Endpoint interrupts + else { + // Handle endpoint interrupts + for (numIT = 0; numIT < NUM_IT_MAX; numIT++) { + + if ((status & (1 << SHIFT_INTERUPT << numIT)) != 0) { + USB_ISR(); + //EndpointHandler(numIT); // TODO: interrupt for bulk + } + } + } + // Retrieve new interrupt status + status = UDPHS->UDPHS_INTSTA & UDPHS->UDPHS_IEN; + } +} + +// VBUS or counting frames +// Any frame counting? +u8 USBConnected() +{ + u8 f = UDFNUML; + delay(3); + return f != UDFNUML; +} + + +//======================================================================= +//======================================================================= + +USB_ USB; + +USB_::USB_() +{ +} + +void USB_::attach() +{/* + _usbConfiguration = 0; + + //UHWCON = 0x01; // power internal reg + //USBCON = (1<PMC_PCER = (1 << ID_UDPHS); + // Enable 480MHZ + //AT91C_BASE_CKGR->CKGR_UCKR |= (AT91C_CKGR_PLLCOUNT & (3 << 20)) | AT91C_CKGR_UPLLEN; + CKGR->CKGR_UCKR |= ((0xf << 20) & (3 << 20)) | AT91C_CKGR_UPLLEN; + // Wait until UTMI PLL is locked + while ((PMC->PMC_SR & PMC_LOCKU) == 0); + + // Reset and enable IP UDPHS + UDPHS->UDPHS_CTRL &= ~UDPHS_CTRL_EN_UDPHS; + UDPHS->UDPHS_CTRL |= UDPHS_CTRL_EN_UDPHS; + + //USBCON = ((1<UDPHS_IEN = 0; + UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_UPSTR_RES + | UDPHS_CLRINT_ENDOFRSM + | UDPHS_CLRINT_WAKE_UP + | UDPHS_CLRINT_ENDRESET + | UDPHS_CLRINT_INT_SOF + | UDPHS_CLRINT_MICRO_SOF + | UDPHS_CLRINT_DET_SUSPD; + + // Enable interrupts for EOR (End of Reset), wake up and SOF (start of frame) + //UDIEN = (1<UDPHS_IEN = UDPHS_IEN_ENDOFRSM + | UDPHS_IEN_WAKE_UP + | UDPHS_IEN_DET_SUSPD; + + // enable attach resistor + //UDCON = 0; + UDPHS->UDPHS_CTRL &= ~UDPHS_CTRL_DETACH; // Pull Up on DP + UDPHS->UDPHS_CTRL |= UDPHS_CTRL_PULLD_DIS; // Disable Pull Down + + TX_RX_LED_INIT; +*/} + +void USB_::detach() +{ + UDPHS->UDPHS_CTRL |= UDPHS_CTRL_DETACH; // detach + UDPHS->UDPHS_CTRL &= ~UDPHS_CTRL_PULLD_DIS; // Enable Pull Down +} + +// Check for interrupts +// TODO: VBUS detection +bool USB_::configured() +{ + return _usbConfiguration; +} + +void USB_::poll() +{ +} + +#endif /* if defined(USBCON) */ + +#endif diff --git a/hardware/sam/cores/sam/USBCore.h b/hardware/sam/cores/sam/USBCore.h new file mode 100644 index 000000000..02558647d --- /dev/null +++ b/hardware/sam/cores/sam/USBCore.h @@ -0,0 +1,304 @@ + +// Copyright (c) 2010, Peter Barrett +/* +** Permission to use, copy, modify, and/or distribute this software for +** any purpose with or without fee is hereby granted, provided that the +** above copyright notice and this permission notice appear in all copies. +** +** THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL +** WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR +** BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES +** OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +** WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +** ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +** SOFTWARE. +*/ + +#ifndef __USBCORE_H__ +#define __USBCORE_H__ + +// Standard requests +#define GET_STATUS 0 +#define CLEAR_FEATURE 1 +#define SET_FEATURE 3 +#define SET_ADDRESS 5 +#define GET_DESCRIPTOR 6 +#define SET_DESCRIPTOR 7 +#define GET_CONFIGURATION 8 +#define SET_CONFIGURATION 9 +#define GET_INTERFACE 10 +#define SET_INTERFACE 11 + + +// bmRequestType +#define REQUEST_HOSTTODEVICE 0x00 +#define REQUEST_DEVICETOHOST 0x80 +#define REQUEST_DIRECTION 0x80 + +#define REQUEST_STANDARD 0x00 +#define REQUEST_CLASS 0x20 +#define REQUEST_VENDOR 0x40 +#define REQUEST_TYPE 0x60 + +#define REQUEST_DEVICE 0x00 +#define REQUEST_INTERFACE 0x01 +#define REQUEST_ENDPOINT 0x02 +#define REQUEST_OTHER 0x03 +#define REQUEST_RECIPIENT 0x03 + +#define REQUEST_DEVICETOHOST_CLASS_INTERFACE (REQUEST_DEVICETOHOST + REQUEST_CLASS + REQUEST_INTERFACE) +#define REQUEST_HOSTTODEVICE_CLASS_INTERFACE (REQUEST_HOSTTODEVICE + REQUEST_CLASS + REQUEST_INTERFACE) + +// Class requests + +#define CDC_SET_LINE_CODING 0x20 +#define CDC_GET_LINE_CODING 0x21 +#define CDC_SET_CONTROL_LINE_STATE 0x22 + +#define MSC_RESET 0xFF +#define MSC_GET_MAX_LUN 0xFE + +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B + +// Descriptors + +#define USB_DEVICE_DESC_SIZE 18 +#define USB_CONFIGUARTION_DESC_SIZE 9 +#define USB_INTERFACE_DESC_SIZE 9 +#define USB_ENDPOINT_DESC_SIZE 7 + +#define USB_DEVICE_DESCRIPTOR_TYPE 1 +#define USB_CONFIGURATION_DESCRIPTOR_TYPE 2 +#define USB_STRING_DESCRIPTOR_TYPE 3 +#define USB_INTERFACE_DESCRIPTOR_TYPE 4 +#define USB_ENDPOINT_DESCRIPTOR_TYPE 5 + +#define USB_DEVICE_CLASS_COMMUNICATIONS 0x02 +#define USB_DEVICE_CLASS_HUMAN_INTERFACE 0x03 +#define USB_DEVICE_CLASS_STORAGE 0x08 +#define USB_DEVICE_CLASS_VENDOR_SPECIFIC 0xFF + +#define USB_CONFIG_POWERED_MASK 0x40 +#define USB_CONFIG_BUS_POWERED 0x80 +#define USB_CONFIG_SELF_POWERED 0xC0 +#define USB_CONFIG_REMOTE_WAKEUP 0x20 + +// bMaxPower in Configuration Descriptor +#define USB_CONFIG_POWER_MA(mA) ((mA)/2) + +// bEndpointAddress in Endpoint Descriptor +#define USB_ENDPOINT_DIRECTION_MASK 0x80 +#define USB_ENDPOINT_OUT(addr) ((addr) | 0x00) +#define USB_ENDPOINT_IN(addr) ((addr) | 0x80) + +#define USB_ENDPOINT_TYPE_MASK 0x03 +#define USB_ENDPOINT_TYPE_CONTROL 0x00 +#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01 +#define USB_ENDPOINT_TYPE_BULK 0x02 +#define USB_ENDPOINT_TYPE_INTERRUPT 0x03 + +#define TOBYTES(x) ((x) & 0xFF),(((x) >> 8) & 0xFF) + +#define CDC_V1_10 0x0110 +#define CDC_COMMUNICATION_INTERFACE_CLASS 0x02 + +#define CDC_CALL_MANAGEMENT 0x01 +#define CDC_ABSTRACT_CONTROL_MODEL 0x02 +#define CDC_HEADER 0x00 +#define CDC_ABSTRACT_CONTROL_MANAGEMENT 0x02 +#define CDC_UNION 0x06 +#define CDC_CS_INTERFACE 0x24 +#define CDC_CS_ENDPOINT 0x25 +#define CDC_DATA_INTERFACE_CLASS 0x0A + +#define MSC_SUBCLASS_SCSI 0x06 +#define MSC_PROTOCOL_BULK_ONLY 0x50 + +#define HID_HID_DESCRIPTOR_TYPE 0x21 +#define HID_REPORT_DESCRIPTOR_TYPE 0x22 +#define HID_PHYSICAL_DESCRIPTOR_TYPE 0x23 + + +// Device +typedef struct { + u8 len; // 18 + u8 dtype; // 1 USB_DEVICE_DESCRIPTOR_TYPE + u16 usbVersion; // 0x200 + u8 deviceClass; + u8 deviceSubClass; + u8 deviceProtocol; + u8 packetSize0; // Packet 0 + u16 idVendor; + u16 idProduct; + u16 deviceVersion; // 0x100 + u8 iManufacturer; + u8 iProduct; + u8 iSerialNumber; + u8 bNumConfigurations; +} DeviceDescriptor; + +// Config +typedef struct { + u8 len; // 9 + u8 dtype; // 2 + u16 clen; // total length + u8 numInterfaces; + u8 config; + u8 iconfig; + u8 attributes; + u8 maxPower; +} ConfigDescriptor; + +// String + +// Interface +typedef struct +{ + u8 len; // 9 + u8 dtype; // 4 + u8 number; + u8 alternate; + u8 numEndpoints; + u8 interfaceClass; + u8 interfaceSubClass; + u8 protocol; + u8 iInterface; +} InterfaceDescriptor; + +// Endpoint +typedef struct +{ + u8 len; // 7 + u8 dtype; // 5 + u8 addr; + u8 attr; + u16 packetSize; + u8 interval; +} EndpointDescriptor; + +// Interface Association Descriptor +// Used to bind 2 interfaces together in CDC compostite device +typedef struct +{ + u8 len; // 8 + u8 dtype; // 11 + u8 firstInterface; + u8 interfaceCount; + u8 functionClass; + u8 funtionSubClass; + u8 functionProtocol; + u8 iInterface; +} IADDescriptor; + +// CDC CS interface descriptor +typedef struct +{ + u8 len; // 5 + u8 dtype; // 0x24 + u8 subtype; + u8 d0; + u8 d1; +} CDCCSInterfaceDescriptor; + +typedef struct +{ + u8 len; // 4 + u8 dtype; // 0x24 + u8 subtype; + u8 d0; +} CDCCSInterfaceDescriptor4; + +typedef struct +{ + u8 len; + u8 dtype; // 0x24 + u8 subtype; // 1 + u8 bmCapabilities; + u8 bDataInterface; +} CMFunctionalDescriptor; + +typedef struct +{ + u8 len; + u8 dtype; // 0x24 + u8 subtype; // 1 + u8 bmCapabilities; +} ACMFunctionalDescriptor; + +typedef struct +{ + // IAD + IADDescriptor iad; // Only needed on compound device + + // Control + InterfaceDescriptor cif; // + CDCCSInterfaceDescriptor header; + CMFunctionalDescriptor callManagement; // Call Management + ACMFunctionalDescriptor controlManagement; // ACM + CDCCSInterfaceDescriptor functionalDescriptor; // CDC_UNION + EndpointDescriptor cifin; + + // Data + InterfaceDescriptor dif; + EndpointDescriptor in; + EndpointDescriptor out; + +} CDCDescriptor; + +typedef struct +{ + InterfaceDescriptor msc; + EndpointDescriptor in; + EndpointDescriptor out; +} MSCDescriptor; + +typedef struct +{ + u8 len; // 9 + u8 dtype; // 0x21 + u8 addr; + u8 versionL; // 0x101 + u8 versionH; // 0x101 + u8 country; + u8 desctype; // 0x22 report + u8 descLenL; + u8 descLenH; +} HIDDescDescriptor; + +typedef struct +{ + InterfaceDescriptor hid; + HIDDescDescriptor desc; + EndpointDescriptor in; +} HIDDescriptor; + + +#define D_DEVICE(_class,_subClass,_proto,_packetSize0,_vid,_pid,_version,_im,_ip,_is,_configs) \ + { 18, 1, 0x200, _class,_subClass,_proto,_packetSize0,_vid,_pid,_version,_im,_ip,_is,_configs } + +#define D_CONFIG(_totalLength,_interfaces) \ + { 9, 2, _totalLength,_interfaces, 1, 0, USB_CONFIG_BUS_POWERED, USB_CONFIG_POWER_MA(500) } + +#define D_INTERFACE(_n,_numEndpoints,_class,_subClass,_protocol) \ + { 9, 4, _n, 0, _numEndpoints, _class,_subClass, _protocol, 0 } + +#define D_ENDPOINT(_addr,_attr,_packetSize, _interval) \ + { 7, 5, _addr,_attr,_packetSize, _interval } + +#define D_IAD(_firstInterface, _count, _class, _subClass, _protocol) \ + { 8, 11, _firstInterface, _count, _class, _subClass, _protocol, 0 } + +#define D_HIDREPORT(_descriptorLength) \ + { 9, 0x21, 0x1, 0x1, 0, 1, 0x22, _descriptorLength, 0 } + +#define D_CDCCS(_subtype,_d0,_d1) { 5, 0x24, _subtype, _d0, _d1 } +#define D_CDCCS4(_subtype,_d0) { 4, 0x24, _subtype, _d0 } + + +#endif diff --git a/hardware/sam/cores/sam/USBDesc.h b/hardware/sam/cores/sam/USBDesc.h new file mode 100644 index 000000000..1c3b28a0c --- /dev/null +++ b/hardware/sam/cores/sam/USBDesc.h @@ -0,0 +1,68 @@ + + +/* Copyright (c) 2011, Peter Barrett +** +** Permission to use, copy, modify, and/or distribute this software for +** any purpose with or without fee is hereby granted, provided that the +** above copyright notice and this permission notice appear in all copies. +** +** THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL +** WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR +** BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES +** OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +** WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +** ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +** SOFTWARE. +*/ + +#define CDC_ENABLED +#define HID_ENABLED + + +#ifdef CDC_ENABLED +#define CDC_INTERFACE_COUNT 2 +#define CDC_ENPOINT_COUNT 3 +#else +#define CDC_INTERFACE_COUNT 0 +#define CDC_ENPOINT_COUNT 0 +#endif + +#ifdef HID_ENABLED +#define HID_INTERFACE_COUNT 1 +#define HID_ENPOINT_COUNT 1 +#else +#define HID_INTERFACE_COUNT 0 +#define HID_ENPOINT_COUNT 0 +#endif + +#define CDC_ACM_INTERFACE 0 // CDC ACM +#define CDC_DATA_INTERFACE 1 // CDC Data +#define CDC_FIRST_ENDPOINT 1 +#define CDC_ENDPOINT_IN (CDC_FIRST_ENDPOINT) // CDC First +#define CDC_ENDPOINT_OUT (CDC_FIRST_ENDPOINT+1) +#define CDC_ENDPOINT_ACM (CDC_FIRST_ENDPOINT+2) + +#define HID_INTERFACE (CDC_ACM_INTERFACE + CDC_INTERFACE_COUNT) // HID Interface +#define HID_FIRST_ENDPOINT (CDC_FIRST_ENDPOINT + CDC_ENPOINT_COUNT) +#define HID_ENDPOINT_INT (HID_FIRST_ENDPOINT) + +#define INTERFACE_COUNT (MSC_INTERFACE + MSC_INTERFACE_COUNT) + +#ifdef CDC_ENABLED +#define CDC_RX CDC_ENDPOINT_OUT +#define CDC_TX CDC_ENDPOINT_IN +#endif + +#ifdef HID_ENABLED +#define HID_TX HID_ENDPOINT_INT +#endif + +#define IMANUFACTURER 1 +#define IPRODUCT 2 +#define USB_PID_LEONARDO 0x0034 +#define USB_PID_MICRO 0x0035 +#define ARDUINO_MODEL_USB_PID 0x0036 +#define USB_VID 0x2341 // arduino LLC vid +#define USB_PID ARDUINO_MODEL_USB_PID + diff --git a/hardware/sam/cores/sam/USB_driver.cpp b/hardware/sam/cores/sam/USB_driver.cpp new file mode 100644 index 000000000..ce16fbdb1 --- /dev/null +++ b/hardware/sam/cores/sam/USB_driver.cpp @@ -0,0 +1,21 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "Arduino.h" +#include "USB_driver.h" + diff --git a/hardware/sam/cores/sam/USB_driver.h b/hardware/sam/cores/sam/USB_driver.h new file mode 100644 index 000000000..2160f2ef3 --- /dev/null +++ b/hardware/sam/cores/sam/USB_driver.h @@ -0,0 +1,22 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _USB_DRIVER_ +#define _USB_DRIVER_ + +#endif /* _USB_DRIVER_*/ diff --git a/hardware/sam/cores/sam/WCharacter.h b/hardware/sam/cores/sam/WCharacter.h new file mode 100644 index 000000000..e84b34857 --- /dev/null +++ b/hardware/sam/cores/sam/WCharacter.h @@ -0,0 +1,180 @@ +/* + WCharacter.h - Character utility functions for Wiring & Arduino + Copyright (c) 2010 Hernando Barragan. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef Character_h +#define Character_h + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// WCharacter.h prototypes +#if defined ( __GNUC__ ) +inline boolean isAlphaNumeric(int c) __attribute__((always_inline)); +inline boolean isAlpha(int c) __attribute__((always_inline)); +inline boolean isAscii(int c) __attribute__((always_inline)); +inline boolean isWhitespace(int c) __attribute__((always_inline)); +inline boolean isControl(int c) __attribute__((always_inline)); +inline boolean isDigit(int c) __attribute__((always_inline)); +inline boolean isGraph(int c) __attribute__((always_inline)); +inline boolean isLowerCase(int c) __attribute__((always_inline)); +inline boolean isPrintable(int c) __attribute__((always_inline)); +inline boolean isPunct(int c) __attribute__((always_inline)); +inline boolean isSpace(int c) __attribute__((always_inline)); +inline boolean isUpperCase(int c) __attribute__((always_inline)); +inline boolean isHexadecimalDigit(int c) __attribute__((always_inline)); +inline int toAscii(int c) __attribute__((always_inline)); +inline int toLowerCase(int c) __attribute__((always_inline)); +inline int toUpperCase(int c)__attribute__((always_inline)); +#elif defined ( __ICCARM__ ) +#endif + +// Checks for an alphanumeric character. +// It is equivalent to (isalpha(c) || isdigit(c)). +inline boolean isAlphaNumeric(int c) +{ + return ( isalnum(c) == 0 ? false : true); +} + + +// Checks for an alphabetic character. +// It is equivalent to (isupper(c) || islower(c)). +inline boolean isAlpha(int c) +{ + return ( isalpha(c) == 0 ? false : true); +} + + +// Checks whether c is a 7-bit unsigned char value +// that fits into the ASCII character set. +inline boolean isAscii(int c) +{ +/* return ( isascii(c) == 0 ? false : true); */ + return ( (c & ~0x7f) != 0 ? false : true); +} + + +// Checks for a blank character, that is, a space or a tab. +inline boolean isWhitespace(int c) +{ + return ( isblank (c) == 0 ? false : true); +} + + +// Checks for a control character. +inline boolean isControl(int c) +{ + return ( iscntrl (c) == 0 ? false : true); +} + + +// Checks for a digit (0 through 9). +inline boolean isDigit(int c) +{ + return ( isdigit (c) == 0 ? false : true); +} + + +// Checks for any printable character except space. +inline boolean isGraph(int c) +{ + return ( isgraph (c) == 0 ? false : true); +} + + +// Checks for a lower-case character. +inline boolean isLowerCase(int c) +{ + return (islower (c) == 0 ? false : true); +} + + +// Checks for any printable character including space. +inline boolean isPrintable(int c) +{ + return ( isprint (c) == 0 ? false : true); +} + + +// Checks for any printable character which is not a space +// or an alphanumeric character. +inline boolean isPunct(int c) +{ + return ( ispunct (c) == 0 ? false : true); +} + + +// Checks for white-space characters. For the avr-libc library, +// these are: space, formfeed ('\f'), newline ('\n'), carriage +// return ('\r'), horizontal tab ('\t'), and vertical tab ('\v'). +inline boolean isSpace(int c) +{ + return ( isspace (c) == 0 ? false : true); +} + + +// Checks for an uppercase letter. +inline boolean isUpperCase(int c) +{ + return ( isupper (c) == 0 ? false : true); +} + + +// Checks for a hexadecimal digits, i.e. one of 0 1 2 3 4 5 6 7 +// 8 9 a b c d e f A B C D E F. +inline boolean isHexadecimalDigit(int c) +{ + return ( isxdigit (c) == 0 ? false : true); +} + + +// Converts c to a 7-bit unsigned char value that fits into the +// ASCII character set, by clearing the high-order bits. +inline int toAscii(int c) +{ +/* return toascii (c); */ + return (c & 0x7f); +} + + +// Warning: +// Many people will be unhappy if you use this function. +// This function will convert accented letters into random +// characters. + +// Converts the letter c to lower case, if possible. +inline int toLowerCase(int c) +{ + return tolower (c); +} + + +// Converts the letter c to upper case, if possible. +inline int toUpperCase(int c) +{ + return toupper (c); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hardware/sam/cores/sam/WInterrupts.c b/hardware/sam/cores/sam/WInterrupts.c new file mode 100644 index 000000000..8d5768aaa --- /dev/null +++ b/hardware/sam/cores/sam/WInterrupts.c @@ -0,0 +1,57 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "WInterrupts.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** PIO interrupt handlers array */ +/*volatile*/ static voidFuncPtr g_apfn_IntFunc[EXTERNAL_NUM_INTERRUPTS]={ 0 } ; + +void attachInterrupt( uint32_t ulInterrupt, void (*pfn_UserFunc)(void), uint32_t ulMode ) +{ + if ( ulInterrupt < EXTERNAL_NUM_INTERRUPTS ) + { + g_apfn_IntFunc[ulInterrupt] = pfn_UserFunc ; + + // Configure the interrupt mode (trigger on low input, any change, rising + // edge, or falling edge). The mode constants were chosen to correspond + // to the configuration bits in the hardware register, so we simply shift + // the mode into place. + + // Enable the interrupt. + + } +} + +void detachInterrupt( uint32_t ulInterrupt ) +{ + if ( ulInterrupt < EXTERNAL_NUM_INTERRUPTS ) + { + /* Disable the interrupt. */ + + + g_apfn_IntFunc[ulInterrupt] = NULL ; + } +} + +#ifdef __cplusplus +} +#endif diff --git a/hardware/sam/cores/sam/WInterrupts.h b/hardware/sam/cores/sam/WInterrupts.h new file mode 100644 index 000000000..3c8caa694 --- /dev/null +++ b/hardware/sam/cores/sam/WInterrupts.h @@ -0,0 +1,82 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _WIRING_INTERRUPTS_ +#define _WIRING_INTERRUPTS_ + +#include "Arduino.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef struct _InterruptSource +//{ +// /* Pointer to the source pin instance. */ +// PinDescription *pPin ; +// +// /* Interrupt handler. */ +// void (*handler)( const PinDescription *pPin ) ; +//} InterruptSource ; + + +/* + * \brief Specifies a function to call when an external interrupt occurs. + * Replaces any previous function that was attached to the interrupt. + * All Arduino SAM3 based boards pins can be switched into INPUT mode and have + * an interrupt user function attached to an event. + * + * \param ulInterrupt + * \param pfn_UserFunc + * \param ulMode + * +PIO_IT_RE_OR_HL = Interrupt High Level/Rising Edge detection is active +PIO_IT_EDGE = Interrupt Edge detection is active +PIO_IT_LOW_LEVEL = Low level interrupt is active +PIO_IT_HIGH_LEVEL = High level interrupt is active +PIO_IT_FALL_EDGE = Falling edge interrupt is active +PIO_IT_RISE_EDGE = Rising edge interrupt is active + +interrupt: the number of the interrupt (int) + +function: the function to call when the interrupt occurs; this function must take no parameters and return nothing. This function is sometimes referred to as an interrupt service routine. + +mode defines when the interrupt should be triggered. Four contstants are predefined as valid values: + + LOW to trigger the interrupt whenever the pin is low, + CHANGE to trigger the interrupt whenever the pin changes value + RISING to trigger when the pin goes from low to high, + FALLING for when the pin goes from high to low. + */ +extern void attachInterrupt( uint32_t ulInterrupt, void (*pfn_UserFunc)(void), uint32_t ulMode ) ; + +/* +Turns off the given interrupt. + +Parameters + +interrupt: the number of interrupt to disable (0 or 1). +*/ +extern void detachInterrupt( uint32_t ulInterrupt ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* _WIRING_INTERRUPTS_ */ diff --git a/hardware/sam/cores/sam/WMath.cpp b/hardware/sam/cores/sam/WMath.cpp new file mode 100644 index 000000000..ec2e29b28 --- /dev/null +++ b/hardware/sam/cores/sam/WMath.cpp @@ -0,0 +1,68 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +extern "C" { + #include "stdlib.h" + #include "stdint.h" +} +#include "WMath.h" + +extern void randomSeed( uint32_t dwSeed ) +{ + if ( dwSeed != 0 ) + { + srand( dwSeed ) ; + } +} + +extern long random( long howbig ) +{ + if ( howbig == 0 ) + { + return 0 ; + } + + return rand() % howbig; +} + +extern long random( long howsmall, long howbig ) +{ + if (howsmall >= howbig) + { + return howsmall; + } + + long diff = howbig - howsmall; + + return random(diff) + howsmall; +} + +extern long map(long x, long in_min, long in_max, long out_min, long out_max) +{ + return (x - in_min) * (out_max - out_min) / (in_max - in_min) + out_min; +} + +extern uint16_t makeWord( uint16_t w ) +{ + return w ; +} + +extern uint16_t makeWord( uint8_t h, uint8_t l ) +{ + return (h << 8) | l ; +} diff --git a/hardware/sam/cores/sam/WMath.h b/hardware/sam/cores/sam/WMath.h new file mode 100644 index 000000000..05779eafb --- /dev/null +++ b/hardware/sam/cores/sam/WMath.h @@ -0,0 +1,33 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _WIRING_MATH_ +#define _WIRING_MATH_ + +extern long random( long ) ; +extern long random( long, long ) ; +extern void randomSeed( uint32_t dwSeed ) ; +extern long map( long, long, long, long, long ) ; + +extern uint16_t makeWord( uint16_t w ) ; +extern uint16_t makeWord( uint8_t h, uint8_t l ) ; + +#define word(...) makeWord(__VA_ARGS__) + + +#endif /* _WIRING_MATH_ */ diff --git a/hardware/sam/cores/sam/WString.cpp b/hardware/sam/cores/sam/WString.cpp new file mode 100644 index 000000000..d0b86ece9 --- /dev/null +++ b/hardware/sam/cores/sam/WString.cpp @@ -0,0 +1,646 @@ +/* + WString.cpp - String library for Wiring & Arduino + ...mostly rewritten by Paul Stoffregen... + Copyright (c) 2009-10 Hernando Barragan. All rights reserved. + Copyright 2011, Paul Stoffregen, paul@pjrc.com + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "WString.h" +#include "itoa.h" + + +/*********************************************/ +/* Constructors */ +/*********************************************/ + +String::String(const char *cstr) +{ + init(); + if (cstr) copy(cstr, strlen(cstr)); +} + +String::String(const String &value) +{ + init(); + *this = value; +} + +#ifdef __GXX_EXPERIMENTAL_CXX0X__ +String::String(String &&rval) +{ + init(); + move(rval); +} +String::String(StringSumHelper &&rval) +{ + init(); + move(rval); +} +#endif + +String::String(char c) +{ + init(); + char buf[2]; + buf[0] = c; + buf[1] = 0; + *this = buf; +} + +String::String(unsigned char value, unsigned char base) +{ + init(); + char buf[9]; + utoa(value, buf, base); + *this = buf; +} + +String::String(int value, unsigned char base) +{ + init(); + char buf[18]; + itoa(value, buf, base); + *this = buf; +} + +String::String(unsigned int value, unsigned char base) +{ + init(); + char buf[17]; + utoa(value, buf, base); + *this = buf; +} + +String::String(long value, unsigned char base) +{ + init(); + char buf[34]; + ltoa(value, buf, base); + *this = buf; +} + +String::String(unsigned long value, unsigned char base) +{ + init(); + char buf[33]; + ultoa(value, buf, base); + *this = buf; +} + +String::~String() +{ + free(buffer); +} + +/*********************************************/ +/* Memory Management */ +/*********************************************/ + +inline void String::init(void) +{ + buffer = NULL; + capacity = 0; + len = 0; + flags = 0; +} + +void String::invalidate(void) +{ + if (buffer) free(buffer); + buffer = NULL; + capacity = len = 0; +} + +unsigned char String::reserve(unsigned int size) +{ + if (buffer && capacity >= size) return 1; + if (changeBuffer(size)) { + if (len == 0) buffer[0] = 0; + return 1; + } + return 0; +} + +unsigned char String::changeBuffer(unsigned int maxStrLen) +{ + char *newbuffer = (char *)realloc(buffer, maxStrLen + 1); + if (newbuffer) { + buffer = newbuffer; + capacity = maxStrLen; + return 1; + } + return 0; +} + +/*********************************************/ +/* Copy and Move */ +/*********************************************/ + +String & String::copy(const char *cstr, unsigned int length) +{ + if (!reserve(length)) { + invalidate(); + return *this; + } + len = length; + strcpy(buffer, cstr); + return *this; +} + +#ifdef __GXX_EXPERIMENTAL_CXX0X__ +void String::move(String &rhs) +{ + if (buffer) { + if (capacity >= rhs.len) { + strcpy(buffer, rhs.buffer); + len = rhs.len; + rhs.len = 0; + return; + } else { + free(buffer); + } + } + buffer = rhs.buffer; + capacity = rhs.capacity; + len = rhs.len; + rhs.buffer = NULL; + rhs.capacity = 0; + rhs.len = 0; +} +#endif + +String & String::operator = (const String &rhs) +{ + if (this == &rhs) return *this; + + if (rhs.buffer) copy(rhs.buffer, rhs.len); + else invalidate(); + + return *this; +} + +#ifdef __GXX_EXPERIMENTAL_CXX0X__ +String & String::operator = (String &&rval) +{ + if (this != &rval) move(rval); + return *this; +} + +String & String::operator = (StringSumHelper &&rval) +{ + if (this != &rval) move(rval); + return *this; +} +#endif + +String & String::operator = (const char *cstr) +{ + if (cstr) copy(cstr, strlen(cstr)); + else invalidate(); + + return *this; +} + +/*********************************************/ +/* concat */ +/*********************************************/ + +unsigned char String::concat(const String &s) +{ + return concat(s.buffer, s.len); +} + +unsigned char String::concat(const char *cstr, unsigned int length) +{ + unsigned int newlen = len + length; + if (!cstr) return 0; + if (length == 0) return 1; + if (!reserve(newlen)) return 0; + strcpy(buffer + len, cstr); + len = newlen; + return 1; +} + +unsigned char String::concat(const char *cstr) +{ + if (!cstr) return 0; + return concat(cstr, strlen(cstr)); +} + +unsigned char String::concat(char c) +{ + char buf[2]; + buf[0] = c; + buf[1] = 0; + return concat(buf, 1); +} + +unsigned char String::concat(unsigned char num) +{ + char buf[4]; +// itoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +unsigned char String::concat(int num) +{ + char buf[7]; + itoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +unsigned char String::concat(unsigned int num) +{ + char buf[6]; + utoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +unsigned char String::concat(long num) +{ + char buf[12]; + ltoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +unsigned char String::concat(unsigned long num) +{ + char buf[11]; + ultoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +/*********************************************/ +/* Concatenate */ +/*********************************************/ + +StringSumHelper & operator + (const StringSumHelper &lhs, const String &rhs) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(rhs.buffer, rhs.len)) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, const char *cstr) +{ + StringSumHelper &a = const_cast(lhs); + if (!cstr || !a.concat(cstr, strlen(cstr))) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, char c) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(c)) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, unsigned char num) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, int num) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, unsigned int num) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, long num) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, unsigned long num) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) a.invalidate(); + return a; +} + +/*********************************************/ +/* Comparison */ +/*********************************************/ + +int String::compareTo(const String &s) const +{ + if (!buffer || !s.buffer) { + if (s.buffer && s.len > 0) return 0 - *(unsigned char *)s.buffer; + if (buffer && len > 0) return *(unsigned char *)buffer; + return 0; + } + return strcmp(buffer, s.buffer); +} + +unsigned char String::equals(const String &s2) const +{ + return (len == s2.len && compareTo(s2) == 0); +} + +unsigned char String::equals(const char *cstr) const +{ + if (len == 0) return (cstr == NULL || *cstr == 0); + if (cstr == NULL) return buffer[0] == 0; + return strcmp(buffer, cstr) == 0; +} + +unsigned char String::operator<(const String &rhs) const +{ + return compareTo(rhs) < 0; +} + +unsigned char String::operator>(const String &rhs) const +{ + return compareTo(rhs) > 0; +} + +unsigned char String::operator<=(const String &rhs) const +{ + return compareTo(rhs) <= 0; +} + +unsigned char String::operator>=(const String &rhs) const +{ + return compareTo(rhs) >= 0; +} + +unsigned char String::equalsIgnoreCase( const String &s2 ) const +{ + if (this == &s2) return 1; + if (len != s2.len) return 0; + if (len == 0) return 1; + const char *p1 = buffer; + const char *p2 = s2.buffer; + while (*p1) { + if (tolower(*p1++) != tolower(*p2++)) return 0; + } + return 1; +} + +unsigned char String::startsWith( const String &s2 ) const +{ + if (len < s2.len) return 0; + return startsWith(s2, 0); +} + +unsigned char String::startsWith( const String &s2, unsigned int offset ) const +{ + if (offset > len - s2.len || !buffer || !s2.buffer) return 0; + return strncmp( &buffer[offset], s2.buffer, s2.len ) == 0; +} + +unsigned char String::endsWith( const String &s2 ) const +{ + if ( len < s2.len || !buffer || !s2.buffer) return 0; + return strcmp(&buffer[len - s2.len], s2.buffer) == 0; +} + +/*********************************************/ +/* Character Access */ +/*********************************************/ + +char String::charAt(unsigned int loc) const +{ + return operator[](loc); +} + +void String::setCharAt(unsigned int loc, char c) +{ + if (loc < len) buffer[loc] = c; +} + +char & String::operator[](unsigned int index) +{ + static char dummy_writable_char; + if (index >= len || !buffer) { + dummy_writable_char = 0; + return dummy_writable_char; + } + return buffer[index]; +} + +char String::operator[]( unsigned int index ) const +{ + if (index >= len || !buffer) return 0; + return buffer[index]; +} + +void String::getBytes(unsigned char *buf, unsigned int bufsize, unsigned int index) const +{ + if (!bufsize || !buf) return; + if (index >= len) { + buf[0] = 0; + return; + } + unsigned int n = bufsize - 1; + if (n > len - index) n = len - index; + strncpy((char *)buf, buffer + index, n); + buf[n] = 0; +} + +/*********************************************/ +/* Search */ +/*********************************************/ + +int String::indexOf(char c) const +{ + return indexOf(c, 0); +} + +int String::indexOf( char ch, unsigned int fromIndex ) const +{ + if (fromIndex >= len) return -1; + const char* temp = strchr(buffer + fromIndex, ch); + if (temp == NULL) return -1; + return temp - buffer; +} + +int String::indexOf(const String &s2) const +{ + return indexOf(s2, 0); +} + +int String::indexOf(const String &s2, unsigned int fromIndex) const +{ + if (fromIndex >= len) return -1; + const char *found = strstr(buffer + fromIndex, s2.buffer); + if (found == NULL) return -1; + return found - buffer; +} + +int String::lastIndexOf( char theChar ) const +{ + return lastIndexOf(theChar, len - 1); +} + +int String::lastIndexOf(char ch, int fromIndex) const +{ + if (fromIndex >= len || fromIndex < 0) return -1; + char tempchar = buffer[fromIndex + 1]; + buffer[fromIndex + 1] = '\0'; + char* temp = strrchr( buffer, ch ); + buffer[fromIndex + 1] = tempchar; + if (temp == NULL) return -1; + return temp - buffer; +} + +int String::lastIndexOf(const String &s2) const +{ + return lastIndexOf(s2, len - s2.len); +} + +int String::lastIndexOf(const String &s2, int fromIndex) const +{ + if (s2.len == 0 || len == 0 || s2.len > len || fromIndex < 0) return -1; + if (fromIndex >= len) fromIndex = len - 1; + int found = -1; + for (char *p = buffer; p <= buffer + fromIndex; p++) { + p = strstr(p, s2.buffer); + if (!p) break; + if (p - buffer <= fromIndex) found = p - buffer; + } + return found; +} + +String String::substring( unsigned int left ) const +{ + return substring(left, len); +} + +String String::substring(unsigned int left, unsigned int right) const +{ + if (left > right) { + unsigned int temp = right; + right = left; + left = temp; + } + String out; + if (left > len) return out; + if (right > len) right = len; + char temp = buffer[right]; // save the replaced character + buffer[right] = '\0'; + out = buffer + left; // pointer arithmetic + buffer[right] = temp; //restore character + return out; +} + +/*********************************************/ +/* Modification */ +/*********************************************/ + +void String::replace(char find, char replace) +{ + if (!buffer) return; + for (char *p = buffer; *p; p++) { + if (*p == find) *p = replace; + } +} + +void String::replace(const String& find, const String& replace) +{ + if (len == 0 || find.len == 0) return; + int diff = replace.len - find.len; + char *readFrom = buffer; + char *foundAt; + if (diff == 0) { + while ((foundAt = strstr(readFrom, find.buffer)) != NULL) { + memcpy(foundAt, replace.buffer, replace.len); + readFrom = foundAt + replace.len; + } + } else if (diff < 0) { + char *writeTo = buffer; + while ((foundAt = strstr(readFrom, find.buffer)) != NULL) { + unsigned int n = foundAt - readFrom; + memcpy(writeTo, readFrom, n); + writeTo += n; + memcpy(writeTo, replace.buffer, replace.len); + writeTo += replace.len; + readFrom = foundAt + find.len; + len += diff; + } + strcpy(writeTo, readFrom); + } else { + unsigned int size = len; // compute size needed for result + while ((foundAt = strstr(readFrom, find.buffer)) != NULL) { + readFrom = foundAt + find.len; + size += diff; + } + if (size == len) return; + if (size > capacity && !changeBuffer(size)) return; // XXX: tell user! + int index = len - 1; + while ((index = lastIndexOf(find, index)) >= 0) { + readFrom = buffer + index + find.len; + memmove(readFrom + diff, readFrom, len - (readFrom - buffer)); + len += diff; + buffer[len] = 0; + memcpy(buffer + index, replace.buffer, replace.len); + index--; + } + } +} + +void String::toLowerCase(void) +{ + if (!buffer) return; + for (char *p = buffer; *p; p++) { + *p = tolower(*p); + } +} + +void String::toUpperCase(void) +{ + if (!buffer) return; + for (char *p = buffer; *p; p++) { + *p = toupper(*p); + } +} + +void String::trim(void) +{ + if (!buffer || len == 0) return; + char *begin = buffer; + while (isspace(*begin)) begin++; + char *end = buffer + len - 1; + while (isspace(*end) && end >= begin) end--; + len = end + 1 - begin; + if (begin > buffer) memcpy(buffer, begin, len); + buffer[len] = 0; +} + +/*********************************************/ +/* Parsing / Conversion */ +/*********************************************/ + +long String::toInt(void) const +{ + if (buffer) return atol(buffer); + return 0; +} + + diff --git a/hardware/sam/cores/sam/WString.h b/hardware/sam/cores/sam/WString.h new file mode 100644 index 000000000..01f144ac6 --- /dev/null +++ b/hardware/sam/cores/sam/WString.h @@ -0,0 +1,204 @@ +/* + WString.h - String library for Wiring & Arduino + ...mostly rewritten by Paul Stoffregen... + Copyright (c) 2009-10 Hernando Barragan. All right reserved. + Copyright 2011, Paul Stoffregen, paul@pjrc.com + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef String_class_h +#define String_class_h +#ifdef __cplusplus + +#include +#include +#include + +// When compiling programs with this class, the following gcc parameters +// dramatically increase performance and memory (RAM) efficiency, typically +// with little or no increase in code size. +// -felide-constructors +// -std=c++0x + +class __FlashStringHelper; +#define F(string_literal) (reinterpret_cast<__FlashStringHelper *>(PSTR(string_literal))) + +// An inherited class for holding the result of a concatenation. These +// result objects are assumed to be writable by subsequent concatenations. +class StringSumHelper; + +// The string class +class String +{ + // use a function pointer to allow for "if (s)" without the + // complications of an operator bool(). for more information, see: + // http://www.artima.com/cppsource/safebool.html + typedef void (String::*StringIfHelperType)() const; + void StringIfHelper() const {} + +public: + // constructors + // creates a copy of the initial value. + // if the initial value is null or invalid, or if memory allocation + // fails, the string will be marked as invalid (i.e. "if (s)" will + // be false). + String(const char *cstr = ""); + String(const String &str); + #ifdef __GXX_EXPERIMENTAL_CXX0X__ + String(String &&rval); + String(StringSumHelper &&rval); + #endif + explicit String(char c); + explicit String(unsigned char, unsigned char base=10); + explicit String(int, unsigned char base=10); + explicit String(unsigned int, unsigned char base=10); + explicit String(long, unsigned char base=10); + explicit String(unsigned long, unsigned char base=10); + ~String(void); + + // memory management + // return true on success, false on failure (in which case, the string + // is left unchanged). reserve(0), if successful, will validate an + // invalid string (i.e., "if (s)" will be true afterwards) + unsigned char reserve(unsigned int size); + inline unsigned int length(void) const {return len;} + + // creates a copy of the assigned value. if the value is null or + // invalid, or if the memory allocation fails, the string will be + // marked as invalid ("if (s)" will be false). + String & operator = (const String &rhs); + String & operator = (const char *cstr); + #ifdef __GXX_EXPERIMENTAL_CXX0X__ + String & operator = (String &&rval); + String & operator = (StringSumHelper &&rval); + #endif + + // concatenate (works w/ built-in types) + + // returns true on success, false on failure (in which case, the string + // is left unchanged). if the argument is null or invalid, the + // concatenation is considered unsucessful. + unsigned char concat(const String &str); + unsigned char concat(const char *cstr); + unsigned char concat(char c); + unsigned char concat(unsigned char c); + unsigned char concat(int num); + unsigned char concat(unsigned int num); + unsigned char concat(long num); + unsigned char concat(unsigned long num); + + // if there's not enough memory for the concatenated value, the string + // will be left unchanged (but this isn't signalled in any way) + String & operator += (const String &rhs) {concat(rhs); return (*this);} + String & operator += (const char *cstr) {concat(cstr); return (*this);} + String & operator += (char c) {concat(c); return (*this);} + String & operator += (unsigned char num) {concat(num); return (*this);} + String & operator += (int num) {concat(num); return (*this);} + String & operator += (unsigned int num) {concat(num); return (*this);} + String & operator += (long num) {concat(num); return (*this);} + String & operator += (unsigned long num) {concat(num); return (*this);} + + friend StringSumHelper & operator + (const StringSumHelper &lhs, const String &rhs); + friend StringSumHelper & operator + (const StringSumHelper &lhs, const char *cstr); + friend StringSumHelper & operator + (const StringSumHelper &lhs, char c); + friend StringSumHelper & operator + (const StringSumHelper &lhs, unsigned char num); + friend StringSumHelper & operator + (const StringSumHelper &lhs, int num); + friend StringSumHelper & operator + (const StringSumHelper &lhs, unsigned int num); + friend StringSumHelper & operator + (const StringSumHelper &lhs, long num); + friend StringSumHelper & operator + (const StringSumHelper &lhs, unsigned long num); + + // comparison (only works w/ Strings and "strings") + operator StringIfHelperType() const { return buffer ? &String::StringIfHelper : 0; } + int compareTo(const String &s) const; + unsigned char equals(const String &s) const; + unsigned char equals(const char *cstr) const; + unsigned char operator == (const String &rhs) const {return equals(rhs);} + unsigned char operator == (const char *cstr) const {return equals(cstr);} + unsigned char operator != (const String &rhs) const {return !equals(rhs);} + unsigned char operator != (const char *cstr) const {return !equals(cstr);} + unsigned char operator < (const String &rhs) const; + unsigned char operator > (const String &rhs) const; + unsigned char operator <= (const String &rhs) const; + unsigned char operator >= (const String &rhs) const; + unsigned char equalsIgnoreCase(const String &s) const; + unsigned char startsWith( const String &prefix) const; + unsigned char startsWith(const String &prefix, unsigned int offset) const; + unsigned char endsWith(const String &suffix) const; + + // character acccess + char charAt(unsigned int index) const; + void setCharAt(unsigned int index, char c); + char operator [] (unsigned int index) const; + char& operator [] (unsigned int index); + void getBytes(unsigned char *buf, unsigned int bufsize, unsigned int index=0) const; + void toCharArray(char *buf, unsigned int bufsize, unsigned int index=0) const + {getBytes((unsigned char *)buf, bufsize, index);} + + // search + int indexOf( char ch ) const; + int indexOf( char ch, unsigned int fromIndex ) const; + int indexOf( const String &str ) const; + int indexOf( const String &str, unsigned int fromIndex ) const; + int lastIndexOf( char ch ) const; + int lastIndexOf( char ch, int fromIndex ) const; + int lastIndexOf( const String &str ) const; + int lastIndexOf( const String &str, int fromIndex ) const; + String substring( unsigned int beginIndex ) const; + String substring( unsigned int beginIndex, unsigned int endIndex ) const; + + // modification + void replace(char find, char replace); + void replace(const String& find, const String& replace); + void toLowerCase(void); + void toUpperCase(void); + void trim(void); + + // parsing/conversion + long toInt(void) const; + +protected: + char *buffer; // the actual char array + unsigned int capacity; // the array length minus one (for the '\0') + unsigned int len; // the String length (not counting the '\0') + unsigned char flags; // unused, for future features +protected: + void init(void); + void invalidate(void); + unsigned char changeBuffer(unsigned int maxStrLen); + unsigned char concat(const char *cstr, unsigned int length); + + // copy and move + String & copy(const char *cstr, unsigned int length); + #ifdef __GXX_EXPERIMENTAL_CXX0X__ + void move(String &rhs); + #endif +}; + +class StringSumHelper : public String +{ +public: + StringSumHelper(const String &s) : String(s) {} + StringSumHelper(const char *p) : String(p) {} + StringSumHelper(char c) : String(c) {} + StringSumHelper(unsigned char num) : String(num) {} + StringSumHelper(int num) : String(num) {} + StringSumHelper(unsigned int num) : String(num) {} + StringSumHelper(long num) : String(num) {} + StringSumHelper(unsigned long num) : String(num) {} +}; + +#endif // __cplusplus +#endif // String_class_h diff --git a/hardware/sam/cores/sam/binary.h b/hardware/sam/cores/sam/binary.h new file mode 100644 index 000000000..af1498033 --- /dev/null +++ b/hardware/sam/cores/sam/binary.h @@ -0,0 +1,515 @@ +#ifndef Binary_h +#define Binary_h + +#define B0 0 +#define B00 0 +#define B000 0 +#define B0000 0 +#define B00000 0 +#define B000000 0 +#define B0000000 0 +#define B00000000 0 +#define B1 1 +#define B01 1 +#define B001 1 +#define B0001 1 +#define B00001 1 +#define B000001 1 +#define B0000001 1 +#define B00000001 1 +#define B10 2 +#define B010 2 +#define B0010 2 +#define B00010 2 +#define B000010 2 +#define B0000010 2 +#define B00000010 2 +#define B11 3 +#define B011 3 +#define B0011 3 +#define B00011 3 +#define B000011 3 +#define B0000011 3 +#define B00000011 3 +#define B100 4 +#define B0100 4 +#define B00100 4 +#define B000100 4 +#define B0000100 4 +#define B00000100 4 +#define B101 5 +#define B0101 5 +#define B00101 5 +#define B000101 5 +#define B0000101 5 +#define B00000101 5 +#define B110 6 +#define B0110 6 +#define B00110 6 +#define B000110 6 +#define B0000110 6 +#define B00000110 6 +#define B111 7 +#define B0111 7 +#define B00111 7 +#define B000111 7 +#define B0000111 7 +#define B00000111 7 +#define B1000 8 +#define B01000 8 +#define B001000 8 +#define B0001000 8 +#define B00001000 8 +#define B1001 9 +#define B01001 9 +#define B001001 9 +#define B0001001 9 +#define B00001001 9 +#define B1010 10 +#define B01010 10 +#define B001010 10 +#define B0001010 10 +#define B00001010 10 +#define B1011 11 +#define B01011 11 +#define B001011 11 +#define B0001011 11 +#define B00001011 11 +#define B1100 12 +#define B01100 12 +#define B001100 12 +#define B0001100 12 +#define B00001100 12 +#define B1101 13 +#define B01101 13 +#define B001101 13 +#define B0001101 13 +#define B00001101 13 +#define B1110 14 +#define B01110 14 +#define B001110 14 +#define B0001110 14 +#define B00001110 14 +#define B1111 15 +#define B01111 15 +#define B001111 15 +#define B0001111 15 +#define B00001111 15 +#define B10000 16 +#define B010000 16 +#define B0010000 16 +#define B00010000 16 +#define B10001 17 +#define B010001 17 +#define B0010001 17 +#define B00010001 17 +#define B10010 18 +#define B010010 18 +#define B0010010 18 +#define B00010010 18 +#define B10011 19 +#define B010011 19 +#define B0010011 19 +#define B00010011 19 +#define B10100 20 +#define B010100 20 +#define B0010100 20 +#define B00010100 20 +#define B10101 21 +#define B010101 21 +#define B0010101 21 +#define B00010101 21 +#define B10110 22 +#define B010110 22 +#define B0010110 22 +#define B00010110 22 +#define B10111 23 +#define B010111 23 +#define B0010111 23 +#define B00010111 23 +#define B11000 24 +#define B011000 24 +#define B0011000 24 +#define B00011000 24 +#define B11001 25 +#define B011001 25 +#define B0011001 25 +#define B00011001 25 +#define B11010 26 +#define B011010 26 +#define B0011010 26 +#define B00011010 26 +#define B11011 27 +#define B011011 27 +#define B0011011 27 +#define B00011011 27 +#define B11100 28 +#define B011100 28 +#define B0011100 28 +#define B00011100 28 +#define B11101 29 +#define B011101 29 +#define B0011101 29 +#define B00011101 29 +#define B11110 30 +#define B011110 30 +#define B0011110 30 +#define B00011110 30 +#define B11111 31 +#define B011111 31 +#define B0011111 31 +#define B00011111 31 +#define B100000 32 +#define B0100000 32 +#define B00100000 32 +#define B100001 33 +#define B0100001 33 +#define B00100001 33 +#define B100010 34 +#define B0100010 34 +#define B00100010 34 +#define B100011 35 +#define B0100011 35 +#define B00100011 35 +#define B100100 36 +#define B0100100 36 +#define B00100100 36 +#define B100101 37 +#define B0100101 37 +#define B00100101 37 +#define B100110 38 +#define B0100110 38 +#define B00100110 38 +#define B100111 39 +#define B0100111 39 +#define B00100111 39 +#define B101000 40 +#define B0101000 40 +#define B00101000 40 +#define B101001 41 +#define B0101001 41 +#define B00101001 41 +#define B101010 42 +#define B0101010 42 +#define B00101010 42 +#define B101011 43 +#define B0101011 43 +#define B00101011 43 +#define B101100 44 +#define B0101100 44 +#define B00101100 44 +#define B101101 45 +#define B0101101 45 +#define B00101101 45 +#define B101110 46 +#define B0101110 46 +#define B00101110 46 +#define B101111 47 +#define B0101111 47 +#define B00101111 47 +#define B110000 48 +#define B0110000 48 +#define B00110000 48 +#define B110001 49 +#define B0110001 49 +#define B00110001 49 +#define B110010 50 +#define B0110010 50 +#define B00110010 50 +#define B110011 51 +#define B0110011 51 +#define B00110011 51 +#define B110100 52 +#define B0110100 52 +#define B00110100 52 +#define B110101 53 +#define B0110101 53 +#define B00110101 53 +#define B110110 54 +#define B0110110 54 +#define B00110110 54 +#define B110111 55 +#define B0110111 55 +#define B00110111 55 +#define B111000 56 +#define B0111000 56 +#define B00111000 56 +#define B111001 57 +#define B0111001 57 +#define B00111001 57 +#define B111010 58 +#define B0111010 58 +#define B00111010 58 +#define B111011 59 +#define B0111011 59 +#define B00111011 59 +#define B111100 60 +#define B0111100 60 +#define B00111100 60 +#define B111101 61 +#define B0111101 61 +#define B00111101 61 +#define B111110 62 +#define B0111110 62 +#define B00111110 62 +#define B111111 63 +#define B0111111 63 +#define B00111111 63 +#define B1000000 64 +#define B01000000 64 +#define B1000001 65 +#define B01000001 65 +#define B1000010 66 +#define B01000010 66 +#define B1000011 67 +#define B01000011 67 +#define B1000100 68 +#define B01000100 68 +#define B1000101 69 +#define B01000101 69 +#define B1000110 70 +#define B01000110 70 +#define B1000111 71 +#define B01000111 71 +#define B1001000 72 +#define B01001000 72 +#define B1001001 73 +#define B01001001 73 +#define B1001010 74 +#define B01001010 74 +#define B1001011 75 +#define B01001011 75 +#define B1001100 76 +#define B01001100 76 +#define B1001101 77 +#define B01001101 77 +#define B1001110 78 +#define B01001110 78 +#define B1001111 79 +#define B01001111 79 +#define B1010000 80 +#define B01010000 80 +#define B1010001 81 +#define B01010001 81 +#define B1010010 82 +#define B01010010 82 +#define B1010011 83 +#define B01010011 83 +#define B1010100 84 +#define B01010100 84 +#define B1010101 85 +#define B01010101 85 +#define B1010110 86 +#define B01010110 86 +#define B1010111 87 +#define B01010111 87 +#define B1011000 88 +#define B01011000 88 +#define B1011001 89 +#define B01011001 89 +#define B1011010 90 +#define B01011010 90 +#define B1011011 91 +#define B01011011 91 +#define B1011100 92 +#define B01011100 92 +#define B1011101 93 +#define B01011101 93 +#define B1011110 94 +#define B01011110 94 +#define B1011111 95 +#define B01011111 95 +#define B1100000 96 +#define B01100000 96 +#define B1100001 97 +#define B01100001 97 +#define B1100010 98 +#define B01100010 98 +#define B1100011 99 +#define B01100011 99 +#define B1100100 100 +#define B01100100 100 +#define B1100101 101 +#define B01100101 101 +#define B1100110 102 +#define B01100110 102 +#define B1100111 103 +#define B01100111 103 +#define B1101000 104 +#define B01101000 104 +#define B1101001 105 +#define B01101001 105 +#define B1101010 106 +#define B01101010 106 +#define B1101011 107 +#define B01101011 107 +#define B1101100 108 +#define B01101100 108 +#define B1101101 109 +#define B01101101 109 +#define B1101110 110 +#define B01101110 110 +#define B1101111 111 +#define B01101111 111 +#define B1110000 112 +#define B01110000 112 +#define B1110001 113 +#define B01110001 113 +#define B1110010 114 +#define B01110010 114 +#define B1110011 115 +#define B01110011 115 +#define B1110100 116 +#define B01110100 116 +#define B1110101 117 +#define B01110101 117 +#define B1110110 118 +#define B01110110 118 +#define B1110111 119 +#define B01110111 119 +#define B1111000 120 +#define B01111000 120 +#define B1111001 121 +#define B01111001 121 +#define B1111010 122 +#define B01111010 122 +#define B1111011 123 +#define B01111011 123 +#define B1111100 124 +#define B01111100 124 +#define B1111101 125 +#define B01111101 125 +#define B1111110 126 +#define B01111110 126 +#define B1111111 127 +#define B01111111 127 +#define B10000000 128 +#define B10000001 129 +#define B10000010 130 +#define B10000011 131 +#define B10000100 132 +#define B10000101 133 +#define B10000110 134 +#define B10000111 135 +#define B10001000 136 +#define B10001001 137 +#define B10001010 138 +#define B10001011 139 +#define B10001100 140 +#define B10001101 141 +#define B10001110 142 +#define B10001111 143 +#define B10010000 144 +#define B10010001 145 +#define B10010010 146 +#define B10010011 147 +#define B10010100 148 +#define B10010101 149 +#define B10010110 150 +#define B10010111 151 +#define B10011000 152 +#define B10011001 153 +#define B10011010 154 +#define B10011011 155 +#define B10011100 156 +#define B10011101 157 +#define B10011110 158 +#define B10011111 159 +#define B10100000 160 +#define B10100001 161 +#define B10100010 162 +#define B10100011 163 +#define B10100100 164 +#define B10100101 165 +#define B10100110 166 +#define B10100111 167 +#define B10101000 168 +#define B10101001 169 +#define B10101010 170 +#define B10101011 171 +#define B10101100 172 +#define B10101101 173 +#define B10101110 174 +#define B10101111 175 +#define B10110000 176 +#define B10110001 177 +#define B10110010 178 +#define B10110011 179 +#define B10110100 180 +#define B10110101 181 +#define B10110110 182 +#define B10110111 183 +#define B10111000 184 +#define B10111001 185 +#define B10111010 186 +#define B10111011 187 +#define B10111100 188 +#define B10111101 189 +#define B10111110 190 +#define B10111111 191 +#define B11000000 192 +#define B11000001 193 +#define B11000010 194 +#define B11000011 195 +#define B11000100 196 +#define B11000101 197 +#define B11000110 198 +#define B11000111 199 +#define B11001000 200 +#define B11001001 201 +#define B11001010 202 +#define B11001011 203 +#define B11001100 204 +#define B11001101 205 +#define B11001110 206 +#define B11001111 207 +#define B11010000 208 +#define B11010001 209 +#define B11010010 210 +#define B11010011 211 +#define B11010100 212 +#define B11010101 213 +#define B11010110 214 +#define B11010111 215 +#define B11011000 216 +#define B11011001 217 +#define B11011010 218 +#define B11011011 219 +#define B11011100 220 +#define B11011101 221 +#define B11011110 222 +#define B11011111 223 +#define B11100000 224 +#define B11100001 225 +#define B11100010 226 +#define B11100011 227 +#define B11100100 228 +#define B11100101 229 +#define B11100110 230 +#define B11100111 231 +#define B11101000 232 +#define B11101001 233 +#define B11101010 234 +#define B11101011 235 +#define B11101100 236 +#define B11101101 237 +#define B11101110 238 +#define B11101111 239 +#define B11110000 240 +#define B11110001 241 +#define B11110010 242 +#define B11110011 243 +#define B11110100 244 +#define B11110101 245 +#define B11110110 246 +#define B11110111 247 +#define B11111000 248 +#define B11111001 249 +#define B11111010 250 +#define B11111011 251 +#define B11111100 252 +#define B11111101 253 +#define B11111110 254 +#define B11111111 255 + +#endif diff --git a/hardware/sam/cores/sam/build_gcc/Makefile b/hardware/sam/cores/sam/build_gcc/Makefile new file mode 100644 index 000000000..4943a9b93 --- /dev/null +++ b/hardware/sam/cores/sam/build_gcc/Makefile @@ -0,0 +1,46 @@ +ifeq ("$(VARIANTS)", "") +VARIANTS = sam3s_ek sam3u_ek arduino_due +#VARIANTS = sam3u_ek +endif + +SUBMAKE_OPTIONS=--no-builtin-rules --no-builtin-variables + +#------------------------------------------------------------------------------- +# Rules +#------------------------------------------------------------------------------- + +all: $(VARIANTS) + +.PHONY: sam3s_ek +sam3s_ek: + @echo --- Making sam3s_ek + @$(MAKE) DEBUG=1 $(SUBMAKE_OPTIONS) -f libarduino_sam3s_ek.mk +# @$(MAKE) $(SUBMAKE_OPTIONS) -f libarduino_sam3s_ek.mk + +.PHONY: sam3u_ek +sam3u_ek: + @echo --- Making sam3u_ek + @$(MAKE) DEBUG=1 $(SUBMAKE_OPTIONS) -f libarduino_sam3u_ek.mk +# @$(MAKE) $(SUBMAKE_OPTIONS) -f libarduino_sam3u_ek.mk + +.PHONY: arduino_due +arduino_due: + @echo --- Making arduino_due + @$(MAKE) DEBUG=1 $(SUBMAKE_OPTIONS) -f libarduino_arduino_due.mk +# @$(MAKE) $(SUBMAKE_OPTIONS) -f libarduino_arduino_due.mk + +.PHONY: clean +clean: + @echo --- Cleaning sam3s_ek + @$(MAKE) DEBUG=1 $(SUBMAKE_OPTIONS) -f libarduino_sam3s_ek.mk $@ +# @$(MAKE) $(SUBMAKE_OPTIONS) -f libarduino_sam3s_ek.mk $@ + + @echo --- Cleaning sam3u_ek + @$(MAKE) DEBUG=1 $(SUBMAKE_OPTIONS) -f libarduino_sam3u_ek.mk $@ +# @$(MAKE) $(SUBMAKE_OPTIONS) -f libarduino_sam3u_ek.mk $@ + + @echo --- Cleaning arduino_due + @$(MAKE) DEBUG=1 $(SUBMAKE_OPTIONS) -f libarduino_arduino_due.mk $@ +# @$(MAKE) $(SUBMAKE_OPTIONS) -f libarduino_arduino_due.mk $@ + + diff --git a/hardware/sam/cores/sam/build_gcc/debug.mk b/hardware/sam/cores/sam/build_gcc/debug.mk new file mode 100644 index 000000000..3ab3f8066 --- /dev/null +++ b/hardware/sam/cores/sam/build_gcc/debug.mk @@ -0,0 +1,7 @@ +# Optimization level +# -O1 Optimize +# -O2 Optimize even more +# -O3 Optimize yet more +# -O0 Reduce compilation time and make debugging produce the expected results +# -Os Optimize for size +OPTIMIZATION = -g -O0 -DDEBUG diff --git a/hardware/sam/cores/sam/build_gcc/gcc.mk b/hardware/sam/cores/sam/build_gcc/gcc.mk new file mode 100644 index 000000000..e7436816e --- /dev/null +++ b/hardware/sam/cores/sam/build_gcc/gcc.mk @@ -0,0 +1,66 @@ + +# Tool suffix when cross-compiling +#CROSS_COMPILE = ../../../../tools/CodeSourcery_arm/bin/arm-none-eabi- +#CROSS_COMPILE = C:/CodeSourcery_2011.03-42/bin/arm-none-eabi- +CROSS_COMPILE = $(ARM_GCC_TOOLCHAIN)/arm-none-eabi- + +# Compilation tools +AR = $(CROSS_COMPILE)ar +CC = $(CROSS_COMPILE)gcc +CXX = $(CROSS_COMPILE)g++ +AS = $(CROSS_COMPILE)as +#LD = $(CROSS_COMPILE)ld +#SIZE = $(CROSS_COMPILE)size +NM = $(CROSS_COMPILE)nm +#OBJCOPY = $(CROSS_COMPILE)objcopy +RM=cs-rm -Rf +SEP=\\ + +# --------------------------------------------------------------------------------------- +# C Flags + +CFLAGS += -Wall -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int +CFLAGS += -Werror-implicit-function-declaration -Wmain -Wparentheses +CFLAGS += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused +CFLAGS += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef +CFLAGS += -Wshadow -Wpointer-arith -Wbad-function-cast -Wwrite-strings +CFLAGS += -Wsign-compare -Waggregate-return -Wstrict-prototypes +CFLAGS += -Wmissing-prototypes -Wmissing-declarations +CFLAGS += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations +CFLAGS += -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long +CFLAGS += -Wunreachable-code +CFLAGS += -Wcast-align +#CFLAGS += -Wmissing-noreturn +#CFLAGS += -Wconversion + +CFLAGS += --param max-inline-insns-single=500 -mcpu=cortex-m3 -mthumb -mlong-calls -ffunction-sections -nostdlib +CFLAGS += $(OPTIMIZATION) $(INCLUDES) -D$(CHIP) -D$(VARIANT) + +# To reduce application size use only integer printf function. +CFLAGS += -Dprintf=iprintf + +# --------------------------------------------------------------------------------------- +# CPP Flags + +CPPFLAGS += -Wall -Wchar-subscripts -Wcomment -Wformat=2 +CPPFLAGS += -Wmain -Wparentheses -Wcast-align -Wunreachable-code +CPPFLAGS += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused +CPPFLAGS += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef +CPPFLAGS += -Wshadow -Wpointer-arith -Wwrite-strings +CPPFLAGS += -Wsign-compare -Waggregate-return -Wmissing-declarations +CPPFLAGS += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations +CPPFLAGS += -Wpacked -Wredundant-decls -Winline -Wlong-long +#CPPFLAGS += -Wmissing-noreturn +#CPPFLAGS += -Wconversion + +#-fno-rtti -fno-exceptions +CPPFLAGS += --param max-inline-insns-single=500 -mcpu=cortex-m3 -mthumb -mlong-calls -ffunction-sections +CPPFLAGS += $(OPTIMIZATION) $(INCLUDES) -D$(CHIP) + +# To reduce application size use only integer printf function. +CPPFLAGS += -Dprintf=iprintf + +# --------------------------------------------------------------------------------------- +# ASM Flags + +ASFLAGS = -mcpu=cortex-m3 -mthumb -Wall -g $(OPTIMIZATION) $(INCLUDES) diff --git a/hardware/sam/cores/sam/build_gcc/libarduino_arduino_due.mk b/hardware/sam/cores/sam/build_gcc/libarduino_arduino_due.mk new file mode 100644 index 000000000..645f794f9 --- /dev/null +++ b/hardware/sam/cores/sam/build_gcc/libarduino_arduino_due.mk @@ -0,0 +1,152 @@ +# Makefile for compiling libArduino +.SUFFIXES: .o .a .c .s + +CHIP=__SAM3U4E__ +VARIANT=arduino_due +LIBNAME=libarduino_$(VARIANT) +TOOLCHAIN=gcc + +#------------------------------------------------------------------------------- +# Path +#------------------------------------------------------------------------------- + +# Output directories +#OUTPUT_BIN = ../lib +OUTPUT_BIN = .. + +# Libraries +PROJECT_BASE_PATH = .. +SYSTEM_PATH = ../../../system +CMSIS_PATH = $(SYSTEM_PATH)/CMSIS/Include +VARIANT_PATH = ../../../variants/$(VARIANT) + +#------------------------------------------------------------------------------- +# Files +#------------------------------------------------------------------------------- + +vpath %.h $(PROJECT_BASE_PATH) $(SYSTEM_PATH) $(VARIANT_PATH) +vpath %.c $(PROJECT_BASE_PATH) $(VARIANT_PATH) +vpath %.cpp $(PROJECT_BASE_PATH) $(PROJECT_BASE_PATH) + +VPATH+=$(PROJECT_BASE_PATH) + +INCLUDES = +INCLUDES += -I$(PROJECT_BASE_PATH) +INCLUDES += -I$(SYSTEM_PATH) +INCLUDES += -I$(SYSTEM_PATH)/libsam +INCLUDES += -I$(VARIANT_PATH) +INCLUDES += -I$(CMSIS_PATH) + +#------------------------------------------------------------------------------- +ifdef DEBUG +include debug.mk +else +include release.mk +endif + +#------------------------------------------------------------------------------- +# Tools +#------------------------------------------------------------------------------- + +include $(TOOLCHAIN).mk + +#------------------------------------------------------------------------------- +ifdef DEBUG +OUTPUT_OBJ=debug +OUTPUT_LIB=$(LIBNAME)_$(TOOLCHAIN)_dbg.a +else +OUTPUT_OBJ=release +OUTPUT_LIB=$(LIBNAME)_$(TOOLCHAIN)_rel.a +endif + +OUTPUT_PATH=$(OUTPUT_OBJ)_$(VARIANT) + +#------------------------------------------------------------------------------- +# C source files and objects +#------------------------------------------------------------------------------- +C_SRC=$(wildcard $(PROJECT_BASE_PATH)/*.c) + +C_OBJ_TEMP = $(patsubst %.c, %.o, $(notdir $(C_SRC))) + +# during development, remove some files +C_OBJ_FILTER=dlib_lowlevel_sam3.o + +C_OBJ=$(filter-out $(C_OBJ_FILTER), $(C_OBJ_TEMP)) + +#------------------------------------------------------------------------------- +# CPP source files and objects +#------------------------------------------------------------------------------- +CPP_SRC=$(wildcard $(PROJECT_BASE_PATH)/*.cpp) + +CPP_OBJ_TEMP = $(patsubst %.cpp, %.o, $(notdir $(CPP_SRC))) + +# during development, remove some files +CPP_OBJ_FILTER= + +CPP_OBJ=$(filter-out $(CPP_OBJ_FILTER), $(CPP_OBJ_TEMP)) + +#------------------------------------------------------------------------------- +# Assembler source files and objects +#------------------------------------------------------------------------------- +A_SRC=$(wildcard $(PROJECT_BASE_PATH)/*.s) + +A_OBJ_TEMP=$(patsubst %.s, %.o, $(notdir $(A_SRC))) + +# during development, remove some files +A_OBJ_FILTER= + +A_OBJ=$(filter-out $(A_OBJ_FILTER), $(A_OBJ_TEMP)) + +#------------------------------------------------------------------------------- +# Rules +#------------------------------------------------------------------------------- +all: $(VARIANT) + +$(VARIANT): create_output $(OUTPUT_LIB) + +.PHONY: create_output +create_output: + @echo --- Preparing $(VARIANT) files in $(OUTPUT_PATH) $(OUTPUT_BIN) + @echo ------------------------- + @echo *$(INCLUDES) + @echo ------------------------- + @echo *$(C_SRC) + @echo ------------------------- + @echo *$(C_OBJ) + @echo ------------------------- + @echo *$(addprefix $(OUTPUT_PATH)/, $(C_OBJ)) + @echo ------------------------- + @echo *$(CPP_SRC) + @echo ------------------------- + @echo *$(CPP_OBJ) + @echo ------------------------- + @echo *$(addprefix $(OUTPUT_PATH)/, $(CPP_OBJ)) + @echo ------------------------- + @echo *$(A_SRC) + @echo ------------------------- + +# -@mkdir $(subst /,$(SEP),$(OUTPUT_BIN)) 1>NUL 2>&1 + -mkdir $(subst /,$(SEP),$(OUTPUT_BIN)) + -@mkdir $(OUTPUT_PATH) 1>NUL 2>&1 + +$(addprefix $(OUTPUT_PATH)/,$(C_OBJ)): $(OUTPUT_PATH)/%.o: %.c +# @$(CC) -v -c $(CFLAGS) $< -o $@ + @$(CC) -c $(CFLAGS) $< -o $@ + +$(addprefix $(OUTPUT_PATH)/,$(CPP_OBJ)): $(OUTPUT_PATH)/%.o: %.cpp +# @$(CC) -c $(CPPFLAGS) $< -o $@ + @$(CC) -xc++ -c $(CPPFLAGS) $< -o $@ + +$(addprefix $(OUTPUT_PATH)/,$(A_OBJ)): $(OUTPUT_PATH)/%.o: %.s + @$(AS) -c $(ASFLAGS) $< -o $@ + +$(OUTPUT_LIB): $(addprefix $(OUTPUT_PATH)/, $(C_OBJ)) $(addprefix $(OUTPUT_PATH)/, $(CPP_OBJ)) $(addprefix $(OUTPUT_PATH)/, $(A_OBJ)) + @$(AR) -v -r "$(OUTPUT_BIN)/$@" $^ + @$(NM) "$(OUTPUT_BIN)/$@" > "$(OUTPUT_BIN)/$@.txt" + + +.PHONY: clean +clean: + @echo --- Cleaning $(VARIANT) files [$(OUTPUT_PATH)$(SEP)*.o] + -@$(RM) $(OUTPUT_PATH) 1>NUL 2>&1 + -@$(RM) $(OUTPUT_BIN)/$(OUTPUT_LIB) 1>NUL 2>&1 diff --git a/hardware/sam/cores/sam/build_gcc/libarduino_sam3s_ek.mk b/hardware/sam/cores/sam/build_gcc/libarduino_sam3s_ek.mk new file mode 100644 index 000000000..c2547027c --- /dev/null +++ b/hardware/sam/cores/sam/build_gcc/libarduino_sam3s_ek.mk @@ -0,0 +1,152 @@ +# Makefile for compiling libArduino +.SUFFIXES: .o .a .c .s + +CHIP=__SAM3S4C__ +VARIANT=sam3s_ek +LIBNAME=libarduino_$(VARIANT) +TOOLCHAIN=gcc + +#------------------------------------------------------------------------------- +# Path +#------------------------------------------------------------------------------- + +# Output directories +#OUTPUT_BIN = ../lib +OUTPUT_BIN = .. + +# Libraries +PROJECT_BASE_PATH = .. +SYSTEM_PATH = ../../../system +CMSIS_PATH = $(SYSTEM_PATH)/CMSIS/Include +VARIANT_PATH = ../../../variants/$(VARIANT) + +#------------------------------------------------------------------------------- +# Files +#------------------------------------------------------------------------------- + +vpath %.h $(PROJECT_BASE_PATH) $(SYSTEM_PATH) $(VARIANT_PATH) +vpath %.c $(PROJECT_BASE_PATH) $(VARIANT_PATH) +vpath %.cpp $(PROJECT_BASE_PATH) $(PROJECT_BASE_PATH) + +VPATH+=$(PROJECT_BASE_PATH) + +INCLUDES = +INCLUDES += -I$(PROJECT_BASE_PATH) +INCLUDES += -I$(SYSTEM_PATH) +INCLUDES += -I$(SYSTEM_PATH)/libsam +INCLUDES += -I$(VARIANT_PATH) +INCLUDES += -I$(CMSIS_PATH) + +#------------------------------------------------------------------------------- +ifdef DEBUG +include debug.mk +else +include release.mk +endif + +#------------------------------------------------------------------------------- +# Tools +#------------------------------------------------------------------------------- + +include $(TOOLCHAIN).mk + +#------------------------------------------------------------------------------- +ifdef DEBUG +OUTPUT_OBJ=debug +OUTPUT_LIB=$(LIBNAME)_$(TOOLCHAIN)_dbg.a +else +OUTPUT_OBJ=release +OUTPUT_LIB=$(LIBNAME)_$(TOOLCHAIN)_rel.a +endif + +OUTPUT_PATH=$(OUTPUT_OBJ)_$(VARIANT) + +#------------------------------------------------------------------------------- +# C source files and objects +#------------------------------------------------------------------------------- +C_SRC=$(wildcard $(PROJECT_BASE_PATH)/*.c) + +C_OBJ_TEMP = $(patsubst %.c, %.o, $(notdir $(C_SRC))) + +# during development, remove some files +C_OBJ_FILTER=dlib_lowlevel_sam3.o + +C_OBJ=$(filter-out $(C_OBJ_FILTER), $(C_OBJ_TEMP)) + +#------------------------------------------------------------------------------- +# CPP source files and objects +#------------------------------------------------------------------------------- +CPP_SRC=$(wildcard $(PROJECT_BASE_PATH)/*.cpp) + +CPP_OBJ_TEMP = $(patsubst %.cpp, %.o, $(notdir $(CPP_SRC))) + +# during development, remove some files +CPP_OBJ_FILTER= + +CPP_OBJ=$(filter-out $(CPP_OBJ_FILTER), $(CPP_OBJ_TEMP)) + +#------------------------------------------------------------------------------- +# Assembler source files and objects +#------------------------------------------------------------------------------- +A_SRC=$(wildcard $(PROJECT_BASE_PATH)/*.s) + +A_OBJ_TEMP=$(patsubst %.s, %.o, $(notdir $(A_SRC))) + +# during development, remove some files +A_OBJ_FILTER= + +A_OBJ=$(filter-out $(A_OBJ_FILTER), $(A_OBJ_TEMP)) + +#------------------------------------------------------------------------------- +# Rules +#------------------------------------------------------------------------------- +all: $(VARIANT) + +$(VARIANT): create_output $(OUTPUT_LIB) + +.PHONY: create_output +create_output: + @echo --- Preparing $(VARIANT) files in $(OUTPUT_PATH) $(OUTPUT_BIN) + @echo ------------------------- + @echo *$(INCLUDES) + @echo ------------------------- + @echo *$(C_SRC) + @echo ------------------------- + @echo *$(C_OBJ) + @echo ------------------------- + @echo *$(addprefix $(OUTPUT_PATH)/, $(C_OBJ)) + @echo ------------------------- + @echo *$(CPP_SRC) + @echo ------------------------- + @echo *$(CPP_OBJ) + @echo ------------------------- + @echo *$(addprefix $(OUTPUT_PATH)/, $(CPP_OBJ)) + @echo ------------------------- + @echo *$(A_SRC) + @echo ------------------------- + +# -@mkdir $(subst /,$(SEP),$(OUTPUT_BIN)) 1>NUL 2>&1 + -mkdir $(subst /,$(SEP),$(OUTPUT_BIN)) + -@mkdir $(OUTPUT_PATH) 1>NUL 2>&1 + +$(addprefix $(OUTPUT_PATH)/,$(C_OBJ)): $(OUTPUT_PATH)/%.o: %.c +# @$(CC) -v -c $(CFLAGS) $< -o $@ + @$(CC) -c $(CFLAGS) $< -o $@ + +$(addprefix $(OUTPUT_PATH)/,$(CPP_OBJ)): $(OUTPUT_PATH)/%.o: %.cpp +# @$(CC) -c $(CPPFLAGS) $< -o $@ + @$(CC) -xc++ -c $(CPPFLAGS) $< -o $@ + +$(addprefix $(OUTPUT_PATH)/,$(A_OBJ)): $(OUTPUT_PATH)/%.o: %.s + @$(AS) -c $(ASFLAGS) $< -o $@ + +$(OUTPUT_LIB): $(addprefix $(OUTPUT_PATH)/, $(C_OBJ)) $(addprefix $(OUTPUT_PATH)/, $(CPP_OBJ)) $(addprefix $(OUTPUT_PATH)/, $(A_OBJ)) + @$(AR) -v -r "$(OUTPUT_BIN)/$@" $^ + @$(NM) "$(OUTPUT_BIN)/$@" > "$(OUTPUT_BIN)/$@.txt" + + +.PHONY: clean +clean: + @echo --- Cleaning $(VARIANT) files [$(OUTPUT_PATH)$(SEP)*.o] + -@$(RM) $(OUTPUT_PATH) 1>NUL 2>&1 + -@$(RM) $(OUTPUT_BIN)/$(OUTPUT_LIB) 1>NUL 2>&1 diff --git a/hardware/sam/cores/sam/build_gcc/libarduino_sam3u_ek.mk b/hardware/sam/cores/sam/build_gcc/libarduino_sam3u_ek.mk new file mode 100644 index 000000000..46c101a35 --- /dev/null +++ b/hardware/sam/cores/sam/build_gcc/libarduino_sam3u_ek.mk @@ -0,0 +1,152 @@ +# Makefile for compiling libArduino +.SUFFIXES: .o .a .c .s + +CHIP=__SAM3U4E__ +VARIANT=sam3u_ek +LIBNAME=libarduino_$(VARIANT) +TOOLCHAIN=gcc + +#------------------------------------------------------------------------------- +# Path +#------------------------------------------------------------------------------- + +# Output directories +#OUTPUT_BIN = ../lib +OUTPUT_BIN = .. + +# Libraries +PROJECT_BASE_PATH = .. +SYSTEM_PATH = ../../../system +CMSIS_PATH = $(SYSTEM_PATH)/CMSIS/Include +VARIANT_PATH = ../../../variants/$(VARIANT) + +#------------------------------------------------------------------------------- +# Files +#------------------------------------------------------------------------------- + +vpath %.h $(PROJECT_BASE_PATH) $(SYSTEM_PATH) $(VARIANT_PATH) +vpath %.c $(PROJECT_BASE_PATH) $(VARIANT_PATH) +vpath %.cpp $(PROJECT_BASE_PATH) $(PROJECT_BASE_PATH) + +VPATH+=$(PROJECT_BASE_PATH) + +INCLUDES = +INCLUDES += -I$(PROJECT_BASE_PATH) +INCLUDES += -I$(SYSTEM_PATH) +INCLUDES += -I$(SYSTEM_PATH)/libsam +INCLUDES += -I$(VARIANT_PATH) +INCLUDES += -I$(CMSIS_PATH) + +#------------------------------------------------------------------------------- +ifdef DEBUG +include debug.mk +else +include release.mk +endif + +#------------------------------------------------------------------------------- +# Tools +#------------------------------------------------------------------------------- + +include $(TOOLCHAIN).mk + +#------------------------------------------------------------------------------- +ifdef DEBUG +OUTPUT_OBJ=debug +OUTPUT_LIB=$(LIBNAME)_$(TOOLCHAIN)_dbg.a +else +OUTPUT_OBJ=release +OUTPUT_LIB=$(LIBNAME)_$(TOOLCHAIN)_rel.a +endif + +OUTPUT_PATH=$(OUTPUT_OBJ)_$(VARIANT) + +#------------------------------------------------------------------------------- +# C source files and objects +#------------------------------------------------------------------------------- +C_SRC=$(wildcard $(PROJECT_BASE_PATH)/*.c) + +C_OBJ_TEMP = $(patsubst %.c, %.o, $(notdir $(C_SRC))) + +# during development, remove some files +C_OBJ_FILTER=dlib_lowlevel_sam3.o + +C_OBJ=$(filter-out $(C_OBJ_FILTER), $(C_OBJ_TEMP)) + +#------------------------------------------------------------------------------- +# CPP source files and objects +#------------------------------------------------------------------------------- +CPP_SRC=$(wildcard $(PROJECT_BASE_PATH)/*.cpp) + +CPP_OBJ_TEMP = $(patsubst %.cpp, %.o, $(notdir $(CPP_SRC))) + +# during development, remove some files +CPP_OBJ_FILTER= + +CPP_OBJ=$(filter-out $(CPP_OBJ_FILTER), $(CPP_OBJ_TEMP)) + +#------------------------------------------------------------------------------- +# Assembler source files and objects +#------------------------------------------------------------------------------- +A_SRC=$(wildcard $(PROJECT_BASE_PATH)/*.s) + +A_OBJ_TEMP=$(patsubst %.s, %.o, $(notdir $(A_SRC))) + +# during development, remove some files +A_OBJ_FILTER= + +A_OBJ=$(filter-out $(A_OBJ_FILTER), $(A_OBJ_TEMP)) + +#------------------------------------------------------------------------------- +# Rules +#------------------------------------------------------------------------------- +all: $(VARIANT) + +$(VARIANT): create_output $(OUTPUT_LIB) + +.PHONY: create_output +create_output: + @echo --- Preparing $(VARIANT) files in $(OUTPUT_PATH) $(OUTPUT_BIN) + @echo ------------------------- + @echo *$(INCLUDES) + @echo ------------------------- + @echo *$(C_SRC) + @echo ------------------------- + @echo *$(C_OBJ) + @echo ------------------------- + @echo *$(addprefix $(OUTPUT_PATH)/, $(C_OBJ)) + @echo ------------------------- + @echo *$(CPP_SRC) + @echo ------------------------- + @echo *$(CPP_OBJ) + @echo ------------------------- + @echo *$(addprefix $(OUTPUT_PATH)/, $(CPP_OBJ)) + @echo ------------------------- + @echo *$(A_SRC) + @echo ------------------------- + +# -@mkdir $(subst /,$(SEP),$(OUTPUT_BIN)) 1>NUL 2>&1 + -mkdir $(subst /,$(SEP),$(OUTPUT_BIN)) + -@mkdir $(OUTPUT_PATH) 1>NUL 2>&1 + +$(addprefix $(OUTPUT_PATH)/,$(C_OBJ)): $(OUTPUT_PATH)/%.o: %.c +# @$(CC) -v -c $(CFLAGS) $< -o $@ + @$(CC) -c $(CFLAGS) $< -o $@ + +$(addprefix $(OUTPUT_PATH)/,$(CPP_OBJ)): $(OUTPUT_PATH)/%.o: %.cpp +# @$(CC) -c $(CPPFLAGS) $< -o $@ + @$(CC) -xc++ -c $(CPPFLAGS) $< -o $@ + +$(addprefix $(OUTPUT_PATH)/,$(A_OBJ)): $(OUTPUT_PATH)/%.o: %.s + @$(AS) -c $(ASFLAGS) $< -o $@ + +$(OUTPUT_LIB): $(addprefix $(OUTPUT_PATH)/, $(C_OBJ)) $(addprefix $(OUTPUT_PATH)/, $(CPP_OBJ)) $(addprefix $(OUTPUT_PATH)/, $(A_OBJ)) + @$(AR) -v -r "$(OUTPUT_BIN)/$@" $^ + @$(NM) "$(OUTPUT_BIN)/$@" > "$(OUTPUT_BIN)/$@.txt" + + +.PHONY: clean +clean: + @echo --- Cleaning $(VARIANT) files [$(OUTPUT_PATH)$(SEP)*.o] + -@$(RM) $(OUTPUT_PATH) 1>NUL 2>&1 + -@$(RM) $(OUTPUT_BIN)/$(OUTPUT_LIB) 1>NUL 2>&1 diff --git a/hardware/sam/cores/sam/build_gcc/release.mk b/hardware/sam/cores/sam/build_gcc/release.mk new file mode 100644 index 000000000..b4e815985 --- /dev/null +++ b/hardware/sam/cores/sam/build_gcc/release.mk @@ -0,0 +1,8 @@ + +# Optimization level +# -O1 Optimize +# -O2 Optimize even more +# -O3 Optimize yet more +# -O0 Reduce compilation time and make debugging produce the expected results +# -Os Optimize for size +OPTIMIZATION = -Os diff --git a/hardware/sam/cores/sam/build_iar/libarduino.ewd b/hardware/sam/cores/sam/build_iar/libarduino.ewd new file mode 100644 index 000000000..66b367087 --- /dev/null +++ b/hardware/sam/cores/sam/build_iar/libarduino.ewd @@ -0,0 +1,2587 @@ + + + + 2 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 1 + + + + + + + + + JLINK_ID + 2 + + 13 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + MACRAIGOR_ID + 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$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 0 + + + + + + + + + JLINK_ID + 2 + + 13 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + MACRAIGOR_ID + 2 + + 3 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + PEMICRO_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 2 + 1 + 0 + + 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$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + + + Debug_sam3s-ek + + ARM + + 1 + + C-SPY + 2 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 1 + + + + + + + + + JLINK_ID + 2 + + 13 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + MACRAIGOR_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + PEMICRO_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + + + + diff --git a/hardware/sam/cores/sam/build_iar/libarduino.ewp b/hardware/sam/cores/sam/build_iar/libarduino.ewp new file mode 100644 index 000000000..99ee36770 --- /dev/null +++ b/hardware/sam/cores/sam/build_iar/libarduino.ewp @@ -0,0 +1,2808 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 13 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 21 + 1 + 0 + + + + + + + + + + + + + + + + + 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+ + $PROJ_DIR$\..\wiring_analog.c + + Debug + + + + $PROJ_DIR$\..\wiring_analog.h + + + $PROJ_DIR$\..\wiring_constants.h + + + $PROJ_DIR$\..\wiring_digital.c + + + $PROJ_DIR$\..\wiring_digital.h + + + $PROJ_DIR$\..\wiring_private.h + + + $PROJ_DIR$\..\wiring_pulse.c + + Debug + + + + $PROJ_DIR$\..\wiring_pulse.h + + + $PROJ_DIR$\..\wiring_shift.c + + + $PROJ_DIR$\..\wiring_shift.h + + + $PROJ_DIR$\..\WMath.cpp + + + $PROJ_DIR$\..\WMath.h + + + $PROJ_DIR$\..\WString.cpp + + + $PROJ_DIR$\..\WString.h + + + + diff --git a/hardware/sam/cores/sam/cortex_handlers.c b/hardware/sam/cores/sam/cortex_handlers.c new file mode 100644 index 000000000..7df048b81 --- /dev/null +++ b/hardware/sam/cores/sam/cortex_handlers.c @@ -0,0 +1,68 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "Arduino.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern void NMI_Handler( void ) +{ + for ( ;; ) ; +} + +extern void HardFault_Handler( void ) +{ + for ( ;; ) ; +} + +extern void MemManage_Handler( void ) +{ + for ( ;; ) ; +} + +extern void BusFault_Handler( void ) +{ + for ( ;; ) ; +} + +extern void UsageFault_Handler( void ) +{ + for ( ;; ) ; +} + +extern void SVC_Handler( void ) +{ + for ( ;; ) ; +} + +extern void DebugMon_Handler( void ) +{ + for ( ;; ) ; +} + +extern void PendSV_Handler( void ) +{ + for ( ;; ) ; +} + +#ifdef __cplusplus +} +#endif + diff --git a/hardware/sam/cores/sam/cxxabi-compat.cpp b/hardware/sam/cores/sam/cxxabi-compat.cpp new file mode 100644 index 000000000..7370b0be1 --- /dev/null +++ b/hardware/sam/cores/sam/cxxabi-compat.cpp @@ -0,0 +1,26 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +extern "C" void __cxa_pure_virtual(void) ; + +/* We compile with nodefaultlibs, so we need to provide an error + * handler for an empty pure virtual function */ +extern "C" void __cxa_pure_virtual(void) { + while(1) + ; +} diff --git a/hardware/sam/cores/sam/iar_calls_sam3.c b/hardware/sam/cores/sam/iar_calls_sam3.c new file mode 100644 index 000000000..253f3b092 --- /dev/null +++ b/hardware/sam/cores/sam/iar_calls_sam3.c @@ -0,0 +1,109 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +/** +* \file +* +* Implementation of low level library. +* +*/ + +#if defined __ICCARM__ /* IAR Ewarm 5.41+ */ + +#include "board.h" + +#include +#include +#include +#include +#include + +extern __weak size_t __write( int handle, const unsigned char *buf, size_t bufSize ) +{ + size_t nChars = 0 ; + + /* Check for the command to flush all handles */ + if ( handle == -1 ) + { + return 0 ; + } + + /* Check for stdout and stderr (only necessary if FILE descriptors are enabled.) */ + if ( handle != 1 && handle != 2 ) + { + /* remove warnings */ + return 0xfffffff ; + } + + for ( /* Empty */ ; bufSize > 0 ; --bufSize ) + { + while ( !uart_is_tx_ready(CONSOLE_UART) ) + ; + uart_write( CONSOLE_UART, *buf ) ; + ++buf ; + ++nChars ; + } + + return nChars ; +} + + +extern __weak size_t __read( int handle, unsigned char *buf, size_t bufSize ) +{ + size_t nChars = 0 ; + + /* Check for stdin (only necessary if FILE descriptors are enabled) */ + if ( handle != 0 ) + { + /* remove warnings */ + return 0xfffffff ; + } + + for ( /*Empty*/; bufSize > 0 ; --bufSize ) + { + uint8_t c; + while (uart_read( CONSOLE_UART, &c )) + ; + + if ( c == 0 ) + { + break ; + } + *buf++ = c ; + ++nChars ; + } + + return nChars ; +} + +/** + * \brief Outputs a character on the UART. + * + * \param c Character to output. + * + * \return The character that was output. + */ +extern __weak signed int putchar( signed int c ) +{ + while ( !uart_is_tx_ready(CONSOLE_UART) ) + ; + uart_write( CONSOLE_UART, c ) ; + + return c ; +} +#endif // defined __ICCARM__ diff --git a/hardware/sam/cores/sam/itoa.c b/hardware/sam/cores/sam/itoa.c new file mode 100644 index 000000000..fc3576602 --- /dev/null +++ b/hardware/sam/cores/sam/itoa.c @@ -0,0 +1,170 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "itoa.h" +#include + +#ifdef __cplusplus +extern "C"{ +#endif // __cplusplus + +#if 0 +/* reverse: reverse string s in place */ +static void reverse( char s[] ) +{ + int i, j ; + char c ; + + for ( i = 0, j = strlen(s)-1 ; i < j ; i++, j-- ) + { + c = s[i] ; + s[i] = s[j] ; + s[j] = c ; + } +} + +/* itoa: convert n to characters in s */ +extern void itoa( int n, char s[] ) +{ + int i, sign ; + + if ( (sign = n) < 0 ) /* record sign */ + { + n = -n; /* make n positive */ + } + + i = 0; + do + { /* generate digits in reverse order */ + s[i++] = n % 10 + '0'; /* get next digit */ + } while ((n /= 10) > 0) ; /* delete it */ + + if (sign < 0 ) + { + s[i++] = '-'; + } + + s[i] = '\0'; + + reverse( s ) ; +} + +#else + +extern char* itoa( int value, char *string, int radix ) +{ + return ltoa( value, string, radix ) ; +} + +extern char* ltoa( long value, char *string, int radix ) +{ + char tmp[33]; + char *tp = tmp; + long i; + unsigned long v; + int sign; + char *sp; + + if ( string == NULL ) + { + return 0 ; + } + + if (radix > 36 || radix <= 1) + { + return 0 ; + } + + sign = (radix == 10 && value < 0); + if (sign) + { + v = -value; + } + else + { + v = (unsigned long)value; + } + + while (v || tp == tmp) + { + i = v % radix; + v = v / radix; + if (i < 10) + *tp++ = i+'0'; + else + *tp++ = i + 'a' - 10; + } + + sp = string; + + if (sign) + *sp++ = '-'; + while (tp > tmp) + *sp++ = *--tp; + *sp = 0; + + return string; +} + +extern char* utoa( unsigned long value, char *string, int radix ) +{ + return ultoa( value, string, radix ) ; +} + +extern char* ultoa( unsigned long value, char *string, int radix ) +{ + char tmp[33]; + char *tp = tmp; + long i; + unsigned long v = value; + char *sp; + + if ( string == NULL ) + { + return 0; + } + + if (radix > 36 || radix <= 1) + { + return 0; + } + + while (v || tp == tmp) + { + i = v % radix; + v = v / radix; + if (i < 10) + *tp++ = i+'0'; + else + *tp++ = i + 'a' - 10; + } + + sp = string; + + + while (tp > tmp) + *sp++ = *--tp; + *sp = 0; + + return string; +} +#endif /* 0 */ + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus diff --git a/hardware/sam/cores/sam/itoa.h b/hardware/sam/cores/sam/itoa.h new file mode 100644 index 000000000..59af10947 --- /dev/null +++ b/hardware/sam/cores/sam/itoa.h @@ -0,0 +1,42 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _ITOA_ +#define _ITOA_ + +#ifdef __cplusplus +extern "C"{ +#endif // __cplusplus + +#if 0 + +extern void itoa( int n, char s[] ) ; + +#else + +extern char* itoa( int value, char *string, int radix ) ; +extern char* ltoa( long value, char *string, int radix ) ; +extern char* utoa( unsigned long value, char *string, int radix ) ; +extern char* ultoa( unsigned long value, char *string, int radix ) ; +#endif /* 0 */ + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus + +#endif // _ITOA_ diff --git a/hardware/sam/cores/sam/main.cpp b/hardware/sam/cores/sam/main.cpp new file mode 100644 index 000000000..325e6a807 --- /dev/null +++ b/hardware/sam/cores/sam/main.cpp @@ -0,0 +1,37 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#define ARDUINO_MAIN +#include "Arduino.h" + +/* + * \brief Main entry point of Arduino application + */ +int main( void ) +{ + init() ; + + setup() ; + + for ( ; ; ) + { + loop() ; + } + +// return 0 ; +} diff --git a/hardware/sam/cores/sam/prod_test_due/build_gcc/Makefile b/hardware/sam/cores/sam/prod_test_due/build_gcc/Makefile new file mode 100644 index 000000000..a24299e2b --- /dev/null +++ b/hardware/sam/cores/sam/prod_test_due/build_gcc/Makefile @@ -0,0 +1,41 @@ +# +# Copyright (c) 2011 Arduino. All right reserved. +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +# See the GNU Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +SUBMAKE_OPTIONS=--no-builtin-rules --no-builtin-variables + +#------------------------------------------------------------------------------- +# Rules +#------------------------------------------------------------------------------- + +all: prod_test_due + +.PHONY: prod_test_due +prod_test_due: + @echo --- Making prod_test_due + @$(MAKE) DEBUG=1 $(SUBMAKE_OPTIONS) -f prod_test_due.mk + +.PHONY: clean +clean: + @echo --- Cleaning prod_test_due + @$(MAKE) DEBUG=1 $(SUBMAKE_OPTIONS) -f prod_test_due.mk $@ + +.PHONY: debug +debug: + @echo --- Debugging prod_test_due + @$(MAKE) DEBUG=1 $(SUBMAKE_OPTIONS) -f prod_test_due.mk $@ + diff --git a/hardware/sam/cores/sam/prod_test_due/build_gcc/debug.mk b/hardware/sam/cores/sam/prod_test_due/build_gcc/debug.mk new file mode 100644 index 000000000..d0716744a --- /dev/null +++ b/hardware/sam/cores/sam/prod_test_due/build_gcc/debug.mk @@ -0,0 +1,25 @@ +# +# Copyright (c) 2011 Arduino. All right reserved. +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +# See the GNU Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +# Optimization level +# -O1 Optimize +# -O2 Optimize even more +# -O3 Optimize yet more +# -O0 Reduce compilation time and make debugging produce the expected results +# -Os Optimize for size +OPTIMIZATION = -g -O0 -DDEBUG diff --git a/hardware/sam/cores/sam/prod_test_due/build_gcc/gcc.mk b/hardware/sam/cores/sam/prod_test_due/build_gcc/gcc.mk new file mode 100644 index 000000000..f26b9b882 --- /dev/null +++ b/hardware/sam/cores/sam/prod_test_due/build_gcc/gcc.mk @@ -0,0 +1,79 @@ +# +# Copyright (c) 2011 Arduino. All right reserved. +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +# See the GNU Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +# Tool suffix when cross-compiling +#CROSS_COMPILE = ../../../../tools/CodeSourcery_arm/bin/arm-none-eabi- +#CROSS_COMPILE = C:/CodeSourcery_2011.03-42/bin/arm-none-eabi- +CROSS_COMPILE = $(ARM_GCC_TOOLCHAIN)/arm-none-eabi- + +# Compilation tools +AR = $(CROSS_COMPILE)ar +CC = $(CROSS_COMPILE)gcc +CXX = $(CROSS_COMPILE)g++ +AS = $(CROSS_COMPILE)as +GDB = $(CROSS_COMPILE)gdb +SIZE = $(CROSS_COMPILE)size +NM = $(CROSS_COMPILE)nm +OBJCOPY = $(CROSS_COMPILE)objcopy +RM=cs-rm -Rf +SEP=\\ + +# --------------------------------------------------------------------------------------- +# C Flags + +CFLAGS += -Wall -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int +CFLAGS += -Werror-implicit-function-declaration -Wmain -Wparentheses +CFLAGS += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused +CFLAGS += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef +CFLAGS += -Wshadow -Wpointer-arith -Wbad-function-cast -Wwrite-strings +CFLAGS += -Wsign-compare -Waggregate-return -Wstrict-prototypes +CFLAGS += -Wmissing-prototypes -Wmissing-declarations +CFLAGS += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations +CFLAGS += -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long +CFLAGS += -Wunreachable-code +CFLAGS += -Wcast-align + +CFLAGS += --param max-inline-insns-single=500 -mcpu=cortex-m3 -mthumb -mlong-calls -ffunction-sections -nostdlib +CFLAGS += $(OPTIMIZATION) $(INCLUDES) -D$(CHIP) -D$(VARIANT) + +# To reduce application size use only integer printf function. +CFLAGS += -Dprintf=iprintf + +# --------------------------------------------------------------------------------------- +# CPP Flags + +CPPFLAGS += -Wall -Wchar-subscripts -Wcomment -Wformat=2 +CPPFLAGS += -Wmain -Wparentheses -Wcast-align -Wunreachable-code +CPPFLAGS += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused +CPPFLAGS += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef +CPPFLAGS += -Wshadow -Wpointer-arith -Wwrite-strings +CPPFLAGS += -Wsign-compare -Waggregate-return -Wmissing-declarations +CPPFLAGS += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations +CPPFLAGS += -Wpacked -Wredundant-decls -Winline -Wlong-long + +#-fno-rtti -fno-exceptions +CPPFLAGS += --param max-inline-insns-single=500 -mcpu=cortex-m3 -mthumb -mlong-calls -ffunction-sections +CPPFLAGS += $(OPTIMIZATION) $(INCLUDES) -D$(CHIP) + +# To reduce application size use only integer printf function. +CPPFLAGS += -Dprintf=iprintf + +# --------------------------------------------------------------------------------------- +# ASM Flags + +ASFLAGS = -mcpu=cortex-m3 -mthumb -Wall -g $(OPTIMIZATION) $(INCLUDES) diff --git a/hardware/sam/cores/sam/prod_test_due/build_gcc/prod_test_due.mk b/hardware/sam/cores/sam/prod_test_due/build_gcc/prod_test_due.mk new file mode 100644 index 000000000..2bf64e1ba --- /dev/null +++ b/hardware/sam/cores/sam/prod_test_due/build_gcc/prod_test_due.mk @@ -0,0 +1,183 @@ +# +# Copyright (c) 2011 Arduino. All right reserved. +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +# See the GNU Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +# Makefile for compiling libArduino +.SUFFIXES: .o .a .c .s + +# putting default variant +ifeq ("$(VARIANT)", "") +#VARIANT=sam3s_ek +VARIANT=sam3u_ek +#VARIANT=arduino_due +endif + +ifeq ("$(VARIANT)", "sam3s_ek") +CHIP=__SAM3S4C__ +else ifeq ("$(VARIANT)", "sam3u_ek") +CHIP=__SAM3U4E__ +else ifeq ("$(VARIANT)", "arduino_due") +CHIP=__SAM3U4E__ +endif + +TOOLCHAIN=gcc + +#------------------------------------------------------------------------------- +# Path +#------------------------------------------------------------------------------- + +# Libraries +PROJECT_BASE_PATH = ./.. +SYSTEM_PATH = ../../../../system +CMSIS_BASE_PATH = $(SYSTEM_PATH)/CMSIS/Include +VARIANT_PATH = ../../../../variants/$(VARIANT) + +ifeq ($(CHIP), __SAM3S4C__) +CHIP_NAME=sam3s4c +CHIP_SERIE=sam3s +else ifeq ($(CHIP), __SAM3U4E__) +CHIP_NAME=sam3u4e +CHIP_SERIE=sam3u +else ifeq ($(CHIP), __SAM3N4C__) +CHIP_NAME=sam3n4c +CHIP_SERIE=sam3n +else ifeq ($(CHIP), __SAM3X8H__) +CHIP_NAME=sam3x8h +CHIP_SERIE=sam3xa +else +endif + +CMSIS_CHIP_PATH=$(SYSTEM_PATH)/libsam/cmsis/$(CHIP_SERIE) + +# Output directories +OUTPUT_PATH = debug_$(VARIANT) + +#------------------------------------------------------------------------------- +# Files +#------------------------------------------------------------------------------- + +vpath %.h $(PROJECT_BASE_PATH)/.. $(VARIANT_PATH) $(SYSTEM_PATH) $(CMSIS_BASE_PATH) +vpath %.cpp $(PROJECT_BASE_PATH) + +VPATH+=$(PROJECT_BASE_PATH) + +INCLUDES = -I$(PROJECT_BASE_PATH)/.. +INCLUDES += -I$(VARIANT_PATH) +INCLUDES += -I$(VARIANT_PATH)/.. +INCLUDES += -I$(SYSTEM_PATH) +INCLUDES += -I$(SYSTEM_PATH)/libsam +INCLUDES += -I$(CMSIS_BASE_PATH) + +#------------------------------------------------------------------------------- +ifdef DEBUG +include debug.mk +else +include release.mk +endif + +#------------------------------------------------------------------------------- +# Tools +#------------------------------------------------------------------------------- + +include $(TOOLCHAIN).mk + +#------------------------------------------------------------------------------- +ifdef DEBUG +OUTPUT_OBJ=debug +LIBS_POSTFIX=dbg +else +OUTPUT_OBJ=release +LIBS_POSTFIX=rel +endif + +OUTPUT_BIN=test_$(TOOLCHAIN)_$(LIBS_POSTFIX) +#LIBS=-L../libsam_$(CHIP_NAME)_$(TOOLCHAIN)_rel.a -L../arduino_$(VARIANT)_$(TOOLCHAIN)_rel.a +# +LIBS=-Wl,--start-group -lgcc -lc -lstdc++ -lsam_$(CHIP_NAME)_$(TOOLCHAIN)_$(LIBS_POSTFIX) -larduino_$(VARIANT)_$(TOOLCHAIN)_$(LIBS_POSTFIX) -lvariant_$(VARIANT)_$(TOOLCHAIN)_$(LIBS_POSTFIX) -Wl,--end-group + +LIB_PATH =-L$(PROJECT_BASE_PATH)/.. +LIB_PATH+=-L=/lib/thumb2 +#LIB_PATH+=-L=/../lib/gcc/arm-none-eabi/4.5.2/thumb2 + +LDFLAGS= -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols + +#------------------------------------------------------------------------------- +# CPP source files and objects +#------------------------------------------------------------------------------- +CPP_SRC=$(wildcard $(PROJECT_BASE_PATH)/*.cpp) + +CPP_OBJ_TEMP = $(patsubst %.cpp, %.o, $(notdir $(CPP_SRC))) + +# during development, remove some files +CPP_OBJ_FILTER= + +CPP_OBJ=$(filter-out $(CPP_OBJ_FILTER), $(CPP_OBJ_TEMP)) + +#------------------------------------------------------------------------------- +# Rules +#------------------------------------------------------------------------------- +all: prod_test_due + +prod_test_due: create_output $(OUTPUT_BIN) + +.PHONY: create_output +create_output: + @echo --- Preparing $(VARIANT) files in $(OUTPUT_PATH) $(OUTPUT_BIN) + @echo ------------------------- + @echo *$(INCLUDES) + @echo ------------------------- + @echo *$(C_SRC) + @echo ------------------------- + @echo *$(C_OBJ) + @echo ------------------------- + @echo *$(addprefix $(OUTPUT_PATH)/, $(C_OBJ)) + @echo ------------------------- + @echo *$(CPP_SRC) + @echo ------------------------- + @echo *$(CPP_OBJ) + @echo ------------------------- + @echo *$(addprefix $(OUTPUT_PATH)/, $(CPP_OBJ)) + @echo ------------------------- + @echo *$(A_SRC) + @echo ------------------------- + + -@mkdir $(OUTPUT_PATH) 1>NUL 2>&1 + +$(addprefix $(OUTPUT_PATH)/,$(CPP_OBJ)): $(OUTPUT_PATH)/%.o: %.cpp +# @$(CC) -c $(CPPFLAGS) $< -o $@ + @$(CXX) -c $(CPPFLAGS) $< -o $@ +# @$(CXX) -v -c $(CPPFLAGS) $< -o $@ + +$(OUTPUT_BIN): $(addprefix $(OUTPUT_PATH)/, $(C_OBJ)) $(addprefix $(OUTPUT_PATH)/, $(CPP_OBJ)) $(addprefix $(OUTPUT_PATH)/, $(A_OBJ)) + @$(CC) $(LIB_PATH) $(LDFLAGS) -T"$(VARIANT_PATH)/linker_scripts/gcc/flash.ld" -Wl,-Map,$(OUTPUT_PATH)/$@.map -o $(OUTPUT_PATH)/$@.elf $^ $(LIBS) +# @$(CC) $(LIB_PATH) $(LDFLAGS) -T"$(VARIANT_PATH)/linker_scripts/gcc/sram.ld" -Wl,-Map,$(OUTPUT_PATH)/$@.map -o $(OUTPUT_PATH)/$@.elf $^ $(LIBS) + @$(NM) $(OUTPUT_PATH)/$@.elf >$(OUTPUT_PATH)/$@.elf.txt + @$(OBJCOPY) -O binary $(OUTPUT_PATH)/$@.elf $(OUTPUT_PATH)/$@.bin + $(SIZE) $^ $(OUTPUT_PATH)/$@.elf + +.PHONY: clean +clean: + @echo --- Cleaning test files + -@$(RM) $(OUTPUT_PATH)/test.o 1>NUL 2>&1 + -@$(RM) $(OUTPUT_PATH)/$(OUTPUT_BIN).elf 1>NUL 2>&1 + -@$(RM) $(OUTPUT_PATH)/$(OUTPUT_BIN).elf.txt 1>NUL 2>&1 + -@$(RM) $(OUTPUT_PATH)/$(OUTPUT_BIN).bin 1>NUL 2>&1 + -@$(RM) $(OUTPUT_PATH)/$(OUTPUT_BIN).map 1>NUL 2>&1 + +debug: test + @$(GDB) -x "$(VARIANT_PATH)/debug_scripts/gcc/$(VARIANT)_flash.gdb" -ex "reset" -readnow -se $(OUTPUT_PATH)/$(OUTPUT_BIN).elf +# @$(GDB) -w -x "$(VARIANT_PATH)/debug_scripts/gcc/$(VARIANT)_sram.gdb" -ex "reset" -readnow -se $(OUTPUT_PATH)/$(OUTPUT_BIN).elf diff --git a/hardware/sam/cores/sam/prod_test_due/build_gcc/release.mk b/hardware/sam/cores/sam/prod_test_due/build_gcc/release.mk new file mode 100644 index 000000000..0d15157f4 --- /dev/null +++ b/hardware/sam/cores/sam/prod_test_due/build_gcc/release.mk @@ -0,0 +1,25 @@ +# +# Copyright (c) 2011 Arduino. All right reserved. +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +# See the GNU Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +# Optimization level +# -O1 Optimize +# -O2 Optimize even more +# -O3 Optimize yet more +# -O0 Reduce compilation time and make debugging produce the expected results +# -Os Optimize for size +OPTIMIZATION = -Os diff --git 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$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + + + + diff --git a/hardware/sam/cores/sam/prod_test_due/build_iar/prod_test_due.ewp b/hardware/sam/cores/sam/prod_test_due/build_iar/prod_test_due.ewp new file mode 100644 index 000000000..c22825fb8 --- /dev/null +++ b/hardware/sam/cores/sam/prod_test_due/build_iar/prod_test_due.ewp @@ -0,0 +1,1834 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 13 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\variants\sam3s_ek\debug_scripts\iar\sam3s_ek_flash.mac + + + $PROJ_DIR$\..\..\..\..\variants\sam3s_ek\linker_scripts\iar\sam3s_ek_sram.icf + + + $PROJ_DIR$\..\..\..\..\variants\sam3s_ek\debug_scripts\iar\sam3s_ek_sram.mac + + + + sam3u_ek + + + + $PROJ_DIR$\..\..\libarduino_sam3s_ek_ewarm_dbg.a + + + $PROJ_DIR$\..\..\libsam_sam3s4c_ewarm_dbg.a + + + $PROJ_DIR$\..\..\libvariant_sam3s_ek_ewarm_dbg.a + + + $PROJ_DIR$\..\test.cpp + + + + diff --git a/hardware/sam/cores/sam/prod_test_due/main.cpp b/hardware/sam/cores/sam/prod_test_due/main.cpp new file mode 100644 index 000000000..59adb4ade --- /dev/null +++ b/hardware/sam/cores/sam/prod_test_due/main.cpp @@ -0,0 +1,219 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "variant.h" + +/* Ensure we are compiling this for Arduino Due */ +#if !defined( arduino_due ) +#error "Error: wrong variant chosen" +#endif + +typedef enum _ePins +{ + /* LEDs */ + PIN_13=0, + PIN_RXL=1, + PIN_TXL=2, + + /* UART */ + PIN_URXD=3, + PIN_UTXD=4, + PIN_UART=5, + + /* USART0 */ + PIN_RXD0=6, + PIN_TXD0=7, + PIN_USART0=8, + + /* USART1 */ + PIN_RXD1=9, + PIN_TXD1=10, + PIN_USART1=11, + + /* USART2 */ + PIN_RXD2=12, + PIN_TXD2=13, + PIN_USART2=14, + + /* SPI */ + PIN_MISO=15, + PIN_MOSI=16, + PIN_SPCK=17, + PIN_NPCS0=18, + + /* TWI0 */ + PIN_SDA1=19, + PIN_SCL1=20, + PIN_TWI0=21, + + /* TWI1 */ + PIN_SDA0=22, + PIN_SCL0=23, + PIN_TWI1=24, + + /* Analog */ + PIN_AD0=25, + PIN_AD1=26, + PIN_AD2=27, + PIN_AD3=28, + PIN_AD4=29, + PIN_AD5=30, + PIN_AD6=31, + PIN_AD7=32, + PIN_AD8=33, + PIN_AD9=34, + PIN_AD10=35, + PIN_AD11=36, + PIN_AD12=37, + PIN_AD13=38, + + /* External DAC */ + PIN_DAC_CS=39, + PIN_DAC_SCK=40, + PIN_DAC_DIN=41, + + /* PWM */ + PIN_PWM=42, + PIN_PWMH0=43, + PIN_PWMH1=44, + PIN_PWMH2=45, + PIN_PWMH3=46, + PIN_PWML0=47, + PIN_PWML1=48, + PIN_PWML2=49, + PIN_PWML3=50, + + PIN_10=51, + + PIN_22=52, + PIN_23=53, + PIN_24=54, + PIN_25=55, + PIN_26=56, + PIN_27=57, + PIN_28=58, + PIN_29=59, + PIN_30=60, + PIN_31=61, + PIN_32=62, + PIN_33=63, + PIN_34=64, + PIN_35=65, + PIN_36=66, + PIN_37=67, + PIN_38=68, + PIN_39=69, + PIN_40=70, + PIN_41=71, + PIN_42=72, + PIN_43=73, + PIN_44=74, + PIN_45=75, + PIN_46=76, + PIN_47=77, + PIN_48=78, + PIN_49=79, + PIN_50=80, + PIN_51=81, + PIN_52=82, + PIN_53=83 +} ePins ; + +#define PIN_FIRST PIN_13 +#define PIN_LAST PIN_53 + +void setup( void ) +{ + // Initialize all digital pins in output mode. + for ( dwIndex=PIN_FIRST ; dwIndex <= PIN_LAST ; dwIndex++ ) + { + if ( ((g_APinDescription[dwIndex].ulPinAttribute & PIN_ATTR_COMBO) == 0) && ((g_APinDescription[dwIndex].ulPinAttribute & PIN_ATTR_ANALOG) == 0) ) + { + pinMode( dwIndex, OUTPUT ) ; + } + } + + // Initialize all analog pins + +} + +void loop( void ) +{ + uint32_t dwIndex ; + uint32_t adwAnalogValues[PIN_AD13-PIN_AD0+1] ; + uint32_t dwChaserIndex=PIN_FIRST ; + uint32_t dwChaserIndexLast=PIN_FIRST ; + + // production test loop + for ( ;; ) + { + // Read analog values + for ( dwIndex=PIN_AD0 ; dwIndex <= PIN_AD13 ; dwIndex++ ) + { +// adwAnalogValues[dwIndex]= ; + } + + // Transmit analog values on USB CDC + for ( dwIndex=PIN_AD0 ; dwIndex <= PIN_AD13 ; dwIndex++ ) + { +// CDC_Print( adwAnalogValues[dwIndex] ) ; + } + + // Do chaser + // set the current pin output to VCC + digitalWrite( dwChaserIndex, HIGH ) ; + + // set the previous pin output to GND + if ( dwChaserIndexLast != dwChaserIndex ) + { + digitalWrite( dwChaserIndex, LOW ) ; + } + + // backup current chaser pin index + dwChaserIndexLast=dwChaserIndex ; + dwChaserIndex++ ; + + // find next chaser pin + for ( ; ; ) + { + // Go circular if we reached the end of pins + if ( dwChaserIndex > PIN_LAST ) + { + dwChaserIndex=PIN_FIRST ; + } + + // bypass combo and analog pins + if ( ((g_APinDescription[dwChaserIndex].ulPinAttribute & PIN_ATTR_COMBO) != 0) || ((g_APinDescription[dwChaserIndex].ulPinAttribute & PIN_ATTR_ANALOG) != 0) ) + { + dwChaserIndex++ ; + } + else + { + break ; + } + } + + // Go circular if we reached the end of pins + if ( dwChaserIndex > PIN_LAST ) + { + dwChaserIndex=PIN_FIRST ; + } + + delay( 500 ) ; // wait for a second + } +} diff --git a/hardware/sam/cores/sam/syscalls.h b/hardware/sam/cores/sam/syscalls.h new file mode 100644 index 000000000..845b4b5d3 --- /dev/null +++ b/hardware/sam/cores/sam/syscalls.h @@ -0,0 +1,60 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +/** + * \file syscalls.h + * + * Implementation of newlib syscall. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include +#include +#include +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +#ifdef __cplusplus +extern "C" { +#endif + +extern caddr_t _sbrk( int incr ) ; + +extern int link( char *cOld, char *cNew ) ; + +extern int _close( int file ) ; + +extern int _fstat( int file, struct stat *st ) ; + +extern int _isatty( int file ) ; + +extern int _lseek( int file, int ptr, int dir ) ; + +extern int _read(int file, char *ptr, int len) ; + +extern int _write( int file, char *ptr, int len ) ; + +#ifdef __cplusplus +} +#endif + diff --git a/hardware/sam/cores/sam/syscalls_sam3.c b/hardware/sam/cores/sam/syscalls_sam3.c new file mode 100644 index 000000000..e0f72dd46 --- /dev/null +++ b/hardware/sam/cores/sam/syscalls_sam3.c @@ -0,0 +1,132 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +/** + * \file syscalls_sam3.c + * + * Implementation of newlib syscall. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + + +#include "syscalls.h" + +#include +#include +#if defined ( __GNUC__ ) /* GCC CS3 */ + #include + #include +#endif + +/*---------------------------------------------------------------------------- + * Exported variables + *----------------------------------------------------------------------------*/ + +#undef errno +extern int errno ; +extern int _end ; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void _exit( int status ) ; +extern void _kill( int pid, int sig ) ; +extern int _getpid ( void ) ; + +extern caddr_t _sbrk ( int incr ) +{ + static unsigned char *heap = NULL ; + unsigned char *prev_heap ; + + if ( heap == NULL ) + { + heap = (unsigned char *)&_end ; + } + prev_heap = heap; + + heap += incr ; + + return (caddr_t) prev_heap ; +} + +extern int link( char *cOld, char *cNew ) +{ + return -1 ; +} + +extern int _close( int file ) +{ + return -1 ; +} + +extern int _fstat( int file, struct stat *st ) +{ + st->st_mode = S_IFCHR ; + + return 0 ; +} + +extern int _isatty( int file ) +{ + return 1 ; +} + +extern int _lseek( int file, int ptr, int dir ) +{ + return 0 ; +} + +extern int _read(int file, char *ptr, int len) +{ + return 0 ; +} + +extern int _write( int file, char *ptr, int len ) +{ + int iIndex ; + + +// for ( ; *ptr != 0 ; ptr++ ) + for ( iIndex=0 ; iIndex < len ; iIndex++, ptr++ ) + { +// UART_PutChar( *ptr ) ; + } + + return iIndex ; +} + +extern void _exit( int status ) +{ + printf( "Exiting with status %d.\n", status ) ; + + for ( ; ; ) ; +} + +extern void _kill( int pid, int sig ) +{ + return ; +} + +extern int _getpid ( void ) +{ + return -1 ; +} diff --git a/hardware/sam/cores/sam/validation/build_gcc/Makefile b/hardware/sam/cores/sam/validation/build_gcc/Makefile new file mode 100644 index 000000000..92bddee3e --- /dev/null +++ b/hardware/sam/cores/sam/validation/build_gcc/Makefile @@ -0,0 +1,41 @@ +# +# Copyright (c) 2011 Arduino. All right reserved. +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +# See the GNU Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +SUBMAKE_OPTIONS=--no-builtin-rules --no-builtin-variables + +#------------------------------------------------------------------------------- +# Rules +#------------------------------------------------------------------------------- + +all: test + +.PHONY: test +test: + @echo --- Making test + @$(MAKE) DEBUG=1 $(SUBMAKE_OPTIONS) -f test.mk + +.PHONY: clean +clean: + @echo --- Cleaning test + @$(MAKE) DEBUG=1 $(SUBMAKE_OPTIONS) -f test.mk $@ + +.PHONY: debug +debug: + @echo --- Debugging test + @$(MAKE) DEBUG=1 $(SUBMAKE_OPTIONS) -f test.mk $@ + diff --git a/hardware/sam/cores/sam/validation/build_gcc/debug.mk b/hardware/sam/cores/sam/validation/build_gcc/debug.mk new file mode 100644 index 000000000..d0716744a --- /dev/null +++ b/hardware/sam/cores/sam/validation/build_gcc/debug.mk @@ -0,0 +1,25 @@ +# +# Copyright (c) 2011 Arduino. All right reserved. +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +# See the GNU Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +# Optimization level +# -O1 Optimize +# -O2 Optimize even more +# -O3 Optimize yet more +# -O0 Reduce compilation time and make debugging produce the expected results +# -Os Optimize for size +OPTIMIZATION = -g -O0 -DDEBUG diff --git a/hardware/sam/cores/sam/validation/build_gcc/gcc.mk b/hardware/sam/cores/sam/validation/build_gcc/gcc.mk new file mode 100644 index 000000000..f26b9b882 --- /dev/null +++ b/hardware/sam/cores/sam/validation/build_gcc/gcc.mk @@ -0,0 +1,79 @@ +# +# Copyright (c) 2011 Arduino. All right reserved. +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +# See the GNU Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +# Tool suffix when cross-compiling +#CROSS_COMPILE = ../../../../tools/CodeSourcery_arm/bin/arm-none-eabi- +#CROSS_COMPILE = C:/CodeSourcery_2011.03-42/bin/arm-none-eabi- +CROSS_COMPILE = $(ARM_GCC_TOOLCHAIN)/arm-none-eabi- + +# Compilation tools +AR = $(CROSS_COMPILE)ar +CC = $(CROSS_COMPILE)gcc +CXX = $(CROSS_COMPILE)g++ +AS = $(CROSS_COMPILE)as +GDB = $(CROSS_COMPILE)gdb +SIZE = $(CROSS_COMPILE)size +NM = $(CROSS_COMPILE)nm +OBJCOPY = $(CROSS_COMPILE)objcopy +RM=cs-rm -Rf +SEP=\\ + +# --------------------------------------------------------------------------------------- +# C Flags + +CFLAGS += -Wall -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int +CFLAGS += -Werror-implicit-function-declaration -Wmain -Wparentheses +CFLAGS += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused +CFLAGS += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef +CFLAGS += -Wshadow -Wpointer-arith -Wbad-function-cast -Wwrite-strings +CFLAGS += -Wsign-compare -Waggregate-return -Wstrict-prototypes +CFLAGS += -Wmissing-prototypes -Wmissing-declarations +CFLAGS += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations +CFLAGS += -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long +CFLAGS += -Wunreachable-code +CFLAGS += -Wcast-align + +CFLAGS += --param max-inline-insns-single=500 -mcpu=cortex-m3 -mthumb -mlong-calls -ffunction-sections -nostdlib +CFLAGS += $(OPTIMIZATION) $(INCLUDES) -D$(CHIP) -D$(VARIANT) + +# To reduce application size use only integer printf function. +CFLAGS += -Dprintf=iprintf + +# --------------------------------------------------------------------------------------- +# CPP Flags + +CPPFLAGS += -Wall -Wchar-subscripts -Wcomment -Wformat=2 +CPPFLAGS += -Wmain -Wparentheses -Wcast-align -Wunreachable-code +CPPFLAGS += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused +CPPFLAGS += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef +CPPFLAGS += -Wshadow -Wpointer-arith -Wwrite-strings +CPPFLAGS += -Wsign-compare -Waggregate-return -Wmissing-declarations +CPPFLAGS += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations +CPPFLAGS += -Wpacked -Wredundant-decls -Winline -Wlong-long + +#-fno-rtti -fno-exceptions +CPPFLAGS += --param max-inline-insns-single=500 -mcpu=cortex-m3 -mthumb -mlong-calls -ffunction-sections +CPPFLAGS += $(OPTIMIZATION) $(INCLUDES) -D$(CHIP) + +# To reduce application size use only integer printf function. +CPPFLAGS += -Dprintf=iprintf + +# --------------------------------------------------------------------------------------- +# ASM Flags + +ASFLAGS = -mcpu=cortex-m3 -mthumb -Wall -g $(OPTIMIZATION) $(INCLUDES) diff --git a/hardware/sam/cores/sam/validation/build_gcc/release.mk b/hardware/sam/cores/sam/validation/build_gcc/release.mk new file mode 100644 index 000000000..0d15157f4 --- /dev/null +++ b/hardware/sam/cores/sam/validation/build_gcc/release.mk @@ -0,0 +1,25 @@ +# +# Copyright (c) 2011 Arduino. All right reserved. +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +# See the GNU Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +# Optimization level +# -O1 Optimize +# -O2 Optimize even more +# -O3 Optimize yet more +# -O0 Reduce compilation time and make debugging produce the expected results +# -Os Optimize for size +OPTIMIZATION = -Os diff --git a/hardware/sam/cores/sam/validation/build_gcc/test.mk b/hardware/sam/cores/sam/validation/build_gcc/test.mk new file mode 100644 index 000000000..e64349433 --- /dev/null +++ b/hardware/sam/cores/sam/validation/build_gcc/test.mk @@ -0,0 +1,183 @@ +# +# Copyright (c) 2011 Arduino. All right reserved. +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +# See the GNU Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +# Makefile for compiling libArduino +.SUFFIXES: .o .a .c .s + +# putting default variant +ifeq ("$(VARIANT)", "") +#VARIANT=sam3s_ek +#VARIANT=sam3u_ek +VARIANT=arduino_due +endif + +ifeq ("$(VARIANT)", "sam3s_ek") +CHIP=__SAM3S4C__ +else ifeq ("$(VARIANT)", "sam3u_ek") +CHIP=__SAM3U4E__ +else ifeq ("$(VARIANT)", "arduino_due") +CHIP=__SAM3U4E__ +endif + +TOOLCHAIN=gcc + +#------------------------------------------------------------------------------- +# Path +#------------------------------------------------------------------------------- + +# Libraries +PROJECT_BASE_PATH = ./.. +SYSTEM_PATH = ../../../../system +CMSIS_BASE_PATH = $(SYSTEM_PATH)/CMSIS/Include +VARIANT_PATH = ../../../../variants/$(VARIANT) + +ifeq ($(CHIP), __SAM3S4C__) +CHIP_NAME=sam3s4c +CHIP_SERIE=sam3s +else ifeq ($(CHIP), __SAM3U4E__) +CHIP_NAME=sam3u4e +CHIP_SERIE=sam3u +else ifeq ($(CHIP), __SAM3N4C__) +CHIP_NAME=sam3n4c +CHIP_SERIE=sam3n +else ifeq ($(CHIP), __SAM3X8H__) +CHIP_NAME=sam3x8h +CHIP_SERIE=sam3xa +else +endif + +CMSIS_CHIP_PATH=$(SYSTEM_PATH)/libsam/cmsis/$(CHIP_SERIE) + +# Output directories +OUTPUT_PATH = debug_$(VARIANT) + +#------------------------------------------------------------------------------- +# Files +#------------------------------------------------------------------------------- + +vpath %.h $(PROJECT_BASE_PATH)/.. $(VARIANT_PATH) $(SYSTEM_PATH) $(CMSIS_BASE_PATH) +vpath %.cpp $(PROJECT_BASE_PATH) + +VPATH+=$(PROJECT_BASE_PATH) + +INCLUDES = -I$(PROJECT_BASE_PATH)/.. +INCLUDES += -I$(VARIANT_PATH) +INCLUDES += -I$(VARIANT_PATH)/.. +INCLUDES += -I$(SYSTEM_PATH) +INCLUDES += -I$(SYSTEM_PATH)/libsam +INCLUDES += -I$(CMSIS_BASE_PATH) + +#------------------------------------------------------------------------------- +ifdef DEBUG +include debug.mk +else +include release.mk +endif + +#------------------------------------------------------------------------------- +# Tools +#------------------------------------------------------------------------------- + +include $(TOOLCHAIN).mk + +#------------------------------------------------------------------------------- +ifdef DEBUG +OUTPUT_OBJ=debug +LIBS_POSTFIX=dbg +else +OUTPUT_OBJ=release +LIBS_POSTFIX=rel +endif + +OUTPUT_BIN=test_$(TOOLCHAIN)_$(LIBS_POSTFIX) +#LIBS=-L../libsam_$(CHIP_NAME)_$(TOOLCHAIN)_rel.a -L../arduino_$(VARIANT)_$(TOOLCHAIN)_rel.a +# +LIBS=-Wl,--start-group -lgcc -lc -lstdc++ -lsam_$(CHIP_NAME)_$(TOOLCHAIN)_$(LIBS_POSTFIX) -larduino_$(VARIANT)_$(TOOLCHAIN)_$(LIBS_POSTFIX) -lvariant_$(VARIANT)_$(TOOLCHAIN)_$(LIBS_POSTFIX) -Wl,--end-group + +LIB_PATH =-L$(PROJECT_BASE_PATH)/.. +LIB_PATH+=-L=/lib/thumb2 +#LIB_PATH+=-L=/../lib/gcc/arm-none-eabi/4.5.2/thumb2 + +LDFLAGS= -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols + +#------------------------------------------------------------------------------- +# CPP source files and objects +#------------------------------------------------------------------------------- +CPP_SRC=$(wildcard $(PROJECT_BASE_PATH)/*.cpp) + +CPP_OBJ_TEMP = $(patsubst %.cpp, %.o, $(notdir $(CPP_SRC))) + +# during development, remove some files +CPP_OBJ_FILTER= + +CPP_OBJ=$(filter-out $(CPP_OBJ_FILTER), $(CPP_OBJ_TEMP)) + +#------------------------------------------------------------------------------- +# Rules +#------------------------------------------------------------------------------- +all: test + +test: create_output $(OUTPUT_BIN) + +.PHONY: create_output +create_output: + @echo --- Preparing $(VARIANT) files in $(OUTPUT_PATH) $(OUTPUT_BIN) + @echo ------------------------- + @echo *$(INCLUDES) + @echo ------------------------- + @echo *$(C_SRC) + @echo ------------------------- + @echo *$(C_OBJ) + @echo ------------------------- + @echo *$(addprefix $(OUTPUT_PATH)/, $(C_OBJ)) + @echo ------------------------- + @echo *$(CPP_SRC) + @echo ------------------------- + @echo *$(CPP_OBJ) + @echo ------------------------- + @echo *$(addprefix $(OUTPUT_PATH)/, $(CPP_OBJ)) + @echo ------------------------- + @echo *$(A_SRC) + @echo ------------------------- + + -@mkdir $(OUTPUT_PATH) 1>NUL 2>&1 + +$(addprefix $(OUTPUT_PATH)/,$(CPP_OBJ)): $(OUTPUT_PATH)/%.o: %.cpp +# @$(CC) -c $(CPPFLAGS) $< -o $@ + @$(CXX) -c $(CPPFLAGS) $< -o $@ +# @$(CXX) -v -c $(CPPFLAGS) $< -o $@ + +$(OUTPUT_BIN): $(addprefix $(OUTPUT_PATH)/, $(C_OBJ)) $(addprefix $(OUTPUT_PATH)/, $(CPP_OBJ)) $(addprefix $(OUTPUT_PATH)/, $(A_OBJ)) + @$(CC) $(LIB_PATH) $(LDFLAGS) -T"$(VARIANT_PATH)/linker_scripts/gcc/flash.ld" -Wl,-Map,$(OUTPUT_PATH)/$@.map -o $(OUTPUT_PATH)/$@.elf $^ $(LIBS) +# @$(CC) $(LIB_PATH) $(LDFLAGS) -T"$(VARIANT_PATH)/linker_scripts/gcc/sram.ld" -Wl,-Map,$(OUTPUT_PATH)/$@.map -o $(OUTPUT_PATH)/$@.elf $^ $(LIBS) + @$(NM) $(OUTPUT_PATH)/$@.elf >$(OUTPUT_PATH)/$@.elf.txt + @$(OBJCOPY) -O binary $(OUTPUT_PATH)/$@.elf $(OUTPUT_PATH)/$@.bin + $(SIZE) $^ $(OUTPUT_PATH)/$@.elf + +.PHONY: clean +clean: + @echo --- Cleaning test files + -@$(RM) $(OUTPUT_PATH)/test.o 1>NUL 2>&1 + -@$(RM) $(OUTPUT_PATH)/$(OUTPUT_BIN).elf 1>NUL 2>&1 + -@$(RM) $(OUTPUT_PATH)/$(OUTPUT_BIN).elf.txt 1>NUL 2>&1 + -@$(RM) $(OUTPUT_PATH)/$(OUTPUT_BIN).bin 1>NUL 2>&1 + -@$(RM) $(OUTPUT_PATH)/$(OUTPUT_BIN).map 1>NUL 2>&1 + +debug: test + @$(GDB) -x "$(VARIANT_PATH)/debug_scripts/gcc/$(VARIANT)_flash.gdb" -ex "reset" -readnow -se $(OUTPUT_PATH)/$(OUTPUT_BIN).elf +# @$(GDB) -w -x "$(VARIANT_PATH)/debug_scripts/gcc/$(VARIANT)_sram.gdb" -ex "reset" -readnow -se $(OUTPUT_PATH)/$(OUTPUT_BIN).elf diff --git a/hardware/sam/cores/sam/validation/build_iar/test.ewd b/hardware/sam/cores/sam/validation/build_iar/test.ewd new file mode 100644 index 000000000..a8513fb89 --- /dev/null +++ b/hardware/sam/cores/sam/validation/build_iar/test.ewd @@ -0,0 +1,1769 @@ + + + + 2 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 1 + + + + + + + + + JLINK_ID + 2 + + 13 + 1 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$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 0 + + + + + + + + + JLINK_ID + 2 + + 13 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + + + + diff --git a/hardware/sam/cores/sam/validation/build_iar/test.ewp b/hardware/sam/cores/sam/validation/build_iar/test.ewp new file mode 100644 index 000000000..c22825fb8 --- /dev/null +++ b/hardware/sam/cores/sam/validation/build_iar/test.ewp @@ -0,0 +1,1834 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + resources + + arduino_due + + + sam3s_ek + + $PROJ_DIR$\..\..\..\..\variants\sam3s_ek\linker_scripts\iar\sam3s_ek_flash.icf + + + $PROJ_DIR$\..\..\..\..\variants\sam3s_ek\debug_scripts\iar\sam3s_ek_flash.mac + + + $PROJ_DIR$\..\..\..\..\variants\sam3s_ek\linker_scripts\iar\sam3s_ek_sram.icf + + + $PROJ_DIR$\..\..\..\..\variants\sam3s_ek\debug_scripts\iar\sam3s_ek_sram.mac + + + + sam3u_ek + + + + $PROJ_DIR$\..\..\libarduino_sam3s_ek_ewarm_dbg.a + + + $PROJ_DIR$\..\..\libsam_sam3s4c_ewarm_dbg.a + + + $PROJ_DIR$\..\..\libvariant_sam3s_ek_ewarm_dbg.a + + + $PROJ_DIR$\..\test.cpp + + + + diff --git a/hardware/sam/cores/sam/validation/test.cpp b/hardware/sam/cores/sam/validation/test.cpp new file mode 100644 index 000000000..7da0fec1a --- /dev/null +++ b/hardware/sam/cores/sam/validation/test.cpp @@ -0,0 +1,81 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "variant.h" + +void setup( void ) +{ + // Initialize the digital pin as an output. + // Pin PIN_LED has a LED connected on most Arduino boards: + pinMode( PIN_LED, OUTPUT ) ; + digitalWrite( PIN_LED, LOW ) ; + + // Initialize the PIN_LED2 digital pin as an output. + pinMode( PIN_LED2, OUTPUT ) ; + digitalWrite( PIN_LED2, HIGH ) ; + + Serial.begin( 115200 ) ; +} + +static void led_step1( void ) +{ +#if defined sam3s_ek + digitalWrite( PIN_LED, HIGH ) ; // set the LED on + digitalWrite( PIN_LED2, LOW ) ; // set the red LED off +#endif /* sam3s_ek */ + +#if defined sam3u_ek + digitalWrite( PIN_LED, HIGH ) ; // set the LED on + digitalWrite( PIN_LED2, LOW ) ; // set the red LED off +#endif /* sam3u_ek */ + +#if defined arduino_due + digitalWrite( PIN_LED, LOW ) ; // set the LED on + digitalWrite( PIN_LED2, LOW ) ; // set the red LED off +#endif /* arduino_due */ +} + +static void led_step2( void ) +{ +#if defined sam3s_ek + digitalWrite( PIN_LED, LOW ) ; // set the LED off + digitalWrite( PIN_LED2, HIGH ) ; // set the red LED on +#endif /* sam3s_ek */ + +#if defined sam3u_ek + digitalWrite( PIN_LED, LOW ) ; // set the LED off + digitalWrite( PIN_LED2, HIGH ) ; // set the red LED on +#endif /* sam3u_ek */ + +#if defined arduino_due + digitalWrite( PIN_LED, HIGH ) ; // set the LED off + digitalWrite( PIN_LED2, HIGH ) ; // set the red LED on +#endif /* arduino_due */ +} + +void loop( void ) +{ + led_step1() ; + delay( 1000 ) ; // wait for a second + led_step2() ; + delay( 1000 ) ; // wait for a second + + Serial.write( '-' ) ; // send a char +// Serial.write( "test1\n" ) ; // send a string +// Serial.write( "test2" ) ; // send another string +} diff --git a/hardware/sam/cores/sam/wiring.c b/hardware/sam/cores/sam/wiring.c new file mode 100644 index 000000000..2b78297f7 --- /dev/null +++ b/hardware/sam/cores/sam/wiring.c @@ -0,0 +1,83 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "Arduino.h" + +#ifdef __cplusplus +extern "C" { +#endif + +uint32_t millis( void ) +{ +// todo: ensure no interrupts + return GetTickCount() ; +} + +uint32_t micros( void ) +{ + uint32_t dwTicks ; + + __disable_irq() ; + dwTicks=SysTick->VAL ; + __enable_irq() ; + + return (GetTickCount()*1000) + ((SysTick->LOAD + 1 - dwTicks)/(SystemCoreClock/1000000)) ; +} + +void delay( uint32_t dwMs ) +{ + Wait( dwMs ) ; +} + +void delayMicroseconds( uint32_t dwUs ) +{ + uint32_t dwStartMicros=micros() ; + + while ( (micros() - dwStartMicros) < dwUs ) + { + // do nothing + } +} + +/* + * Cortex-M3 Systick IT handler + */ +extern void SysTick_Handler( void ) +{ + // Increment tick count each ms + TimeTick_Increment() ; +} + +#if defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */ +extern signed int putchar( signed int c ) ; +/** + * \brief + * + * \param c Character to output. + * + * \return The character that was output. + */ +extern WEAK signed int putchar( signed int c ) +{ + return c ; +} +#endif /* __ICCARM__ */ + +#ifdef __cplusplus +} +#endif diff --git a/hardware/sam/cores/sam/wiring.h b/hardware/sam/cores/sam/wiring.h new file mode 100644 index 000000000..ad13cac66 --- /dev/null +++ b/hardware/sam/cores/sam/wiring.h @@ -0,0 +1,72 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _WIRING_ +#define _WIRING_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * + */ +extern void init( void ) ; + +/** + * \brief Returns the number of milliseconds since the Arduino board began running the current program. + * + * This number will overflow (go back to zero), after approximately 50 days. + * + * \return Number of milliseconds since the program started (uint32_t) + */ +extern uint32_t millis( void ) ; + +/** + * \brief Returns the number of microseconds since the Arduino board began running the current program. + * + * This number will overflow (go back to zero), after approximately 70 minutes. On 16 MHz Arduino boards + * (e.g. Duemilanove and Nano), this function has a resolution of four microseconds (i.e. the value returned is + * always a multiple of four). On 8 MHz Arduino boards (e.g. the LilyPad), this function has a resolution + * of eight microseconds. + * + * \note There are 1,000 microseconds in a millisecond and 1,000,000 microseconds in a second. + */ +extern uint32_t micros( void ) ; + +/** + * \brief Pauses the program for the amount of time (in miliseconds) specified as parameter. + * (There are 1000 milliseconds in a second.) + * + * \param dwMs the number of milliseconds to pause (uint32_t) + */ +extern void delay( uint32_t dwMs ) ; + +/** + * \brief Pauses the program for the amount of time (in microseconds) specified as parameter. + * + * \param dwUs the number of microseconds to pause (uint32_t) + */ +extern void delayMicroseconds( uint32_t dwUs ) ; + + +#ifdef __cplusplus +} +#endif + +#endif /* _WIRING_ */ diff --git a/hardware/sam/cores/sam/wiring_analog.c b/hardware/sam/cores/sam/wiring_analog.c new file mode 100644 index 000000000..da3ba8f44 --- /dev/null +++ b/hardware/sam/cores/sam/wiring_analog.c @@ -0,0 +1,231 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +//#include "wiring_private.h" +#include "Arduino.h" +#include "variant.h" + +#ifdef __cplusplus +extern "C" { +#endif + +eAnalogReference analog_reference = AR_DEFAULT; + +void analogReference(eAnalogReference ulMode) +{ + analog_reference = ulMode; +} + +uint32_t analogRead(uint32_t ulPin) +{ + uint32_t ulValue = 0; + uint32_t ulChannel; + + if (ulPin < A0) + ulPin += A0; + + ulChannel = g_APinDescription[ulPin].ulADCChannelNumber ; + +#if defined __SAM3U4E__ + switch ( g_APinDescription[ulPin].ulAnalogChannel ) + { + // Handling ADC 10 bits channels + case ADC0 : + case ADC1 : + case ADC2 : + case ADC3 : + case ADC4 : + case ADC5 : + case ADC6 : + case ADC7 : + // Enable the corresponding channel + adc_enable_channel( ADC, ulChannel ); + + // Start the ADC + adc_start( ADC ); + + // Wait for end of conversion + while ((adc_get_status(ADC) & (1<TC_CHANNEL+chan; + ch->TC_RA = v; +} + +static void TC_SetRB(Tc *tc, uint32_t chan, uint32_t v ) +{ + TcChannel* ch = &tc->TC_CHANNEL+chan; + ch->TC_RB = v; +} + +static void TC_SetRC(Tc *tc, uint32_t chan, uint32_t v ) +{ + TcChannel* ch = &tc->TC_CHANNEL+chan; + ch->TC_RC = v; +} + +static uint8_t PWMEnabled = 0; +static uint8_t pinEnabled[PINS_COUNT]; +static uint8_t TCChanEnabled[] = {0, 0, 0}; + +void analogOutputInit() { + uint8_t i; + for (i=0; i 96Mhz/2 => 48Mhz as clock. + // To get 1KHz we should use 48000 as TC + // 48Mhz/48000 = 1KHz + const uint32_t TC = VARIANT_MCK / 2 / TC_FREQUENCY; + + // Map value to Timer ranges 0..255=>0..48000 + ulValue = ulValue * TC; + ulValue = ulValue / TC_MAX_DUTY_CYCLE; + + // Setup Timer for this pin + ETCChannel channel = g_APinDescription[ulPin].ulTCChannel; + static const channelToChNo[] = { 0, 0, 1, 1, 2, 2 }; + static const channelToAB[] = { 1, 0, 1, 0, 1, 0 }; + uint32_t chNo = channelToChNo[channel]; + uint32_t chA = channelToAB[channel]; + + if (!TCChanEnabled[chNo]) { + PMC_EnablePeripheral(TC_INTERFACE_ID + chNo); + TC_Configure(TC_INTERFACE, chNo, + TC_CMR_TCCLKS_TIMER_CLOCK1 | + TC_CMR_WAVE | + TC_CMR_WAVSEL_UP_RC | + TC_CMR_ACPA_CLEAR | // RA Compare Effect on OA: clear + TC_CMR_ACPC_SET | // RC Compare Effect on OA: set + TC_CMR_BCPB_CLEAR | // RB Compare Effect on OB: clear + TC_CMR_BCPC_SET); // RC Compare Effect on OB: set + TC_SetRC(TC_INTERFACE, chNo, TC); + } + if (chA) + TC_SetRA(TC_INTERFACE, chNo, ulValue); + else + TC_SetRB(TC_INTERFACE, chNo, ulValue); + if (!pinEnabled[ulPin]) { + PIO_Configure(g_APinDescription[ulPin].pPort, + g_APinDescription[ulPin].ulPinType, + g_APinDescription[ulPin].ulPin, + g_APinDescription[ulPin].ulPinConfiguration); + pinEnabled[ulPin] = 1; + } + if (!TCChanEnabled[chNo]) { + TC_Start(TC_INTERFACE, chNo); + TCChanEnabled[chNo] = 1; + } + return; + } + + // Default to digital write + pinMode(ulPin, OUTPUT); + if (ulValue < 128) + digitalWrite(ulPin, LOW); + else + digitalWrite(ulPin, HIGH); +} + +#ifdef __cplusplus +} +#endif diff --git a/hardware/sam/cores/sam/wiring_analog.h b/hardware/sam/cores/sam/wiring_analog.h new file mode 100644 index 000000000..06a6a9d04 --- /dev/null +++ b/hardware/sam/cores/sam/wiring_analog.h @@ -0,0 +1,64 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _WIRING_ANALOG_ +#define _WIRING_ANALOG_ + +#ifdef __cplusplus + extern "C" { +#endif + +/* + * \brief SAM3 products have only one reference for ADC + */ +typedef enum _eAnalogReference +{ + AR_DEFAULT, +} eAnalogReference ; + +/* + * \brief Configures the reference voltage used for analog input (i.e. the value used as the top of the input range). + * This function is kept only for compatibility with existing AVR based API. + * + * \param ulMmode Should be set to AR_DEFAULT. + */ +extern void analogReference( eAnalogReference ulMode ) ; + +/* + * \brief Writes an analog value (PWM wave) to a pin. + * + * \param ulPin + * \param ulValue + */ +extern void analogWrite( uint32_t ulPin, uint32_t ulValue ) ; + +/* + * \brief Reads the value from the specified analog pin. + * + * \param ulPin + * + * \return Read value from selected pin, if no error. + */ +extern uint32_t analogRead( uint32_t ulPin ) ; + + +#ifdef __cplusplus +} +#endif + +#endif /* _WIRING_ANALOG_ */ diff --git a/hardware/sam/cores/sam/wiring_constants.h b/hardware/sam/cores/sam/wiring_constants.h new file mode 100644 index 000000000..3d8ba03e8 --- /dev/null +++ b/hardware/sam/cores/sam/wiring_constants.h @@ -0,0 +1,92 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _WIRING_CONSTANTS_ +#define _WIRING_CONSTANTS_ + +#ifdef __cplusplus +extern "C"{ +#endif // __cplusplus + +#define HIGH 0x1 +#define LOW 0x0 + +#define INPUT 0x0 +#define OUTPUT 0x1 + +#define true 0x1 +#define false 0x0 + +#define PI 3.1415926535897932384626433832795 +#define HALF_PI 1.5707963267948966192313216916398 +#define TWO_PI 6.283185307179586476925286766559 +#define DEG_TO_RAD 0.017453292519943295769236907684886 +#define RAD_TO_DEG 57.295779513082320876798154814105 + +#define SERIAL 0x0 +#define DISPLAY 0x1 + +#define LSBFIRST 0 +#define MSBFIRST 1 + +#define CHANGE 1 +#define FALLING 2 +#define RISING 3 + +#define DEFAULT 1 +#define EXTERNAL 0 + +// undefine stdlib's abs if encountered +#ifdef abs +#undef abs +#endif // abs + +#define min(a,b) ((a)<(b)?(a):(b)) +#define max(a,b) ((a)>(b)?(a):(b)) +#define abs(x) ((x)>0?(x):-(x)) +#define constrain(amt,low,high) ((amt)<(low)?(low):((amt)>(high)?(high):(amt))) +#define round(x) ((x)>=0?(long)((x)+0.5):(long)((x)-0.5)) +#define radians(deg) ((deg)*DEG_TO_RAD) +#define degrees(rad) ((rad)*RAD_TO_DEG) +#define sq(x) ((x)*(x)) + +#define interrupts() __enable_irq() +#define noInterrupts() __disable_irq() + +#define lowByte(w) ((uint8_t) ((w) & 0xff)) +#define highByte(w) ((uint8_t) ((w) >> 8)) + +#define bitRead(value, bit) (((value) >> (bit)) & 0x01) +#define bitSet(value, bit) ((value) |= (1UL << (bit))) +#define bitClear(value, bit) ((value) &= ~(1UL << (bit))) +#define bitWrite(value, bit, bitvalue) (bitvalue ? bitSet(value, bit) : bitClear(value, bit)) + +typedef unsigned int word; + +#define bit(b) (1UL << (b)) + +// TODO: to be checked +typedef uint8_t boolean ; +typedef uint8_t byte ; + + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus + +#endif /* _WIRING_CONSTANTS_ */ diff --git a/hardware/sam/cores/sam/wiring_digital.c b/hardware/sam/cores/sam/wiring_digital.c new file mode 100644 index 000000000..791ae5b87 --- /dev/null +++ b/hardware/sam/cores/sam/wiring_digital.c @@ -0,0 +1,90 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "Arduino.h" + +#ifdef __cplusplus + extern "C" { +#endif + +extern void pinMode( uint32_t ulPin, uint32_t ulMode ) +{ + if ( g_APinDescription[ulPin].ulPinType == PIO_NOT_A_PIN ) + { + return ; + } + + switch ( ulMode ) + { + case INPUT: + /* Enable peripheral for clocking input */ + PMC_EnablePeripheral( g_APinDescription[ulPin].ulPeripheralId ) ; + PIO_Configure( g_APinDescription[ulPin].pPort, PIO_INPUT, g_APinDescription[ulPin].ulPin, 0 ) ; + break ; + + case OUTPUT: + /* if all pins are output, disable PIO Controller clocking, reduce power consomption */ + if ( g_APinDescription[ulPin].pPort->PIO_OSR == 0xffffffff ) + { + PMC_DisablePeripheral( g_APinDescription[ulPin].ulPeripheralId ) ; + } + PIO_Configure( g_APinDescription[ulPin].pPort, PIO_OUTPUT_1, g_APinDescription[ulPin].ulPin, g_APinDescription[ulPin].ulPinConfiguration ) ; + break ; + + default: + break ; + } +} + +extern void digitalWrite( uint32_t ulPin, uint32_t ulVal ) +{ + /* Handle */ + if ( g_APinDescription[ulPin].ulPinType == PIO_NOT_A_PIN ) + { + return ; + } + + if ( PIO_GetOutputDataStatus( g_APinDescription[ulPin].pPort, g_APinDescription[ulPin].ulPin ) == 0 ) + { + PIO_PullUp( g_APinDescription[ulPin].pPort, g_APinDescription[ulPin].ulPin, 1 ) ; + } + else + { + PIO_SetOutput( g_APinDescription[ulPin].pPort, g_APinDescription[ulPin].ulPin, ulVal, 0, PIO_PULLUP ) ; + } +} + +extern int digitalRead( uint32_t ulPin ) +{ + if ( g_APinDescription[ulPin].ulPinType == PIO_NOT_A_PIN ) + { + return LOW ; + } + + if ( PIO_Get( g_APinDescription[ulPin].pPort, PIO_INPUT, g_APinDescription[ulPin].ulPin ) == 1 ) + { + return HIGH ; + } + + return LOW ; +} + +#ifdef __cplusplus +} +#endif + diff --git a/hardware/sam/cores/sam/wiring_digital.h b/hardware/sam/cores/sam/wiring_digital.h new file mode 100644 index 000000000..449902409 --- /dev/null +++ b/hardware/sam/cores/sam/wiring_digital.h @@ -0,0 +1,69 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _WIRING_DIGITAL_ +#define _WIRING_DIGITAL_ + +#ifdef __cplusplus + extern "C" { +#endif + +/** + * \brief Configures the specified pin to behave either as an input or an output. See the description of digital pins for details. + * + * \param ulPin The number of the pin whose mode you wish to set + * \param ulMode Either INPUT or OUTPUT + */ +extern void pinMode( uint32_t dwPin, uint32_t dwMode ) ; + +/** + * \brief Write a HIGH or a LOW value to a digital pin. + * + * If the pin has been configured as an OUTPUT with pinMode(), its voltage will be set to the + * corresponding value: 5V (or 3.3V on 3.3V boards) for HIGH, 0V (ground) for LOW. + * + * If the pin is configured as an INPUT, writing a HIGH value with digitalWrite() will enable an internal + * 20K pullup resistor (see the tutorial on digital pins). Writing LOW will disable the pullup. The pullup + * resistor is enough to light an LED dimly, so if LEDs appear to work, but very dimly, this is a likely + * cause. The remedy is to set the pin to an output with the pinMode() function. + * + * \note Digital pin PIN_LED is harder to use as a digital input than the other digital pins because it has an LED + * and resistor attached to it that's soldered to the board on most boards. If you enable its internal 20k pull-up + * resistor, it will hang at around 1.7 V instead of the expected 5V because the onboard LED and series resistor + * pull the voltage level down, meaning it always returns LOW. If you must use pin PIN_LED as a digital input, use an + * external pull down resistor. + * + * \param dwPin the pin number + * \param dwVal HIGH or LOW + */ +extern void digitalWrite( uint32_t dwPin, uint32_t dwVal ) ; + +/** + * \brief Reads the value from a specified digital pin, either HIGH or LOW. + * + * \param ulPin The number of the digital pin you want to read (int) + * + * \return HIGH or LOW + */ +extern int digitalRead( uint32_t ulPin ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* _WIRING_DIGITAL_ */ diff --git a/hardware/sam/cores/sam/wiring_private.h b/hardware/sam/cores/sam/wiring_private.h new file mode 100644 index 000000000..2938d3eac --- /dev/null +++ b/hardware/sam/cores/sam/wiring_private.h @@ -0,0 +1,40 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef WiringPrivate_h +#define WiringPrivate_h + +#include +#include +#include + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "libsam/chip.h" +#include "wiring_constants.h" + +#ifdef __cplusplus +} // extern "C" + +#include "HardwareSerial.h" + +#endif + +#endif diff --git a/hardware/sam/cores/sam/wiring_pulse.cpp b/hardware/sam/cores/sam/wiring_pulse.cpp new file mode 100644 index 000000000..40f1261ae --- /dev/null +++ b/hardware/sam/cores/sam/wiring_pulse.cpp @@ -0,0 +1,61 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "Arduino.h" +#include "wiring_private.h" + +/* Measures the length (in microseconds) of a pulse on the pin; state is HIGH + * or LOW, the type of pulse to measure. Works on pulses from 2-3 microseconds + * to 3 minutes in length, but must be called at least a few dozen microseconds + * before the start of the pulse. */ +extern uint32_t pulseIn( uint32_t pin, uint32_t state, uint32_t timeout ) +{ + // cache the port and bit of the pin in order to speed up the + // pulse width measuring loop and achieve finer resolution. calling + // digitalRead() instead yields much coarser resolution. + PinDescription p = g_APinDescription[pin]; + uint32_t width = 0; // keep initialization out of time critical area + + // convert the timeout from microseconds to a number of times through + // the initial loop; it takes 22 clock cycles per iteration. + uint32_t numloops = 0; + uint32_t maxloops = microsecondsToClockCycles(timeout) / 22; + + // wait for any previous pulse to end + while (PIO_Get(p.pPort, PIO_INPUT, p.ulPin) == state) + if (numloops++ == maxloops) + return 0; + + // wait for the pulse to start + while (PIO_Get(p.pPort, PIO_INPUT, p.ulPin) != state) + if (numloops++ == maxloops) + return 0; + + // wait for the pulse to stop + while (PIO_Get(p.pPort, PIO_INPUT, p.ulPin) == state) { + if (numloops++ == maxloops) + return 0; + width++; + } + + // convert the reading to microseconds. The loop has been determined + // to be 22 clock cycles long and have about 16 clocks between the edge + // and the start of the loop. There will be some error introduced by + // the interrupt handlers. + return clockCyclesToMicroseconds(width * 22 + 16); +} diff --git a/hardware/sam/cores/sam/wiring_pulse.h b/hardware/sam/cores/sam/wiring_pulse.h new file mode 100644 index 000000000..f32896984 --- /dev/null +++ b/hardware/sam/cores/sam/wiring_pulse.h @@ -0,0 +1,39 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _WIRING_PULSE_ +#define _WIRING_PULSE_ + +#ifdef __cplusplus + extern "C" { +#endif + +/* + * \brief Measures the length (in microseconds) of a pulse on the pin; state is HIGH + * or LOW, the type of pulse to measure. Works on pulses from 2-3 microseconds + * to 3 minutes in length, but must be called at least a few dozen microseconds + * before the start of the pulse. + */ +extern uint32_t pulseIn( uint32_t ulPin, uint32_t ulState, uint32_t ulTimeout = 1000000L ) ; + + +#ifdef __cplusplus +} +#endif + +#endif /* _WIRING_PULSE_ */ diff --git a/hardware/sam/cores/sam/wiring_shift.c b/hardware/sam/cores/sam/wiring_shift.c new file mode 100644 index 000000000..30d3f43b6 --- /dev/null +++ b/hardware/sam/cores/sam/wiring_shift.c @@ -0,0 +1,71 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "Arduino.h" + +#ifdef __cplusplus +extern "C"{ +#endif + +extern uint32_t shiftIn( uint32_t ulDataPin, uint32_t ulClockPin, uint32_t ulBitOrder ) +{ + uint8_t value = 0 ; + uint8_t i ; + + for ( i=0 ; i < 8 ; ++i ) + { + digitalWrite( ulClockPin, HIGH ) ; + + if ( ulBitOrder == LSBFIRST ) + { + value |= digitalRead( ulDataPin ) << i ; + } + else + { + value |= digitalRead( ulDataPin ) << (7 - i) ; + } + + digitalWrite( ulClockPin, LOW ) ; + } + + return value ; +} + +extern void shiftOut( uint32_t ulDataPin, uint32_t ulClockPin, uint32_t ulBitOrder, uint32_t ulVal ) +{ + uint8_t i ; + + for ( i=0 ; i < 8 ; i++ ) + { + if ( ulBitOrder == LSBFIRST ) + { + digitalWrite( ulDataPin, !!(ulVal & (1 << i)) ) ; + } + else + { + digitalWrite( ulDataPin, !!(ulVal & (1 << (7 - i))) ) ; + } + + digitalWrite( ulClockPin, HIGH ) ; + digitalWrite( ulClockPin, LOW ) ; + } +} + +#ifdef __cplusplus +} // extern "C" +#endif diff --git a/hardware/sam/cores/sam/wiring_shift.h b/hardware/sam/cores/sam/wiring_shift.h new file mode 100644 index 000000000..f33d84856 --- /dev/null +++ b/hardware/sam/cores/sam/wiring_shift.h @@ -0,0 +1,42 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _WIRING_SHIFT_ +#define _WIRING_SHIFT_ + +#ifdef __cplusplus + extern "C" { +#endif + +/* + * \brief + */ +extern uint32_t shiftIn( uint32_t ulDataPin, uint32_t ulClockPin, uint32_t ulBitOrder ) ; + + +/* + * \brief + */ +extern void shiftOut( uint32_t ulDataPin, uint32_t ulClockPin, uint32_t ulBitOrder, uint32_t ulVal ) ; + + +#ifdef __cplusplus +} +#endif + +#endif /* _WIRING_SHIFT_ */ diff --git a/hardware/sam/libraries/SPI/SPI.cpp b/hardware/sam/libraries/SPI/SPI.cpp new file mode 100644 index 000000000..bd7a6433a --- /dev/null +++ b/hardware/sam/libraries/SPI/SPI.cpp @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2010 by Cristian Maglie + * SPI Master library for arduino. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of either the GNU General Public License version 2 + * or the GNU Lesser General Public License version 2.1, both as + * published by the Free Software Foundation. + */ + +#include "SPI.h" + +SPIClass::SPIClass(Spi *_spi, uint32_t _id, void(*_initCb)(void)) : + spi(_spi), id(_id), initCb(_initCb) { + // Empty +} + +void SPIClass::begin() { + initCb(); + + // Set CS on NPCS3 + SPI_Configure(spi, id, SPI_MR_MSTR | SPI_MR_PCS(0x07)); + SPI_Enable( spi); + setClockDivider(1); +} + +void SPIClass::end() { + SPI_Disable( spi); +} + +void SPIClass::setBitOrder(uint8_t bitOrder) { + // Not supported +} + +void SPIClass::setDataMode(uint8_t _mode) { + mode = _mode; + SPI_ConfigureNPCS(spi, 3, mode | SPI_CSR_SCBR(divider)); +} + +void SPIClass::setClockDivider(uint8_t _divider) { + divider = _divider; + SPI_ConfigureNPCS(spi, 3, mode | SPI_CSR_SCBR(divider)); +} + +byte SPIClass::transfer(byte _data) { + SPI_Write(spi, 0, _data); + return SPI_Read(spi); +} + +void SPIClass::attachInterrupt(void) { + // Should be enableInterrupt() +} + +void SPIClass::detachInterrupt(void) { + // Should be disableInterrupt() +} + +#if SPI_INTERFACES_COUNT > 0 +static void SPI0_Init(void) { + PIO_Configure(g_APinDescription[PIN_SPI_MOSI].pPort, + g_APinDescription[PIN_SPI_MOSI].ulPinType, + g_APinDescription[PIN_SPI_MOSI].ulPin, + g_APinDescription[PIN_SPI_MOSI].ulPinConfiguration); + PIO_Configure(g_APinDescription[PIN_SPI_MISO].pPort, + g_APinDescription[PIN_SPI_MISO].ulPinType, + g_APinDescription[PIN_SPI_MISO].ulPin, + g_APinDescription[PIN_SPI_MISO].ulPinConfiguration); + PIO_Configure(g_APinDescription[PIN_SPI_SCK].pPort, + g_APinDescription[PIN_SPI_SCK].ulPinType, + g_APinDescription[PIN_SPI_SCK].ulPin, + g_APinDescription[PIN_SPI_SCK].ulPinConfiguration); +} + +SPIClass SPI0(SPI_INTERFACE, SPI_INTERFACE_ID, SPI0_Init); +#endif diff --git a/hardware/sam/libraries/SPI/SPI.h b/hardware/sam/libraries/SPI/SPI.h new file mode 100644 index 000000000..ceeaa3f52 --- /dev/null +++ b/hardware/sam/libraries/SPI/SPI.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2010 by Cristian Maglie + * SPI Master library for arduino. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of either the GNU General Public License version 2 + * or the GNU Lesser General Public License version 2.1, both as + * published by the Free Software Foundation. + */ + +#ifndef _SPI_H_INCLUDED +#define _SPI_H_INCLUDED + +#include "variant.h" +#include + +#define SPI_CLOCK_DIV4 0x00 +#define SPI_CLOCK_DIV16 0x01 +#define SPI_CLOCK_DIV64 0x02 +#define SPI_CLOCK_DIV128 0x03 +#define SPI_CLOCK_DIV2 0x04 +#define SPI_CLOCK_DIV8 0x05 +#define SPI_CLOCK_DIV32 0x06 +#define SPI_CLOCK_DIV64 0x07 + +#define SPI_MODE0 0x00 +#define SPI_MODE1 0x02 +#define SPI_MODE2 0x01 +#define SPI_MODE3 0x03 + +#define SPI_MODE_MASK 0x03 // CPOL = bit 3, CPHA = bit 2 on SPCR +#define SPI_CLOCK_MASK 0x03 // SPR1 = bit 1, SPR0 = bit 0 on SPCR +#define SPI_2XCLOCK_MASK 0x01 // SPI2X = bit 0 on SPSR + +class SPIClass { + public: + SPIClass(Spi *_spi, uint32_t _id, void(*_initCb)(void)); + + byte transfer(byte _data); + + // SPI Configuration methods + + void attachInterrupt(void); + void detachInterrupt(void); // Default + + void begin(void); // Default + void end(void); + + void setBitOrder(uint8_t); + void setDataMode(uint8_t); + void setClockDivider(uint8_t); + + private: + Spi *spi; + uint32_t id, divider, mode; + void (*initCb)(void); +}; + +#if SPI_INTERFACES_COUNT > 0 +extern SPIClass SPI0; +#endif + +#endif diff --git a/hardware/sam/libraries/SPI/examples/BarometricPressureSensor/BarometricPressureSensor.pde b/hardware/sam/libraries/SPI/examples/BarometricPressureSensor/BarometricPressureSensor.pde new file mode 100644 index 000000000..9d77a4261 --- /dev/null +++ b/hardware/sam/libraries/SPI/examples/BarometricPressureSensor/BarometricPressureSensor.pde @@ -0,0 +1,143 @@ +/* + SCP1000 Barometric Pressure Sensor Display + + Shows the output of a Barometric Pressure Sensor on a + Uses the SPI library. For details on the sensor, see: + http://www.sparkfun.com/commerce/product_info.php?products_id=8161 + http://www.vti.fi/en/support/obsolete_products/pressure_sensors/ + + This sketch adapted from Nathan Seidle's SCP1000 example for PIC: + http://www.sparkfun.com/datasheets/Sensors/SCP1000-Testing.zip + + Circuit: + SCP1000 sensor attached to pins 6, 7, 10 - 13: + DRDY: pin 6 + CSB: pin 7 + MOSI: pin 11 + MISO: pin 12 + SCK: pin 13 + + created 31 July 2010 + modified 14 August 2010 + by Tom Igoe + */ + +// the sensor communicates using SPI, so include the library: +#include + +//Sensor's memory register addresses: +const int PRESSURE = 0x1F; //3 most significant bits of pressure +const int PRESSURE_LSB = 0x20; //16 least significant bits of pressure +const int TEMPERATURE = 0x21; //16 bit temperature reading +const byte READ = 0b11111100; // SCP1000's read command +const byte WRITE = 0b00000010; // SCP1000's write command + +// pins used for the connection with the sensor +// the other you need are controlled by the SPI library): +const int dataReadyPin = 6; +const int chipSelectPin = 7; + +void setup() { + Serial.begin(9600); + + // start the SPI library: + SPI.begin(); + + // initalize the data ready and chip select pins: + pinMode(dataReadyPin, INPUT); + pinMode(chipSelectPin, OUTPUT); + + //Configure SCP1000 for low noise configuration: + writeRegister(0x02, 0x2D); + writeRegister(0x01, 0x03); + writeRegister(0x03, 0x02); + // give the sensor time to set up: + delay(100); +} + +void loop() { + //Select High Resolution Mode + writeRegister(0x03, 0x0A); + + // don't do anything until the data ready pin is high: + if (digitalRead(dataReadyPin) == HIGH) { + //Read the temperature data + int tempData = readRegister(0x21, 2); + + // convert the temperature to celsius and display it: + float realTemp = (float)tempData / 20.0; + Serial.print("Temp[C]="); + Serial.print(realTemp); + + + //Read the pressure data highest 3 bits: + byte pressure_data_high = readRegister(0x1F, 1); + pressure_data_high &= 0b00000111; //you only needs bits 2 to 0 + + //Read the pressure data lower 16 bits: + unsigned int pressure_data_low = readRegister(0x20, 2); + //combine the two parts into one 19-bit number: + long pressure = ((pressure_data_high << 16) | pressure_data_low)/4; + + // display the temperature: + Serial.println("\tPressure [Pa]=" + String(pressure)); + } +} + +//Read from or write to register from the SCP1000: +unsigned int readRegister(byte thisRegister, int bytesToRead ) { + byte inByte = 0; // incoming byte from the SPI + unsigned int result = 0; // result to return + Serial.print(thisRegister, BIN); + Serial.print("\t"); + // SCP1000 expects the register name in the upper 6 bits + // of the byte. So shift the bits left by two bits: + thisRegister = thisRegister << 2; + // now combine the address and the command into one byte + byte dataToSend = thisRegister & READ; + Serial.println(thisRegister, BIN); + // take the chip select low to select the device: + digitalWrite(chipSelectPin, LOW); + // send the device the register you want to read: + SPI.transfer(dataToSend); + // send a value of 0 to read the first byte returned: + result = SPI.transfer(0x00); + // decrement the number of bytes left to read: + bytesToRead--; + // if you still have another byte to read: + if (bytesToRead > 0) { + // shift the first byte left, then get the second byte: + result = result << 8; + inByte = SPI.transfer(0x00); + // combine the byte you just got with the previous one: + result = result | inByte; + // decrement the number of bytes left to read: + bytesToRead--; + } + // take the chip select high to de-select: + digitalWrite(chipSelectPin, HIGH); + // return the result: + return(result); +} + + +//Sends a write command to SCP1000 + +void writeRegister(byte thisRegister, byte thisValue) { + + // SCP1000 expects the register address in the upper 6 bits + // of the byte. So shift the bits left by two bits: + thisRegister = thisRegister << 2; + // now combine the register address and the command into one byte: + byte dataToSend = thisRegister | WRITE; + + // take the chip select low to select the device: + digitalWrite(chipSelectPin, LOW); + + SPI.transfer(dataToSend); //Send register location + SPI.transfer(thisValue); //Send value to record into register + + // take the chip select high to de-select: + digitalWrite(chipSelectPin, HIGH); +} + diff --git a/hardware/sam/libraries/SPI/examples/DigitalPotControl/DigitalPotControl.pde b/hardware/sam/libraries/SPI/examples/DigitalPotControl/DigitalPotControl.pde new file mode 100644 index 000000000..ef97dae88 --- /dev/null +++ b/hardware/sam/libraries/SPI/examples/DigitalPotControl/DigitalPotControl.pde @@ -0,0 +1,71 @@ +/* + Digital Pot Control + + This example controls an Analog Devices AD5206 digital potentiometer. + The AD5206 has 6 potentiometer channels. Each channel's pins are labeled + A - connect this to voltage + W - this is the pot's wiper, which changes when you set it + B - connect this to ground. + + The AD5206 is SPI-compatible,and to command it, you send two bytes, + one with the channel number (0 - 5) and one with the resistance value for the + channel (0 - 255). + + The circuit: + * All A pins of AD5206 connected to +5V + * All B pins of AD5206 connected to ground + * An LED and a 220-ohm resisor in series connected from each W pin to ground + * CS - to digital pin 10 (SS pin) + * SDI - to digital pin 11 (MOSI pin) + * CLK - to digital pin 13 (SCK pin) + + created 10 Aug 2010 + by Tom Igoe + + Thanks to Heather Dewey-Hagborg for the original tutorial, 2005 + +*/ + + +// inslude the SPI library: +#include + + +// set pin 10 as the slave select for the digital pot: +const int slaveSelectPin = 10; + +void setup() { + // set the slaveSelectPin as an output: + pinMode (slaveSelectPin, OUTPUT); + // initialize SPI: + SPI.begin(); +} + +void loop() { + // go through the six channels of the digital pot: + for (int channel = 0; channel < 6; channel++) { + // change the resistance on this channel from min to max: + for (int level = 0; level < 255; level++) { + digitalPotWrite(channel, level); + delay(10); + } + // wait a second at the top: + delay(100); + // change the resistance on this channel from max to min: + for (int level = 0; level < 255; level++) { + digitalPotWrite(channel, 255 - level); + delay(10); + } + } + +} + +int digitalPotWrite(int address, int value) { + // take the SS pin low to select the chip: + digitalWrite(slaveSelectPin,LOW); + // send in the address and value via SPI: + SPI.transfer(address); + SPI.transfer(value); + // take the SS pin high to de-select the chip: + digitalWrite(slaveSelectPin,HIGH); +} \ No newline at end of file diff --git a/hardware/sam/libraries/SPI/keywords.txt b/hardware/sam/libraries/SPI/keywords.txt new file mode 100644 index 000000000..fa7616581 --- /dev/null +++ b/hardware/sam/libraries/SPI/keywords.txt @@ -0,0 +1,36 @@ +####################################### +# Syntax Coloring Map SPI +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +SPI KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### +begin KEYWORD2 +end KEYWORD2 +transfer KEYWORD2 +setBitOrder KEYWORD2 +setDataMode KEYWORD2 +setClockDivider KEYWORD2 + + +####################################### +# Constants (LITERAL1) +####################################### +SPI_CLOCK_DIV4 LITERAL1 +SPI_CLOCK_DIV16 LITERAL1 +SPI_CLOCK_DIV64 LITERAL1 +SPI_CLOCK_DIV128 LITERAL1 +SPI_CLOCK_DIV2 LITERAL1 +SPI_CLOCK_DIV8 LITERAL1 +SPI_CLOCK_DIV32 LITERAL1 +SPI_CLOCK_DIV64 LITERAL1 +SPI_MODE0 LITERAL1 +SPI_MODE1 LITERAL1 +SPI_MODE2 LITERAL1 +SPI_MODE3 LITERAL1 \ No newline at end of file diff --git a/hardware/sam/libraries/Wire/Wire.cpp b/hardware/sam/libraries/Wire/Wire.cpp new file mode 100644 index 000000000..67383ac3f --- /dev/null +++ b/hardware/sam/libraries/Wire/Wire.cpp @@ -0,0 +1,348 @@ +/* + * TwoWire.h - TWI/I2C library for Arduino Due + * Copyright (c) 2011 Cristian Maglie . + * All rights reserved. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern "C" { +#include +#include "twi.h" +} + +#include "Wire.h" + +static inline bool TWI_FailedAcknowledge(Twi *pTwi) { + return pTwi->TWI_SR & TWI_SR_NACK; +} + +static inline bool TWI_WaitTransferComplete(Twi *_twi, uint32_t _timeout) { + while (!TWI_TransferComplete(_twi)) { + if (TWI_FailedAcknowledge(_twi)) + return false; + if (--_timeout == 0) + return false; + } + return true; +} + +static inline bool TWI_WaitByteSent(Twi *_twi, uint32_t _timeout) { + while (!TWI_ByteSent(_twi)) { + if (TWI_FailedAcknowledge(_twi)) + return false; + if (--_timeout == 0) + return false; + } + return true; +} + +static inline bool TWI_WaitByteReceived(Twi *_twi, uint32_t _timeout) { + while (!TWI_ByteReceived(_twi)) { + if (TWI_FailedAcknowledge(_twi)) + return false; + if (--_timeout == 0) + return false; + } + return true; +} + +static inline bool TWI_STATUS_SVREAD(uint32_t status) { + return (status & TWI_SR_SVREAD) == TWI_SR_SVREAD; +} + +static inline bool TWI_STATUS_SVACC(uint32_t status) { + return (status & TWI_SR_SVACC) == TWI_SR_SVACC; +} + +static inline bool TWI_STATUS_GACC(uint32_t status) { + return (status & TWI_SR_GACC) == TWI_SR_GACC; +} + +static inline bool TWI_STATUS_EOSACC(uint32_t status) { + return (status & TWI_SR_EOSACC) == TWI_SR_EOSACC; +} + +static inline bool TWI_STATUS_NACK(uint32_t status) { + return (status & TWI_SR_NACK) == TWI_SR_NACK; +} + +TwoWire::TwoWire(Twi *_twi, void(*_beginCb)(void)) : + twi(_twi), rxBufferIndex(0), rxBufferLength(0), txAddress(0), + txBufferLength(0), srvBufferIndex(0), srvBufferLength(0), status( + UNINITIALIZED), onBeginCallback(_beginCb) { + // Empty +} + +void TwoWire::begin(void) { + if (onBeginCallback) + onBeginCallback(); + + // Disable PDC channel + twi->TWI_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS; + + TWI_ConfigureMaster(twi, TWI_CLOCK, VARIANT_MCK); + status = MASTER_IDLE; +} + +void TwoWire::begin(uint8_t address) { + if (onBeginCallback) + onBeginCallback(); + + // Disable PDC channel + twi->TWI_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS; + + TWI_ConfigureSlave(twi, address); + status = SLAVE_IDLE; + TWI_EnableIt(twi, TWI_IER_SVACC); + //| TWI_IER_RXRDY | TWI_IER_TXRDY | TWI_IER_TXCOMP); +} + +void TwoWire::begin(int address) { + begin((uint8_t) address); +} + +uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity) { + if (quantity > BUFFER_LENGTH) + quantity = BUFFER_LENGTH; + + // perform blocking read into buffer + int readed = 0; + TWI_StartRead(twi, address, 0, 0); + do { + // Stop condition must be set during the reception of last byte + if (readed + 1 == quantity) + TWI_SendSTOPCondition( twi); + + TWI_WaitByteReceived(twi, RECV_TIMEOUT); + rxBuffer[readed++] = TWI_ReadByte(twi); + } while (readed < quantity); + TWI_WaitTransferComplete(twi, RECV_TIMEOUT); + + // set rx buffer iterator vars + rxBufferIndex = 0; + rxBufferLength = readed; + + return readed; +} + +uint8_t TwoWire::requestFrom(int address, int quantity) { + return requestFrom((uint8_t) address, (uint8_t) quantity); +} + +void TwoWire::beginTransmission(uint8_t address) { + status = MASTER_SEND; + + // save address of target and empty buffer + txAddress = address; + txBufferLength = 0; +} + +void TwoWire::beginTransmission(int address) { + beginTransmission((uint8_t) address); +} + +uint8_t TwoWire::endTransmission(void) { + // transmit buffer (blocking) + TWI_StartWrite(twi, txAddress, 0, 0, txBuffer[0]); + TWI_WaitByteSent(twi, XMIT_TIMEOUT); + int sent = 1; + while (sent < txBufferLength) { + TWI_WriteByte(twi, txBuffer[sent++]); + TWI_WaitByteSent(twi, XMIT_TIMEOUT); + } + TWI_Stop( twi); + TWI_WaitTransferComplete(twi, XMIT_TIMEOUT); + + // empty buffer + txBufferLength = 0; + + status = MASTER_IDLE; + return sent; +} + +void TwoWire::write(uint8_t data) { + if (status == MASTER_SEND) { + if (txBufferLength >= BUFFER_LENGTH) + return; + txBuffer[txBufferLength++] = data; + } else { + if (srvBufferLength >= BUFFER_LENGTH) + return; + srvBuffer[srvBufferLength++] = data; + } +} + +void TwoWire::write(const uint8_t *data, size_t quantity) { + if (status == MASTER_SEND) { + for (size_t i = 0; i < quantity; ++i) { + if (txBufferLength >= BUFFER_LENGTH) + return; + txBuffer[txBufferLength++] = data[i]; + } + } else { + for (size_t i = 0; i < quantity; ++i) { + if (srvBufferLength >= BUFFER_LENGTH) + return; + srvBuffer[srvBufferLength++] = data[i]; + } + } +} + +void TwoWire::write(const char *data) { + write((uint8_t*) data, strlen(data)); +} + +int TwoWire::available(void) { + return rxBufferLength - rxBufferIndex; +} + +int TwoWire::read(void) { + if (rxBufferIndex < rxBufferLength) + return rxBuffer[rxBufferIndex++]; + return -1; +} + +int TwoWire::peek(void) { + if (rxBufferIndex < rxBufferLength) + return rxBuffer[rxBufferIndex]; + return -1; +} + +void TwoWire::flush(void) { + // Do nothing, use endTransmission(..) to force + // data transfer. +} + +void TwoWire::onReceive(void(*function)(int)) { + onReceiveCallback = function; +} + +void TwoWire::onRequest(void(*function)(void)) { + onRequestCallback = function; +} + +void TwoWire::onService(void) { + // Retrieve interrupt status + uint32_t sr = TWI_GetStatus(twi); + + if (status == SLAVE_IDLE && TWI_STATUS_SVACC(sr)) { + TWI_DisableIt(twi, TWI_IDR_SVACC); + TWI_EnableIt(twi, TWI_IER_RXRDY | TWI_IER_GACC | TWI_IER_NACK + | TWI_IER_EOSACC | TWI_IER_SCL_WS | TWI_IER_TXCOMP); + + srvBufferLength = 0; + srvBufferIndex = 0; + + // Detect if we should go into RECV or SEND status + // SVREAD==1 means *master* reading -> SLAVE_SEND + if (!TWI_STATUS_SVREAD(sr)) { + status = SLAVE_RECV; + } else { + status = SLAVE_SEND; + + // Alert calling program to generate a response ASAP + if (onRequestCallback) + onRequestCallback(); + else + // create a default 1-byte response + write((uint8_t) 0); + } + } + + if (status != SLAVE_IDLE) { + if (TWI_STATUS_TXCOMP(sr) && TWI_STATUS_EOSACC(sr)) { + if (status == SLAVE_RECV && onReceiveCallback) { + // Copy data into rxBuffer + // (allows to receive another packet while the + // user program reads actual data) + for (uint8_t i = 0; i < srvBufferLength; ++i) + rxBuffer[i] = srvBuffer[i]; + rxBufferIndex = 0; + rxBufferLength = srvBufferLength; + + // Alert calling program + onReceiveCallback( rxBufferLength); + } + + // Transfer completed + TWI_EnableIt(twi, TWI_SR_SVACC); + TWI_DisableIt(twi, TWI_IDR_RXRDY | TWI_IDR_GACC | TWI_IDR_NACK + | TWI_IDR_EOSACC | TWI_IDR_SCL_WS | TWI_IER_TXCOMP); + status = SLAVE_IDLE; + } + } + + if (status == SLAVE_RECV) { + if (TWI_STATUS_RXRDY(sr)) { + if (srvBufferLength < BUFFER_LENGTH) + srvBuffer[srvBufferLength++] = TWI_ReadByte(twi); + } + } + + if (status == SLAVE_SEND) { + if (TWI_STATUS_TXRDY(sr) && !TWI_STATUS_NACK(sr)) { + uint8_t c = 'x'; + if (srvBufferIndex < srvBufferLength) + c = srvBuffer[srvBufferIndex++]; + TWI_WriteByte(twi, c); + } + } +} + +#if WIRE_INTERFACES_COUNT > 0 +static void Wire_Init(void) { + PMC_EnablePeripheral( WIRE_INTERFACE_ID); + PIO_Configure(g_APinDescription[PIN_WIRE_SDA].pPort, + g_APinDescription[PIN_WIRE_SDA].ulPinType, + g_APinDescription[PIN_WIRE_SDA].ulPin, + g_APinDescription[PIN_WIRE_SDA].ulPinConfiguration); + PIO_Configure(g_APinDescription[PIN_WIRE_SCL].pPort, + g_APinDescription[PIN_WIRE_SCL].ulPinType, + g_APinDescription[PIN_WIRE_SCL].ulPin, + g_APinDescription[PIN_WIRE_SCL].ulPinConfiguration); + + NVIC_DisableIRQ(TWI1_IRQn); + NVIC_ClearPendingIRQ(TWI1_IRQn); + NVIC_SetPriority(TWI1_IRQn, 0); + NVIC_EnableIRQ(TWI1_IRQn); +} + +TwoWire Wire = TwoWire(WIRE_INTERFACE, Wire_Init); + +void WIRE_ISR_HANDLER(void) { + Wire.onService(); +} +#endif + +#if WIRE_INTERFACES_COUNT > 1 +static void Wire1_Init(void) { + PMC_EnablePeripheral( WIRE1_INTERFACE_ID); + PIO_Configure(g_APinDescription[PIN_WIRE1_SDA].pPort, + g_APinDescription[PIN_WIRE1_SDA].ulPinType, + g_APinDescription[PIN_WIRE1_SDA].ulPin, + g_APinDescription[PIN_WIRE1_SDA].ulPinConfiguration); + PIO_Configure(g_APinDescription[PIN_WIRE1_SCL].pPort, + g_APinDescription[PIN_WIRE1_SCL].ulPinType, + g_APinDescription[PIN_WIRE1_SCL].ulPin, + g_APinDescription[PIN_WIRE1_SCL].ulPinConfiguration); +} + +TwoWire Wire1 = TwoWire(WIRE1_INTERFACE, Wire1_Init); + +void WIRE1_ISR_HANDLER(void) { + Wire1.onService(); +} +#endif diff --git a/hardware/sam/libraries/Wire/Wire.h b/hardware/sam/libraries/Wire/Wire.h new file mode 100644 index 000000000..b5edc2425 --- /dev/null +++ b/hardware/sam/libraries/Wire/Wire.h @@ -0,0 +1,107 @@ +/* + * TwoWire.h - TWI/I2C library for Arduino Due + * Copyright (c) 2011 Cristian Maglie . + * All rights reserved. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef TwoWire_h +#define TwoWire_h + +#include "Stream.h" +#include "twi.h" +#include "variant.h" + +#define BUFFER_LENGTH 32 + +class TwoWire: public Stream { +public: + TwoWire(Twi *twi, void(*begin_cb)(void)); + void begin(); + void begin(uint8_t); + void begin(int); + void beginTransmission(uint8_t); + void beginTransmission(int); + uint8_t endTransmission(void); + uint8_t requestFrom(uint8_t, uint8_t); + uint8_t requestFrom(int, int); + virtual void write(uint8_t); + virtual void write(const char *); + virtual void write(const uint8_t *, size_t); + virtual int available(void); + virtual int read(void); + virtual int peek(void); + virtual void flush(void); + void onReceive(void(*)(int)); + void onRequest(void(*)(void)); + + void onService(void); + +private: + // RX Buffer + uint8_t rxBuffer[BUFFER_LENGTH]; + uint8_t rxBufferIndex; + uint8_t rxBufferLength; + + // TX Buffer + uint8_t txAddress; + uint8_t txBuffer[BUFFER_LENGTH]; + uint8_t txBufferLength; + + // Service buffer + uint8_t srvBuffer[BUFFER_LENGTH]; + uint8_t srvBufferIndex; + uint8_t srvBufferLength; + + // Callback user functions + void (*onRequestCallback)(void); + void (*onReceiveCallback)(int); + + // Called before initialization + void (*onBeginCallback)(void); + + // TWI instance + Twi *twi; + + // TWI state + enum TwoWireStatus { + UNINITIALIZED, + MASTER_IDLE, + MASTER_SEND, + MASTER_RECV, + SLAVE_IDLE, + SLAVE_RECV, + SLAVE_SEND + }; + TwoWireStatus status; + + // TWI clock frequency + static const uint32_t TWI_CLOCK = 100000; + + // Timeouts ( + static const uint32_t RECV_TIMEOUT = 100000; + static const uint32_t XMIT_TIMEOUT = 100000; +}; + +#if WIRE_INTERFACES_COUNT > 0 +extern TwoWire Wire; +#endif +#if WIRE_INTERFACES_COUNT > 1 +extern TwoWire Wire1; +#endif + +#endif + diff --git a/hardware/sam/libraries/Wire/examples/SFRRanger_reader/SFRRanger_reader.pde b/hardware/sam/libraries/Wire/examples/SFRRanger_reader/SFRRanger_reader.pde new file mode 100644 index 000000000..9c41c18f1 --- /dev/null +++ b/hardware/sam/libraries/Wire/examples/SFRRanger_reader/SFRRanger_reader.pde @@ -0,0 +1,87 @@ +// I2C SRF10 or SRF08 Devantech Ultrasonic Ranger Finder +// by Nicholas Zambetti +// and James Tichenor + +// Demonstrates use of the Wire library reading data from the +// Devantech Utrasonic Rangers SFR08 and SFR10 + +// Created 29 April 2006 + +// This example code is in the public domain. + + +#include + +void setup() +{ + Wire.begin(); // join i2c bus (address optional for master) + Serial.begin(9600); // start serial communication at 9600bps +} + +int reading = 0; + +void loop() +{ + // step 1: instruct sensor to read echoes + Wire.beginTransmission(112); // transmit to device #112 (0x70) + // the address specified in the datasheet is 224 (0xE0) + // but i2c adressing uses the high 7 bits so it's 112 + Wire.write(byte(0x00)); // sets register pointer to the command register (0x00) + Wire.write(byte(0x50)); // command sensor to measure in "inches" (0x50) + // use 0x51 for centimeters + // use 0x52 for ping microseconds + Wire.endTransmission(); // stop transmitting + + // step 2: wait for readings to happen + delay(70); // datasheet suggests at least 65 milliseconds + + // step 3: instruct sensor to return a particular echo reading + Wire.beginTransmission(112); // transmit to device #112 + Wire.write(byte(0x02)); // sets register pointer to echo #1 register (0x02) + Wire.endTransmission(); // stop transmitting + + // step 4: request reading from sensor + Wire.requestFrom(112, 2); // request 2 bytes from slave device #112 + + // step 5: receive reading from sensor + if(2 <= Wire.available()) // if two bytes were received + { + reading = Wire.read(); // receive high byte (overwrites previous reading) + reading = reading << 8; // shift high byte to be high 8 bits + reading |= Wire.read(); // receive low byte as lower 8 bits + Serial.println(reading); // print the reading + } + + delay(250); // wait a bit since people have to read the output :) +} + + +/* + +// The following code changes the address of a Devantech Ultrasonic Range Finder (SRF10 or SRF08) +// usage: changeAddress(0x70, 0xE6); + +void changeAddress(byte oldAddress, byte newAddress) +{ + Wire.beginTransmission(oldAddress); + Wire.write(byte(0x00)); + Wire.write(byte(0xA0)); + Wire.endTransmission(); + + Wire.beginTransmission(oldAddress); + Wire.write(byte(0x00)); + Wire.write(byte(0xAA)); + Wire.endTransmission(); + + Wire.beginTransmission(oldAddress); + Wire.write(byte(0x00)); + Wire.write(byte(0xA5)); + Wire.endTransmission(); + + Wire.beginTransmission(oldAddress); + Wire.write(byte(0x00)); + Wire.write(newAddress); + Wire.endTransmission(); +} + +*/ diff --git a/hardware/sam/libraries/Wire/examples/digital_potentiometer/digital_potentiometer.pde b/hardware/sam/libraries/Wire/examples/digital_potentiometer/digital_potentiometer.pde new file mode 100644 index 000000000..38da1c543 --- /dev/null +++ b/hardware/sam/libraries/Wire/examples/digital_potentiometer/digital_potentiometer.pde @@ -0,0 +1,39 @@ +// I2C Digital Potentiometer +// by Nicholas Zambetti +// and Shawn Bonkowski + +// Demonstrates use of the Wire library +// Controls AD5171 digital potentiometer via I2C/TWI + +// Created 31 March 2006 + +// This example code is in the public domain. + +// This example code is in the public domain. + + +#include + +void setup() +{ + Wire.begin(); // join i2c bus (address optional for master) +} + +byte val = 0; + +void loop() +{ + Wire.beginTransmission(44); // transmit to device #44 (0x2c) + // device address is specified in datasheet + Wire.write(byte(0x00)); // sends instruction byte + Wire.write(val); // sends potentiometer value byte + Wire.endTransmission(); // stop transmitting + + val++; // increment value + if(val == 64) // if reached 64th position (max) + { + val = 0; // start over from lowest value + } + delay(500); +} + diff --git a/hardware/sam/libraries/Wire/examples/master_reader/master_reader.pde b/hardware/sam/libraries/Wire/examples/master_reader/master_reader.pde new file mode 100644 index 000000000..4124d7d6b --- /dev/null +++ b/hardware/sam/libraries/Wire/examples/master_reader/master_reader.pde @@ -0,0 +1,32 @@ +// Wire Master Reader +// by Nicholas Zambetti + +// Demonstrates use of the Wire library +// Reads data from an I2C/TWI slave device +// Refer to the "Wire Slave Sender" example for use with this + +// Created 29 March 2006 + +// This example code is in the public domain. + + +#include + +void setup() +{ + Wire.begin(); // join i2c bus (address optional for master) + Serial.begin(9600); // start serial for output +} + +void loop() +{ + Wire.requestFrom(2, 6); // request 6 bytes from slave device #2 + + while(Wire.available()) // slave may send less than requested + { + char c = Wire.read(); // receive a byte as character + Serial.print(c); // print the character + } + + delay(500); +} diff --git a/hardware/sam/libraries/Wire/examples/master_writer/master_writer.pde b/hardware/sam/libraries/Wire/examples/master_writer/master_writer.pde new file mode 100644 index 000000000..ccaa0361b --- /dev/null +++ b/hardware/sam/libraries/Wire/examples/master_writer/master_writer.pde @@ -0,0 +1,31 @@ +// Wire Master Writer +// by Nicholas Zambetti + +// Demonstrates use of the Wire library +// Writes data to an I2C/TWI slave device +// Refer to the "Wire Slave Receiver" example for use with this + +// Created 29 March 2006 + +// This example code is in the public domain. + + +#include + +void setup() +{ + Wire.begin(); // join i2c bus (address optional for master) +} + +byte x = 0; + +void loop() +{ + Wire.beginTransmission(4); // transmit to device #4 + Wire.write("x is "); // sends five bytes + Wire.write(x); // sends one byte + Wire.endTransmission(); // stop transmitting + + x++; + delay(500); +} diff --git a/hardware/sam/libraries/Wire/examples/slave_receiver/slave_receiver.pde b/hardware/sam/libraries/Wire/examples/slave_receiver/slave_receiver.pde new file mode 100644 index 000000000..60dd4bdde --- /dev/null +++ b/hardware/sam/libraries/Wire/examples/slave_receiver/slave_receiver.pde @@ -0,0 +1,38 @@ +// Wire Slave Receiver +// by Nicholas Zambetti + +// Demonstrates use of the Wire library +// Receives data as an I2C/TWI slave device +// Refer to the "Wire Master Writer" example for use with this + +// Created 29 March 2006 + +// This example code is in the public domain. + + +#include + +void setup() +{ + Wire.begin(4); // join i2c bus with address #4 + Wire.onReceive(receiveEvent); // register event + Serial.begin(9600); // start serial for output +} + +void loop() +{ + delay(100); +} + +// function that executes whenever data is received from master +// this function is registered as an event, see setup() +void receiveEvent(int howMany) +{ + while(1 < Wire.available()) // loop through all but the last + { + char c = Wire.read(); // receive byte as a character + Serial.print(c); // print the character + } + int x = Wire.read(); // receive byte as an integer + Serial.println(x); // print the integer +} diff --git a/hardware/sam/libraries/Wire/examples/slave_sender/slave_sender.pde b/hardware/sam/libraries/Wire/examples/slave_sender/slave_sender.pde new file mode 100644 index 000000000..d3b238af9 --- /dev/null +++ b/hardware/sam/libraries/Wire/examples/slave_sender/slave_sender.pde @@ -0,0 +1,32 @@ +// Wire Slave Sender +// by Nicholas Zambetti + +// Demonstrates use of the Wire library +// Sends data as an I2C/TWI slave device +// Refer to the "Wire Master Reader" example for use with this + +// Created 29 March 2006 + +// This example code is in the public domain. + + +#include + +void setup() +{ + Wire.begin(2); // join i2c bus with address #2 + Wire.onRequest(requestEvent); // register event +} + +void loop() +{ + delay(100); +} + +// function that executes whenever data is requested by master +// this function is registered as an event, see setup() +void requestEvent() +{ + Wire.write("hello "); // respond with message of 6 bytes + // as expected by master +} diff --git a/hardware/sam/libraries/Wire/keywords.txt b/hardware/sam/libraries/Wire/keywords.txt new file mode 100644 index 000000000..12f129b99 --- /dev/null +++ b/hardware/sam/libraries/Wire/keywords.txt @@ -0,0 +1,31 @@ +####################################### +# Syntax Coloring Map For Wire +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +begin KEYWORD2 +beginTransmission KEYWORD2 +endTransmission KEYWORD2 +requestFrom KEYWORD2 +send KEYWORD2 +receive KEYWORD2 +onReceive KEYWORD2 +onRequest KEYWORD2 + +####################################### +# Instances (KEYWORD2) +####################################### + +Wire KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### + diff --git a/hardware/sam/platforms.txt b/hardware/sam/platforms.txt new file mode 100755 index 000000000..3740fdb9e --- /dev/null +++ b/hardware/sam/platforms.txt @@ -0,0 +1,69 @@ +#########Compiler Recipe################################# +##compile c object files +##Default.recipe, overide if overide exists, these defauls should remain the same, if you need to change them do it as an overide. + +#default.recipe.c.o.pattern={0}{1}|{2}|{3}{4}|-DF_CPU={5}|-D{6}={7}|{8}|{9}|-o|{10} +#default.recipe.cpp.o.pattern={0}{1}|{2}|{3}{4}|-DF_CPU={5}|-D{6}={7}|{8}|{9}|-o|{10} +#default.recipe.ar.pattern={0}{1}|{2}|{3}{4}|{5} +#default.recipe.c.combine.pattern={0}{1}|{2}|{3}{4}|-o|{5}{6}.elf|{7}|{8}|-L{9}|-lm +#default.recipe.objcopy.eep.pattern={0}{1}|{2}|{3}.elf|{4}.eep +#default.recipe.objcopy.hex.pattern={0}{1}|{2}|{3}.elf|{4}.hex + +########sam compile pattern ########## +#sam.recipe.c.o.pattern={0=compiler.path}{1=compiler.c.cmd}{2=compiler.c.flags}{3=compiler.cpudef}{4=build.mcu}-DF_CPU={5=build.f_cpu}-D{7=ARDUINO}={6=Base.REVISION}{7=-I/INCLUDE_PATHS} {8=SOURCE_NAME} -o{9=OBJECT_NAME} +#object name seems to have build path in it. +sam.recipe.c.o.pattern={0}{1}|{2}|{3}{4}|-DF_CPU={5}|-D{6}={7}|{11}|{8}|{9}|-o|{10} + + +##compile cc object files +#sam.recipe.cc.o.pattern={0=compiler.path}{1=compiler.cc.cmd}{2=compiler.c.flags}{3=compiler.cpudef}{4=build.mcu}-DF_CPU={5=build.f_cpu}-DARDUINO={6=Base.REVISION}{-7=I/INCLUDE_PATHS} {8=SOURCE_NAME} -o{9=BUILD_PATH}{10=OBJECT_NAME} +sam.recipe.cpp.o.pattern={0}{1}|{2}|{3}{4}|-DF_CPU={5}|-D{6}={7}|{11}|{8}|{9}|-o|{10} +##create archives +#sam.recipe.ar.pattern={0=compiler.path}{1=compiler.ar.cmd}{2=compiler.ar.flags}{3=BUILD_PATH}{4=CORE_NAME=core.a}{5=BUILD_PATH}{6=OBJECT_NAME} +sam.recipe.ar.pattern={0}{1}|{2}|{3}{4}|{5} + +##combine gc-sections| archives, and objects +#sam.recipe.c.combine.pattern={0=compiler.path}{1=compiler.c.cmd}{2=compiler.combine.flags}{3=compiler.cpudef}{4=build.mcu} -o {5=BUILD_PATH}{6=SOURCE_NAME}.elf {7=BUILD_PATH}{8=SOURCE_NAME}.o {9=BUILD_PATH}{10=CORE_NAME=core.a} -L{11=BUILD_PATH} -lm +#sam.recipe.c.combine.pattern={0}{1}|{2}|{3}{4}|-o|{5}{6}.elf|{7}{8}|{9}|-L{10}|-lm +sam.recipe.c.combine.pattern={0}{1}|{2}|{3}{4}|-T{11}|-Wl,-Map,{5}{6}.map|-o|{5}{6}.elf|-L{9}|-lm|-lgcc|-mthumb|-Wl,--cref|-Wl,--check-sections|-Wl,--gc-sections|-Wl,--entry=Reset_Handler|-Wl,--unresolved-symbols=report-all|-Wl,--warn-common|-Wl,--warn-section-align|-Wl,--warn-unresolved-symbols|-Wl,--start-group|{7}|{8}|-Wl,--end-group + +##create eeprom +#sam.recipe.objcopy.eep.pattern={0=compiler.path}{1=compiler.objcopy.cmd}{2=compiler.objcopy.eep.flags} {3=BUILD_PATH}{4=SOURCE_NAME}.elf {5=BUILD_PATH}{6=SOURCE_NAME}.eep +#sam.recipe.objcopy.eep.pattern={0}{1}|{2}|{3}.elf|{4}.eep +sam.recipe.objcopy.eep.pattern= + +##create hex +#sam.recipe.objcopy.hex.pattern={0=compiler.path}{1=compiler.objcopy.cmd}{2=compiler.objcopy.elf.flags} {3=BUILD_PATH}{4=SOURCE_NAME}.elf {5=BUILD_PATH}{6=SOURCE_NAME}.hex +sam.recipe.objcopy.hex.pattern={0}{1}|{2}|{3}.elf|{4}.bin + + +##compute size +sam.recipe.size.pattern={0}{1}|{2}.elf + + +######################################################## +sam.name=Atmel SAM +#sam.compiler.path Official default is correct, only need to change this if you want to overide the initial default +sam.compiler.path={0}/hardware/tools/CodeSourcery_arm/bin/ +sam.compiler.c.cmd=arm-none-eabi-gcc +sam.compiler.c.flags=|-c|-g|-Os|-w|-mthumb|-mlong-calls|-ffunction-sections|-nostdlib|--param|max-inline-insns-single=500|-Dprintf=iprintf +sam.compiler.c.elf.flags=|-Os|-Wl,--gc-sections +sam.compiler.c.elf.cmd=arm-none-eabi-gcc +sam.compiler.S.flags=|-c|-g|-assembler-with-cpp +sam.compiler.cpp.cmd=arm-none-eabi-g++ +sam.compiler.cpp.flags=|-c|-g|-Os|-w|-mthumb|-mlong-calls|-ffunction-sections|-nostdlib|--param|max-inline-insns-single=500|-fno-rtti|-fno-exceptions|-Dprintf=iprintf +sam.compiler.ar.cmd=arm-none-eabi-ar +sam.compiler.ar.flags=rcs +sam.compiler.objcopy.cmd=arm-none-eabi-objcopy +sam.compiler.objcopy.eep.flags=|-O|ihex|-j|.eeprom|--set-section-flags=.eeprom=alloc,load|--no-change-warnings|--change-section-lma|.eeprom=0 +sam.compiler.elf2hex.flags=|-O|binary +sam.compiler.elf2hex.cmd=arm-none-eabi-objcopy +sam.compiler.ldflags= +sam.compiler.cpudef=-mcpu= +sam.compiler.size.cmd=arm-none-eabi-size +sam.compiler.upload.cmd= +sam.compiler.upload.flags= +sam.compiler.define=-DARDUINO= +sam.library.path=./hardware/sam/cores/sam +sam.library.core.path=./libraries;./hardware/sam/libraries + diff --git a/hardware/sam/programmers.txt b/hardware/sam/programmers.txt new file mode 100644 index 000000000..371e5ae82 --- /dev/null +++ b/hardware/sam/programmers.txt @@ -0,0 +1,18 @@ +samba.name=SAM-BA +samba.communication=serial +samba.protocol=sam-ba +samba.speed=19200 + +sambausb.name=SAM-BA +sambausb.communication=usb +sambausb.protocol=sam-ba + +arduinosamba.name=Arduino as SAM-BA +arduinosamba.communication=serial +arduinosamba.protocol=sam-ba +arduinosamba.speed=19200 + +arduinosambausb.name=Arduino as SAM-BA USB +arduinosambausb.communication=usb +arduinosambausb.protocol=sam-ba + diff --git a/hardware/sam/sam.bat b/hardware/sam/sam.bat new file mode 100644 index 000000000..550f9a642 --- /dev/null +++ b/hardware/sam/sam.bat @@ -0,0 +1,6 @@ +start "libsam" /d"system\libsam\build_gcc" /max "cd" +start "libarduino" /d"cores\sam\build_gcc" /max "cd" +start "libvariant sam3s-ek" /d"variants\sam3s_ek\build_gcc" /max "cd" +start "libvariant sam3u-ek" /d"variants\sam3u_ek\build_gcc" /max "cd" +start "libvariant Arduino Due" /d"variants\arduino_due\build_gcc" /max "cd" +start "test" /d"cores\sam\validation\build_gcc" /max "cd" \ No newline at end of file diff --git a/hardware/sam/system/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf b/hardware/sam/system/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf new file mode 100644 index 000000000..e04afaee6 Binary files /dev/null and b/hardware/sam/system/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf differ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/Common/Include/math_helper.h b/hardware/sam/system/CMSIS/DSP_Lib/Examples/Common/Include/math_helper.h new file mode 100644 index 000000000..4eb34ace8 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/Common/Include/math_helper.h @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 29. November 2010 +* $Revision: V1.0.3 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.h +* +* +* Description: Prototypes of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +#ifndef MATH_HELPER_H +#define MATH_HELPER_H + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples); +void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples); +void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_clip_f32(float *pIn, uint32_t numSamples); +uint32_t arm_calc_guard_bits(uint32_t num_adds); +void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits); +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples); +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_2pow(uint32_t guard_bits); +#endif + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/Common/Source/math_helper.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/Common/Source/math_helper.c new file mode 100644 index 000000000..75dcd5f25 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/Common/Source/math_helper.c @@ -0,0 +1,447 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 29. November 2010 +* $Revision: V1.0.3 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param float* Pointer to the reference buffer + * @param float* Pointer to the test buffer + * @param uint32_t total number of samples + * @return float SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if(temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if(temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if(temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + + +/** + * @brief Provide guard bits for Input buffer + * @param q15_t* Pointer to input buffer + * @param uint32_t blockSize + * @param uint32_t guard_bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param uint32_t number of samples in the buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param q15_t* Pointer to Ref buffer + * @param q15_t* Pointer to Test buffer + * @param uint32_t number of samples in the buffer + * @return none + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if(diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param q31_t* Pointer to Ref buffer + * @param q31_t* Pointer to Test buffer + * @param uint32_t number of samples in the buffer + * @return none + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if(diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param q31_t* Pointer to input buffer + * @param uint32_t blockSize + * @param uint32_t guard_bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param q31_t* Pointer to input buffer + * @param uint32_t blockSize + * @param uint32_t guard_bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param uint32_t number of additions + * @return none + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Converts Q15 to floating-point + * @param uint32_t number of samples in the buffer + * @return none + */ + +void arm_apply_guard_bits (float32_t * pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param uint32_t number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param uint32_t number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t * pOut, + uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param uint32_t number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, + uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param uint32_t number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t * pOut, + uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param uint32_t number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t * pOut, + uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Clip the float values to +/- 1 + * @param pIn input buffer + * @param numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if(pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_class_marks_example.ini b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_class_marks_example.ini new file mode 100644 index 000000000..0ca6ba5ef --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_class_marks_example.ini @@ -0,0 +1,14 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_class_marks_example.ini + +*/ + + +// usual initialisation for target setup +MAP 0x20000000, 0x20008000 READ WRITE // allow R/W access to IO space + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM0l_class_marks_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM0l_class_marks_example.uvopt new file mode 100644 index 000000000..2654ad975 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM0l_class_marks_example.uvopt @@ -0,0 +1,281 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_class_marks_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 193 + 1 +
330
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM0l_class_marks_example\../arm_class_marks_example_f32.c\193 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 183 + 193 + 0 + ..\arm_class_marks_example_f32.c + arm_class_marks_example_f32.c + + + + + CMSIS Device + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\system_ARMCM0.c + system_ARMCM0.c + + + 2 + 3 + 2 + 0 + 0 + 0 + 0 + 78 + 78 + 0 + .\startup_ARMCM0.s + startup_ARMCM0.s + + + + + CMSIS SW_DSP_Library + 1 + 0 + 0 + + 3 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib + arm_cortexM0l_math.lib + + + + + 1 + 0 + + 100 + 0 + + + ..\arm_class_marks_example_f32.c + 0 + 183 + 193 + + + .\startup_ARMCM0.s + 0 + 78 + 78 + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM0l_class_marks_example.uvproj b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM0l_class_marks_example.uvproj new file mode 100644 index 000000000..989129cbd --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM0l_class_marks_example.uvproj @@ -0,0 +1,425 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M0 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + + 4803 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM0l_class_marks_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_class_marks_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + ARM_MATH_CM0 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_class_marks_example_f32.c + 1 + ..\arm_class_marks_example_f32.c + + + + + CMSIS Device + + + system_ARMCM0.c + 1 + ..\system_ARMCM0.c + + + startup_ARMCM0.s + 2 + .\startup_ARMCM0.s + + + + + CMSIS DSP_Library + + + arm_cortexM0l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib + + + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM3l_class_marks_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM3l_class_marks_example.uvopt new file mode 100644 index 000000000..439df6547 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM3l_class_marks_example.uvopt @@ -0,0 +1,287 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_class_marks_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 193 + 1 +
334
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM3l_class_marks_example\../arm_class_marks_example_f32.c\193 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 183 + 193 + 0 + ..\arm_class_marks_example_f32.c + arm_class_marks_example_f32.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 29 + 0 + 1 + 15 + 0 + ..\system_ARMCM3.c + system_ARMCM3.c + + + 2 + 3 + 2 + 0 + 0 + 0 + 0 + 78 + 78 + 0 + .\startup_ARMCM3.s + startup_ARMCM3.s + + + + + CMSIS SW_DSP_Library + 1 + 0 + 0 + + 3 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM3l_math.lib + arm_cortexM3l_math.lib + + + + + 1 + 0 + + 100 + 0 + + + ..\arm_class_marks_example_f32.c + 0 + 183 + 193 + + + ..\system_ARMCM3.c + 29 + 1 + 15 + + + .\startup_ARMCM3.s + 0 + 78 + 78 + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM3l_class_marks_example.uvproj b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM3l_class_marks_example.uvproj new file mode 100644 index 000000000..cd8c06a18 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM3l_class_marks_example.uvproj @@ -0,0 +1,425 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M3 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE + + + + 4349 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM3l_class_marks_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_class_marks_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + ARM_MATH_CM3 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_class_marks_example_f32.c + 1 + ..\arm_class_marks_example_f32.c + + + + + CMSIS Device + + + system_ARMCM3.c + 1 + ..\system_ARMCM3.c + + + startup_ARMCM3.s + 2 + .\startup_ARMCM3.s + + + + + CMSIS DSP_Library + + + arm_cortexM3l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM3l_math.lib + + + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM4lf_class_marks_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM4lf_class_marks_example.uvopt new file mode 100644 index 000000000..3640e4584 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM4lf_class_marks_example.uvopt @@ -0,0 +1,281 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_class_marks_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 193 + 1 +
334
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM4lfclass_marks_example\../arm_class_marks_example_f32.c\193 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 183 + 193 + 0 + ..\arm_class_marks_example_f32.c + arm_class_marks_example_f32.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\system_ARMCM4.c + system_ARMCM4.c + + + 2 + 3 + 2 + 0 + 0 + 0 + 0 + 78 + 78 + 0 + .\startup_ARMCM4.s + startup_ARMCM4.s + + + + + CMSIS SW_DSP_Library + 1 + 0 + 0 + + 3 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + arm_cortexM4lf_math.lib + + + + + 1 + 0 + + 100 + 0 + + + ..\arm_class_marks_example_f32.c + 0 + 183 + 193 + + + .\startup_ARMCM4.s + 0 + 78 + 78 + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM4lf_class_marks_example.uvproj b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM4lf_class_marks_example.uvproj new file mode 100644 index 000000000..5cc7c3d79 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM4lf_class_marks_example.uvproj @@ -0,0 +1,425 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lfclass_marks_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_class_marks_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_class_marks_example_f32.c + 1 + ..\arm_class_marks_example_f32.c + + + + + CMSIS Device + + + system_ARMCM4.c + 1 + ..\system_ARMCM4.c + + + startup_ARMCM4.s + 2 + .\startup_ARMCM4.s + + + + + CMSIS DSP_Library + + + arm_cortexM4lf_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + + + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/startup_ARMCM0.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/startup_ARMCM0.s new file mode 100644 index 000000000..0acd34611 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/startup_ARMCM0.s @@ -0,0 +1,144 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Cortex-M0 Core Device Startup File +; * for CM0 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/startup_ARMCM3.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/startup_ARMCM3.s new file mode 100644 index 000000000..5af584bdc --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/startup_ARMCM3.s @@ -0,0 +1,164 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Cortex-M3 Core Device Startup File +; * for CM3 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/startup_ARMCM4.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/startup_ARMCM4.s new file mode 100644 index 000000000..09fdbd6ed --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/startup_ARMCM4.s @@ -0,0 +1,164 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Cortex-M4 Core Device Startup File +; * for CM4 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/ARMCMx.ld b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/ARMCMx.ld new file mode 100644 index 000000000..9cf8c92fa --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/ARMCMx.ld @@ -0,0 +1,198 @@ +/* Linker script for Cortex-M0 + * + * Version:CodeSourcery Sourcery G++ Lite 2007q3-53 + * BugURL:https://support.codesourcery.com/GNUToolchain/ + * + * Copyright 2007 CodeSourcery. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. */ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +ENTRY(_start) +SEARCH_DIR(.) +GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3micro) + +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 64K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K +} + +/* These force the linker to search for particular symbols from + * the start of the link process and thus ensure the user's + * overrides are picked up + */ +EXTERN(__cs3_reset_cortex_m) +EXTERN(__cs3_interrupt_vector_cortex_m) +EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end) + +PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram); +PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end); +PROVIDE(__cs3_heap_start = _end); +PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram); + +SECTIONS +{ + .text : + { + CREATE_OBJECT_SYMBOLS + __cs3_region_start_rom = .; + *(.cs3.region-head.rom) + __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m; + *(.cs3.interrupt_vector) + /* Make sure we pulled in an interrupt vector. */ + ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector"); + *(.rom) + *(.rom.b) + + __cs3_reset = __cs3_reset_cortex_m; + *(.cs3.reset) + /* Make sure we pulled in some reset code. */ + ASSERT (. != __cs3_reset, "No reset code"); + + *(.text .text.* .gnu.linkonce.t.*) + *(.plt) + *(.gnu.warning) + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) + + *(.rodata .rodata.* .gnu.linkonce.r.*) + + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.gcc_except_table) + *(.eh_frame_hdr) + *(.eh_frame) + + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + __cs3_regions = .; + LONG (0) + LONG (__cs3_region_init_ram) + LONG (__cs3_region_start_ram) + LONG (__cs3_region_init_size_ram) + LONG (__cs3_region_zero_size_ram) + } + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >rom + __exidx_end = .; + .text.align : + { + . = ALIGN(8); + _etext = .; + } >rom + __cs3_region_size_rom = LENGTH(rom); + __cs3_region_num = 1; + + .data : + { + __cs3_region_start_ram = .; + *(.cs3.region-head.ram) + KEEP(*(.jcr)) + *(.got.plt) *(.got) + *(.shdata) + *(.data .data.* .gnu.linkonce.d.*) + *(.ram) + . = ALIGN (8); + _edata = .; + } >ram AT>rom + .bss : + { + *(.shbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + *(.ram.b) + . = ALIGN (8); + _end = .; + __end = .; + } >ram AT>rom + .heap : + { + *(.heap) + } >ram + .stack (__cs3_stack - __cs3_stack_size) : + { + *(.stack) + } >ram + __cs3_region_init_ram = LOADADDR (.data); + __cs3_region_init_size_ram = _edata - __cs3_region_start_ram; + __cs3_region_zero_size_ram = _end - _edata; + __cs3_region_size_ram = LENGTH(ram); + __cs3_region_num = 1; + + .stab 0 (NOLOAD) : { *(.stab) } + .stabstr 0 (NOLOAD) : { *(.stabstr) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } + .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) } + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_class_marks_example.ini b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_class_marks_example.ini new file mode 100644 index 000000000..0ca6ba5ef --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_class_marks_example.ini @@ -0,0 +1,14 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_class_marks_example.ini + +*/ + + +// usual initialisation for target setup +MAP 0x20000000, 0x20008000 READ WRITE // allow R/W access to IO space + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM0l_class_marks_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM0l_class_marks_example.uvopt new file mode 100644 index 000000000..4efa018b9 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM0l_class_marks_example.uvopt @@ -0,0 +1,261 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_class_marks_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 193 + 1 +
268
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM0l_class_marks_example\../arm_class_marks_example_f32.c\193 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 183 + 193 + 0 + ../arm_class_marks_example_f32.c + arm_class_marks_example_f32.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../system_ARMCM0.c + system_ARMCM0.c + + + 2 + 3 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\startup_ARMCM0.s + startup_ARMCM0.s + + + + + CMSIS SW_DSP_Library + 1 + 0 + 0 + + + + 1 + 0 + + 100 + 0 + + + ../arm_class_marks_example_f32.c + 0 + 183 + 193 + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM0l_class_marks_example.uvproj b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM0l_class_marks_example.uvproj new file mode 100644 index 000000000..902e454c4 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM0l_class_marks_example.uvproj @@ -0,0 +1,328 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x3 + ARM-GNU + + + Cortex-M0 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + + 4803 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM0l_class_marks_example + 1 + 0 + 0 + 1 + 0 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_class_marks_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + "Cortex-M0" + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 2 + 1 + + + ARM_MATH_CM0 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include + + + + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + + + + arm_cortexM0l_math + ..\..\..\..\Lib\GCC + -Wl,--gc-sections + ARMCMx.ld + + + + + + Source Group 1 + + + arm_class_marks_example_f32.c + 1 + ../arm_class_marks_example_f32.c + + + + + CMSIS Device + + + system_ARMCM0.c + 1 + ../system_ARMCM0.c + + + startup_ARMCM0.s + 2 + .\startup_ARMCM0.s + + + + + CMSIS DSP_Library + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM3l_class_marks_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM3l_class_marks_example.uvopt new file mode 100644 index 000000000..d8322edd5 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM3l_class_marks_example.uvopt @@ -0,0 +1,261 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_class_marks_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 193 + 1 +
392
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM3l_class_marks_example\../arm_class_marks_example_f32.c\193 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 183 + 193 + 0 + ../arm_class_marks_example_f32.c + arm_class_marks_example_f32.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../system_ARMCM3.c + system_ARMCM3.c + + + 2 + 3 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\startup_ARMCM3.s + startup_ARMCM3.s + + + + + CMSIS SW_DSP_Library + 1 + 0 + 0 + + + + 1 + 0 + + 100 + 0 + + + ../arm_class_marks_example_f32.c + 0 + 183 + 193 + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM3l_class_marks_example.uvproj b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM3l_class_marks_example.uvproj new file mode 100644 index 000000000..23eeea730 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM3l_class_marks_example.uvproj @@ -0,0 +1,328 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x3 + ARM-GNU + + + Cortex-M3 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE + + + + 4349 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM3l_class_marks_example + 1 + 0 + 0 + 1 + 0 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_class_marks_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + "Cortex-M3" + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 2 + 1 + + + ARM_MATH_CM3 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include + + + + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + + + + arm_cortexM3l_math + ..\..\..\..\Lib\GCC + -Wl,--gc-sections + ARMCMx.ld + + + + + + Source Group 1 + + + arm_class_marks_example_f32.c + 1 + ../arm_class_marks_example_f32.c + + + + + CMSIS Device + + + system_ARMCM3.c + 1 + ../system_ARMCM3.c + + + startup_ARMCM3.s + 2 + .\startup_ARMCM3.s + + + + + CMSIS DSP_Library + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM4lf_class_marks_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM4lf_class_marks_example.uvopt new file mode 100644 index 000000000..d42b1f73a --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM4lf_class_marks_example.uvopt @@ -0,0 +1,261 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_class_marks_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 193 + 1 +
392
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM4lf_class_marks_example\../arm_class_marks_example_f32.c\193 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 183 + 193 + 0 + ../arm_class_marks_example_f32.c + arm_class_marks_example_f32.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../system_ARMCM4.c + system_ARMCM4.c + + + 2 + 3 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\startup_ARMCM4.s + startup_ARMCM4.s + + + + + CMSIS SW_DSP_Library + 1 + 0 + 0 + + + + 1 + 0 + + 100 + 0 + + + ../arm_class_marks_example_f32.c + 0 + 183 + 193 + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM4lf_class_marks_example.uvproj b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM4lf_class_marks_example.uvproj new file mode 100644 index 000000000..16828d0a6 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM4lf_class_marks_example.uvproj @@ -0,0 +1,328 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x3 + ARM-GNU + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_class_marks_example + 1 + 0 + 0 + 1 + 0 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_class_marks_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + "Cortex-M4" + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 2 + 1 + + -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -fno-strict-aliasing -ffunction-sections + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + + + + arm_cortexM4lf_math + ..\..\..\..\Lib\GCC + -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -Wl,--gc-sections + ARMCMx.ld + + + + + + Source Group 1 + + + arm_class_marks_example_f32.c + 1 + ../arm_class_marks_example_f32.c + + + + + CMSIS Device + + + system_ARMCM4.c + 1 + ../system_ARMCM4.c + + + startup_ARMCM4.s + 2 + .\startup_ARMCM4.s + + + + + CMSIS DSP_Library + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/startup_ARMCM0.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/startup_ARMCM0.s new file mode 100644 index 000000000..faa790939 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/startup_ARMCM0.s @@ -0,0 +1,155 @@ +/**************************************************************************//** + * @file startup_ARMCM0.s + * @brief CMSIS Cortex-M0 Core Device Startup File + * for CM0 Device Series + * @version V1.04 + * @date 14. January 2011 + *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + * + ******************************************************************************/ + +/*****************************************************************************/ +/* Version: CodeSourcery Sourcery G++ Lite (with CS3) */ +/*****************************************************************************/ + + +/* +// Stack Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .equ Stack_Size, 0x00000100 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack_size +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + + +/* +// Heap Configuration +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .equ Heap_Size, 0x00001000 + + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + +/* Vector Table */ + + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object + +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* Top of Stack */ + .long __cs3_reset /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .long DEF_IRQHandler /* 0: Default */ + + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0,=_start + BX R0 + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ DEF_IRQHandler + + .end diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/startup_ARMCM3.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/startup_ARMCM3.s new file mode 100644 index 000000000..07b53c81c --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/startup_ARMCM3.s @@ -0,0 +1,179 @@ +/**************************************************************************//** + * @file startup_ARMCM3.s + * @brief CMSIS Cortex-M3 Core Device Startup File + * for CM3 Device Series + * @version V1.04 + * @date 14. January 2011 + *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + * + ******************************************************************************/ + +/*****************************************************************************/ +/* Version: CodeSourcery Sourcery G++ Lite (with CS3) */ +/*****************************************************************************/ + + +/* +// Stack Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .equ Stack_Size, 0x00000100 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack_size +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + + +/* +// Heap Configuration +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .equ Heap_Size, 0x00001000 + + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + +/* Vector Table */ + + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object + +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* Top of Stack */ + .long __cs3_reset /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .long DEF_IRQHandler /* 0: Default */ + + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0,=_start + BX R0 + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + B . + .size MemManage_Handler, . - MemManage_Handler + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + B . + .size BusFault_Handler, . - BusFault_Handler + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + B . + .size UsageFault_Handler, . - UsageFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + B . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ DEF_IRQHandler + + .end diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/startup_ARMCM4.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/startup_ARMCM4.s new file mode 100644 index 000000000..004d00130 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/startup_ARMCM4.s @@ -0,0 +1,179 @@ +/**************************************************************************//** + * @file startup_ARMCM4.s + * @brief CMSIS Cortex-M4 Core Device Startup File + * for CM4 Device Series + * @version V1.04 + * @date 14. January 2011 + *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + * + ******************************************************************************/ + +/*****************************************************************************/ +/* Version: CodeSourcery Sourcery G++ Lite (with CS3) */ +/*****************************************************************************/ + + +/* +// Stack Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .equ Stack_Size, 0x00000100 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack_size +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + + +/* +// Heap Configuration +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .equ Heap_Size, 0x00001000 + + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + +/* Vector Table */ + + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object + +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* Top of Stack */ + .long __cs3_reset /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .long DEF_IRQHandler /* 0: Default */ + + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0,=_start + BX R0 + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + B . + .size MemManage_Handler, . - MemManage_Handler + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + B . + .size BusFault_Handler, . - BusFault_Handler + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + B . + .size UsageFault_Handler, . - UsageFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + B . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ DEF_IRQHandler + + .end diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/arm_class_marks_example_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/arm_class_marks_example_f32.c new file mode 100644 index 000000000..fef0280da --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/arm_class_marks_example_f32.c @@ -0,0 +1,196 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 29. November 2010 +* $Revision: V1.0.3 +* +* Project: CMSIS DSP Library +* Title: arm_class_marks_example_f32.c +* +* Description: Example code to calculate Minimum, Maximum +* Mean, std and variance of marks obtained in a class +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.1 2010/10/05 KK +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 KK +* Production release and review comments incorporated. +* ------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup ClassMarks Class Marks Example + * + * \par Description: + * \par + * Demonstrates the use the Maximum, Minimum, Mean, Standard Deviation, Variance + * and Matrix functions to calculate statistical values of marks obtained in a class. + * + * \note This example also demonstrates the usage of static initialization. + * + * \par Variables Description: + * \par + * \li \c testMarks_f32 points to the marks scored by 20 students in 4 subjects + * \li \c max_marks Maximum of all marks + * \li \c min_marks Minimum of all marks + * \li \c mean Mean of all marks + * \li \c var Variance of the marks + * \li \c std Standard deviation of the marks + * \li \c numStudents Total number of students in the class + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_mat_init_f32() + * - arm_mat_mult_f32() + * - arm_max_f32() + * - arm_min_f32() + * - arm_mean_f32() + * - arm_std_f32() + * - arm_var_f32() + * + * Refer + * \link arm_class_marks_example_f32.c \endlink + * + */ + + +/** \example arm_class_marks_example_f32.c + */ +#include "arm_math.h" + +#define USE_STATIC_INIT + + /* ---------------------------------------------------------------------- +** Global defines +** ------------------------------------------------------------------- */ + +#define TEST_LENGTH_SAMPLES (20*4) + +/* ---------------------------------------------------------------------- +** List of Marks scored by 20 students for 4 subjects +** ------------------------------------------------------------------- */ +const float32_t testMarks_f32[TEST_LENGTH_SAMPLES] = +{ + 42.000000, 37.000000, 81.000000, 28.000000, + 83.000000, 72.000000, 36.000000, 38.000000, + 32.000000, 51.000000, 63.000000, 64.000000, + 97.000000, 82.000000, 95.000000, 90.000000, + 66.000000, 51.000000, 54.000000, 42.000000, + 67.000000, 56.000000, 45.000000, 57.000000, + 67.000000, 69.000000, 35.000000, 52.000000, + 29.000000, 81.000000, 58.000000, 47.000000, + 38.000000, 76.000000, 100.000000, 29.000000, + 33.000000, 47.000000, 29.000000, 50.000000, + 34.000000, 41.000000, 61.000000, 46.000000, + 52.000000, 50.000000, 48.000000, 36.000000, + 47.000000, 55.000000, 44.000000, 40.000000, + 100.000000, 94.000000, 84.000000, 37.000000, + 32.000000, 71.000000, 47.000000, 77.000000, + 31.000000, 50.000000, 49.000000, 35.000000, + 63.000000, 67.000000, 40.000000, 31.000000, + 29.000000, 68.000000, 61.000000, 38.000000, + 31.000000, 28.000000, 28.000000, 76.000000, + 55.000000, 33.000000, 29.000000, 39.000000 +}; + + +/* ---------------------------------------------------------------------- +* Number of subjects X 1 +* ------------------------------------------------------------------- */ +const float32_t testUnity_f32[4] = +{ + 1.000, 1.000, 1.000, 1.000 +}; + + +/* ---------------------------------------------------------------------- +** f32 Output buffer +** ------------------------------------------------------------------- */ +static float32_t testOutput[TEST_LENGTH_SAMPLES]; + + +/* ------------------------------------------------------------------ +* Global defines +*------------------------------------------------------------------- */ +#define NUMSTUDENTS 20 +#define NUMSUBJECTS 4 + +/* ------------------------------------------------------------------ +* Global variables +*------------------------------------------------------------------- */ + +uint32_t numStudents = 20; +uint32_t numSubjects = 4; +float32_t max_marks, min_marks, mean, std, var; +uint32_t student_num; + +/* ---------------------------------------------------------------------------------- +* Main f32 test function. It returns maximum marks secured and student number +* ------------------------------------------------------------------------------- */ + +int32_t main() +{ + +#ifndef USE_STATIC_INIT + + arm_matrix_instance_f32 srcA; + arm_matrix_instance_f32 srcB; + arm_matrix_instance_f32 dstC; + + /* Input and output matrices initializations */ + arm_mat_init_f32(&srcA, numStudents, numSubjects, (float32_t *)testMarks_f32); + arm_mat_init_f32(&srcB, numSubjects, 1, (float32_t *)testUnity_f32); + arm_mat_init_f32(&dstC, numStudents, 1, testOutput); + +#else + + /* Static Initializations of Input and output matrix sizes and array */ + arm_matrix_instance_f32 srcA = {NUMSTUDENTS, NUMSUBJECTS, (float32_t *)testMarks_f32}; + arm_matrix_instance_f32 srcB = {NUMSUBJECTS, 1, (float32_t *)testUnity_f32}; + arm_matrix_instance_f32 dstC = {NUMSTUDENTS, 1, testOutput}; + +#endif + + + /* ---------------------------------------------------------------------- + *Call the Matrix multiplication process function + * ------------------------------------------------------------------- */ + arm_mat_mult_f32(&srcA, &srcB, &dstC); + + /* ---------------------------------------------------------------------- + ** Call the Max function to calculate max marks among numStudents + ** ------------------------------------------------------------------- */ + arm_max_f32(testOutput, numStudents, &max_marks, &student_num); + + /* ---------------------------------------------------------------------- + ** Call the Min function to calculate min marks among numStudents + ** ------------------------------------------------------------------- */ + arm_min_f32(testOutput, numStudents, &min_marks, &student_num); + + /* ---------------------------------------------------------------------- + ** Call the Mean function to calculate mean + ** ------------------------------------------------------------------- */ + arm_mean_f32(testOutput, numStudents, &mean); + + /* ---------------------------------------------------------------------- + ** Call the std function to calculate standard deviation + ** ------------------------------------------------------------------- */ + arm_std_f32(testOutput, numStudents, &std); + + /* ---------------------------------------------------------------------- + ** Call the var function to calculate variance + ** ------------------------------------------------------------------- */ + arm_var_f32(testOutput, numStudents, &var); + + while(1); /* main function does not return */ +} + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/system_ARMCM0.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/system_ARMCM0.c new file mode 100644 index 000000000..ece74d2de --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/system_ARMCM0.c @@ -0,0 +1,76 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Cortex-M0 Device System Source File + * for CM0 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/system_ARMCM3.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/system_ARMCM3.c new file mode 100644 index 000000000..2f5fa0b93 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/system_ARMCM3.c @@ -0,0 +1,76 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Cortex-M3 Device System Source File + * for CM3 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/system_ARMCM4.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/system_ARMCM4.c new file mode 100644 index 000000000..beaaf6fb8 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_class_marks_example/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Cortex-M4 Device System Source File + * for CM4 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM4.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ + #endif + + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_convolution_example.ini b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_convolution_example.ini new file mode 100644 index 000000000..5509390f0 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_convolution_example.ini @@ -0,0 +1,14 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_convolution_example.ini + +*/ + + +// usual initialisation for target setup +MAP 0x20000000, 0x20008000 READ WRITE // allow R/W access to IO space + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM0l_convolution_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM0l_convolution_example.uvopt new file mode 100644 index 000000000..06c25dd1f --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM0l_convolution_example.uvopt @@ -0,0 +1,325 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_convolution_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 94 + 1 +
1414
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384
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+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM0l_convolution_example\../arm_convolution_example_f32.c\225 + + + + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 218 + 228 + 0 + ..\arm_convolution_example_f32.c + arm_convolution_example_f32.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Common\Source\math_helper.c + math_helper.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\system_ARMCM0.c + system_ARMCM0.c + + + 2 + 4 + 2 + 0 + 0 + 0 + 0 + 78 + 78 + 0 + .\startup_ARMCM0.s + startup_ARMCM0.s + + + + + CMSIS SW_DSP_library + 1 + 0 + 0 + + 3 + 5 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib + arm_cortexM0l_math.lib + + + + + 1 + 0 + + 100 + 1 + + + .\startup_ARMCM0.s + 0 + 78 + 78 + + + ..\arm_convolution_example_f32.c + 0 + 218 + 228 + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM0l_convolution_example.uvproj b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM0l_convolution_example.uvproj new file mode 100644 index 000000000..e2f1000d9 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM0l_convolution_example.uvproj @@ -0,0 +1,430 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M0 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + + 4803 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM0l_convolution_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_convolution_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + ARM_MATH_CM0 + + ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_convolution_example_f32.c + 1 + ..\arm_convolution_example_f32.c + + + math_helper.c + 1 + ..\..\Common\Source\math_helper.c + + + + + CMSIS Device + + + system_ARMCM0.c + 1 + ..\system_ARMCM0.c + + + startup_ARMCM0.s + 2 + .\startup_ARMCM0.s + + + + + CMSIS DSP_Library + + + arm_cortexM0l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib + + + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM3l_convolution_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM3l_convolution_example.uvopt new file mode 100644 index 000000000..631898420 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM3l_convolution_example.uvopt @@ -0,0 +1,310 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_convolution_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 225 + 1 +
380
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382
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M3 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE + + + + 4349 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM3l_convolution_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_convolution_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM3 + + ..\..\Common\Include;..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_convolution_example_f32.c + 1 + ..\arm_convolution_example_f32.c + + + math_helper.c + 1 + ..\..\Common\Source\math_helper.c + + + + + CMSIS Device + + + system_ARMCM3.c + 1 + ..\system_ARMCM3.c + + + startup_ARMCM3.s + 2 + .\startup_ARMCM3.s + + + + + CMSIS DSP_Library + + + arm_cortexM3l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM3l_math.lib + + + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM4lf_convolution_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM4lf_convolution_example.uvopt new file mode 100644 index 000000000..1976ab073 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM4lf_convolution_example.uvopt @@ -0,0 +1,310 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_convolution_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 225 + 1 +
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+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM4lf_convolution_example\../arm_convolution_example_f32.c\228 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 218 + 228 + 0 + ..\arm_convolution_example_f32.c + arm_convolution_example_f32.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Common\Source\math_helper.c + math_helper.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\system_ARMCM4.c + system_ARMCM4.c + + + 2 + 4 + 2 + 0 + 0 + 0 + 0 + 78 + 78 + 0 + .\startup_ARMCM4.s + startup_ARMCM4.s + + + + + CMSIS SW_DSP_Library + 1 + 0 + 0 + + 3 + 5 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + arm_cortexM4lf_math.lib + + + + + 1 + 0 + + 100 + 0 + + + ..\arm_convolution_example_f32.c + 0 + 218 + 228 + + + .\startup_ARMCM4.s + 0 + 78 + 78 + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM4lf_convolution_example.uvproj b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM4lf_convolution_example.uvproj new file mode 100644 index 000000000..5f10472c3 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM4lf_convolution_example.uvproj @@ -0,0 +1,430 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_convolution_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_convolution_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\Common\Include;..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_convolution_example_f32.c + 1 + ..\arm_convolution_example_f32.c + + + math_helper.c + 1 + ..\..\Common\Source\math_helper.c + + + + + CMSIS Device + + + system_ARMCM4.c + 1 + ..\system_ARMCM4.c + + + startup_ARMCM4.s + 2 + .\startup_ARMCM4.s + + + + + CMSIS DSP_Library + + + arm_cortexM4lf_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + + + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/startup_ARMCM0.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/startup_ARMCM0.s new file mode 100644 index 000000000..0acd34611 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/startup_ARMCM0.s @@ -0,0 +1,144 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Cortex-M0 Core Device Startup File +; * for CM0 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/startup_ARMCM3.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/startup_ARMCM3.s new file mode 100644 index 000000000..5af584bdc --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/startup_ARMCM3.s @@ -0,0 +1,164 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Cortex-M3 Core Device Startup File +; * for CM3 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/startup_ARMCM4.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/startup_ARMCM4.s new file mode 100644 index 000000000..09fdbd6ed --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/startup_ARMCM4.s @@ -0,0 +1,164 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Cortex-M4 Core Device Startup File +; * for CM4 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/ARMCMx.ld b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/ARMCMx.ld new file mode 100644 index 000000000..9cf8c92fa --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/ARMCMx.ld @@ -0,0 +1,198 @@ +/* Linker script for Cortex-M0 + * + * Version:CodeSourcery Sourcery G++ Lite 2007q3-53 + * BugURL:https://support.codesourcery.com/GNUToolchain/ + * + * Copyright 2007 CodeSourcery. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. */ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +ENTRY(_start) +SEARCH_DIR(.) +GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3micro) + +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 64K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K +} + +/* These force the linker to search for particular symbols from + * the start of the link process and thus ensure the user's + * overrides are picked up + */ +EXTERN(__cs3_reset_cortex_m) +EXTERN(__cs3_interrupt_vector_cortex_m) +EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end) + +PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram); +PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end); +PROVIDE(__cs3_heap_start = _end); +PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram); + +SECTIONS +{ + .text : + { + CREATE_OBJECT_SYMBOLS + __cs3_region_start_rom = .; + *(.cs3.region-head.rom) + __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m; + *(.cs3.interrupt_vector) + /* Make sure we pulled in an interrupt vector. */ + ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector"); + *(.rom) + *(.rom.b) + + __cs3_reset = __cs3_reset_cortex_m; + *(.cs3.reset) + /* Make sure we pulled in some reset code. */ + ASSERT (. != __cs3_reset, "No reset code"); + + *(.text .text.* .gnu.linkonce.t.*) + *(.plt) + *(.gnu.warning) + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) + + *(.rodata .rodata.* .gnu.linkonce.r.*) + + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.gcc_except_table) + *(.eh_frame_hdr) + *(.eh_frame) + + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + __cs3_regions = .; + LONG (0) + LONG (__cs3_region_init_ram) + LONG (__cs3_region_start_ram) + LONG (__cs3_region_init_size_ram) + LONG (__cs3_region_zero_size_ram) + } + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >rom + __exidx_end = .; + .text.align : + { + . = ALIGN(8); + _etext = .; + } >rom + __cs3_region_size_rom = LENGTH(rom); + __cs3_region_num = 1; + + .data : + { + __cs3_region_start_ram = .; + *(.cs3.region-head.ram) + KEEP(*(.jcr)) + *(.got.plt) *(.got) + *(.shdata) + *(.data .data.* .gnu.linkonce.d.*) + *(.ram) + . = ALIGN (8); + _edata = .; + } >ram AT>rom + .bss : + { + *(.shbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + *(.ram.b) + . = ALIGN (8); + _end = .; + __end = .; + } >ram AT>rom + .heap : + { + *(.heap) + } >ram + .stack (__cs3_stack - __cs3_stack_size) : + { + *(.stack) + } >ram + __cs3_region_init_ram = LOADADDR (.data); + __cs3_region_init_size_ram = _edata - __cs3_region_start_ram; + __cs3_region_zero_size_ram = _end - _edata; + __cs3_region_size_ram = LENGTH(ram); + __cs3_region_num = 1; + + .stab 0 (NOLOAD) : { *(.stab) } + .stabstr 0 (NOLOAD) : { *(.stabstr) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } + .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) } + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_convolution_example.ini b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_convolution_example.ini new file mode 100644 index 000000000..5509390f0 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_convolution_example.ini @@ -0,0 +1,14 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_convolution_example.ini + +*/ + + +// usual initialisation for target setup +MAP 0x20000000, 0x20008000 READ WRITE // allow R/W access to IO space + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM0l_convolution_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM0l_convolution_example.uvopt new file mode 100644 index 000000000..e7a7637a2 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM0l_convolution_example.uvopt @@ -0,0 +1,290 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_convolution_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 228 + 1 +
398
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM0l_convolution_example\../arm_convolution_example_f32.c\228 + + + 1 + 0 + 225 + 1 +
396
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x3 + ARM-GNU + + + Cortex-M0 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + + 4803 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM0l_convolution_example + 1 + 0 + 0 + 1 + 0 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_convolution_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + "Cortex-M0" + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 2 + 1 + + + ARM_MATH_CM0 + + ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include + + + + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + + + + arm_cortexM0l_math + ..\..\..\..\Lib\GCC + -Wl,--gc-sections + ARMCMx.ld + + + + + + Source Group 1 + + + arm_convolution_example_f32.c + 1 + ../arm_convolution_example_f32.c + + + math_helper.c + 1 + ../../Common/Source/math_helper.c + + + + + CMSIS Device + + + system_ARMCM0.c + 1 + ../system_ARMCM0.c + + + startup_ARMCM0.s + 2 + .\startup_ARMCM0.s + + + + + CMSIS DSP_Library + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM3l_convolution_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM3l_convolution_example.uvopt new file mode 100644 index 000000000..5d839e8e1 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM3l_convolution_example.uvopt @@ -0,0 +1,290 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_convolution_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 225 + 1 +
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x3 + ARM-GNU + + + Cortex-M3 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE + + + + 4349 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM3l_convolution_example + 1 + 0 + 0 + 1 + 0 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_convolution_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + "Cortex-M3" + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 2 + 1 + + + ARM_MATH_CM3 + + ..\..\Common\Include;..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include + + + + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + + + + arm_cortexM3l_math + ..\..\..\..\Lib\GCC + -Wl,--gc-sections + ARMCMx.ld + + + + + + Source Group 1 + + + arm_convolution_example_f32.c + 1 + ../arm_convolution_example_f32.c + + + math_helper.c + 1 + ../../Common/Source/math_helper.c + + + + + CMSIS Device + + + system_ARMCM3.c + 1 + ../system_ARMCM3.c + + + startup_ARMCM3.s + 2 + .\startup_ARMCM3.s + + + + + CMSIS DSP_Library + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM4lf_convolution_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM4lf_convolution_example.uvopt new file mode 100644 index 000000000..8d0514a3a --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM4lf_convolution_example.uvopt @@ -0,0 +1,290 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_convolution_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 225 + 1 +
492
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494
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x3 + ARM-GNU + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_convolution_example + 1 + 0 + 0 + 1 + 0 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_convolution_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + "Cortex-M4" + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 2 + 1 + + -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -fno-strict-aliasing -ffunction-sections + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\Common\Include;..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + + + + arm_cortexM4lf_math + ..\..\..\..\Lib\GCC + -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -Wl,--gc-sections + ARMCMx.ld + + + + + + Source Group 1 + + + arm_convolution_example_f32.c + 1 + ../arm_convolution_example_f32.c + + + math_helper.c + 1 + ../../Common/Source/math_helper.c + + + + + CMSIS Device + + + system_ARMCM4.c + 1 + ../system_ARMCM4.c + + + startup_ARMCM4.s + 2 + .\startup_ARMCM4.s + + + + + CMSIS DSP_Library + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/startup_ARMCM0.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/startup_ARMCM0.s new file mode 100644 index 000000000..faa790939 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/startup_ARMCM0.s @@ -0,0 +1,155 @@ +/**************************************************************************//** + * @file startup_ARMCM0.s + * @brief CMSIS Cortex-M0 Core Device Startup File + * for CM0 Device Series + * @version V1.04 + * @date 14. January 2011 + *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + * + ******************************************************************************/ + +/*****************************************************************************/ +/* Version: CodeSourcery Sourcery G++ Lite (with CS3) */ +/*****************************************************************************/ + + +/* +// Stack Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .equ Stack_Size, 0x00000100 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack_size +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + + +/* +// Heap Configuration +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .equ Heap_Size, 0x00001000 + + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + +/* Vector Table */ + + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object + +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* Top of Stack */ + .long __cs3_reset /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .long DEF_IRQHandler /* 0: Default */ + + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0,=_start + BX R0 + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ DEF_IRQHandler + + .end diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/startup_ARMCM3.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/startup_ARMCM3.s new file mode 100644 index 000000000..07b53c81c --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/startup_ARMCM3.s @@ -0,0 +1,179 @@ +/**************************************************************************//** + * @file startup_ARMCM3.s + * @brief CMSIS Cortex-M3 Core Device Startup File + * for CM3 Device Series + * @version V1.04 + * @date 14. January 2011 + *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + * + ******************************************************************************/ + +/*****************************************************************************/ +/* Version: CodeSourcery Sourcery G++ Lite (with CS3) */ +/*****************************************************************************/ + + +/* +// Stack Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .equ Stack_Size, 0x00000100 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack_size +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + + +/* +// Heap Configuration +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .equ Heap_Size, 0x00001000 + + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + +/* Vector Table */ + + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object + +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* Top of Stack */ + .long __cs3_reset /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .long DEF_IRQHandler /* 0: Default */ + + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0,=_start + BX R0 + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + B . + .size MemManage_Handler, . - MemManage_Handler + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + B . + .size BusFault_Handler, . - BusFault_Handler + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + B . + .size UsageFault_Handler, . - UsageFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + B . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ DEF_IRQHandler + + .end diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/startup_ARMCM4.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/startup_ARMCM4.s new file mode 100644 index 000000000..004d00130 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/startup_ARMCM4.s @@ -0,0 +1,179 @@ +/**************************************************************************//** + * @file startup_ARMCM4.s + * @brief CMSIS Cortex-M4 Core Device Startup File + * for CM4 Device Series + * @version V1.04 + * @date 14. January 2011 + *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + * + ******************************************************************************/ + +/*****************************************************************************/ +/* Version: CodeSourcery Sourcery G++ Lite (with CS3) */ +/*****************************************************************************/ + + +/* +// Stack Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .equ Stack_Size, 0x00000100 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack_size +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + + +/* +// Heap Configuration +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .equ Heap_Size, 0x00001000 + + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + +/* Vector Table */ + + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object + +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* Top of Stack */ + .long __cs3_reset /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .long DEF_IRQHandler /* 0: Default */ + + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0,=_start + BX R0 + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + B . + .size MemManage_Handler, . - MemManage_Handler + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + B . + .size BusFault_Handler, . - BusFault_Handler + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + B . + .size UsageFault_Handler, . - UsageFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + B . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ DEF_IRQHandler + + .end diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/arm_convolution_example_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/arm_convolution_example_f32.c new file mode 100644 index 000000000..4d547b207 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/arm_convolution_example_f32.c @@ -0,0 +1,232 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 29. November 2010 +* $Revision: V1.0.3 +* +* Project: CMSIS DSP Library +* Title: arm_convolution_example_f32.c +* +* Description: Example code demonstrating Convolution of two input signals using fft. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.1 2010/10/05 KK +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 KK +* Production release and review comments incorporated. +* ------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup ConvolutionExample Convolution Example + * + * \par Description: + * \par + * Demonstrates the convolution theorem with the use of the Complex FFT, Complex-by-Complex + * Multiplication, and Support Functions. + * + * \par Algorithm: + * \par + * The convolution theorem states that convolution in the time domain corresponds to + * multiplication in the frequency domain. Therefore, the Fourier transform of the convoution of + * two signals is equal to the product of their individual Fourier transforms. + * The Fourier transform of a signal can be evaluated efficiently using the Fast Fourier Transform (FFT). + * \par + * Two input signals, a[n] and b[n], with lengths \c n1 and \c n2 respectively, + * are zero padded so that their lengths become \c N, which is greater than or equal to (n1+n2-1) + * and is a power of 4 as FFT implementation is radix-4. + * The convolution of a[n] and b[n] is obtained by taking the FFT of the input + * signals, multiplying the Fourier transforms of the two signals, and taking the inverse FFT of + * the multiplied result. + * \par + * This is denoted by the following equations: + * 
 A[k] = FFT(a[n],N)
+ * B[k] = FFT(b[n],N)
+ * conv(a[n], b[n]) = IFFT(A[k] * B[k], N)
+ * where A[k] and B[k] are the N-point FFTs of the signals a[n] + * and b[n] respectively. + * The length of the convolved signal is (n1+n2-1). + * + * \par Block Diagram: + * \par + * \image html Convolution.gif + * + * \par Variables Description: + * \par + * \li \c testInputA_f32 points to the first input sequence + * \li \c srcALen length of the first input sequence + * \li \c testInputB_f32 points to the second input sequence + * \li \c srcBLen length of the second input sequence + * \li \c outLen length of convolution output sequence, (srcALen + srcBLen - 1) + * \li \c AxB points to the output array where the product of individual FFTs of inputs is stored. + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_fill_f32() + * - arm_copy_f32() + * - arm_cfft_radix4_init_f32() + * - arm_cfft_radix4_f32() + * - arm_cmplx_mult_cmplx_f32() + * + * Refer + * \link arm_convolution_example_f32.c \endlink + * + */ + + +/** \example arm_convolution_example_f32.c + */ + +#include "arm_math.h" +#include "math_helper.h" + +/* ---------------------------------------------------------------------- +* Defines each of the tests performed +* ------------------------------------------------------------------- */ +#define MAX_BLOCKSIZE 128 +#define DELTA (0.000001f) +#define SNR_THRESHOLD 90 + +/* ---------------------------------------------------------------------- +* Declare I/O buffers +* ------------------------------------------------------------------- */ +float32_t Ak[MAX_BLOCKSIZE]; /* Input A */ +float32_t Bk[MAX_BLOCKSIZE]; /* Input B */ +float32_t AxB[MAX_BLOCKSIZE * 2]; /* Output */ + +/* ---------------------------------------------------------------------- +* Test input data for Floating point Convolution example for 32-blockSize +* Generated by the MATLAB randn() function +* ------------------------------------------------------------------- */ +float32_t testInputA_f32[64] = +{ +-0.808920, 1.357369, 1.180861, -0.504544, 1.762637, -0.703285, +1.696966, 0.620571, -0.151093, -0.100235, -0.872382, -0.403579, +-0.860749, -0.382648, -1.052338, 0.128113, -0.646269, 1.093377, +-2.209198, 0.471706, 0.408901, 1.266242, 0.598252, 1.176827, +-0.203421, 0.213596, -0.851964, -0.466958, 0.021841, -0.698938, +-0.604107, 0.461778, -0.318219, 0.942520, 0.577585, 0.417619, +0.614665, 0.563679, -1.295073, -0.764437, 0.952194, -0.859222, +-0.618554, -2.268542, -1.210592, 1.655853, -2.627219, -0.994249, +-1.374704, 0.343799, 0.025619, 1.227481, -0.708031, 0.069355, +-1.845228, -1.570886, 1.010668, -1.802084, 1.630088, 1.286090, +-0.161050, -0.940794, 0.367961, 0.291907 + +}; + +float32_t testInputB_f32[64] = +{ +0.933724, 0.046881, 1.316470, 0.438345, 0.332682, 2.094885, +0.512081, 0.035546, 0.050894, -2.320371, 0.168711, -1.830493, +-0.444834, -1.003242, -0.531494, -1.365600, -0.155420, -0.757692, +-0.431880, -0.380021, 0.096243, -0.695835, 0.558850, -1.648962, +0.020369, -0.363630, 0.887146, 0.845503, -0.252864, -0.330397, +1.269131, -1.109295, -1.027876, 0.135940, 0.116721, -0.293399, +-1.349799, 0.166078, -0.802201, 0.369367, -0.964568, -2.266011, +0.465178, 0.651222, -0.325426, 0.320245, -0.784178, -0.579456, +0.093374, 0.604778, -0.048225, 0.376297, -0.394412, 0.578182, +-1.218141, -1.387326, 0.692462, -0.631297, 0.153137, -0.638952, +0.635474, -0.970468, 1.334057, -0.111370 +}; + +const float testRefOutput_f32[126] = +{ +-0.818943, 1.229484, -0.533664, 1.016604, 0.341875, -1.963656, +5.171476, 3.478033, 7.616361, 6.648384, 0.479069, 1.792012, +-1.295591, -7.447818, 0.315830, -10.657445, -2.483469, -6.524236, +-7.380591, -3.739005, -8.388957, 0.184147, -1.554888, 3.786508, +-1.684421, 5.400610, -1.578126, 7.403361, 8.315999, 2.080267, +11.077776, 2.749673, 7.138962, 2.748762, 0.660363, 0.981552, +1.442275, 0.552721, -2.576892, 4.703989, 0.989156, 8.759344, +-0.564825, -3.994680, 0.954710, -5.014144, 6.592329, 1.599488, +-13.979146, -0.391891, -4.453369, -2.311242, -2.948764, 1.761415, +-0.138322, 10.433007, -2.309103, 4.297153, 8.535523, 3.209462, +8.695819, 5.569919, 2.514304, 5.582029, 2.060199, 0.642280, +7.024616, 1.686615, -6.481756, 1.343084, -3.526451, 1.099073, +-2.965764, -0.173723, -4.111484, 6.528384, -6.965658, 1.726291, +1.535172, 11.023435, 2.338401, -4.690188, 1.298210, 3.943885, +8.407885, 5.168365, 0.684131, 1.559181, 1.859998, 2.852417, +8.574070, -6.369078, 6.023458, 11.837963, -6.027632, 4.469678, +-6.799093, -2.674048, 6.250367, -6.809971, -3.459360, 9.112410, +-2.711621, -1.336678, 1.564249, -1.564297, -1.296760, 8.904013, +-3.230109, 6.878013, -7.819823, 3.369909, -1.657410, -2.007358, +-4.112825, 1.370685, -3.420525, -6.276605, 3.244873, -3.352638, +1.545372, 0.902211, 0.197489, -1.408732, 0.523390, 0.348440 +}; + + +/* ---------------------------------------------------------------------- +* Declare Global variables +* ------------------------------------------------------------------- */ +uint32_t srcALen = 64; /* Length of Input A */ +uint32_t srcBLen = 64; /* Length of Input B */ +uint32_t outLen; /* Length of convolution output */ +float32_t snr; /* output SNR */ + +int32_t main(void) +{ + arm_status status; /* Status of the example */ + arm_cfft_radix4_instance_f32 cfft_instance; /* CFFT Structure instance */ + + /* CFFT Structure instance pointer */ + arm_cfft_radix4_instance_f32 *cfft_instance_ptr = + (arm_cfft_radix4_instance_f32*) &cfft_instance; + + /* output length of convolution */ + outLen = srcALen + srcBLen - 1; + + /* Initialise the fft input buffers with all zeros */ + arm_fill_f32(0.0, Ak, MAX_BLOCKSIZE); + arm_fill_f32(0.0, Bk, MAX_BLOCKSIZE); + + /* Copy the input values to the fft input buffers */ + arm_copy_f32(testInputA_f32, Ak, MAX_BLOCKSIZE/2); + arm_copy_f32(testInputB_f32, Bk, MAX_BLOCKSIZE/2); + + /* Initialize the CFFT function to compute 64 point fft */ + status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 0, 1); + + /* Transform input a[n] from time domain to frequency domain A[k] */ + arm_cfft_radix4_f32(cfft_instance_ptr, Ak); + /* Transform input b[n] from time domain to frequency domain B[k] */ + arm_cfft_radix4_f32(cfft_instance_ptr, Bk); + + /* Complex Multiplication of the two input buffers in frequency domain */ + arm_cmplx_mult_cmplx_f32(Ak, Bk, AxB, MAX_BLOCKSIZE/2); + + /* Initialize the CIFFT function to compute 64 point ifft */ + status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 1, 1); + + /* Transform the multiplication output from frequency domain to time domain, + that gives the convolved output */ + arm_cfft_radix4_f32(cfft_instance_ptr, AxB); + + /* SNR Calculation */ + snr = arm_snr_f32((float32_t *)testRefOutput_f32, AxB, srcALen + srcBLen - 1); + + /* Compare the SNR with threshold to test whether the + computed output is matched with the reference output values. */ + if( snr > SNR_THRESHOLD) + { + status = ARM_MATH_SUCCESS; + } + + if( status != ARM_MATH_SUCCESS) + { + while(1); + } + + while(1); /* main function does not return */ +} + + /** \endlink */ + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/system_ARMCM0.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/system_ARMCM0.c new file mode 100644 index 000000000..ece74d2de --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/system_ARMCM0.c @@ -0,0 +1,76 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Cortex-M0 Device System Source File + * for CM0 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/system_ARMCM3.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/system_ARMCM3.c new file mode 100644 index 000000000..2f5fa0b93 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/system_ARMCM3.c @@ -0,0 +1,76 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Cortex-M3 Device System Source File + * for CM3 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/system_ARMCM4.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/system_ARMCM4.c new file mode 100644 index 000000000..beaaf6fb8 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_convolution_example/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Cortex-M4 Device System Source File + * for CM4 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM4.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ + #endif + + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM0l_dotproduct_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM0l_dotproduct_example.uvopt new file mode 100644 index 000000000..0c77fcd38 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM0l_dotproduct_example.uvopt @@ -0,0 +1,290 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M0 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + + 4803 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM0l_dotproduct_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_dotproduct_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + ARM_MATH_CM0 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_dotproduct_example_f32.c + 1 + ..\arm_dotproduct_example_f32.c + + + + + CMSIS Device + + + system_ARMCM0.c + 1 + ..\system_ARMCM0.c + + + startup_ARMCM0.s + 2 + .\startup_ARMCM0.s + + + + + CMSIS DSP_Library + + + arm_cortexM0l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib + + + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM3l_dotproduct_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM3l_dotproduct_example.uvopt new file mode 100644 index 000000000..4b80fb888 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM3l_dotproduct_example.uvopt @@ -0,0 +1,290 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_dotproduct_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 156 + 1 +
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_dotProduct_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 156 + 1 +
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_dotProduct_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_dotProduct_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_dotproduct_example_f32.c + 1 + ..\arm_dotproduct_example_f32.c + + + + + CMSIS Device + + + system_ARMCM4.c + 1 + ..\system_ARMCM4.c + + + startup_ARMCM4.s + 2 + .\startup_ARMCM4.s + + + + + CMSIS DSP_Library + + + arm_cortexM4lf_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + + + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_dotproduct_example.ini b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_dotproduct_example.ini new file mode 100644 index 000000000..df2ec0e5c --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_dotproduct_example.ini @@ -0,0 +1,12 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_dotproduct_example.ini + +*/ + +// usual initialisation for target setup +MAP 0x20000000, 0x20008000 READ WRITE // allow R/W access to IO space + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/startup_ARMCM0.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/startup_ARMCM0.s new file mode 100644 index 000000000..0acd34611 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/startup_ARMCM0.s @@ -0,0 +1,144 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Cortex-M0 Core Device Startup File +; * for CM0 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/startup_ARMCM3.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/startup_ARMCM3.s new file mode 100644 index 000000000..5af584bdc --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/startup_ARMCM3.s @@ -0,0 +1,164 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Cortex-M3 Core Device Startup File +; * for CM3 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/startup_ARMCM4.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/startup_ARMCM4.s new file mode 100644 index 000000000..09fdbd6ed --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/startup_ARMCM4.s @@ -0,0 +1,164 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Cortex-M4 Core Device Startup File +; * for CM4 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/arm_dotproduct_example_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/arm_dotproduct_example_f32.c new file mode 100644 index 000000000..f2acfbc07 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/arm_dotproduct_example_f32.c @@ -0,0 +1,163 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 29. November 2010 +* $Revision: V1.0.3 +* +* Project: CMSIS DSP Library +* Title: arm_dotproduct_example_f32.c +* +* Description: Example code computing dot product of two vectors. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.1 2010/10/05 KK +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 KK +* Production release and review comments incorporated. +* ------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup DotproductExample Dot Product Example + * + * \par Description: + * \par + * Demonstrates the use of the Multiply and Add functions to perform the dot product. + * The dot product of two vectors is obtained by multiplying corresponding elements + * and summing the products. + + * \par Algorithm: + * \par + * The two input vectors \c A and \c B with length \c n, are multiplied element-by-element + * and then added to obtain dot product. + * \par + * This is denoted by the following equation: + * 
  dotProduct = A[0] * B[0] + A[1] * B[1] + ... + A[n-1] * B[n-1]
+ * + * \par Block Diagram: + * \par + * \image html dotProduct.gif + * + * \par Variables Description: + * \par + * \li \c srcA_buf_f32 points to first input vector + * \li \c srcB_buf_f32 points to second input vector + * \li \c testOutput stores dot product of the two input vectors. + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_mult_f32() + * - arm_add_f32() + * + * Refer + * \link arm_dotproduct_example_f32.c \endlink + * + */ + + +/** \example arm_dotproduct_example_f32.c + */ + +#include +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +* Defines each of the tests performed +* ------------------------------------------------------------------- */ +#define MAX_BLOCKSIZE 32 +#define DELTA (0.000001f) + +/* ---------------------------------------------------------------------- +* Test input data for Floating point Dot Product example for 32-blockSize +* Generated by the MATLAB randn() function +* ------------------------------------------------------------------- */ +/* ---------------------------------------------------------------------- +** Test input data of srcA for blockSize 32 +** ------------------------------------------------------------------- */ +float32_t srcA_buf_f32[MAX_BLOCKSIZE] = +{ +-0.4325648115282207, -1.6655843782380970, 0.1253323064748307, + 0.2876764203585489, -1.1464713506814637, 1.1909154656429988, + 1.1891642016521031, -0.0376332765933176, 0.3272923614086541, + 0.1746391428209245, -0.1867085776814394, 0.7257905482933027, +-0.5883165430141887, 2.1831858181971011, -0.1363958830865957, + 0.1139313135208096, 1.0667682113591888, 0.0592814605236053, +-0.0956484054836690, -0.8323494636500225, 0.2944108163926404, +-1.3361818579378040, 0.7143245518189522, 1.6235620644462707, +-0.6917757017022868, 0.8579966728282626, 1.2540014216025324, +-1.5937295764474768, -1.4409644319010200, 0.5711476236581780, +-0.3998855777153632, 0.6899973754643451 +}; + +/* ---------------------------------------------------------------------- +** Test input data of srcB for blockSize 32 +** ------------------------------------------------------------------- */ +float32_t srcB_buf_f32[MAX_BLOCKSIZE] = +{ + 1.7491401329284098, 0.1325982188803279, 0.3252281811989881, +-0.7938091410349637, 0.3149236145048914, -0.5272704888029532, + 0.9322666565031119, 1.1646643544607362, -2.0456694357357357, +-0.6443728590041911, 1.7410657940825480, 0.4867684246821860, + 1.0488288293660140, 1.4885752747099299, 1.2705014969484090, +-1.8561241921210170, 2.1343209047321410, 1.4358467535865909, +-0.9173023332875400, -1.1060770780029008, 0.8105708062681296, + 0.6985430696369063, -0.4015827425012831, 1.2687512030669628, +-0.7836083053674872, 0.2132664971465569, 0.7878984786088954, + 0.8966819356782295, -0.1869172943544062, 1.0131816724341454, + 0.2484350696132857, 0.0596083377937976 +}; + +/* Reference dot product output */ +float32_t refDotProdOut = 5.9273644806352142; + +/* ---------------------------------------------------------------------- +* Declare Global variables +* ------------------------------------------------------------------- */ +float32_t multOutput[MAX_BLOCKSIZE]; /* Intermediate output */ +float32_t testOutput; /* Final ouput */ + +arm_status status; /* Status of the example */ + +int32_t main(void) +{ + uint32_t i; /* Loop counter */ + float32_t diff; /* Difference between reference and test outputs */ + + /* Multiplication of two input buffers */ + arm_mult_f32(srcA_buf_f32, srcB_buf_f32, multOutput, MAX_BLOCKSIZE); + + /* Accumulate the multiplication output values to + get the dot product of the two inputs */ + for(i=0; i< MAX_BLOCKSIZE; i++) + { + arm_add_f32(&testOutput, &multOutput[i], &testOutput, 1); + } + + /* absolute value of difference between ref and test */ + diff = fabsf(refDotProdOut - testOutput); + + /* Comparison of dot product value with reference */ + if(diff > DELTA) + { + status = ARM_MATH_TEST_FAILURE; + } + + if( status == ARM_MATH_TEST_FAILURE) + { + while(1); + } + + while(1); /* main function does not return */ +} + + /** \endlink */ + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/system_ARMCM0.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/system_ARMCM0.c new file mode 100644 index 000000000..ece74d2de --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/system_ARMCM0.c @@ -0,0 +1,76 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Cortex-M0 Device System Source File + * for CM0 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/system_ARMCM3.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/system_ARMCM3.c new file mode 100644 index 000000000..2f5fa0b93 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/system_ARMCM3.c @@ -0,0 +1,76 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Cortex-M3 Device System Source File + * for CM3 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/system_ARMCM4.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/system_ARMCM4.c new file mode 100644 index 000000000..beaaf6fb8 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Cortex-M4 Device System Source File + * for CM4 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM4.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ + #endif + + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM0l_fft_bin_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM0l_fft_bin_example.uvopt new file mode 100644 index 000000000..a5def4886 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM0l_fft_bin_example.uvopt @@ -0,0 +1,304 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_fft_bin_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 143 + 1 +
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M0 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + + 4803 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM0l_fft_bin_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_fft_bin_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + ARM_MATH_CM0 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_fft_bin_example_f32.c + 1 + ..\arm_fft_bin_example_f32.c + + + arm_fft_bin_data.c + 1 + ..\arm_fft_bin_data.c + + + + + CMSIS Device + + + system_ARMCM0.c + 1 + ..\system_ARMCM0.c + + + startup_ARMCM0.s + 2 + .\startup_ARMCM0.s + + + + + CMSIS DSP_Library + + + arm_cortexM0l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib + + + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM3l_fft_bin_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM3l_fft_bin_example.uvopt new file mode 100644 index 000000000..39bfd9cad --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM3l_fft_bin_example.uvopt @@ -0,0 +1,304 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_fft_bin_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 143 + 1 +
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M3 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE + + + + 4349 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM3l_fft_bin_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_fft_bin_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM3 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_fft_bin_data.c + 1 + ..\arm_fft_bin_data.c + + + arm_fft_bin_example_f32.c + 1 + ..\arm_fft_bin_example_f32.c + + + + + CMSIS Device + + + system_ARMCM3.c + 1 + ..\system_ARMCM3.c + + + startup_ARMCM3.s + 2 + .\startup_ARMCM3.s + + + + + CMSIS DSP_Library + + + arm_cortexM3l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM3l_math.lib + + + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM4lf_fft_bin_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM4lf_fft_bin_example.uvopt new file mode 100644 index 000000000..12356134f --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM4lf_fft_bin_example.uvopt @@ -0,0 +1,304 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_fft_bin_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 143 + 1 +
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+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM4lf_fft_bin_example\../arm_fft_bin_example_f32.c\146 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\arm_fft_bin_data.c + arm_fft_bin_data.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + ..\arm_fft_bin_example_f32.c + arm_fft_bin_example_f32.c + + + + + CMSIS DeviceSupport + 1 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\system_ARMCM4.c + system_ARMCM4.c + + + 2 + 4 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\startup_ARMCM4.s + startup_ARMCM4.s + + + + + CMSIS SW_DSP_Library + 1 + 0 + 0 + + 3 + 5 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + arm_cortexM4lf_math.lib + + + + + 1 + 0 + + 100 + 0 + + + ..\arm_fft_bin_example_f32.c + 0 + 1 + 1 + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM4lf_fft_bin_example.uvproj b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM4lf_fft_bin_example.uvproj new file mode 100644 index 000000000..5fe326d79 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM4lf_fft_bin_example.uvproj @@ -0,0 +1,430 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_fft_bin_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_fft_bin_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_fft_bin_data.c + 1 + ..\arm_fft_bin_data.c + + + arm_fft_bin_example_f32.c + 1 + ..\arm_fft_bin_example_f32.c + + + + + CMSIS Device + + + system_ARMCM4.c + 1 + ..\system_ARMCM4.c + + + startup_ARMCM4.s + 2 + .\startup_ARMCM4.s + + + + + CMSIS DSP_Library + + + arm_cortexM4lf_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + + + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_fft_bin_example.ini b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_fft_bin_example.ini new file mode 100644 index 000000000..fdf91bebf --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_fft_bin_example.ini @@ -0,0 +1,12 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_fft_bin_example.ini + +*/ + +// usual initialisation for target setup +MAP 0x20000000, 0x20008000 READ WRITE // allow R/W access to IO space + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/startup_ARMCM0.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/startup_ARMCM0.s new file mode 100644 index 000000000..0acd34611 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/startup_ARMCM0.s @@ -0,0 +1,144 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Cortex-M0 Core Device Startup File +; * for CM0 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/startup_ARMCM3.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/startup_ARMCM3.s new file mode 100644 index 000000000..5af584bdc --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/startup_ARMCM3.s @@ -0,0 +1,164 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Cortex-M3 Core Device Startup File +; * for CM3 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/startup_ARMCM4.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/startup_ARMCM4.s new file mode 100644 index 000000000..09fdbd6ed --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/startup_ARMCM4.s @@ -0,0 +1,164 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Cortex-M4 Core Device Startup File +; * for CM4 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/arm_fft_bin_data.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/arm_fft_bin_data.c new file mode 100644 index 000000000..64c9df249 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/arm_fft_bin_data.c @@ -0,0 +1,268 @@ +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +Test Input signal contains 10KHz signal + Uniformly distributed white noise +** ------------------------------------------------------------------- */ + +float32_t testInput_f32_10khz[2048] = +{ +-0.865129623056441, 0.000000000000000, -2.655020678073846, 0.000000000000000, 0.600664612949661, 0.000000000000000, 0.080378093886515, 0.000000000000000, +-2.899160484012034, 0.000000000000000, 2.563004262857762, 0.000000000000000, 3.078328403304206, 0.000000000000000, 0.105906778385130, 0.000000000000000, +0.048366940168201, 0.000000000000000, -0.145696461188734, 0.000000000000000, -0.023417155362879, 0.000000000000000, 2.127729174988954, 0.000000000000000, +-1.176633086028377, 0.000000000000000, 3.690223557991855, 0.000000000000000, -0.622791766173194, 0.000000000000000, 0.722837373872203, 0.000000000000000, +2.739754205367484, 0.000000000000000, -0.062610410524552, 0.000000000000000, -0.891296810967338, 0.000000000000000, -1.845872258871811, 0.000000000000000, +1.195039415434387, 0.000000000000000, -2.177388969045026, 0.000000000000000, 1.078649103637905, 0.000000000000000, 2.570976050490193, 0.000000000000000, +-1.383551403404574, 0.000000000000000, 2.392141424058873, 0.000000000000000, 2.858002843205065, 0.000000000000000, -3.682433899725536, 0.000000000000000, +-3.488146646451150, 0.000000000000000, 1.323468578888120, 0.000000000000000, -0.099771155430726, 0.000000000000000, 1.561168082500454, 0.000000000000000, +1.025026795103179, 0.000000000000000, 0.928841900171200, 0.000000000000000, 2.930499509864950, 0.000000000000000, 2.013349089766430, 0.000000000000000, +2.381676148486737, 0.000000000000000, -3.081062307950236, 0.000000000000000, -0.389579115537544, 0.000000000000000, 0.181540149166620, 0.000000000000000, +-2.601953341353208, 0.000000000000000, 0.333435137783218, 0.000000000000000, -2.812945856162965, 0.000000000000000, 2.649109640172910, 0.000000000000000, +-1.003963025744654, 0.000000000000000, 1.552460768755035, 0.000000000000000, 0.088641345335247, 0.000000000000000, -2.519951327113426, 0.000000000000000, +-4.341348988610527, 0.000000000000000, 0.557772429359965, 0.000000000000000, -1.671267412948494, 0.000000000000000, 0.733951350960387, 0.000000000000000, +0.409263788034864, 0.000000000000000, 3.566033071952806, 0.000000000000000, 1.882565173848352, 0.000000000000000, -1.106017073793287, 0.000000000000000, +0.154456720778718, 0.000000000000000, -2.513205795512153, 0.000000000000000, 0.310978660939421, 0.000000000000000, 0.579706500111723, 0.000000000000000, +0.000086383683251, 0.000000000000000, -1.311866980897721, 0.000000000000000, 1.840007477574986, 0.000000000000000, -3.253005768451345, 0.000000000000000, +1.462584328739432, 0.000000000000000, 1.610103610851738, 0.000000000000000, 0.761914676858907, 0.000000000000000, 0.974541361089834, 0.000000000000000, +0.686845845885983, 0.000000000000000, 1.849153122025191, 0.000000000000000, 0.787800410401453, 0.000000000000000, -1.187438909666279, 0.000000000000000, +-0.754937911044720, 0.000000000000000, 0.084373858395232, 0.000000000000000, -2.600269011710521, 0.000000000000000, -0.962982842142644, 0.000000000000000, +-0.369328108540868, 0.000000000000000, 0.810791418361879, 0.000000000000000, 3.587016488699641, 0.000000000000000, -0.520776145083723, 0.000000000000000, +0.640249919627884, 0.000000000000000, 1.103122489464969, 0.000000000000000, 2.231779881455556, 0.000000000000000, -1.308035392685241, 0.000000000000000, +0.424070304330106, 0.000000000000000, -0.200383932651189, 0.000000000000000, -2.365526783356541, 0.000000000000000, -0.989114757436628, 0.000000000000000, +2.770807688959777, 0.000000000000000, -0.444172737462307, 0.000000000000000, 0.079760979374078, 0.000000000000000, -0.005199118412183, 0.000000000000000, +-0.664712668309527, 0.000000000000000, -0.624171857561896, 0.000000000000000, 0.537306979007338, 0.000000000000000, -2.575955675497642, 0.000000000000000, +1.562363235756780, 0.000000000000000, 1.814069369848895, 0.000000000000000, -1.293428583392509, 0.000000000000000, -1.026188449495686, 0.000000000000000, +-2.981771815588717, 0.000000000000000, -4.223468103075124, 0.000000000000000, 2.672674782004045, 0.000000000000000, -0.856096801117735, 0.000000000000000, +0.048517345512563, 0.000000000000000, -0.026860721136222, 0.000000000000000, 0.392932277758187, 0.000000000000000, -1.331740855093099, 0.000000000000000, +-1.894292129477081, 0.000000000000000, -1.425006468460681, 0.000000000000000, -2.721772427617057, 0.000000000000000, -1.616831100216806, 0.000000000000000, +3.551177651488947, 0.000000000000000, -0.069685667896087, 0.000000000000000, -3.134634907409102, 0.000000000000000, -0.263627598944639, 0.000000000000000, +-1.650469945991350, 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---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 29. November 2010 +* $Revision: V1.0.3 +* +* Project: CMSIS DSP Library +* Title: arm_fft_bin_example_f32.c +* +* Description: Example code demonstrating calculation of Max energy bin of +* frequency domain of input signal. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.1 2010/10/05 KK +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 KK +* Production release and review comments incorporated. +* ------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup FrequencyBin Frequency Bin Example + * + * \par Description + * \par + * Demonstrates the calculation of the maximum energy bin in the frequency + * domain of the input signal with the use of Complex FFT, Complex + * Magnitude, and Maximum functions. + * + * \par Algorithm: + * \par + * The input test signal contains a 10 kHz signal with uniformly distributed white noise. + * Calculating the FFT of the input signal will give us the maximum energy of the + * bin corresponding to the input frequency of 10 kHz. + * + * \par Block Diagram: + * \image html FFTBin.gif "Block Diagram" + * \par + * The figure below shows the time domain signal of 10 kHz signal with + * uniformly distributed white noise, and the next figure shows the input + * in the frequency domain. The bin with maximum energy corresponds to 10 kHz signal. + * \par + * \image html FFTBinInput.gif "Input signal in Time domain" + * \image html FFTBinOutput.gif "Input signal in Frequency domain" + * + * \par Variables Description: + * \par + * \li \c testInput_f32_10khz points to the input data + * \li \c testOutput points to the output data + * \li \c fftSize length of FFT + * \li \c ifftFlag flag for the selection of CFFT/CIFFT + * \li \c doBitReverse Flag for selection of normal order or bit reversed order + * \li \c refIndex reference index value at which maximum energy of bin ocuurs + * \li \c testIndex calculated index value at which maximum energy of bin ocuurs + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_cfft_radix4_init_f32() + * - arm_cfft_radix4_f32() + * - arm_cmplx_mag_f32() + * - arm_max_f32() + * + * Refer + * \link arm_fft_bin_example_f32.c \endlink + * + */ + + +/** \example arm_fft_bin_example_f32.c + */ + + +#include "arm_math.h" + +#define TEST_LENGTH_SAMPLES 2048 + +/* ------------------------------------------------------------------- +* External Input and Output buffer Declarations for FFT Bin Example +* ------------------------------------------------------------------- */ +extern float32_t testInput_f32_10khz[TEST_LENGTH_SAMPLES]; +static float32_t testOutput[TEST_LENGTH_SAMPLES/2]; + +/* ------------------------------------------------------------------ +* Global variables for FFT Bin Example +* ------------------------------------------------------------------- */ +uint32_t fftSize = 1024; +uint32_t ifftFlag = 0; +uint32_t doBitReverse = 1; + +/* Reference index at which max energy of bin ocuurs */ +uint32_t refIndex = 213, testIndex = 0; + +/* ---------------------------------------------------------------------- +* Max magnitude FFT Bin test +* ------------------------------------------------------------------- */ + +int32_t main(void) +{ + + arm_status status; + arm_cfft_radix4_instance_f32 S; + float32_t maxValue; + + status = ARM_MATH_SUCCESS; + + /* Initialize the CFFT/CIFFT module */ + status = arm_cfft_radix4_init_f32(&S, fftSize, + ifftFlag, doBitReverse); + + /* Process the data through the CFFT/CIFFT module */ + arm_cfft_radix4_f32(&S, testInput_f32_10khz); + + + /* Process the data through the Complex Magnitude Module for + calculating the magnitude at each bin */ + arm_cmplx_mag_f32(testInput_f32_10khz, testOutput, + fftSize); + + /* Calculates maxValue and returns corresponding BIN value */ + arm_max_f32(testOutput, fftSize, &maxValue, &testIndex); + + if(testIndex != refIndex) + { + status = ARM_MATH_TEST_FAILURE; + } + + /* ---------------------------------------------------------------------- + ** Loop here if the signals fail the PASS check. + ** This denotes a test failure + ** ------------------------------------------------------------------- */ + + if( status != ARM_MATH_SUCCESS) + { + while(1); + } + + while(1); /* main function does not return */ +} + + /** \endlink */ + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/system_ARMCM0.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/system_ARMCM0.c new file mode 100644 index 000000000..ece74d2de --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/system_ARMCM0.c @@ -0,0 +1,76 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Cortex-M0 Device System Source File + * for CM0 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/system_ARMCM3.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/system_ARMCM3.c new file mode 100644 index 000000000..2f5fa0b93 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/system_ARMCM3.c @@ -0,0 +1,76 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Cortex-M3 Device System Source File + * for CM3 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/system_ARMCM4.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/system_ARMCM4.c new file mode 100644 index 000000000..beaaf6fb8 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Cortex-M4 Device System Source File + * for CM4 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM4.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ + #endif + + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM0l_fir_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM0l_fir_example.uvopt new file mode 100644 index 000000000..0c6ce4117 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM0l_fir_example.uvopt @@ -0,0 +1,318 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_fir_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 211 + 1 +
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390
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM4lf_fir_example\../arm_fir_example_f32.c\214 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 77 + 0 + 0 + 0 + 0 + ..\arm_fir_data.c + arm_fir_data.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + ..\arm_fir_example_f32.c + arm_fir_example_f32.c + + + 1 + 3 + 1 + 0 + 0 + 16 + 0 + 0 + 0 + 0 + ..\..\Common\Source\math_helper.c + math_helper.c + + + + + CMSIS DeviceSupport + 1 + 0 + 0 + + 2 + 4 + 1 + 0 + 0 + 43 + 0 + 0 + 0 + 0 + ..\system_ARMCM4.c + system_ARMCM4.c + + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\startup_ARMCM4.s + startup_ARMCM4.s + + + + + CMSIS SW_DSP_Library + 1 + 0 + 0 + + 3 + 6 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + arm_cortexM4lf_math.lib + + + + + 1 + 0 + + 100 + 0 + + + ..\arm_fir_example_f32.c + 0 + 1 + 1 + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM4lf_fir_example.uvproj b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM4lf_fir_example.uvproj new file mode 100644 index 000000000..8d68e4415 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM4lf_fir_example.uvproj @@ -0,0 +1,435 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_fir_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_fir_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\Common\Include;..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_fir_data.c + 1 + ..\arm_fir_data.c + + + arm_fir_example_f32.c + 1 + ..\arm_fir_example_f32.c + + + math_helper.c + 1 + ..\..\Common\Source\math_helper.c + + + + + CMSIS Device + + + system_ARMCM4.c + 1 + ..\system_ARMCM4.c + + + startup_ARMCM4.s + 2 + .\startup_ARMCM4.s + + + + + CMSIS DSP_Library + + + arm_cortexM4lf_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + + + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_fir_example.ini b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_fir_example.ini new file mode 100644 index 000000000..06c86a62d --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_fir_example.ini @@ -0,0 +1,12 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_fir_lpf_example.ini + +*/ + +// usual initialisation for target setup +MAP 0x20000000, 0x20008000 READ WRITE // allow R/W access to IO space + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/startup_ARMCM0.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/startup_ARMCM0.s new file mode 100644 index 000000000..0acd34611 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/startup_ARMCM0.s @@ -0,0 +1,144 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Cortex-M0 Core Device Startup File +; * for CM0 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/startup_ARMCM3.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/startup_ARMCM3.s new file mode 100644 index 000000000..5af584bdc --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/startup_ARMCM3.s @@ -0,0 +1,164 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Cortex-M3 Core Device Startup File +; * for CM3 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/startup_ARMCM4.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/startup_ARMCM4.s new file mode 100644 index 000000000..09fdbd6ed --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/startup_ARMCM4.s @@ -0,0 +1,164 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Cortex-M4 Core Device Startup File +; * for CM4 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/arm_fir_data.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/arm_fir_data.c new file mode 100644 index 000000000..e2e9ad658 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/arm_fir_data.c @@ -0,0 +1,94 @@ +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +** Test input signal contains 1000Hz + 15000 Hz +** ------------------------------------------------------------------- */ + +float32_t testInput_f32_1kHz_15kHz[320] = +{ ++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, +-0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, ++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, ++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, +-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, +-0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, ++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, +-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, +-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +}; + +float32_t refOutput[320] = +{ ++0.0000000000f, -0.0010797829f, -0.0007681386f, -0.0001982932f, +0.0000644313f, +0.0020854271f, +0.0036891871f, +0.0015855941f, +-0.0026280805f, -0.0075907658f, -0.0119390538f, -0.0086665968f, +0.0088981202f, +0.0430539279f, +0.0974468742f, +0.1740405600f, ++0.2681416601f, +0.3747720089f, +0.4893362230f, +0.6024154672f, +0.7058740791f, +0.7968348987f, +0.8715901940f, +0.9277881093f, ++0.9682182661f, +0.9934674267f, +1.0012052245f, +0.9925859371f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, -0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, -0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, -0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, +0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, +0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, -0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, +0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f +}; + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/arm_fir_example_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/arm_fir_example_f32.c new file mode 100644 index 000000000..37897e094 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/arm_fir_example_f32.c @@ -0,0 +1,220 @@ +/* ---------------------------------------------------------------------- + * Copyright (C) 2010 ARM Limited. All rights reserved. + * + * $Date: 29. November 2010 + * $Revision: V1.0.3 + * + * Project: CMSIS DSP Library + * Title: arm_fir_example_f32.c + * + * Description: Example code demonstrating how an FIR filter can be used + * as a low pass filter. + * + * Target Processor: Cortex-M4/Cortex-M3 + * + * + * Version 1.0.3 2010/11/29 + * Re-organized the CMSIS folders and updated documentation. + * + * Version 1.0.1 2010/10/05 KK + * Production release and review comments incorporated. + * + * Version 1.0.0 2010/09/20 KK + * Production release and review comments incorporated. + * ------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup FIRLPF FIR Lowpass Filter Example + * + * \par Description: + * \par + * Removes high frequency signal components from the input using an FIR lowpass filter. + * The example demonstrates how to configure an FIR filter and then pass data through + * it in a block-by-block fashion. + * \image html FIRLPF_signalflow.gif + * + * \par Algorithm: + * \par + * The input signal is a sum of two sine waves: 1 kHz and 15 kHz. + * This is processed by an FIR lowpass filter with cutoff frequency 6 kHz. + * The lowpass filter eliminates the 15 kHz signal leaving only the 1 kHz sine wave at the output. + * \par + * The lowpass filter was designed using MATLAB with a sample rate of 48 kHz and + * a length of 29 points. + * The MATLAB code to generate the filter coefficients is shown below: + * 
+ *     h = fir1(28, 6/24);
+ *
+ * The first argument is the "order" of the filter and is always one less than the desired length. + * The second argument is the normalized cutoff frequency. This is in the range 0 (DC) to 1.0 (Nyquist). + * A 6 kHz cutoff with a Nyquist frequency of 24 kHz lies at a normalized frequency of 6/24 = 0.25. + * The CMSIS FIR filter function requires the coefficients to be in time reversed order. + * 
+ *     fliplr(h)
+ *
+ * The resulting filter coefficients and are shown below. + * Note that the filter is symmetric (a property of linear phase FIR filters) + * and the point of symmetry is sample 14. Thus the filter will have a delay of + * 14 samples for all frequencies. + * \par + * \image html FIRLPF_coeffs.gif + * \par + * The frequency response of the filter is shown next. + * The passband gain of the filter is 1.0 and it reaches 0.5 at the cutoff frequency 6 kHz. + * \par + * \image html FIRLPF_response.gif + * \par + * The input signal is shown below. + * The left hand side shows the signal in the time domain while the right hand side is a frequency domain representation. + * The two sine wave components can be clearly seen. + * \par + * \image html FIRLPF_input.gif + * \par + * The output of the filter is shown below. The 15 kHz component has been eliminated. + * \par + * \image html FIRLPF_output.gif + * + * \par Variables Description: + * \par + * \li \c testInput_f32_1kHz_15kHz points to the input data + * \li \c refOutput points to the reference output data + * \li \c testOutput points to the test output data + * \li \c firStateF32 points to state buffer + * \li \c firCoeffs32 points to coefficient buffer + * \li \c blockSize number of samples processed at a time + * \li \c numBlocks number of frames + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_fir_init_f32() + * - arm_fir_f32() + * + * Refer + * \link arm_fir_example_f32.c \endlink + * + */ + + +/** \example arm_fir_example_f32.c + */ + +/* ---------------------------------------------------------------------- +** Include Files +** ------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "math_helper.h" + +/* ---------------------------------------------------------------------- +** Macro Defines +** ------------------------------------------------------------------- */ + +#define TEST_LENGTH_SAMPLES 320 +#define SNR_THRESHOLD_F32 140.0f +#define BLOCK_SIZE 32 +#define NUM_TAPS 29 + +/* ------------------------------------------------------------------- + * The input signal and reference output (computed with MATLAB) + * are defined externally in arm_fir_lpf_data.c. + * ------------------------------------------------------------------- */ + +extern float32_t testInput_f32_1kHz_15kHz[TEST_LENGTH_SAMPLES]; +extern float32_t refOutput[TEST_LENGTH_SAMPLES]; + +/* ------------------------------------------------------------------- + * Declare Test output buffer + * ------------------------------------------------------------------- */ + +static float32_t testOutput[TEST_LENGTH_SAMPLES]; + +/* ------------------------------------------------------------------- + * Declare State buffer of size (numTaps + blockSize - 1) + * ------------------------------------------------------------------- */ + +static float32_t firStateF32[BLOCK_SIZE + NUM_TAPS - 1]; + +/* ---------------------------------------------------------------------- +** FIR Coefficients buffer generated using fir1() MATLAB function. +** fir1(28, 6/24) +** ------------------------------------------------------------------- */ + +const float32_t firCoeffs32[NUM_TAPS] = { +-0.0018225230f, -0.0015879294f, +0.0000000000f, +0.0036977508f, +0.0080754303f, +0.0085302217f, -0.0000000000f, -0.0173976984f, +-0.0341458607f, -0.0333591565f, +0.0000000000f, +0.0676308395f, +0.1522061835f, +0.2229246956f, +0.2504960933f, +0.2229246956f, ++0.1522061835f, +0.0676308395f, +0.0000000000f, -0.0333591565f, -0.0341458607f, -0.0173976984f, -0.0000000000f, +0.0085302217f, ++0.0080754303f, +0.0036977508f, +0.0000000000f, -0.0015879294f, -0.0018225230f +}; + +/* ------------------------------------------------------------------ + * Global variables for FIR LPF Example + * ------------------------------------------------------------------- */ + +uint32_t blockSize = BLOCK_SIZE; +uint32_t numBlocks = TEST_LENGTH_SAMPLES/BLOCK_SIZE; + +float32_t snr; + +/* ---------------------------------------------------------------------- + * FIR LPF Example + * ------------------------------------------------------------------- */ + +int32_t main(void) +{ + uint32_t i; + arm_fir_instance_f32 S; + arm_status status; + float32_t *inputF32, *outputF32; + + /* Initialize input and output buffer pointers */ + inputF32 = &testInput_f32_1kHz_15kHz[0]; + outputF32 = &testOutput[0]; + + /* Call FIR init function to initialize the instance structure. */ + arm_fir_init_f32(&S, NUM_TAPS, (float32_t *)&firCoeffs32[0], &firStateF32[0], blockSize); + + /* ---------------------------------------------------------------------- + ** Call the FIR process function for every blockSize samples + ** ------------------------------------------------------------------- */ + + for(i=0; i < numBlocks; i++) + { + arm_fir_f32(&S, inputF32 + (i * blockSize), outputF32 + (i * blockSize), blockSize); + } + + /* ---------------------------------------------------------------------- + ** Compare the generated output against the reference output computed + ** in MATLAB. + ** ------------------------------------------------------------------- */ + + snr = arm_snr_f32(&refOutput[0], &testOutput[0], TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) + { + status = ARM_MATH_TEST_FAILURE; + } + else + { + status = ARM_MATH_SUCCESS; + } + + /* ---------------------------------------------------------------------- + ** Loop here if the signal does not match the reference output. + ** ------------------------------------------------------------------- */ + + if( status != ARM_MATH_SUCCESS) + { + while(1); + } + + while(1); /* main function does not return */ +} + +/** \endlink */ + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/system_ARMCM0.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/system_ARMCM0.c new file mode 100644 index 000000000..ece74d2de --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/system_ARMCM0.c @@ -0,0 +1,76 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Cortex-M0 Device System Source File + * for CM0 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/system_ARMCM3.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/system_ARMCM3.c new file mode 100644 index 000000000..2f5fa0b93 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/system_ARMCM3.c @@ -0,0 +1,76 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Cortex-M3 Device System Source File + * for CM3 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/system_ARMCM4.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/system_ARMCM4.c new file mode 100644 index 000000000..beaaf6fb8 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_fir_example/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Cortex-M4 Device System Source File + * for CM4 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM4.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ + #endif + + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM0l_graphic_equalizer_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM0l_graphic_equalizer_example.uvopt new file mode 100644 index 000000000..bcef850a6 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM0l_graphic_equalizer_example.uvopt @@ -0,0 +1,318 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM4lf_graphic_equalizer_example\../arm_graphic_equalizer_example_q31.c\389 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\arm_graphic_equalizer_data.c + arm_graphic_equalizer_data.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + ..\arm_graphic_equalizer_example_q31.c + arm_graphic_equalizer_example_q31.c + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Common\Source\math_helper.c + math_helper.c + + + + + CMSIS DeviceSupport + 1 + 0 + 0 + + 2 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\system_ARMCM4.c + system_ARMCM4.c + + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\startup_ARMCM4.s + startup_ARMCM4.s + + + + + CMSIS SW_DSP_Library + 1 + 0 + 0 + + 3 + 6 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + arm_cortexM4lf_math.lib + + + + + 1 + 0 + + 100 + 0 + + + ..\arm_graphic_equalizer_example_q31.c + 0 + 1 + 1 + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM4lf_graphic_equalizer_example.uvproj b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM4lf_graphic_equalizer_example.uvproj new file mode 100644 index 000000000..71acd00ed --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM4lf_graphic_equalizer_example.uvproj @@ -0,0 +1,435 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_graphic_equalizer_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_graphic_equalizer_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_graphic_equalizer_data.c + 1 + ..\arm_graphic_equalizer_data.c + + + arm_graphic_equalizer_example_q31.c + 1 + ..\arm_graphic_equalizer_example_q31.c + + + math_helper.c + 1 + ..\..\Common\Source\math_helper.c + + + + + CMSIS Device + + + system_ARMCM4.c + 1 + ..\system_ARMCM4.c + + + startup_ARMCM4.s + 2 + .\startup_ARMCM4.s + + + + + CMSIS DSP_Library + + + arm_cortexM4lf_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + + + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_graphic_equalizer_example.ini b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_graphic_equalizer_example.ini new file mode 100644 index 000000000..4e1a3e43d --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_graphic_equalizer_example.ini @@ -0,0 +1,14 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_geq_5band_example.ini + +*/ + + +// usual initialisation for target setup +MAP 0x20000000, 0x20008000 READ WRITE // allow R/W access to IO space + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/startup_ARMCM0.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/startup_ARMCM0.s new file mode 100644 index 000000000..0acd34611 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/startup_ARMCM0.s @@ -0,0 +1,144 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Cortex-M0 Core Device Startup File +; * for CM0 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/startup_ARMCM3.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/startup_ARMCM3.s new file mode 100644 index 000000000..5af584bdc --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/startup_ARMCM3.s @@ -0,0 +1,164 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Cortex-M3 Core Device Startup File +; * for CM3 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/startup_ARMCM4.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/startup_ARMCM4.s new file mode 100644 index 000000000..09fdbd6ed --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/startup_ARMCM4.s @@ -0,0 +1,164 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Cortex-M4 Core Device Startup File +; * for CM4 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c new file mode 100644 index 000000000..b1a314e8b --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c @@ -0,0 +1,94 @@ +#include "arm_math.h" + +float32_t testRefOutput_f32[320] = { + +0.000000000000000000, 0.001898396760225296, 0.004215449094772339, 0.007432077080011368, 0.010948467999696732, 0.015026375651359558, 0.019191544502973557, 0.023574527353048325, +0.027919445186853409, 0.032277785241603851, 0.036551639437675476, 0.040732793509960175, 0.044799156486988068, 0.048710610717535019, 0.052476800978183746, 0.056059073656797409, +0.059482168406248093, 0.062726479023694992, 0.065821025520563126, 0.068763464689254761, 0.071577839553356171, 0.074270240962505341, 0.076856281608343124, 0.079344697296619415, +0.081745062023401260, 0.084067162126302719, 0.086318407207727432, 0.088509257882833481, 0.090647127479314804, 0.092742368578910828, 0.094802625477313995, 0.096837285906076431, +0.098853722214698792, 0.100859899073839190, 0.102862443774938580, 0.104867763817310330, 0.106881409883499150, 0.108908228576183320, 0.110952425748109820, 0.113017357885837550, +0.115105822682380680, 0.117219865322113040, 0.119361080229282380, 0.121530555188655850, 0.123729091137647630, 0.125957202166318890, 0.128215309232473370, 0.130503740161657330, +0.132822841405868530, 0.135173004120588300, 0.137554679065942760, 0.139968376606702800, 0.142414685338735580, 0.144894234836101530, 0.147407654672861100, 0.149955596774816510, +0.152538605034351350, 0.155157200992107390, 0.157811731100082400, 0.160502441227436070, 0.163229387253522870, 0.165992442518472670, 0.168791320174932480, 0.171625509858131410, +0.174494370818138120, 0.177397061139345170, 0.180332608520984650, 0.183299910277128220, 0.186297744512557980, 0.189324837177991870, 0.192379791289567950, 0.195461250841617580, +0.198567759245634080, 0.201697919517755510, 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0.994262944906950000, 0.996163722127676010, 0.998020399361848830, 0.999832402914762500, 1.001599155366420700, +1.003320086747407900, 1.004994612187147100, 1.006622135639190700, 1.008202098309993700, 1.009733878076076500, 1.011216927319765100, 1.012650609016418500, 1.014034371823072400, +1.015367589890956900, 1.016649682074785200, 1.017880033701658200, 1.019058048725128200, 1.020183108747005500, 1.021254621446132700, 1.022271949797868700, 1.023234523832798000, + +}; +/* ---------------------------------------------------------------------- +** Test input - logarithmic chirp signal +** ------------------------------------------------------------------- */ + +float32_t testInput_f32[320] = + { + 0.000000000000000061, 0.002622410992047861, 0.005253663973466970, 0.007893770384930297, 0.010542741395035495, 0.013200587895525877, 0.015867320496454066, 0.018542949521290073, +0.021227485001971542, 0.023920936673895138, 0.026623313970853074, 0.029334626019908643, 0.032054881636210709, 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0.945759008001275100, 0.947949942849885320, 0.950104073472023970, 0.952220875168933280, 0.954299819839202090, +0.956340376000621160, 0.958342008813221960, 0.960304180103520260, 0.962226348389994210, 0.964107968909812760, 0.965948493646846980, 0.967747371360983650, 0.969504047618768740, +0.971217964825405680, 0.972888562258134030, 0.974515276101013520, 0.976097539481141750, 0.977634782506330400, 0.979126432304266880, 0.980571913063189360, 0.981970646074102120, +0.983322049774557390, 0.984625539794035220, 0.985880529000944810, 0.987086427551279730, 0.988242642938953360, 0.989348580047844540, 0.990403641205582440, 0.991407226239099710, +0.992358732531984260, 0.993257555083659870, 0.994103086570423680, 0.994894717408374870, 0.995631835818261310, 0.996313827892278070, 0.996940077662846650, 0.997509967173408010, + + }; diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c new file mode 100644 index 000000000..82345d4fd --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c @@ -0,0 +1,395 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 29. November 2010 +* $Revision: V1.0.3 +* +* Project: CMSIS DSP Library +* Title: arm_graphic_equalizer_example_q31.c +* +* Description: Example showing an audio graphic equalizer constructed +* out of Biquad filters. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.1 2010/10/05 KK +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 KK +* Production release and review comments incorporated. +* ------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup GEQ5Band Graphic Audio Equalizer Example + * + * \par Description: + * \par + * This example demonstrates how a 5-band graphic equalizer can be constructed + * using the Biquad cascade functions. + * A graphic equalizer is used in audio applications to vary the tonal quality + * of the audio. + * + * \par Block Diagram: + * \par + * The design is based on a cascade of 5 filter sections. + * \image html GEQ_signalflow.gif + * Each filter section is 4th order and consists of a cascade of two Biquads. + * Each filter has a nominal gain of 0 dB (1.0 in linear units) and + * boosts or cuts signals within a specific frequency range. + * The edge frequencies between the 5 bands are 100, 500, 2000, and 6000 Hz. + * Each band has an adjustable boost or cut in the range of +/- 9 dB. + * For example, the band that extends from 500 to 2000 Hz has the response shown below: + * \par + * \image html GEQ_bandresponse.gif + * \par + * With 1 dB steps, each filter has a total of 19 different settings. + * The filter coefficients for all possible 19 settings were precomputed + * in MATLAB and stored in a table. With 5 different tables, there are + * a total of 5 x 19 = 95 different 4th order filters. + * All 95 responses are shown below: + * \par + * \image html GEQ_allbandresponse.gif + * \par + * Each 4th order filter has 10 coefficents for a grand total of 950 different filter + * coefficients that must be tabulated. The input and output data is in Q31 format. + * For better noise performance, the two low frequency bands are implemented using the high + * precision 32x64-bit Biquad filters. The remaining 3 high frequency bands use standard + * 32x32-bit Biquad filters. The input signal used in the example is a logarithmic chirp. + * \par + * \image html GEQ_inputchirp.gif + * \par + * The array bandGains specifies the gain in dB to apply in each band. + * For example, if bandGains={0, -3, 6, 4, -6}; then the output signal will be: + * \par + * \image html GEQ_outputchirp.gif + * \par + * \note The output chirp signal follows the gain or boost of each band. + * \par + * + * \par Variables Description: + * \par + * \li \c testInput_f32 points to the input data + * \li \c testRefOutput_f32 points to the reference output data + * \li \c testOutput points to the test output data + * \li \c inputQ31 temporary input buffer + * \li \c outputQ31 temporary output buffer + * \li \c biquadStateBand1Q31 points to state buffer for band1 + * \li \c biquadStateBand2Q31 points to state buffer for band2 + * \li \c biquadStateBand3Q31 points to state buffer for band3 + * \li \c biquadStateBand4Q31 points to state buffer for band4 + * \li \c biquadStateBand5Q31 points to state buffer for band5 + * \li \c coeffTable points to coefficient buffer for all bands + * \li \c gainDB gain buffer which has gains applied for all the bands + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_biquad_cas_df1_32x64_init_q31() + * - arm_biquad_cas_df1_32x64_q31() + * - arm_biquad_cascade_df1_init_q31() + * - arm_biquad_cascade_df1_q31() + * - arm_scale_q31() + * - arm_scale_f32() + * - arm_float_to_q31() + * - arm_q31_to_float() + * + * Refer + * \link arm_graphic_equalizer_example_q31.c \endlink + * + */ + + +/** \example arm_graphic_equalizer_example_q31.c + */ + + +#include "arm_math.h" +#include "math_helper.h" + +/* Length of the overall data in the test */ +#define TESTLENGTH 320 + +/* Block size for the underlying processing */ +#define BLOCKSIZE 32 + +/* Total number of blocks to run */ +#define NUMBLOCKS (TESTLENGTH/BLOCKSIZE) + +/* Number of 2nd order Biquad stages per filter */ +#define NUMSTAGES 2 + +#define SNR_THRESHOLD_F32 98 + +/* ------------------------------------------------------------------- + * External Declarations for Input and Output buffers + * ------------------------------------------------------------------- */ + +extern float32_t testInput_f32[TESTLENGTH]; +static float32_t testOutput[TESTLENGTH]; + +extern float32_t testRefOutput_f32[TESTLENGTH]; + +/* ---------------------------------------------------------------------- +** Q31 state buffers for Band1, Band2, Band3, Band4, Band5 +** ------------------------------------------------------------------- */ + +static q63_t biquadStateBand1Q31[4 * 2]; +static q63_t biquadStateBand2Q31[4 * 2]; +static q31_t biquadStateBand3Q31[4 * 2]; +static q31_t biquadStateBand4Q31[4 * 2]; +static q31_t biquadStateBand5Q31[4 * 2]; + +/* ---------------------------------------------------------------------- +** Q31 input and output buffers +** ------------------------------------------------------------------- */ + +q31_t inputQ31[BLOCKSIZE]; +q31_t outputQ31[BLOCKSIZE]; + +/* ---------------------------------------------------------------------- +** Entire coefficient table. There are 10 coefficients per 4th order Biquad +** cascade filter. The first 10 coefficients correspond to the -9 dB gain +** setting of band 1; the next 10 coefficient correspond to the -8 dB gain +** setting of band 1; and so on. There are 10*19=190 coefficients in total +** for band 1 (gains = -9, -8, -7, ..., 9). After this come the 190 coefficients +** for band 2. +** +** The coefficients are in Q29 format and require a postShift of 2. +** ------------------------------------------------------------------- */ + +const q31_t coeffTable[950] = { + + /* Band 1, -9 dB gain */ + 535576962, -1071153923, 535576962, 1073741824, -536870912, 535576962, -1063501998, 527979313, 1060865294, -524146981, + /* Band 1, -8 dB gain */ + 535723226, -1071446451, 535723226, 1073741824, -536870912, 535723226, -1063568947, 527903217, 1061230578, -524503778, + 535868593, -1071737186, 535868593, 1073741824, -536870912, 535868593, -1063627467, 527819780, 1061585502, -524850686, + 536013181, -1072026363, 536013181, 1073741824, -536870912, 536013181, -1063677598, 527728935, 1061930361, -525187972, + 536157109, -1072314217, 536157109, 1073741824, -536870912, 536157109, -1063719372, 527630607, 1062265438, -525515897, + 536300492, -1072600983, 536300492, 1073741824, -536870912, 536300492, -1063752815, 527524720, 1062591011, -525834716, + 536443447, -1072886894, 536443447, 1073741824, -536870912, 536443447, -1063777945, 527411186, 1062907350, -526144676, + 536586091, -1073172183, 536586091, 1073741824, -536870912, 536586091, -1063794775, 527289917, 1063214717, -526446017, + 536728541, -1073457082, 536728541, 1073741824, -536870912, 536728541, -1063803308, 527160815, 1063513366, -526738975, + 536870912, -1073741824, 536870912, 1073741824, -536870912, 536870912, -1063803543, 527023777, 1063803543, -527023777, + 537013321, -1074026642, 537013321, 1073741824, -536870912, 537013321, -1063795470, 526878696, 1064085490, -527300648, + 537155884, -1074311768, 537155884, 1073741824, -536870912, 537155884, -1063779073, 526725455, 1064359439, -527569803, + 537298718, -1074597435, 537298718, 1073741824, -536870912, 537298718, -1063754328, 526563934, 1064625617, -527831454, + 537441939, -1074883878, 537441939, 1073741824, -536870912, 537441939, -1063721205, 526394005, 1064884245, -528085806, + 537585666, -1075171331, 537585666, 1073741824, -536870912, 537585666, -1063679666, 526215534, 1065135536, -528333059, + 537730015, -1075460030, 537730015, 1073741824, -536870912, 537730015, -1063629666, 526028380, 1065379699, -528573409, + 537875106, -1075750212, 537875106, 1073741824, -536870912, 537875106, -1063571152, 525832396, 1065616936, -528807045, + 538021057, -1076042114, 538021057, 1073741824, -536870912, 538021057, -1063504065, 525627429, 1065847444, -529034151, + 538167989, -1076335977, 538167989, 1073741824, -536870912, 538167989, -1063428338, 525413317, 1066071412, -529254907, + + /* Band 2, -9 dB gain */ + 531784976, -1055497692, 523873415, 1066213307, -529420241, 531784976, -1040357886, 509828014, 1028908252, -494627367, + /* Band 2, -8 dB gain */ + 532357636, -1056601982, 524400080, 1066115844, -529326645, 532357636, -1040623406, 509562600, 1030462237, -496062122, + 532927392, -1057707729, 524931110, 1066024274, -529239070, 532927392, -1040848253, 509262081, 1031969246, -497457090, + 533494678, -1058816094, 525467240, 1065939047, -529157961, 533494678, -1041032161, 508925950, 1033429976, -498812573, + 534059929, -1059928204, 526009170, 1065860582, -529083734, 534059929, -1041174868, 508553717, 1034845124, -500128887, + 534623580, -1061045148, 526557561, 1065789260, -529016764, 534623580, -1041276126, 508144920, 1036215393, -501406373, + 535186068, -1062167969, 527113032, 1065725420, -528957385, 535186068, -1041335703, 507699125, 1037541500, -502645399, + 535747827, -1063297666, 527676151, 1065669351, -528905879, 535747827, -1041353386, 507215934, 1038824183, -503846368, + 536309295, -1064435183, 528247436, 1065621289, -528862476, 536309295, -1041328990, 506694984, 1040064203, -505009724, + 536870912, -1065581413, 528827349, 1065581413, -528827349, 536870912, -1041262354, 506135953, 1041262354, -506135953, + 537433117, -1066737194, 529416295, 1065549847, -528800610, 537433117, -1041153346, 505538564, 1042419457, -507225588, + 537996352, -1067903307, 530014622, 1065526651, -528782316, 537996352, -1041001864, 504902578, 1043536370, -508279208, + 538561061, -1069080480, 530622620, 1065511830, -528772462, 538561061, -1040807833, 504227800, 1044613981, -509297437, + 539127690, -1070269387, 531240527, 1065505333, -528770987, 539127690, -1040571205, 503514074, 1045653211, -510280946, + 539696690, -1071470656, 531868525, 1065507054, -528777778, 539696690, -1040291951, 502761277, 1046655011, -511230450, + 540268512, -1072684867, 532506750, 1065516837, -528792672, 540268512, -1039970063, 501969320, 1047620358, -512146700, + 540843613, -1073912567, 533155297, 1065534483, -528815459, 540843613, -1039605542, 501138139, 1048550251, -513030484, + 541422451, -1075154268, 533814224, 1065559750, -528845892, 541422451, -1039198394, 500267687, 1049445708, -513882621, + 542005489, -1076410460, 534483561, 1065592362, -528883686, 542005489, -1038748624, 499357932, 1050307760, -514703956, + 518903861, -1001986830, 486725277, 1037235801, -502367695, 518903861, -945834422, 446371043, 902366163, -400700571, + 520899989, -1005630916, 488289126, 1036926846, -502147311, 520899989, -946490935, 445581846, 907921945, -404936158, + 522893209, -1009290002, 489869792, 1036650484, -501961419, 522893209, -947006359, 444685310, 913306106, -409075225, + 524884763, -1012968199, 491470256, 1036407567, -501810737, 524884763, -947377809, 443679533, 918521018, -413116221, + 526875910, -1016669649, 493093518, 1036198712, -501695739, 526875910, -947602324, 442562672, 923569247, -417057897, + 528867927, -1020398503, 494742575, 1036024293, -501616651, 528867927, -947676875, 441332970, 928453558, -420899319, + 530862111, -1024158905, 496420407, 1035884447, -501573457, 530862111, -947598385, 439988777, 933176909, -424639872, + 532859778, -1027954970, 498129955, 1035779077, -501565907, 532859778, -947363742, 438528571, 937742446, -428279254, + 534862260, -1031790763, 499874098, 1035707863, -501593525, 534862260, -946969823, 436950987, 942153486, -431817474, + 536870912, -1035670279, 501655630, 1035670279, -501655630, 536870912, -946413508, 435254839, 946413508, -435254839, + 538887107, -1039597419, 503477238, 1035665609, -501751354, 538887107, -945691703, 433439146, 950526127, -438591937, + 540912240, -1043575967, 505341475, 1035692963, -501879659, 540912240, -944801359, 431503152, 954495080, -441829621, + 542947726, -1047609569, 507250741, 1035751307, -502039364, 542947726, -943739490, 429446349, 958324201, -444968987, + 544995000, -1051701717, 509207261, 1035839473, -502229165, 544995000, -942503190, 427268492, 962017400, -448011351, + 547055523, -1055855728, 511213065, 1035956193, -502447657, 547055523, -941089647, 424969617, 965578640, -450958226, + 549130774, -1060074734, 513269973, 1036100110, -502693359, 549130774, -939496155, 422550049, 969011913, -453811298, + 551222259, -1064361672, 515379585, 1036269804, -502964731, 551222259, -937720119, 420010407, 972321228, -456572401, + 553331507, -1068719280, 517543273, 1036463810, -503260192, 553331507, -935759057, 417351601, 975510582, -459243495, + 555460072, -1073150100, 519762181, 1036680633, -503578144, 555460072, -933610600, 414574832, 978583948, -461826644, + 494084017, -851422604, 404056273, 930151631, -423619864, 494084017, -673714108, 339502486, 561843007, -265801750, + 498713542, -859177141, 406587077, 929211656, -423786402, 498713542, -673274906, 338185129, 573719128, -272222942, + 503369016, -867012190, 409148384, 928362985, -424054784, 503369016, -672533059, 336693984, 585290277, -278599028, + 508052536, -874935599, 411746438, 927604291, -424422151, 508052536, -671478538, 335026905, 596558312, -284920289, + 512766286, -882955583, 414387826, 926933782, -424885216, 512766286, -670100998, 333182045, 607525792, -291177811, + 517512534, -891080712, 417079474, 926349262, -425440318, 517512534, -668389789, 331157902, 618195914, -297363485, + 522293635, -899319903, 419828635, 925848177, -426083491, 522293635, -666333963, 328953368, 628572440, -303470012, + 527112032, -907682405, 422642886, 925427679, -426810526, 527112032, -663922286, 326567785, 638659631, -309490882, + 531970251, -916177781, 425530105, 925084675, -427617023, 531970251, -661143261, 324000998, 648462180, -315420352, + 536870912, -924815881, 428498454, 924815881, -428498454, 536870912, -657985147, 321253420, 657985147, -321253420, + 541816719, -933606817, 431556352, 924617870, -429450209, 541816719, -654435997, 318326093, 667233900, -326985786, + 546810467, -942560921, 434712438, 924487114, -430467639, 546810467, -650483688, 315220754, 676214053, -332613816, + 551855042, -951688708, 437975532, 924420027, -431546101, 551855042, -646115970, 311939896, 684931422, -338134495, + 556953421, -961000826, 441354588, 924413001, -432680993, 556953421, -641320513, 308486839, 693391970, -343545389, + 562108672, -970508005, 444858642, 924462435, -433867780, 562108672, -636084967, 304865786, 701601770, -348844597, + 567323959, -980220994, 448496743, 924564764, -435102022, 567323959, -630397020, 301081886, 709566963, -354030710, + 572602539, -990150500, 452277894, 924716482, -436379394, 572602539, -624244471, 297141281, 717293726, -359102767, + 577947763, -1000307125, 456210977, 924914158, -437695705, 577947763, -617615296, 293051155, 724788245, -364060214, + 583363084, -1010701292, 460304674, 925154455, -439046908, 583363084, -610497723, 288819761, 732056685, -368902865, + 387379495, -506912469, 196933274, 840112184, -347208270, 387379495, 506912469, 196933274, -840112184, -347208270, + 401658082, -532275898, 207149427, 833765363, -343175316, 401658082, 532275898, 207149427, -833765363, -343175316, + 416472483, -558722695, 217902617, 827270154, -339107319, 416472483, 558722695, 217902617, -827270154, -339107319, + 431841949, -586290861, 229212798, 820624988, -335007540, 431841949, 586290861, 229212798, -820624988, -335007540, + 447786335, -615019650, 241100489, 813828443, -330879528, 447786335, 615019650, 241100489, -813828443, -330879528, + 464326111, -644949597, 253586805, 806879270, -326727141, 464326111, 644949597, 253586805, -806879270, -326727141, + 481482377, -676122557, 266693475, 799776409, -322554559, 481482377, 676122557, 266693475, -799776409, -322554559, + 499276882, -708581728, 280442865, 792519013, -318366296, 499276882, 708581728, 280442865, -792519013, -318366296, + 517732032, -742371685, 294857996, 785106465, -314167221, 517732032, 742371685, 294857996, -785106465, -314167221, + 536870912, -777538408, 309962566, 777538408, -309962566, 536870912, 777538408, 309962566, -777538408, -309962566, + 556717294, -814129313, 325780968, 769814766, -305757943, 556717294, 814129313, 325780968, -769814766, -305757943, + 577295658, -852193284, 342338310, 761935777, -301559360, 577295658, 852193284, 342338310, -761935777, -301559360, + 598631206, -891780698, 359660433, 753902014, -297373230, 598631206, 891780698, 359660433, -753902014, -297373230, + 620749877, -932943463, 377773927, 745714425, -293206383, 620749877, 932943463, 377773927, -745714425, -293206383, + 643678365, -975735041, 396706151, 737374355, -289066077, 643678365, 975735041, 396706151, -737374355, -289066077, + 667444134, -1020210487, 416485252, 728883588, -284960004, 667444134, 1020210487, 416485252, -728883588, -284960004, + 692075438, -1066426476, 437140179, 720244375, -280896294, 692075438, 1066426476, 437140179, -720244375, -280896294, + 717601336, -1114441339, 458700704, 711459472, -276883515, 717601336, 1114441339, 458700704, -711459472, -276883515, + 744051710, -1164315096, 481197437, 702532174, -272930673, 744051710, 1164315096, 481197437, -702532174, -272930673 + +}; + +/* ---------------------------------------------------------------------- +** Desired gains, in dB, per band +** ------------------------------------------------------------------- */ + +int gainDB[5] = {0, -3, 6, 4, -6}; + +float32_t snr; + + +/* ---------------------------------------------------------------------- + * Graphic equalizer Example + * ------------------------------------------------------------------- */ + +int32_t main(void) +{ + float32_t *inputF32, *outputF32; + arm_biquad_cas_df1_32x64_ins_q31 S1; + arm_biquad_cas_df1_32x64_ins_q31 S2; + arm_biquad_casd_df1_inst_q31 S3; + arm_biquad_casd_df1_inst_q31 S4; + arm_biquad_casd_df1_inst_q31 S5; + int i; + int32_t status; + + inputF32 = &testInput_f32[0]; + outputF32 = &testOutput[0]; + + /* Initialize the state and coefficient buffers for all Biquad sections */ + + arm_biquad_cas_df1_32x64_init_q31(&S1, NUMSTAGES, + (q31_t *) &coeffTable[190*0 + 10*(gainDB[0] + 9)], + &biquadStateBand1Q31[0], 2); + + arm_biquad_cas_df1_32x64_init_q31(&S2, NUMSTAGES, + (q31_t *) &coeffTable[190*1 + 10*(gainDB[1] + 9)], + &biquadStateBand2Q31[0], 2); + + arm_biquad_cascade_df1_init_q31(&S3, NUMSTAGES, + (q31_t *) &coeffTable[190*2 + 10*(gainDB[2] + 9)], + &biquadStateBand3Q31[0], 2); + + arm_biquad_cascade_df1_init_q31(&S4, NUMSTAGES, + (q31_t *) &coeffTable[190*3 + 10*(gainDB[3] + 9)], + &biquadStateBand4Q31[0], 2); + + arm_biquad_cascade_df1_init_q31(&S5, NUMSTAGES, + (q31_t *) &coeffTable[190*4 + 10*(gainDB[4] + 9)], + &biquadStateBand5Q31[0], 2); + + + /* Call the process functions and needs to change filter coefficients + for varying the gain of each band */ + + for(i=0; i < NUMBLOCKS; i++) + { + + /* ---------------------------------------------------------------------- + ** Convert block of input data from float to Q31 + ** ------------------------------------------------------------------- */ + + arm_float_to_q31(inputF32 + (i*BLOCKSIZE), inputQ31, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Scale down by 1/8. This provides additional headroom so that the + ** graphic EQ can apply gain. + ** ------------------------------------------------------------------- */ + + arm_scale_q31(inputQ31, 0x7FFFFFFF, -3, inputQ31, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Call the Q31 Biquad Cascade DF1 32x64 process function for band1, band2 + ** ------------------------------------------------------------------- */ + + arm_biquad_cas_df1_32x64_q31(&S1, inputQ31, outputQ31, BLOCKSIZE); + arm_biquad_cas_df1_32x64_q31(&S2, outputQ31, outputQ31, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Call the Q31 Biquad Cascade DF1 process function for band3, band4, band5 + ** ------------------------------------------------------------------- */ + + arm_biquad_cascade_df1_q31(&S3, outputQ31, outputQ31, BLOCKSIZE); + arm_biquad_cascade_df1_q31(&S4, outputQ31, outputQ31, BLOCKSIZE); + arm_biquad_cascade_df1_q31(&S5, outputQ31, outputQ31, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Convert Q31 result back to float + ** ------------------------------------------------------------------- */ + + arm_q31_to_float(outputQ31, outputF32 + (i * BLOCKSIZE), BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Scale back up + ** ------------------------------------------------------------------- */ + + arm_scale_f32(outputF32 + (i * BLOCKSIZE), 8.0f, outputF32 + (i * BLOCKSIZE), BLOCKSIZE); + }; + + snr = arm_snr_f32(testRefOutput_f32, testOutput, TESTLENGTH); + + if (snr < SNR_THRESHOLD_F32) + { + status = ARM_MATH_TEST_FAILURE; + } + else + { + status = ARM_MATH_SUCCESS; + } + + /* ---------------------------------------------------------------------- + ** Loop here if the signal does not match the reference output. + ** ------------------------------------------------------------------- */ + + if( status != ARM_MATH_SUCCESS) + { + while(1); + } + + while(1); /* main function does not return */ +} + +/** \endlink */ + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/system_ARMCM0.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/system_ARMCM0.c new file mode 100644 index 000000000..ece74d2de --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/system_ARMCM0.c @@ -0,0 +1,76 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Cortex-M0 Device System Source File + * for CM0 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/system_ARMCM3.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/system_ARMCM3.c new file mode 100644 index 000000000..2f5fa0b93 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/system_ARMCM3.c @@ -0,0 +1,76 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Cortex-M3 Device System Source File + * for CM3 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/system_ARMCM4.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/system_ARMCM4.c new file mode 100644 index 000000000..beaaf6fb8 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Cortex-M4 Device System Source File + * for CM4 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM4.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ + #endif + + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM0l_linear_interp_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM0l_linear_interp_example.uvopt new file mode 100644 index 000000000..082f09ce2 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM0l_linear_interp_example.uvopt @@ -0,0 +1,318 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M0 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + + 4803 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM0l_linear_interp_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_linear_interp_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + ARM_MATH_CM0 + + ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_linear_interp_example_f32.c + 1 + ..\arm_linear_interp_example_f32.c + + + arm_linear_interp_data.c + 1 + ..\arm_linear_interp_data.c + + + math_helper.c + 1 + ..\..\Common\Source\math_helper.c + + + + + CMSIS Device + + + system_ARMCM0.c + 1 + ..\system_ARMCM0.c + + + startup_ARMCM0.s + 2 + .\startup_ARMCM0.s + + + + + CMSIS DSP_Library + + + arm_cortexM0l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib + + + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM3l_linear_interp_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM3l_linear_interp_example.uvopt new file mode 100644 index 000000000..f5c5cfccd --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM3l_linear_interp_example.uvopt @@ -0,0 +1,318 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM4lf_linear_interp_example\../arm_linear_interp_example_f32.c\178 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + ..\arm_linear_interp_example_f32.c + arm_linear_interp_example_f32.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\arm_linear_interp_data.c + arm_linear_interp_data.c + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Common\Source\math_helper.c + math_helper.c + + + + + CMSIS DeviceSupport + 1 + 0 + 0 + + 2 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\system_ARMCM4.c + system_ARMCM4.c + + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\startup_ARMCM4.s + startup_ARMCM4.s + + + + + CMSIS SW_DSP_Library + 1 + 0 + 0 + + 3 + 6 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + arm_cortexM4lf_math.lib + + + + + 1 + 0 + + 100 + 0 + + + ..\arm_linear_interp_example_f32.c + 0 + 1 + 1 + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM4lf_linear_interp_example.uvproj b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM4lf_linear_interp_example.uvproj new file mode 100644 index 000000000..24aef81b3 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM4lf_linear_interp_example.uvproj @@ -0,0 +1,435 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_linear_interp_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_linear_interp_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_linear_interp_example_f32.c + 1 + ..\arm_linear_interp_example_f32.c + + + arm_linear_interp_data.c + 1 + ..\arm_linear_interp_data.c + + + math_helper.c + 1 + ..\..\Common\Source\math_helper.c + + + + + CMSIS Device + + + system_ARMCM4.c + 1 + ..\system_ARMCM4.c + + + startup_ARMCM4.s + 2 + .\startup_ARMCM4.s + + + + + CMSIS DSP_Library + + + arm_cortexM4lf_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + + + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_linear_interp_example.ini b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_linear_interp_example.ini new file mode 100644 index 000000000..63e18b0b2 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_linear_interp_example.ini @@ -0,0 +1,14 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_linear_interp_example.ini + +*/ + + +// usual initialisation for target setup +MAP 0x20000000, 0x20008000 READ WRITE // allow R/W access to IO space + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/startup_ARMCM0.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/startup_ARMCM0.s new file mode 100644 index 000000000..0acd34611 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/startup_ARMCM0.s @@ -0,0 +1,144 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Cortex-M0 Core Device Startup File +; * for CM0 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/startup_ARMCM3.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/startup_ARMCM3.s new file mode 100644 index 000000000..5af584bdc --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/startup_ARMCM3.s @@ -0,0 +1,164 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Cortex-M3 Core Device Startup File +; * for CM3 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/startup_ARMCM4.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/startup_ARMCM4.s new file mode 100644 index 000000000..09fdbd6ed --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/startup_ARMCM4.s @@ -0,0 +1,164 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Cortex-M4 Core Device Startup File +; * for CM4 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/arm_linear_interp_data.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/arm_linear_interp_data.c new file mode 100644 index 000000000..464ce85c4 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/arm_linear_interp_data.c @@ -0,0 +1,23576 @@ + +/* ---------------------------------------------------------------------- +* Table generated from following MATLAB Command +* x = -pi: 0.00005 : (2*pi - 0.00005); +* y = sin(x); +* where pi value is 3.141592653589793 +* --------------------------------------------------------------------*/ + +const float arm_linear_interep_table[188495] = { + + +-0.000000000000000122, -0.000049999999979173, -0.000099999999833667, -0.000149999999437717, -0.000199999998666767, -0.000249999997395817, -0.000299999995500311, -0.000349999992854362, +-0.000399999989333412, -0.000449999984812462, -0.000499999979166956, -0.000549999972271007, -0.000599999964000057, -0.000649999954229107, -0.000699999942833602, -0.000749999929687653, +-0.000799999914666704, -0.000849999897645755, -0.000899999878500250, -0.000949999857104302, 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-0.000477960751181838, -0.000427960756316500, +-0.000377960760381259, -0.000327960763501117, -0.000277960765801072, -0.000227960767405237, -0.000177960768440389, -0.000127960769030639, -0.000077960769300987 +}; + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/arm_linear_interp_example_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/arm_linear_interp_example_f32.c new file mode 100644 index 000000000..56f469d15 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/arm_linear_interp_example_f32.c @@ -0,0 +1,182 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 29. November 2010 +* $Revision: V1.0.3 +* +* Project: CMSIS DSP Library +* Title: arm_linear_interp_example_f32.c +* +* Description: Example code demonstrating usage of sin function +* and uses linear interpolation to get higher precision +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.1 2010/10/05 KK +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 KK +* Production release and review comments incorporated. +* ------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup LinearInterpExample Linear Interpolate Example + * + * CMSIS DSP Software Library -- Linear Interpolate Example + * + * Description + * This example demonstrates usage of linear interpolate modules and fast math modules. + * Method 1 uses fast math sine function to calculate sine values using cubic interpolation and method 2 uses + * linear interpolation function and results are compared to reference output. + * Example shows linear interpolation function can be used to get higher precision compared to fast math sin calculation. + * + * \par Block Diagram: + * \par + * \image html linearInterpExampleMethod1.gif "Method 1: Sine caluclation using fast math" + * \par + * \image html linearInterpExampleMethod2.gif "Method 2: Sine caluclation using interpolation function" + * + * \par Variables Description: + * \par + * \li \c testInputSin_f32 points to the input values for sine calculation + * \li \c testRefSinOutput32_f32 points to the reference values caculated from sin() matlab function + * \li \c testOutput points to output buffer calculation from cubic interpolation + * \li \c testLinIntOutput points to output buffer calculation from linear interpolation + * \li \c snr1 Signal to noise ratio for reference and cubic interpolation output + * \li \c snr2 Signal to noise ratio for reference and linear interpolation output + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_sin_f32() + * - arm_linear_interp_f32() + * + * Refer + * \link arm_linear_interp_example_f32.c \endlink + * + */ + + +/** \example arm_linear_interp_example_f32.c + */ + +#include "arm_math.h" +#include "math_helper.h" + +#define SNR_THRESHOLD 90 +#define TEST_LENGTH_SAMPLES 10 +#define XSPACING (0.00005f) + +/* ---------------------------------------------------------------------- +* Test input data for F32 SIN function +* Generated by the MATLAB rand() function +* randn('state', 0) +* xi = (((1/4.18318581819710)* randn(blockSize, 1) * 2* pi)); +* --------------------------------------------------------------------*/ +float32_t testInputSin_f32[TEST_LENGTH_SAMPLES] = +{ + -0.649716504673081170, -2.501723745497831200, 0.188250329003310100, 0.432092748487532540, -1.722010988459680800, 1.788766476323060600, 1.786136060975809500, -0.056525543169408797, + 0.491596272728153760, 0.262309671126153390 +}; + +/*------------------------------------------------------------------------------ +* Reference out of SIN F32 function for Block Size = 10 +* Calculated from sin(testInputSin_f32) +*------------------------------------------------------------------------------*/ +float32_t testRefSinOutput32_f32[TEST_LENGTH_SAMPLES] = +{ + -0.604960695383043530, -0.597090287967934840, 0.187140422442966500, 0.418772124875992690, -0.988588831792106880, 0.976338412038794010, 0.976903856413481100, -0.056495446835214236, + 0.472033731854734240, 0.259311907228582830 +}; + +/*------------------------------------------------------------------------------ +* Method 1: Test out Buffer Calculated from Cubic Interpolation +*------------------------------------------------------------------------------*/ +float32_t testOutput[TEST_LENGTH_SAMPLES]; + +/*------------------------------------------------------------------------------ +* Method 2: Test out buffer Calculated from Linear Interpolation +*------------------------------------------------------------------------------*/ +float32_t testLinIntOutput[TEST_LENGTH_SAMPLES]; + +/*------------------------------------------------------------------------------ +* External table used for linear interpolation +*------------------------------------------------------------------------------*/ +extern float32_t arm_linear_interep_table[188495]; + +/* ---------------------------------------------------------------------- +* Global Variables for caluclating SNR's for Method1 & Method 2 +* ------------------------------------------------------------------- */ +float32_t snr1; +float32_t snr2; + +/* ---------------------------------------------------------------------------- +* Calculation of Sine values from Cubic Interpolation and Linear interpolation +* ---------------------------------------------------------------------------- */ +int32_t main(void) +{ + uint32_t i; + arm_status status; + + arm_linear_interp_instance_f32 S = {188495, -3.141592653589793238, XSPACING, &arm_linear_interep_table[0]}; + + /*------------------------------------------------------------------------------ + * Method 1: Test out Calculated from Cubic Interpolation + *------------------------------------------------------------------------------*/ + for(i=0; i< TEST_LENGTH_SAMPLES; i++) + { + testOutput[i] = arm_sin_f32(testInputSin_f32[i]); + } + + /*------------------------------------------------------------------------------ + * Method 2: Test out Calculated from Cubic Interpolation and Linear interpolation + *------------------------------------------------------------------------------*/ + + for(i=0; i< TEST_LENGTH_SAMPLES; i++) + { + testLinIntOutput[i] = arm_linear_interp_f32(&S, testInputSin_f32[i]); + } + + /*------------------------------------------------------------------------------ + * SNR calculation for method 1 + *------------------------------------------------------------------------------*/ + snr1 = arm_snr_f32(testRefSinOutput32_f32, testOutput, 2); + + /*------------------------------------------------------------------------------ + * SNR calculation for method 2 + *------------------------------------------------------------------------------*/ + snr2 = arm_snr_f32(testRefSinOutput32_f32, testLinIntOutput, 2); + + /*------------------------------------------------------------------------------ + * Initialise status depending on SNR calculations + *------------------------------------------------------------------------------*/ + if( snr2 > snr1) + { + status = ARM_MATH_SUCCESS; + } + else + { + status = ARM_MATH_TEST_FAILURE; + } + + /* ---------------------------------------------------------------------- + ** Loop here if the signals fail the PASS check. + ** This denotes a test failure + ** ------------------------------------------------------------------- */ + if( status != ARM_MATH_SUCCESS) + { + while(1); + } + + while(1); /* main function does not return */ +} + + /** \endlink */ + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/system_ARMCM0.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/system_ARMCM0.c new file mode 100644 index 000000000..ece74d2de --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/system_ARMCM0.c @@ -0,0 +1,76 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Cortex-M0 Device System Source File + * for CM0 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/system_ARMCM3.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/system_ARMCM3.c new file mode 100644 index 000000000..2f5fa0b93 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/system_ARMCM3.c @@ -0,0 +1,76 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Cortex-M3 Device System Source File + * for CM3 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/system_ARMCM4.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/system_ARMCM4.c new file mode 100644 index 000000000..beaaf6fb8 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Cortex-M4 Device System Source File + * for CM4 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM4.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ + #endif + + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_cortexM0l_matrix_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_cortexM0l_matrix_example.uvopt new file mode 100644 index 000000000..527f80e53 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_cortexM0l_matrix_example.uvopt @@ -0,0 +1,304 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_matrix_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_matrix_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_matrix_example_f32.c + 1 + ..\arm_matrix_example_f32.c + + + math_helper.c + 1 + ..\..\Common\Source\math_helper.c + + + + + CMSIS Device + + + system_ARMCM4.c + 1 + ..\system_ARMCM4.c + + + startup_ARMCM4.s + 2 + .\startup_ARMCM4.s + + + + + CMSIS DSP_Library + + + arm_cortexM4lf_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + + + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_matrix_example.ini b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_matrix_example.ini new file mode 100644 index 000000000..6d6cba436 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_matrix_example.ini @@ -0,0 +1,14 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_matrix_example.ini + +*/ + + +// usual initialisation for target setup +MAP 0x20000000, 0x20008000 READ WRITE // allow R/W access to IO space + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/startup_ARMCM0.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/startup_ARMCM0.s new file mode 100644 index 000000000..0acd34611 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/startup_ARMCM0.s @@ -0,0 +1,144 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Cortex-M0 Core Device Startup File +; * for CM0 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/startup_ARMCM3.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/startup_ARMCM3.s new file mode 100644 index 000000000..5af584bdc --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/startup_ARMCM3.s @@ -0,0 +1,164 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Cortex-M3 Core Device Startup File +; * for CM3 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/startup_ARMCM4.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/startup_ARMCM4.s new file mode 100644 index 000000000..09fdbd6ed --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/startup_ARMCM4.s @@ -0,0 +1,164 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Cortex-M4 Core Device Startup File +; * for CM4 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/arm_matrix_example_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/arm_matrix_example_f32.c new file mode 100644 index 000000000..1fa348b3a --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/arm_matrix_example_f32.c @@ -0,0 +1,218 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 29. November 2010 +* $Revision: V1.0.3 +* +* Project: CMSIS DSP Library +* Title: arm_matrix_example_f32.c +* +* Description: Example code demonstrating least square fit to data +* using matrix functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.1 2010/10/05 KK +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 KK +* Production release and review comments incorporated. +* ------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup MatrixExample Matrix Example + * + * \par Description: + * \par + * Demonstrates the use of Matrix Transpose, Matrix Muliplication, and Matrix Inverse + * functions to apply least squares fitting to input data. Least squares fitting is + * the procedure for finding the best-fitting curve that minimizes the sum of the + * squares of the offsets (least square error) from a given set of data. + * + * \par Algorithm: + * \par + * The linear combination of parameters considered is as follows: + * \par + * A * X = B, where \c X is the unknown value and can be estimated + * from \c A & \c B. + * \par + * The least squares estimate \c X is given by the following equation: + * \par + * X = Inverse(AT * A) * AT * B + * + * \par Block Diagram: + * \par + * \image html matrixExample.gif + * + * \par Variables Description: + * \par + * \li \c A_f32 input matrix in the linear combination equation + * \li \c B_f32 output matrix in the linear combination equation + * \li \c X_f32 unknown matrix estimated using \c A_f32 & \c B_f32 matrices + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_mat_init_f32() + * - arm_mat_trans_f32() + * - arm_mat_mult_f32() + * - arm_mat_inverse_f32() + * + * Refer + * \link arm_matrix_example_f32.c \endlink + * + */ + + +/** \example arm_matrix_example_f32.c + */ + +#include "arm_math.h" +#include "math_helper.h" + +#define SNR_THRESHOLD 90 + +/* -------------------------------------------------------------------------------- +* Test input data(Cycles) taken from FIR Q15 module for differant cases of blockSize +* and tapSize +* --------------------------------------------------------------------------------- */ + +const float32_t B_f32[4] = +{ + 782.0, 7577.0, 470.0, 4505.0 +}; + +/* -------------------------------------------------------------------------------- +* Formula to fit is C1 + C2 * numTaps + C3 * blockSize + C4 * numTaps * blockSize +* -------------------------------------------------------------------------------- */ + +const float32_t A_f32[16] = +{ + /* Const, numTaps, blockSize, numTaps*blockSize */ + 1.0, 32.0, 4.0, 128.0, + 1.0, 32.0, 64.0, 2048.0, + 1.0, 16.0, 4.0, 64.0, + 1.0, 16.0, 64.0, 1024.0, +}; + + +/* ---------------------------------------------------------------------- +* Temporary buffers for storing intermediate values +* ------------------------------------------------------------------- */ +/* Transpose of A Buffer */ +float32_t AT_f32[16]; +/* (Transpose of A * A) Buffer */ +float32_t ATMA_f32[16]; +/* Inverse(Transpose of A * A) Buffer */ +float32_t ATMAI_f32[16]; +/* Test Output Buffer */ +float32_t X_f32[4]; + +/* ---------------------------------------------------------------------- +* Reference ouput buffer C1, C2, C3 and C4 taken from MATLAB +* ------------------------------------------------------------------- */ +const float32_t xRef_f32[4] = {73.0, 8.0, 21.25, 2.875}; + +float32_t snr; + + +/* ---------------------------------------------------------------------- +* Max magnitude FFT Bin test +* ------------------------------------------------------------------- */ + +int32_t main(void) +{ + + arm_matrix_instance_f32 A; /* Matrix A Instance */ + arm_matrix_instance_f32 AT; /* Matrix AT(A transpose) instance */ + arm_matrix_instance_f32 ATMA; /* Matrix ATMA( AT multiply with A) instance */ + arm_matrix_instance_f32 ATMAI; /* Matrix ATMAI(Inverse of ATMA) instance */ + arm_matrix_instance_f32 B; /* Matrix B instance */ + arm_matrix_instance_f32 X; /* Matrix X(Unknown Matrix) instance */ + + uint32_t srcRows, srcColumns; /* Temporary variables */ + arm_status status; + + /* Initialise A Matrix Instance with numRows, numCols and data array(A_f32) */ + srcRows = 4; + srcColumns = 4; + arm_mat_init_f32(&A, srcRows, srcColumns, (float32_t *)A_f32); + + /* Initialise Matrix Instance AT with numRows, numCols and data array(AT_f32) */ + srcRows = 4; + srcColumns = 4; + arm_mat_init_f32(&AT, srcRows, srcColumns, AT_f32); + + /* calculation of A transpose */ + status = arm_mat_trans_f32(&A, &AT); + + + /* Initialise ATMA Matrix Instance with numRows, numCols and data array(ATMA_f32) */ + srcRows = 4; + srcColumns = 4; + arm_mat_init_f32(&ATMA, srcRows, srcColumns, ATMA_f32); + + /* calculation of AT Multiply with A */ + status = arm_mat_mult_f32(&AT, &A, &ATMA); + + /* Initialise ATMAI Matrix Instance with numRows, numCols and data array(ATMAI_f32) */ + srcRows = 4; + srcColumns = 4; + arm_mat_init_f32(&ATMAI, srcRows, srcColumns, ATMAI_f32); + + /* calculation of Inverse((Transpose(A) * A) */ + status = arm_mat_inverse_f32(&ATMA, &ATMAI); + + /* calculation of (Inverse((Transpose(A) * A)) * Transpose(A)) */ + status = arm_mat_mult_f32(&ATMAI, &AT, &ATMA); + + /* Initialise B Matrix Instance with numRows, numCols and data array(B_f32) */ + srcRows = 4; + srcColumns = 1; + arm_mat_init_f32(&B, srcRows, srcColumns, (float32_t *)B_f32); + + /* Initialise X Matrix Instance with numRows, numCols and data array(X_f32) */ + srcRows = 4; + srcColumns = 1; + arm_mat_init_f32(&X, srcRows, srcColumns, X_f32); + + /* calculation ((Inverse((Transpose(A) * A)) * Transpose(A)) * B) */ + status = arm_mat_mult_f32(&ATMA, &B, &X); + + /* Comparison of reference with test output */ + snr = arm_snr_f32((float32_t *)xRef_f32, X_f32, 4); + + /*------------------------------------------------------------------------------ + * Initialise status depending on SNR calculations + *------------------------------------------------------------------------------*/ + if( snr > SNR_THRESHOLD) + { + status = ARM_MATH_SUCCESS; + } + else + { + status = ARM_MATH_TEST_FAILURE; + } + + + /* ---------------------------------------------------------------------- + ** Loop here if the signals fail the PASS check. + ** This denotes a test failure + ** ------------------------------------------------------------------- */ + if( status != ARM_MATH_SUCCESS) + { + while(1); + } + + while(1); /* main function does not return */ +} + + /** \endlink */ + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/system_ARMCM0.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/system_ARMCM0.c new file mode 100644 index 000000000..ece74d2de --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/system_ARMCM0.c @@ -0,0 +1,76 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Cortex-M0 Device System Source File + * for CM0 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/system_ARMCM3.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/system_ARMCM3.c new file mode 100644 index 000000000..2f5fa0b93 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/system_ARMCM3.c @@ -0,0 +1,76 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Cortex-M3 Device System Source File + * for CM3 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/system_ARMCM4.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/system_ARMCM4.c new file mode 100644 index 000000000..beaaf6fb8 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_matrix_example/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Cortex-M4 Device System Source File + * for CM4 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM4.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ + #endif + + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM0l_signal_converge_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM0l_signal_converge_example.uvopt new file mode 100644 index 000000000..bee0dbd68 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM0l_signal_converge_example.uvopt @@ -0,0 +1,318 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM4lf_signal_converge_example\../arm_signal_converge_example_f32.c\240 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\arm_signal_converge_data.c + arm_signal_converge_data.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + ..\arm_signal_converge_example_f32.c + arm_signal_converge_example_f32.c + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Common\Source\math_helper.c + math_helper.c + + + + + CMSIS DeviceSupport + 1 + 0 + 0 + + 2 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\system_ARMCM4.c + system_ARMCM4.c + + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\startup_ARMCM4.s + startup_ARMCM4.s + + + + + CMSIS SW_DSP_Library + 1 + 0 + 0 + + 3 + 6 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + arm_cortexM4lf_math.lib + + + + + 1 + 0 + + 100 + 0 + + + ..\arm_signal_converge_example_f32.c + 0 + 1 + 1 + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM4lf_signal_converge_example.uvproj b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM4lf_signal_converge_example.uvproj new file mode 100644 index 000000000..103c61c01 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM4lf_signal_converge_example.uvproj @@ -0,0 +1,435 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_signal_converge_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_signal_converge_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_signal_converge_data.c + 1 + ..\arm_signal_converge_data.c + + + arm_signal_converge_example_f32.c + 1 + ..\arm_signal_converge_example_f32.c + + + math_helper.c + 1 + ..\..\Common\Source\math_helper.c + + + + + CMSIS Device + + + system_ARMCM4.c + 1 + ..\system_ARMCM4.c + + + startup_ARMCM4.s + 2 + .\startup_ARMCM4.s + + + + + CMSIS DSP_Library + + + arm_cortexM4lf_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + + + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_signal_converge_example.ini b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_signal_converge_example.ini new file mode 100644 index 000000000..d48a8f2d6 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_signal_converge_example.ini @@ -0,0 +1,14 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_signal_converge_example.ini + +*/ + + +// usual initialisation for target setup +MAP 0x20000000, 0x20008000 READ WRITE // allow R/W access to IO space + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/startup_ARMCM0.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/startup_ARMCM0.s new file mode 100644 index 000000000..0acd34611 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/startup_ARMCM0.s @@ -0,0 +1,144 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Cortex-M0 Core Device Startup File +; * for CM0 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/startup_ARMCM3.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/startup_ARMCM3.s new file mode 100644 index 000000000..5af584bdc --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/startup_ARMCM3.s @@ -0,0 +1,164 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Cortex-M3 Core Device Startup File +; * for CM3 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/startup_ARMCM4.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/startup_ARMCM4.s new file mode 100644 index 000000000..09fdbd6ed --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/startup_ARMCM4.s @@ -0,0 +1,164 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Cortex-M4 Core Device Startup File +; * for CM4 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/arm_signal_converge_data.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/arm_signal_converge_data.c new file mode 100644 index 000000000..be64907a7 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/arm_signal_converge_data.c @@ -0,0 +1,229 @@ +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +** Test input data for Floating point LMS Norm FIR filter +** Generated by the MATLAB randn() function +** ------------------------------------------------------------------- */ + +float32_t testInput_f32[1536] = +{ +-0.432565, -1.665584, 0.125332, 0.287676, -1.146471, 1.190915, 1.189164, -0.037633, +0.327292, 0.174639, -0.186709, 0.725791, -0.588317, 2.183186, -0.136396, 0.113931, +1.066768, 0.059281, -0.095648, -0.832349, 0.294411, -1.336182, 0.714325, 1.623562, +-0.691776, 0.857997, 1.254001, -1.593730, -1.440964, 0.571148, -0.399886, 0.689997, +0.815622, 0.711908, 1.290250, 0.668601, 1.190838, -1.202457, -0.019790, -0.156717, +-1.604086, 0.257304, -1.056473, 1.415141, -0.805090, 0.528743, 0.219321, -0.921902, +-2.170674, -0.059188, -1.010634, 0.614463, 0.507741, 1.692430, 0.591283, -0.643595, +0.380337, -1.009116, -0.019511, -0.048221, 0.000043, -0.317859, 1.095004, -1.873990, +0.428183, 0.895638, 0.730957, 0.577857, 0.040314, 0.677089, 0.568900, -0.255645, +-0.377469, -0.295887, -1.475135, -0.234004, 0.118445, 0.314809, 1.443508, -0.350975, +0.623234, 0.799049, 0.940890, -0.992092, 0.212035, 0.237882, -1.007763, -0.742045, +1.082295, -0.131500, 0.389880, 0.087987, -0.635465, -0.559573, 0.443653, -0.949904, +0.781182, 0.568961, -0.821714, -0.265607, -1.187777, -2.202321, 0.986337, -0.518635, +0.327368, 0.234057, 0.021466, -1.003944, -0.947146, -0.374429, -1.185886, -1.055903, +1.472480, 0.055744, -1.217317, -0.041227, -1.128344, -1.349278, -0.261102, 0.953465, +0.128644, 0.656468, -1.167819, -0.460605, -0.262440, -1.213152, -1.319437, 0.931218, +0.011245, -0.645146, 0.805729, 0.231626, -0.989760, 1.339586, 0.289502, 1.478917, +1.138028, -0.684139, -1.291936, -0.072926, -0.330599, -0.843628, 0.497770, 1.488490, +-0.546476, -0.846758, -0.246337, 0.663024, -0.854197, -1.201315, -0.119869, -0.065294, +0.485296, -0.595491, -0.149668, -0.434752, -0.079330, 1.535152, -0.606483, -1.347363, +0.469383, -0.903567, 0.035880, -0.627531, 0.535398, 0.552884, -0.203690, -2.054325, +0.132561, 1.592941, 1.018412, -1.580402, -0.078662, -0.681657, -1.024553, -1.234353, +0.288807, -0.429303, 0.055801, -0.367874, -0.464973, 0.370961, 0.728283, 2.112160, +-1.357298, -1.022610, 1.037834, -0.389800, -1.381266, 0.315543, 1.553243, 0.707894, +1.957385, 0.504542, 1.864529, -0.339812, -1.139779, -0.211123, 1.190245, -1.116209, +0.635274, -0.601412, 0.551185, -1.099840, 0.085991, -2.004563, -0.493088, 0.462048, +-0.321005, 1.236556, -0.631280, -2.325211, -1.231637, 1.055648, -0.113224, 0.379224, +0.944200, -2.120427, -0.644679, -0.704302, -1.018137, -0.182082, 1.521013, -0.038439, +1.227448, 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+ +/* ---------------------------------------------------------------------- +** Coefficients for 32-tap filter for Floating point LMS FIR filter +* FIR high pass filter with cutoff freq 9.6kHz (transition 9.6KHz to 11.52KHz) +** ------------------------------------------------------------------- */ +float32_t lmsNormCoeff_f32[32] = { +-0.004240, 0.002301, 0.008860, -0.000000, -0.019782, -0.010543, 0.032881, 0.034736, +-0.037374, -0.069586, 0.022397, 0.102169, 0.014185, -0.115908, -0.061648, 0.101018, +0.101018, -0.061648, -0.115908, 0.014185, 0.102169, 0.022397, -0.069586, -0.037374, +0.034736, 0.032881, -0.010543, -0.019782, -0.000000, 0.008860, 0.002301, -0.004240 + +}; + +/* ---------------------------------------------------------------------- +** Coefficients for 32-tap filter for Floating point FIR filter +* FIR low pass filter with cutoff freq 24Hz (transition 24Hz to 240Hz) +** ------------------------------------------------------------------- */ +const float32_t FIRCoeff_f32[32] = { +0.004502, 0.005074, 0.006707, 0.009356, 0.012933, 0.017303, 0.022298, 0.027717, +0.033338, 0.038930, 0.044258, 0.049098, 0.053243, 0.056519, 0.058784, 0.059941, +0.059941, 0.058784, 0.056519, 0.053243, 0.049098, 0.044258, 0.038930, 0.033338, +0.027717, 0.022298, 0.017303, 0.012933, 0.009356, 0.006707, 0.005074, 0.004502 + +}; + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/arm_signal_converge_example_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/arm_signal_converge_example_f32.c new file mode 100644 index 000000000..34d9c8626 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/arm_signal_converge_example_f32.c @@ -0,0 +1,246 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 29. November 2010 +* $Revision: V1.0.3 +* +* Project: CMSIS DSP Library +* Title: arm_signal_converge_example_f32.c +* +* Description: Example code demonstrating convergence of an adaptive +* filter. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.1 2010/10/05 KK +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 KK +* Production release and review comments incorporated. +* ------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup SignalConvergence Signal Convergence Example + * + * \par Description: + * \par + * Demonstrates the ability of an adaptive filter to "learn" the transfer function of + * a FIR lowpass filter using the Normalized LMS Filter, Finite Impulse + * Response (FIR) Filter, and Basic Math Functions. + * + * \par Algorithm: + * \par + * The figure below illustrates the signal flow in this example. Uniformly distributed white + * noise is passed through an FIR lowpass filter. The output of the FIR filter serves as the + * reference input of the adaptive filter (normalized LMS filter). The white noise is input + * to the adaptive filter. The adaptive filter learns the transfer function of the FIR filter. + * The filter outputs two signals: (1) the output of the internal adaptive FIR filter, and + * (2) the error signal which is the difference between the adaptive filter and the reference + * output of the FIR filter. Over time as the adaptive filter learns the transfer function + * of the FIR filter, the first output approaches the reference output of the FIR filter, + * and the error signal approaches zero. + * \par + * The adaptive filter converges properly even if the input signal has a large dynamic + * range (i.e., varies from small to large values). The coefficients of the adaptive filter + * are initially zero, and then converge over 1536 samples. The internal function test_signal_converge() + * implements the stopping condition. The function checks if all of the values of the error signal have a + * magnitude below a threshold DELTA. + * + * \par Block Diagram: + * \par + * \image html SignalFlow.gif + * + * + * \par Variables Description: + * \par + * \li \c testInput_f32 points to the input data + * \li \c firStateF32 points to FIR state buffer + * \li \c lmsStateF32 points to Normalised Least mean square FIR filter state buffer + * \li \c FIRCoeff_f32 points to coefficient buffer + * \li \c lmsNormCoeff_f32 points to Normalised Least mean square FIR filter coefficient buffer + * \li \c wire1, wir2, wire3 temporary buffers + * \li \c errOutput, err_signal temporary error buffers + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_lms_norm_init_f32() + * - arm_fir_init_f32() + * - arm_fir_f32() + * - arm_lms_norm_f32() + * - arm_scale_f32() + * - arm_abs_f32() + * - arm_sub_f32() + * - arm_min_f32() + * - arm_copy_f32() + * + * Refer + * \link arm_signal_converge_example_f32.c \endlink + * + */ + + +/** \example arm_signal_converge_example_f32.c + */ + +#include "arm_math.h" +#include "math_helper.h" + +/* ---------------------------------------------------------------------- +** Global defines for the simulation +* ------------------------------------------------------------------- */ + +#define TEST_LENGTH_SAMPLES 1536 +#define NUMTAPS 32 +#define BLOCKSIZE 32 +#define DELTA_ERROR 0.000001f +#define DELTA_COEFF 0.0001f +#define MU 0.5f + +#define NUMFRAMES (TEST_LENGTH_SAMPLES / BLOCKSIZE) + +/* ---------------------------------------------------------------------- +* Declare FIR state buffers and structure +* ------------------------------------------------------------------- */ + +float32_t firStateF32[NUMTAPS + BLOCKSIZE]; +arm_fir_instance_f32 LPF_instance; + +/* ---------------------------------------------------------------------- +* Declare LMSNorm state buffers and structure +* ------------------------------------------------------------------- */ + +float32_t lmsStateF32[NUMTAPS + BLOCKSIZE]; +float32_t errOutput[TEST_LENGTH_SAMPLES]; +arm_lms_norm_instance_f32 lmsNorm_instance; + + +/* ---------------------------------------------------------------------- +* Function Declarations for Signal Convergence Example +* ------------------------------------------------------------------- */ + +arm_status test_signal_converge_example( void ); + + +/* ---------------------------------------------------------------------- +* Internal functions +* ------------------------------------------------------------------- */ +arm_status test_signal_converge(float32_t* err_signal, + uint32_t blockSize); + +void getinput(float32_t* input, + uint32_t fr_cnt, + uint32_t blockSize); + +/* ---------------------------------------------------------------------- +* External Declarations for FIR F32 module Test +* ------------------------------------------------------------------- */ +extern float32_t testInput_f32[TEST_LENGTH_SAMPLES]; +extern float32_t lmsNormCoeff_f32[32]; +extern const float32_t FIRCoeff_f32[32]; +extern arm_lms_norm_instance_f32 lmsNorm_instance; + +/* ---------------------------------------------------------------------- +* Declare I/O buffers +* ------------------------------------------------------------------- */ + +float32_t wire1[BLOCKSIZE]; +float32_t wire2[BLOCKSIZE]; +float32_t wire3[BLOCKSIZE]; +float32_t err_signal[BLOCKSIZE]; + +/* ---------------------------------------------------------------------- +* Signal converge test +* ------------------------------------------------------------------- */ + +int32_t main(void) +{ + uint32_t i; + arm_status status; + uint32_t index; + float32_t minValue; + + /* Initialize the LMSNorm data structure */ + arm_lms_norm_init_f32(&lmsNorm_instance, NUMTAPS, lmsNormCoeff_f32, lmsStateF32, MU, BLOCKSIZE); + + /* Initialize the FIR data structure */ + arm_fir_init_f32(&LPF_instance, NUMTAPS, (float32_t *)FIRCoeff_f32, firStateF32, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + * Loop over the frames of data and execute each of the processing + * functions in the system. + * ------------------------------------------------------------------- */ + + for(i=0; i < NUMFRAMES; i++) + { + /* Read the input data - uniformly distributed random noise - into wire1 */ + arm_copy_f32(testInput_f32 + (i * BLOCKSIZE), wire1, BLOCKSIZE); + + /* Execute the FIR processing function. Input wire1 and output wire2 */ + arm_fir_f32(&LPF_instance, wire1, wire2, BLOCKSIZE); + + /* Execute the LMS Norm processing function*/ + + arm_lms_norm_f32(&lmsNorm_instance, /* LMSNorm instance */ + wire1, /* Input signal */ + wire2, /* Reference Signal */ + wire3, /* Converged Signal */ + err_signal, /* Error Signal, this will become small as the signal converges */ + BLOCKSIZE); /* BlockSize */ + + /* apply overall gain */ + arm_scale_f32(wire3, 5, wire3, BLOCKSIZE); /* in-place buffer */ + } + + status = ARM_MATH_SUCCESS; + + /* ------------------------------------------------------------------------------- + * Test whether the error signal has reached towards 0. + * ----------------------------------------------------------------------------- */ + + arm_abs_f32(err_signal, err_signal, BLOCKSIZE); + arm_min_f32(err_signal, BLOCKSIZE, &minValue, &index); + + if (minValue > DELTA_ERROR) + { + status = ARM_MATH_TEST_FAILURE; + } + + /* ---------------------------------------------------------------------- + * Test whether the filter coefficients have converged. + * ------------------------------------------------------------------- */ + + arm_sub_f32((float32_t *)FIRCoeff_f32, lmsNormCoeff_f32, lmsNormCoeff_f32, NUMTAPS); + + arm_abs_f32(lmsNormCoeff_f32, lmsNormCoeff_f32, NUMTAPS); + arm_min_f32(lmsNormCoeff_f32, NUMTAPS, &minValue, &index); + + if (minValue > DELTA_COEFF) + { + status = ARM_MATH_TEST_FAILURE; + } + + /* ---------------------------------------------------------------------- + * Loop here if the signals did not pass the convergence check. + * This denotes a test failure + * ------------------------------------------------------------------- */ + + if( status != ARM_MATH_SUCCESS) + { + while(1); + } + + while(1); /* main function does not return */ +} + + /** \endlink */ + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/system_ARMCM0.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/system_ARMCM0.c new file mode 100644 index 000000000..ece74d2de --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/system_ARMCM0.c @@ -0,0 +1,76 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Cortex-M0 Device System Source File + * for CM0 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/system_ARMCM3.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/system_ARMCM3.c new file mode 100644 index 000000000..2f5fa0b93 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/system_ARMCM3.c @@ -0,0 +1,76 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Cortex-M3 Device System Source File + * for CM3 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/system_ARMCM4.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/system_ARMCM4.c new file mode 100644 index 000000000..beaaf6fb8 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Cortex-M4 Device System Source File + * for CM4 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM4.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ + #endif + + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM0l_sin_cos_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM0l_sin_cos_example.uvopt new file mode 100644 index 000000000..cf1481b0e --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM0l_sin_cos_example.uvopt @@ -0,0 +1,290 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M0 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + + 4803 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM0l_sin_cos_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_sin_cos_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + ARM_MATH_CM0 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_sin_cos_example_f32.c + 1 + ..\arm_sin_cos_example_f32.c + + + + + CMSIS Device + + + system_ARMCM0.c + 1 + ..\system_ARMCM0.c + + + startup_ARMCM0.s + 2 + .\startup_ARMCM0.s + + + + + CMSIS DSP_Library + + + arm_cortexM0l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib + + + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM3l_sin_cos_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM3l_sin_cos_example.uvopt new file mode 100644 index 000000000..94565c87a --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM3l_sin_cos_example.uvopt @@ -0,0 +1,290 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_sin_cos_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 137 + 1 +
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+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM3l_sin_cos_example\../arm_sin_cos_example_f32.c\137 + + + 1 + 0 + 142 + 1 +
346
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM3l_sin_cos_example\../arm_sin_cos_example_f32.c\142 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + ..\arm_sin_cos_example_f32.c + arm_sin_cos_example_f32.c + + + + + CMSIS DeviceSupport + 1 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\system_ARMCM3.c + system_ARMCM3.c + + + 2 + 3 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\startup_ARMCM3.s + startup_ARMCM3.s + + + + + CMSIS SW_DSP_Library + 1 + 0 + 0 + + 3 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM3l_math.lib + arm_cortexM3l_math.lib + + + + + 1 + 0 + + 100 + 0 + + + ..\arm_sin_cos_example_f32.c + 0 + 1 + 1 + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM3l_sin_cos_example.uvproj b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM3l_sin_cos_example.uvproj new file mode 100644 index 000000000..f950fdac2 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM3l_sin_cos_example.uvproj @@ -0,0 +1,425 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M3 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE + + + + 4349 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM3l_sin_cos_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_sin_cos_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM3 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_sin_cos_example_f32.c + 1 + ..\arm_sin_cos_example_f32.c + + + + + CMSIS Device + + + system_ARMCM3.c + 1 + ..\system_ARMCM3.c + + + startup_ARMCM3.s + 2 + .\startup_ARMCM3.s + + + + + CMSIS DSP_Library + + + arm_cortexM3l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM3l_math.lib + + + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM4lf_sin_cos_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM4lf_sin_cos_example.uvopt new file mode 100644 index 000000000..06373a079 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM4lf_sin_cos_example.uvopt @@ -0,0 +1,290 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_sin_cos_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 137 + 1 +
368
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM4lf_sin_cos_example\../arm_sin_cos_example_f32.c\137 + + + 1 + 0 + 142 + 1 +
366
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM4lf_sin_cos_example\../arm_sin_cos_example_f32.c\142 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + ..\arm_sin_cos_example_f32.c + arm_sin_cos_example_f32.c + + + + + CMSIS DeviceSupport + 1 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\system_ARMCM4.c + system_ARMCM4.c + + + 2 + 3 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\startup_ARMCM4.s + startup_ARMCM4.s + + + + + CMSIS SW_DSP_Library + 1 + 0 + 0 + + 3 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + arm_cortexM4lf_math.lib + + + + + 1 + 0 + + 100 + 0 + + + ..\arm_sin_cos_example_f32.c + 0 + 1 + 1 + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM4lf_sin_cos_example.uvproj b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM4lf_sin_cos_example.uvproj new file mode 100644 index 000000000..9677178d4 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM4lf_sin_cos_example.uvproj @@ -0,0 +1,425 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_sin_cos_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_sin_cos_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_sin_cos_example_f32.c + 1 + ..\arm_sin_cos_example_f32.c + + + + + CMSIS Device + + + system_ARMCM4.c + 1 + ..\system_ARMCM4.c + + + startup_ARMCM4.s + 2 + .\startup_ARMCM4.s + + + + + CMSIS DSP_Library + + + arm_cortexM4lf_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + + + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_sin_cos_example.ini b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_sin_cos_example.ini new file mode 100644 index 000000000..813fb16fc --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_sin_cos_example.ini @@ -0,0 +1,14 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_sin_cos_example.ini + +*/ + + +// usual initialisation for target setup +MAP 0x20000000, 0x20008000 READ WRITE // allow R/W access to IO space + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/startup_ARMCM0.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/startup_ARMCM0.s new file mode 100644 index 000000000..0acd34611 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/startup_ARMCM0.s @@ -0,0 +1,144 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Cortex-M0 Core Device Startup File +; * for CM0 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/startup_ARMCM3.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/startup_ARMCM3.s new file mode 100644 index 000000000..5af584bdc --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/startup_ARMCM3.s @@ -0,0 +1,164 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Cortex-M3 Core Device Startup File +; * for CM3 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/startup_ARMCM4.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/startup_ARMCM4.s new file mode 100644 index 000000000..09fdbd6ed --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/startup_ARMCM4.s @@ -0,0 +1,164 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Cortex-M4 Core Device Startup File +; * for CM4 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/arm_sin_cos_example_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/arm_sin_cos_example_f32.c new file mode 100644 index 000000000..a79d813d3 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/arm_sin_cos_example_f32.c @@ -0,0 +1,146 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 29. November 2010 +* $Revision: V1.0.3 +* +* Project: CMSIS DSP Library +* Title: arm_sin_cos_example_f32.c +* +* Description: Example code demonstrating sin and cos calculation of input signal. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.1 2010/10/05 KK +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 KK +* Production release and review comments incorporated. +* ------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup SinCosExample SineCosine Example + * + * \par Description: + * \par + * Demonstrates the Pythagorean trignometric identity with the use of Cosine, Sine, Vector + * Multiplication, and Vector Addition functions. + * + * \par Algorithm: + * \par + * Mathematically, the Pythagorean trignometric identity is defined by the following equation: + * 
sin(x) * sin(x) + cos(x) * cos(x) = 1
+ * where \c x is the angle in radians. + * + * \par Block Diagram: + * \par + * \image html sinCos.gif + * + * \par Variables Description: + * \par + * \li \c testInput_f32 array of input angle in radians + * \li \c testOutput stores sum of the squares of sine and cosine values of input angle + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_cos_f32() + * - arm_sin_f32() + * - arm_mult_f32() + * - arm_add_f32() + * + * Refer + * \link arm_sin_cos_example_f32.c \endlink + * + */ + + +/** \example arm_sin_cos_example_f32.c + */ + +#include +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +* Defines each of the tests performed +* ------------------------------------------------------------------- */ +#define MAX_BLOCKSIZE 32 +#define DELTA (0.000001f) + + +/* ---------------------------------------------------------------------- +* Test input data for Floating point sin_cos example for 32-blockSize +* Generated by the MATLAB randn() function +* ------------------------------------------------------------------- */ + +const float32_t testInput_f32[MAX_BLOCKSIZE] = +{ + -1.244916875853235400, -4.793533929171324800, 0.360705030233248850, 0.827929644170887320, -3.299532218312426900, 3.427441903227623800, 3.422401784294607700, -0.108308165334010680, + 0.941943896490312180, 0.502609575000365850, -0.537345278736373500, 2.088817392965764500, -1.693168684143455700, 6.283185307179590700, -0.392545884746175080, 0.327893095115825040, + 3.070147440456292300, 0.170611405884662230, -0.275275082396073010, -2.395492805446796300, 0.847311163536506600, -3.845517018083148800, 2.055818378415868300, 4.672594161978930800, + -1.990923030266425800, 2.469305197656249500, 3.609002606064021000, -4.586736582331667500, -4.147080139136136300, 1.643756718868359500, -1.150866392366494800, 1.985805026477433800 + + +}; + +const float32_t testRefOutput_f32 = 1.000000000; + +/* ---------------------------------------------------------------------- +* Declare Global variables +* ------------------------------------------------------------------- */ +uint32_t blockSize = 32; +float32_t testOutput; +float32_t cosOutput; +float32_t sinOutput; +float32_t cosSquareOutput; +float32_t sinSquareOutput; + +/* ---------------------------------------------------------------------- +* Max magnitude FFT Bin test +* ------------------------------------------------------------------- */ + +arm_status status; + +int32_t main(void) +{ + float32_t diff; + uint32_t i; + + for(i=0; i< blockSize; i++) + { + cosOutput = arm_cos_f32(testInput_f32[i]); + sinOutput = arm_sin_f32(testInput_f32[i]); + + arm_mult_f32(&cosOutput, &cosOutput, &cosSquareOutput, 1); + arm_mult_f32(&sinOutput, &sinOutput, &sinSquareOutput, 1); + + arm_add_f32(&cosSquareOutput, &sinSquareOutput, &testOutput, 1); + + /* absolute value of difference between ref and test */ + diff = fabsf(testRefOutput_f32 - testOutput); + + /* Comparison of sin_cos value with reference */ + if(diff > DELTA) + { + status = ARM_MATH_TEST_FAILURE; + } + + if( status == ARM_MATH_TEST_FAILURE) + { + while(1); + } + + } + + while(1); /* main function does not return */ +} + + /** \endlink */ + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/system_ARMCM0.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/system_ARMCM0.c new file mode 100644 index 000000000..ece74d2de --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/system_ARMCM0.c @@ -0,0 +1,76 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Cortex-M0 Device System Source File + * for CM0 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/system_ARMCM3.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/system_ARMCM3.c new file mode 100644 index 000000000..2f5fa0b93 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/system_ARMCM3.c @@ -0,0 +1,76 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Cortex-M3 Device System Source File + * for CM3 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/system_ARMCM4.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/system_ARMCM4.c new file mode 100644 index 000000000..beaaf6fb8 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Cortex-M4 Device System Source File + * for CM4 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM4.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ + #endif + + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM0l_variance_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM0l_variance_example.uvopt new file mode 100644 index 000000000..b2f3f6dc3 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM0l_variance_example.uvopt @@ -0,0 +1,290 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_variance_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 182 + 1 +
402
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM0l_variance_example\../arm_variance_example_f32.c\182 + + + 1 + 0 + 185 + 1 +
404
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M0 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + + 4803 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM0l_variance_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_variance_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + ARM_MATH_CM0 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_variance_example_f32.c + 1 + ..\arm_variance_example_f32.c + + + + + CMSIS Device + + + system_ARMCM0.c + 1 + ..\system_ARMCM0.c + + + startup_ARMCM0.s + 2 + .\startup_ARMCM0.s + + + + + CMSIS DSP_Library + + + arm_cortexM0l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib + + + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM3l_variance_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM3l_variance_example.uvopt new file mode 100644 index 000000000..37249e05a --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM3l_variance_example.uvopt @@ -0,0 +1,290 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_variance_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 182 + 1 +
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M3 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE + + + + 4349 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM3l_variance_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_variance_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM3 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_variance_example_f32.c + 1 + ..\arm_variance_example_f32.c + + + + + CMSIS Device + + + system_ARMCM3.c + 1 + ..\system_ARMCM3.c + + + startup_ARMCM3.s + 2 + .\startup_ARMCM3.s + + + + + CMSIS DSP_Library + + + arm_cortexM3l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM3l_math.lib + + + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM4lf_variance_example.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM4lf_variance_example.uvopt new file mode 100644 index 000000000..7cd95d321 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM4lf_variance_example.uvopt @@ -0,0 +1,290 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_variance_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 182 + 1 +
432
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_variance_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_variance_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_variance_example_f32.c + 1 + ..\arm_variance_example_f32.c + + + + + CMSIS Device + + + system_ARMCM4.c + 1 + ..\system_ARMCM4.c + + + startup_ARMCM4.s + 2 + .\startup_ARMCM4.s + + + + + CMSIS DSP_Library + + + arm_cortexM4lf_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + + + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_variance_example.ini b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_variance_example.ini new file mode 100644 index 000000000..0aab2ea8e --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_variance_example.ini @@ -0,0 +1,14 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_variance_example.ini + +*/ + + +// usual initialisation for target setup +MAP 0x20000000, 0x20008000 READ WRITE // allow R/W access to IO space + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/startup_ARMCM0.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/startup_ARMCM0.s new file mode 100644 index 000000000..0acd34611 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/startup_ARMCM0.s @@ -0,0 +1,144 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Cortex-M0 Core Device Startup File +; * for CM0 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/startup_ARMCM3.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/startup_ARMCM3.s new file mode 100644 index 000000000..5af584bdc --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/startup_ARMCM3.s @@ -0,0 +1,164 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Cortex-M3 Core Device Startup File +; * for CM3 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/startup_ARMCM4.s b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/startup_ARMCM4.s new file mode 100644 index 000000000..09fdbd6ed --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/startup_ARMCM4.s @@ -0,0 +1,164 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Cortex-M4 Core Device Startup File +; * for CM4 Device Series +; * @version V1.04 +; * @date 14. January 2011 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; ******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DEF_IRQHandler ; 0: Default +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DEF_IRQHandler [WEAK] +DEF_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/arm_variance_example_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/arm_variance_example_f32.c new file mode 100644 index 000000000..a163302f5 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/arm_variance_example_f32.c @@ -0,0 +1,189 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 29. November 2010 +* $Revision: V1.0.3 +* +* Project: CMSIS DSP Library +* Title: arm_variance_example_f32.c +* +* Description: Example code demonstrating variance calculation of input sequence. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.1 2010/10/05 KK +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 KK +* Production release and review comments incorporated. +* ------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup VarianceExample Variance Example + * + * \par Description: + * \par + * Demonstrates the use of Basic Math and Support Functions to calculate the variance of an + * input sequence with N samples. Uniformly distributed white noise is taken as input. + * + * \par Algorithm: + * \par + * The variance of a sequence is the mean of the squared deviation of the sequence from its mean. + * \par + * This is denoted by the following equation: + * 
 variance = ((x[0] - x') * (x[0] - x') + (x[1] - x') * (x[1] - x') + ... + * (x[n-1] - x') * (x[n-1] - x')) / (N-1)
+ * where, x[n] is the input sequence, N is the number of input samples, and + * x' is the mean value of the input sequence, x[n]. + * \par + * The mean value x' is defined as: + * 
 x' = (x[0] + x[1] + ... + x[n-1]) / N
+ * + * \par Block Diagram: + * \par + * \image html Variance.gif + * + * + * \par Variables Description: + * \par + * \li \c testInput_f32 points to the input data + * \li \c wire1, \c wir2, \c wire3 temporary buffers + * \li \c blockSize number of samples processed at a time + * \li \c refVarianceOut reference variance value + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_dot_prod_f32() + * - arm_mult_f32() + * - arm_sub_f32() + * - arm_fill_f32() + * - arm_copy_f32() + * + * Refer + * \link arm_variance_example_f32.c \endlink + * + */ + + +/** \example arm_variance_example_f32.c + */ +#include +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +* Defines each of the tests performed +* ------------------------------------------------------------------- */ +#define MAX_BLOCKSIZE 32 +#define DELTA (0.000001f) + + +/* ---------------------------------------------------------------------- +* Declare I/O buffers +* ------------------------------------------------------------------- */ +float32_t wire1[MAX_BLOCKSIZE]; +float32_t wire2[MAX_BLOCKSIZE]; +float32_t wire3[MAX_BLOCKSIZE]; + +/* ---------------------------------------------------------------------- +* Test input data for Floating point Variance example for 32-blockSize +* Generated by the MATLAB randn() function +* ------------------------------------------------------------------- */ + +float32_t testInput_f32[32] = +{ +-0.432564811528221, -1.665584378238097, 0.125332306474831, 0.287676420358549, +-1.146471350681464, 1.190915465642999, 1.189164201652103, -0.037633276593318, +0.327292361408654, 0.174639142820925, -0.186708577681439, 0.725790548293303, +-0.588316543014189, 2.183185818197101, -0.136395883086596, 0.113931313520810, +1.066768211359189, 0.059281460523605, -0.095648405483669, -0.832349463650022, +0.294410816392640, -1.336181857937804, 0.714324551818952, 1.623562064446271, +-0.691775701702287, 0.857996672828263, 1.254001421602532, -1.593729576447477, +-1.440964431901020, 0.571147623658178, -0.399885577715363, 0.689997375464345 + +}; + +/* ---------------------------------------------------------------------- +* Declare Global variables +* ------------------------------------------------------------------- */ +uint32_t blockSize = 32; +float32_t refVarianceOut = 0.903941793931839; + +/* ---------------------------------------------------------------------- +* Variance calculation test +* ------------------------------------------------------------------- */ + +int32_t main(void) +{ + arm_status status; + float32_t mean, oneByBlockSize; + float32_t variance; + float32_t diff; + + status = ARM_MATH_SUCCESS; + + /* Calculation of mean value of input */ + + /* x' = 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1) */ + + /* Fill wire1 buffer with 1.0 value */ + arm_fill_f32(1.0, wire1, blockSize); + + /* Calculate the dot product of wire1 and wire2 */ + /* (x(0)* 1 + x(1) * 1 + ...+ x(n-1) * 1) */ + arm_dot_prod_f32(testInput_f32, wire1, blockSize, &mean); + + /* Calculation of 1/blockSize */ + oneByBlockSize = 1.0 / (blockSize); + + /* 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1) */ + arm_mult_f32(&mean, &oneByBlockSize, &mean, 1); + + + /* Calculation of variance value of input */ + + /* (1/blockSize) * (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */ + + /* Fill wire2 with mean value x' */ + arm_fill_f32(mean, wire2, blockSize); + + /* wire3 contains (x-x') */ + arm_sub_f32(testInput_f32, wire2, wire3, blockSize); + + /* wire2 contains (x-x') */ + arm_copy_f32(wire3, wire2, blockSize); + + /* (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */ + arm_dot_prod_f32(wire2, wire3, blockSize, &variance); + + /* Calculation of 1/blockSize */ + oneByBlockSize = 1.0 / (blockSize - 1); + + /* Calculation of variance */ + arm_mult_f32(&variance, &oneByBlockSize, &variance, 1); + + /* absolute value of difference between ref and test */ + diff = fabsf(refVarianceOut - variance); + + /* Comparison of variance value with reference */ + if(diff > DELTA) + { + status = ARM_MATH_TEST_FAILURE; + } + + if( status != ARM_MATH_SUCCESS) + { + while(1); + } + + while(1); /* main function does not return */ +} + + /** \endlink */ + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/system_ARMCM0.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/system_ARMCM0.c new file mode 100644 index 000000000..ece74d2de --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/system_ARMCM0.c @@ -0,0 +1,76 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Cortex-M0 Device System Source File + * for CM0 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/system_ARMCM3.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/system_ARMCM3.c new file mode 100644 index 000000000..2f5fa0b93 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/system_ARMCM3.c @@ -0,0 +1,76 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Cortex-M3 Device System Source File + * for CM3 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/system_ARMCM4.c b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/system_ARMCM4.c new file mode 100644 index 000000000..beaaf6fb8 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Examples/arm_variance_example/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Cortex-M4 Device System Source File + * for CM4 Device Series + * @version V1.05 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM4.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL (12000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (4*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ + #endif + + SystemCoreClock = __SYSTEM_CLOCK; + +#ifdef __USE_GPIO + ARM_GPIO0->DATA[0].WORD = 0; + ARM_GPIO0->IE = 0; + ARM_GPIO0->DIR = 0xff83; + + ARM_GPIO1->DATA[0].WORD = 0; + ARM_GPIO1->IE = 0; + ARM_GPIO1->DIR = 0; + + ARM_GPIO2->DATA[0].WORD = 0; + ARM_GPIO2->IE = 0; + ARM_GPIO2->DIR = 0; +#endif +} diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ARM/arm_cortexM0x_math.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Source/ARM/arm_cortexM0x_math.uvopt new file mode 100644 index 000000000..ff5038c54 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ARM/arm_cortexM0x_math.uvopt @@ -0,0 +1,3711 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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..\FilteringFunctions\arm_fir_init_f32.c + + + arm_fir_init_q7.c + 1 + ..\FilteringFunctions\arm_fir_init_q7.c + + + arm_fir_init_q15.c + 1 + ..\FilteringFunctions\arm_fir_init_q15.c + + + arm_fir_init_q31.c + 1 + ..\FilteringFunctions\arm_fir_init_q31.c + + + arm_fir_interpolate_f32.c + 1 + ..\FilteringFunctions\arm_fir_interpolate_f32.c + + + arm_fir_interpolate_init_f32.c + 1 + ..\FilteringFunctions\arm_fir_interpolate_init_f32.c + + + arm_fir_interpolate_init_q15.c + 1 + ..\FilteringFunctions\arm_fir_interpolate_init_q15.c + + + arm_fir_interpolate_init_q31.c + 1 + ..\FilteringFunctions\arm_fir_interpolate_init_q31.c + + + arm_fir_interpolate_q15.c + 1 + ..\FilteringFunctions\arm_fir_interpolate_q15.c + + + arm_fir_interpolate_q31.c + 1 + ..\FilteringFunctions\arm_fir_interpolate_q31.c + + + arm_fir_lattice_f32.c + 1 + ..\FilteringFunctions\arm_fir_lattice_f32.c + + + arm_fir_lattice_init_f32.c + 1 + ..\FilteringFunctions\arm_fir_lattice_init_f32.c + + + arm_fir_lattice_init_q15.c + 1 + ..\FilteringFunctions\arm_fir_lattice_init_q15.c + + + arm_fir_lattice_init_q31.c + 1 + ..\FilteringFunctions\arm_fir_lattice_init_q31.c + + + arm_fir_lattice_q15.c + 1 + ..\FilteringFunctions\arm_fir_lattice_q15.c + + + arm_fir_lattice_q31.c + 1 + ..\FilteringFunctions\arm_fir_lattice_q31.c + + + arm_fir_q7.c + 1 + ..\FilteringFunctions\arm_fir_q7.c + + + arm_fir_q15.c + 1 + ..\FilteringFunctions\arm_fir_q15.c + + + arm_fir_q31.c + 1 + ..\FilteringFunctions\arm_fir_q31.c + + + arm_fir_sparse_f32.c + 1 + ..\FilteringFunctions\arm_fir_sparse_f32.c + + + arm_fir_sparse_init_f32.c + 1 + ..\FilteringFunctions\arm_fir_sparse_init_f32.c + + + arm_fir_sparse_init_q7.c + 1 + ..\FilteringFunctions\arm_fir_sparse_init_q7.c + + + arm_fir_sparse_init_q15.c + 1 + ..\FilteringFunctions\arm_fir_sparse_init_q15.c + + + arm_fir_sparse_init_q31.c + 1 + ..\FilteringFunctions\arm_fir_sparse_init_q31.c + + + arm_fir_sparse_q7.c + 1 + ..\FilteringFunctions\arm_fir_sparse_q7.c + + + arm_fir_sparse_q15.c + 1 + ..\FilteringFunctions\arm_fir_sparse_q15.c + + + arm_fir_sparse_q31.c + 1 + ..\FilteringFunctions\arm_fir_sparse_q31.c + + + arm_iir_lattice_f32.c + 1 + ..\FilteringFunctions\arm_iir_lattice_f32.c + + + arm_iir_lattice_init_f32.c + 1 + ..\FilteringFunctions\arm_iir_lattice_init_f32.c + + + arm_iir_lattice_init_q15.c + 1 + ..\FilteringFunctions\arm_iir_lattice_init_q15.c + + + arm_iir_lattice_init_q31.c + 1 + ..\FilteringFunctions\arm_iir_lattice_init_q31.c + + + arm_iir_lattice_q15.c + 1 + ..\FilteringFunctions\arm_iir_lattice_q15.c + + + arm_iir_lattice_q31.c + 1 + ..\FilteringFunctions\arm_iir_lattice_q31.c + + + arm_lms_f32.c + 1 + ..\FilteringFunctions\arm_lms_f32.c + + + arm_lms_init_f32.c + 1 + ..\FilteringFunctions\arm_lms_init_f32.c + + + arm_lms_init_q15.c + 1 + ..\FilteringFunctions\arm_lms_init_q15.c + + + arm_lms_init_q31.c + 1 + ..\FilteringFunctions\arm_lms_init_q31.c + + + arm_lms_norm_f32.c + 1 + ..\FilteringFunctions\arm_lms_norm_f32.c + + + arm_lms_norm_init_f32.c + 1 + ..\FilteringFunctions\arm_lms_norm_init_f32.c + + + arm_lms_norm_init_q15.c + 1 + ..\FilteringFunctions\arm_lms_norm_init_q15.c + + + arm_lms_norm_init_q31.c + 1 + ..\FilteringFunctions\arm_lms_norm_init_q31.c + + + arm_lms_norm_q15.c + 1 + ..\FilteringFunctions\arm_lms_norm_q15.c + + + arm_lms_norm_q31.c + 1 + ..\FilteringFunctions\arm_lms_norm_q31.c + + + arm_lms_q15.c + 1 + ..\FilteringFunctions\arm_lms_q15.c + + + arm_lms_q31.c + 1 + ..\FilteringFunctions\arm_lms_q31.c + + + + + MatrixFunctions + + + arm_mat_add_f32.c + 1 + ..\MatrixFunctions\arm_mat_add_f32.c + + + arm_mat_add_q15.c + 1 + ..\MatrixFunctions\arm_mat_add_q15.c + + + arm_mat_add_q31.c + 1 + ..\MatrixFunctions\arm_mat_add_q31.c + + + arm_mat_init_f32.c + 1 + ..\MatrixFunctions\arm_mat_init_f32.c + + + arm_mat_init_q15.c + 1 + ..\MatrixFunctions\arm_mat_init_q15.c + + + arm_mat_init_q31.c + 1 + ..\MatrixFunctions\arm_mat_init_q31.c + + + arm_mat_inverse_f32.c + 1 + ..\MatrixFunctions\arm_mat_inverse_f32.c + + + arm_mat_mult_f32.c + 1 + ..\MatrixFunctions\arm_mat_mult_f32.c + + + arm_mat_mult_fast_q15.c + 1 + ..\MatrixFunctions\arm_mat_mult_fast_q15.c + + + arm_mat_mult_fast_q31.c + 1 + ..\MatrixFunctions\arm_mat_mult_fast_q31.c + + + arm_mat_mult_q15.c + 1 + ..\MatrixFunctions\arm_mat_mult_q15.c + + + arm_mat_mult_q31.c + 1 + ..\MatrixFunctions\arm_mat_mult_q31.c + + + arm_mat_scale_f32.c + 1 + ..\MatrixFunctions\arm_mat_scale_f32.c + + + arm_mat_scale_q15.c + 1 + ..\MatrixFunctions\arm_mat_scale_q15.c + + + arm_mat_scale_q31.c + 1 + ..\MatrixFunctions\arm_mat_scale_q31.c + + + arm_mat_sub_f32.c + 1 + ..\MatrixFunctions\arm_mat_sub_f32.c + + + arm_mat_sub_q15.c + 1 + ..\MatrixFunctions\arm_mat_sub_q15.c + + + arm_mat_sub_q31.c + 1 + ..\MatrixFunctions\arm_mat_sub_q31.c + + + arm_mat_trans_f32.c + 1 + ..\MatrixFunctions\arm_mat_trans_f32.c + + + arm_mat_trans_q15.c + 1 + ..\MatrixFunctions\arm_mat_trans_q15.c + + + arm_mat_trans_q31.c + 1 + ..\MatrixFunctions\arm_mat_trans_q31.c + + + + + TransformFunctions + + + arm_cfft_radix4_f32.c + 1 + ..\TransformFunctions\arm_cfft_radix4_f32.c + + + arm_cfft_radix4_init_f32.c + 1 + ..\TransformFunctions\arm_cfft_radix4_init_f32.c + + + arm_cfft_radix4_init_q15.c + 1 + ..\TransformFunctions\arm_cfft_radix4_init_q15.c + + + arm_cfft_radix4_init_q31.c + 1 + ..\TransformFunctions\arm_cfft_radix4_init_q31.c + + + arm_cfft_radix4_q15.c + 1 + ..\TransformFunctions\arm_cfft_radix4_q15.c + + + arm_cfft_radix4_q31.c + 1 + ..\TransformFunctions\arm_cfft_radix4_q31.c + + + arm_dct4_f32.c + 1 + ..\TransformFunctions\arm_dct4_f32.c + + + arm_dct4_init_f32.c + 1 + ..\TransformFunctions\arm_dct4_init_f32.c + + + arm_dct4_init_q15.c + 1 + ..\TransformFunctions\arm_dct4_init_q15.c + + + arm_dct4_init_q31.c + 1 + ..\TransformFunctions\arm_dct4_init_q31.c + + + arm_dct4_q15.c + 1 + ..\TransformFunctions\arm_dct4_q15.c + + + arm_dct4_q31.c + 1 + ..\TransformFunctions\arm_dct4_q31.c + + + arm_rfft_f32.c + 1 + ..\TransformFunctions\arm_rfft_f32.c + + + arm_rfft_init_f32.c + 1 + ..\TransformFunctions\arm_rfft_init_f32.c + + + arm_rfft_init_q15.c + 1 + ..\TransformFunctions\arm_rfft_init_q15.c + + + arm_rfft_init_q31.c + 1 + ..\TransformFunctions\arm_rfft_init_q31.c + + + arm_rfft_q15.c + 1 + ..\TransformFunctions\arm_rfft_q15.c + + + arm_rfft_q31.c + 1 + ..\TransformFunctions\arm_rfft_q31.c + + + + + ControllerFunctions + + + arm_pid_init_f32.c + 1 + ..\ControllerFunctions\arm_pid_init_f32.c + + + arm_pid_init_q15.c + 1 + ..\ControllerFunctions\arm_pid_init_q15.c + + + arm_pid_init_q31.c + 1 + ..\ControllerFunctions\arm_pid_init_q31.c + + + arm_pid_reset_f32.c + 1 + ..\ControllerFunctions\arm_pid_reset_f32.c + + + arm_pid_reset_q15.c + 1 + ..\ControllerFunctions\arm_pid_reset_q15.c + + + arm_pid_reset_q31.c + 1 + ..\ControllerFunctions\arm_pid_reset_q31.c + + + arm_sin_cos_f32.c + 1 + ..\ControllerFunctions\arm_sin_cos_f32.c + + + arm_sin_cos_q31.c + 1 + ..\ControllerFunctions\arm_sin_cos_q31.c + + + + + StatisticsFunctions + + + arm_max_f32.c + 1 + ..\StatisticsFunctions\arm_max_f32.c + + + arm_max_q7.c + 1 + ..\StatisticsFunctions\arm_max_q7.c + + + arm_max_q15.c + 1 + ..\StatisticsFunctions\arm_max_q15.c + + + arm_max_q31.c + 1 + ..\StatisticsFunctions\arm_max_q31.c + + + arm_mean_f32.c + 1 + ..\StatisticsFunctions\arm_mean_f32.c + + + arm_mean_q7.c + 1 + ..\StatisticsFunctions\arm_mean_q7.c + + + arm_mean_q15.c + 1 + ..\StatisticsFunctions\arm_mean_q15.c + + + arm_mean_q31.c + 1 + ..\StatisticsFunctions\arm_mean_q31.c + + + arm_min_f32.c + 1 + ..\StatisticsFunctions\arm_min_f32.c + + + arm_min_q7.c + 1 + ..\StatisticsFunctions\arm_min_q7.c + + + arm_min_q15.c + 1 + ..\StatisticsFunctions\arm_min_q15.c + + + arm_min_q31.c + 1 + ..\StatisticsFunctions\arm_min_q31.c + + + arm_power_f32.c + 1 + ..\StatisticsFunctions\arm_power_f32.c + + + arm_power_q7.c + 1 + ..\StatisticsFunctions\arm_power_q7.c + + + arm_power_q15.c + 1 + ..\StatisticsFunctions\arm_power_q15.c + + + arm_power_q31.c + 1 + ..\StatisticsFunctions\arm_power_q31.c + + + arm_rms_f32.c + 1 + ..\StatisticsFunctions\arm_rms_f32.c + + + arm_rms_q15.c + 1 + ..\StatisticsFunctions\arm_rms_q15.c + + + arm_rms_q31.c + 1 + ..\StatisticsFunctions\arm_rms_q31.c + + + arm_std_f32.c + 1 + ..\StatisticsFunctions\arm_std_f32.c + + + arm_std_q15.c + 1 + ..\StatisticsFunctions\arm_std_q15.c + + + arm_std_q31.c + 1 + ..\StatisticsFunctions\arm_std_q31.c + + + arm_var_f32.c + 1 + ..\StatisticsFunctions\arm_var_f32.c + + + arm_var_q15.c + 1 + ..\StatisticsFunctions\arm_var_q15.c + + + arm_var_q31.c + 1 + ..\StatisticsFunctions\arm_var_q31.c + + + + + SupportFunctions + + + arm_copy_f32.c + 1 + ..\SupportFunctions\arm_copy_f32.c + + + arm_copy_q7.c + 1 + ..\SupportFunctions\arm_copy_q7.c + + + arm_copy_q15.c + 1 + ..\SupportFunctions\arm_copy_q15.c + + + arm_copy_q31.c + 1 + ..\SupportFunctions\arm_copy_q31.c + + + arm_fill_f32.c + 1 + ..\SupportFunctions\arm_fill_f32.c + + + arm_fill_q7.c + 1 + ..\SupportFunctions\arm_fill_q7.c + + + arm_fill_q15.c + 1 + ..\SupportFunctions\arm_fill_q15.c + + + arm_fill_q31.c + 1 + ..\SupportFunctions\arm_fill_q31.c + + + arm_float_to_q7.c + 1 + ..\SupportFunctions\arm_float_to_q7.c + + + arm_float_to_q15.c + 1 + ..\SupportFunctions\arm_float_to_q15.c + + + arm_float_to_q31.c + 1 + ..\SupportFunctions\arm_float_to_q31.c + + + arm_q7_to_float.c + 1 + ..\SupportFunctions\arm_q7_to_float.c + + + arm_q7_to_q15.c + 1 + ..\SupportFunctions\arm_q7_to_q15.c + + + arm_q7_to_q31.c + 1 + ..\SupportFunctions\arm_q7_to_q31.c + + + arm_q15_to_float.c + 1 + ..\SupportFunctions\arm_q15_to_float.c + + + arm_q15_to_q7.c + 1 + ..\SupportFunctions\arm_q15_to_q7.c + + + arm_q15_to_q31.c + 1 + ..\SupportFunctions\arm_q15_to_q31.c + + + arm_q31_to_float.c + 1 + ..\SupportFunctions\arm_q31_to_float.c + + + arm_q31_to_q7.c + 1 + ..\SupportFunctions\arm_q31_to_q7.c + + + arm_q31_to_q15.c + 1 + ..\SupportFunctions\arm_q31_to_q15.c + + + + + CommonTables + + + arm_common_tables.c + 1 + ..\CommonTables\arm_common_tables.c + + + + + + + + diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ARM/arm_cortexMx_math_Build.bat b/hardware/sam/system/CMSIS/DSP_Lib/Source/ARM/arm_cortexMx_math_Build.bat new file mode 100644 index 000000000..600ceb55e --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ARM/arm_cortexMx_math_Build.bat @@ -0,0 +1,14 @@ + +SET TMP=C:\Temp +SET TEMP=C:\Temp + +SET UVEXE=C:\Keil\UV4\UV4.EXE + +%UVEXE% -rb arm_cortexM0x_math.uvproj -t"DSP_Lib CM0 LE" -o"DSP_Lib CM0 LE.txt" +%UVEXE% -rb arm_cortexM0x_math.uvproj -t"DSP_Lib CM0 BE" -o"DSP_Lib CM0 BE.txt" +%UVEXE% -rb arm_cortexM3x_math.uvproj -t"DSP_Lib CM3 LE" -o"DSP_Lib CM3 LE.txt" +%UVEXE% -rb arm_cortexM3x_math.uvproj -t"DSP_Lib CM3 BE" -o"DSP_Lib CM3 BE.txt" +%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 LE" -o"DSP_Lib CM4 LE.txt" +%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 BE" -o"DSP_Lib CM4 BE.txt" +%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 LE FPU" -o"DSP_Lib CM4 LE FPU.txt" +%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 BE FPU" -o"DSP_Lib CM4 BE FPU.txt" \ No newline at end of file diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_f32.c new file mode 100644 index 000000000..2b6bd5389 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_f32.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_abs_f32.c +* +* Description: Vector absolute value. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* ---------------------------------------------------------------------------- */ + +#include "arm_math.h" +#include + +/** + * @ingroup groupMath + */ + +/** + * @defgroup BasicAbs Vector Absolute Value + * + * Computes the absolute value of a vector on an element-by-element basis. + * + * 
   
+ *     pDst[n] = abs(pSrcA[n]),   0 <= n < blockSize.   
+ *
+ * + * The operation can be done in-place by setting the input and output pointers to the same buffer. + * There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + * @addtogroup BasicAbs + * @{ + */ + +/** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = |A| */ + /* Calculate absolute and then store the results in the destination buffer. */ + *pDst++ = fabsf(*pSrc++); + *pDst++ = fabsf(*pSrc++); + *pDst++ = fabsf(*pSrc++); + *pDst++ = fabsf(*pSrc++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = |A| */ + /* Calculate absolute and then store the results in the destination buffer. */ + *pDst++ = fabsf(*pSrc++); + + /* Decrement the loop counter */ + blkCnt--; + } + +} + +/** + * @} end of BasicAbs group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c new file mode 100644 index 000000000..0a3941bef --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c @@ -0,0 +1,170 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_abs_q15.c +* +* Description: Q15 vector absolute value. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicAbs + * @{ + */ + +/** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. + */ + +void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + q15_t in1; /* Input value1 */ + q15_t in2; /* Input value2 */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = |A| */ + /* Read two inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + + + /* Store the Absolute result in the destination buffer by packing the two values, in a single cycle */ + +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = + __PKHBT(((in1 > 0) ? in1 : __SSAT(-in1, 16)), + ((in2 > 0) ? in2 : __SSAT(-in2, 16)), 16); + +#else + + + *__SIMD32(pDst)++ = + __PKHBT(((in2 > 0) ? in2 : __SSAT(-in2, 16)), + ((in1 > 0) ? in1 : __SSAT(-in1, 16)), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + in1 = *pSrc++; + in2 = *pSrc++; + + +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = + __PKHBT(((in1 > 0) ? in1 : __SSAT(-in1, 16)), + ((in2 > 0) ? in2 : __SSAT(-in2, 16)), 16); + + +#else + + *__SIMD32(pDst)++ = + __PKHBT(((in2 > 0) ? in2 : __SSAT(-in2, 16)), + ((in1 > 0) ? in1 : __SSAT(-in1, 16)), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = |A| */ + /* Read the input */ + in1 = *pSrc++; + + /* Calculate absolute value of input and then store the result in the destination buffer. */ + *pDst++ = (in1 > 0) ? in1 : __SSAT(-in1, 16); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + q15_t in; /* Temporary input variable */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = |A| */ + /* Read the input */ + in = *pSrc++; + + /* Calculate absolute value of input and then store the result in the destination buffer. */ + *pDst++ = (in > 0) ? in : __SSAT(-in, 16); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of BasicAbs group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c new file mode 100644 index 000000000..52d7d3d33 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c @@ -0,0 +1,120 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_abs_q31.c +* +* Description: Q31 vector absolute value. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicAbs + * @{ + */ + + +/** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. + */ + +void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + q31_t in; /* Input value */ + +#ifndef ARM_MATH_CM0 + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = |A| */ + /* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */ + in = *pSrc++; + *pDst++ = (in > 0) ? in : ((in == 0x80000000) ? 0x7fffffff : -in); + in = *pSrc++; + *pDst++ = (in > 0) ? in : ((in == 0x80000000) ? 0x7fffffff : -in); + in = *pSrc++; + *pDst++ = (in > 0) ? in : ((in == 0x80000000) ? 0x7fffffff : -in); + in = *pSrc++; + *pDst++ = (in > 0) ? in : ((in == 0x80000000) ? 0x7fffffff : -in); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = |A| */ + /* Calculate absolute value of the input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */ + in = *pSrc++; + *pDst++ = (in > 0) ? in : ((in == 0x80000000) ? 0x7fffffff : -in); + + /* Decrement the loop counter */ + blkCnt--; + } + +} + +/** + * @} end of BasicAbs group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c new file mode 100644 index 000000000..81019fd90 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c @@ -0,0 +1,143 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_abs_q7.c +* +* Description: Q7 vector absolute value. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicAbs + * @{ + */ + +/** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. + */ + +void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + q7_t in1; /* Input value1 */ + q7_t in2; /* Input value2 */ + q7_t in3; /* Input value3 */ + q7_t in4; /* Input value4 */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = |A| */ + /* Read 4 inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + /* Store the Absolute result in the destination buffer by packing the 4 values in single cycle */ + *__SIMD32(pDst)++ = + __PACKq7(((in1 > 0) ? in1 : __SSAT(-in1, 8)), + ((in2 > 0) ? in2 : __SSAT(-in2, 8)), + ((in3 > 0) ? in3 : __SSAT(-in3, 8)), + ((in4 > 0) ? in4 : __SSAT(-in4, 8))); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = |A| */ + /* Read the input */ + in1 = *pSrc++; + + /* Store the Absolute result in the destination buffer */ + *pDst++ = (in1 > 0) ? in1 : __SSAT(-in1, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + q7_t in; /* Temporary input varible */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = |A| */ + /* Read the input */ + in = *pSrc++; + + /* Store the Absolute result in the destination buffer */ + *pDst++ = (in > 0) ? in : __SSAT(-in, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of BasicAbs group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c new file mode 100644 index 000000000..d73a6ef68 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_add_f32.c +* +* Description: Floating-point vector addition. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* ---------------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup BasicAdd Vector Addition + * + * Element-by-element addition of two vectors. + * + * 
   
+ *     pDst[n] = pSrcA[n] + pSrcB[n],   0 <= n < blockSize.   
+ *
+ * + * There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + * @addtogroup BasicAdd + * @{ + */ + +/** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = (*pSrcA++) + (*pSrcB++); + *pDst++ = (*pSrcA++) + (*pSrcB++); + *pDst++ = (*pSrcA++) + (*pSrcB++); + *pDst++ = (*pSrcA++) + (*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = (*pSrcA++) + (*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of BasicAdd group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c new file mode 100644 index 000000000..f4ede5325 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c @@ -0,0 +1,127 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_add_q15.c +* +* Description: Q15 vector addition +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicAdd + * @{ + */ + +/** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++); + *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = (q15_t) __QADD16(*pSrcA++, *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ + *pSrcB++), 16); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + + +} + +/** + * @} end of BasicAdd group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c new file mode 100644 index 000000000..e33b9e2fd --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c @@ -0,0 +1,129 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_add_q31.c +* +* Description: Q31 vector addition. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicAdd + * @{ + */ + + +/** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated. + */ + +void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ + *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of BasicAdd group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c new file mode 100644 index 000000000..08199c31b --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_add_q7.c +* +* Description: Q7 vector addition. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicAdd + * @{ + */ + +/** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ + +void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = (q7_t) __SSAT(*pSrcA++ + *pSrcB++, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ + *pSrcB++, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + + +} + +/** + * @} end of BasicAdd group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c new file mode 100644 index 000000000..bc7516e5a --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_dot_prod_f32.c +* +* Description: Floating-point dot product. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* ---------------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup dot_prod Vector Dot Product + * + * Computes the dot product of two vectors. + * The vectors are multiplied element-by-element and then summed. + * There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + * @addtogroup dot_prod + * @{ + */ + +/** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + +void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result) +{ + float32_t sum = 0.0f; /* Temporary result storage */ + uint32_t blkCnt; /* loop counter */ + + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer */ + sum += (*pSrcA++) * (*pSrcB++); + sum += (*pSrcA++) * (*pSrcB++); + sum += (*pSrcA++) * (*pSrcB++); + sum += (*pSrcA++) * (*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer. */ + sum += (*pSrcA++) * (*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + /* Store the result back in the destination buffer */ + *result = sum; +} + +/** + * @} end of dot_prod group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c new file mode 100644 index 000000000..50be68cf9 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_dot_prod_q15.c +* +* Description: Q15 dot product. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup dot_prod + * @{ + */ + +/** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The intermediate multiplications are in 1.15 x 1.15 = 2.30 format and these + * results are added to a 64-bit accumulator in 34.30 format. + * Nonsaturating additions are used and given that there are 33 guard bits in the accumulator + * there is no risk of overflow. + * The return result is in 34.30 format. + */ + +void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result) +{ + q63_t sum = 0; /* Temporary result storage */ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer. */ + sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum); + sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the results in a temporary buffer. */ + sum = __SMLALD(*pSrcA++, *pSrcB++, sum); + + /* Decrement the loop counter */ + blkCnt--; + } + + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the results in a temporary buffer. */ + sum += (q63_t) ((q31_t) * pSrcA++ * *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + + /* Store the result in the destination buffer in 34.30 format */ + *result = sum; + +} + +/** + * @} end of dot_prod group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c new file mode 100644 index 000000000..eb5f674a7 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c @@ -0,0 +1,124 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_dot_prod_q31.c +* +* Description: Q31 dot product. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup dot_prod + * @{ + */ + +/** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The intermediate multiplications are in 1.31 x 1.31 = 2.62 format and these + * are truncated to 2.48 format by discarding the lower 14 bits. + * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. + * There are 15 guard bits in the accumulator and there is no risk of overflow as long as + * the length of the vectors is less than 2^16 elements. + * The return result is in 16.48 format. + */ + +void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result) +{ + q63_t sum = 0; /* Temporary result storage */ + uint32_t blkCnt; /* loop counter */ + + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer. */ + sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14u; + sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14u; + sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14u; + sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14u; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer. */ + sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14u; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Store the result in the destination buffer in 16.48 format */ + *result = sum; +} + +/** + * @} end of dot_prod group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c new file mode 100644 index 000000000..cfea032ff --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c @@ -0,0 +1,163 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_dot_prod_q7.c +* +* Description: Q7 dot product. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup dot_prod + * @{ + */ + +/** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The intermediate multiplications are in 1.7 x 1.7 = 2.14 format and these + * results are added to an accumulator in 18.14 format. + * Nonsaturating additions are used and there is no danger of wrap around as long as + * the vectors are less than 2^18 elements long. + * The return result is in 18.14 format. + */ + +void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result) +{ + uint32_t blkCnt; /* loop counter */ + + q31_t sum = 0; /* Temporary variables to store output */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + q31_t input1, input2; /* Temporary variables to store input */ + q15_t in1, in2; /* Temporary variables to store input */ + + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) * pSrcA++; + in2 = (q15_t) * pSrcA++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) * pSrcB++; + in2 = (q15_t) * pSrcB++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Perform Dot product of 2 packed inputs using SMLALD and store the result in a temporary variable. */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) * pSrcA++; + in2 = (q15_t) * pSrcA++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) * pSrcB++; + in2 = (q15_t) * pSrcB++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Perform Dot product of 2 packed inputs using SMLALD and store the result in a temporary variable. */ + sum = __SMLAD(input1, input2, sum); + + + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Dot product and then store the results in a temporary buffer. */ + sum = __SMLAD(*pSrcA++, *pSrcB++, sum); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Dot product and then store the results in a temporary buffer. */ + sum += (q31_t) ((q15_t) * pSrcA++ * *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + + + /* Store the result in the destination buffer in 18.14 format */ + *result = sum; +} + +/** + * @} end of dot_prod group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c new file mode 100644 index 000000000..5c2dac070 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_mult_f32.c +* +* Description: Floating-point vector multiplication. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.5 2010/04/26 +* incorporated review comments and updated with latest CMSIS layer +* +* Version 0.0.3 2010/03/10 +* Initial version +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup BasicMult Vector Multiplication + * + * Element-by-element multiplication of two vectors. + * + * 
   
+ *     pDst[n] = pSrcA[n] * pSrcB[n],   0 <= n < blockSize.   
+ *
+ * + * There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + * @addtogroup BasicMult + * @{ + */ + +/** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + /* loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A * B */ + /* Multiply the inputs and store the results in output buffer */ + *pDst++ = (*pSrcA++) * (*pSrcB++); + *pDst++ = (*pSrcA++) * (*pSrcB++); + *pDst++ = (*pSrcA++) * (*pSrcB++); + *pDst++ = (*pSrcA++) * (*pSrcB++); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + + while(blkCnt > 0u) + { + /* C = A * B */ + /* Multiply the inputs and store the results in output buffer */ + *pDst++ = (*pSrcA++) * (*pSrcB++); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + +} + +/** + * @} end of BasicMult group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c new file mode 100644 index 000000000..76a3843c4 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c @@ -0,0 +1,119 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_mult_q15.c +* +* Description: Q15 vector multiplication. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.5 2010/04/26 +* incorporated review comments and updated with latest CMSIS layer +* +* Version 0.0.3 2010/03/10 +* Initial version +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicMult + * @{ + */ + + +/** + * @brief Q15 vector multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + /* loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A * B */ + /* Multiply the inputs and store the result in the destination buffer */ + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + + while(blkCnt > 0u) + { + /* C = A * B */ + /* Multiply the inputs and store the result in the destination buffer */ + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of BasicMult group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c new file mode 100644 index 000000000..c682c1123 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_mult_q31.c +* +* Description: Q31 vector multiplication. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.5 2010/04/26 +* incorporated review comments and updated with latest CMSIS layer +* +* Version 0.0.3 2010/03/10 +* Initial version +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicMult + * @{ + */ + +/** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated. + */ + +void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + /* loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A * B */ + /* Multiply the inputs and then store the results in the destination buffer. */ + *pDst++ = + (q31_t) clip_q63_to_q31(((q63_t) (*pSrcA++) * (*pSrcB++)) >> 31); + *pDst++ = + (q31_t) clip_q63_to_q31(((q63_t) (*pSrcA++) * (*pSrcB++)) >> 31); + *pDst++ = + (q31_t) clip_q63_to_q31(((q63_t) (*pSrcA++) * (*pSrcB++)) >> 31); + *pDst++ = + (q31_t) clip_q63_to_q31(((q63_t) (*pSrcA++) * (*pSrcB++)) >> 31); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = A * B */ + /* Multiply the inputs and then store the results in the destination buffer. */ + *pDst++ = + (q31_t) clip_q63_to_q31(((q63_t) (*pSrcA++) * (*pSrcB++)) >> 31); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of BasicMult group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c new file mode 100644 index 000000000..285fc04af --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c @@ -0,0 +1,125 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_mult_q7.c +* +* Description: Q7 vector multiplication. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* +* Version 0.0.5 2010/04/26 +* incorporated review comments and updated with latest CMSIS layer +* +* Version 0.0.3 2010/03/10 DP +* Initial version +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicMult + * @{ + */ + +/** + * @brief Q7 vector multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ + +void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q7_t out1, out2, out3, out4; /* Temporary variables to store the product */ + + /* loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A * B */ + /* Multiply the inputs and store the results in temporary variables */ + out1 = (q7_t) (((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7); + out2 = (q7_t) (((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7); + out3 = (q7_t) (((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7); + out4 = (q7_t) (((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7); + + /* Store the results of 4 inputs in the destination buffer in single cycle by packing */ + *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + + while(blkCnt > 0u) + { + /* C = A * B */ + /* Multiply the inputs and store the result in the destination buffer */ + *pDst++ = (q7_t) (((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of BasicMult group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c new file mode 100644 index 000000000..13deaa919 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c @@ -0,0 +1,117 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_negate_f32.c +* +* Description: Negates floating-point vectors. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* ---------------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup negate Vector Negate + * + * Negates the elements of a vector. + * + * 
   
+ *     pDst[n] = -pSrc[n],   0 <= n < blockSize.   
+ *
+ */ + +/** + * @addtogroup negate + * @{ + */ + +/** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = -A */ + /* Negate and then store the results in the destination buffer. */ + *pDst++ = -*pSrc++; + *pDst++ = -*pSrc++; + *pDst++ = -*pSrc++; + *pDst++ = -*pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = -A */ + /* Negate and then store the results in the destination buffer. */ + *pDst++ = -*pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of negate group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c new file mode 100644 index 000000000..705143191 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c @@ -0,0 +1,140 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_negate_q15.c +* +* Description: Negates Q15 vectors. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup negate + * @{ + */ + +/** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. + */ + +void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + q15_t in1, in2; /* Temporary variables */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = -A */ + /* Read two inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + /* Negate and then store the results in the destination buffer by packing. */ + +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = __PKHBT(__SSAT(-in1, 16), __SSAT(-in2, 16), 16); + +#else + + *__SIMD32(pDst)++ = __PKHBT(__SSAT(-in2, 16), __SSAT(-in1, 16), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + in1 = *pSrc++; + in2 = *pSrc++; + +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = __PKHBT(__SSAT(-in1, 16), __SSAT(-in2, 16), 16); + +#else + + + *__SIMD32(pDst)++ = __PKHBT(__SSAT(-in2, 16), __SSAT(-in1, 16), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = -A */ + /* Negate and then store the result in the destination buffer. */ + *pDst++ = __SSAT(-*pSrc++, 16); + + /* Decrement the loop counter */ + blkCnt--; + } + +} + +/** + * @} end of negate group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c new file mode 100644 index 000000000..c917a84df --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c @@ -0,0 +1,119 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_negate_q31.c +* +* Description: Negates Q31 vectors. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup negate + * @{ + */ + +/** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. + */ + +void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t in; /* Temporary variable */ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = -A */ + /* Negate and then store the results in the destination buffer. */ + in = *pSrc++; + *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in; + in = *pSrc++; + *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in; + in = *pSrc++; + *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in; + in = *pSrc++; + *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + + while(blkCnt > 0u) + { + /* C = -A */ + /* Negate and then store the result in the destination buffer. */ + in = *pSrc++; + *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of negate group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c new file mode 100644 index 000000000..ec991bd45 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_negate_q7.c +* +* Description: Negates Q7 vectors. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup negate + * @{ + */ + +/** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. + */ + +void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q7_t in1; /* Input value1 */ + q7_t in2; /* Input value2 */ + q7_t in3; /* Input value3 */ + q7_t in4; /* Input value4 */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = -A */ + /* Read four inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + /* Store the Negated results in the destination buffer in a single cycle by packing the results */ + *__SIMD32(pDst)++ = + __PACKq7(__SSAT(-in1, 8), __SSAT(-in2, 8), __SSAT(-in3, 8), + __SSAT(-in4, 8)); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = -A */ + /* Negate and then store the results in the destination buffer. */ + *pDst++ = __SSAT(-*pSrc++, 8); + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of negate group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c new file mode 100644 index 000000000..4fcbbbe94 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_offset_f32.c +* +* Description: Floating-point vector offset. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* ---------------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup offset Vector Offset + * + * Adds a constant offset to each element of a vector. + * + * 
   
+ *     pDst[n] = pSrc[n] + offset,   0 <= n < blockSize.   
+ *
+ * + * There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + * @addtogroup offset + * @{ + */ + +/** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + +void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the results in the destination buffer. */ + *pDst++ = (*pSrc++) + offset; + *pDst++ = (*pSrc++) + offset; + *pDst++ = (*pSrc++) + offset; + *pDst++ = (*pSrc++) + offset; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the result in the destination buffer. */ + *pDst++ = (*pSrc++) + offset; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of offset group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c new file mode 100644 index 000000000..a6eaa86ed --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_offset_q15.c +* +* Description: Q15 vector offset. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup offset + * @{ + */ + +/** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ + +void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t offset_packed; /* Offset packed to 32 bit */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* Offset is packed to 32 bit in order to use SIMD32 for addition */ + offset_packed = __PKHBT(offset, offset, 16); + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the results in the destination buffer, 2 samples at a time. */ + *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed); + *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the results in the destination buffer. */ + *pDst++ = (q15_t) __QADD16(*pSrc++, offset); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the results in the destination buffer. */ + *pDst++ = (q15_t) __SSAT(((q31_t) * pSrc++ + offset), 16); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of offset group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c new file mode 100644 index 000000000..dab3a774f --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_offset_q31.c +* +* Description: Q31 vector offset. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup offset + * @{ + */ + +/** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ + +void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the results in the destination buffer. */ + *pDst++ = __QADD(*pSrc++, offset); + *pDst++ = __QADD(*pSrc++, offset); + *pDst++ = __QADD(*pSrc++, offset); + *pDst++ = __QADD(*pSrc++, offset); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the result in the destination buffer. */ + *pDst++ = __QADD(*pSrc++, offset); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the result in the destination buffer. */ + *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of offset group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c new file mode 100644 index 000000000..8ed8ddd7f --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c @@ -0,0 +1,127 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_offset_q7.c +* +* Description: Q7 vector offset. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup offset + * @{ + */ + +/** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] are saturated. + */ + +void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t offset_packed; /* Offset packed to 32 bit */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* Offset is packed to 32 bit in order to use SIMD32 for addition */ + offset_packed = __PACKq7(offset, offset, offset, offset); + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the results in the destination bufferfor 4 samples at a time. */ + *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrc)++, offset_packed); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the result in the destination buffer. */ + *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the result in the destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) * pSrc++ + offset, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of offset group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c new file mode 100644 index 000000000..f51f78e84 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c @@ -0,0 +1,133 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_scale_f32.c +* +* Description: Multiplies a floating-point vector by a scalar. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* ---------------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup scale Vector Scale + * + * Multiply a vector by a scalar value. For floating-point data, the algorithm used is: + * + * 
   
+ *     pDst[n] = pSrc[n] * scale,   0 <= n < blockSize.   
+ *
+ * + * In the fixed-point Q7, Q15, and Q31 functions, scale is represented by + * a fractional multiplication scaleFract and an arithmetic shift shift. + * The shift allows the gain of the scaling operation to exceed 1.0. + * The algorithm used with fixed-point data is: + * + * 
   
+ *     pDst[n] = (pSrc[n] * scaleFract) << shift,   0 <= n < blockSize.   
+ *
+ * + * The overall scale factor applied to the fixed-point data is + * 
   
+ *     scale = scaleFract * 2^shift.   
+ *
+ */ + +/** + * @addtogroup scale + * @{ + */ + +/** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + +void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A * scale */ + /* Scale the input and then store the results in the destination buffer. */ + *pDst++ = (*pSrc++) * scale; + *pDst++ = (*pSrc++) * scale; + *pDst++ = (*pSrc++) * scale; + *pDst++ = (*pSrc++) * scale; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = A * scale */ + /* Scale the input and then store the result in the destination buffer. */ + *pDst++ = (*pSrc++) * scale; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of scale group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c new file mode 100644 index 000000000..5e4615f31 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c @@ -0,0 +1,162 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_scale_q15.c +* +* Description: Multiplies a Q15 vector by a scalar. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup scale + * @{ + */ + +/** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The input data *pSrc and scaleFract are in 1.15 format. + * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format. + */ + + +void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize) +{ + int8_t kShift = 15 - shift; /* shift to apply after scaling */ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + q15_t in1, in2; /* Temporary variables */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* Reading 2 inputs from memory */ + in1 = *pSrc++; + in2 = *pSrc++; + /* C = A * scale */ + /* Scale the inputs and then store the 2 results in the destination buffer + * in single cycle by packing the outputs */ +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = + __PKHBT(__SSAT((in1 * scaleFract) >> kShift, 16), + __SSAT((in2 * scaleFract) >> kShift, 16), 16); + +#else + + *__SIMD32(pDst)++ = + __PKHBT(__SSAT((in2 * scaleFract) >> kShift, 16), + __SSAT((in1 * scaleFract) >> kShift, 16), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + in1 = *pSrc++; + in2 = *pSrc++; + +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = + __PKHBT(__SSAT((in1 * scaleFract) >> kShift, 16), + __SSAT((in2 * scaleFract) >> kShift, 16), 16); + +#else + + *__SIMD32(pDst)++ = + __PKHBT(__SSAT((in2 * scaleFract) >> kShift, 16), + __SSAT((in1 * scaleFract) >> kShift, 16), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A * scale */ + /* Scale the input and then store the result in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 16)); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A * scale */ + /* Scale the input and then store the result in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT(((q31_t) * pSrc++ * scaleFract) >> kShift, 16)); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of scale group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c new file mode 100644 index 000000000..1b2b7de7f --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c @@ -0,0 +1,117 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_scale_q31.c +* +* Description: Multiplies a Q31 vector by a scalar. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup scale + * @{ + */ + +/** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The input data *pSrc and scaleFract are in 1.31 format. + * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format. + */ + +void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize) +{ + int8_t kShift = 31 - shift; /* Shift to apply after scaling */ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A * scale */ + /* Scale the input and then store the results in the destination buffer. */ + *pDst++ = clip_q63_to_q31(((q63_t) * pSrc++ * scaleFract) >> kShift); + *pDst++ = clip_q63_to_q31(((q63_t) * pSrc++ * scaleFract) >> kShift); + *pDst++ = clip_q63_to_q31(((q63_t) * pSrc++ * scaleFract) >> kShift); + *pDst++ = clip_q63_to_q31(((q63_t) * pSrc++ * scaleFract) >> kShift); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = A * scale */ + /* Scale the input and then store the result in the destination buffer. */ + *pDst++ = clip_q63_to_q31(((q63_t) * pSrc++ * scaleFract) >> kShift); + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of scale group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c new file mode 100644 index 000000000..f058b0e9c --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c @@ -0,0 +1,141 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_scale_q7.c +* +* Description: Multiplies a Q7 vector by a scalar. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup scale + * @{ + */ + +/** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The input data *pSrc and scaleFract are in 1.7 format. + * These are multiplied to yield a 2.14 intermediate result and this is shifted with saturation to 1.7 format. + */ + +void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize) +{ + int8_t kShift = 7 - shift; /* shift to apply after scaling */ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q7_t in1, in2, in3, in4, out1, out2, out3, out4; /* Temporary variables to store input & output */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* Reading 4 inputs from memory */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + /* C = A * scale */ + /* Scale the inputs and then store the results in the temporary variables. */ + out1 = (q7_t) (__SSAT(((in1) * scaleFract) >> kShift, 8)); + out2 = (q7_t) (__SSAT(((in2) * scaleFract) >> kShift, 8)); + out3 = (q7_t) (__SSAT(((in3) * scaleFract) >> kShift, 8)); + out4 = (q7_t) (__SSAT(((in4) * scaleFract) >> kShift, 8)); + + /* Packing the individual outputs into 32bit and storing in + * destination buffer in single write */ + *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A * scale */ + /* Scale the input and then store the result in the destination buffer. */ + *pDst++ = (q7_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 8)); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A * scale */ + /* Scale the input and then store the result in the destination buffer. */ + *pDst++ = (q7_t) (__SSAT((((q15_t) * pSrc++ * scaleFract) >> kShift), 8)); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of scale group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c new file mode 100644 index 000000000..70a80c2f7 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c @@ -0,0 +1,239 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_shift_q15.c +* +* Description: Shifts the elements of a Q15 vector by a specified number of bits. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup shift + * @{ + */ + +/** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + uint8_t sign; /* Sign of shiftBits */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + q15_t in1, in2; /* Temporary variables */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* Getting the sign of shiftBits */ + sign = (shiftBits & 0x80); + + /* If the shift value is positive then do right shift else left shift */ + if(sign == 0u) + { + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* Read 2 inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + /* C = A << shiftBits */ + /* Shift the inputs and then store the results in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16), + __SSAT((in2 << shiftBits), 16), 16); + +#else + + *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16), + __SSAT((in1 << shiftBits), 16), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + in1 = *pSrc++; + in2 = *pSrc++; + +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16), + __SSAT((in2 << shiftBits), 16), 16); + +#else + + *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16), + __SSAT((in1 << shiftBits), 16), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A << shiftBits */ + /* Shift and then store the results in the destination buffer. */ + *pDst++ = __SSAT((*pSrc++ << shiftBits), 16); + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* Read 2 inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + /* C = A >> shiftBits */ + /* Shift the inputs and then store the results in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits), + (in2 >> -shiftBits), 16); + +#else + + *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits), + (in1 >> -shiftBits), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + in1 = *pSrc++; + in2 = *pSrc++; + +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits), + (in2 >> -shiftBits), 16); + +#else + + *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits), + (in1 >> -shiftBits), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A >> shiftBits */ + /* Shift the inputs and then store the results in the destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement the loop counter */ + blkCnt--; + } + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Getting the sign of shiftBits */ + sign = (shiftBits & 0x80); + + /* If the shift value is positive then do right shift else left shift */ + if(sign == 0u) + { + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A << shiftBits */ + /* Shift and then store the results in the destination buffer. */ + *pDst++ = __SSAT(((q31_t) * pSrc++ << shiftBits), 16); + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A >> shiftBits */ + /* Shift the inputs and then store the results in the destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement the loop counter */ + blkCnt--; + } + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of shift group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c new file mode 100644 index 000000000..81f45bd1a --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c @@ -0,0 +1,141 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_shift_q31.c +* +* Description: Shifts the elements of a Q31 vector by a specified number of bits. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ +/** + * @defgroup shift Vector Shift + * + * Shifts the elements of a fixed-point vector by a specified number of bits. + * There are separate functions for Q7, Q15, and Q31 data types. + * The underlying algorithm used is: + * + * 
   
+ *     pDst[n] = pSrc[n] << shift,   0 <= n < blockSize.   
+ *
+ * + * If shift is positive then the elements of the vector are shifted to the left. + * If shift is negative then the elements of the vector are shifted to the right. + */ + +/** + * @addtogroup shift + * @{ + */ + +/** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. + */ + +void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + uint8_t sign; /* Sign of shiftBits */ + /* Getting the sign of shiftBits */ + sign = (shiftBits & 0x80); + + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A (>> or <<) shiftBits */ + /* Shift the input and then store the results in the destination buffer. */ + *pDst++ = (sign == 0u) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) : + (*pSrc++ >> -shiftBits); + *pDst++ = (sign == 0u) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) : + (*pSrc++ >> -shiftBits); + *pDst++ = (sign == 0u) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) : + (*pSrc++ >> -shiftBits); + *pDst++ = (sign == 0u) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) : + (*pSrc++ >> -shiftBits); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + + while(blkCnt > 0u) + { + /* C = A (>> or <<) shiftBits */ + /* Shift the input and then store the result in the destination buffer. */ + *pDst++ = (sign == 0u) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) : + (*pSrc++ >> -shiftBits); + + /* Decrement the loop counter */ + blkCnt--; + } + +} + +/** + * @} end of shift group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c new file mode 100644 index 000000000..cf13ef3ab --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c @@ -0,0 +1,202 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_shift_q7.c +* +* Description: Processing function for the Q7 Shifting +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup shift + * @{ + */ + + +/** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x8 0x7F] will be saturated. + */ + +void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + uint8_t sign; /* Sign of shiftBits */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q7_t in1; /* Input value1 */ + q7_t in2; /* Input value2 */ + q7_t in3; /* Input value3 */ + q7_t in4; /* Input value4 */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* Getting the sign of shiftBits */ + sign = (shiftBits & 0x80); + + /* If the shift value is positive then do right shift else left shift */ + if(sign == 0u) + { + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A << shiftBits */ + /* Read 4 inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */ + *__SIMD32(pDst)++ = __PACKq7(__SSAT((in1 << shiftBits), 8), + __SSAT((in2 << shiftBits), 8), + __SSAT((in3 << shiftBits), 8), + __SSAT((in4 << shiftBits), 8)); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A << shiftBits */ + /* Shift the input and then store the result in the destination buffer. */ + *pDst++ = (q7_t) __SSAT((*pSrc++ << shiftBits), 8); + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A >> shiftBits */ + /* Read 4 inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */ + *__SIMD32(pDst)++ = __PACKq7((in1 >> -shiftBits), (in2 >> -shiftBits), + (in3 >> -shiftBits), (in4 >> -shiftBits)); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A >> shiftBits */ + /* Shift the input and then store the result in the destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement the loop counter */ + blkCnt--; + } + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Getting the sign of shiftBits */ + sign = (shiftBits & 0x80); + + /* If the shift value is positive then do right shift else left shift */ + if(sign == 0u) + { + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A << shiftBits */ + /* Shift the input and then store the result in the destination buffer. */ + *pDst++ = (q7_t) __SSAT(((q15_t) * pSrc++ << shiftBits), 8); + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A >> shiftBits */ + /* Shift the input and then store the result in the destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement the loop counter */ + blkCnt--; + } + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of shift group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c new file mode 100644 index 000000000..3ec5c7431 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_sub_f32.c +* +* Description: Floating-point vector subtraction. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* ---------------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup BasicSub Vector Subtraction + * + * Element-by-element subtraction of two vectors. + * + * 
   
+ *     pDst[n] = pSrcA[n] - pSrcB[n],   0 <= n < blockSize.   
+ *
+ * + * There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + * @addtogroup BasicSub + * @{ + */ + + +/** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the results in the destination buffer. */ + *pDst++ = (*pSrcA++) - (*pSrcB++); + *pDst++ = (*pSrcA++) - (*pSrcB++); + *pDst++ = (*pSrcA++) - (*pSrcB++); + *pDst++ = (*pSrcA++) - (*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the results in the destination buffer. */ + *pDst++ = (*pSrcA++) - (*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of BasicSub group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c new file mode 100644 index 000000000..6d170e25d --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c @@ -0,0 +1,124 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_sub_q15.c +* +* Description: Q15 vector subtraction. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicSub + * @{ + */ + +/** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the results in the destination buffer two samples at a time. */ + *__SIMD32(pDst)++ = __QSUB16(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++); + *__SIMD32(pDst)++ = __QSUB16(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the result in the destination buffer. */ + *pDst++ = (q15_t) __QSUB16(*pSrcA++, *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the result in the destination buffer. */ + *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ - *pSrcB++), 16); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + + +} + +/** + * @} end of BasicSub group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c new file mode 100644 index 000000000..489a28f3a --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c @@ -0,0 +1,125 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_sub_q31.c +* +* Description: Q31 vector subtraction. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicSub + * @{ + */ + +/** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. + */ + +void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the results in the destination buffer. */ + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the result in the destination buffer. */ + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the result in the destination buffer. */ + *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ - *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of BasicSub group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c new file mode 100644 index 000000000..f1bb2c6fa --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c @@ -0,0 +1,123 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_sub_q7.c +* +* Description: Q7 vector subtraction. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicSub + * @{ + */ + +/** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ + +void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the results in the destination buffer 4 samples at a time. */ + *__SIMD32(pDst)++ = __QSUB8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the result in the destination buffer. */ + *pDst++ = __SSAT(*pSrcA++ - *pSrcB++, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the result in the destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ - *pSrcB++, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + + +} + +/** + * @} end of BasicSub group + */ diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c new file mode 100644 index 000000000..619315848 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c @@ -0,0 +1,257 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2011 ARM Limited. All rights reserved. +* +* $Date: 17. August 2011 +* $Revision: V1.0.11 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.c +* +* Description: This file has common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.11 2011/08/17 +* Updated Bit Reversal table to support 4096 CFFT length. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +/** + * @ingroup groupTransforms + */ + +/** + * @addtogroup CFFT_CIFFT + * @{ + */ + +/** +* \par +* Pseudo code for Generation of Bit reversal Table is +* \par +* 
for(l=1;l <= N/4;l++)   
+* {   
+*   for(i=0;i> 1;   
+*  }
+* \par +* where N = 1024 logN2 = 10 +* \par +* N is the maximum FFT Size supported +*/ + +/* +* @brief Table for bit reversal process +*/ +uint16_t armBitRevTable[1024] = { + 0x400, 0x200, 0x600, 0x100, 0x500, 0x300, 0x700, +0x80, 0x480, 0x280, 0x680, 0x180, 0x580, 0x380, +0x780, 0x40, 0x440, 0x240, 0x640, 0x140, 0x540, +0x340, 0x740, 0xc0, 0x4c0, 0x2c0, 0x6c0, 0x1c0, +0x5c0, 0x3c0, 0x7c0, 0x20, 0x420, 0x220, 0x620, +0x120, 0x520, 0x320, 0x720, 0xa0, 0x4a0, 0x2a0, +0x6a0, 0x1a0, 0x5a0, 0x3a0, 0x7a0, 0x60, 0x460, +0x260, 0x660, 0x160, 0x560, 0x360, 0x760, 0xe0, +0x4e0, 0x2e0, 0x6e0, 0x1e0, 0x5e0, 0x3e0, 0x7e0, +0x10, 0x410, 0x210, 0x610, 0x110, 0x510, 0x310, +0x710, 0x90, 0x490, 0x290, 0x690, 0x190, 0x590, +0x390, 0x790, 0x50, 0x450, 0x250, 0x650, 0x150, +0x550, 0x350, 0x750, 0xd0, 0x4d0, 0x2d0, 0x6d0, +0x1d0, 0x5d0, 0x3d0, 0x7d0, 0x30, 0x430, 0x230, +0x630, 0x130, 0x530, 0x330, 0x730, 0xb0, 0x4b0, +0x2b0, 0x6b0, 0x1b0, 0x5b0, 0x3b0, 0x7b0, 0x70, +0x470, 0x270, 0x670, 0x170, 0x570, 0x370, 0x770, +0xf0, 0x4f0, 0x2f0, 0x6f0, 0x1f0, 0x5f0, 0x3f0, +0x7f0, 0x8, 0x408, 0x208, 0x608, 0x108, 0x508, +0x308, 0x708, 0x88, 0x488, 0x288, 0x688, 0x188, +0x588, 0x388, 0x788, 0x48, 0x448, 0x248, 0x648, +0x148, 0x548, 0x348, 0x748, 0xc8, 0x4c8, 0x2c8, +0x6c8, 0x1c8, 0x5c8, 0x3c8, 0x7c8, 0x28, 0x428, +0x228, 0x628, 0x128, 0x528, 0x328, 0x728, 0xa8, +0x4a8, 0x2a8, 0x6a8, 0x1a8, 0x5a8, 0x3a8, 0x7a8, +0x68, 0x468, 0x268, 0x668, 0x168, 0x568, 0x368, +0x768, 0xe8, 0x4e8, 0x2e8, 0x6e8, 0x1e8, 0x5e8, +0x3e8, 0x7e8, 0x18, 0x418, 0x218, 0x618, 0x118, +0x518, 0x318, 0x718, 0x98, 0x498, 0x298, 0x698, +0x198, 0x598, 0x398, 0x798, 0x58, 0x458, 0x258, +0x658, 0x158, 0x558, 0x358, 0x758, 0xd8, 0x4d8, +0x2d8, 0x6d8, 0x1d8, 0x5d8, 0x3d8, 0x7d8, 0x38, +0x438, 0x238, 0x638, 0x138, 0x538, 0x338, 0x738, +0xb8, 0x4b8, 0x2b8, 0x6b8, 0x1b8, 0x5b8, 0x3b8, +0x7b8, 0x78, 0x478, 0x278, 0x678, 0x178, 0x578, +0x378, 0x778, 0xf8, 0x4f8, 0x2f8, 0x6f8, 0x1f8, +0x5f8, 0x3f8, 0x7f8, 0x4, 0x404, 0x204, 0x604, +0x104, 0x504, 0x304, 0x704, 0x84, 0x484, 0x284, +0x684, 0x184, 0x584, 0x384, 0x784, 0x44, 0x444, +0x244, 0x644, 0x144, 0x544, 0x344, 0x744, 0xc4, +0x4c4, 0x2c4, 0x6c4, 0x1c4, 0x5c4, 0x3c4, 0x7c4, +0x24, 0x424, 0x224, 0x624, 0x124, 0x524, 0x324, +0x724, 0xa4, 0x4a4, 0x2a4, 0x6a4, 0x1a4, 0x5a4, +0x3a4, 0x7a4, 0x64, 0x464, 0x264, 0x664, 0x164, +0x564, 0x364, 0x764, 0xe4, 0x4e4, 0x2e4, 0x6e4, +0x1e4, 0x5e4, 0x3e4, 0x7e4, 0x14, 0x414, 0x214, +0x614, 0x114, 0x514, 0x314, 0x714, 0x94, 0x494, +0x294, 0x694, 0x194, 0x594, 0x394, 0x794, 0x54, +0x454, 0x254, 0x654, 0x154, 0x554, 0x354, 0x754, +0xd4, 0x4d4, 0x2d4, 0x6d4, 0x1d4, 0x5d4, 0x3d4, +0x7d4, 0x34, 0x434, 0x234, 0x634, 0x134, 0x534, +0x334, 0x734, 0xb4, 0x4b4, 0x2b4, 0x6b4, 0x1b4, +0x5b4, 0x3b4, 0x7b4, 0x74, 0x474, 0x274, 0x674, +0x174, 0x574, 0x374, 0x774, 0xf4, 0x4f4, 0x2f4, +0x6f4, 0x1f4, 0x5f4, 0x3f4, 0x7f4, 0xc, 0x40c, +0x20c, 0x60c, 0x10c, 0x50c, 0x30c, 0x70c, 0x8c, +0x48c, 0x28c, 0x68c, 0x18c, 0x58c, 0x38c, 0x78c, +0x4c, 0x44c, 0x24c, 0x64c, 0x14c, 0x54c, 0x34c, +0x74c, 0xcc, 0x4cc, 0x2cc, 0x6cc, 0x1cc, 0x5cc, +0x3cc, 0x7cc, 0x2c, 0x42c, 0x22c, 0x62c, 0x12c, +0x52c, 0x32c, 0x72c, 0xac, 0x4ac, 0x2ac, 0x6ac, +0x1ac, 0x5ac, 0x3ac, 0x7ac, 0x6c, 0x46c, 0x26c, +0x66c, 0x16c, 0x56c, 0x36c, 0x76c, 0xec, 0x4ec, +0x2ec, 0x6ec, 0x1ec, 0x5ec, 0x3ec, 0x7ec, 0x1c, +0x41c, 0x21c, 0x61c, 0x11c, 0x51c, 0x31c, 0x71c, +0x9c, 0x49c, 0x29c, 0x69c, 0x19c, 0x59c, 0x39c, +0x79c, 0x5c, 0x45c, 0x25c, 0x65c, 0x15c, 0x55c, +0x35c, 0x75c, 0xdc, 0x4dc, 0x2dc, 0x6dc, 0x1dc, +0x5dc, 0x3dc, 0x7dc, 0x3c, 0x43c, 0x23c, 0x63c, +0x13c, 0x53c, 0x33c, 0x73c, 0xbc, 0x4bc, 0x2bc, +0x6bc, 0x1bc, 0x5bc, 0x3bc, 0x7bc, 0x7c, 0x47c, +0x27c, 0x67c, 0x17c, 0x57c, 0x37c, 0x77c, 0xfc, +0x4fc, 0x2fc, 0x6fc, 0x1fc, 0x5fc, 0x3fc, 0x7fc, +0x2, 0x402, 0x202, 0x602, 0x102, 0x502, 0x302, +0x702, 0x82, 0x482, 0x282, 0x682, 0x182, 0x582, +0x382, 0x782, 0x42, 0x442, 0x242, 0x642, 0x142, +0x542, 0x342, 0x742, 0xc2, 0x4c2, 0x2c2, 0x6c2, +0x1c2, 0x5c2, 0x3c2, 0x7c2, 0x22, 0x422, 0x222, +0x622, 0x122, 0x522, 0x322, 0x722, 0xa2, 0x4a2, +0x2a2, 0x6a2, 0x1a2, 0x5a2, 0x3a2, 0x7a2, 0x62, +0x462, 0x262, 0x662, 0x162, 0x562, 0x362, 0x762, +0xe2, 0x4e2, 0x2e2, 0x6e2, 0x1e2, 0x5e2, 0x3e2, +0x7e2, 0x12, 0x412, 0x212, 0x612, 0x112, 0x512, +0x312, 0x712, 0x92, 0x492, 0x292, 0x692, 0x192, +0x592, 0x392, 0x792, 0x52, 0x452, 0x252, 0x652, +0x152, 0x552, 0x352, 0x752, 0xd2, 0x4d2, 0x2d2, +0x6d2, 0x1d2, 0x5d2, 0x3d2, 0x7d2, 0x32, 0x432, +0x232, 0x632, 0x132, 0x532, 0x332, 0x732, 0xb2, +0x4b2, 0x2b2, 0x6b2, 0x1b2, 0x5b2, 0x3b2, 0x7b2, +0x72, 0x472, 0x272, 0x672, 0x172, 0x572, 0x372, +0x772, 0xf2, 0x4f2, 0x2f2, 0x6f2, 0x1f2, 0x5f2, +0x3f2, 0x7f2, 0xa, 0x40a, 0x20a, 0x60a, 0x10a, +0x50a, 0x30a, 0x70a, 0x8a, 0x48a, 0x28a, 0x68a, +0x18a, 0x58a, 0x38a, 0x78a, 0x4a, 0x44a, 0x24a, +0x64a, 0x14a, 0x54a, 0x34a, 0x74a, 0xca, 0x4ca, +0x2ca, 0x6ca, 0x1ca, 0x5ca, 0x3ca, 0x7ca, 0x2a, +0x42a, 0x22a, 0x62a, 0x12a, 0x52a, 0x32a, 0x72a, +0xaa, 0x4aa, 0x2aa, 0x6aa, 0x1aa, 0x5aa, 0x3aa, +0x7aa, 0x6a, 0x46a, 0x26a, 0x66a, 0x16a, 0x56a, +0x36a, 0x76a, 0xea, 0x4ea, 0x2ea, 0x6ea, 0x1ea, +0x5ea, 0x3ea, 0x7ea, 0x1a, 0x41a, 0x21a, 0x61a, +0x11a, 0x51a, 0x31a, 0x71a, 0x9a, 0x49a, 0x29a, +0x69a, 0x19a, 0x59a, 0x39a, 0x79a, 0x5a, 0x45a, +0x25a, 0x65a, 0x15a, 0x55a, 0x35a, 0x75a, 0xda, +0x4da, 0x2da, 0x6da, 0x1da, 0x5da, 0x3da, 0x7da, +0x3a, 0x43a, 0x23a, 0x63a, 0x13a, 0x53a, 0x33a, +0x73a, 0xba, 0x4ba, 0x2ba, 0x6ba, 0x1ba, 0x5ba, +0x3ba, 0x7ba, 0x7a, 0x47a, 0x27a, 0x67a, 0x17a, +0x57a, 0x37a, 0x77a, 0xfa, 0x4fa, 0x2fa, 0x6fa, +0x1fa, 0x5fa, 0x3fa, 0x7fa, 0x6, 0x406, 0x206, +0x606, 0x106, 0x506, 0x306, 0x706, 0x86, 0x486, +0x286, 0x686, 0x186, 0x586, 0x386, 0x786, 0x46, +0x446, 0x246, 0x646, 0x146, 0x546, 0x346, 0x746, +0xc6, 0x4c6, 0x2c6, 0x6c6, 0x1c6, 0x5c6, 0x3c6, +0x7c6, 0x26, 0x426, 0x226, 0x626, 0x126, 0x526, +0x326, 0x726, 0xa6, 0x4a6, 0x2a6, 0x6a6, 0x1a6, +0x5a6, 0x3a6, 0x7a6, 0x66, 0x466, 0x266, 0x666, +0x166, 0x566, 0x366, 0x766, 0xe6, 0x4e6, 0x2e6, +0x6e6, 0x1e6, 0x5e6, 0x3e6, 0x7e6, 0x16, 0x416, +0x216, 0x616, 0x116, 0x516, 0x316, 0x716, 0x96, +0x496, 0x296, 0x696, 0x196, 0x596, 0x396, 0x796, +0x56, 0x456, 0x256, 0x656, 0x156, 0x556, 0x356, +0x756, 0xd6, 0x4d6, 0x2d6, 0x6d6, 0x1d6, 0x5d6, +0x3d6, 0x7d6, 0x36, 0x436, 0x236, 0x636, 0x136, +0x536, 0x336, 0x736, 0xb6, 0x4b6, 0x2b6, 0x6b6, +0x1b6, 0x5b6, 0x3b6, 0x7b6, 0x76, 0x476, 0x276, +0x676, 0x176, 0x576, 0x376, 0x776, 0xf6, 0x4f6, +0x2f6, 0x6f6, 0x1f6, 0x5f6, 0x3f6, 0x7f6, 0xe, +0x40e, 0x20e, 0x60e, 0x10e, 0x50e, 0x30e, 0x70e, +0x8e, 0x48e, 0x28e, 0x68e, 0x18e, 0x58e, 0x38e, +0x78e, 0x4e, 0x44e, 0x24e, 0x64e, 0x14e, 0x54e, +0x34e, 0x74e, 0xce, 0x4ce, 0x2ce, 0x6ce, 0x1ce, +0x5ce, 0x3ce, 0x7ce, 0x2e, 0x42e, 0x22e, 0x62e, +0x12e, 0x52e, 0x32e, 0x72e, 0xae, 0x4ae, 0x2ae, +0x6ae, 0x1ae, 0x5ae, 0x3ae, 0x7ae, 0x6e, 0x46e, +0x26e, 0x66e, 0x16e, 0x56e, 0x36e, 0x76e, 0xee, +0x4ee, 0x2ee, 0x6ee, 0x1ee, 0x5ee, 0x3ee, 0x7ee, +0x1e, 0x41e, 0x21e, 0x61e, 0x11e, 0x51e, 0x31e, +0x71e, 0x9e, 0x49e, 0x29e, 0x69e, 0x19e, 0x59e, +0x39e, 0x79e, 0x5e, 0x45e, 0x25e, 0x65e, 0x15e, +0x55e, 0x35e, 0x75e, 0xde, 0x4de, 0x2de, 0x6de, +0x1de, 0x5de, 0x3de, 0x7de, 0x3e, 0x43e, 0x23e, +0x63e, 0x13e, 0x53e, 0x33e, 0x73e, 0xbe, 0x4be, +0x2be, 0x6be, 0x1be, 0x5be, 0x3be, 0x7be, 0x7e, +0x47e, 0x27e, 0x67e, 0x17e, 0x57e, 0x37e, 0x77e, +0xfe, 0x4fe, 0x2fe, 0x6fe, 0x1fe, 0x5fe, 0x3fe, +0x7fe, 0x1 +}; + +/** + * @} end of CFFT_CIFFT group + */ + +/* +* @brief Q15 table for reciprocal +*/ +const q15_t armRecipTableQ15[64] = { + 0x7F03, 0x7D13, 0x7B31, 0x795E, 0x7798, 0x75E0, + 0x7434, 0x7294, 0x70FF, 0x6F76, 0x6DF6, 0x6C82, + 0x6B16, 0x69B5, 0x685C, 0x670C, 0x65C4, 0x6484, + 0x634C, 0x621C, 0x60F3, 0x5FD0, 0x5EB5, 0x5DA0, + 0x5C91, 0x5B88, 0x5A85, 0x5988, 0x5890, 0x579E, + 0x56B0, 0x55C8, 0x54E4, 0x5405, 0x532B, 0x5255, + 0x5183, 0x50B6, 0x4FEC, 0x4F26, 0x4E64, 0x4DA6, + 0x4CEC, 0x4C34, 0x4B81, 0x4AD0, 0x4A23, 0x4978, + 0x48D1, 0x482D, 0x478C, 0x46ED, 0x4651, 0x45B8, + 0x4521, 0x448D, 0x43FC, 0x436C, 0x42DF, 0x4255, + 0x41CC, 0x4146, 0x40C2, 0x4040 +}; + +/* +* @brief Q31 table for reciprocal +*/ +const q31_t armRecipTableQ31[64] = { + 0x7F03F03F, 0x7D137420, 0x7B31E739, 0x795E9F94, 0x7798FD29, 0x75E06928, + 0x7434554D, 0x72943B4B, 0x70FF9C40, 0x6F760031, 0x6DF6F593, 0x6C8210E3, + 0x6B16EC3A, 0x69B526F6, 0x685C655F, 0x670C505D, 0x65C4952D, 0x6484E519, + 0x634CF53E, 0x621C7E4F, 0x60F33C61, 0x5FD0EEB3, 0x5EB55785, 0x5DA03BEB, + 0x5C9163A1, 0x5B8898E6, 0x5A85A85A, 0x598860DF, 0x58909373, 0x579E1318, + 0x56B0B4B8, 0x55C84F0B, 0x54E4BA80, 0x5405D124, 0x532B6E8F, 0x52556FD0, + 0x5183B35A, 0x50B618F3, 0x4FEC81A2, 0x4F26CFA2, 0x4E64E64E, 0x4DA6AA1D, + 0x4CEC008B, 0x4C34D010, 0x4B810016, 0x4AD078EF, 0x4A2323C4, 0x4978EA96, + 0x48D1B827, 0x482D77FE, 0x478C1657, 0x46ED801D, 0x4651A2E5, 0x45B86CE2, + 0x4521CCE1, 0x448DB244, 0x43FC0CFA, 0x436CCD78, 0x42DFE4B4, 0x42554426, + 0x41CCDDB6, 0x4146A3C6, 0x40C28923, 0x40408102 +}; diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c new file mode 100644 index 000000000..4623357b7 --- /dev/null +++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c @@ -0,0 +1,141 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_cmplx_conj_f32.c +* +* Description: Floating-point complex conjugate. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* ---------------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupCmplxMath + */ + +/** + * @defgroup cmplx_conj Complex Conjugate + * + * Conjugates the elements of a complex data vector. + * + * The pSrc points to the source data and + * pDst points to the where the result should be written. + * numSamples specifies the number of complex samples + * and the data in each array is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * Each array has a total of 2*numSamples values. + * The underlying algorithm is used: + * + * 
   
+ * for(n=0; n   
+ *   
+ * There are separate functions for floating-point, Q15, and Q31 data types.   
+ */
+
+/**   
+ * @addtogroup cmplx_conj   
+ * @{   
+ */
+
+/**   
+ * @brief  Floating-point complex conjugate.   
+ * @param  *pSrc points to the input vector   
+ * @param  *pDst points to the output vector   
+ * @param  numSamples number of complex samples in each vector   
+ * @return none.   
+ */
+
+void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* realOut + j (imagOut) = realIn + j (-1) imagIn */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_conj group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
new file mode 100644
index 000000000..5c4c389f1
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
@@ -0,0 +1,123 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_conj_q15.c   
+*   
+* Description:	Q15 complex conjugate.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup cmplx_conj   
+ * @{   
+ */
+
+/**   
+ * @brief  Q15 complex conjugate.   
+ * @param  *pSrc points to the input vector   
+ * @param  *pDst points to the output vector   
+ * @param  numSamples number of complex samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.   
+ */
+
+void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = __SSAT(-*pSrc++, 16);
+    *pDst++ = *pSrc++;
+    *pDst++ = __SSAT(-*pSrc++, 16);
+    *pDst++ = *pSrc++;
+    *pDst++ = __SSAT(-*pSrc++, 16);
+    *pDst++ = *pSrc++;
+    *pDst++ = __SSAT(-*pSrc++, 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = __SSAT(-*pSrc++, 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* realOut + j (imagOut) = realIn+ j (-1) imagIn */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_conj group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
new file mode 100644
index 000000000..b139ea25f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
@@ -0,0 +1,131 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_conj_q31.c   
+*   
+* Description:	Q31 complex conjugate.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup cmplx_conj   
+ * @{   
+ */
+
+/**   
+ * @brief  Q31 complex conjugate.   
+ * @param  *pSrc points to the input vector   
+ * @param  *pDst points to the output vector   
+ * @param  numSamples number of complex samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.   
+ */
+
+void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+  q31_t in;                                      /* Input value */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
+    *pDst++ = *pSrc++;
+    in = *pSrc++;
+    *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in;
+    *pDst++ = *pSrc++;
+    in = *pSrc++;
+    *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in;
+    *pDst++ = *pSrc++;
+    in = *pSrc++;
+    *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in;
+    *pDst++ = *pSrc++;
+    in = *pSrc++;
+    *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
+    *pDst++ = *pSrc++;
+    in = *pSrc++;
+    *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* realOut + j (imagOut) = realIn+ j (-1) imagIn */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_conj group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
new file mode 100644
index 000000000..90b8a8b34
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
@@ -0,0 +1,157 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_dot_prod_f32.c   
+*   
+* Description:	Floating-point complex dot product   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @defgroup cmplx_dot_prod Complex Dot Product   
+ *   
+ * Computes the dot product of two complex vectors.   
+ * The vectors are multiplied element-by-element and then summed.   
+ *  
+ * The pSrcA points to the first complex input vector and   
+ * pSrcB points to the second complex input vector.   
+ * numSamples specifies the number of complex samples   
+ * and the data in each array is stored in an interleaved fashion   
+ * (real, imag, real, imag, ...).   
+ * Each array has a total of 2*numSamples values.   
+ *   
+ * The underlying algorithm is used:   
+ * 
   
+ * realResult=0;   
+ * imagResult=0;   
+ * for(n=0; n   
+ *   
+ * There are separate functions for floating-point, Q15, and Q31 data types.   
+ */
+
+/**   
+ * @addtogroup cmplx_dot_prod   
+ * @{   
+ */
+
+/**   
+ * @brief  Floating-point complex dot product   
+ * @param  *pSrcA points to the first input vector   
+ * @param  *pSrcB points to the second input vector   
+ * @param  numSamples number of complex samples in each vector   
+ * @param  *realResult real part of the result returned here   
+ * @param  *imagResult imaginary part of the result returned here   
+ * @return none.   
+ */
+
+void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult)
+{
+  float32_t real_sum = 0.0f, imag_sum = 0.0f;    /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += (*pSrcA++) * (*pSrcB++);
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += (*pSrcA++) * (*pSrcB++);
+
+    real_sum += (*pSrcA++) * (*pSrcB++);
+    imag_sum += (*pSrcA++) * (*pSrcB++);
+
+    real_sum += (*pSrcA++) * (*pSrcB++);
+    imag_sum += (*pSrcA++) * (*pSrcB++);
+
+    real_sum += (*pSrcA++) * (*pSrcB++);
+    imag_sum += (*pSrcA++) * (*pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += (*pSrcA++) * (*pSrcB++);
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += (*pSrcA++) * (*pSrcB++);
+
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += (*pSrcA++) * (*pSrcB++);
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += (*pSrcA++) * (*pSrcB++);
+
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Store the real and imaginary results in the destination buffers */
+  *realResult = real_sum;
+  *imagResult = imag_sum;
+}
+
+/**   
+ * @} end of cmplx_dot_prod group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
new file mode 100644
index 000000000..2e341bffd
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
@@ -0,0 +1,141 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_dot_prod_q15.c   
+*   
+* Description:	Processing function for the Q15 Complex Dot product   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup cmplx_dot_prod   
+ * @{   
+ */
+
+/**   
+ * @brief  Q15 complex dot product   
+ * @param  *pSrcA points to the first input vector   
+ * @param  *pSrcB points to the second input vector   
+ * @param  numSamples number of complex samples in each vector   
+ * @param  *realResult real part of the result returned here   
+ * @param  *imagResult imaginary part of the result returned here   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The intermediate 1.15 by 1.15 multiplications are performed with full precision and yield a 2.30 result.   
+ * These are accumulated in a 64-bit accumulator with 34.30 precision.   
+ * As a final step, the accumulators are converted to 8.24 format.   
+ * The return results realResult and imagResult are in 8.24 format.   
+ */
+
+void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult)
+{
+  q63_t real_sum = 0, imag_sum = 0;              /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Store the real and imaginary results in 8.24 format  */
+  /* Convert real data in 34.30 to 8.24 by 6 right shifts */
+  *realResult = (q31_t) (real_sum) >> 6;
+  /* Convert imaginary data in 34.30 to 8.24 by 6 right shifts */
+  *imagResult = (q31_t) (imag_sum) >> 6;
+}
+
+/**   
+ * @} end of cmplx_dot_prod group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
new file mode 100644
index 000000000..30ee59c7e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
@@ -0,0 +1,142 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_dot_prod_q31.c   
+*   
+* Description:	Q31 complex dot product   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup cmplx_dot_prod   
+ * @{   
+ */
+
+/**   
+ * @brief  Q31 complex dot product   
+ * @param  *pSrcA points to the first input vector   
+ * @param  *pSrcB points to the second input vector   
+ * @param  numSamples number of complex samples in each vector   
+ * @param  *realResult real part of the result returned here   
+ * @param  *imagResult imaginary part of the result returned here   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format.   
+ * The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits.   
+ * Additions are nonsaturating and no overflow will occur as long as numSamples is less than 32768.   
+ * The return results realResult and imagResult are in 16.48 format.   
+ * Input down scaling is not required.   
+ */
+
+void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult)
+{
+  q63_t real_sum = 0, imag_sum = 0;              /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    /* Convert real data in 2.62 to 16.48 by 14 right shifts */
+    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    /* Convert imag data in 2.62 to 16.48 by 14 right shifts */
+    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples  is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* outReal = realA[0]* realB[0] + realA[2]* realB[2] + realA[4]* realB[4] + .....+ realA[numSamples-2]* realB[numSamples-2] */
+    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+    /* outImag = imagA[1]* imagB[1] + imagA[3]* imagB[3] + imagA[5]* imagB[5] + .....+ imagA[numSamples-1]* imagB[numSamples-1] */
+    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Store the real and imaginary results in 16.48 format  */
+  *realResult = real_sum;
+  *imagResult = imag_sum;
+}
+
+/**   
+ * @} end of cmplx_dot_prod group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
new file mode 100644
index 000000000..e84195ec1
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
@@ -0,0 +1,154 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_mag_f32.c   
+*   
+* Description:	Floating-point complex magnitude.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @defgroup cmplx_mag Complex Magnitude   
+ *   
+ * Computes the magnitude of the elements of a complex data vector.   
+ *  
+ * The pSrc points to the source data and   
+ * pDst points to the where the result should be written.   
+ * numSamples specifies the number of complex samples   
+ * in the input array and the data is stored in an interleaved fashion   
+ * (real, imag, real, imag, ...).   
+ * The input array has a total of 2*numSamples values;   
+ * the output array has a total of numSamples values.   
+ * The underlying algorithm is used:   
+ *   
+ * 
   
+ * for(n=0; n   
+ *   
+ * There are separate functions for floating-point, Q15, and Q31 data types.   
+ */
+
+/**   
+ * @addtogroup cmplx_mag   
+ * @{   
+ */
+/**   
+ * @brief Floating-point complex magnitude.   
+ * @param[in]       *pSrc points to complex input buffer   
+ * @param[out]      *pDst points to real output buffer   
+ * @param[in]       numSamples number of complex samples in the input vector   
+ * @return none.   
+ *   
+ */
+
+
+void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples)
+{
+  float32_t realIn, imagIn;                      /* Temporary variables to hold input values */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    /* store the result in the destination buffer. */
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    /* store the result in the destination buffer. */
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* out = sqrt((real * real) + (imag * imag)) */
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    /* store the result in the destination buffer. */
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_mag group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
new file mode 100644
index 000000000..6f5f7e041
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
@@ -0,0 +1,153 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_mag_q15.c   
+*   
+* Description:	Q15 complex magnitude.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup cmplx_mag   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Q15 complex magnitude   
+ * @param  *pSrc points to the complex input vector   
+ * @param  *pDst points to the real output vector   
+ * @param  numSamples number of complex samples in the input vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format.   
+ */
+
+void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples)
+{
+  q15_t real, imag;                              /* Temporary variables to hold input values */
+  q31_t acc0, acc1;                              /* Accumulators */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* out = sqrt(real * real + imag * imag) */
+    real = *pSrc++;
+    imag = *pSrc++;
+
+    acc0 = (real * real);
+    acc1 = (imag * imag);
+
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_mag group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
new file mode 100644
index 000000000..07b683dc6
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
@@ -0,0 +1,151 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_mag_q31.c   
+*   
+* Description:	Q31 complex magnitude   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup cmplx_mag   
+ * @{   
+ */
+
+/**   
+ * @brief  Q31 complex magnitude   
+ * @param  *pSrc points to the complex input vector   
+ * @param  *pDst points to the real output vector   
+ * @param  numSamples number of complex samples in the input vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 2.30 format.   
+ * Input down scaling is not required.   
+ */
+
+void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples)
+{
+  q31_t real, imag;                              /* Temporary variables to hold input values */
+  q31_t acc0, acc1;                              /* Accumulators */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 2.30 format in the destination buffer. */
+    arm_sqrt_q31(acc0 + acc1, pDst++);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 2.30 format in the destination buffer. */
+    arm_sqrt_q31(acc0 + acc1, pDst++);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 2.30 format in the destination buffer. */
+    arm_sqrt_q31(acc0 + acc1, pDst++);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 2.30 format in the destination buffer. */
+    arm_sqrt_q31(acc0 + acc1, pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 2.30 format in the destination buffer. */
+    arm_sqrt_q31(acc0 + acc1, pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* out = sqrt((real * real) + (imag * imag)) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 2.30 format in the destination buffer. */
+    arm_sqrt_q31(acc0 + acc1, pDst++);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_mag group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
new file mode 100644
index 000000000..87b89dea1
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
@@ -0,0 +1,155 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_mag_squared_f32.c   
+*   
+* Description:	Floating-point complex magnitude squared.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @defgroup cmplx_mag_squared Complex Magnitude Squared   
+ *   
+ * Computes the magnitude squared of the elements of a complex data vector.   
+ *  
+ * The pSrc points to the source data and   
+ * pDst points to the where the result should be written.   
+ * numSamples specifies the number of complex samples   
+ * in the input array and the data is stored in an interleaved fashion   
+ * (real, imag, real, imag, ...).   
+ * The input array has a total of 2*numSamples values;   
+ * the output array has a total of numSamples values.   
+ *   
+ * The underlying algorithm is used:   
+ *   
+ * 
   
+ * for(n=0; n   
+ *   
+ * There are separate functions for floating-point, Q15, and Q31 data types.   
+ */
+
+/**   
+ * @addtogroup cmplx_mag_squared   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Floating-point complex magnitude squared   
+ * @param[in]  *pSrc points to the complex input vector   
+ * @param[out]  *pDst points to the real output vector   
+ * @param[in]  numSamples number of complex samples in the input vector   
+ * @return none.   
+ */
+
+void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples)
+{
+  float32_t real, imag;                          /* Temporary variables to store real and imaginary values */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    /* store the result in the destination buffer. */
+    *pDst++ = (real * real) + (imag * imag);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    *pDst++ = (real * real) + (imag * imag);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    *pDst++ = (real * real) + (imag * imag);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    *pDst++ = (real * real) + (imag * imag);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    /* store the result in the destination buffer. */
+    *pDst++ = (real * real) + (imag * imag);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* reading real and imaginary values */
+    real = *pSrc++;
+    imag = *pSrc++;
+
+    /* out = (real * real) + (imag * imag) */
+    /* store the result in the destination buffer. */
+    *pDst++ = (real * real) + (imag * imag);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_mag_squared group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
new file mode 100644
index 000000000..31fb79dfc
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
@@ -0,0 +1,148 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_mag_squared_q15.c   
+*   
+* Description:	Q15 complex magnitude squared.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup cmplx_mag_squared   
+ * @{   
+ */
+
+/**   
+ * @brief  Q15 complex magnitude squared   
+ * @param  *pSrc points to the complex input vector   
+ * @param  *pDst points to the real output vector   
+ * @param  numSamples number of complex samples in the input vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.   
+ */
+
+void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples)
+{
+  q15_t real, imag;                              /* Temporary variables to store real and imaginary values */
+  q31_t acc0, acc1;                              /* Accumulators */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* out = ((real * real) + (imag * imag)) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (real * real);
+    acc1 = (imag * imag);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_mag_squared group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
new file mode 100644
index 000000000..807632e3f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
@@ -0,0 +1,150 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_mag_squared_q31.c   
+*   
+* Description:	Q31 complex magnitude squared.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup cmplx_mag_squared   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Q31 complex magnitude squared   
+ * @param  *pSrc points to the complex input vector   
+ * @param  *pDst points to the real output vector   
+ * @param  numSamples number of complex samples in the input vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.   
+ * Input down scaling is not required.   
+ */
+
+void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples)
+{
+  q31_t real, imag;                              /* Temporary variables to store real and imaginary values */
+  q31_t acc0, acc1;                              /* Accumulators */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* out = ((real * real) + (imag * imag)) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_mag_squared group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
new file mode 100644
index 000000000..4cdda3273
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
@@ -0,0 +1,180 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cmplx_mult_cmplx_f32.c   
+*   
+* Description:	Floating-point complex-by-complex multiplication   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @defgroup CmplxByCmplxMult Complex-by-Complex Multiplication   
+ *   
+ * Multiplies a complex vector by another complex vector and generates a complex result.   
+ * The data in the complex arrays is stored in an interleaved fashion   
+ * (real, imag, real, imag, ...).   
+ * The parameter numSamples represents the number of complex   
+ * samples processed.  The complex arrays have a total of 2*numSamples   
+ * real values.   
+ *   
+ * The underlying algorithm is used:   
+ *   
+ * 
   
+ * for(n=0; n   
+ *   
+ * There are separate functions for floating-point, Q15, and Q31 data types.   
+ */
+
+/**   
+ * @addtogroup CmplxByCmplxMult   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Floating-point complex-by-complex multiplication   
+ * @param[in]  *pSrcA points to the first input vector   
+ * @param[in]  *pSrcB points to the second input vector   
+ * @param[out]  *pDst  points to the output vector   
+ * @param[in]  numSamples number of complex samples in each vector   
+ * @return none.   
+ */
+
+void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples)
+{
+  float32_t a, b, c, d;                          /* Temporary variables to store real and imaginary values */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counters */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in the destination buffer. */
+    *pDst++ = (a * c) - (b * d);
+    *pDst++ = (a * d) + (b * c);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    *pDst++ = (a * c) - (b * d);
+    *pDst++ = (a * d) + (b * c);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    *pDst++ = (a * c) - (b * d);
+    *pDst++ = (a * d) + (b * c);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    *pDst++ = (a * c) - (b * d);
+    *pDst++ = (a * d) + (b * c);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in the destination buffer. */
+    *pDst++ = (a * c) - (b * d);
+    *pDst++ = (a * d) + (b * c);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in the destination buffer. */
+    *pDst++ = (a * c) - (b * d);
+    *pDst++ = (a * d) + (b * c);
+
+    /* Decrement the numSamples loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of CmplxByCmplxMult group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
new file mode 100644
index 000000000..b31e1bddb
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
@@ -0,0 +1,182 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cmplx_mult_cmplx_q15.c   
+*   
+* Description:	Q15 complex-by-complex multiplication   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup CmplxByCmplxMult   
+ * @{   
+ */
+
+/**   
+ * @brief  Q15 complex-by-complex multiplication   
+ * @param[in]  *pSrcA points to the first input vector   
+ * @param[in]  *pSrcB points to the second input vector   
+ * @param[out]  *pDst  points to the output vector   
+ * @param[in]  numSamples number of complex samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.   
+ */
+
+void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples)
+{
+  q15_t a, b, c, d;                              /* Temporary variables to store real and imaginary values */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counters */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    /* Decrement the blockSize loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of CmplxByCmplxMult group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
new file mode 100644
index 000000000..ba8e352fa
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
@@ -0,0 +1,209 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cmplx_mult_cmplx_q31.c   
+*   
+* Description:	Q31 complex-by-complex multiplication   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup CmplxByCmplxMult   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Q31 complex-by-complex multiplication   
+ * @param[in]  *pSrcA points to the first input vector   
+ * @param[in]  *pSrcB points to the second input vector   
+ * @param[out]  *pDst  points to the output vector   
+ * @param[in]  numSamples number of complex samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.   
+ * Input down scaling is not required.   
+ */
+
+void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples)
+{
+  q31_t a, b, c, d;                              /* Temporary variables to store real and imaginary values */
+  uint32_t blkCnt;                               /* loop counters */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33));
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33));
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33));
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33));
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33));
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33));
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33));
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33));
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33));
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33));
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 1u;
+
+  /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.    
+   ** a second loop below computes the remaining 1 sample. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33));
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33));
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33));
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33));
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 2, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x2u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33));
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33));
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of CmplxByCmplxMult group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
new file mode 100644
index 000000000..5d00cdcb1
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
@@ -0,0 +1,157 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cmplx_mult_real_f32.c   
+*   
+* Description:	Floating-point complex by real multiplication   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @defgroup CmplxByRealMult Complex-by-Real Multiplication   
+ *   
+ * Multiplies a complex vector by a real vector and generates a complex result.   
+ * The data in the complex arrays is stored in an interleaved fashion   
+ * (real, imag, real, imag, ...).   
+ * The parameter numSamples represents the number of complex   
+ * samples processed.  The complex arrays have a total of 2*numSamples   
+ * real values while the real array has a total of numSamples   
+ * real values.   
+ *   
+ * The underlying algorithm is used:   
+ *   
+ * 
   
+ * for(n=0; n   
+ *   
+ * There are separate functions for floating-point, Q15, and Q31 data types.   
+ */
+
+/**   
+ * @addtogroup CmplxByRealMult   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Floating-point complex-by-real multiplication   
+ * @param[in]  *pSrcCmplx points to the complex input vector   
+ * @param[in]  *pSrcReal points to the real input vector   
+ * @param[out]  *pCmplxDst points to the complex output vector   
+ * @param[in]  numSamples number of samples in each vector   
+ * @return none.   
+ */
+
+void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples)
+{
+  float32_t in;                                  /* Temporary variable to store input value */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counters */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* realOut = realA * realB.            */
+    /* imagOut = imagA * realB.                */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+
+    /* Decrement the numSamples loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of CmplxByRealMult group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
new file mode 100644
index 000000000..253fc20e6
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
@@ -0,0 +1,151 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cmplx_mult_real_q15.c   
+*   
+* Description:	Q15 complex by real multiplication   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup CmplxByRealMult   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Q15 complex-by-real multiplication   
+ * @param[in]  *pSrcCmplx points to the complex input vector   
+ * @param[in]  *pSrcReal points to the real input vector   
+ * @param[out]  *pCmplxDst points to the complex output vector   
+ * @param[in]  numSamples number of samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.   
+ */
+
+void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples)
+{
+  q15_t in;                                      /* Temporary variable to store input value */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counters */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* realOut = realA * realB.            */
+    /* imagOut = imagA * realB.                */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+    /* Decrement the numSamples loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of CmplxByRealMult group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
new file mode 100644
index 000000000..cb5f9d7d4
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
@@ -0,0 +1,151 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cmplx_mult_real_q31.c   
+*   
+* Description:	Q31 complex by real multiplication   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup CmplxByRealMult   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Q31 complex-by-real multiplication   
+ * @param[in]  *pSrcCmplx points to the complex input vector   
+ * @param[in]  *pSrcReal points to the real input vector   
+ * @param[out]  *pCmplxDst points to the complex output vector   
+ * @param[in]  numSamples number of samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.   
+ */
+
+void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples)
+{
+  q31_t in;                                      /* Temporary variable to store input value */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counters */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* realOut = realA * realB.            */
+    /* imagReal = imagA * realB.               */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+
+    /* Decrement the numSamples loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of CmplxByRealMult group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c
new file mode 100644
index 000000000..3fd65094c
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_pid_init_f32.c   
+*   
+* Description:	Floating-point PID Control initialization function   
+*				  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**   
+ * @addtogroup PID   
+ * @{   
+ */
+
+/**   
+ * @brief  Initialization function for the floating-point PID Control.  
+ * @param[in,out] *S points to an instance of the PID structure.  
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state & 1 = reset the state.  
+ * @return none.  
+ * \par Description:  
+ * \par   
+ * The resetStateFlag specifies whether to set state to zero or not. \n  
+ * The function computes the structure fields: A0, A1 A2   
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)   
+ * also sets the state variables to all zeros.   
+ */
+
+void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag)
+{
+
+  /* Derived coefficient A0 */
+  S->A0 = S->Kp + S->Ki + S->Kd;
+
+  /* Derived coefficient A1 */
+  S->A1 = (-S->Kp) - ((float32_t) 2.0 * S->Kd);
+
+  /* Derived coefficient A2 */
+  S->A2 = S->Kd;
+
+  /* Check whether state needs reset or not */
+  if(resetStateFlag)
+  {
+    /* Clear the state buffer.  The size will be always 3 samples */
+    memset(S->state, 0, 3u * sizeof(float32_t));
+  }
+
+}
+
+/**   
+ * @} end of PID group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c
new file mode 100644
index 000000000..c1a09e503
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c
@@ -0,0 +1,111 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_pid_init_q15.c   
+*   
+* Description:	Q15 PID Control initialization function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**   
+ * @addtogroup PID   
+ * @{   
+ */
+
+/**   
+ * @details   
+ * @param[in,out] *S points to an instance of the Q15 PID structure.   
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.   
+ * @return none.   
+ * \par Description:  
+ * \par   
+ * The resetStateFlag specifies whether to set state to zero or not. \n  
+ * The function computes the structure fields: A0, A1 A2   
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)   
+ * also sets the state variables to all zeros.   
+ */
+
+void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Derived coefficient A0 */
+  S->A0 = __QADD16(__QADD16(S->Kp, S->Ki), S->Kd);
+
+  /* Derived coefficients and pack into A1 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+  S->A1 = __PKHBT(-__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), S->Kd, 16);
+
+#else
+
+  S->A1 = __PKHBT(S->Kd, -__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+  /* Check whether state needs reset or not */
+  if(resetStateFlag)
+  {
+    /* Clear the state buffer.  The size will be always 3 samples */
+    memset(S->state, 0, 3u * sizeof(q15_t));
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t temp;                                    /*to store the sum */
+
+  /* Derived coefficient A0 */
+  temp = S->Kp + S->Ki + S->Kd;
+  S->A0 = (q15_t) __SSAT(temp, 16);
+
+  /* Derived coefficients and pack into A1 */
+  temp = -(S->Kd + S->Kd + S->Kp);
+  S->A1 = (q15_t) __SSAT(temp, 16);
+  S->A2 = S->Kd;
+
+
+
+  /* Check whether state needs reset or not */
+  if(resetStateFlag)
+  {
+    /* Clear the state buffer.  The size will be always 3 samples */
+    memset(S->state, 0, 3u * sizeof(q15_t));
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of PID group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c
new file mode 100644
index 000000000..78f1d3ef2
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_pid_init_q31.c   
+*   
+* Description:	Q31 PID Control initialization function    
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**   
+ * @addtogroup PID   
+ * @{   
+ */
+
+/**   
+ * @brief  Initialization function for the Q31 PID Control.  
+ * @param[in,out] *S points to an instance of the Q31 PID structure.  
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.  
+ * @return none.   
+ * \par Description:  
+ * \par   
+ * The resetStateFlag specifies whether to set state to zero or not. \n  
+ * The function computes the structure fields: A0, A1 A2   
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)   
+ * also sets the state variables to all zeros.   
+ */
+
+void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Derived coefficient A0 */
+  S->A0 = __QADD(__QADD(S->Kp, S->Ki), S->Kd);
+
+  /* Derived coefficient A1 */
+  S->A1 = -__QADD(__QADD(S->Kd, S->Kd), S->Kp);
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t temp;
+
+  /* Derived coefficient A0 */
+  temp = clip_q63_to_q31((q63_t) S->Kp + S->Ki);
+  S->A0 = clip_q63_to_q31((q63_t) temp + S->Kd);
+
+  /* Derived coefficient A1 */
+  temp = clip_q63_to_q31((q63_t) S->Kd + S->Kd);
+  S->A1 = -clip_q63_to_q31((q63_t) temp + S->Kp);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Derived coefficient A2 */
+  S->A2 = S->Kd;
+
+  /* Check whether state needs reset or not */
+  if(resetStateFlag)
+  {
+    /* Clear the state buffer.  The size will be always 3 samples */
+    memset(S->state, 0, 3u * sizeof(q31_t));
+  }
+
+}
+
+/**   
+ * @} end of PID group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c
new file mode 100644
index 000000000..4d2feda28
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c
@@ -0,0 +1,54 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_pid_reset_f32.c   
+*   
+* Description:	Floating-point PID Control reset function  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**   
+ * @addtogroup PID   
+ * @{   
+ */
+
+/**   
+* @brief  Reset function for the floating-point PID Control.  
+* @param[in] *S	Instance pointer of PID control data structure.  
+* @return none.   
+* \par Description:  
+* The function resets the state buffer to zeros.   
+*/
+void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S)
+{
+
+  /* Clear the state buffer.  The size will be always 3 samples */
+  memset(S->state, 0, 3u * sizeof(float32_t));
+}
+
+/**   
+ * @} end of PID group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c
new file mode 100644
index 000000000..b6200f1f8
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c
@@ -0,0 +1,53 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_pid_reset_q15.c   
+*   
+* Description:	Q15 PID Control reset function  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**   
+ * @addtogroup PID   
+ * @{   
+ */
+
+/**   
+* @brief  Reset function for the Q15 PID Control.  
+* @param[in] *S		Instance pointer of PID control data structure.  
+* @return none.   
+* \par Description:  
+* The function resets the state buffer to zeros.   
+*/
+void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S)
+{
+  /* Reset state to zero, The size will be always 3 samples */
+  memset(S->state, 0, 3u * sizeof(q15_t));
+}
+
+/**   
+ * @} end of PID group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c
new file mode 100644
index 000000000..0b609a4dc
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c
@@ -0,0 +1,54 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_pid_reset_q31.c   
+*   
+* Description:	Q31 PID Control reset function  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**   
+ * @addtogroup PID   
+ * @{   
+ */
+
+/**   
+* @brief  Reset function for the Q31 PID Control.  
+* @param[in] *S	Instance pointer of PID control data structure.  
+* @return none.   
+* \par Description:  
+* The function resets the state buffer to zeros.   
+*/
+void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S)
+{
+
+  /* Clear the state buffer.  The size will be always 3 samples */
+  memset(S->state, 0, 3u * sizeof(q31_t));
+}
+
+/**   
+ * @} end of PID group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c
new file mode 100644
index 000000000..6eded6d6b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c
@@ -0,0 +1,408 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_sin_cos_f32.c   
+*   
+* Description:	Sine and Cosine calculation for floating-point values.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupController   
+ */
+
+/**   
+ * @defgroup SinCos Sine Cosine  
+ *   
+ * Computes the trigonometric sine and cosine values using a combination of table lookup  
+ * and linear interpolation.    
+ * There are separate functions for Q31 and floating-point data types.  
+ * The input to the floating-point version is in degrees while the  
+ * fixed-point Q31 have a scaled input with the range  
+ * [-1 1) mapping to [-180 180) degrees.  
+ *  
+ * The implementation is based on table lookup using 360 values together with linear interpolation.  
+ * The steps used are:  
+ *  -# Calculation of the nearest integer table index.  
+ *  -# Compute the fractional portion (fract) of the input.  
+ *  -# Fetch the value corresponding to \c index from sine table to \c y0 and also value from \c index+1 to \c y1.     
+ *  -# Sine value is computed as  *psinVal = y0 + (fract * (y1 - y0)).   
+ *  -# Fetch the value corresponding to \c index from cosine table to \c y0 and also value from \c index+1 to \c y1.     
+ *  -# Cosine value is computed as  *pcosVal = y0 + (fract * (y1 - y0)).   
+ */
+
+ /**   
+ * @addtogroup SinCos   
+ * @{   
+ */
+
+
+/**   
+* \par   
+* Cosine Table is generated from following loop   
+* 
for(i = 0; i < 360; i++)   
+* {   
+*    cosTable[i]= cos((i-180) * PI/180.0);   
+* } 
  
+*/
+
+static const float32_t cosTable[360] = {
+  -0.999847695156391270f, -0.999390827019095760f, -0.998629534754573830f,
+  -0.997564050259824200f, -0.996194698091745550f, -0.994521895368273290f,
+  -0.992546151641321980f, -0.990268068741570250f,
+  -0.987688340595137660f, -0.984807753012208020f, -0.981627183447663980f,
+  -0.978147600733805690f, -0.974370064785235250f, -0.970295726275996470f,
+  -0.965925826289068200f, -0.961261695938318670f,
+  -0.956304755963035440f, -0.951056516295153530f, -0.945518575599316740f,
+  -0.939692620785908320f, -0.933580426497201740f, -0.927183854566787310f,
+  -0.920504853452440150f, -0.913545457642600760f,
+  -0.906307787036649940f, -0.898794046299167040f, -0.891006524188367790f,
+  -0.882947592858926770f, -0.874619707139395740f, -0.866025403784438710f,
+  -0.857167300702112220f, -0.848048096156425960f,
+  -0.838670567945424160f, -0.829037572555041620f, -0.819152044288991580f,
+  -0.809016994374947340f, -0.798635510047292940f, -0.788010753606721900f,
+  -0.777145961456970680f, -0.766044443118977900f,
+  -0.754709580222772010f, -0.743144825477394130f, -0.731353701619170460f,
+  -0.719339800338651300f, -0.707106781186547460f, -0.694658370458997030f,
+  -0.681998360062498370f, -0.669130606358858240f,
+  -0.656059028990507500f, -0.642787609686539360f, -0.629320391049837280f,
+  -0.615661475325658290f, -0.601815023152048380f, -0.587785252292473030f,
+  -0.573576436351045830f, -0.559192903470746680f,
+  -0.544639035015027080f, -0.529919264233204790f, -0.515038074910054270f,
+  -0.499999999999999780f, -0.484809620246337000f, -0.469471562785890530f,
+  -0.453990499739546750f, -0.438371146789077510f,
+  -0.422618261740699330f, -0.406736643075800100f, -0.390731128489273600f,
+  -0.374606593415912070f, -0.358367949545300270f, -0.342020143325668710f,
+  -0.325568154457156420f, -0.309016994374947340f,
+  -0.292371704722736660f, -0.275637355816999050f, -0.258819045102520850f,
+  -0.241921895599667790f, -0.224951054343864810f, -0.207911690817759120f,
+  -0.190808995376544800f, -0.173648177666930300f,
+  -0.156434465040231040f, -0.139173100960065350f, -0.121869343405147370f,
+  -0.104528463267653330f, -0.087155742747658235f, -0.069756473744125330f,
+  -0.052335956242943620f, -0.034899496702500733f,
+  -0.017452406437283477f, 0.000000000000000061f, 0.017452406437283376f,
+  0.034899496702501080f, 0.052335956242943966f, 0.069756473744125455f,
+  0.087155742747658138f, 0.104528463267653460f,
+  0.121869343405147490f, 0.139173100960065690f, 0.156434465040230920f,
+  0.173648177666930410f, 0.190808995376544920f, 0.207911690817759450f,
+  0.224951054343864920f, 0.241921895599667900f,
+  0.258819045102520740f, 0.275637355816999160f, 0.292371704722736770f,
+  0.309016994374947450f, 0.325568154457156760f, 0.342020143325668820f,
+  0.358367949545300380f, 0.374606593415911960f,
+  0.390731128489273940f, 0.406736643075800210f, 0.422618261740699440f,
+  0.438371146789077460f, 0.453990499739546860f, 0.469471562785890860f,
+  0.484809620246337110f, 0.500000000000000110f,
+  0.515038074910054380f, 0.529919264233204900f, 0.544639035015027200f,
+  0.559192903470746790f, 0.573576436351046050f, 0.587785252292473140f,
+  0.601815023152048270f, 0.615661475325658290f,
+  0.629320391049837500f, 0.642787609686539360f, 0.656059028990507280f,
+  0.669130606358858240f, 0.681998360062498480f, 0.694658370458997370f,
+  0.707106781186547570f, 0.719339800338651190f,
+  0.731353701619170570f, 0.743144825477394240f, 0.754709580222772010f,
+  0.766044443118978010f, 0.777145961456970900f, 0.788010753606722010f,
+  0.798635510047292830f, 0.809016994374947450f,
+  0.819152044288991800f, 0.829037572555041620f, 0.838670567945424050f,
+  0.848048096156425960f, 0.857167300702112330f, 0.866025403784438710f,
+  0.874619707139395740f, 0.882947592858926990f,
+  0.891006524188367900f, 0.898794046299167040f, 0.906307787036649940f,
+  0.913545457642600870f, 0.920504853452440370f, 0.927183854566787420f,
+  0.933580426497201740f, 0.939692620785908430f,
+  0.945518575599316850f, 0.951056516295153530f, 0.956304755963035440f,
+  0.961261695938318890f, 0.965925826289068310f, 0.970295726275996470f,
+  0.974370064785235250f, 0.978147600733805690f,
+  0.981627183447663980f, 0.984807753012208020f, 0.987688340595137770f,
+  0.990268068741570360f, 0.992546151641321980f, 0.994521895368273290f,
+  0.996194698091745550f, 0.997564050259824200f,
+  0.998629534754573830f, 0.999390827019095760f, 0.999847695156391270f,
+  1.000000000000000000f, 0.999847695156391270f, 0.999390827019095760f,
+  0.998629534754573830f, 0.997564050259824200f,
+  0.996194698091745550f, 0.994521895368273290f, 0.992546151641321980f,
+  0.990268068741570360f, 0.987688340595137770f, 0.984807753012208020f,
+  0.981627183447663980f, 0.978147600733805690f,
+  0.974370064785235250f, 0.970295726275996470f, 0.965925826289068310f,
+  0.961261695938318890f, 0.956304755963035440f, 0.951056516295153530f,
+  0.945518575599316850f, 0.939692620785908430f,
+  0.933580426497201740f, 0.927183854566787420f, 0.920504853452440370f,
+  0.913545457642600870f, 0.906307787036649940f, 0.898794046299167040f,
+  0.891006524188367900f, 0.882947592858926990f,
+  0.874619707139395740f, 0.866025403784438710f, 0.857167300702112330f,
+  0.848048096156425960f, 0.838670567945424050f, 0.829037572555041620f,
+  0.819152044288991800f, 0.809016994374947450f,
+  0.798635510047292830f, 0.788010753606722010f, 0.777145961456970900f,
+  0.766044443118978010f, 0.754709580222772010f, 0.743144825477394240f,
+  0.731353701619170570f, 0.719339800338651190f,
+  0.707106781186547570f, 0.694658370458997370f, 0.681998360062498480f,
+  0.669130606358858240f, 0.656059028990507280f, 0.642787609686539360f,
+  0.629320391049837500f, 0.615661475325658290f,
+  0.601815023152048270f, 0.587785252292473140f, 0.573576436351046050f,
+  0.559192903470746790f, 0.544639035015027200f, 0.529919264233204900f,
+  0.515038074910054380f, 0.500000000000000110f,
+  0.484809620246337110f, 0.469471562785890860f, 0.453990499739546860f,
+  0.438371146789077460f, 0.422618261740699440f, 0.406736643075800210f,
+  0.390731128489273940f, 0.374606593415911960f,
+  0.358367949545300380f, 0.342020143325668820f, 0.325568154457156760f,
+  0.309016994374947450f, 0.292371704722736770f, 0.275637355816999160f,
+  0.258819045102520740f, 0.241921895599667900f,
+  0.224951054343864920f, 0.207911690817759450f, 0.190808995376544920f,
+  0.173648177666930410f, 0.156434465040230920f, 0.139173100960065690f,
+  0.121869343405147490f, 0.104528463267653460f,
+  0.087155742747658138f, 0.069756473744125455f, 0.052335956242943966f,
+  0.034899496702501080f, 0.017452406437283376f, 0.000000000000000061f,
+  -0.017452406437283477f, -0.034899496702500733f,
+  -0.052335956242943620f, -0.069756473744125330f, -0.087155742747658235f,
+  -0.104528463267653330f, -0.121869343405147370f, -0.139173100960065350f,
+  -0.156434465040231040f, -0.173648177666930300f,
+  -0.190808995376544800f, -0.207911690817759120f, -0.224951054343864810f,
+  -0.241921895599667790f, -0.258819045102520850f, -0.275637355816999050f,
+  -0.292371704722736660f, -0.309016994374947340f,
+  -0.325568154457156420f, -0.342020143325668710f, -0.358367949545300270f,
+  -0.374606593415912070f, -0.390731128489273600f, -0.406736643075800100f,
+  -0.422618261740699330f, -0.438371146789077510f,
+  -0.453990499739546750f, -0.469471562785890530f, -0.484809620246337000f,
+  -0.499999999999999780f, -0.515038074910054270f, -0.529919264233204790f,
+  -0.544639035015027080f, -0.559192903470746680f,
+  -0.573576436351045830f, -0.587785252292473030f, -0.601815023152048380f,
+  -0.615661475325658290f, -0.629320391049837280f, -0.642787609686539360f,
+  -0.656059028990507500f, -0.669130606358858240f,
+  -0.681998360062498370f, -0.694658370458997030f, -0.707106781186547460f,
+  -0.719339800338651300f, -0.731353701619170460f, -0.743144825477394130f,
+  -0.754709580222772010f, -0.766044443118977900f,
+  -0.777145961456970680f, -0.788010753606721900f, -0.798635510047292940f,
+  -0.809016994374947340f, -0.819152044288991580f, -0.829037572555041620f,
+  -0.838670567945424160f, -0.848048096156425960f,
+  -0.857167300702112220f, -0.866025403784438710f, -0.874619707139395740f,
+  -0.882947592858926770f, -0.891006524188367790f, -0.898794046299167040f,
+  -0.906307787036649940f, -0.913545457642600760f,
+  -0.920504853452440150f, -0.927183854566787310f, -0.933580426497201740f,
+  -0.939692620785908320f, -0.945518575599316740f, -0.951056516295153530f,
+  -0.956304755963035440f, -0.961261695938318670f,
+  -0.965925826289068200f, -0.970295726275996470f, -0.974370064785235250f,
+  -0.978147600733805690f, -0.981627183447663980f, -0.984807753012208020f,
+  -0.987688340595137660f, -0.990268068741570250f,
+  -0.992546151641321980f, -0.994521895368273290f, -0.996194698091745550f,
+  -0.997564050259824200f, -0.998629534754573830f, -0.999390827019095760f,
+  -0.999847695156391270f, -1.000000000000000000f
+};
+
+/**   
+* \par   
+* Sine Table is generated from following loop   
+* 
for(i = 0; i < 360; i++)   
+* {   
+*    sinTable[i]= sin((i-180) * PI/180.0);   
+* } 
   
+*/
+
+
+static const float32_t sinTable[360] = {
+  -0.017452406437283439f, -0.034899496702500699f, -0.052335956242943807f,
+  -0.069756473744125524f, -0.087155742747658638f, -0.104528463267653730f,
+  -0.121869343405147550f, -0.139173100960065740f,
+  -0.156434465040230980f, -0.173648177666930280f, -0.190808995376544970f,
+  -0.207911690817759310f, -0.224951054343864780f, -0.241921895599667730f,
+  -0.258819045102521020f, -0.275637355816999660f,
+  -0.292371704722737050f, -0.309016994374947510f, -0.325568154457156980f,
+  -0.342020143325668880f, -0.358367949545300210f, -0.374606593415912240f,
+  -0.390731128489274160f, -0.406736643075800430f,
+  -0.422618261740699500f, -0.438371146789077290f, -0.453990499739546860f,
+  -0.469471562785891080f, -0.484809620246337170f, -0.499999999999999940f,
+  -0.515038074910054380f, -0.529919264233204900f,
+  -0.544639035015026860f, -0.559192903470746900f, -0.573576436351046380f,
+  -0.587785252292473250f, -0.601815023152048160f, -0.615661475325658400f,
+  -0.629320391049837720f, -0.642787609686539470f,
+  -0.656059028990507280f, -0.669130606358858350f, -0.681998360062498590f,
+  -0.694658370458997140f, -0.707106781186547570f, -0.719339800338651410f,
+  -0.731353701619170570f, -0.743144825477394240f,
+  -0.754709580222771790f, -0.766044443118978010f, -0.777145961456971010f,
+  -0.788010753606722010f, -0.798635510047292720f, -0.809016994374947450f,
+  -0.819152044288992020f, -0.829037572555041740f,
+  -0.838670567945424050f, -0.848048096156426070f, -0.857167300702112330f,
+  -0.866025403784438710f, -0.874619707139395850f, -0.882947592858927100f,
+  -0.891006524188367900f, -0.898794046299166930f,
+  -0.906307787036650050f, -0.913545457642600980f, -0.920504853452440370f,
+  -0.927183854566787420f, -0.933580426497201740f, -0.939692620785908430f,
+  -0.945518575599316850f, -0.951056516295153640f,
+  -0.956304755963035550f, -0.961261695938318890f, -0.965925826289068310f,
+  -0.970295726275996470f, -0.974370064785235250f, -0.978147600733805690f,
+  -0.981627183447663980f, -0.984807753012208020f,
+  -0.987688340595137660f, -0.990268068741570360f, -0.992546151641322090f,
+  -0.994521895368273400f, -0.996194698091745550f, -0.997564050259824200f,
+  -0.998629534754573830f, -0.999390827019095760f,
+  -0.999847695156391270f, -1.000000000000000000f, -0.999847695156391270f,
+  -0.999390827019095760f, -0.998629534754573830f, -0.997564050259824200f,
+  -0.996194698091745550f, -0.994521895368273290f,
+  -0.992546151641321980f, -0.990268068741570250f, -0.987688340595137770f,
+  -0.984807753012208020f, -0.981627183447663980f, -0.978147600733805580f,
+  -0.974370064785235250f, -0.970295726275996470f,
+  -0.965925826289068310f, -0.961261695938318890f, -0.956304755963035440f,
+  -0.951056516295153530f, -0.945518575599316740f, -0.939692620785908320f,
+  -0.933580426497201740f, -0.927183854566787420f,
+  -0.920504853452440260f, -0.913545457642600870f, -0.906307787036649940f,
+  -0.898794046299167040f, -0.891006524188367790f, -0.882947592858926880f,
+  -0.874619707139395740f, -0.866025403784438600f,
+  -0.857167300702112220f, -0.848048096156426070f, -0.838670567945423940f,
+  -0.829037572555041740f, -0.819152044288991800f, -0.809016994374947450f,
+  -0.798635510047292830f, -0.788010753606722010f,
+  -0.777145961456970790f, -0.766044443118978010f, -0.754709580222772010f,
+  -0.743144825477394240f, -0.731353701619170460f, -0.719339800338651080f,
+  -0.707106781186547460f, -0.694658370458997250f,
+  -0.681998360062498480f, -0.669130606358858240f, -0.656059028990507160f,
+  -0.642787609686539250f, -0.629320391049837390f, -0.615661475325658180f,
+  -0.601815023152048270f, -0.587785252292473140f,
+  -0.573576436351046050f, -0.559192903470746900f, -0.544639035015027080f,
+  -0.529919264233204900f, -0.515038074910054160f, -0.499999999999999940f,
+  -0.484809620246337060f, -0.469471562785890810f,
+  -0.453990499739546750f, -0.438371146789077400f, -0.422618261740699440f,
+  -0.406736643075800150f, -0.390731128489273720f, -0.374606593415912010f,
+  -0.358367949545300270f, -0.342020143325668710f,
+  -0.325568154457156640f, -0.309016994374947400f, -0.292371704722736770f,
+  -0.275637355816999160f, -0.258819045102520740f, -0.241921895599667730f,
+  -0.224951054343865000f, -0.207911690817759310f,
+  -0.190808995376544800f, -0.173648177666930330f, -0.156434465040230870f,
+  -0.139173100960065440f, -0.121869343405147480f, -0.104528463267653460f,
+  -0.087155742747658166f, -0.069756473744125302f,
+  -0.052335956242943828f, -0.034899496702500969f, -0.017452406437283512f,
+  0.000000000000000000f, 0.017452406437283512f, 0.034899496702500969f,
+  0.052335956242943828f, 0.069756473744125302f,
+  0.087155742747658166f, 0.104528463267653460f, 0.121869343405147480f,
+  0.139173100960065440f, 0.156434465040230870f, 0.173648177666930330f,
+  0.190808995376544800f, 0.207911690817759310f,
+  0.224951054343865000f, 0.241921895599667730f, 0.258819045102520740f,
+  0.275637355816999160f, 0.292371704722736770f, 0.309016994374947400f,
+  0.325568154457156640f, 0.342020143325668710f,
+  0.358367949545300270f, 0.374606593415912010f, 0.390731128489273720f,
+  0.406736643075800150f, 0.422618261740699440f, 0.438371146789077400f,
+  0.453990499739546750f, 0.469471562785890810f,
+  0.484809620246337060f, 0.499999999999999940f, 0.515038074910054160f,
+  0.529919264233204900f, 0.544639035015027080f, 0.559192903470746900f,
+  0.573576436351046050f, 0.587785252292473140f,
+  0.601815023152048270f, 0.615661475325658180f, 0.629320391049837390f,
+  0.642787609686539250f, 0.656059028990507160f, 0.669130606358858240f,
+  0.681998360062498480f, 0.694658370458997250f,
+  0.707106781186547460f, 0.719339800338651080f, 0.731353701619170460f,
+  0.743144825477394240f, 0.754709580222772010f, 0.766044443118978010f,
+  0.777145961456970790f, 0.788010753606722010f,
+  0.798635510047292830f, 0.809016994374947450f, 0.819152044288991800f,
+  0.829037572555041740f, 0.838670567945423940f, 0.848048096156426070f,
+  0.857167300702112220f, 0.866025403784438600f,
+  0.874619707139395740f, 0.882947592858926880f, 0.891006524188367790f,
+  0.898794046299167040f, 0.906307787036649940f, 0.913545457642600870f,
+  0.920504853452440260f, 0.927183854566787420f,
+  0.933580426497201740f, 0.939692620785908320f, 0.945518575599316740f,
+  0.951056516295153530f, 0.956304755963035440f, 0.961261695938318890f,
+  0.965925826289068310f, 0.970295726275996470f,
+  0.974370064785235250f, 0.978147600733805580f, 0.981627183447663980f,
+  0.984807753012208020f, 0.987688340595137770f, 0.990268068741570250f,
+  0.992546151641321980f, 0.994521895368273290f,
+  0.996194698091745550f, 0.997564050259824200f, 0.998629534754573830f,
+  0.999390827019095760f, 0.999847695156391270f, 1.000000000000000000f,
+  0.999847695156391270f, 0.999390827019095760f,
+  0.998629534754573830f, 0.997564050259824200f, 0.996194698091745550f,
+  0.994521895368273400f, 0.992546151641322090f, 0.990268068741570360f,
+  0.987688340595137660f, 0.984807753012208020f,
+  0.981627183447663980f, 0.978147600733805690f, 0.974370064785235250f,
+  0.970295726275996470f, 0.965925826289068310f, 0.961261695938318890f,
+  0.956304755963035550f, 0.951056516295153640f,
+  0.945518575599316850f, 0.939692620785908430f, 0.933580426497201740f,
+  0.927183854566787420f, 0.920504853452440370f, 0.913545457642600980f,
+  0.906307787036650050f, 0.898794046299166930f,
+  0.891006524188367900f, 0.882947592858927100f, 0.874619707139395850f,
+  0.866025403784438710f, 0.857167300702112330f, 0.848048096156426070f,
+  0.838670567945424050f, 0.829037572555041740f,
+  0.819152044288992020f, 0.809016994374947450f, 0.798635510047292720f,
+  0.788010753606722010f, 0.777145961456971010f, 0.766044443118978010f,
+  0.754709580222771790f, 0.743144825477394240f,
+  0.731353701619170570f, 0.719339800338651410f, 0.707106781186547570f,
+  0.694658370458997140f, 0.681998360062498590f, 0.669130606358858350f,
+  0.656059028990507280f, 0.642787609686539470f,
+  0.629320391049837720f, 0.615661475325658400f, 0.601815023152048160f,
+  0.587785252292473250f, 0.573576436351046380f, 0.559192903470746900f,
+  0.544639035015026860f, 0.529919264233204900f,
+  0.515038074910054380f, 0.499999999999999940f, 0.484809620246337170f,
+  0.469471562785891080f, 0.453990499739546860f, 0.438371146789077290f,
+  0.422618261740699500f, 0.406736643075800430f,
+  0.390731128489274160f, 0.374606593415912240f, 0.358367949545300210f,
+  0.342020143325668880f, 0.325568154457156980f, 0.309016994374947510f,
+  0.292371704722737050f, 0.275637355816999660f,
+  0.258819045102521020f, 0.241921895599667730f, 0.224951054343864780f,
+  0.207911690817759310f, 0.190808995376544970f, 0.173648177666930280f,
+  0.156434465040230980f, 0.139173100960065740f,
+  0.121869343405147550f, 0.104528463267653730f, 0.087155742747658638f,
+  0.069756473744125524f, 0.052335956242943807f, 0.034899496702500699f,
+  0.017452406437283439f, 0.000000000000000122f
+};
+
+
+/**   
+ * @brief  Floating-point sin_cos function.  
+ * @param[in]  theta    input value in degrees   
+ * @param[out] *pSinVal points to the processed sine output.   
+ * @param[out] *pCosVal points to the processed cos output.   
+ * @return none.  
+ */
+
+
+void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCosVal)
+{
+  uint32_t i;                                    /* Index for reading nearwst output values */
+  float32_t x1 = -179.0f;                        /* Initial input value */
+  float32_t y0, y1;                              /* nearest output values */
+  float32_t fract;                               /* fractional part of input */
+
+  /* Calculation of fractional part */
+  if(theta > 0.0f)
+  {
+    fract = theta - (float32_t) ((int32_t) theta);
+  }
+  else
+  {
+    fract = (theta - (float32_t) ((int32_t) theta)) + 1.0f;
+  }
+
+  /* index calculation for reading nearest output values */
+  i = (uint32_t) (theta - x1);
+
+  /* reading nearest sine output values */
+  y0 = sinTable[i];
+  y1 = sinTable[i + 1u];
+
+  /* Calculation of sine value */
+  *pSinVal = y0 + (fract * (y1 - y0));
+
+  /* reading nearest cosine output values */
+  y0 = cosTable[i];
+  y1 = cosTable[i + 1u];
+
+  /* Calculation of cosine value */
+  *pCosVal = y0 + (fract * (y1 - y0));
+
+}
+
+/**   
+ * @} end of SinCos group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c
new file mode 100644
index 000000000..118599475
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c
@@ -0,0 +1,311 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_sin_cos_q31.c   
+*   
+* Description:	Cosine & Sine calculation for Q31 values.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupController   
+ */
+
+ /**   
+ * @addtogroup SinCos   
+ * @{   
+ */
+
+/**   
+* \par   
+* Sine Table is generated from following loop   
+* 
for(i = 0; i < 360; i++)   
+* {   
+*    sinTable[i]= sin((i-180) * PI/180.0);   
+* } 
  
+* Convert above coefficients to fixed point 1.31 format.   
+*/
+
+static const int32_t sinTableQ31[360] = {
+
+  0x0, 0xfdc41e9b, 0xfb8869ce, 0xf94d0e2e, 0xf7123849, 0xf4d814a4, 0xf29ecfb2,
+  0xf06695da,
+  0xee2f9369, 0xebf9f498, 0xe9c5e582, 0xe7939223, 0xe5632654, 0xe334cdc9,
+  0xe108b40d, 0xdedf047d,
+  0xdcb7ea46, 0xda939061, 0xd8722192, 0xd653c860, 0xd438af17, 0xd220ffc0,
+  0xd00ce422, 0xcdfc85bb,
+  0xcbf00dbe, 0xc9e7a512, 0xc7e3744b, 0xc5e3a3a9, 0xc3e85b18, 0xc1f1c224,
+  0xc0000000, 0xbe133b7c,
+  0xbc2b9b05, 0xba4944a2, 0xb86c5df0, 0xb6950c1e, 0xb4c373ee, 0xb2f7b9af,
+  0xb1320139, 0xaf726def,
+  0xadb922b7, 0xac0641fb, 0xaa59eda4, 0xa8b4471a, 0xa7156f3c, 0xa57d8666,
+  0xa3ecac65, 0xa263007d,
+  0xa0e0a15f, 0x9f65ad2d, 0x9df24175, 0x9c867b2c, 0x9b2276b0, 0x99c64fc5,
+  0x98722192, 0x9726069c,
+  0x95e218c9, 0x94a6715d, 0x937328f5, 0x92485786, 0x9126145f, 0x900c7621,
+  0x8efb92c2, 0x8df37f8b,
+  0x8cf45113, 0x8bfe1b3f, 0x8b10f144, 0x8a2ce59f, 0x89520a1a, 0x88806fc4,
+  0x87b826f7, 0x86f93f50,
+  0x8643c7b3, 0x8597ce46, 0x84f56073, 0x845c8ae3, 0x83cd5982, 0x8347d77b,
+  0x82cc0f36, 0x825a0a5b,
+  0x81f1d1ce, 0x81936daf, 0x813ee55b, 0x80f43f69, 0x80b381ac, 0x807cb130,
+  0x804fd23a, 0x802ce84c,
+  0x8013f61d, 0x8004fda0, 0x80000000, 0x8004fda0, 0x8013f61d, 0x802ce84c,
+  0x804fd23a, 0x807cb130,
+  0x80b381ac, 0x80f43f69, 0x813ee55b, 0x81936daf, 0x81f1d1ce, 0x825a0a5b,
+  0x82cc0f36, 0x8347d77b,
+  0x83cd5982, 0x845c8ae3, 0x84f56073, 0x8597ce46, 0x8643c7b3, 0x86f93f50,
+  0x87b826f7, 0x88806fc4,
+  0x89520a1a, 0x8a2ce59f, 0x8b10f144, 0x8bfe1b3f, 0x8cf45113, 0x8df37f8b,
+  0x8efb92c2, 0x900c7621,
+  0x9126145f, 0x92485786, 0x937328f5, 0x94a6715d, 0x95e218c9, 0x9726069c,
+  0x98722192, 0x99c64fc5,
+  0x9b2276b0, 0x9c867b2c, 0x9df24175, 0x9f65ad2d, 0xa0e0a15f, 0xa263007d,
+  0xa3ecac65, 0xa57d8666,
+  0xa7156f3c, 0xa8b4471a, 0xaa59eda4, 0xac0641fb, 0xadb922b7, 0xaf726def,
+  0xb1320139, 0xb2f7b9af,
+  0xb4c373ee, 0xb6950c1e, 0xb86c5df0, 0xba4944a2, 0xbc2b9b05, 0xbe133b7c,
+  0xc0000000, 0xc1f1c224,
+  0xc3e85b18, 0xc5e3a3a9, 0xc7e3744b, 0xc9e7a512, 0xcbf00dbe, 0xcdfc85bb,
+  0xd00ce422, 0xd220ffc0,
+  0xd438af17, 0xd653c860, 0xd8722192, 0xda939061, 0xdcb7ea46, 0xdedf047d,
+  0xe108b40d, 0xe334cdc9,
+  0xe5632654, 0xe7939223, 0xe9c5e582, 0xebf9f498, 0xee2f9369, 0xf06695da,
+  0xf29ecfb2, 0xf4d814a4,
+  0xf7123849, 0xf94d0e2e, 0xfb8869ce, 0xfdc41e9b, 0x0, 0x23be165, 0x4779632,
+  0x6b2f1d2,
+  0x8edc7b7, 0xb27eb5c, 0xd61304e, 0xf996a26, 0x11d06c97, 0x14060b68,
+  0x163a1a7e, 0x186c6ddd,
+  0x1a9cd9ac, 0x1ccb3237, 0x1ef74bf3, 0x2120fb83, 0x234815ba, 0x256c6f9f,
+  0x278dde6e, 0x29ac37a0,
+  0x2bc750e9, 0x2ddf0040, 0x2ff31bde, 0x32037a45, 0x340ff242, 0x36185aee,
+  0x381c8bb5, 0x3a1c5c57,
+  0x3c17a4e8, 0x3e0e3ddc, 0x40000000, 0x41ecc484, 0x43d464fb, 0x45b6bb5e,
+  0x4793a210, 0x496af3e2,
+  0x4b3c8c12, 0x4d084651, 0x4ecdfec7, 0x508d9211, 0x5246dd49, 0x53f9be05,
+  0x55a6125c, 0x574bb8e6,
+  0x58ea90c4, 0x5a82799a, 0x5c13539b, 0x5d9cff83, 0x5f1f5ea1, 0x609a52d3,
+  0x620dbe8b, 0x637984d4,
+  0x64dd8950, 0x6639b03b, 0x678dde6e, 0x68d9f964, 0x6a1de737, 0x6b598ea3,
+  0x6c8cd70b, 0x6db7a87a,
+  0x6ed9eba1, 0x6ff389df, 0x71046d3e, 0x720c8075, 0x730baeed, 0x7401e4c1,
+  0x74ef0ebc, 0x75d31a61,
+  0x76adf5e6, 0x777f903c, 0x7847d909, 0x7906c0b0, 0x79bc384d, 0x7a6831ba,
+  0x7b0a9f8d, 0x7ba3751d,
+  0x7c32a67e, 0x7cb82885, 0x7d33f0ca, 0x7da5f5a5, 0x7e0e2e32, 0x7e6c9251,
+  0x7ec11aa5, 0x7f0bc097,
+  0x7f4c7e54, 0x7f834ed0, 0x7fb02dc6, 0x7fd317b4, 0x7fec09e3, 0x7ffb0260,
+  0x7fffffff, 0x7ffb0260,
+  0x7fec09e3, 0x7fd317b4, 0x7fb02dc6, 0x7f834ed0, 0x7f4c7e54, 0x7f0bc097,
+  0x7ec11aa5, 0x7e6c9251,
+  0x7e0e2e32, 0x7da5f5a5, 0x7d33f0ca, 0x7cb82885, 0x7c32a67e, 0x7ba3751d,
+  0x7b0a9f8d, 0x7a6831ba,
+  0x79bc384d, 0x7906c0b0, 0x7847d909, 0x777f903c, 0x76adf5e6, 0x75d31a61,
+  0x74ef0ebc, 0x7401e4c1,
+  0x730baeed, 0x720c8075, 0x71046d3e, 0x6ff389df, 0x6ed9eba1, 0x6db7a87a,
+  0x6c8cd70b, 0x6b598ea3,
+  0x6a1de737, 0x68d9f964, 0x678dde6e, 0x6639b03b, 0x64dd8950, 0x637984d4,
+  0x620dbe8b, 0x609a52d3,
+  0x5f1f5ea1, 0x5d9cff83, 0x5c13539b, 0x5a82799a, 0x58ea90c4, 0x574bb8e6,
+  0x55a6125c, 0x53f9be05,
+  0x5246dd49, 0x508d9211, 0x4ecdfec7, 0x4d084651, 0x4b3c8c12, 0x496af3e2,
+  0x4793a210, 0x45b6bb5e,
+  0x43d464fb, 0x41ecc484, 0x40000000, 0x3e0e3ddc, 0x3c17a4e8, 0x3a1c5c57,
+  0x381c8bb5, 0x36185aee,
+  0x340ff242, 0x32037a45, 0x2ff31bde, 0x2ddf0040, 0x2bc750e9, 0x29ac37a0,
+  0x278dde6e, 0x256c6f9f,
+  0x234815ba, 0x2120fb83, 0x1ef74bf3, 0x1ccb3237, 0x1a9cd9ac, 0x186c6ddd,
+  0x163a1a7e, 0x14060b68,
+  0x11d06c97, 0xf996a26, 0xd61304e, 0xb27eb5c, 0x8edc7b7, 0x6b2f1d2,
+  0x4779632, 0x23be165,
+
+
+};
+
+/**   
+* \par   
+* Cosine Table is generated from following loop   
+* 
for(i = 0; i < 360; i++)   
+* {   
+*    cosTable[i]= cos((i-180) * PI/180.0);   
+* } 
  
+* \par   
+* Convert above coefficients to fixed point 1.31 format.   
+*/
+static const int32_t cosTableQ31[360] = {
+  0x80000000, 0x8004fda0, 0x8013f61d, 0x802ce84c, 0x804fd23a, 0x807cb130,
+  0x80b381ac, 0x80f43f69,
+  0x813ee55b, 0x81936daf, 0x81f1d1ce, 0x825a0a5b, 0x82cc0f36, 0x8347d77b,
+  0x83cd5982, 0x845c8ae3,
+  0x84f56073, 0x8597ce46, 0x8643c7b3, 0x86f93f50, 0x87b826f7, 0x88806fc4,
+  0x89520a1a, 0x8a2ce59f,
+  0x8b10f144, 0x8bfe1b3f, 0x8cf45113, 0x8df37f8b, 0x8efb92c2, 0x900c7621,
+  0x9126145f, 0x92485786,
+  0x937328f5, 0x94a6715d, 0x95e218c9, 0x9726069c, 0x98722192, 0x99c64fc5,
+  0x9b2276b0, 0x9c867b2c,
+  0x9df24175, 0x9f65ad2d, 0xa0e0a15f, 0xa263007d, 0xa3ecac65, 0xa57d8666,
+  0xa7156f3c, 0xa8b4471a,
+  0xaa59eda4, 0xac0641fb, 0xadb922b7, 0xaf726def, 0xb1320139, 0xb2f7b9af,
+  0xb4c373ee, 0xb6950c1e,
+  0xb86c5df0, 0xba4944a2, 0xbc2b9b05, 0xbe133b7c, 0xc0000000, 0xc1f1c224,
+  0xc3e85b18, 0xc5e3a3a9,
+  0xc7e3744b, 0xc9e7a512, 0xcbf00dbe, 0xcdfc85bb, 0xd00ce422, 0xd220ffc0,
+  0xd438af17, 0xd653c860,
+  0xd8722192, 0xda939061, 0xdcb7ea46, 0xdedf047d, 0xe108b40d, 0xe334cdc9,
+  0xe5632654, 0xe7939223,
+  0xe9c5e582, 0xebf9f498, 0xee2f9369, 0xf06695da, 0xf29ecfb2, 0xf4d814a4,
+  0xf7123849, 0xf94d0e2e,
+  0xfb8869ce, 0xfdc41e9b, 0x0, 0x23be165, 0x4779632, 0x6b2f1d2, 0x8edc7b7,
+  0xb27eb5c,
+  0xd61304e, 0xf996a26, 0x11d06c97, 0x14060b68, 0x163a1a7e, 0x186c6ddd,
+  0x1a9cd9ac, 0x1ccb3237,
+  0x1ef74bf3, 0x2120fb83, 0x234815ba, 0x256c6f9f, 0x278dde6e, 0x29ac37a0,
+  0x2bc750e9, 0x2ddf0040,
+  0x2ff31bde, 0x32037a45, 0x340ff242, 0x36185aee, 0x381c8bb5, 0x3a1c5c57,
+  0x3c17a4e8, 0x3e0e3ddc,
+  0x40000000, 0x41ecc484, 0x43d464fb, 0x45b6bb5e, 0x4793a210, 0x496af3e2,
+  0x4b3c8c12, 0x4d084651,
+  0x4ecdfec7, 0x508d9211, 0x5246dd49, 0x53f9be05, 0x55a6125c, 0x574bb8e6,
+  0x58ea90c4, 0x5a82799a,
+  0x5c13539b, 0x5d9cff83, 0x5f1f5ea1, 0x609a52d3, 0x620dbe8b, 0x637984d4,
+  0x64dd8950, 0x6639b03b,
+  0x678dde6e, 0x68d9f964, 0x6a1de737, 0x6b598ea3, 0x6c8cd70b, 0x6db7a87a,
+  0x6ed9eba1, 0x6ff389df,
+  0x71046d3e, 0x720c8075, 0x730baeed, 0x7401e4c1, 0x74ef0ebc, 0x75d31a61,
+  0x76adf5e6, 0x777f903c,
+  0x7847d909, 0x7906c0b0, 0x79bc384d, 0x7a6831ba, 0x7b0a9f8d, 0x7ba3751d,
+  0x7c32a67e, 0x7cb82885,
+  0x7d33f0ca, 0x7da5f5a5, 0x7e0e2e32, 0x7e6c9251, 0x7ec11aa5, 0x7f0bc097,
+  0x7f4c7e54, 0x7f834ed0,
+  0x7fb02dc6, 0x7fd317b4, 0x7fec09e3, 0x7ffb0260, 0x7fffffff, 0x7ffb0260,
+  0x7fec09e3, 0x7fd317b4,
+  0x7fb02dc6, 0x7f834ed0, 0x7f4c7e54, 0x7f0bc097, 0x7ec11aa5, 0x7e6c9251,
+  0x7e0e2e32, 0x7da5f5a5,
+  0x7d33f0ca, 0x7cb82885, 0x7c32a67e, 0x7ba3751d, 0x7b0a9f8d, 0x7a6831ba,
+  0x79bc384d, 0x7906c0b0,
+  0x7847d909, 0x777f903c, 0x76adf5e6, 0x75d31a61, 0x74ef0ebc, 0x7401e4c1,
+  0x730baeed, 0x720c8075,
+  0x71046d3e, 0x6ff389df, 0x6ed9eba1, 0x6db7a87a, 0x6c8cd70b, 0x6b598ea3,
+  0x6a1de737, 0x68d9f964,
+  0x678dde6e, 0x6639b03b, 0x64dd8950, 0x637984d4, 0x620dbe8b, 0x609a52d3,
+  0x5f1f5ea1, 0x5d9cff83,
+  0x5c13539b, 0x5a82799a, 0x58ea90c4, 0x574bb8e6, 0x55a6125c, 0x53f9be05,
+  0x5246dd49, 0x508d9211,
+  0x4ecdfec7, 0x4d084651, 0x4b3c8c12, 0x496af3e2, 0x4793a210, 0x45b6bb5e,
+  0x43d464fb, 0x41ecc484,
+  0x40000000, 0x3e0e3ddc, 0x3c17a4e8, 0x3a1c5c57, 0x381c8bb5, 0x36185aee,
+  0x340ff242, 0x32037a45,
+  0x2ff31bde, 0x2ddf0040, 0x2bc750e9, 0x29ac37a0, 0x278dde6e, 0x256c6f9f,
+  0x234815ba, 0x2120fb83,
+  0x1ef74bf3, 0x1ccb3237, 0x1a9cd9ac, 0x186c6ddd, 0x163a1a7e, 0x14060b68,
+  0x11d06c97, 0xf996a26,
+  0xd61304e, 0xb27eb5c, 0x8edc7b7, 0x6b2f1d2, 0x4779632, 0x23be165, 0x0,
+  0xfdc41e9b,
+  0xfb8869ce, 0xf94d0e2e, 0xf7123849, 0xf4d814a4, 0xf29ecfb2, 0xf06695da,
+  0xee2f9369, 0xebf9f498,
+  0xe9c5e582, 0xe7939223, 0xe5632654, 0xe334cdc9, 0xe108b40d, 0xdedf047d,
+  0xdcb7ea46, 0xda939061,
+  0xd8722192, 0xd653c860, 0xd438af17, 0xd220ffc0, 0xd00ce422, 0xcdfc85bb,
+  0xcbf00dbe, 0xc9e7a512,
+  0xc7e3744b, 0xc5e3a3a9, 0xc3e85b18, 0xc1f1c224, 0xc0000000, 0xbe133b7c,
+  0xbc2b9b05, 0xba4944a2,
+  0xb86c5df0, 0xb6950c1e, 0xb4c373ee, 0xb2f7b9af, 0xb1320139, 0xaf726def,
+  0xadb922b7, 0xac0641fb,
+  0xaa59eda4, 0xa8b4471a, 0xa7156f3c, 0xa57d8666, 0xa3ecac65, 0xa263007d,
+  0xa0e0a15f, 0x9f65ad2d,
+  0x9df24175, 0x9c867b2c, 0x9b2276b0, 0x99c64fc5, 0x98722192, 0x9726069c,
+  0x95e218c9, 0x94a6715d,
+  0x937328f5, 0x92485786, 0x9126145f, 0x900c7621, 0x8efb92c2, 0x8df37f8b,
+  0x8cf45113, 0x8bfe1b3f,
+  0x8b10f144, 0x8a2ce59f, 0x89520a1a, 0x88806fc4, 0x87b826f7, 0x86f93f50,
+  0x8643c7b3, 0x8597ce46,
+  0x84f56073, 0x845c8ae3, 0x83cd5982, 0x8347d77b, 0x82cc0f36, 0x825a0a5b,
+  0x81f1d1ce, 0x81936daf,
+  0x813ee55b, 0x80f43f69, 0x80b381ac, 0x807cb130, 0x804fd23a, 0x802ce84c,
+  0x8013f61d, 0x8004fda0,
+
+};
+
+
+/**   
+ * @brief  Q31 sin_cos function.  
+ * @param[in]  theta    scaled input value in degrees   
+ * @param[out] *pSinVal points to the processed sine output.   
+ * @param[out] *pCosVal points to the processed cosine output.   
+ * @return none.  
+ *   
+ * The Q31 input value is in the range [-1 +1) and is mapped to a degree value in the range [-180 180).  
+ *   
+ */
+
+
+void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal)
+{
+  q31_t x0;                                      /* Nearest input value */
+  q31_t y0, y1;                                  /* Nearest output values */
+  q31_t xSpacing = INPUT_SPACING;                /* Spaing between inputs */
+  uint32_t i;                                    /* Index */
+  q31_t oneByXSpacing;                           /* 1/ xSpacing value */
+  q31_t out;                                     /* temporary variable */
+  uint32_t sign_bits;                            /* No.of sign bits */
+  uint32_t firstX = 0x80000000;                  /* First X value */
+
+  /* Calculation of index */
+  i = ((uint32_t) theta - firstX) / (uint32_t) xSpacing;
+
+  /* Calculation of first nearest input value */
+  x0 = (q31_t) firstX + ((q31_t) i * xSpacing);
+
+  /* Reading nearest sine output values from table */
+  y0 = sinTableQ31[i];
+  y1 = sinTableQ31[i + 1u];
+
+  /* Calculation of 1/(x1-x0) */
+  /* (x1-x0) is xSpacing which is fixed value */
+  sign_bits = 8u;
+  oneByXSpacing = 0x5A000000;
+
+  /* Calculation of (theta - x0)/(x1-x0) */
+  out =
+    (((q31_t) (((q63_t) (theta - x0) * oneByXSpacing) >> 32)) << sign_bits);
+
+  /* Calculation of y0 + (y1 - y0) * ((theta - x0)/(x1-x0)) */
+  *pSinVal = y0 + ((q31_t) (((q63_t) (y1 - y0) * out) >> 30));
+
+  /* Reading nearest cosine output values from table */
+  y0 = cosTableQ31[i];
+  y1 = cosTableQ31[i + 1u];
+
+  /* Calculation of y0 + (y1 - y0) * ((theta - x0)/(x1-x0)) */
+  *pCosVal = y0 + ((q31_t) (((q63_t) (y1 - y0) * out) >> 30));
+
+}
+
+/**   
+ * @} end of SinCos group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c
new file mode 100644
index 000000000..59f787732
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c
@@ -0,0 +1,254 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cos_f32.c   
+*   
+* Description:	Fast cosine calculation for floating-point values.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+/**   
+ * @ingroup groupFastMath   
+ */
+
+/**   
+ * @defgroup cos Cosine   
+ *   
+ * Computes the trigonometric cosine function using a combination of table lookup  
+ * and cubic interpolation.  There are separate functions for  
+ * Q15, Q31, and floating-point data types.  
+ * The input to the floating-point version is in radians while the  
+ * fixed-point Q15 and Q31 have a scaled input with the range  
+ * [0 1) mapping to [0 2*pi).  
+ *  
+ * The implementation is based on table lookup using 256 values together with cubic interpolation.  
+ * The steps used are:  
+ *  -# Calculation of the nearest integer table index  
+ *  -# Fetch the four table values a, b, c, and d    
+ *  -# Compute the fractional portion (fract) of the table index.  
+ *  -# Calculation of wa, wb, wc, wd   
+ *  -# The final result equals a*wa + b*wb + c*wc + d*wd  
+ *  
+ * where  
+ * 
   
+ *    a=Table[index-1];   
+ *    b=Table[index+0];   
+ *    c=Table[index+1];   
+ *    d=Table[index+2];   
+ * 
  
+ * and  
+ * 
   
+ *    wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;   
+ *    wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;   
+ *    wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;   
+ *    wd=(1/6)*fract.^3 - (1/6)*fract;   
+ * 
   
+ */
+
+ /**   
+ * @addtogroup cos   
+ * @{   
+ */
+
+
+/**   
+* \par   
+* Example code for Generation of Cos Table:  
+* tableSize = 256;   
+* 
for(n = -1; n < (tableSize + 1); n++)   
+* {   
+*	cosTable[n+1]= cos(2*pi*n/tableSize);   
+* } 
   
+* where pi value is  3.14159265358979   
+*/
+
+static const float32_t cosTable[259] = {
+  0.999698817729949950f, 1.000000000000000000f, 0.999698817729949950f,
+  0.998795449733734130f, 0.997290432453155520f, 0.995184719562530520f,
+  0.992479562759399410f, 0.989176511764526370f,
+  0.985277652740478520f, 0.980785250663757320f, 0.975702106952667240f,
+  0.970031261444091800f, 0.963776051998138430f, 0.956940352916717530f,
+  0.949528157711029050f, 0.941544055938720700f,
+  0.932992815971374510f, 0.923879504203796390f, 0.914209783077239990f,
+  0.903989315032958980f, 0.893224298954010010f, 0.881921291351318360f,
+  0.870086967945098880f, 0.857728600502014160f,
+  0.844853579998016360f, 0.831469595432281490f, 0.817584812641143800f,
+  0.803207516670227050f, 0.788346409797668460f, 0.773010432720184330f,
+  0.757208824157714840f, 0.740951120853424070f,
+  0.724247097969055180f, 0.707106769084930420f, 0.689540565013885500f,
+  0.671558976173400880f, 0.653172850608825680f, 0.634393274784088130f,
+  0.615231573581695560f, 0.595699310302734380f,
+  0.575808167457580570f, 0.555570244789123540f, 0.534997642040252690f,
+  0.514102756977081300f, 0.492898195981979370f, 0.471396744251251220f,
+  0.449611335992813110f, 0.427555084228515630f,
+  0.405241310596466060f, 0.382683426141738890f, 0.359895050525665280f,
+  0.336889863014221190f, 0.313681751489639280f, 0.290284663438797000f,
+  0.266712754964828490f, 0.242980182170867920f,
+  0.219101235270500180f, 0.195090323686599730f, 0.170961886644363400f,
+  0.146730467677116390f, 0.122410677373409270f, 0.098017141222953796f,
+  0.073564566671848297f, 0.049067676067352295f,
+  0.024541229009628296f, 0.000000000000000061f, -0.024541229009628296f,
+  -0.049067676067352295f, -0.073564566671848297f, -0.098017141222953796f,
+  -0.122410677373409270f, -0.146730467677116390f,
+  -0.170961886644363400f, -0.195090323686599730f, -0.219101235270500180f,
+  -0.242980182170867920f, -0.266712754964828490f, -0.290284663438797000f,
+  -0.313681751489639280f, -0.336889863014221190f,
+  -0.359895050525665280f, -0.382683426141738890f, -0.405241310596466060f,
+  -0.427555084228515630f, -0.449611335992813110f, -0.471396744251251220f,
+  -0.492898195981979370f, -0.514102756977081300f,
+  -0.534997642040252690f, -0.555570244789123540f, -0.575808167457580570f,
+  -0.595699310302734380f, -0.615231573581695560f, -0.634393274784088130f,
+  -0.653172850608825680f, -0.671558976173400880f,
+  -0.689540565013885500f, -0.707106769084930420f, -0.724247097969055180f,
+  -0.740951120853424070f, -0.757208824157714840f, -0.773010432720184330f,
+  -0.788346409797668460f, -0.803207516670227050f,
+  -0.817584812641143800f, -0.831469595432281490f, -0.844853579998016360f,
+  -0.857728600502014160f, -0.870086967945098880f, -0.881921291351318360f,
+  -0.893224298954010010f, -0.903989315032958980f,
+  -0.914209783077239990f, -0.923879504203796390f, -0.932992815971374510f,
+  -0.941544055938720700f, -0.949528157711029050f, -0.956940352916717530f,
+  -0.963776051998138430f, -0.970031261444091800f,
+  -0.975702106952667240f, -0.980785250663757320f, -0.985277652740478520f,
+  -0.989176511764526370f, -0.992479562759399410f, -0.995184719562530520f,
+  -0.997290432453155520f, -0.998795449733734130f,
+  -0.999698817729949950f, -1.000000000000000000f, -0.999698817729949950f,
+  -0.998795449733734130f, -0.997290432453155520f, -0.995184719562530520f,
+  -0.992479562759399410f, -0.989176511764526370f,
+  -0.985277652740478520f, -0.980785250663757320f, -0.975702106952667240f,
+  -0.970031261444091800f, -0.963776051998138430f, -0.956940352916717530f,
+  -0.949528157711029050f, -0.941544055938720700f,
+  -0.932992815971374510f, -0.923879504203796390f, -0.914209783077239990f,
+  -0.903989315032958980f, -0.893224298954010010f, -0.881921291351318360f,
+  -0.870086967945098880f, -0.857728600502014160f,
+  -0.844853579998016360f, -0.831469595432281490f, -0.817584812641143800f,
+  -0.803207516670227050f, -0.788346409797668460f, -0.773010432720184330f,
+  -0.757208824157714840f, -0.740951120853424070f,
+  -0.724247097969055180f, -0.707106769084930420f, -0.689540565013885500f,
+  -0.671558976173400880f, -0.653172850608825680f, -0.634393274784088130f,
+  -0.615231573581695560f, -0.595699310302734380f,
+  -0.575808167457580570f, -0.555570244789123540f, -0.534997642040252690f,
+  -0.514102756977081300f, -0.492898195981979370f, -0.471396744251251220f,
+  -0.449611335992813110f, -0.427555084228515630f,
+  -0.405241310596466060f, -0.382683426141738890f, -0.359895050525665280f,
+  -0.336889863014221190f, -0.313681751489639280f, -0.290284663438797000f,
+  -0.266712754964828490f, -0.242980182170867920f,
+  -0.219101235270500180f, -0.195090323686599730f, -0.170961886644363400f,
+  -0.146730467677116390f, -0.122410677373409270f, -0.098017141222953796f,
+  -0.073564566671848297f, -0.049067676067352295f,
+  -0.024541229009628296f, -0.000000000000000184f, 0.024541229009628296f,
+  0.049067676067352295f, 0.073564566671848297f, 0.098017141222953796f,
+  0.122410677373409270f, 0.146730467677116390f,
+  0.170961886644363400f, 0.195090323686599730f, 0.219101235270500180f,
+  0.242980182170867920f, 0.266712754964828490f, 0.290284663438797000f,
+  0.313681751489639280f, 0.336889863014221190f,
+  0.359895050525665280f, 0.382683426141738890f, 0.405241310596466060f,
+  0.427555084228515630f, 0.449611335992813110f, 0.471396744251251220f,
+  0.492898195981979370f, 0.514102756977081300f,
+  0.534997642040252690f, 0.555570244789123540f, 0.575808167457580570f,
+  0.595699310302734380f, 0.615231573581695560f, 0.634393274784088130f,
+  0.653172850608825680f, 0.671558976173400880f,
+  0.689540565013885500f, 0.707106769084930420f, 0.724247097969055180f,
+  0.740951120853424070f, 0.757208824157714840f, 0.773010432720184330f,
+  0.788346409797668460f, 0.803207516670227050f,
+  0.817584812641143800f, 0.831469595432281490f, 0.844853579998016360f,
+  0.857728600502014160f, 0.870086967945098880f, 0.881921291351318360f,
+  0.893224298954010010f, 0.903989315032958980f,
+  0.914209783077239990f, 0.923879504203796390f, 0.932992815971374510f,
+  0.941544055938720700f, 0.949528157711029050f, 0.956940352916717530f,
+  0.963776051998138430f, 0.970031261444091800f,
+  0.975702106952667240f, 0.980785250663757320f, 0.985277652740478520f,
+  0.989176511764526370f, 0.992479562759399410f, 0.995184719562530520f,
+  0.997290432453155520f, 0.998795449733734130f,
+  0.999698817729949950f, 1.000000000000000000f, 0.999698817729949950f
+};
+
+/**  
+ * @brief  Fast approximation to the trigonometric cosine function for floating-point data.  
+ * @param[in] x input value in radians.  
+ * @return cos(x).  
+ */
+
+float32_t arm_cos_f32(
+  float32_t x)
+{
+  float32_t cosVal, fract, in;
+  uint32_t index;
+  uint32_t tableSize = (uint32_t) TABLE_SIZE;
+  float32_t wa, wb, wc, wd;
+  float32_t a, b, c, d;
+  float32_t *tablePtr;
+  int32_t n;
+
+  /* input x is in radians */
+  /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi */
+  in = x * 0.159154943092f;
+
+  /* Calculation of floor value of input */
+  n = (int32_t) in;
+
+  /* Make negative values towards -infinity */
+  if(x < 0.0f)
+  {
+    n = n - 1;
+  }
+
+  /* Map input value to [0 1] */
+  in = in - (float32_t) n;
+
+  /* Calculation of index of the table */
+  index = (uint32_t) (tableSize * in);
+
+  /* fractional value calculation */
+  fract = ((float32_t) tableSize * in) - (float32_t) index;
+
+  /* Initialise table pointer */
+  tablePtr = (float32_t *) & cosTable[index];
+
+  /* Read four nearest values of input value from the cos table */
+  a = *tablePtr++;
+  b = *tablePtr++;
+  c = *tablePtr++;
+  d = *tablePtr++;
+
+  /* Cubic interpolation process */
+  wa = -(((0.166666667f) * fract) * (fract * fract)) +
+    (((0.5f) * (fract * fract)) - ((0.3333333333333f) * fract));
+  wb = ((((0.5f) * fract) * (fract * fract)) - (fract * fract)) +
+    (-((0.5f) * fract) + 1.0f);
+  wc = -(((0.5f) * fract) * (fract * fract)) +
+    (((0.5f) * (fract * fract)) + fract);
+  wd = (((0.166666667f) * fract) * (fract * fract)) -
+    ((0.166666667f) * fract);
+
+  /* Calculate cos value */
+  cosVal = ((a * wa) + (b * wb)) + ((c * wc) + (d * wd));
+
+  /* Return the output value */
+  return (cosVal);
+
+}
+
+/**   
+ * @} end of cos group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c
new file mode 100644
index 000000000..6e804c30e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c
@@ -0,0 +1,189 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cos_q15.c   
+*   
+* Description:	Fast cosine calculation for Q15 values.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFastMath   
+ */
+
+ /**   
+ * @addtogroup cos   
+ * @{   
+ */
+
+/**  
+* \par   
+* Table Values are in Q15(1.15 Fixed point format) and generation is done in three steps   
+* \par   
+* First Generate cos values in floating point:   
+* tableSize = 256;    
+* 
for(n = -1; n < (tableSize + 1); n++)   
+* {   
+*	cosTable[n+1]= cos(2*pi*n/tableSize);   
+* }
  
+* where pi value is  3.14159265358979   
+* \par   
+* Secondly Convert Floating point to Q15(Fixed point):   
+*	(cosTable[i] * pow(2, 15))   
+* \par   
+* Finally Rounding to nearest integer is done   
+* 	cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5);   
+*/
+
+static const q15_t cosTableQ15[259] = {
+  0x7ff6, 0x7fff, 0x7ff6, 0x7fd9, 0x7fa7, 0x7f62, 0x7f0a, 0x7e9d,
+  0x7e1e, 0x7d8a, 0x7ce4, 0x7c2a, 0x7b5d, 0x7a7d, 0x798a, 0x7885,
+  0x776c, 0x7642, 0x7505, 0x73b6, 0x7255, 0x70e3, 0x6f5f, 0x6dca,
+  0x6c24, 0x6a6e, 0x68a7, 0x66d0, 0x64e9, 0x62f2, 0x60ec, 0x5ed7,
+  0x5cb4, 0x5a82, 0x5843, 0x55f6, 0x539b, 0x5134, 0x4ec0, 0x4c40,
+  0x49b4, 0x471d, 0x447b, 0x41ce, 0x3f17, 0x3c57, 0x398d, 0x36ba,
+  0x33df, 0x30fc, 0x2e11, 0x2b1f, 0x2827, 0x2528, 0x2224, 0x1f1a,
+  0x1c0c, 0x18f9, 0x15e2, 0x12c8, 0xfab, 0xc8c, 0x96b, 0x648,
+  0x324, 0x0, 0xfcdc, 0xf9b8, 0xf695, 0xf374, 0xf055, 0xed38,
+  0xea1e, 0xe707, 0xe3f4, 0xe0e6, 0xdddc, 0xdad8, 0xd7d9, 0xd4e1,
+  0xd1ef, 0xcf04, 0xcc21, 0xc946, 0xc673, 0xc3a9, 0xc0e9, 0xbe32,
+  0xbb85, 0xb8e3, 0xb64c, 0xb3c0, 0xb140, 0xaecc, 0xac65, 0xaa0a,
+  0xa7bd, 0xa57e, 0xa34c, 0xa129, 0x9f14, 0x9d0e, 0x9b17, 0x9930,
+  0x9759, 0x9592, 0x93dc, 0x9236, 0x90a1, 0x8f1d, 0x8dab, 0x8c4a,
+  0x8afb, 0x89be, 0x8894, 0x877b, 0x8676, 0x8583, 0x84a3, 0x83d6,
+  0x831c, 0x8276, 0x81e2, 0x8163, 0x80f6, 0x809e, 0x8059, 0x8027,
+  0x800a, 0x8000, 0x800a, 0x8027, 0x8059, 0x809e, 0x80f6, 0x8163,
+  0x81e2, 0x8276, 0x831c, 0x83d6, 0x84a3, 0x8583, 0x8676, 0x877b,
+  0x8894, 0x89be, 0x8afb, 0x8c4a, 0x8dab, 0x8f1d, 0x90a1, 0x9236,
+  0x93dc, 0x9592, 0x9759, 0x9930, 0x9b17, 0x9d0e, 0x9f14, 0xa129,
+  0xa34c, 0xa57e, 0xa7bd, 0xaa0a, 0xac65, 0xaecc, 0xb140, 0xb3c0,
+  0xb64c, 0xb8e3, 0xbb85, 0xbe32, 0xc0e9, 0xc3a9, 0xc673, 0xc946,
+  0xcc21, 0xcf04, 0xd1ef, 0xd4e1, 0xd7d9, 0xdad8, 0xdddc, 0xe0e6,
+  0xe3f4, 0xe707, 0xea1e, 0xed38, 0xf055, 0xf374, 0xf695, 0xf9b8,
+  0xfcdc, 0x0, 0x324, 0x648, 0x96b, 0xc8c, 0xfab, 0x12c8,
+  0x15e2, 0x18f9, 0x1c0c, 0x1f1a, 0x2224, 0x2528, 0x2827, 0x2b1f,
+  0x2e11, 0x30fc, 0x33df, 0x36ba, 0x398d, 0x3c57, 0x3f17, 0x41ce,
+  0x447b, 0x471d, 0x49b4, 0x4c40, 0x4ec0, 0x5134, 0x539b, 0x55f6,
+  0x5843, 0x5a82, 0x5cb4, 0x5ed7, 0x60ec, 0x62f2, 0x64e9, 0x66d0,
+  0x68a7, 0x6a6e, 0x6c24, 0x6dca, 0x6f5f, 0x70e3, 0x7255, 0x73b6,
+  0x7505, 0x7642, 0x776c, 0x7885, 0x798a, 0x7a7d, 0x7b5d, 0x7c2a,
+  0x7ce4, 0x7d8a, 0x7e1e, 0x7e9d, 0x7f0a, 0x7f62, 0x7fa7, 0x7fd9,
+  0x7ff6, 0x7fff, 0x7ff6
+};
+
+
+/**  
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.  
+ * @param[in] x Scaled input value in radians.  
+ * @return  cos(x).  
+ *  
+ * The Q15 input value is in the range [0 +1) and is mapped to a radian value in the range [0 2*pi).  
+ */
+
+q15_t arm_cos_q15(
+  q15_t x)
+{
+  q31_t cosVal;                                  /* Temporary variable for output */
+  q15_t *tablePtr;                               /* Pointer to table */
+  q15_t in, in2;                                 /* Temporary variables for input */
+  q31_t wa, wb, wc, wd;                          /* Cubic interpolation coefficients */
+  q15_t a, b, c, d;                              /* Four nearest output values */
+  q15_t fract, fractCube, fractSquare;           /* Variables for fractional value */
+  q15_t oneBy6 = 0x1555;                         /* Fixed point value of 1/6 */
+  q15_t tableSpacing = TABLE_SPACING_Q15;        /* Table spacing */
+  int32_t index;                                 /* Index variable */
+
+  in = x;
+
+  /* Calculate the nearest index */
+  index = (int32_t) in / tableSpacing;
+
+  /* Calculate the nearest value of input */
+  in2 = (q15_t) index *tableSpacing;
+
+  /* Calculation of fractional value */
+  fract = (in - in2) << 8;
+
+  /* fractSquare = fract * fract */
+  fractSquare = (q15_t) ((fract * fract) >> 15);
+
+  /* fractCube = fract * fract * fract */
+  fractCube = (q15_t) ((fractSquare * fract) >> 15);
+
+  /* Initialise table pointer */
+  tablePtr = (q15_t *) & cosTableQ15[index];
+
+  /* Cubic interpolation process */
+  /* Calculation of wa */
+  /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAA)*fract; */
+  wa = (q31_t) oneBy6 *fractCube;
+  wa += (q31_t) 0x2AAA *fract;
+  wa = -(wa >> 15);
+  wa += (fractSquare >> 1u);
+
+  /* Read first nearest value of output from the cos table */
+  a = *tablePtr++;
+
+  /* cosVal = a * wa */
+  cosVal = a * wa;
+
+  /* Calculation of wb */
+  wb = (((fractCube >> 1u) - fractSquare) - (fract >> 1u)) + 0x7FFF;
+
+  /* Read second nearest value of output from the cos table */
+  b = *tablePtr++;
+
+  /*      cosVal += b*wb */
+  cosVal += b * wb;
+
+  /* Calculation of wc */
+  wc = -(q31_t) fractCube + fractSquare;
+  wc = (wc >> 1u) + fract;
+
+  /* Read third nearest value of output from the cos table */
+  c = *tablePtr++;
+
+  /*      cosVal += c*wc */
+  cosVal += c * wc;
+
+  /* Calculation of wd */
+  /* wd = (oneBy6)*fractCube - (oneBy6)*fract; */
+  fractCube = fractCube - fract;
+  wd = ((q15_t) (((q31_t) oneBy6 * fractCube) >> 15));
+
+  /* Read fourth nearest value of output from the cos table */
+  d = *tablePtr++;
+
+  /* cosVal += d*wd; */
+  cosVal += d * wd;
+
+  /* Return the output value in 1.15(q15) format */
+  return ((q15_t) (cosVal >> 15u));
+
+}
+
+/**   
+ * @} end of cos group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c
new file mode 100644
index 000000000..bcbda5908
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c
@@ -0,0 +1,225 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cos_q31.c   
+*   
+* Description:	Fast cosine calculation for Q31 values.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFastMath   
+ */
+
+ /**   
+ * @addtogroup cos   
+ * @{   
+ */
+
+/**   
+ * \par   
+ * Table Values are in Q31(1.31 Fixed point format) and generation is done in three steps   
+ * First Generate cos values in floating point:   
+ * tableSize = 256;     
+ * 
for(n = -1; n < (tableSize + 1); n++)   
+ * {   
+ *	cosTable[n+1]= cos(2*pi*n/tableSize);   
+ * } 
    
+ * where pi value is  3.14159265358979   
+ * \par   
+ * Secondly Convert Floating point to Q31(Fixed point):   
+ *	(cosTable[i] * pow(2, 31))   
+ * \par   
+ * Finally Rounding to nearest integer is done   
+ * 	cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5);   
+ */
+
+
+static const q31_t cosTableQ31[259] = {
+  0x7ff62182, 0x7fffffff, 0x7ff62182, 0x7fd8878e, 0x7fa736b4, 0x7f62368f,
+  0x7f0991c4, 0x7e9d55fc,
+  0x7e1d93ea, 0x7d8a5f40, 0x7ce3ceb2, 0x7c29fbee, 0x7b5d039e, 0x7a7d055b,
+  0x798a23b1, 0x78848414,
+  0x776c4edb, 0x7641af3d, 0x7504d345, 0x73b5ebd1, 0x72552c85, 0x70e2cbc6,
+  0x6f5f02b2, 0x6dca0d14,
+  0x6c242960, 0x6a6d98a4, 0x68a69e81, 0x66cf8120, 0x64e88926, 0x62f201ac,
+  0x60ec3830, 0x5ed77c8a,
+  0x5cb420e0, 0x5a82799a, 0x5842dd54, 0x55f5a4d2, 0x539b2af0, 0x5133cc94,
+  0x4ebfe8a5, 0x4c3fdff4,
+  0x49b41533, 0x471cece7, 0x447acd50, 0x41ce1e65, 0x3f1749b8, 0x3c56ba70,
+  0x398cdd32, 0x36ba2014,
+  0x33def287, 0x30fbc54d, 0x2e110a62, 0x2b1f34eb, 0x2826b928, 0x25280c5e,
+  0x2223a4c5, 0x1f19f97b,
+  0x1c0b826a, 0x18f8b83c, 0x15e21445, 0x12c8106f, 0xfab272b, 0xc8bd35e,
+  0x96a9049, 0x647d97c,
+  0x3242abf, 0x0, 0xfcdbd541, 0xf9b82684, 0xf6956fb7, 0xf3742ca2, 0xf054d8d5,
+  0xed37ef91,
+  0xea1debbb, 0xe70747c4, 0xe3f47d96, 0xe0e60685, 0xdddc5b3b, 0xdad7f3a2,
+  0xd7d946d8, 0xd4e0cb15,
+  0xd1eef59e, 0xcf043ab3, 0xcc210d79, 0xc945dfec, 0xc67322ce, 0xc3a94590,
+  0xc0e8b648, 0xbe31e19b,
+  0xbb8532b0, 0xb8e31319, 0xb64beacd, 0xb3c0200c, 0xb140175b, 0xaecc336c,
+  0xac64d510, 0xaa0a5b2e,
+  0xa7bd22ac, 0xa57d8666, 0xa34bdf20, 0xa1288376, 0x9f13c7d0, 0x9d0dfe54,
+  0x9b1776da, 0x99307ee0,
+  0x9759617f, 0x9592675c, 0x93dbd6a0, 0x9235f2ec, 0x90a0fd4e, 0x8f1d343a,
+  0x8daad37b, 0x8c4a142f,
+  0x8afb2cbb, 0x89be50c3, 0x8893b125, 0x877b7bec, 0x8675dc4f, 0x8582faa5,
+  0x84a2fc62, 0x83d60412,
+  0x831c314e, 0x8275a0c0, 0x81e26c16, 0x8162aa04, 0x80f66e3c, 0x809dc971,
+  0x8058c94c, 0x80277872,
+  0x8009de7e, 0x80000000, 0x8009de7e, 0x80277872, 0x8058c94c, 0x809dc971,
+  0x80f66e3c, 0x8162aa04,
+  0x81e26c16, 0x8275a0c0, 0x831c314e, 0x83d60412, 0x84a2fc62, 0x8582faa5,
+  0x8675dc4f, 0x877b7bec,
+  0x8893b125, 0x89be50c3, 0x8afb2cbb, 0x8c4a142f, 0x8daad37b, 0x8f1d343a,
+  0x90a0fd4e, 0x9235f2ec,
+  0x93dbd6a0, 0x9592675c, 0x9759617f, 0x99307ee0, 0x9b1776da, 0x9d0dfe54,
+  0x9f13c7d0, 0xa1288376,
+  0xa34bdf20, 0xa57d8666, 0xa7bd22ac, 0xaa0a5b2e, 0xac64d510, 0xaecc336c,
+  0xb140175b, 0xb3c0200c,
+  0xb64beacd, 0xb8e31319, 0xbb8532b0, 0xbe31e19b, 0xc0e8b648, 0xc3a94590,
+  0xc67322ce, 0xc945dfec,
+  0xcc210d79, 0xcf043ab3, 0xd1eef59e, 0xd4e0cb15, 0xd7d946d8, 0xdad7f3a2,
+  0xdddc5b3b, 0xe0e60685,
+  0xe3f47d96, 0xe70747c4, 0xea1debbb, 0xed37ef91, 0xf054d8d5, 0xf3742ca2,
+  0xf6956fb7, 0xf9b82684,
+  0xfcdbd541, 0x0, 0x3242abf, 0x647d97c, 0x96a9049, 0xc8bd35e, 0xfab272b,
+  0x12c8106f,
+  0x15e21445, 0x18f8b83c, 0x1c0b826a, 0x1f19f97b, 0x2223a4c5, 0x25280c5e,
+  0x2826b928, 0x2b1f34eb,
+  0x2e110a62, 0x30fbc54d, 0x33def287, 0x36ba2014, 0x398cdd32, 0x3c56ba70,
+  0x3f1749b8, 0x41ce1e65,
+  0x447acd50, 0x471cece7, 0x49b41533, 0x4c3fdff4, 0x4ebfe8a5, 0x5133cc94,
+  0x539b2af0, 0x55f5a4d2,
+  0x5842dd54, 0x5a82799a, 0x5cb420e0, 0x5ed77c8a, 0x60ec3830, 0x62f201ac,
+  0x64e88926, 0x66cf8120,
+  0x68a69e81, 0x6a6d98a4, 0x6c242960, 0x6dca0d14, 0x6f5f02b2, 0x70e2cbc6,
+  0x72552c85, 0x73b5ebd1,
+  0x7504d345, 0x7641af3d, 0x776c4edb, 0x78848414, 0x798a23b1, 0x7a7d055b,
+  0x7b5d039e, 0x7c29fbee,
+  0x7ce3ceb2, 0x7d8a5f40, 0x7e1d93ea, 0x7e9d55fc, 0x7f0991c4, 0x7f62368f,
+  0x7fa736b4, 0x7fd8878e,
+  0x7ff62182, 0x7fffffff, 0x7ff62182
+};
+
+/**  
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.  
+ * @param[in] x Scaled input value in radians.  
+ * @return  cos(x).  
+ *  
+ * The Q31 input value is in the range [0 +1) and is mapped to a radian value in the range [0 2*pi).  
+ */
+
+q31_t arm_cos_q31(
+  q31_t x)
+{
+  q31_t cosVal, in, in2;                         /* Temporary variables for input, output */
+  q31_t wa, wb, wc, wd;                          /* Cubic interpolation coefficients */
+  q31_t a, b, c, d;                              /* Four nearest output values */
+  q31_t *tablePtr;                               /* Pointer to table */
+  q31_t fract, fractCube, fractSquare;           /* Temporary values for fractional values */
+  q31_t oneBy6 = 0x15555555;                     /* Fixed point value of 1/6 */
+  q31_t tableSpacing = TABLE_SPACING_Q31;        /* Table spacing */
+  q31_t temp;                                    /* Temporary variable for intermediate process */
+  uint32_t index;                                /* Index variable */
+
+  in = x;
+
+  /* Calculate the nearest index */
+  index = in / tableSpacing;
+
+  /* Calculate the nearest value of input */
+  in2 = ((q31_t) index) * tableSpacing;
+
+  /* Calculation of fractional value */
+  fract = (in - in2) << 8;
+
+  /* fractSquare = fract * fract */
+  fractSquare = ((q31_t) (((q63_t) fract * fract) >> 32));
+  fractSquare = fractSquare << 1;
+
+  /* fractCube = fract * fract * fract */
+  fractCube = ((q31_t) (((q63_t) fractSquare * fract) >> 32));
+  fractCube = fractCube << 1;
+
+  /* Initialise table pointer */
+  tablePtr = (q31_t *) & cosTableQ31[index];
+
+  /* Cubic interpolation process */
+  /* Calculation of wa */
+  /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAAAAAA)*fract; */
+  wa = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
+  temp = 0x2AAAAAAA;
+  wa = (q31_t) ((((q63_t) wa << 32) + ((q63_t) temp * fract)) >> 32);
+  wa = -(wa << 1u);
+  wa += (fractSquare >> 1u);
+
+  /* Read first nearest value of output from the cos table */
+  a = *tablePtr++;
+
+  /* cosVal = a*wa */
+  cosVal = ((q31_t) (((q63_t) a * wa) >> 32));
+
+  /* q31(1.31) Fixed point value of 1 */
+  temp = 0x7FFFFFFF;
+
+  /* Calculation of wb */
+  wb = ((fractCube >> 1u) - (fractSquare + (fract >> 1u))) + temp;
+  /* Read second nearest value of output from the cos table */
+  b = *tablePtr++;
+
+  /*      cosVal += b*wb */
+  cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) b * (wb))) >> 32);
+
+  /* Calculation of wc */
+  wc = -fractCube + fractSquare;
+  wc = (wc >> 1u) + fract;
+  /* Read third nearest values of output value from the cos table */
+  c = *tablePtr++;
+
+  /*      cosVal += c*wc */
+  cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) c * (wc))) >> 32);
+
+  /* Calculation of wd */
+  /* wd = (oneBy6)*fractCube - (oneBy6)*fract; */
+  fractCube = fractCube - fract;
+  wd = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
+  wd = (wd << 1u);
+
+  /* Read fourth nearest value of output from the cos table */
+  d = *tablePtr++;
+
+  /* cosVal += d*wd; */
+  cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) d * (wd))) >> 32);
+
+  /* convert cosVal in 2.30 format to 1.31 format */
+  return (cosVal << 1u);
+
+}
+
+/**   
+ * @} end of cos group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c
new file mode 100644
index 000000000..877cfa422
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c
@@ -0,0 +1,257 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_sin_f32.c   
+*   
+* Description:	Fast sine calculation for floating-point values.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFastMath   
+ */
+
+/**   
+ * @defgroup sin Sine   
+ *   
+ * Computes the trigonometric sine function using a combination of table lookup  
+ * and cubic interpolation.  There are separate functions for  
+ * Q15, Q31, and floating-point data types.  
+ * The input to the floating-point version is in radians while the  
+ * fixed-point Q15 and Q31 have a scaled input with the range  
+ * [0 1) mapping to [0 2*pi).  
+ *  
+ * The implementation is based on table lookup using 256 values together with cubic interpolation.  
+ * The steps used are:  
+ *  -# Calculation of the nearest integer table index  
+ *  -# Fetch the four table values a, b, c, and d    
+ *  -# Compute the fractional portion (fract) of the table index.  
+ *  -# Calculation of wa, wb, wc, wd   
+ *  -# The final result equals a*wa + b*wb + c*wc + d*wd  
+ *  
+ * where  
+ * 
   
+ *    a=Table[index-1];   
+ *    b=Table[index+0];   
+ *    c=Table[index+1];   
+ *    d=Table[index+2];   
+ * 
  
+ * and  
+ * 
   
+ *    wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;   
+ *    wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;   
+ *    wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;   
+ *    wd=(1/6)*fract.^3 - (1/6)*fract;   
+ * 
   
+ */
+
+/**   
+ * @addtogroup sin   
+ * @{   
+ */
+
+
+/**  
+ * \par   
+ * Example code for Generation of Floating-point Sin Table:  
+ * tableSize = 256;   
+ * 
for(n = -1; n < (tableSize + 1); n++)   
+ * {   
+ *	sinTable[n+1]=sin(2*pi*n/tableSize);   
+ * }
   
+ * \par   
+ * where pi value is  3.14159265358979   
+ */
+
+static const float32_t sinTable[259] = {
+  -0.024541229009628296f, 0.000000000000000000f, 0.024541229009628296f,
+  0.049067676067352295f, 0.073564566671848297f, 0.098017141222953796f,
+  0.122410677373409270f, 0.146730467677116390f,
+  0.170961886644363400f, 0.195090323686599730f, 0.219101235270500180f,
+  0.242980182170867920f, 0.266712754964828490f, 0.290284663438797000f,
+  0.313681751489639280f, 0.336889863014221190f,
+  0.359895050525665280f, 0.382683426141738890f, 0.405241310596466060f,
+  0.427555084228515630f, 0.449611335992813110f, 0.471396744251251220f,
+  0.492898195981979370f, 0.514102756977081300f,
+  0.534997642040252690f, 0.555570244789123540f, 0.575808167457580570f,
+  0.595699310302734380f, 0.615231573581695560f, 0.634393274784088130f,
+  0.653172850608825680f, 0.671558976173400880f,
+  0.689540565013885500f, 0.707106769084930420f, 0.724247097969055180f,
+  0.740951120853424070f, 0.757208824157714840f, 0.773010432720184330f,
+  0.788346409797668460f, 0.803207516670227050f,
+  0.817584812641143800f, 0.831469595432281490f, 0.844853579998016360f,
+  0.857728600502014160f, 0.870086967945098880f, 0.881921291351318360f,
+  0.893224298954010010f, 0.903989315032958980f,
+  0.914209783077239990f, 0.923879504203796390f, 0.932992815971374510f,
+  0.941544055938720700f, 0.949528157711029050f, 0.956940352916717530f,
+  0.963776051998138430f, 0.970031261444091800f,
+  0.975702106952667240f, 0.980785250663757320f, 0.985277652740478520f,
+  0.989176511764526370f, 0.992479562759399410f, 0.995184719562530520f,
+  0.997290432453155520f, 0.998795449733734130f,
+  0.999698817729949950f, 1.000000000000000000f, 0.999698817729949950f,
+  0.998795449733734130f, 0.997290432453155520f, 0.995184719562530520f,
+  0.992479562759399410f, 0.989176511764526370f,
+  0.985277652740478520f, 0.980785250663757320f, 0.975702106952667240f,
+  0.970031261444091800f, 0.963776051998138430f, 0.956940352916717530f,
+  0.949528157711029050f, 0.941544055938720700f,
+  0.932992815971374510f, 0.923879504203796390f, 0.914209783077239990f,
+  0.903989315032958980f, 0.893224298954010010f, 0.881921291351318360f,
+  0.870086967945098880f, 0.857728600502014160f,
+  0.844853579998016360f, 0.831469595432281490f, 0.817584812641143800f,
+  0.803207516670227050f, 0.788346409797668460f, 0.773010432720184330f,
+  0.757208824157714840f, 0.740951120853424070f,
+  0.724247097969055180f, 0.707106769084930420f, 0.689540565013885500f,
+  0.671558976173400880f, 0.653172850608825680f, 0.634393274784088130f,
+  0.615231573581695560f, 0.595699310302734380f,
+  0.575808167457580570f, 0.555570244789123540f, 0.534997642040252690f,
+  0.514102756977081300f, 0.492898195981979370f, 0.471396744251251220f,
+  0.449611335992813110f, 0.427555084228515630f,
+  0.405241310596466060f, 0.382683426141738890f, 0.359895050525665280f,
+  0.336889863014221190f, 0.313681751489639280f, 0.290284663438797000f,
+  0.266712754964828490f, 0.242980182170867920f,
+  0.219101235270500180f, 0.195090323686599730f, 0.170961886644363400f,
+  0.146730467677116390f, 0.122410677373409270f, 0.098017141222953796f,
+  0.073564566671848297f, 0.049067676067352295f,
+  0.024541229009628296f, 0.000000000000000122f, -0.024541229009628296f,
+  -0.049067676067352295f, -0.073564566671848297f, -0.098017141222953796f,
+  -0.122410677373409270f, -0.146730467677116390f,
+  -0.170961886644363400f, -0.195090323686599730f, -0.219101235270500180f,
+  -0.242980182170867920f, -0.266712754964828490f, -0.290284663438797000f,
+  -0.313681751489639280f, -0.336889863014221190f,
+  -0.359895050525665280f, -0.382683426141738890f, -0.405241310596466060f,
+  -0.427555084228515630f, -0.449611335992813110f, -0.471396744251251220f,
+  -0.492898195981979370f, -0.514102756977081300f,
+  -0.534997642040252690f, -0.555570244789123540f, -0.575808167457580570f,
+  -0.595699310302734380f, -0.615231573581695560f, -0.634393274784088130f,
+  -0.653172850608825680f, -0.671558976173400880f,
+  -0.689540565013885500f, -0.707106769084930420f, -0.724247097969055180f,
+  -0.740951120853424070f, -0.757208824157714840f, -0.773010432720184330f,
+  -0.788346409797668460f, -0.803207516670227050f,
+  -0.817584812641143800f, -0.831469595432281490f, -0.844853579998016360f,
+  -0.857728600502014160f, -0.870086967945098880f, -0.881921291351318360f,
+  -0.893224298954010010f, -0.903989315032958980f,
+  -0.914209783077239990f, -0.923879504203796390f, -0.932992815971374510f,
+  -0.941544055938720700f, -0.949528157711029050f, -0.956940352916717530f,
+  -0.963776051998138430f, -0.970031261444091800f,
+  -0.975702106952667240f, -0.980785250663757320f, -0.985277652740478520f,
+  -0.989176511764526370f, -0.992479562759399410f, -0.995184719562530520f,
+  -0.997290432453155520f, -0.998795449733734130f,
+  -0.999698817729949950f, -1.000000000000000000f, -0.999698817729949950f,
+  -0.998795449733734130f, -0.997290432453155520f, -0.995184719562530520f,
+  -0.992479562759399410f, -0.989176511764526370f,
+  -0.985277652740478520f, -0.980785250663757320f, -0.975702106952667240f,
+  -0.970031261444091800f, -0.963776051998138430f, -0.956940352916717530f,
+  -0.949528157711029050f, -0.941544055938720700f,
+  -0.932992815971374510f, -0.923879504203796390f, -0.914209783077239990f,
+  -0.903989315032958980f, -0.893224298954010010f, -0.881921291351318360f,
+  -0.870086967945098880f, -0.857728600502014160f,
+  -0.844853579998016360f, -0.831469595432281490f, -0.817584812641143800f,
+  -0.803207516670227050f, -0.788346409797668460f, -0.773010432720184330f,
+  -0.757208824157714840f, -0.740951120853424070f,
+  -0.724247097969055180f, -0.707106769084930420f, -0.689540565013885500f,
+  -0.671558976173400880f, -0.653172850608825680f, -0.634393274784088130f,
+  -0.615231573581695560f, -0.595699310302734380f,
+  -0.575808167457580570f, -0.555570244789123540f, -0.534997642040252690f,
+  -0.514102756977081300f, -0.492898195981979370f, -0.471396744251251220f,
+  -0.449611335992813110f, -0.427555084228515630f,
+  -0.405241310596466060f, -0.382683426141738890f, -0.359895050525665280f,
+  -0.336889863014221190f, -0.313681751489639280f, -0.290284663438797000f,
+  -0.266712754964828490f, -0.242980182170867920f,
+  -0.219101235270500180f, -0.195090323686599730f, -0.170961886644363400f,
+  -0.146730467677116390f, -0.122410677373409270f, -0.098017141222953796f,
+  -0.073564566671848297f, -0.049067676067352295f,
+  -0.024541229009628296f, -0.000000000000000245f, 0.024541229009628296f
+};
+
+
+/**  
+ * @brief  Fast approximation to the trigonometric sine function for floating-point data.  
+ * @param[in] x input value in radians.  
+ * @return  sin(x).  
+ */
+
+float32_t arm_sin_f32(
+  float32_t x)
+{
+  float32_t sinVal, fract, in;                   /* Temporary variables for input, output */
+  uint32_t index;                                /* Index variable */
+  uint32_t tableSize = (uint32_t) TABLE_SIZE;    /* Initialise tablesize */
+  float32_t wa, wb, wc, wd;                      /* Cubic interpolation coefficients */
+  float32_t a, b, c, d;                          /* Four nearest output values */
+  float32_t *tablePtr;                           /* Pointer to table */
+  int32_t n;
+
+  /* input x is in radians */
+  /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi */
+  in = x * 0.159154943092f;
+
+  /* Calculation of floor value of input */
+  n = (int32_t) in;
+
+  /* Make negative values towards -infinity */
+  if(x < 0.0f)
+  {
+    n = n - 1;
+  }
+
+  /* Map input value to [0 1] */
+  in = in - (float32_t) n;
+
+  /* Calculation of index of the table */
+  index = (uint32_t) (tableSize * in);
+
+  /* fractional value calculation */
+  fract = ((float32_t) tableSize * in) - (float32_t) index;
+
+  /* Initialise table pointer */
+  tablePtr = (float32_t *) & sinTable[index];
+
+  /* Read four nearest values of output value from the sin table */
+  a = *tablePtr++;
+  b = *tablePtr++;
+  c = *tablePtr++;
+  d = *tablePtr++;
+
+  /* Cubic interpolation process */
+  wa = -(((0.166666667f) * (fract * (fract * fract))) +
+         ((0.3333333333333f) * fract)) + ((0.5f) * (fract * fract));
+  wb = (((0.5f) * (fract * (fract * fract))) -
+        ((fract * fract) + ((0.5f) * fract))) + 1.0f;
+  wc = (-((0.5f) * (fract * (fract * fract))) +
+        ((0.5f) * (fract * fract))) + fract;
+  wd = ((0.166666667f) * (fract * (fract * fract))) -
+    ((0.166666667f) * fract);
+
+  /* Calculate sin value */
+  sinVal = ((a * wa) + (b * wb)) + ((c * wc) + (d * wd));
+
+  /* Return the output value */
+  return (sinVal);
+
+}
+
+/**   
+ * @} end of sin group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c
new file mode 100644
index 000000000..8f3f3650b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c
@@ -0,0 +1,192 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_sin_q15.c   
+*   
+* Description:	Fast sine calculation for Q15 values.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFastMath   
+ */
+
+ /**   
+ * @addtogroup sin   
+ * @{   
+ */
+
+
+/**   
+ * \par   
+ * Example code for Generation of Q15 Sin Table:  
+ * \par   
+ * 
tableSize = 256;   
+ * for(n = -1; n < (tableSize + 1); n++)   
+ * {   
+ *	sinTable[n+1]=sin(2*pi*n/tableSize);   
+ * } 
   
+ * where pi value is  3.14159265358979   
+ * \par   
+ * Convert Floating point to Q15(Fixed point):   
+ *	(sinTable[i] * pow(2, 15))   
+ * \par   
+ * rounding to nearest integer is done   
+ * 	sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);   
+ */
+
+
+static const q15_t sinTableQ15[259] = {
+  0xfcdc, 0x0, 0x324, 0x648, 0x96b, 0xc8c, 0xfab, 0x12c8,
+  0x15e2, 0x18f9, 0x1c0c, 0x1f1a, 0x2224, 0x2528, 0x2827, 0x2b1f,
+  0x2e11, 0x30fc, 0x33df, 0x36ba, 0x398d, 0x3c57, 0x3f17, 0x41ce,
+  0x447b, 0x471d, 0x49b4, 0x4c40, 0x4ec0, 0x5134, 0x539b, 0x55f6,
+  0x5843, 0x5a82, 0x5cb4, 0x5ed7, 0x60ec, 0x62f2, 0x64e9, 0x66d0,
+  0x68a7, 0x6a6e, 0x6c24, 0x6dca, 0x6f5f, 0x70e3, 0x7255, 0x73b6,
+  0x7505, 0x7642, 0x776c, 0x7885, 0x798a, 0x7a7d, 0x7b5d, 0x7c2a,
+  0x7ce4, 0x7d8a, 0x7e1e, 0x7e9d, 0x7f0a, 0x7f62, 0x7fa7, 0x7fd9,
+  0x7ff6, 0x7fff, 0x7ff6, 0x7fd9, 0x7fa7, 0x7f62, 0x7f0a, 0x7e9d,
+  0x7e1e, 0x7d8a, 0x7ce4, 0x7c2a, 0x7b5d, 0x7a7d, 0x798a, 0x7885,
+  0x776c, 0x7642, 0x7505, 0x73b6, 0x7255, 0x70e3, 0x6f5f, 0x6dca,
+  0x6c24, 0x6a6e, 0x68a7, 0x66d0, 0x64e9, 0x62f2, 0x60ec, 0x5ed7,
+  0x5cb4, 0x5a82, 0x5843, 0x55f6, 0x539b, 0x5134, 0x4ec0, 0x4c40,
+  0x49b4, 0x471d, 0x447b, 0x41ce, 0x3f17, 0x3c57, 0x398d, 0x36ba,
+  0x33df, 0x30fc, 0x2e11, 0x2b1f, 0x2827, 0x2528, 0x2224, 0x1f1a,
+  0x1c0c, 0x18f9, 0x15e2, 0x12c8, 0xfab, 0xc8c, 0x96b, 0x648,
+  0x324, 0x0, 0xfcdc, 0xf9b8, 0xf695, 0xf374, 0xf055, 0xed38,
+  0xea1e, 0xe707, 0xe3f4, 0xe0e6, 0xdddc, 0xdad8, 0xd7d9, 0xd4e1,
+  0xd1ef, 0xcf04, 0xcc21, 0xc946, 0xc673, 0xc3a9, 0xc0e9, 0xbe32,
+  0xbb85, 0xb8e3, 0xb64c, 0xb3c0, 0xb140, 0xaecc, 0xac65, 0xaa0a,
+  0xa7bd, 0xa57e, 0xa34c, 0xa129, 0x9f14, 0x9d0e, 0x9b17, 0x9930,
+  0x9759, 0x9592, 0x93dc, 0x9236, 0x90a1, 0x8f1d, 0x8dab, 0x8c4a,
+  0x8afb, 0x89be, 0x8894, 0x877b, 0x8676, 0x8583, 0x84a3, 0x83d6,
+  0x831c, 0x8276, 0x81e2, 0x8163, 0x80f6, 0x809e, 0x8059, 0x8027,
+  0x800a, 0x8000, 0x800a, 0x8027, 0x8059, 0x809e, 0x80f6, 0x8163,
+  0x81e2, 0x8276, 0x831c, 0x83d6, 0x84a3, 0x8583, 0x8676, 0x877b,
+  0x8894, 0x89be, 0x8afb, 0x8c4a, 0x8dab, 0x8f1d, 0x90a1, 0x9236,
+  0x93dc, 0x9592, 0x9759, 0x9930, 0x9b17, 0x9d0e, 0x9f14, 0xa129,
+  0xa34c, 0xa57e, 0xa7bd, 0xaa0a, 0xac65, 0xaecc, 0xb140, 0xb3c0,
+  0xb64c, 0xb8e3, 0xbb85, 0xbe32, 0xc0e9, 0xc3a9, 0xc673, 0xc946,
+  0xcc21, 0xcf04, 0xd1ef, 0xd4e1, 0xd7d9, 0xdad8, 0xdddc, 0xe0e6,
+  0xe3f4, 0xe707, 0xea1e, 0xed38, 0xf055, 0xf374, 0xf695, 0xf9b8,
+  0xfcdc, 0x0, 0x324
+};
+
+
+/**  
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.  
+ * @param[in] x Scaled input value in radians.  
+ * @return  sin(x).  
+ *  
+ * The Q15 input value is in the range [0 +1) and is mapped to a radian value in the range [0 2*pi).  
+ */
+
+q15_t arm_sin_q15(
+  q15_t x)
+{
+  q31_t sinVal;                                  /* Temporary variables output */
+  q15_t *tablePtr;                               /* Pointer to table */
+  q15_t fract, in, in2;                          /* Temporary variables for input, output */
+  q31_t wa, wb, wc, wd;                          /* Cubic interpolation coefficients */
+  q15_t a, b, c, d;                              /* Four nearest output values */
+  q15_t fractCube, fractSquare;                  /* Temporary values for fractional value */
+  q15_t oneBy6 = 0x1555;                         /* Fixed point value of 1/6 */
+  q15_t tableSpacing = TABLE_SPACING_Q15;        /* Table spacing */
+  int32_t index;                                 /* Index variable */
+
+  in = x;
+
+  /* Calculate the nearest index */
+  index = (int32_t) in / tableSpacing;
+
+  /* Calculate the nearest value of input */
+  in2 = (q15_t) ((index) * tableSpacing);
+
+  /* Calculation of fractional value */
+  fract = (in - in2) << 8;
+
+  /* fractSquare = fract * fract */
+  fractSquare = (q15_t) ((fract * fract) >> 15);
+
+  /* fractCube = fract * fract * fract */
+  fractCube = (q15_t) ((fractSquare * fract) >> 15);
+
+  /* Initialise table pointer */
+  tablePtr = (q15_t *) & sinTableQ15[index];
+
+  /* Cubic interpolation process */
+  /* Calculation of wa */
+  /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAA)*fract; */
+  wa = (q31_t) oneBy6 *fractCube;
+  wa += (q31_t) 0x2AAA *fract;
+  wa = -(wa >> 15);
+  wa += ((q31_t) fractSquare >> 1u);
+
+  /* Read first nearest value of output from the sin table */
+  a = *tablePtr++;
+
+  /* sinVal = a * wa */
+  sinVal = a * wa;
+
+  /* Calculation of wb */
+  wb = (((q31_t) fractCube >> 1u) - (q31_t) fractSquare) -
+    (((q31_t) fract >> 1u) - 0x7FFF);
+
+  /* Read second nearest value of output from the sin table */
+  b = *tablePtr++;
+
+  /*      sinVal += b*wb */
+  sinVal += b * wb;
+
+
+  /* Calculation of wc */
+  wc = -(q31_t) fractCube + fractSquare;
+  wc = (wc >> 1u) + fract;
+
+  /* Read third nearest value of output from the sin table */
+  c = *tablePtr++;
+
+  /*      sinVal += c*wc */
+  sinVal += c * wc;
+
+  /* Calculation of wd */
+  /* wd = (oneBy6)*fractCube - (oneBy6)*fract; */
+  fractCube = fractCube - fract;
+  wd = ((q15_t) (((q31_t) oneBy6 * fractCube) >> 15));
+
+  /* Read fourth nearest value of output from the sin table */
+  d = *tablePtr++;
+
+  /* sinVal += d*wd; */
+  sinVal += d * wd;
+
+  /* Return the output value in 1.15(q15) format */
+  return ((q15_t) (sinVal >> 15u));
+
+}
+
+/**   
+ * @} end of sin group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c
new file mode 100644
index 000000000..28b58ab3d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c
@@ -0,0 +1,227 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_sin_q31.c   
+*   
+* Description:	Fast sine calculation for Q31 values.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFastMath   
+ */
+
+ /**   
+ * @addtogroup sin   
+ * @{   
+ */
+
+/**  
+ * \par   
+ * Tables generated are in Q31(1.31 Fixed point format)   
+ * Generation of sin values in floating point:   
+ * 
tableSize = 256;     
+ * for(n = -1; n < (tableSize + 1); n++)   
+ * {   
+ *	sinTable[n+1]= sin(2*pi*n/tableSize);   
+ * } 
   
+ * where pi value is  3.14159265358979   
+ * \par   
+ * Convert Floating point to Q31(Fixed point):   
+ *	(sinTable[i] * pow(2, 31))   
+ * \par   
+ * rounding to nearest integer is done   
+ * 	sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);   
+ */
+
+static const q31_t sinTableQ31[259] = {
+  0xfcdbd541, 0x0, 0x3242abf, 0x647d97c, 0x96a9049, 0xc8bd35e, 0xfab272b,
+  0x12c8106f,
+  0x15e21445, 0x18f8b83c, 0x1c0b826a, 0x1f19f97b, 0x2223a4c5, 0x25280c5e,
+  0x2826b928, 0x2b1f34eb,
+  0x2e110a62, 0x30fbc54d, 0x33def287, 0x36ba2014, 0x398cdd32, 0x3c56ba70,
+  0x3f1749b8, 0x41ce1e65,
+  0x447acd50, 0x471cece7, 0x49b41533, 0x4c3fdff4, 0x4ebfe8a5, 0x5133cc94,
+  0x539b2af0, 0x55f5a4d2,
+  0x5842dd54, 0x5a82799a, 0x5cb420e0, 0x5ed77c8a, 0x60ec3830, 0x62f201ac,
+  0x64e88926, 0x66cf8120,
+  0x68a69e81, 0x6a6d98a4, 0x6c242960, 0x6dca0d14, 0x6f5f02b2, 0x70e2cbc6,
+  0x72552c85, 0x73b5ebd1,
+  0x7504d345, 0x7641af3d, 0x776c4edb, 0x78848414, 0x798a23b1, 0x7a7d055b,
+  0x7b5d039e, 0x7c29fbee,
+  0x7ce3ceb2, 0x7d8a5f40, 0x7e1d93ea, 0x7e9d55fc, 0x7f0991c4, 0x7f62368f,
+  0x7fa736b4, 0x7fd8878e,
+  0x7ff62182, 0x7fffffff, 0x7ff62182, 0x7fd8878e, 0x7fa736b4, 0x7f62368f,
+  0x7f0991c4, 0x7e9d55fc,
+  0x7e1d93ea, 0x7d8a5f40, 0x7ce3ceb2, 0x7c29fbee, 0x7b5d039e, 0x7a7d055b,
+  0x798a23b1, 0x78848414,
+  0x776c4edb, 0x7641af3d, 0x7504d345, 0x73b5ebd1, 0x72552c85, 0x70e2cbc6,
+  0x6f5f02b2, 0x6dca0d14,
+  0x6c242960, 0x6a6d98a4, 0x68a69e81, 0x66cf8120, 0x64e88926, 0x62f201ac,
+  0x60ec3830, 0x5ed77c8a,
+  0x5cb420e0, 0x5a82799a, 0x5842dd54, 0x55f5a4d2, 0x539b2af0, 0x5133cc94,
+  0x4ebfe8a5, 0x4c3fdff4,
+  0x49b41533, 0x471cece7, 0x447acd50, 0x41ce1e65, 0x3f1749b8, 0x3c56ba70,
+  0x398cdd32, 0x36ba2014,
+  0x33def287, 0x30fbc54d, 0x2e110a62, 0x2b1f34eb, 0x2826b928, 0x25280c5e,
+  0x2223a4c5, 0x1f19f97b,
+  0x1c0b826a, 0x18f8b83c, 0x15e21445, 0x12c8106f, 0xfab272b, 0xc8bd35e,
+  0x96a9049, 0x647d97c,
+  0x3242abf, 0x0, 0xfcdbd541, 0xf9b82684, 0xf6956fb7, 0xf3742ca2, 0xf054d8d5,
+  0xed37ef91,
+  0xea1debbb, 0xe70747c4, 0xe3f47d96, 0xe0e60685, 0xdddc5b3b, 0xdad7f3a2,
+  0xd7d946d8, 0xd4e0cb15,
+  0xd1eef59e, 0xcf043ab3, 0xcc210d79, 0xc945dfec, 0xc67322ce, 0xc3a94590,
+  0xc0e8b648, 0xbe31e19b,
+  0xbb8532b0, 0xb8e31319, 0xb64beacd, 0xb3c0200c, 0xb140175b, 0xaecc336c,
+  0xac64d510, 0xaa0a5b2e,
+  0xa7bd22ac, 0xa57d8666, 0xa34bdf20, 0xa1288376, 0x9f13c7d0, 0x9d0dfe54,
+  0x9b1776da, 0x99307ee0,
+  0x9759617f, 0x9592675c, 0x93dbd6a0, 0x9235f2ec, 0x90a0fd4e, 0x8f1d343a,
+  0x8daad37b, 0x8c4a142f,
+  0x8afb2cbb, 0x89be50c3, 0x8893b125, 0x877b7bec, 0x8675dc4f, 0x8582faa5,
+  0x84a2fc62, 0x83d60412,
+  0x831c314e, 0x8275a0c0, 0x81e26c16, 0x8162aa04, 0x80f66e3c, 0x809dc971,
+  0x8058c94c, 0x80277872,
+  0x8009de7e, 0x80000000, 0x8009de7e, 0x80277872, 0x8058c94c, 0x809dc971,
+  0x80f66e3c, 0x8162aa04,
+  0x81e26c16, 0x8275a0c0, 0x831c314e, 0x83d60412, 0x84a2fc62, 0x8582faa5,
+  0x8675dc4f, 0x877b7bec,
+  0x8893b125, 0x89be50c3, 0x8afb2cbb, 0x8c4a142f, 0x8daad37b, 0x8f1d343a,
+  0x90a0fd4e, 0x9235f2ec,
+  0x93dbd6a0, 0x9592675c, 0x9759617f, 0x99307ee0, 0x9b1776da, 0x9d0dfe54,
+  0x9f13c7d0, 0xa1288376,
+  0xa34bdf20, 0xa57d8666, 0xa7bd22ac, 0xaa0a5b2e, 0xac64d510, 0xaecc336c,
+  0xb140175b, 0xb3c0200c,
+  0xb64beacd, 0xb8e31319, 0xbb8532b0, 0xbe31e19b, 0xc0e8b648, 0xc3a94590,
+  0xc67322ce, 0xc945dfec,
+  0xcc210d79, 0xcf043ab3, 0xd1eef59e, 0xd4e0cb15, 0xd7d946d8, 0xdad7f3a2,
+  0xdddc5b3b, 0xe0e60685,
+  0xe3f47d96, 0xe70747c4, 0xea1debbb, 0xed37ef91, 0xf054d8d5, 0xf3742ca2,
+  0xf6956fb7, 0xf9b82684,
+  0xfcdbd541, 0x0, 0x3242abf
+};
+
+
+/**  
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.  
+ * @param[in] x Scaled input value in radians.  
+ * @return  sin(x).  
+ *  
+ * The Q31 input value is in the range [0 +1) and is mapped to a radian value in the range [0 2*pi).  
+ */
+
+q31_t arm_sin_q31(
+  q31_t x)
+{
+  q31_t sinVal, in, in2;                         /* Temporary variables for input, output */
+  uint32_t index;                                /* Index variables */
+  q31_t wa, wb, wc, wd;                          /* Cubic interpolation coefficients */
+  q31_t a, b, c, d;                              /* Four nearest output values */
+  q31_t *tablePtr;                               /* Pointer to table */
+  q31_t fract, fractCube, fractSquare;           /* Temporary values for fractional values */
+  q31_t oneBy6 = 0x15555555;                     /* Fixed point value of 1/6 */
+  q31_t tableSpacing = TABLE_SPACING_Q31;        /* Table spacing */
+  q31_t temp;                                    /* Temporary variable for intermediate process */
+
+  in = x;
+
+  /* Calculate the nearest index */
+  index = (uint32_t) in / (uint32_t) tableSpacing;
+
+  /* Calculate the nearest value of input */
+  in2 = (q31_t) index *tableSpacing;
+
+  /* Calculation of fractional value */
+  fract = (in - in2) << 8;
+
+  /* fractSquare = fract * fract */
+  fractSquare = ((q31_t) (((q63_t) fract * fract) >> 32));
+  fractSquare = fractSquare << 1;
+
+  /* fractCube = fract * fract * fract */
+  fractCube = ((q31_t) (((q63_t) fractSquare * fract) >> 32));
+  fractCube = fractCube << 1;
+
+  /* Initialise table pointer */
+  tablePtr = (q31_t *) & sinTableQ31[index];
+
+  /* Cubic interpolation process */
+  /* Calculation of wa */
+  /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAAAAAA)*fract; */
+  wa = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
+  temp = 0x2AAAAAAA;
+  wa = (q31_t) ((((q63_t) wa << 32) + ((q63_t) temp * fract)) >> 32);
+  wa = -(wa << 1u);
+  wa += (fractSquare >> 1u);
+
+  /* Read first nearest value of output from the sin table */
+  a = *tablePtr++;
+
+  /* sinVal = a*wa */
+  sinVal = ((q31_t) (((q63_t) a * wa) >> 32));
+
+  /* q31(1.31) Fixed point value of 1 */
+  temp = 0x7FFFFFFF;
+
+  /* Calculation of wb */
+  wb = ((fractCube >> 1u) - (fractSquare + (fract >> 1u))) + temp;
+
+  /* Read second nearest value of output from the sin table */
+  b = *tablePtr++;
+
+  /*  sinVal += b*wb */
+  sinVal = (q31_t) ((((q63_t) sinVal << 32) + (q63_t) b * (wb)) >> 32);
+
+  /* Calculation of wc */
+  wc = -fractCube + fractSquare;
+  wc = (wc >> 1u) + fract;
+
+  /* Read third nearest value of output from the sin table */
+  c = *tablePtr++;
+
+  /*      sinVal += c*wc */
+  sinVal = (q31_t) ((((q63_t) sinVal << 32) + ((q63_t) c * wc)) >> 32);
+
+  /* Calculation of wd */
+  /* wd = (oneBy6) * fractCube - (oneBy6) * fract; */
+  fractCube = fractCube - fract;
+  wd = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
+  wd = (wd << 1u);
+
+  /* Read fourth nearest value of output from the sin table */
+  d = *tablePtr++;
+
+  /* sinVal += d*wd; */
+  sinVal = (q31_t) ((((q63_t) sinVal << 32) + ((q63_t) d * wd)) >> 32);
+
+  /* convert sinVal in 2.30 format to 1.31 format */
+  return (sinVal << 1u);
+
+}
+
+/**   
+ * @} end of sin group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c
new file mode 100644
index 000000000..bcd5287f9
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c
@@ -0,0 +1,178 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_sqrt_q15.c   
+*   
+* Description:	Q15 square root function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+
+/**   
+ * @ingroup groupFastMath   
+ */
+
+/**   
+ * @addtogroup SQRT   
+ * @{   
+ */
+
+  /**  
+   * @brief  Q15 square root function.  
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.  
+   * @param[out]  *pOut  square root of input value.  
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if  
+   * in is negative value and returns zero output for negative values.  
+   */
+
+arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut)
+{
+  q31_t prevOut;
+  q15_t oneByOut;
+  uint32_t sign_bits;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t out;
+
+  if(in > 0)
+  {
+    /* run for ten iterations */
+
+    /* Take initial guess as half of the input and first iteration */
+    out = ((q31_t) in >> 1u) + 0x3FFF;
+
+    /* Calculation of reciprocal of out */
+    /* oneByOut contains reciprocal of out which is in 2.14 format   
+       and oneByOut should be upscaled by signBits */
+    sign_bits = arm_recip_q15((q15_t) out, &oneByOut, armRecipTableQ15);
+
+    /* 0.5 * (out) */
+    out = out >> 1u;
+    /* prevOut = 0.5 * out + (in * (oneByOut << signBits))) */
+    prevOut = out + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    /* Third iteration */
+    sign_bits = arm_recip_q15((q15_t) prevOut, &oneByOut, armRecipTableQ15);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    sign_bits = arm_recip_q15((q15_t) out, &oneByOut, armRecipTableQ15);
+    out = out >> 1u;
+    prevOut = out + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    /* Fifth iteration */
+    sign_bits = arm_recip_q15((q15_t) prevOut, &oneByOut, armRecipTableQ15);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    sign_bits = arm_recip_q15((q15_t) out, &oneByOut, armRecipTableQ15);
+    out = out >> 1u;
+    prevOut = out + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    /* Seventh iteration */
+    sign_bits = arm_recip_q15((q15_t) prevOut, &oneByOut, armRecipTableQ15);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    sign_bits = arm_recip_q15((q15_t) out, &oneByOut, armRecipTableQ15);
+    out = out >> 1u;
+    prevOut = out + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    sign_bits = arm_recip_q15((q15_t) prevOut, &oneByOut, armRecipTableQ15);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    /* tenth iteration */
+    sign_bits = arm_recip_q15((q15_t) out, &oneByOut, armRecipTableQ15);
+    out = out >> 1u;
+    *pOut = out + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    return (ARM_MATH_SUCCESS);
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t out, loopVar;                            /* Temporary variable for output, loop variable */
+  if(in > 0)
+  {
+    /* run for ten iterations */
+
+    /* Take initial guess as half of the input and first iteration */
+    out = ((q31_t) in >> 1u) + 0x3FFF;
+
+    /* Calculation of reciprocal of out */
+
+    /* oneByOut contains reciprocal of out which is in 2.14 format   
+       and oneByOut should be upscaled by sign bits */
+    sign_bits = arm_recip_q15((q15_t) out, &oneByOut, armRecipTableQ15);
+
+    /* 0.5 * (out) */
+    out = out >> 1u;
+    /* prevOut = 0.5 * out + (in * oneByOut) << signbits))) */
+    prevOut = out + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    /* loop for third iteration to tenth iteration */
+
+    for (loopVar = 1; loopVar <= 8; loopVar++)
+    {
+
+      sign_bits = arm_recip_q15((q15_t) prevOut, &oneByOut, armRecipTableQ15);
+      /* 0.5 * (prevOut) */
+      prevOut = prevOut >> 1u;
+      /* prevOut = 0.5 * prevOut+ (in * oneByOut) << signbits))) */
+      out =
+        prevOut + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+      /* prevOut      = out */
+      prevOut = out;
+
+    }
+    /* output is moved to pOut pointer */
+    *pOut = prevOut;
+
+    return (ARM_MATH_SUCCESS);
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  else
+  {
+
+    *pOut = 0;
+    return (ARM_MATH_ARGUMENT_ERROR);
+  }
+
+}
+
+/**   
+ * @} end of SQRT group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c
new file mode 100644
index 000000000..043678da3
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c
@@ -0,0 +1,199 @@
+/* ----------------------------------------------------------------------  
+* Copyright (C) 2010 ARM Limited. All rights reserved.  
+*  
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*  
+* Project: 	    CMSIS DSP Library  
+* Title:		arm_sqrt_q31.c  
+*  
+* Description:	Q31 square root function. 
+*  
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.2 2010/11/11  
+*    Documentation updated.   
+*  
+* Version 1.0.1 2010/10/05   
+*    Production release and review comments incorporated.  
+*  
+* Version 1.0.0 2010/09/20   
+*    Production release and review comments incorporated. 
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**  
+ * @ingroup groupFastMath  
+ */
+
+/**  
+ * @addtogroup SQRT  
+ * @{  
+ */
+
+/** 
+ * @brief Q31 square root function. 
+ * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. 
+ * @param[out]  *pOut square root of input value. 
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if 
+ * in is negative value and returns zero output for negative values. 
+ */
+
+arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut)
+{
+  q63_t prevOut;
+  q31_t oneByOut;
+  uint32_t signBits;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q63_t out;
+
+  if(in > 0)
+  {
+
+    /* run for ten iterations */
+
+    /* Take initial guess as half of the input and first iteration */
+    out = (in >> 1) + 0x3FFFFFFF;
+
+    /* Calculation of reciprocal of out */
+    /* oneByOut contains reciprocal of out which is in 2.30 format  
+       and oneByOut should be upscaled by signBits */
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+
+    /* 0.5 * (out) */
+    out = out >> 1u;
+
+    /* prevOut = 0.5 * out + (in * (oneByOut << signBits))) */
+    prevOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    /* Third iteration */
+    signBits = arm_recip_q31((q31_t) prevOut, &oneByOut, armRecipTableQ31);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+    out = out >> 1u;
+    prevOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    /* Fifth iteration */
+    signBits = arm_recip_q31((q31_t) prevOut, &oneByOut, armRecipTableQ31);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+    out = out >> 1u;
+    prevOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    /* Seventh iteration */
+    signBits = arm_recip_q31((q31_t) prevOut, &oneByOut, armRecipTableQ31);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+    out = out >> 1u;
+    prevOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) prevOut, &oneByOut, armRecipTableQ31);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+    out = out >> 1u;
+    prevOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) prevOut, &oneByOut, armRecipTableQ31);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+    out = out >> 1u;
+    prevOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) prevOut, &oneByOut, armRecipTableQ31);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+    out = out >> 1u;
+    prevOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) prevOut, &oneByOut, armRecipTableQ31);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    /* tenth iteration */
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+    out = out >> 1u;
+    *pOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    return (ARM_MATH_SUCCESS);
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q63_t out, loopVar;                            /* Temporary variable for output, loop variable */
+  if(in > 0)
+  {
+
+    /* run for ten iterations */
+
+    /* Take initial guess as half of the input and first iteration */
+    out = (in >> 1) + 0x3FFFFFFF;
+
+    /* Calculation of reciprocal of out */
+    /* oneByOut contains reciprocal of out which is in 2.30 format   
+       and oneByOut should be upscaled by sign bits */
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+
+    /* 0.5 * (out) */
+    out = out >> 1u;
+
+    /* prevOut = 0.5 * out + (in * (oneByOut) << signbits) */
+    prevOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+
+    /* loop for third iteration to tength iteration */
+
+    for (loopVar = 1; loopVar <= 14; loopVar++)
+    {
+
+      signBits = arm_recip_q31((q31_t) prevOut, &oneByOut, armRecipTableQ31);
+      /* 0.5 * (prevOut) */
+      prevOut = prevOut >> 1u;
+      /* out = 0.5 * prevOut + (in * oneByOut) << signbits))) */
+      out = prevOut + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+      /* prevOut      = out */
+      prevOut = out;
+
+    }
+    /* output is moved to pOut pointer */
+    *pOut = prevOut;
+
+    return (ARM_MATH_SUCCESS);
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  else
+  {
+    *pOut = 0;
+    return (ARM_MATH_ARGUMENT_ERROR);
+  }
+}
+
+/**  
+ * @} end of SQRT group  
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
new file mode 100644
index 000000000..ff6239a9e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
@@ -0,0 +1,102 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df1_32x64_init_q31.c   
+*   
+* Description:	High precision Q31 Biquad cascade filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1_32x64   
+ * @{   
+ */
+
+/**   
+ * @details   
+ *   
+ * @param[in,out] *S           	points to an instance of the high precision Q31 Biquad cascade filter structure.   
+ * @param[in]     numStages     number of 2nd order stages in the filter.   
+ * @param[in]     *pCoeffs      points to the filter coefficients.   
+ * @param[in]     *pState       points to the state buffer.   
+ * @param[in]     postShift     Shift to be applied after the accumulator.  Varies according to the coefficients format.   
+ * @return        none   
+ *   
+ * Coefficient and State Ordering:   
+ *   
+ * \par   
+ * The coefficients are stored in the array pCoeffs in the following order:   
+ * 
   
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}   
+ * 
   
+ * where b1x and a1x are the coefficients for the first stage,   
+ * b2x and a2x are the coefficients for the second stage,   
+ * and so on.  The pCoeffs array contains a total of 5*numStages values.   
+ *   
+ * \par   
+ * The pState points to state variables array and size of each state variable is 1.63 format.   
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].   
+ * The state variables are arranged in the state array as:   
+ * 
   
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ * 
   
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.   
+ * The state array has a total length of 4*numStages values.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ */
+
+void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign postShift to be applied to the output */
+  S->postShift = postShift;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 4 * numStages */
+  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q63_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**   
+ * @} end of BiquadCascadeDF1_32x64 group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
new file mode 100644
index 000000000..73ff8b0d7
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
@@ -0,0 +1,476 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df1_32x64_q31.c   
+*   
+* Description:	High precision Q31 Biquad cascade filter processing function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup BiquadCascadeDF1_32x64 High Precision Q31 Biquad Cascade Filter   
+ *   
+ * This function implements a high precision Biquad cascade filter which operates on   
+ * Q31 data values.  The filter coefficients are in 1.31 format and the state variables   
+ * are in 1.63 format.  The double precision state variables reduce quantization noise   
+ * in the filter and provide a cleaner output.   
+ * These filters are particularly useful when implementing filters in which the   
+ * singularities are close to the unit circle.  This is common for low pass or high   
+ * pass filters with very low cutoff frequencies.   
+ *   
+ * The function operates on blocks of input and output data   
+ * and each call to the function processes blockSize samples through   
+ * the filter. pSrc and pDst points to input and output arrays   
+ * containing blockSize Q31 values.   
+ *   
+ * \par Algorithm   
+ * Each Biquad stage implements a second order filter using the difference equation:   
+ * 
   
+ *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+ * 
   
+ * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.   
+ * \image html Biquad.gif "Single Biquad filter stage"   
+ * Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.   
+ * Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.   
+ * Pay careful attention to the sign of the feedback coefficients.   
+ * Some design tools use the difference equation   
+ * 
   
+ *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]   
+ * 
   
+ * In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.   
+ *   
+ * \par   
+ * Higher order filters are realized as a cascade of second order sections.   
+ * numStages refers to the number of second order stages used.   
+ * For example, an 8th order filter would be realized with numStages=4 second order stages.   
+ * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"   
+ * A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).   
+ *   
+ * \par   
+ * The pState points to state variables array .   
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2] and each state variable in 1.63 format to improve precision.   
+ * The state variables are arranged in the array as:   
+ * 
   
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ * 
   
+ *   
+ * \par   
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.   
+ * The state array has a total length of 4*numStages values of data in 1.63 format.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ *   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.   
+ *   
+ * \par Init Function   
+ * There is also an associated initialization function which performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Set the values in the state buffer to zeros before static initialization.   
+ * For example, to statically initialize the filter instance structure use   
+ * 
   
+ *     arm_biquad_cas_df1_32x64_ins_q31 S1 = {numStages, pState, pCoeffs, postShift};   
+ * 
   
+ * where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer;   
+ * pCoeffs is the address of the coefficient buffer; postShift shift to be applied which is described in detail below.   
+ * \par Fixed-Point Behavior   
+ * Care must be taken while using Biquad Cascade 32x64 filter function.   
+ * Following issues must be considered:   
+ * - Scaling of coefficients   
+ * - Filter gain   
+ * - Overflow and saturation   
+ *   
+ * \par   
+ * Filter coefficients are represented as fractional values and   
+ * restricted to lie in the range [-1 +1).   
+ * The processing function has an additional scaling parameter postShift   
+ * which allows the filter coefficients to exceed the range [+1 -1).   
+ * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.   
+ * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"   
+ * This essentially scales the filter coefficients by 2^postShift.   
+ * For example, to realize the coefficients   
+ * 
   
+ *    {1.5, -0.8, 1.2, 1.6, -0.9}   
+ * 
   
+ * set the Coefficient array to:   
+ * 
   
+ *    {0.75, -0.4, 0.6, 0.8, -0.45}   
+ * 
   
+ * and set postShift=1   
+ *   
+ * \par   
+ * The second thing to keep in mind is the gain through the filter.   
+ * The frequency response of a Biquad filter is a function of its coefficients.   
+ * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.   
+ * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.   
+ * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.   
+ *   
+ * \par   
+ * The third item to consider is the overflow and saturation behavior of the fixed-point Q31 version.   
+ * This is described in the function specific documentation below.   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1_32x64   
+ * @{   
+ */
+
+/**   
+ * @details   
+   
+ * @param[in]  *S points to an instance of the high precision Q31 Biquad cascade filter.   
+ * @param[in]  *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in]  blockSize number of samples to process.   
+ * @return none.   
+ *   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around rather than clip.   
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).   
+ * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to   
+ * 1.31 format by discarding the low 32 bits.   
+ *   
+ * \par   
+ * Two related functions are provided in the CMSIS DSP library.   
+ * arm_biquad_cascade_df1_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q63 accumulator.   
+ * arm_biquad_cascade_df1_fast_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q31 accumulator.   
+ */
+
+void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /*  input pointer initialization  */
+  q31_t *pOut = pDst;                            /*  output pointer initialization */
+  q63_t *pState = S->pState;                     /*  state pointer initialization  */
+  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */
+  q63_t acc;                                     /*  accumulator                   */
+  q63_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
+  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
+  q63_t Xn;                                      /*  temporary input               */
+  int32_t shift = (int32_t) S->postShift + 1;    /*  Shift to be applied to the output */
+  uint32_t sample, stage = S->numStages;         /*  loop counters                     */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    /* The variable acc hold output value that is being computed and   
+     * stored in the destination buffer   
+     * acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+     */
+
+    sample = blockSize >> 2u;
+
+    /* First part of the processing with loop unrolling. Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* The value is shifted to the MSB to perform 32x64 multiplication */
+      Xn = Xn << 32;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = mult32x64(Xn, b0);
+      /* acc +=  b1 * x[n-1] */
+      acc += mult32x64(Xn1, b1);
+      /* acc +=  b[2] * x[n-2] */
+      acc += mult32x64(Xn2, b2);
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn1, a1);
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn2, a2);
+
+      /* The result is converted to 1.63 , Yn2 variable is reused */
+      Yn2 = acc << shift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *pOut++ = (q31_t) (acc >> (32 - shift));
+
+      /* Read the second input into Xn2, to reuse the value */
+      Xn2 = *pIn++;
+
+      /* The value is shifted to the MSB to perform 32x64 multiplication */
+      Xn2 = Xn2 << 32;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = mult32x64(Xn2, b0);
+      /* acc +=  b1 * x[n-1] */
+      acc += mult32x64(Xn, b1);
+      /* acc +=  b[2] * x[n-2] */
+      acc += mult32x64(Xn1, b2);
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn2, a1);
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn1, a2);
+
+      /* The result is converted to 1.63, Yn1 variable is reused */
+      Yn1 = acc << shift;
+
+      /* The result is converted to 1.31 */
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q31_t) (acc >> (32 - shift));
+
+      /* Read the third input into Xn1, to reuse the value */
+      Xn1 = *pIn++;
+
+      /* The value is shifted to the MSB to perform 32x64 multiplication */
+      Xn1 = Xn1 << 32;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = mult32x64(Xn1, b0);
+      /* acc +=  b1 * x[n-1] */
+      acc += mult32x64(Xn2, b1);
+      /* acc +=  b[2] * x[n-2] */
+      acc += mult32x64(Xn, b2);
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn1, a1);
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn2, a2);
+
+      /* The result is converted to 1.63, Yn2 variable is reused  */
+      Yn2 = acc << shift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *pOut++ = (q31_t) (acc >> (32 - shift));
+
+      /* Read the fourth input into Xn, to reuse the value */
+      Xn = *pIn++;
+
+      /* The value is shifted to the MSB to perform 32x64 multiplication */
+      Xn = Xn << 32;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = mult32x64(Xn, b0);
+      /* acc +=  b1 * x[n-1] */
+      acc += mult32x64(Xn1, b1);
+      /* acc +=  b[2] * x[n-2] */
+      acc += mult32x64(Xn2, b2);
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn2, a1);
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn1, a2);
+
+      /* The result is converted to 1.63, Yn1 variable is reused  */
+      Yn1 = acc << shift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *pOut++ = (q31_t) (acc >> (32 - shift));
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    sample = (blockSize & 0x3u);
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* The value is shifted to the MSB to perform 32x64 multiplication */
+      Xn = Xn << 32;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = mult32x64(Xn, b0);
+      /* acc +=  b1 * x[n-1] */
+      acc += mult32x64(Xn1, b1);
+      /* acc +=  b[2] * x[n-2] */
+      acc += mult32x64(Xn2, b2);
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn1, a1);
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn2, a2);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = acc << shift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *pOut++ = (q31_t) (acc >> (32 - shift));
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage output is given as input to the second stage. */
+    pIn = pDst;
+
+    /* Reset to destination buffer working pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* The variable acc hold output value that is being computed and       
+     * stored in the destination buffer           
+     * acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]           
+     */
+
+    sample = blockSize;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* The value is shifted to the MSB to perform 32x64 multiplication */
+      Xn = Xn << 32;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = mult32x64(Xn, b0);
+      /* acc +=  b1 * x[n-1] */
+      acc += mult32x64(Xn1, b1);
+      /* acc +=  b[2] * x[n-2] */
+      acc += mult32x64(Xn2, b2);
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn1, a1);
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn2, a2);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = acc << shift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *pOut++ = (q31_t) (acc >> (32 - shift));
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage output is given as input to the second stage. */
+    pIn = pDst;
+
+    /* Reset to destination buffer working pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+
+#endif /*    #ifndef ARM_MATH_CM0     */
+}
+
+  /**   
+   * @} end of BiquadCascadeDF1_32x64 group   
+   */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
new file mode 100644
index 000000000..bdfbf22fe
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
@@ -0,0 +1,418 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df1_f32.c   
+*   
+* Description:	Processing function for the   
+*               floating-point Biquad cascade DirectFormI(DF1) filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup BiquadCascadeDF1 Biquad Cascade IIR Filters Using Direct Form I Structure   
+ *   
+ * This set of functions implements arbitrary order recursive (IIR) filters.   
+ * The filters are implemented as a cascade of second order Biquad sections.   
+ * The functions support Q15, Q31 and floating-point data types. 
+ * Fast version of Q15 and Q31 also supported on CortexM4 and Cortex-M3.   
+ *   
+ * The functions operate on blocks of input and output data and each call to the function   
+ * processes blockSize samples through the filter.   
+ * pSrc points to the array of input data and   
+ * pDst points to the array of output data.   
+ * Both arrays contain blockSize values.   
+ *   
+ * \par Algorithm   
+ * Each Biquad stage implements a second order filter using the difference equation:   
+ * 
   
+ *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+ * 
   
+ * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.   
+ * \image html Biquad.gif "Single Biquad filter stage"   
+ * Coefficients b0, b1 and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.   
+ * Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.   
+ * Pay careful attention to the sign of the feedback coefficients.   
+ * Some design tools use the difference equation   
+ * 
   
+ *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]   
+ * 
   
+ * In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.   
+ *   
+ * \par   
+ * Higher order filters are realized as a cascade of second order sections.   
+ * numStages refers to the number of second order stages used.   
+ * For example, an 8th order filter would be realized with numStages=4 second order stages.   
+ * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"   
+ * A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).   
+ *   
+ * \par   
+ * The pState points to state variables array.   
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].   
+ * The state variables are arranged in the pState array as:   
+ * 
   
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ * 
   
+ *   
+ * \par   
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.   
+ * The state array has a total length of 4*numStages values.   
+ * The state variables are updated after each block of data is processed, the coefficients are untouched.   
+ *   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Init Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ *   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Set the values in the state buffer to zeros before static initialization.   
+ * The code below statically initializes each of the 3 different data type filter instance structures   
+ * 
   
+ *     arm_biquad_casd_df1_inst_f32 S1 = {numStages, pState, pCoeffs};   
+ *     arm_biquad_casd_df1_inst_q15 S2 = {numStages, pState, pCoeffs, postShift};   
+ *     arm_biquad_casd_df1_inst_q31 S3 = {numStages, pState, pCoeffs, postShift};   
+ * 
   
+ * where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer;   
+ * pCoeffs is the address of the coefficient buffer; postShift shift to be applied.   
+ *   
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the Q15 and Q31 versions of the Biquad Cascade filter functions.   
+ * Following issues must be considered:   
+ * - Scaling of coefficients   
+ * - Filter gain   
+ * - Overflow and saturation   
+ *   
+ * \par   
+ * Scaling of coefficients:    
+ * Filter coefficients are represented as fractional values and   
+ * coefficients are restricted to lie in the range [-1 +1).   
+ * The fixed-point functions have an additional scaling parameter postShift   
+ * which allow the filter coefficients to exceed the range [+1 -1).   
+ * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.   
+ * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"   
+ * This essentially scales the filter coefficients by 2^postShift.   
+ * For example, to realize the coefficients   
+ * 
   
+ *    {1.5, -0.8, 1.2, 1.6, -0.9}   
+ * 
   
+ * set the pCoeffs array to:   
+ * 
   
+ *    {0.75, -0.4, 0.6, 0.8, -0.45}   
+ * 
   
+ * and set postShift=1   
+ *   
+ * \par   
+ * Filter gain:    
+ * The frequency response of a Biquad filter is a function of its coefficients.   
+ * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.   
+ * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.   
+ * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.   
+ *   
+ * \par   
+ * Overflow and saturation:    
+ * For Q15 and Q31 versions, it is described separately as part of the function specific documentation below.   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1   
+ * @{   
+ */
+
+/**   
+ * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.   
+ * @param[in]  *pSrc      points to the block of input data.   
+ * @param[out] *pDst      points to the block of output data.   
+ * @param[in]  blockSize  number of samples to process per call.   
+ * @return     none.   
+ *   
+ */
+
+void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pIn = pSrc;                         /*  source pointer            */
+  float32_t *pOut = pDst;                        /*  destination pointer       */
+  float32_t *pState = S->pState;                 /*  pState pointer            */
+  float32_t *pCoeffs = S->pCoeffs;               /*  coefficient pointer       */
+  float32_t acc;                                 /*  Simulates the accumulator */
+  float32_t b0, b1, b2, a1, a2;                  /*  Filter coefficients       */
+  float32_t Xn1, Xn2, Yn1, Yn2;                  /*  Filter pState variables   */
+  float32_t Xn;                                  /*  temporary input           */
+  uint32_t sample, stage = S->numStages;         /*  loop counters             */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the pState values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    /*      The variable acc hold output values that are being computed:   
+     *   
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]   
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]   
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]   
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]   
+     */
+
+    sample = blockSize >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(sample > 0u)
+    {
+      /* Read the first input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      Yn2 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+
+      /* Read the second input */
+      Xn2 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      Yn1 = (b0 * Xn2) + (b1 * Xn) + (b2 * Xn1) + (a1 * Yn2) + (a2 * Yn1);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+
+      /* Read the third input */
+      Xn1 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      Yn2 = (b0 * Xn1) + (b1 * Xn2) + (b2 * Xn) + (a1 * Yn1) + (a2 * Yn2);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as: */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+
+      /* Read the forth input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      Yn1 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn2) + (a2 * Yn1);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+
+      /* decrement the loop counter */
+      sample--;
+
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    sample = blockSize & 0x3u;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:    */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = acc;
+
+      /* decrement the loop counter */
+      sample--;
+
+    }
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent numStages  occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset the output pointer */
+    pOut = pDst;
+
+    /* decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the pState values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /*      The variables acc holds the output value that is computed:       
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]       
+     */
+
+    sample = blockSize;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:    */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent numStages  occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset the output pointer */
+    pOut = pDst;
+
+    /* decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+
+#endif /*   #ifndef ARM_MATH_CM0         */
+
+}
+
+
+  /**   
+   * @} end of BiquadCascadeDF1 group   
+   */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
new file mode 100644
index 000000000..c2ac80255
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
@@ -0,0 +1,283 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df1_fast_q15.c   
+*   
+* Description:	Fast processing function for the   
+*				Q15 Biquad cascade filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.9  2010/08/16    
+*    Initial version   
+*   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1   
+ * @{   
+ */
+
+/**   
+ * @details   
+ * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.   
+ * @param[in]  *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in]  blockSize number of samples to process per call.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * This fast version uses a 32-bit accumulator with 2.30 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.   
+ * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25).   
+ * The 2.30 accumulator is then shifted by postShift bits and the result truncated to 1.15 format by discarding the low 16 bits.   
+ *   
+ * \par   
+ * Refer to the function arm_biquad_cascade_df1_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.  Both the slow and the fast versions use the same instance structure.   
+ * Use the function arm_biquad_cascade_df1_init_q15() to initialize the filter structure.   
+ *   
+ */
+
+void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pIn = pSrc;                             /*  Source pointer                               */
+  q15_t *pOut = pDst;                            /*  Destination pointer                          */
+  q31_t in;                                      /*  Temporary variable to hold input value       */
+  q31_t out;                                     /*  Temporary variable to hold output value      */
+  q31_t b0;                                      /*  Temporary variable to hold bo value          */
+  q31_t b1, a1;                                  /*  Filter coefficients                          */
+  q31_t state_in, state_out;                     /*  Filter state variables                       */
+  q31_t acc0;                                    /*  Accumulator                                  */
+  int32_t shift = (int32_t) (15 - S->postShift); /*  Post shift                                   */
+  q15_t *pState = S->pState;                     /*  State pointer                                */
+  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */
+  q31_t *pState_q31;                             /*  32-bit state pointer for SIMD implementation */
+  uint32_t sample, stage = S->numStages;         /*  Stage loop counter                           */
+
+
+
+  do
+  {
+    /* Initialize state pointer of type q31 */
+    pState_q31 = (q31_t *) (pState);
+
+    /* Read the b0 and 0 coefficients using SIMD  */
+    b0 = *__SIMD32(pCoeffs)++;
+
+    /* Read the b1 and b2 coefficients using SIMD */
+    b1 = *__SIMD32(pCoeffs)++;
+
+    /* Read the a1 and a2 coefficients using SIMD */
+    a1 = *__SIMD32(pCoeffs)++;
+
+    /* Read the input state values from the state buffer:  x[n-1], x[n-2] */
+    state_in = (q31_t) (*pState_q31++);
+
+    /* Read the output state values from the state buffer:  y[n-1], y[n-2] */
+    state_out = (q31_t) (*pState_q31);
+
+    /* Apply loop unrolling and compute 2 output values simultaneously. */
+    /*      The variables acc0 ... acc3 hold output values that are being computed:   
+     *   
+     *    acc0 =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+     *    acc0 =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+     */
+    sample = blockSize >> 1u;
+
+    /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.   
+     ** a second loop below computes the remaining 1 sample. */
+    while(sample > 0u)
+    {
+
+      /* Read the input */
+      in = *__SIMD32(pIn)++;
+
+      /* out =  b0 * x[n] + 0 * 0 */
+      out = __SMUAD(b0, in);
+      /* acc0 =  b1 * x[n-1] + acc0 +=  b2 * x[n-2] + out */
+      acc0 = __SMLAD(b1, state_in, out);
+      /* acc0 +=  a1 * y[n-1] + acc0 +=  a2 * y[n-2] */
+      acc0 = __SMLAD(a1, state_out, acc0);
+
+      /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+      out = __SSAT((acc0 >> shift), 16);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc0   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
+      state_out = __PKHBT(state_out >> 16, (out), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* out =  b0 * x[n] + 0 * 0 */
+      out = __SMUADX(b0, in);
+      /* acc0 =  b1 * x[n-1] + acc0 +=  b2 * x[n-2] + out */
+      acc0 = __SMLAD(b1, state_in, out);
+      /* acc0 +=  a1 * y[n-1] + acc0 +=  a2 * y[n-2] */
+      acc0 = __SMLAD(a1, state_out, acc0);
+
+      /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+      out = __SSAT((acc0 >> shift), 16);
+
+
+      /* Store the output in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);
+
+#else
+
+      *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc0   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in >> 16, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, in, 16);
+      state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+
+      /* Decrement the loop counter */
+      sample--;
+
+    }
+
+    /* If the blockSize is not a multiple of 2, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+
+    if((blockSize & 0x1u) != 0u)
+    {
+      /* Read the input */
+      in = *pIn++;
+
+      /* out =  b0 * x[n] + 0 * 0 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      out = __SMUAD(b0, in);
+
+#else
+
+      out = __SMUADX(b0, in);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* acc0 =  b1 * x[n-1] + acc0 +=  b2 * x[n-2] + out */
+      acc0 = __SMLAD(b1, state_in, out);
+      /* acc0 +=  a1 * y[n-1] + acc0 +=  a2 * y[n-2] */
+      acc0 = __SMLAD(a1, state_out, acc0);
+
+      /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+      out = __SSAT((acc0 >> shift), 16);
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q15_t) out;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc0   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, in, 16);
+      state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /*   #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer.  */
+    /*  Subsequent (numStages - 1) occur in-place in the output buffer  */
+    pIn = pDst;
+
+    /* Reset the output pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the state array */
+    *__SIMD32(pState)++ = state_in;
+    *__SIMD32(pState)++ = state_out;
+
+
+    /* Decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+}
+
+
+/**   
+ * @} end of BiquadCascadeDF1 group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
new file mode 100644
index 000000000..1242ae720
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
@@ -0,0 +1,271 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df1_fast_q31.c   
+*   
+* Description:	Processing function for the   
+*				Q31 Fast Biquad cascade DirectFormI(DF1) filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.9  2010/08/27    
+*    Initial version   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1   
+ * @{   
+ */
+
+/**   
+ * @details   
+ *   
+ * @param[in]  *S        points to an instance of the Q31 Biquad cascade structure.   
+ * @param[in]  *pSrc     points to the block of input data.   
+ * @param[out] *pDst     points to the block of output data.   
+ * @param[in]  blockSize number of samples to process per call.   
+ * @return 	   none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.   
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.   
+ * These intermediate results are added to a 2.30 accumulator.   
+ * Finally, the accumulator is saturated and converted to a 1.31 result.   
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.   
+ * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). Use the intialization function   
+ * arm_biquad_cascade_df1_init_q31() to initialize filter structure.   
+ *   
+ * \par   
+ * Refer to the function arm_biquad_cascade_df1_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.  Both the slow and the fast versions use the same instance structure.   
+ * Use the function arm_biquad_cascade_df1_init_q31() to initialize the filter structure.   
+ */
+
+void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /*  input pointer initialization  */
+  q31_t *pOut = pDst;                            /*  output pointer initialization */
+  q31_t *pState = S->pState;                     /*  pState pointer initialization */
+  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */
+  q31_t acc;                                     /*  accumulator                   */
+  q31_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
+  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
+  q31_t Xn;                                      /*  temporary input               */
+  int32_t shift = (int32_t) S->postShift + 1;    /*  Shift to be applied to the output */
+  uint32_t sample, stage = S->numStages;         /*  loop counters                     */
+
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    /*      The variables acc ... acc3 hold output values that are being computed:   
+     *   
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+     */
+
+    sample = blockSize >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q31_t) (((q63_t) b0 * Xn) >> 32);
+      /* acc +=  b1 * x[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
+      /* acc +=  b[2] * x[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
+      /* acc +=  a1 * y[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
+      /* acc +=  a2 * y[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
+
+      /* The result is converted to 1.31 , Yn2 variable is reused */
+      Yn2 = acc << shift;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Read the second input */
+      Xn2 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q31_t) (((q63_t) b0 * (Xn2)) >> 32);
+      /* acc +=  b1 * x[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn))) >> 32);
+      /* acc +=  b[2] * x[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn1))) >> 32);
+      /* acc +=  a1 * y[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);
+      /* acc +=  a2 * y[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);
+
+      /* The result is converted to 1.31, Yn1 variable is reused  */
+      Yn1 = acc << shift;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* Read the third input  */
+      Xn1 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q31_t) (((q63_t) b0 * (Xn1)) >> 32);
+      /* acc +=  b1 * x[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn2))) >> 32);
+      /* acc +=  b[2] * x[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn))) >> 32);
+      /* acc +=  a1 * y[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
+      /* acc +=  a2 * y[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
+
+      /* The result is converted to 1.31, Yn2 variable is reused  */
+      Yn2 = acc << shift;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Read the forth input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);
+      /* acc +=  b1 * x[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
+      /* acc +=  b[2] * x[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
+      /* acc +=  a1 * y[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);
+      /* acc +=  a2 * y[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);
+
+      /* The result is converted to 1.31, Yn1 variable is reused  */
+      Yn1 = acc << shift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    sample = (blockSize & 0x3u);
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);
+      /* acc +=  b1 * x[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
+      /* acc +=  b[2] * x[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
+      /* acc +=  a1 * y[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
+      /* acc +=  a2 * y[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
+      /* The result is converted to 1.31  */
+      acc = acc << shift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = acc;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent stages occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset to destination pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+}
+
+/**   
+  * @} end of BiquadCascadeDF1 group   
+  */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
new file mode 100644
index 000000000..e3e5a8540
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
@@ -0,0 +1,104 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_biquad_cascade_df1_init_f32.c   
+*   
+* Description:  floating-point Biquad cascade DirectFormI(DF1) filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1   
+ * @{   
+ */
+
+/**   
+ * @details   
+ * @brief  Initialization function for the floating-point Biquad cascade filter.   
+ * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.   
+ * @param[in]     numStages    number of 2nd order stages in the filter.   
+ * @param[in]     *pCoeffs     points to the filter coefficients array.   
+ * @param[in]     *pState      points to the state array.   
+ * @return        none   
+ *   
+ *   
+ * Coefficient and State Ordering:   
+ *   
+ * \par   
+ * The coefficients are stored in the array pCoeffs in the following order:   
+ * 
   
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}   
+ * 
   
+ *   
+ * \par   
+ * where b1x and a1x are the coefficients for the first stage,   
+ * b2x and a2x are the coefficients for the second stage,   
+ * and so on.  The pCoeffs array contains a total of 5*numStages values.   
+ *   
+ * \par   
+ * The pState is a pointer to state array.   
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].   
+ * The state variables are arranged in the pState array as:   
+ * 
   
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ * 
   
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.   
+ * The state array has a total length of 4*numStages values.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ *   
+ */
+
+void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 4 * numStages */
+  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**   
+ * @} end of BiquadCascadeDF1 group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
new file mode 100644
index 000000000..42c60fb14
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
@@ -0,0 +1,106 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_biquad_cascade_df1_init_q15.c   
+*   
+* Description:  Q15 Biquad cascade DirectFormI(DF1) filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1   
+ * @{   
+ */
+
+/**   
+ * @details   
+ *   
+ * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.   
+ * @param[in]     numStages    number of 2nd order stages in the filter.   
+ * @param[in]     *pCoeffs     points to the filter coefficients.   
+ * @param[in]     *pState      points to the state buffer.   
+ * @param[in]     postShift    Shift to be applied to the accumulator result. Varies according to the coefficients format   
+ * @return        none   
+ *   
+ * Coefficient and State Ordering:   
+ *   
+ * \par   
+ * The coefficients are stored in the array pCoeffs in the following order:   
+ * 
   
+ *     {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...}   
+ * 
   
+ * where b1x and a1x are the coefficients for the first stage,   
+ * b2x and a2x are the coefficients for the second stage,   
+ * and so on.  The pCoeffs array contains a total of 6*numStages values.   
+ * The zero coefficient between b1 and b2 facilities  use of 16-bit SIMD instructions on the Cortex-M4.   
+ *   
+ * \par   
+ * The state variables are stored in the array pState.   
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].   
+ * The state variables are arranged in the pState array as:   
+ * 
   
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ * 
   
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.   
+ * The state array has a total length of 4*numStages values.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ */
+
+void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign postShift to be applied to the output */
+  S->postShift = postShift;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 4 * numStages */
+  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**   
+ * @} end of BiquadCascadeDF1 group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
new file mode 100644
index 000000000..2e6028e9d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
@@ -0,0 +1,106 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df1_init_q31.c   
+*   
+* Description:	Q31 Biquad cascade DirectFormI(DF1) filter initialization function.   
+*   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1   
+ * @{   
+ */
+
+/**   
+ * @details   
+ *   
+ * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.   
+ * @param[in]     numStages    number of 2nd order stages in the filter.   
+ * @param[in]     *pCoeffs     points to the filter coefficients buffer.   
+ * @param[in]     *pState      points to the state buffer.   
+ * @param[in]     postShift    Shift to be applied after the accumulator.  Varies according to the coefficients format   
+ * @return        none   
+ *   
+ * Coefficient and State Ordering:   
+ *   
+ * \par   
+ * The coefficients are stored in the array pCoeffs in the following order:   
+ * 
   
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}   
+ * 
   
+ * where b1x and a1x are the coefficients for the first stage,   
+ * b2x and a2x are the coefficients for the second stage,   
+ * and so on.  The pCoeffs array contains a total of 5*numStages values.   
+ *   
+ * \par   
+ * The pState points to state variables array.   
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].   
+ * The state variables are arranged in the pState array as:   
+ * 
   
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ * 
   
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.   
+ * The state array has a total length of 4*numStages values.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ */
+
+void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign postShift to be applied to the output */
+  S->postShift = postShift;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 4 * numStages */
+  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**   
+ * @} end of BiquadCascadeDF1 group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
new file mode 100644
index 000000000..9e7bd011d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
@@ -0,0 +1,380 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df1_q15.c   
+*   
+* Description:	Processing function for the   
+*				Q15 Biquad cascade DirectFormI(DF1) filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q15 Biquad cascade filter.   
+ * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.   
+ * @param[in]  *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the location where the output result is written.   
+ * @param[in]  blockSize number of samples to process per call.   
+ * @return none.   
+ *   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.   
+ * The accumulator is then shifted by postShift bits to truncate the result to 1.15 format by discarding the low 16 bits.   
+ * Finally, the result is saturated to 1.15 format.   
+ *   
+ * \par   
+ * Refer to the function arm_biquad_cascade_df1_fast_q15() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn = pSrc;                             /*  Source pointer                               */
+  q15_t *pOut = pDst;                            /*  Destination pointer                          */
+  q31_t in;                                      /*  Temporary variable to hold input value       */
+  q31_t out;                                     /*  Temporary variable to hold output value      */
+  q31_t b0;                                      /*  Temporary variable to hold bo value          */
+  q31_t b1, a1;                                  /*  Filter coefficients                          */
+  q31_t state_in, state_out;                     /*  Filter state variables                       */
+  q63_t acc;                                     /*  Accumulator                                  */
+  int32_t shift = (15 - (int32_t) S->postShift); /*  Post shift                                   */
+  q15_t *pState = S->pState;                     /*  State pointer                                */
+  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */
+  q31_t *pState_q31;                             /*  32-bit state pointer for SIMD implementation */
+  uint32_t sample, stage = (uint32_t) S->numStages;     /*  Stage loop counter                           */
+
+  do
+  {
+    /* Initialize state pointer of type q31 */
+    pState_q31 = (q31_t *) (pState);
+
+    /* Read the b0 and 0 coefficients using SIMD  */
+    b0 = *__SIMD32(pCoeffs)++;
+
+    /* Read the b1 and b2 coefficients using SIMD */
+    b1 = *__SIMD32(pCoeffs)++;
+
+    /* Read the a1 and a2 coefficients using SIMD */
+    a1 = *__SIMD32(pCoeffs)++;
+
+    /* Read the input state values from the state buffer:  x[n-1], x[n-2] */
+    state_in = (q31_t) (*pState_q31++);
+
+    /* Read the output state values from the state buffer:  y[n-1], y[n-2] */
+    state_out = (q31_t) (*pState_q31);
+
+    /* Apply loop unrolling and compute 2 output values simultaneously. */
+    /*      The variable acc hold output values that are being computed:   
+     *   
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+     */
+    sample = blockSize >> 1u;
+
+    /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.   
+     ** a second loop below computes the remaining 1 sample. */
+    while(sample > 0u)
+    {
+
+      /* Read the input */
+      in = *__SIMD32(pIn)++;
+
+      /* out =  b0 * x[n] + 0 * 0 */
+      out = __SMUAD(b0, in);
+
+      /* acc +=  b1 * x[n-1] +  b2 * x[n-2] + out */
+      acc = __SMLALD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] +  a2 * y[n-2] */
+      acc = __SMLALD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+      out = __SSAT((acc >> shift), 16);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
+      state_out = __PKHBT(state_out >> 16, (out), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* out =  b0 * x[n] + 0 * 0 */
+      out = __SMUADX(b0, in);
+      /* acc +=  b1 * x[n-1] +  b2 * x[n-2] + out */
+      acc = __SMLALD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] + a2 * y[n-2] */
+      acc = __SMLALD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+      out = __SSAT((acc >> shift), 16);
+
+      /* Store the output in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);
+
+#else
+
+      *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in >> 16, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, in, 16);
+      state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+
+      /* Decrement the loop counter */
+      sample--;
+
+    }
+
+    /* If the blockSize is not a multiple of 2, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+
+    if((blockSize & 0x1u) != 0u)
+    {
+      /* Read the input */
+      in = *pIn++;
+
+      /* out =  b0 * x[n] + 0 * 0 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      out = __SMUAD(b0, in);
+
+#else
+
+      out = __SMUADX(b0, in);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* acc =  b1 * x[n-1] + b2 * x[n-2] + out */
+      acc = __SMLALD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] + a2 * y[n-2] */
+      acc = __SMLALD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+      out = __SSAT((acc >> shift), 16);
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q15_t) out;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, in, 16);
+      state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /*   #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    }
+
+    /*  The first stage goes from the input wire to the output wire.  */
+    /*  Subsequent numStages occur in-place in the output wire  */
+    pIn = pDst;
+
+    /* Reset the output pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the state array */
+    *__SIMD32(pState)++ = state_in;
+    *__SIMD32(pState)++ = state_out;
+
+
+    /* Decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t *pIn = pSrc;                             /*  Source pointer                               */
+  q15_t *pOut = pDst;                            /*  Destination pointer                          */
+  q15_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
+  q15_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
+  q15_t Xn;                                      /*  temporary input               */
+  q63_t acc;                                     /*  Accumulator                                  */
+  int32_t shift = (15 - (int32_t) S->postShift); /*  Post shift                                   */
+  q15_t *pState = S->pState;                     /*  State pointer                                */
+  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */
+  uint32_t sample, stage = (uint32_t) S->numStages;     /*  Stage loop counter                           */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /*      The variables acc holds the output value that is computed:        
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]        
+     */
+
+    sample = blockSize;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q31_t) b0 *Xn;
+
+      /* acc +=  b1 * x[n-1] */
+      acc += (q31_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q31_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q31_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q31_t) a2 *Yn2;
+
+      /* The result is converted to 1.31  */
+      acc = __SSAT((acc >> shift), 16);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = (q15_t) acc;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q15_t) acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent stages occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset to destination pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+
+#endif /*     #ifndef ARM_MATH_CM0 */
+
+}
+
+
+/**   
+ * @} end of BiquadCascadeDF1 group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
new file mode 100644
index 000000000..068722772
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
@@ -0,0 +1,362 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df1_q31.c   
+*   
+* Description:	Processing function for the   
+*				Q31 Biquad cascade filter   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q31 Biquad cascade filter.   
+ * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.   
+ * @param[in]  *pSrc      points to the block of input data.   
+ * @param[out] *pDst      points to the block of output data.   
+ * @param[in]  blockSize  number of samples to process per call.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around rather than clip.   
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).   
+ * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to   
+ * 1.31 format by discarding the low 32 bits.   
+ *   
+ * \par   
+ * Refer to the function arm_biquad_cascade_df1_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /*  input pointer initialization  */
+  q31_t *pOut = pDst;                            /*  output pointer initialization */
+  q31_t *pState = S->pState;                     /*  pState pointer initialization */
+  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */
+  q63_t acc;                                     /*  accumulator                   */
+  q31_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
+  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
+  q31_t Xn;                                      /*  temporary input               */
+  uint32_t shift = 32u - ((uint32_t) S->postShift + 1u);        /*  Shift to be applied to the output */
+  uint32_t sample, stage = S->numStages;         /*  loop counters                     */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    /*      The variable acc hold output values that are being computed:   
+     *   
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+     */
+
+    sample = blockSize >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn2;
+
+      /* The result is converted to 1.31 , Yn2 variable is reused */
+      Yn2 = (q31_t) (acc >> shift);
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Read the second input */
+      Xn2 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn2;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn1;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn2;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn1;
+
+
+      /* The result is converted to 1.31, Yn1 variable is reused  */
+      Yn1 = (q31_t) (acc >> shift);
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* Read the third input  */
+      Xn1 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn1;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn2;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn2;
+
+      /* The result is converted to 1.31, Yn2 variable is reused  */
+      Yn2 = (q31_t) (acc >> shift);
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Read the forth input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn2;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn1;
+
+      /* The result is converted to 1.31, Yn1 variable is reused  */
+      Yn1 = (q31_t) (acc >> shift);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    sample = (blockSize & 0x3u);
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn2;
+
+      /* The result is converted to 1.31  */
+      acc = acc >> shift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = (q31_t) acc;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q31_t) acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent stages occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset to destination pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /*      The variables acc holds the output value that is computed:        
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]        
+     */
+
+    sample = blockSize;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn;
+
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn2;
+
+      /* The result is converted to 1.31  */
+      acc = acc >> shift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = (q31_t) acc;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q31_t) acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent stages occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset to destination pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+
+#endif /*  #ifndef ARM_MATH_CM0 */
+}
+
+/**   
+  * @} end of BiquadCascadeDF1 group   
+  */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
new file mode 100644
index 000000000..4cf42173c
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
@@ -0,0 +1,359 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df2T_f32.c   
+*   
+* Description:  Processing function for the floating-point transposed   
+*               direct form II Biquad cascade filter.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure   
+ *   
+ * This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.   
+ * The filters are implemented as a cascade of second order Biquad sections.   
+ * These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.  
+ * Only floating-point data is supported.   
+ *   
+ * This function operate on blocks of input and output data and each call to the function   
+ * processes blockSize samples through the filter.   
+ * pSrc points to the array of input data and   
+ * pDst points to the array of output data.   
+ * Both arrays contain blockSize values.   
+ *   
+ * \par Algorithm   
+ * Each Biquad stage implements a second order filter using the difference equation:   
+ * 
   
+ *    y[n] = b0 * x[n] + d1   
+ *    d1 = b1 * x[n] + a1 * y[n] + d2   
+ *    d2 = b2 * x[n] + a2 * y[n]   
+ * 
   
+ * where d1 and d2 represent the two state values.   
+ *   
+ * \par   
+ * A Biquad filter using a transposed Direct Form II structure is shown below.   
+ * \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"   
+ * Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.   
+ * Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.   
+ * Pay careful attention to the sign of the feedback coefficients.   
+ * Some design tools flip the sign of the feedback coefficients:   
+ * 
   
+ *    y[n] = b0 * x[n] + d1;   
+ *    d1 = b1 * x[n] - a1 * y[n] + d2;   
+ *    d2 = b2 * x[n] - a2 * y[n];   
+ * 
   
+ * In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.   
+ *   
+ * \par   
+ * Higher order filters are realized as a cascade of second order sections.   
+ * numStages refers to the number of second order stages used.   
+ * For example, an 8th order filter would be realized with numStages=4 second order stages.   
+ * A 9th order filter would be realized with numStages=5 second order stages with the   
+ * coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).   
+ *   
+ * \par   
+ * pState points to the state variable array.   
+ * Each Biquad stage has 2 state variables d1 and d2.   
+ * The state variables are arranged in the pState array as:   
+ * 
   
+ *     {d11, d12, d21, d22, ...}   
+ * 
   
+ * where d1x refers to the state variables for the first Biquad and   
+ * d2x refers to the state variables for the second Biquad.   
+ * The state array has a total length of 2*numStages values.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ *   
+ * \par   
+ * The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.   
+ * The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.   
+ * That is why the Direct Form I structure supports Q15 and Q31 data types.   
+ * The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2.   
+ * Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.   
+ * The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.   
+ *   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.   
+ *   
+ * \par Init Functions   
+ * There is also an associated initialization function.  
+ * The initialization function performs following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ *   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Set the values in the state buffer to zeros before static initialization.   
+ * For example, to statically initialize the instance structure use   
+ * 
   
+ *     arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};   
+ * 
   
+ * where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer.   
+ * pCoeffs is the address of the coefficient buffer;    
+ *   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF2T   
+ * @{   
+ */
+
+/**  
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.  
+ * @param[in]  *S        points to an instance of the filter data structure.  
+ * @param[in]  *pSrc     points to the block of input data.  
+ * @param[out] *pDst     points to the block of output data  
+ * @param[in]  blockSize number of samples to process.  
+ * @return none.  
+ */
+
+void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+
+  float32_t *pIn = pSrc;                         /*  source pointer            */
+  float32_t *pOut = pDst;                        /*  destination pointer       */
+  float32_t *pState = S->pState;                 /*  State pointer            */
+  float32_t *pCoeffs = S->pCoeffs;               /*  coefficient pointer       */
+  float32_t acc0;                                /*  Simulates the accumulator */
+  float32_t b0, b1, b2, a1, a2;                  /*  Filter coefficients       */
+  float32_t Xn;                                  /*  temporary input           */
+  float32_t d1, d2;                              /*  state variables          */
+  uint32_t sample, stage = S->numStages;         /*  loop counters             */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /*Reading the state values */
+    d1 = pState[0];
+    d2 = pState[1];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    sample = blockSize >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(sample > 0u)
+    {
+      /* Read the first input */
+      Xn = *pIn++;
+
+      /* y[n] = b0 * x[n] + d1 */
+      acc0 = (b0 * Xn) + d1;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+
+      /* Every time after the output is computed state should be updated. */
+      /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+      d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
+
+      /* d2 = b2 * x[n] + a2 * y[n] */
+      d2 = (b2 * Xn) + (a2 * acc0);
+
+      /* Read the second input */
+      Xn = *pIn++;
+
+      /* y[n] = b0 * x[n] + d1 */
+      acc0 = (b0 * Xn) + d1;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+
+      /* Every time after the output is computed state should be updated. */
+      /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+      d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
+
+      /* d2 = b2 * x[n] + a2 * y[n] */
+      d2 = (b2 * Xn) + (a2 * acc0);
+
+      /* Read the third input */
+      Xn = *pIn++;
+
+      /* y[n] = b0 * x[n] + d1 */
+      acc0 = (b0 * Xn) + d1;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+
+      /* Every time after the output is computed state should be updated. */
+      /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+      d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
+
+      /* d2 = b2 * x[n] + a2 * y[n] */
+      d2 = (b2 * Xn) + (a2 * acc0);
+
+      /* Read the fourth input */
+      Xn = *pIn++;
+
+      /* y[n] = b0 * x[n] + d1 */
+      acc0 = (b0 * Xn) + d1;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+
+      /* Every time after the output is computed state should be updated. */
+      /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+      d1 = (b1 * Xn) + (a1 * acc0) + d2;
+
+      /* d2 = b2 * x[n] + a2 * y[n] */
+      d2 = (b2 * Xn) + (a2 * acc0);
+
+      /* decrement the loop counter */
+      sample--;
+
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    sample = blockSize & 0x3u;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* y[n] = b0 * x[n] + d1 */
+      acc0 = (b0 * Xn) + d1;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+
+      /* Every time after the output is computed state should be updated. */
+      /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+      d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
+
+      /* d2 = b2 * x[n] + a2 * y[n] */
+      d2 = (b2 * Xn) + (a2 * acc0);
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /* Store the updated state variables back into the state array */
+    *pState++ = d1;
+    *pState++ = d2;
+
+    /* The current stage input is given as the output to the next stage */
+    pIn = pDst;
+
+    /*Reset the output working pointer */
+    pOut = pDst;
+
+    /* decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /*Reading the state values */
+    d1 = pState[0];
+    d2 = pState[1];
+
+
+    sample = blockSize;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* y[n] = b0 * x[n] + d1 */
+      acc0 = (b0 * Xn) + d1;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+
+      /* Every time after the output is computed state should be updated. */
+      /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+      d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
+
+      /* d2 = b2 * x[n] + a2 * y[n] */
+      d2 = (b2 * Xn) + (a2 * acc0);
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /* Store the updated state variables back into the state array */
+    *pState++ = d1;
+    *pState++ = d2;
+
+    /* The current stage input is given as the output to the next stage */
+    pIn = pDst;
+
+    /*Reset the output working pointer */
+    pOut = pDst;
+
+    /* decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+
+#endif /*  #ifndef ARM_MATH_CM0         */
+
+}
+
+
+  /**   
+   * @} end of BiquadCascadeDF2T group   
+   */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
new file mode 100644
index 000000000..552778505
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
@@ -0,0 +1,94 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_biquad_cascade_df2T_init_f32.c   
+*   
+* Description:  Initialization function for the floating-point transposed  
+*               direct form II Biquad cascade filter.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF2T   
+ * @{   
+ */
+
+/**  
+ * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.  
+ * @param[in,out] *S           points to an instance of the filter data structure.  
+ * @param[in]     numStages    number of 2nd order stages in the filter.  
+ * @param[in]     *pCoeffs     points to the filter coefficients.  
+ * @param[in]     *pState      points to the state buffer.  
+ * @return        none  
+ *   
+ * Coefficient and State Ordering:   
+ * \par   
+ * The coefficients are stored in the array pCoeffs in the following order:   
+ * 
   
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}   
+ * 
   
+ *   
+ * \par   
+ * where b1x and a1x are the coefficients for the first stage,   
+ * b2x and a2x are the coefficients for the second stage,   
+ * and so on.  The pCoeffs array contains a total of 5*numStages values.   
+ *   
+ * \par   
+ * The pState is a pointer to state array.   
+ * Each Biquad stage has 2 state variables d1, and d2.   
+ * The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.   
+ * The state array has a total length of 2*numStages values.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ */
+
+void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 2 * numStages */
+  memset(pState, 0, (2u * (uint32_t) numStages) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**   
+ * @} end of BiquadCascadeDF2T group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c
new file mode 100644
index 000000000..db3990c57
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c
@@ -0,0 +1,623 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_f32.c   
+*   
+* Description:	Convolution of floating-point sequences.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup Conv Convolution   
+ *   
+ * Convolution is a mathematical operation that operates on two finite length vectors to generate a finite length output vector.   
+ * Convolution is similar to correlation and is frequently used in filtering and data analysis.   
+ * The CMSIS DSP library contains functions for convolving Q7, Q15, Q31, and floating-point data types.   
+ * The library also provides fast versions of the Q15 and Q31 functions on Cortex-M4 and Cortex-M3.   
+ *   
+ * \par Algorithm   
+ * Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively.   
+ * Then the convolution   
+ *   
+ * 
   
+ *                   c[n] = a[n] * b[n]   
+ * 
   
+ *   
+ * \par   
+ * is defined as   
+ * \image html ConvolutionEquation.gif   
+ * \par   
+ * Note that c[n] is of length srcALen + srcBLen - 1 and is defined over the interval n=0, 1, 2, ..., srcALen + srcBLen - 2.   
+ * pSrcA points to the first input vector of length srcALen and   
+ * pSrcB points to the second input vector of length srcBLen.   
+ * The output result is written to pDst and the calling function must allocate srcALen+srcBLen-1 words for the result.   
+ *   
+ * \par   
+ * Conceptually, when two signals a[n] and b[n] are convolved,   
+ * the signal b[n] slides over a[n].   
+ * For each offset \c n, the overlapping portions of a[n] and b[n] are multiplied and summed together.   
+ *   
+ * \par   
+ * Note that convolution is a commutative operation:   
+ *   
+ * 
   
+ *                   a[n] * b[n] = b[n] * a[n].   
+ * 
   
+ *   
+ * \par   
+ * This means that switching the A and B arguments to the convolution functions has no effect.   
+ *   
+ * Fixed-Point Behavior   
+ *   
+ * \par   
+ * Convolution requires summing up a large number of intermediate products.   
+ * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.   
+ * Refer to the function specific documentation below for further details of the particular algorithm used.   
+ */
+
+/**   
+ * @addtogroup Conv   
+ * @{   
+ */
+
+/**   
+ * @brief Convolution of floating-point sequences.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
+ * @return none.   
+ */
+
+void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t *pIn1;                               /* inputA pointer */
+  float32_t *pIn2;                               /* inputB pointer */
+  float32_t *pOut = pDst;                        /* output pointer */
+  float32_t *px;                                 /* Intermediate inputA pointer */
+  float32_t *py;                                 /* Intermediate inputB pointer */
+  float32_t *pSrc1, *pSrc2;                      /* Intermediate pointers */
+  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulator */
+  float32_t x0, x1, x2, x3, c0;                  /* Temporary variables to hold state and coefficient values */
+  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counters */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally   
+   * divided into three stages according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first stage of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+   * In the third stage of the algorithm, the multiplications decrease by one   
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.   
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]   
+   * sum = x[0] * y[1] + x[1] * y[0]   
+   * ....   
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0.0f;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 1] */
+      sum += *px++ * *py--;
+
+      /* x[1] * y[srcBLen - 2] */
+      sum += *px++ * *py--;
+
+      /* x[2] * y[srcBLen - 3] */
+      sum += *px++ * *py--;
+
+      /* x[3] * y[srcBLen - 4] */
+      sum += *px++ * *py--;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += *px++ * *py--;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0.0f;
+      acc1 = 0.0f;
+      acc2 = 0.0f;
+      acc3 = 0.0f;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[srcBLen - 1] sample */
+        c0 = *(py--);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[0] * y[srcBLen - 1] */
+        acc0 += x0 * c0;
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] */
+        acc1 += x1 * c0;
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] */
+        acc2 += x2 * c0;
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] */
+        acc3 += x3 * c0;
+
+        /* Read y[srcBLen - 2] sample */
+        c0 = *(py--);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[1] * y[srcBLen - 2] */
+        acc0 += x1 * c0;
+        /* acc1 +=  x[2] * y[srcBLen - 2] */
+        acc1 += x2 * c0;
+        /* acc2 +=  x[3] * y[srcBLen - 2] */
+        acc2 += x3 * c0;
+        /* acc3 +=  x[4] * y[srcBLen - 2] */
+        acc3 += x0 * c0;
+
+        /* Read y[srcBLen - 3] sample */
+        c0 = *(py--);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[srcBLen - 3] */
+        acc0 += x2 * c0;
+        /* acc1 +=  x[3] * y[srcBLen - 2] */
+        acc1 += x3 * c0;
+        /* acc2 +=  x[4] * y[srcBLen - 2] */
+        acc2 += x0 * c0;
+        /* acc3 +=  x[5] * y[srcBLen - 2] */
+        acc3 += x1 * c0;
+
+        /* Read y[srcBLen - 4] sample */
+        c0 = *(py--);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[srcBLen - 4] */
+        acc0 += x3 * c0;
+        /* acc1 +=  x[4] * y[srcBLen - 4] */
+        acc1 += x0 * c0;
+        /* acc2 +=  x[5] * y[srcBLen - 4] */
+        acc2 += x1 * c0;
+        /* acc3 +=  x[6] * y[srcBLen - 4] */
+        acc3 += x2 * c0;
+
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[srcBLen - 5] sample */
+        c0 = *(py--);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[srcBLen - 5] */
+        acc0 += x0 * c0;
+        /* acc1 +=  x[5] * y[srcBLen - 5] */
+        acc1 += x1 * c0;
+        /* acc2 +=  x[6] * y[srcBLen - 5] */
+        acc2 += x2 * c0;
+        /* acc3 +=  x[7] * y[srcBLen - 5] */
+        acc3 += x3 * c0;
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+      *pOut++ = acc1;
+      *pOut++ = acc2;
+      *pOut++ = acc3;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pSrc2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += *px++ * *py--;
+        sum += *px++ * *py--;
+        sum += *px++ * *py--;
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+   * sum +=  x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0.0f;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+      sum += *px++ * *py--;
+
+      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+      sum += *px++ * *py--;
+
+      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+      sum += *px++ * *py--;
+
+      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+      sum += *px++ * *py--;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+      sum += *px++ * *py--;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
+  float32_t *pIn2 = pSrcB;                       /* inputB pointer */
+  float32_t sum;                                 /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0u; i < ((srcALen + srcBLen) - 1u); i++)
+  {
+    /* Initialize sum with zero to carry out MAC operations */
+    sum = 0.0f;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0u; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += pIn1[j] * pIn2[i - j];
+      }
+    }
+    /* Store the output in the destination buffer */
+    pDst[i] = sum;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0        */
+
+}
+
+/**   
+ * @} end of Conv group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c
new file mode 100644
index 000000000..70038f86a
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c
@@ -0,0 +1,677 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_fast_q15.c   
+*   
+* Description:	Fast Q15 Convolution.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Conv   
+ * @{   
+ */
+
+/**   
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * This fast version uses a 32-bit accumulator with 2.30 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results   
+ * but provides only a single guard bit. There is no saturation on intermediate additions.   
+ * Thus, if the accumulator overflows it wraps around and distorts the result.   
+ * The input signals should be scaled down to avoid intermediate overflows.   
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,   
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.   
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.   
+ *   
+ * \par   
+ * See arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.   
+ */
+
+void arm_conv_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst)
+{
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *pOut = pDst;                            /* output pointer */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
+  uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt;     /* loop counter */
+  q31_t *pb;                                     /* 32 bit pointer for inputB buffer */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally   
+   * divided into three stages according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first stage of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+   * In the third stage of the algorithm, the multiplications decrease by one   
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.   
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]   
+   * sum = x[0] * y[1] + x[1] * y[0]   
+   * ....   
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations less than 4 */
+  /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  while((count < 4u) && (blockSize1 > 0u))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Loop over number of MAC operations between   
+     * inputA samples and inputB samples */
+    k = count;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLAD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* The second part of the stage starts here */
+  /* The internal loop, over count, is unrolled by 4 */
+  /* To, read the last two inputB samples using SIMD:   
+   * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+  py = py - 1;
+
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+      /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* For the next MAC operations, the pointer py is used without SIMD   
+     * So, py is incremented by 1 */
+    py = py + 1u;
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLAD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + (count - 1u);
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* Initialize inputB pointer of type q31 */
+  pb = (q31_t *) (py - 1u);
+
+  /* count is the index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+
+  /* --------------------   
+   * Stage2 process   
+   * -------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+
+      /* read x[0], x[1] samples */
+      x0 = *(q31_t *) (px++);
+      /* read x[1], x[2] samples */
+      x1 = *(q31_t *) (px++);
+
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the last two inputB samples using SIMD:   
+         * y[srcBLen - 1] and y[srcBLen - 2] */
+        c0 = *(pb--);
+
+        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+        acc0 = __SMLADX(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+        acc1 = __SMLADX(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *(q31_t *) (px++);
+
+        /* Read x[3], x[4] */
+        x3 = *(q31_t *) (px++);
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+        acc2 = __SMLADX(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+        acc3 = __SMLADX(x3, c0, acc3);
+
+        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+        c0 = *(pb--);
+
+        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+        acc0 = __SMLADX(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+        acc1 = __SMLADX(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = *(q31_t *) (px++);
+
+        /* Read x[5], x[6] */
+        x1 = *(q31_t *) (px++);
+
+        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+        acc2 = __SMLADX(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+        acc3 = __SMLADX(x1, c0, acc3);
+
+      } while(--k);
+
+      /* For the next MAC operations, SIMD is not used   
+       * So, the 16 bit pointer if inputB, py is updated */
+      py = (q15_t *) pb;
+      py = py + 1;
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[srcBLen - 5] */
+        c0 = *(py);
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+//          c0 = unallign_rev(p, c0); 
+        c0 = c0 << 16;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+        x3 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLADX(x1, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = *(pb);
+
+        /* Read x[7], x[8] */
+        x3 = *(q31_t *) px++;
+
+        /* Read x[9] */
+        x2 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x0, c0, acc0);
+        acc1 = __SMLADX(x1, c0, acc1);
+        acc2 = __SMLADX(x3, c0, acc2);
+        acc3 = __SMLADX(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = *pb--;
+
+        /* Read x[7], x[8] */
+        x3 = *(q31_t *) px++;
+
+        /* Read x[9] */
+        x2 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x0, c0, acc0);
+        acc1 = __SMLADX(x1, c0, acc1);
+        acc2 = __SMLADX(x3, c0, acc2);
+        acc3 = __SMLADX(x2, c0, acc3);
+
+        /* Read y[srcBLen - 7] */
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = (*pb);
+//              c0 = (c0 & 0x0000FFFF)<<16;     
+        c0 = (c0) << 16;
+
+#else
+
+        c0 = (q15_t) (*pb >> 16);
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+        x3 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x1, c0, acc0);
+        acc1 = __SMLAD(x2, c0, acc1);
+        acc2 = __SMLADX(x2, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      /* Store the results in the accumulators in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ = __PKHBT((acc0 >> 15), (acc1 >> 15), 16);
+      *__SIMD32(pOut)++ = __PKHBT((acc2 >> 15), (acc3 >> 15), 16);
+
+#else
+
+      *__SIMD32(pOut)++ = __PKHBT((acc1 >> 15), (acc0 >> 15), 16);
+      *__SIMD32(pOut)++ = __PKHBT((acc3 >> 15), (acc2 >> 15), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pSrc2;
+      pb = (q31_t *) (py - 1);
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+   * sum +=  x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  pIn2 = pSrc2 - 1u;
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations greater than 4 */
+  /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  j = blockSize3 >> 2u;
+
+  while((j > 0u) && (blockSize3 > 0u))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
+       * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+      /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
+       * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* For the next MAC operations, the pointer py is used without SIMD   
+     * So, py is incremented by 1 */
+    py = py + 1u;
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+      sum = __SMLAD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+
+    j--;
+  }
+
+  /* The second part of the stage starts here */
+  /* SIMD is not used for the next MAC operations,   
+   * so pointer py is updated to read only one sample at a time */
+  py = py + 1u;
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+      sum = __SMLAD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+}
+
+/**   
+ * @} end of Conv group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c
new file mode 100644
index 000000000..d1eeeaca1
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c
@@ -0,0 +1,567 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_fast_q31.c   
+*   
+* Description:	Q31 Convolution (fast version).   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Conv   
+ * @{   
+ */
+
+/**   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.   
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.   
+ * These intermediate results are accumulated in a 32-bit register in 2.30 format.   
+ * Finally, the accumulator is saturated and converted to a 1.31 result.   
+ *   
+ * \par   
+ * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.   
+ * In order to avoid overflows completely the input signals must be scaled down.   
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,   
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.   
+ *   
+ * \par   
+ * See arm_conv_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.   
+ */
+
+void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst)
+{
+  q31_t *pIn1;                                   /* inputA pointer */
+  q31_t *pIn2;                                   /* inputB pointer */
+  q31_t *pOut = pDst;                            /* output pointer */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
+  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally   
+   * divided into three stages according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first stage of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+   * In the third stage of the algorithm, the multiplications decrease by one   
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.   
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]   
+   * sum = x[0] * y[1] + x[1] * y[0]   
+   * ....   
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* x[1] * y[srcBLen - 2] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* x[2] * y[srcBLen - 3] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* x[3] * y[srcBLen - 4] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = sum << 1;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[srcBLen - 1] sample */
+        c0 = *(py--);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[0] * y[srcBLen - 1] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+        /* Read y[srcBLen - 2] sample */
+        c0 = *(py--);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[1] * y[srcBLen - 2] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc1 +=  x[2] * y[srcBLen - 2] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc2 +=  x[3] * y[srcBLen - 2] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc3 +=  x[4] * y[srcBLen - 2] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+        /* Read y[srcBLen - 3] sample */
+        c0 = *(py--);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[srcBLen - 3] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc1 +=  x[3] * y[srcBLen - 2] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc2 +=  x[4] * y[srcBLen - 2] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc3 +=  x[5] * y[srcBLen - 2] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+        /* Read y[srcBLen - 4] sample */
+        c0 = *(py--);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[srcBLen - 4] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc1 +=  x[4] * y[srcBLen - 4] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc2 +=  x[5] * y[srcBLen - 4] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc3 +=  x[6] * y[srcBLen - 4] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[srcBLen - 5] sample */
+        c0 = *(py--);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[srcBLen - 5] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc1 +=  x[5] * y[srcBLen - 5] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc2 +=  x[6] * y[srcBLen - 5] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc3 +=  x[7] * y[srcBLen - 5] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the results in the accumulators in the destination buffer. */
+      *pOut++ = (q31_t) (acc0 << 1);
+      *pOut++ = (q31_t) (acc1 << 1);
+      *pOut++ = (q31_t) (acc2 << 1);
+      *pOut++ = (q31_t) (acc3 << 1);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pSrc2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum << 1;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum << 1;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+   * sum +=  x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = sum << 1;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+}
+
+/**   
+ * @} end of Conv group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c
new file mode 100644
index 000000000..74b8c8e4d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c
@@ -0,0 +1,641 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_partial_f32.c   
+*   
+* Description:	Partial convolution of floating-point sequences.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup PartialConv Partial Convolution   
+ *   
+ * Partial Convolution is equivalent to Convolution except that a subset of the output samples is generated.   
+ * Each function has two additional arguments.   
+ * firstIndex specifies the starting index of the subset of output samples.   
+ * numPoints is the number of output samples to compute.   
+ * The function computes the output in the range   
+ * [firstIndex, ..., firstIndex+numPoints-1].   
+ * The output array pDst contains numPoints values.   
+ *   
+ * The allowable range of output indices is [0 srcALen+srcBLen-2].   
+ * If the requested subset does not fall in this range then the functions return ARM_MATH_ARGUMENT_ERROR.   
+ * Otherwise the functions return ARM_MATH_SUCCESS.   
+ * \note Refer arm_conv_f32() for details on fixed point behavior.  
+ */
+
+/**   
+ * @addtogroup PartialConv   
+ * @{   
+ */
+
+/**   
+ * @brief Partial convolution of floating-point sequences.   
+ * @param[in]       *pSrcA points to the first input sequence.   
+ * @param[in]       srcALen length of the first input sequence.   
+ * @param[in]       *pSrcB points to the second input sequence.   
+ * @param[in]       srcBLen length of the second input sequence.   
+ * @param[out]      *pDst points to the location where the output result is written.   
+ * @param[in]       firstIndex is the first output sample to start with.   
+ * @param[in]       numPoints is the number of output points to be computed.   
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+ */
+
+arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
+  float32_t *pIn2 = pSrcB;                       /* inputB pointer */
+  float32_t *pOut = pDst;                        /* output pointer */
+  float32_t *px;                                 /* Intermediate inputA pointer */
+  float32_t *py;                                 /* Intermediate inputB pointer */
+  float32_t *pSrc1, *pSrc2;                      /* Intermediate pointers */
+  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulator */
+  float32_t x0, x1, x2, x3, c0;                  /* Temporary variables to hold state and coefficient values */
+  uint32_t j, k, count = 0u, blkCnt, check;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds   
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = (int32_t) check - (int32_t) srcALen;
+    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+    blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex;
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = ((int32_t) check - blockSize3) -
+      (blockSize1 + (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally   
+     * divided into three stages according to the number of multiplications that has to be   
+     * taken place between inputA samples and inputB samples. In the first stage of the   
+     * algorithm, the multiplications increase by one for every iteration.   
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+     * In the third stage of the algorithm, the multiplications decrease by one   
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex   
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------   
+     * Initializations of stage1   
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]   
+     * sum = x[0] * y[1] + x[1] * y[0]   
+     * ....   
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed.   
+       Since the partial convolution starts from from firstIndex   
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc1 = pIn2 + firstIndex;
+    py = pSrc1;
+
+    /* ------------------------   
+     * Stage1 process   
+     * ----------------------*/
+
+    /* The first stage starts here */
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[0] * y[srcBLen - 1] */
+        sum += *px++ * *py--;
+
+        /* x[1] * y[srcBLen - 2] */
+        sum += *px++ * *py--;
+
+        /* x[2] * y[srcBLen - 3] */
+        sum += *px++ * *py--;
+
+        /* x[3] * y[srcBLen - 4] */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc1;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------   
+     * Initializations of stage2   
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+     * ....   
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+     */
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* count is index by which the pointer pIn1 to be incremented */
+    count = 1u;
+
+    /* -------------------   
+     * Stage2 process   
+     * ------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+     * So, to loop unroll over blockSize2,   
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2, by 4 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0.0f;
+        acc1 = 0.0f;
+        acc2 = 0.0f;
+        acc3 = 0.0f;
+
+        /* read x[0], x[1], x[2] samples */
+        x0 = *(px++);
+        x1 = *(px++);
+        x2 = *(px++);
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read y[srcBLen - 1] sample */
+          c0 = *(py--);
+
+          /* Read x[3] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[0] * y[srcBLen - 1] */
+          acc0 += x0 * c0;
+
+          /* acc1 +=  x[1] * y[srcBLen - 1] */
+          acc1 += x1 * c0;
+
+          /* acc2 +=  x[2] * y[srcBLen - 1] */
+          acc2 += x2 * c0;
+
+          /* acc3 +=  x[3] * y[srcBLen - 1] */
+          acc3 += x3 * c0;
+
+          /* Read y[srcBLen - 2] sample */
+          c0 = *(py--);
+
+          /* Read x[4] sample */
+          x0 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[1] * y[srcBLen - 2] */
+          acc0 += x1 * c0;
+          /* acc1 +=  x[2] * y[srcBLen - 2] */
+          acc1 += x2 * c0;
+          /* acc2 +=  x[3] * y[srcBLen - 2] */
+          acc2 += x3 * c0;
+          /* acc3 +=  x[4] * y[srcBLen - 2] */
+          acc3 += x0 * c0;
+
+          /* Read y[srcBLen - 3] sample */
+          c0 = *(py--);
+
+          /* Read x[5] sample */
+          x1 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[2] * y[srcBLen - 3] */
+          acc0 += x2 * c0;
+          /* acc1 +=  x[3] * y[srcBLen - 2] */
+          acc1 += x3 * c0;
+          /* acc2 +=  x[4] * y[srcBLen - 2] */
+          acc2 += x0 * c0;
+          /* acc3 +=  x[5] * y[srcBLen - 2] */
+          acc3 += x1 * c0;
+
+          /* Read y[srcBLen - 4] sample */
+          c0 = *(py--);
+
+          /* Read x[6] sample */
+          x2 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[3] * y[srcBLen - 4] */
+          acc0 += x3 * c0;
+          /* acc1 +=  x[4] * y[srcBLen - 4] */
+          acc1 += x0 * c0;
+          /* acc2 +=  x[5] * y[srcBLen - 4] */
+          acc2 += x1 * c0;
+          /* acc3 +=  x[6] * y[srcBLen - 4] */
+          acc3 += x2 * c0;
+
+
+        } while(--k);
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Read y[srcBLen - 5] sample */
+          c0 = *(py--);
+
+          /* Read x[7] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[4] * y[srcBLen - 5] */
+          acc0 += x0 * c0;
+          /* acc1 +=  x[5] * y[srcBLen - 5] */
+          acc1 += x1 * c0;
+          /* acc2 +=  x[6] * y[srcBLen - 5] */
+          acc2 += x2 * c0;
+          /* acc3 +=  x[7] * y[srcBLen - 5] */
+          acc3 += x3 * c0;
+
+          /* Reuse the present samples for the next MAC */
+          x0 = x1;
+          x1 = x2;
+          x2 = x3;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = acc0;
+        *pOut++ = acc1;
+        *pOut++ = acc2;
+        *pOut++ = acc3;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + (count * 4u);
+        py = pSrc2;
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0.0f;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += *px++ * *py--;
+          sum += *px++ * *py--;
+          sum += *px++ * *py--;
+          sum += *px++ * *py--;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += *px++ * *py--;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = sum;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,   
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0.0f;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += *px++ * *py--;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = sum;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------   
+     * Initializations of stage3   
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+     * ....   
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+     * sum +=  x[srcALen-1] * y[srcBLen-1]   
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+        sum += *px++ * *py--;
+
+        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+        sum += *px++ * *py--;
+
+        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+        sum += *px++ * *py--;
+
+        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
+  float32_t *pIn2 = pSrcB;                       /* inputB pointer */
+  float32_t sum;                                 /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Loop to calculate convolution for output length number of values */
+    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+    {
+      /* Initialize sum with zero to carry on MAC operations */
+      sum = 0.0f;
+
+      /* Loop to perform MAC operations according to convolution equation */
+      for (j = 0u; j <= i; j++)
+      {
+        /* Check the array limitations for inputs */
+        if((((i - j) < srcBLen) && (j < srcALen)))
+        {
+          /* z[i] += x[i-j] * y[j] */
+          sum += pIn1[j] * pIn2[i - j];
+        }
+      }
+      /* Store the output in the destination buffer */
+      pDst[i] = sum;
+    }
+    /* set status as ARM_SUCCESS as there are no argument errors */
+    status = ARM_MATH_SUCCESS;
+  }
+  return (status);
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of PartialConv group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
new file mode 100644
index 000000000..dcb4ed7b5
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
@@ -0,0 +1,705 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_partial_fast_q15.c   
+*   
+* Description:	Fast Q15 Partial convolution.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup PartialConv   
+ * @{   
+ */
+
+/**   
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.   
+ * @param[in]       *pSrcA points to the first input sequence.   
+ * @param[in]       srcALen length of the first input sequence.   
+ * @param[in]       *pSrcB points to the second input sequence.   
+ * @param[in]       srcBLen length of the second input sequence.   
+ * @param[out]      *pDst points to the location where the output result is written.   
+ * @param[in]       firstIndex is the first output sample to start with.   
+ * @param[in]       numPoints is the number of output points to be computed.   
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+ *   
+ * See arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.   
+ */
+
+
+arm_status arm_conv_partial_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters                 */
+  arm_status status;                             /* status of Partial convolution */
+  q31_t *pb;                                     /* 32 bit pointer for inputB buffer */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds   
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t) check - (int32_t) srcALen);
+    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally   
+     * divided into three stages according to the number of multiplications that has to be   
+     * taken place between inputA samples and inputB samples. In the first stage of the   
+     * algorithm, the multiplications increase by one for every iteration.   
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+     * In the third stage of the algorithm, the multiplications decrease by one   
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex   
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------   
+     * Initializations of stage1   
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]   
+     * sum = x[0] * y[1] + x[1] * y[0]   
+     * ....   
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed.   
+       Since the partial convolution starts from firstIndex   
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------   
+     * Stage1 process   
+     * ----------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations less than 4 */
+    /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    while((count < 4u) && (blockSize1 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over number of MAC operations between   
+       * inputA samples and inputB samples */
+      k = count;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* The second part of the stage starts here */
+    /* The internal loop, over count, is unrolled by 4 */
+    /* To, read the last two inputB samples using SIMD:   
+     * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+    py = py - 1;
+
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+        /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* For the next MAC operations, the pointer py is used without SIMD   
+       * So, py is incremented by 1 */
+      py = py + 1u;
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2 - 1u;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------   
+     * Initializations of stage2   
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+     * ....   
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+     */
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* Initialize inputB pointer of type q31 */
+    pb = (q31_t *) (py - 1u);
+
+    /* count is the index by which the pointer pIn1 to be incremented */
+    count = 1u;
+
+
+    /* --------------------   
+     * Stage2 process   
+     * -------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+     * So, to loop unroll over blockSize2,   
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2, by 4 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+
+        /* read x[0], x[1] samples */
+        x0 = *(q31_t *) (px++);
+        /* read x[1], x[2] samples */
+        x1 = *(q31_t *) (px++);
+
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read the last two inputB samples using SIMD:   
+           * y[srcBLen - 1] and y[srcBLen - 2] */
+          c0 = *(pb--);
+
+          /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+          acc0 = __SMLADX(x0, c0, acc0);
+
+          /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+          acc1 = __SMLADX(x1, c0, acc1);
+
+          /* Read x[2], x[3] */
+          x2 = *(q31_t *) (px++);
+
+          /* Read x[3], x[4] */
+          x3 = *(q31_t *) (px++);
+
+          /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+          acc2 = __SMLADX(x2, c0, acc2);
+
+          /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+          acc3 = __SMLADX(x3, c0, acc3);
+
+          /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+          c0 = *(pb--);
+
+          /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+          acc0 = __SMLADX(x2, c0, acc0);
+
+          /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+          acc1 = __SMLADX(x3, c0, acc1);
+
+          /* Read x[4], x[5] */
+          x0 = *(q31_t *) (px++);
+
+          /* Read x[5], x[6] */
+          x1 = *(q31_t *) (px++);
+
+          /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+          acc2 = __SMLADX(x0, c0, acc2);
+
+          /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+          acc3 = __SMLADX(x1, c0, acc3);
+
+        } while(--k);
+
+        /* For the next MAC operations, SIMD is not used   
+         * So, the 16 bit pointer if inputB, py is updated */
+        py = (q15_t *) pb;
+        py = py + 1;
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        if(k == 1u)
+        {
+          /* Read y[srcBLen - 5] */
+          c0 = *(py);
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+          c0 = c0 << 16;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+          /* Read x[7] */
+          x3 = *(q31_t *) px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLAD(x0, c0, acc0);
+          acc1 = __SMLAD(x1, c0, acc1);
+          acc2 = __SMLADX(x1, c0, acc2);
+          acc3 = __SMLADX(x3, c0, acc3);
+        }
+
+        if(k == 2u)
+        {
+          /* Read y[srcBLen - 5], y[srcBLen - 6] */
+          c0 = *(pb);
+
+          /* Read x[7], x[8] */
+          x3 = *(q31_t *) px++;
+
+          /* Read x[9] */
+          x2 = *(q31_t *) px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLADX(x0, c0, acc0);
+          acc1 = __SMLADX(x1, c0, acc1);
+          acc2 = __SMLADX(x3, c0, acc2);
+          acc3 = __SMLADX(x2, c0, acc3);
+        }
+
+        if(k == 3u)
+        {
+          /* Read y[srcBLen - 5], y[srcBLen - 6] */
+          c0 = *pb--;
+
+          /* Read x[7], x[8] */
+          x3 = *(q31_t *) px++;
+
+          /* Read x[9] */
+          x2 = *(q31_t *) px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLADX(x0, c0, acc0);
+          acc1 = __SMLADX(x1, c0, acc1);
+          acc2 = __SMLADX(x3, c0, acc2);
+          acc3 = __SMLADX(x2, c0, acc3);
+
+          /* Read y[srcBLen - 7] */
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+          c0 = (*pb);
+          c0 = (c0) << 16;
+
+#else
+
+          c0 = (q15_t) (*pb >> 16);
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+          /* Read x[10] */
+          x3 = *(q31_t *) px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLADX(x1, c0, acc0);
+          acc1 = __SMLAD(x2, c0, acc1);
+          acc2 = __SMLADX(x2, c0, acc2);
+          acc3 = __SMLADX(x3, c0, acc3);
+        }
+
+        /* Store the results in the accumulators in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *__SIMD32(pOut)++ = __PKHBT(acc0 >> 15, acc1 >> 15, 16);
+        *__SIMD32(pOut)++ = __PKHBT(acc2 >> 15, acc3 >> 15, 16);
+
+#else
+
+        *__SIMD32(pOut)++ = __PKHBT(acc1 >> 15, acc0 >> 15, 16);
+        *__SIMD32(pOut)++ = __PKHBT(acc3 >> 15, acc2 >> 15, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + (count * 4u);
+        py = pSrc2;
+        pb = (q31_t *) (py - 1);
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (sum >> 15);
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,   
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (sum >> 15);
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------   
+     * Initializations of stage3   
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+     * ....   
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+     * sum +=  x[srcALen-1] * y[srcBLen-1]   
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    pIn2 = pSrc2 - 1u;
+    py = pIn2;
+
+    /* -------------------   
+     * Stage3 process   
+     * ------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations greater than 4 */
+    /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    j = count >> 2u;
+
+    while((j > 0u) && (blockSize3 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
+         * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+        /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
+         * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* For the next MAC operations, the pointer py is used without SIMD   
+       * So, py is incremented by 1 */
+      py = py + 1u;
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+        sum = __SMLAD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pIn2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+      j--;
+    }
+
+    /* The second part of the stage starts here */
+    /* SIMD is not used for the next MAC operations,   
+     * so pointer py is updated to read only one sample at a time */
+    py = py + 1u;
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum = __SMLAD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+}
+
+/**   
+ * @} end of PartialConv group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
new file mode 100644
index 000000000..0b848053d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
@@ -0,0 +1,593 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_partial_fast_q31.c   
+*   
+* Description:	Fast Q31 Partial convolution.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup PartialConv   
+ * @{   
+ */
+
+/**   
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.   
+ * @param[in]       *pSrcA points to the first input sequence.   
+ * @param[in]       srcALen length of the first input sequence.   
+ * @param[in]       *pSrcB points to the second input sequence.   
+ * @param[in]       srcBLen length of the second input sequence.   
+ * @param[out]      *pDst points to the location where the output result is written.   
+ * @param[in]       firstIndex is the first output sample to start with.   
+ * @param[in]       numPoints is the number of output points to be computed.   
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+ *   
+ * \par   
+ * See arm_conv_partial_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.   
+ */
+
+arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+  q31_t *pIn1;                                   /* inputA pointer               */
+  q31_t *pIn2;                                   /* inputB pointer               */
+  q31_t *pOut = pDst;                            /* output pointer               */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q31_t x0, x1, x2, x3, c0;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters                 */
+  arm_status status;                             /* status of Partial convolution */
+
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds   
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t) check - (int32_t) srcALen);
+    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally   
+     * divided into three stages according to the number of multiplications that has to be   
+     * taken place between inputA samples and inputB samples. In the first stage of the   
+     * algorithm, the multiplications increase by one for every iteration.   
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+     * In the third stage of the algorithm, the multiplications decrease by one   
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex   
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------   
+     * Initializations of stage1   
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]   
+     * sum = x[0] * y[1] + x[1] * y[0]   
+     * ....   
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed.   
+       Since the partial convolution starts from firstIndex   
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------   
+     * Stage1 process   
+     * ----------------------*/
+
+    /* The first loop starts here */
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[0] * y[srcBLen - 1] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* x[1] * y[srcBLen - 2] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* x[2] * y[srcBLen - 3] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* x[3] * y[srcBLen - 4] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum << 1;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------   
+     * Initializations of stage2   
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+     * ....   
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+     */
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* count is index by which the pointer pIn1 to be incremented */
+    count = 1u;
+
+    /* -------------------   
+     * Stage2 process   
+     * ------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+     * So, to loop unroll over blockSize2,   
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+        /* read x[0], x[1], x[2] samples */
+        x0 = *(px++);
+        x1 = *(px++);
+        x2 = *(px++);
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read y[srcBLen - 1] sample */
+          c0 = *(py--);
+
+          /* Read x[3] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[0] * y[srcBLen - 1] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+          /* acc1 +=  x[1] * y[srcBLen - 1] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+          /* acc2 +=  x[2] * y[srcBLen - 1] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+          /* acc3 +=  x[3] * y[srcBLen - 1] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+          /* Read y[srcBLen - 2] sample */
+          c0 = *(py--);
+
+          /* Read x[4] sample */
+          x0 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[1] * y[srcBLen - 2] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+          /* acc1 +=  x[2] * y[srcBLen - 2] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+          /* acc2 +=  x[3] * y[srcBLen - 2] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+          /* acc3 +=  x[4] * y[srcBLen - 2] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+          /* Read y[srcBLen - 3] sample */
+          c0 = *(py--);
+
+          /* Read x[5] sample */
+          x1 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[2] * y[srcBLen - 3] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+          /* acc1 +=  x[3] * y[srcBLen - 2] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+          /* acc2 +=  x[4] * y[srcBLen - 2] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+          /* acc3 +=  x[5] * y[srcBLen - 2] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+          /* Read y[srcBLen - 4] sample */
+          c0 = *(py--);
+
+          /* Read x[6] sample */
+          x2 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[3] * y[srcBLen - 4] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+          /* acc1 +=  x[4] * y[srcBLen - 4] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+          /* acc2 +=  x[5] * y[srcBLen - 4] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+          /* acc3 +=  x[6] * y[srcBLen - 4] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+        } while(--k);
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Read y[srcBLen - 5] sample */
+          c0 = *(py--);
+
+          /* Read x[7] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[4] * y[srcBLen - 5] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+          /* acc1 +=  x[5] * y[srcBLen - 5] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+          /* acc2 +=  x[6] * y[srcBLen - 5] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+          /* acc3 +=  x[7] * y[srcBLen - 5] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+          /* Reuse the present samples for the next MAC */
+          x0 = x1;
+          x1 = x2;
+          x2 = x3;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q31_t) (acc0 << 1);
+        *pOut++ = (q31_t) (acc1 << 1);
+        *pOut++ = (q31_t) (acc2 << 1);
+        *pOut++ = (q31_t) (acc3 << 1);
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + (count * 4u);
+        py = pSrc2;
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = sum << 1;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,   
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = sum << 1;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------   
+     * Initializations of stage3   
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+     * ....   
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+     * sum +=  x[srcALen-1] * y[srcBLen-1]   
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* -------------------   
+     * Stage3 process   
+     * ------------------*/
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum << 1;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+}
+
+/**   
+ * @} end of PartialConv group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c
new file mode 100644
index 000000000..4a74726db
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c
@@ -0,0 +1,765 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_partial_q15.c   
+*   
+* Description:	Partial convolution of Q15 sequences.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup PartialConv   
+ * @{   
+ */
+
+/**   
+ * @brief Partial convolution of Q15 sequences.   
+ * @param[in]       *pSrcA points to the first input sequence.   
+ * @param[in]       srcALen length of the first input sequence.   
+ * @param[in]       *pSrcB points to the second input sequence.   
+ * @param[in]       srcBLen length of the second input sequence.   
+ * @param[out]      *pDst points to the location where the output result is written.   
+ * @param[in]       firstIndex is the first output sample to start with.   
+ * @param[in]       numPoints is the number of output points to be computed.   
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+ *   
+ * Refer to arm_conv_partial_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+
+arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary input variables */
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter                 */
+  arm_status status;                             /* status of Partial convolution */
+  q31_t *pb;                                     /* 32 bit pointer for inputB buffer */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds   
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t) check - (int32_t) srcALen);
+    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally   
+     * divided into three stages according to the number of multiplications that has to be   
+     * taken place between inputA samples and inputB samples. In the first stage of the   
+     * algorithm, the multiplications increase by one for every iteration.   
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+     * In the third stage of the algorithm, the multiplications decrease by one   
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex   
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------   
+     * Initializations of stage1   
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]   
+     * sum = x[0] * y[1] + x[1] * y[0]   
+     * ....   
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed.   
+       Since the partial convolution starts from firstIndex   
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------   
+     * Stage1 process   
+     * ----------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations less than 4 */
+    /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    while((count < 4u) && (blockSize1 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over number of MAC operations between   
+       * inputA samples and inputB samples */
+      k = count;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = __SMLALD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* The second part of the stage starts here */
+    /* The internal loop, over count, is unrolled by 4 */
+    /* To, read the last two inputB samples using SIMD:   
+     * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+    py = py - 1;
+
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+        /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* For the next MAC operations, the pointer py is used without SIMD   
+       * So, py is incremented by 1 */
+      py = py + 1u;
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = __SMLALD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2 - 1u;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------   
+     * Initializations of stage2   
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+     * ....   
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+     */
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* Initialize inputB pointer of type q31 */
+    pb = (q31_t *) (py - 1u);
+
+    /* count is the index by which the pointer pIn1 to be incremented */
+    count = 1u;
+
+
+    /* --------------------   
+     * Stage2 process   
+     * -------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+     * So, to loop unroll over blockSize2,   
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2, by 4 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+
+        /* read x[0], x[1] samples */
+        x0 = *(q31_t *) (px++);
+        /* read x[1], x[2] samples */
+        x1 = *(q31_t *) (px++);
+
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read the last two inputB samples using SIMD:   
+           * y[srcBLen - 1] and y[srcBLen - 2] */
+          c0 = *(pb--);
+
+          /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+          acc0 = __SMLALDX(x0, c0, acc0);
+
+          /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+          acc1 = __SMLALDX(x1, c0, acc1);
+
+          /* Read x[2], x[3] */
+          x2 = *(q31_t *) (px++);
+
+          /* Read x[3], x[4] */
+          x3 = *(q31_t *) (px++);
+
+          /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+          acc2 = __SMLALDX(x2, c0, acc2);
+
+          /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+          acc3 = __SMLALDX(x3, c0, acc3);
+
+          /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+          c0 = *(pb--);
+
+          /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+          acc0 = __SMLALDX(x2, c0, acc0);
+
+          /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+          acc1 = __SMLALDX(x3, c0, acc1);
+
+          /* Read x[4], x[5] */
+          x0 = *(q31_t *) (px++);
+
+          /* Read x[5], x[6] */
+          x1 = *(q31_t *) (px++);
+
+          /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+          acc2 = __SMLALDX(x0, c0, acc2);
+
+          /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+          acc3 = __SMLALDX(x1, c0, acc3);
+
+        } while(--k);
+
+        /* For the next MAC operations, SIMD is not used   
+         * So, the 16 bit pointer if inputB, py is updated */
+        py = (q15_t *) pb;
+        py = py + 1;
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        if(k == 1u)
+        {
+          /* Read y[srcBLen - 5] */
+          c0 = *(py);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+          c0 = c0 << 16u;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+          /* Read x[7] */
+          x3 = *(q31_t *) px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLALD(x0, c0, acc0);
+          acc1 = __SMLALD(x1, c0, acc1);
+          acc2 = __SMLALDX(x1, c0, acc2);
+          acc3 = __SMLALDX(x3, c0, acc3);
+        }
+
+        if(k == 2u)
+        {
+          /* Read y[srcBLen - 5], y[srcBLen - 6] */
+          c0 = *(pb);
+
+          /* Read x[7], x[8] */
+          x3 = *(q31_t *) px++;
+
+          /* Read x[9] */
+          x2 = *(q31_t *) px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLALDX(x0, c0, acc0);
+          acc1 = __SMLALDX(x1, c0, acc1);
+          acc2 = __SMLALDX(x3, c0, acc2);
+          acc3 = __SMLALDX(x2, c0, acc3);
+        }
+
+        if(k == 3u)
+        {
+          /* Read y[srcBLen - 5], y[srcBLen - 6] */
+          c0 = *pb--;
+
+          /* Read x[7], x[8] */
+          x3 = *(q31_t *) px++;
+
+          /* Read x[9] */
+          x2 = *(q31_t *) px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLALDX(x0, c0, acc0);
+          acc1 = __SMLALDX(x1, c0, acc1);
+          acc2 = __SMLALDX(x3, c0, acc2);
+          acc3 = __SMLALDX(x2, c0, acc3);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+          /* Read y[srcBLen - 7] */
+          c0 = (*pb);
+          c0 = (c0) << 16;
+
+#else
+
+          /* Read y[srcBLen - 7] */
+          c0 = (q15_t) (*pb >> 16);
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+          /* Read x[10] */
+          x3 = *(q31_t *) px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLALDX(x1, c0, acc0);
+          acc1 = __SMLALD(x2, c0, acc1);
+          acc2 = __SMLALDX(x2, c0, acc2);
+          acc3 = __SMLALDX(x3, c0, acc3);
+        }
+
+        /* Store the results in the accumulators in the destination buffer. */
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+        *__SIMD32(pOut)++ =
+          __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+        *__SIMD32(pOut)++ =
+          __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+        *__SIMD32(pOut)++ =
+          __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+        *__SIMD32(pOut)++ =
+          __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + (count * 4u);
+        py = pSrc2;
+        pb = (q31_t *) (py - 1);
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,   
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------   
+     * Initializations of stage3   
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+     * ....   
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+     * sum +=  x[srcALen-1] * y[srcBLen-1]   
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    pIn2 = pSrc2 - 1u;
+    py = pIn2;
+
+    /* -------------------   
+     * Stage3 process   
+     * ------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations greater than 4 */
+    /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    j = count >> 2u;
+
+    while((j > 0u) && (blockSize3 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
+         * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+        /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
+         * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* For the next MAC operations, the pointer py is used without SIMD   
+       * So, py is incremented by 1 */
+      py = py + 1u;
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+        sum = __SMLALD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pIn2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+      j--;
+    }
+
+    /* The second part of the stage starts here */
+    /* SIMD is not used for the next MAC operations,   
+     * so pointer py is updated to read only one sample at a time */
+    py = py + 1u;
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum = __SMLALD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t *pIn1 = pSrcA;                           /* inputA pointer */
+  q15_t *pIn2 = pSrcB;                           /* inputB pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Loop to calculate convolution for output length number of values */
+    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+    {
+      /* Initialize sum with zero to carry on MAC operations */
+      sum = 0;
+
+      /* Loop to perform MAC operations according to convolution equation */
+      for (j = 0; j <= i; j++)
+      {
+        /* Check the array limitations */
+        if(((i - j) < srcBLen) && (j < srcALen))
+        {
+          /* z[i] += x[i-j] * y[j] */
+          sum += ((q31_t) pIn1[j] * (pIn2[i - j]));
+        }
+      }
+
+      /* Store the output in the destination buffer */
+      pDst[i] = (q15_t) __SSAT((sum >> 15u), 16u);
+    }
+    /* set status as ARM_SUCCESS as there are no argument errors */
+    status = ARM_MATH_SUCCESS;
+  }
+  return (status);
+
+#endif /*     #ifndef ARM_MATH_CM0      */
+
+}
+
+/**   
+ * @} end of PartialConv group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c
new file mode 100644
index 000000000..a592d74d1
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c
@@ -0,0 +1,616 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_partial_q31.c   
+*   
+* Description:	Partial convolution of Q31 sequences.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup PartialConv   
+ * @{   
+ */
+
+/**   
+ * @brief Partial convolution of Q31 sequences.   
+ * @param[in]       *pSrcA points to the first input sequence.   
+ * @param[in]       srcALen length of the first input sequence.   
+ * @param[in]       *pSrcB points to the second input sequence.   
+ * @param[in]       srcBLen length of the second input sequence.   
+ * @param[out]      *pDst points to the location where the output result is written.   
+ * @param[in]       firstIndex is the first output sample to start with.   
+ * @param[in]       numPoints is the number of output points to be computed.   
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+ *   
+ * See arm_conv_partial_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn1;                                   /* inputA pointer               */
+  q31_t *pIn2;                                   /* inputB pointer               */
+  q31_t *pOut = pDst;                            /* output pointer               */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */
+  q31_t x0, x1, x2, x3, c0;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter                 */
+  arm_status status;                             /* status of Partial convolution */
+
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds   
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t) check - (int32_t) srcALen);
+    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally   
+     * divided into three stages according to the number of multiplications that has to be   
+     * taken place between inputA samples and inputB samples. In the first stage of the   
+     * algorithm, the multiplications increase by one for every iteration.   
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+     * In the third stage of the algorithm, the multiplications decrease by one   
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex   
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------   
+     * Initializations of stage1   
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]   
+     * sum = x[0] * y[1] + x[1] * y[0]   
+     * ....   
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed.   
+       Since the partial convolution starts from firstIndex   
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------   
+     * Stage1 process   
+     * ----------------------*/
+
+    /* The first loop starts here */
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[0] * y[srcBLen - 1] */
+        sum += (q63_t) * px++ * (*py--);
+        /* x[1] * y[srcBLen - 2] */
+        sum += (q63_t) * px++ * (*py--);
+        /* x[2] * y[srcBLen - 3] */
+        sum += (q63_t) * px++ * (*py--);
+        /* x[3] * y[srcBLen - 4] */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q31_t) (sum >> 31);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------   
+     * Initializations of stage2   
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+     * ....   
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+     */
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* count is index by which the pointer pIn1 to be incremented */
+    count = 1u;
+
+    /* -------------------   
+     * Stage2 process   
+     * ------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+     * So, to loop unroll over blockSize2,   
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+        /* read x[0], x[1], x[2] samples */
+        x0 = *(px++);
+        x1 = *(px++);
+        x2 = *(px++);
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read y[srcBLen - 1] sample */
+          c0 = *(py--);
+
+          /* Read x[3] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[0] * y[srcBLen - 1] */
+          acc0 += (q63_t) x0 *c0;
+          /* acc1 +=  x[1] * y[srcBLen - 1] */
+          acc1 += (q63_t) x1 *c0;
+          /* acc2 +=  x[2] * y[srcBLen - 1] */
+          acc2 += (q63_t) x2 *c0;
+          /* acc3 +=  x[3] * y[srcBLen - 1] */
+          acc3 += (q63_t) x3 *c0;
+
+          /* Read y[srcBLen - 2] sample */
+          c0 = *(py--);
+
+          /* Read x[4] sample */
+          x0 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[1] * y[srcBLen - 2] */
+          acc0 += (q63_t) x1 *c0;
+          /* acc1 +=  x[2] * y[srcBLen - 2] */
+          acc1 += (q63_t) x2 *c0;
+          /* acc2 +=  x[3] * y[srcBLen - 2] */
+          acc2 += (q63_t) x3 *c0;
+          /* acc3 +=  x[4] * y[srcBLen - 2] */
+          acc3 += (q63_t) x0 *c0;
+
+          /* Read y[srcBLen - 3] sample */
+          c0 = *(py--);
+
+          /* Read x[5] sample */
+          x1 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[2] * y[srcBLen - 3] */
+          acc0 += (q63_t) x2 *c0;
+          /* acc1 +=  x[3] * y[srcBLen - 2] */
+          acc1 += (q63_t) x3 *c0;
+          /* acc2 +=  x[4] * y[srcBLen - 2] */
+          acc2 += (q63_t) x0 *c0;
+          /* acc3 +=  x[5] * y[srcBLen - 2] */
+          acc3 += (q63_t) x1 *c0;
+
+          /* Read y[srcBLen - 4] sample */
+          c0 = *(py--);
+
+          /* Read x[6] sample */
+          x2 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[3] * y[srcBLen - 4] */
+          acc0 += (q63_t) x3 *c0;
+          /* acc1 +=  x[4] * y[srcBLen - 4] */
+          acc1 += (q63_t) x0 *c0;
+          /* acc2 +=  x[5] * y[srcBLen - 4] */
+          acc2 += (q63_t) x1 *c0;
+          /* acc3 +=  x[6] * y[srcBLen - 4] */
+          acc3 += (q63_t) x2 *c0;
+
+        } while(--k);
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Read y[srcBLen - 5] sample */
+          c0 = *(py--);
+
+          /* Read x[7] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[4] * y[srcBLen - 5] */
+          acc0 += (q63_t) x0 *c0;
+          /* acc1 +=  x[5] * y[srcBLen - 5] */
+          acc1 += (q63_t) x1 *c0;
+          /* acc2 +=  x[6] * y[srcBLen - 5] */
+          acc2 += (q63_t) x2 *c0;
+          /* acc3 +=  x[7] * y[srcBLen - 5] */
+          acc3 += (q63_t) x3 *c0;
+
+          /* Reuse the present samples for the next MAC */
+          x0 = x1;
+          x1 = x2;
+          x2 = x3;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q31_t) (acc0 >> 31);
+        *pOut++ = (q31_t) (acc1 >> 31);
+        *pOut++ = (q31_t) (acc2 >> 31);
+        *pOut++ = (q31_t) (acc3 >> 31);
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + (count * 4u);
+        py = pSrc2;
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) * px++ * (*py--);
+          sum += (q63_t) * px++ * (*py--);
+          sum += (q63_t) * px++ * (*py--);
+          sum += (q63_t) * px++ * (*py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += (q63_t) * px++ * (*py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q31_t) (sum >> 31);
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,   
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += (q63_t) * px++ * (*py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q31_t) (sum >> 31);
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------   
+     * Initializations of stage3   
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+     * ....   
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+     * sum +=  x[srcALen-1] * y[srcBLen-1]   
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.   
+       The blockSize3 variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* -------------------   
+     * Stage3 process   
+     * ------------------*/
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q31_t) (sum >> 31);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t *pIn1 = pSrcA;                           /* inputA pointer */
+  q31_t *pIn2 = pSrcB;                           /* inputB pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Loop to calculate convolution for output length number of values */
+    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+    {
+      /* Initialize sum with zero to carry on MAC operations */
+      sum = 0;
+
+      /* Loop to perform MAC operations according to convolution equation */
+      for (j = 0; j <= i; j++)
+      {
+        /* Check the array limitations */
+        if(((i - j) < srcBLen) && (j < srcALen))
+        {
+          /* z[i] += x[i-j] * y[j] */
+          sum += ((q63_t) pIn1[j] * (pIn2[i - j]));
+        }
+      }
+
+      /* Store the output in the destination buffer */
+      pDst[i] = (q31_t) (sum >> 31u);
+    }
+    /* set status as ARM_SUCCESS as there are no argument errors */
+    status = ARM_MATH_SUCCESS;
+  }
+  return (status);
+
+#endif /*    #ifndef ARM_MATH_CM0      */
+
+}
+
+/**   
+ * @} end of PartialConv group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c
new file mode 100644
index 000000000..d49903fa5
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c
@@ -0,0 +1,723 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_partial_q7.c   
+*   
+* Description:	Partial convolution of Q7 sequences.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup PartialConv   
+ * @{   
+ */
+
+/**   
+ * @brief Partial convolution of Q7 sequences.   
+ * @param[in]       *pSrcA points to the first input sequence.   
+ * @param[in]       srcALen length of the first input sequence.   
+ * @param[in]       *pSrcB points to the second input sequence.   
+ * @param[in]       srcBLen length of the second input sequence.   
+ * @param[out]      *pDst points to the location where the output result is written.   
+ * @param[in]       firstIndex is the first output sample to start with.   
+ * @param[in]       numPoints is the number of output points to be computed.   
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+ *   
+ */
+
+arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t *pIn1;                                    /* inputA pointer */
+  q7_t *pIn2;                                    /* inputB pointer */
+  q7_t *pOut = pDst;                             /* output pointer */
+  q7_t *px;                                      /* Intermediate inputA pointer */
+  q7_t *py;                                      /* Intermediate inputB pointer */
+  q7_t *pSrc1, *pSrc2;                           /* Intermediate pointers */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q31_t input1, input2;
+  q15_t in1, in2;
+  q7_t x0, x1, x2, x3, c0, c1;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter */
+  arm_status status;
+
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds   
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t) check - (int32_t) srcALen);
+    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally   
+     * divided into three stages according to the number of multiplications that has to be   
+     * taken place between inputA samples and inputB samples. In the first stage of the   
+     * algorithm, the multiplications increase by one for every iteration.   
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+     * In the third stage of the algorithm, the multiplications decrease by one   
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex   
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------   
+     * Initializations of stage1   
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]   
+     * sum = x[0] * y[1] + x[1] * y[0]   
+     * ....   
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed.   
+       Since the partial convolution starts from from firstIndex   
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------   
+     * Stage1 process   
+     * ----------------------*/
+
+    /* The first stage starts here */
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[0] , x[1] */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* y[srcBLen - 1] , y[srcBLen - 2] */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* x[0] * y[srcBLen - 1] */
+        /* x[1] * y[srcBLen - 2] */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* x[2] , x[3] */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* y[srcBLen - 3] , y[srcBLen - 4] */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* x[2] * y[srcBLen - 3] */
+        /* x[3] * y[srcBLen - 4] */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------   
+     * Initializations of stage2   
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+     * ....   
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+     */
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* count is index by which the pointer pIn1 to be incremented */
+    count = 1u;
+
+    /* -------------------   
+     * Stage2 process   
+     * ------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+     * So, to loop unroll over blockSize2,   
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2, by 4 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+        /* read x[0], x[1], x[2] samples */
+        x0 = *(px++);
+        x1 = *(px++);
+        x2 = *(px++);
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read y[srcBLen - 1] sample */
+          c0 = *(py--);
+          /* Read y[srcBLen - 2] sample */
+          c1 = *(py--);
+
+          /* Read x[3] sample */
+          x3 = *(px++);
+
+          /* x[0] and x[1] are packed */
+          in1 = (q15_t) x0;
+          in2 = (q15_t) x1;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* y[srcBLen - 1]   and y[srcBLen - 2] are packed */
+          in1 = (q15_t) c0;
+          in2 = (q15_t) c1;
+
+          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2]  */
+          acc0 = __SMLAD(input1, input2, acc0);
+
+          /* x[1] and x[2] are packed */
+          in1 = (q15_t) x1;
+          in2 = (q15_t) x2;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2]  */
+          acc1 = __SMLAD(input1, input2, acc1);
+
+          /* x[2] and x[3] are packed */
+          in1 = (q15_t) x2;
+          in2 = (q15_t) x3;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2]  */
+          acc2 = __SMLAD(input1, input2, acc2);
+
+          /* Read x[4] sample */
+          x0 = *(px++);
+
+          /* x[3] and x[4] are packed */
+          in1 = (q15_t) x3;
+          in2 = (q15_t) x0;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2]  */
+          acc3 = __SMLAD(input1, input2, acc3);
+
+          /* Read y[srcBLen - 3] sample */
+          c0 = *(py--);
+          /* Read y[srcBLen - 4] sample */
+          c1 = *(py--);
+
+          /* Read x[5] sample */
+          x1 = *(px++);
+
+          /* x[2] and x[3] are packed */
+          in1 = (q15_t) x2;
+          in2 = (q15_t) x3;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
+          in1 = (q15_t) c0;
+          in2 = (q15_t) c1;
+
+          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4]  */
+          acc0 = __SMLAD(input1, input2, acc0);
+
+          /* x[3] and x[4] are packed */
+          in1 = (q15_t) x3;
+          in2 = (q15_t) x0;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4]  */
+          acc1 = __SMLAD(input1, input2, acc1);
+
+          /* x[4] and x[5] are packed */
+          in1 = (q15_t) x0;
+          in2 = (q15_t) x1;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4]  */
+          acc2 = __SMLAD(input1, input2, acc2);
+
+          /* Read x[6] sample */
+          x2 = *(px++);
+
+          /* x[5] and x[6] are packed */
+          in1 = (q15_t) x1;
+          in2 = (q15_t) x2;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4]  */
+          acc3 = __SMLAD(input1, input2, acc3);
+
+        } while(--k);
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Read y[srcBLen - 5] sample */
+          c0 = *(py--);
+
+          /* Read x[7] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[4] * y[srcBLen - 5] */
+          acc0 += ((q31_t) x0 * c0);
+          /* acc1 +=  x[5] * y[srcBLen - 5] */
+          acc1 += ((q31_t) x1 * c0);
+          /* acc2 +=  x[6] * y[srcBLen - 5] */
+          acc2 += ((q31_t) x2 * c0);
+          /* acc3 +=  x[7] * y[srcBLen - 5] */
+          acc3 += ((q31_t) x3 * c0);
+
+          /* Reuse the present samples for the next MAC */
+          x0 = x1;
+          x1 = x2;
+          x2 = x3;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q7_t) (__SSAT(acc0 >> 7, 8));
+        *pOut++ = (q7_t) (__SSAT(acc1 >> 7, 8));
+        *pOut++ = (q7_t) (__SSAT(acc2 >> 7, 8));
+        *pOut++ = (q7_t) (__SSAT(acc3 >> 7, 8));
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count * 4u;
+        py = pSrc2;
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+
+          /* Reading two inputs of SrcA buffer and packing */
+          in1 = (q15_t) * px++;
+          in2 = (q15_t) * px++;
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* Reading two inputs of SrcB buffer and packing */
+          in1 = (q15_t) * py--;
+          in2 = (q15_t) * py--;
+          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* Perform the multiply-accumulates */
+          sum = __SMLAD(input1, input2, sum);
+
+          /* Reading two inputs of SrcA buffer and packing */
+          in1 = (q15_t) * px++;
+          in2 = (q15_t) * px++;
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* Reading two inputs of SrcB buffer and packing */
+          in1 = (q15_t) * py--;
+          in2 = (q15_t) * py--;
+          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* Perform the multiply-accumulates */
+          sum = __SMLAD(input1, input2, sum);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,   
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------   
+     * Initializations of stage3   
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+     * ....   
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+     * sum +=  x[srcALen-1] * y[srcBLen-1]   
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* -------------------   
+     * Stage3 process   
+     * ------------------*/
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q7_t *pIn1 = pSrcA;                            /* inputA pointer */
+  q7_t *pIn2 = pSrcB;                            /* inputB pointer */
+  q31_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Loop to calculate convolution for output length number of values */
+    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+    {
+      /* Initialize sum with zero to carry on MAC operations */
+      sum = 0;
+
+      /* Loop to perform MAC operations according to convolution equation */
+      for (j = 0; j <= i; j++)
+      {
+        /* Check the array limitations */
+        if(((i - j) < srcBLen) && (j < srcALen))
+        {
+          /* z[i] += x[i-j] * y[j] */
+          sum += ((q15_t) pIn1[j] * (pIn2[i - j]));
+        }
+      }
+
+      /* Store the output in the destination buffer */
+      pDst[i] = (q7_t) __SSAT((sum >> 7u), 8u);
+    }
+    /* set status as ARM_SUCCESS as there are no argument errors */
+    status = ARM_MATH_SUCCESS;
+  }
+  return (status);
+
+#endif /*  #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of PartialConv group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c
new file mode 100644
index 000000000..a33a834ff
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c
@@ -0,0 +1,727 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_q15.c   
+*   
+* Description:	Convolution of Q15 sequences.     
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Conv   
+ * @{   
+ */
+
+/**   
+ * @brief Convolution of Q15 sequences.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * This approach provides 33 guard bits and there is no risk of overflow.   
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.   
+ *   
+ * \par   
+ * Refer to arm_conv_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *pOut = pDst;                            /* output pointer */
+  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
+  uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt;     /* loop counter */
+  q31_t *pb;                                     /* 32 bit pointer for inputB buffer */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally   
+   * divided into three stages according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first stage of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+   * In the third stage of the algorithm, the multiplications decrease by one   
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.   
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]   
+   * sum = x[0] * y[1] + x[1] * y[0]   
+   * ....   
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations less than 4 */
+  /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  while((count < 4u) && (blockSize1 > 0u))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Loop over number of MAC operations between   
+     * inputA samples and inputB samples */
+    k = count;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLALD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* The second part of the stage starts here */
+  /* The internal loop, over count, is unrolled by 4 */
+  /* To, read the last two inputB samples using SIMD:   
+   * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+  py = py - 1;
+
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+      /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* For the next MAC operations, the pointer py is used without SIMD   
+     * So, py is incremented by 1 */
+    py = py + 1u;
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLALD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + (count - 1u);
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* Initialize inputB pointer of type q31 */
+  pb = (q31_t *) (py - 1u);
+
+  /* count is the index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+
+  /* --------------------   
+   * Stage2 process   
+   * -------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+
+      /* read x[0], x[1] samples */
+      x0 = *(q31_t *) (px++);
+      /* read x[1], x[2] samples */
+      x1 = *(q31_t *) (px++);
+
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the last two inputB samples using SIMD:   
+         * y[srcBLen - 1] and y[srcBLen - 2] */
+        c0 = *(pb--);
+
+        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+        acc0 = __SMLALDX(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+        acc1 = __SMLALDX(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *(q31_t *) (px++);
+
+        /* Read x[3], x[4] */
+        x3 = *(q31_t *) (px++);
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+        acc2 = __SMLALDX(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+        acc3 = __SMLALDX(x3, c0, acc3);
+
+        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+        c0 = *(pb--);
+
+        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+        acc0 = __SMLALDX(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+        acc1 = __SMLALDX(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = *(q31_t *) (px++);
+
+        /* Read x[5], x[6] */
+        x1 = *(q31_t *) (px++);
+
+        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+        acc2 = __SMLALDX(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+        acc3 = __SMLALDX(x1, c0, acc3);
+
+      } while(--k);
+
+      /* For the next MAC operations, SIMD is not used   
+       * So, the 16 bit pointer if inputB, py is updated */
+      py = (q15_t *) pb;
+      py = py + 1;
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[srcBLen - 5] */
+        c0 = *(py);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+        x3 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALDX(x1, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = *(pb);
+
+        /* Read x[7], x[8] */
+        x3 = *(q31_t *) px++;
+
+        /* Read x[9] */
+        x2 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x0, c0, acc0);
+        acc1 = __SMLALDX(x1, c0, acc1);
+        acc2 = __SMLALDX(x3, c0, acc2);
+        acc3 = __SMLALDX(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = *pb--;
+
+        /* Read x[7], x[8] */
+        x3 = *(q31_t *) px++;
+
+        /* Read x[9] */
+        x2 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x0, c0, acc0);
+        acc1 = __SMLALDX(x1, c0, acc1);
+        acc2 = __SMLALDX(x3, c0, acc2);
+        acc3 = __SMLALDX(x2, c0, acc3);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        /* Read y[srcBLen - 7] */
+        c0 = (*pb);
+
+        //c0 = (c0 & 0x0000FFFF)<<16; 
+        c0 = (c0) << 16;
+
+#else
+
+        /* Read y[srcBLen - 7] */
+        c0 = (q15_t) (*pb >> 16);
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+        x3 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x1, c0, acc0);
+        acc1 = __SMLALD(x2, c0, acc1);
+        acc2 = __SMLALDX(x2, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+
+      /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pSrc2;
+      pb = (q31_t *) (py - 1);
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+   * sum +=  x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  blockSize3 = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  pIn2 = pSrc2 - 1u;
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations greater than 4 */
+  /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  j = blockSize3 >> 2u;
+
+  while((j > 0u) && (blockSize3 > 0u))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
+       * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+      /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
+       * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* For the next MAC operations, the pointer py is used without SIMD   
+     * So, py is incremented by 1 */
+    py = py + 1u;
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+      sum = __SMLALD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+
+    j--;
+  }
+
+  /* The second part of the stage starts here */
+  /* SIMD is not used for the next MAC operations,   
+   * so pointer py is updated to read only one sample at a time */
+  py = py + 1u;
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+      sum = __SMLALD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q15_t *pIn1 = pSrcA;                           /* input pointer */
+  q15_t *pIn2 = pSrcB;                           /* coefficient pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counter */
+
+  /* Loop to calculate output of convolution for output length number of times */
+  for (i = 0; i < (srcALen + srcBLen - 1); i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if(((i - j) < srcBLen) && (j < srcALen))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += (q31_t) pIn1[j] * (pIn2[i - j]);
+      }
+    }
+
+    /* Store the output in the destination buffer */
+    pDst[i] = (q15_t) __SSAT((sum >> 15u), 16u);
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of Conv group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c
new file mode 100644
index 000000000..22a2a9574
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c
@@ -0,0 +1,583 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_q31.c   
+*   
+* Description:	Convolution of Q31 sequences. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Conv   
+ * @{   
+ */
+
+/**   
+ * @brief Convolution of Q31 sequences.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * There is no saturation on intermediate additions.   
+ * Thus, if the accumulator overflows it wraps around and distorts the result.   
+ * The input signals should be scaled down to avoid intermediate overflows.   
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,   
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.   
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.   
+ *   
+ * \par   
+ * See arm_conv_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn1;                                   /* inputA pointer */
+  q31_t *pIn2;                                   /* inputB pointer */
+  q31_t *pOut = pDst;                            /* output pointer */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q63_t sum;                                     /* Accumulator */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
+  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (q31_t *) pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = (q31_t *) pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally   
+   * divided into three stages according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first stage of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+   * In the third stage of the algorithm, the multiplications decrease by one   
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.   
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]   
+   * sum = x[0] * y[1] + x[1] * y[0]   
+   * ....   
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 1] */
+      sum += (q63_t) * px++ * (*py--);
+      /* x[1] * y[srcBLen - 2] */
+      sum += (q63_t) * px++ * (*py--);
+      /* x[2] * y[srcBLen - 3] */
+      sum += (q63_t) * px++ * (*py--);
+      /* x[3] * y[srcBLen - 4] */
+      sum += (q63_t) * px++ * (*py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (q63_t) * px++ * (*py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q31_t) (sum >> 31);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[srcBLen - 1] sample */
+        c0 = *(py--);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[0] * y[srcBLen - 1] */
+        acc0 += ((q63_t) x0 * c0);
+        /* acc1 +=  x[1] * y[srcBLen - 1] */
+        acc1 += ((q63_t) x1 * c0);
+        /* acc2 +=  x[2] * y[srcBLen - 1] */
+        acc2 += ((q63_t) x2 * c0);
+        /* acc3 +=  x[3] * y[srcBLen - 1] */
+        acc3 += ((q63_t) x3 * c0);
+
+        /* Read y[srcBLen - 2] sample */
+        c0 = *(py--);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[1] * y[srcBLen - 2] */
+        acc0 += ((q63_t) x1 * c0);
+        /* acc1 +=  x[2] * y[srcBLen - 2] */
+        acc1 += ((q63_t) x2 * c0);
+        /* acc2 +=  x[3] * y[srcBLen - 2] */
+        acc2 += ((q63_t) x3 * c0);
+        /* acc3 +=  x[4] * y[srcBLen - 2] */
+        acc3 += ((q63_t) x0 * c0);
+
+        /* Read y[srcBLen - 3] sample */
+        c0 = *(py--);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[srcBLen - 3] */
+        acc0 += ((q63_t) x2 * c0);
+        /* acc1 +=  x[3] * y[srcBLen - 2] */
+        acc1 += ((q63_t) x3 * c0);
+        /* acc2 +=  x[4] * y[srcBLen - 2] */
+        acc2 += ((q63_t) x0 * c0);
+        /* acc3 +=  x[5] * y[srcBLen - 2] */
+        acc3 += ((q63_t) x1 * c0);
+
+        /* Read y[srcBLen - 4] sample */
+        c0 = *(py--);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[srcBLen - 4] */
+        acc0 += ((q63_t) x3 * c0);
+        /* acc1 +=  x[4] * y[srcBLen - 4] */
+        acc1 += ((q63_t) x0 * c0);
+        /* acc2 +=  x[5] * y[srcBLen - 4] */
+        acc2 += ((q63_t) x1 * c0);
+        /* acc3 +=  x[6] * y[srcBLen - 4] */
+        acc3 += ((q63_t) x2 * c0);
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[srcBLen - 5] sample */
+        c0 = *(py--);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[srcBLen - 5] */
+        acc0 += ((q63_t) x0 * c0);
+        /* acc1 +=  x[5] * y[srcBLen - 5] */
+        acc1 += ((q63_t) x1 * c0);
+        /* acc2 +=  x[6] * y[srcBLen - 5] */
+        acc2 += ((q63_t) x2 * c0);
+        /* acc3 +=  x[7] * y[srcBLen - 5] */
+        acc3 += ((q63_t) x3 * c0);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the results in the accumulators in the destination buffer. */
+      *pOut++ = (q31_t) (acc0 >> 31);
+      *pOut++ = (q31_t) (acc1 >> 31);
+      *pOut++ = (q31_t) (acc2 >> 31);
+      *pOut++ = (q31_t) (acc3 >> 31);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pSrc2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q31_t) (sum >> 31);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q31_t) (sum >> 31);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+   * sum +=  x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+      sum += (q63_t) * px++ * (*py--);
+      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+      sum += (q63_t) * px++ * (*py--);
+      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+      sum += (q63_t) * px++ * (*py--);
+      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+      sum += (q63_t) * px++ * (*py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (q63_t) * px++ * (*py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q31_t) (sum >> 31);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t *pIn1 = pSrcA;                           /* input pointer */
+  q31_t *pIn2 = pSrcB;                           /* coefficient pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counter */
+
+  /* Loop to calculate output of convolution for output length number of times */
+  for (i = 0; i < (srcALen + srcBLen - 1); i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if(((i - j) < srcBLen) && (j < srcALen))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += ((q63_t) pIn1[j] * (pIn2[i - j]));
+      }
+    }
+
+    /* Store the output in the destination buffer */
+    pDst[i] = (q31_t) (sum >> 31u);
+  }
+
+#endif /*     #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of Conv group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c
new file mode 100644
index 000000000..6f844dd68
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c
@@ -0,0 +1,680 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_q7.c   
+*   
+* Description:	Convolution of Q7 sequences. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Conv   
+ * @{   
+ */
+
+/**   
+ * @brief Convolution of Q7 sequences.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 32-bit internal accumulator.   
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.   
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.   
+ * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.   
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.   
+ */
+
+void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t *pIn1;                                    /* inputA pointer */
+  q7_t *pIn2;                                    /* inputB pointer */
+  q7_t *pOut = pDst;                             /* output pointer */
+  q7_t *px;                                      /* Intermediate inputA pointer */
+  q7_t *py;                                      /* Intermediate inputB pointer */
+  q7_t *pSrc1, *pSrc2;                           /* Intermediate pointers */
+  q7_t x0, x1, x2, x3, c0, c1;                   /* Temporary variables to hold state and coefficient values */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q31_t input1, input2;                          /* Temporary input variables */
+  q15_t in1, in2;                                /* Temporary input variables */
+  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally   
+   * divided into three stages according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first stage of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+   * In the third stage of the algorithm, the multiplications decrease by one   
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.   
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = (srcALen - srcBLen) + 1u;
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]   
+   * sum = x[0] * y[1] + x[1] * y[0]   
+   * ....   
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] , x[1] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* y[srcBLen - 1] , y[srcBLen - 2] */
+      in1 = (q15_t) * py--;
+      in2 = (q15_t) * py--;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* x[0] * y[srcBLen - 1] */
+      /* x[1] * y[srcBLen - 2] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* x[2] , x[3] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* y[srcBLen - 3] , y[srcBLen - 4] */
+      in1 = (q15_t) * py--;
+      in2 = (q15_t) * py--;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* x[2] * y[srcBLen - 3] */
+      /* x[3] * y[srcBLen - 4] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += ((q15_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[srcBLen - 1] sample */
+        c0 = *(py--);
+        /* Read y[srcBLen - 2] sample */
+        c1 = *(py--);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* x[0] and x[1] are packed */
+        in1 = (q15_t) x0;
+        in2 = (q15_t) x1;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* y[srcBLen - 1]   and y[srcBLen - 2] are packed */
+        in1 = (q15_t) c0;
+        in2 = (q15_t) c1;
+
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2]  */
+        acc0 = __SMLAD(input1, input2, acc0);
+
+        /* x[1] and x[2] are packed */
+        in1 = (q15_t) x1;
+        in2 = (q15_t) x2;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2]  */
+        acc1 = __SMLAD(input1, input2, acc1);
+
+        /* x[2] and x[3] are packed */
+        in1 = (q15_t) x2;
+        in2 = (q15_t) x3;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2]  */
+        acc2 = __SMLAD(input1, input2, acc2);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* x[3] and x[4] are packed */
+        in1 = (q15_t) x3;
+        in2 = (q15_t) x0;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2]  */
+        acc3 = __SMLAD(input1, input2, acc3);
+
+        /* Read y[srcBLen - 3] sample */
+        c0 = *(py--);
+        /* Read y[srcBLen - 4] sample */
+        c1 = *(py--);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* x[2] and x[3] are packed */
+        in1 = (q15_t) x2;
+        in2 = (q15_t) x3;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
+        in1 = (q15_t) c0;
+        in2 = (q15_t) c1;
+
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4]  */
+        acc0 = __SMLAD(input1, input2, acc0);
+
+        /* x[3] and x[4] are packed */
+        in1 = (q15_t) x3;
+        in2 = (q15_t) x0;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4]  */
+        acc1 = __SMLAD(input1, input2, acc1);
+
+        /* x[4] and x[5] are packed */
+        in1 = (q15_t) x0;
+        in2 = (q15_t) x1;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4]  */
+        acc2 = __SMLAD(input1, input2, acc2);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* x[5] and x[6] are packed */
+        in1 = (q15_t) x1;
+        in2 = (q15_t) x2;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4]  */
+        acc3 = __SMLAD(input1, input2, acc3);
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[srcBLen - 5] sample */
+        c0 = *(py--);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[srcBLen - 5] */
+        acc0 += ((q15_t) x0 * c0);
+        /* acc1 +=  x[5] * y[srcBLen - 5] */
+        acc1 += ((q15_t) x1 * c0);
+        /* acc2 +=  x[6] * y[srcBLen - 5] */
+        acc2 += ((q15_t) x2 * c0);
+        /* acc3 +=  x[7] * y[srcBLen - 5] */
+        acc3 += ((q15_t) x3 * c0);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
+      *pOut++ = (q7_t) (__SSAT(acc1 >> 7u, 8));
+      *pOut++ = (q7_t) (__SSAT(acc2 >> 7u, 8));
+      *pOut++ = (q7_t) (__SSAT(acc3 >> 7u, 8));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pSrc2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+
+        /* Reading two inputs of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* Reading two inputs of SrcB buffer and packing */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Reading two inputs of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* Reading two inputs of SrcB buffer and packing */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q15_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q15_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+   * sum +=  x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
+      in1 = (q15_t) * py--;
+      in2 = (q15_t) * py--;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
+      in1 = (q15_t) * py--;
+      in2 = (q15_t) * py--;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += ((q15_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q7_t *pIn1 = pSrcA;                            /* input pointer */
+  q7_t *pIn2 = pSrcB;                            /* coefficient pointer */
+  q31_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counter */
+
+  /* Loop to calculate output of convolution for output length number of times */
+  for (i = 0; i < (srcALen + srcBLen - 1); i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if(((i - j) < srcBLen) && (j < srcALen))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += (q15_t) pIn1[j] * (pIn2[i - j]);
+      }
+    }
+
+    /* Store the output in the destination buffer */
+    pDst[i] = (q7_t) __SSAT((sum >> 7u), 8u);
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0        */
+
+}
+
+/**   
+ * @} end of Conv group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c
new file mode 100644
index 000000000..bfbe0d34b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c
@@ -0,0 +1,718 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_correlate_f32.c   
+*   
+* Description:	 Correlation of floating-point sequences.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup Corr Correlation   
+ *   
+ * Correlation is a mathematical operation that is similar to convolution.   
+ * As with convolution, correlation uses two signals to produce a third signal.   
+ * The underlying algorithms in correlation and convolution are identical except that one of the inputs is flipped in convolution.   
+ * Correlation is commonly used to measure the similarity between two signals.   
+ * It has applications in pattern recognition, cryptanalysis, and searching.   
+ * The CMSIS library provides correlation functions for Q7, Q15, Q31 and floating-point data types.   
+ * Fast versions of the Q15 and Q31 functions are also provided.   
+ *   
+ * \par Algorithm   
+ * Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively.   
+ * The convolution of the two signals is denoted by   
+ * 
   
+ *                   c[n] = a[n] * b[n]   
+ * 
   
+ * In correlation, one of the signals is flipped in time   
+ * 
   
+ *                   c[n] = a[n] * b[-n]   
+ * 
   
+ *   
+ * \par   
+ * and this is mathematically defined as   
+ * \image html CorrelateEquation.gif   
+ * \par   
+ * The pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen.   
+ * The result c[n] is of length 2 * max(srcALen, srcBLen) - 1 and is defined over the interval n=0, 1, 2, ..., (2 * max(srcALen, srcBLen) - 2).   
+ * The output result is written to pDst and the calling function must allocate 2 * max(srcALen, srcBLen) - 1 words for the result.   
+ *   
+ * Note  
+ * \par 
+ * The pDst should be initialized to all zeros before being used. 
+ * 
+ * Fixed-Point Behavior   
+ * \par   
+ * Correlation requires summing up a large number of intermediate products.   
+ * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.   
+ * Refer to the function specific documentation below for further details of the particular algorithm used.   
+ */
+
+/**   
+ * @addtogroup Corr   
+ * @{   
+ */
+/**   
+ * @brief Correlation of floating-point sequences.   
+ * @param[in]  *pSrcA points to the first input sequence.   
+ * @param[in]  srcALen length of the first input sequence.   
+ * @param[in]  *pSrcB points to the second input sequence.   
+ * @param[in]  srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
+ * @return none.   
+ */
+
+void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t *pIn1;                               /* inputA pointer */
+  float32_t *pIn2;                               /* inputB pointer */
+  float32_t *pOut = pDst;                        /* output pointer */
+  float32_t *px;                                 /* Intermediate inputA pointer */
+  float32_t *py;                                 /* Intermediate inputB pointer */
+  float32_t *pSrc1;                              /* Intermediate pointers */
+  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulators */
+  float32_t x0, x1, x2, x3, c0;                  /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counters */
+  int32_t inc = 1;                               /* Destination address modifier */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,   
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding has to be done to srcB   
+     * to make their lengths equal.   
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+    //while(j > 0u)  
+    //{  
+    //  /* Zero is stored in the destination buffer */  
+    //  *pOut++ = 0.0f;  
+
+    //  /* Decrement the loop counter */  
+    //  j--;  
+    //}  
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally   
+   * divided into three parts according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first part of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second part of the algorithm, srcBLen number of multiplications are done.   
+   * In the third part of the algorithm, the multiplications decrease by one   
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.   
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]   
+   * sum = x[0] * y[srcBlen-2] + x[1] * y[srcBlen - 1]   
+   * ....   
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0.0f;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] */
+      sum += *px++ * *py++;
+      /* x[1] * y[srcBLen - 3] */
+      sum += *px++ * *py++;
+      /* x[2] * y[srcBLen - 2] */
+      sum += *px++ * *py++;
+      /* x[3] * y[srcBLen - 1] */
+      sum += *px++ * *py++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      /* x[0] * y[srcBLen - 1] */
+      sum += *px++ * *py++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = sum;
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0.0f;
+      acc1 = 0.0f;
+      acc2 = 0.0f;
+      acc3 = 0.0f;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[0] sample */
+        c0 = *(py++);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[0] * y[0] */
+        acc0 += x0 * c0;
+        /* acc1 +=  x[1] * y[0] */
+        acc1 += x1 * c0;
+        /* acc2 +=  x[2] * y[0] */
+        acc2 += x2 * c0;
+        /* acc3 +=  x[3] * y[0] */
+        acc3 += x3 * c0;
+
+        /* Read y[1] sample */
+        c0 = *(py++);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[1] * y[1] */
+        acc0 += x1 * c0;
+        /* acc1 +=  x[2] * y[1] */
+        acc1 += x2 * c0;
+        /* acc2 +=  x[3] * y[1] */
+        acc2 += x3 * c0;
+        /* acc3 +=  x[4] * y[1] */
+        acc3 += x0 * c0;
+
+        /* Read y[2] sample */
+        c0 = *(py++);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[2] */
+        acc0 += x2 * c0;
+        /* acc1 +=  x[3] * y[2] */
+        acc1 += x3 * c0;
+        /* acc2 +=  x[4] * y[2] */
+        acc2 += x0 * c0;
+        /* acc3 +=  x[5] * y[2] */
+        acc3 += x1 * c0;
+
+        /* Read y[3] sample */
+        c0 = *(py++);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[3] */
+        acc0 += x3 * c0;
+        /* acc1 +=  x[4] * y[3] */
+        acc1 += x0 * c0;
+        /* acc2 +=  x[5] * y[3] */
+        acc2 += x1 * c0;
+        /* acc3 +=  x[6] * y[3] */
+        acc3 += x2 * c0;
+
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[4] sample */
+        c0 = *(py++);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[4] */
+        acc0 += x0 * c0;
+        /* acc1 +=  x[5] * y[4] */
+        acc1 += x1 * c0;
+        /* acc2 +=  x[6] * y[4] */
+        acc2 += x2 * c0;
+        /* acc3 +=  x[7] * y[4] */
+        acc3 += x3 * c0;
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = acc0;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = acc1;
+      pOut += inc;
+
+      *pOut = acc2;
+      pOut += inc;
+
+      *pOut = acc3;
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pIn2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += *px++ * *py++;
+        sum += *px++ * *py++;
+        sum += *px++ * *py++;
+        sum += *px++ * *py++;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *px++ * *py++;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = sum;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *px++ * *py++;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = sum;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
+   * sum +=  x[srcALen-1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0.0f;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] */
+      sum += *px++ * *py++;
+      /* sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum += *px++ * *py++;
+      /* sum += x[srcALen - srcBLen + 2] * y[1] */
+      sum += *px++ * *py++;
+      /* sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum += *px++ * *py++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += *px++ * *py++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = sum;
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
+  float32_t *pIn2 = pSrcB + (srcBLen - 1u);      /* inputB pointer */
+  float32_t sum;                                 /* Accumulator */
+  uint32_t i = 0u, j;                            /* loop counters */
+  uint32_t inv = 0u;                             /* Reverse order flag */
+  uint32_t tot = 0u;                             /* Length */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and a varaible, inv is set to 1 */
+  /* If lengths are not equal then zero pad has to be done to  make the two   
+   * inputs of same length. But to improve the performance, we include zeroes   
+   * in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the   
+   * starting of the output buffer */
+  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the  
+   * ending of the output buffer */
+  /* Once the zero padding is done the remaining of the output is calcualted  
+   * using convolution but with the shorter signal time shifted. */
+
+  /* Calculate the length of the remaining sequence */
+  tot = ((srcALen + srcBLen) - 2u);
+
+  if(srcALen > srcBLen)
+  {
+    /* Calculating the number of zeros to be padded to the output */
+    j = srcALen - srcBLen;
+
+    /* Initialise the pointer after zero padding */
+    pDst += j;
+  }
+
+  else if(srcALen < srcBLen)
+  {
+    /* Initialization to inputB pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization to the end of inputA pointer */
+    pIn2 = pSrcA + (srcALen - 1u);
+
+    /* Initialisation of the pointer after zero padding */
+    pDst = pDst + tot;
+
+    /* Swapping the lengths */
+    j = srcALen;
+    srcALen = srcBLen;
+    srcBLen = j;
+
+    /* Setting the reverse flag */
+    inv = 1;
+
+  }
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0u; i <= tot; i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0.0f;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0u; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += pIn1[j] * pIn2[-((int32_t) i - j)];
+      }
+    }
+    /* Store the output in the destination buffer */
+    if(inv == 1)
+      *pDst-- = sum;
+    else
+      *pDst++ = sum;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of Corr group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c
new file mode 100644
index 000000000..f93d85a5b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c
@@ -0,0 +1,622 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_correlate_fast_q15.c   
+*   
+* Description:	Fast Q15 Correlation.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Corr   
+ * @{   
+ */
+
+/**   
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * This fast version uses a 32-bit accumulator with 2.30 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * There is no saturation on intermediate additions.   
+ * Thus, if the accumulator overflows it wraps around and distorts the result.   
+ * The input signals should be scaled down to avoid intermediate overflows.   
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a   
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.   
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.   
+ *   
+ * \par   
+ * See arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.   
+ */
+
+void arm_correlate_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst)
+{
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1;                                  /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+  q31_t *pb;                                     /* 32 bit pointer for inputB buffer */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,   
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB   
+     * to make their lengths equal.   
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally   
+   * divided into three parts according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first part of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second part of the algorithm, srcBLen number of multiplications are done.   
+   * In the third part of the algorithm, the multiplications decrease by one   
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.   
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]   
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
+   * ....   
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first loop starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+      /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */
+      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum = __SMLAD(*px++, *py++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (sum >> 15);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* Initialize inputB pointer of type q31 */
+  pb = (q31_t *) (py);
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1] samples */
+      x0 = *(q31_t *) (px++);
+      /* read x[1], x[2] samples */
+      x1 = *(q31_t *) (px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the first two inputB samples using SIMD:   
+         * y[0] and y[1] */
+        c0 = *(pb++);
+
+        /* acc0 +=  x[0] * y[0] + x[1] * y[1] */
+        acc0 = __SMLAD(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[0] + x[2] * y[1] */
+        acc1 = __SMLAD(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *(q31_t *) (px++);
+
+        /* Read x[3], x[4] */
+        x3 = *(q31_t *) (px++);
+
+        /* acc2 +=  x[2] * y[0] + x[3] * y[1] */
+        acc2 = __SMLAD(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[0] + x[4] * y[1] */
+        acc3 = __SMLAD(x3, c0, acc3);
+
+        /* Read y[2] and y[3] */
+        c0 = *(pb++);
+
+        /* acc0 +=  x[2] * y[2] + x[3] * y[3] */
+        acc0 = __SMLAD(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[2] + x[4] * y[3] */
+        acc1 = __SMLAD(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = *(q31_t *) (px++);
+
+        /* Read x[5], x[6] */
+        x1 = *(q31_t *) (px++);
+
+        /* acc2 +=  x[4] * y[2] + x[5] * y[3] */
+        acc2 = __SMLAD(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[2] + x[6] * y[3] */
+        acc3 = __SMLAD(x1, c0, acc3);
+
+      } while(--k);
+
+      /* For the next MAC operations, SIMD is not used   
+       * So, the 16 bit pointer if inputB, py is updated */
+      py = (q15_t *) (pb);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[4] */
+        c0 = *py;
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+        x3 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLADX(x1, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[4], y[5] */
+        c0 = *(pb);
+
+        /* Read x[7], x[8] */
+        x3 = *(q31_t *) px++;
+
+        /* Read x[9] */
+        x2 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLAD(x3, c0, acc2);
+        acc3 = __SMLAD(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[4], y[5] */
+        c0 = *pb++;
+
+        /* Read x[7], x[8] */
+        x3 = *(q31_t *) px++;
+
+        /* Read x[9] */
+        x2 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLAD(x3, c0, acc2);
+        acc3 = __SMLAD(x2, c0, acc3);
+
+        /* Read y[6] */
+#ifdef  ARM_MATH_BIG_ENDIAN
+        c0 = (*pb);
+        c0 = c0 & 0xFFFF0000;
+
+#else
+        c0 = (q15_t) (*pb);
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+        x3 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x1, c0, acc0);
+        acc1 = __SMLAD(x2, c0, acc1);
+        acc2 = __SMLADX(x2, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (acc0 >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q15_t) (acc1 >> 15);
+      pOut += inc;
+
+      *pOut = (q15_t) (acc2 >> 15);
+      pOut += inc;
+
+      *pOut = (q15_t) (acc3 >> 15);
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+      pb = (q31_t *) (py);
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (sum >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (sum >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
+   * sum +=  x[srcALen-1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+      /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLAD(*px++, *py++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (sum >> 15);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+}
+
+/**   
+ * @} end of Corr group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c
new file mode 100644
index 000000000..62d35dd25
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c
@@ -0,0 +1,599 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_correlate_fast_q31.c   
+*   
+* Description:	Fast Q31 Correlation.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Corr   
+ * @{   
+ */
+
+/**   
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.   
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.   
+ * These intermediate results are accumulated in a 32-bit register in 2.30 format.   
+ * Finally, the accumulator is saturated and converted to a 1.31 result.   
+ *   
+ * \par   
+ * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.   
+ * In order to avoid overflows completely the input signals must be scaled down.   
+ * The input signals should be scaled down to avoid intermediate overflows.   
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a   
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.   
+ *   
+ * \par   
+ * See arm_correlate_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.   
+ */
+
+void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst)
+{
+  q31_t *pIn1;                                   /* inputA pointer               */
+  q31_t *pIn2;                                   /* inputB pointer               */
+  q31_t *pOut = pDst;                            /* output pointer               */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1;                                  /* Intermediate pointers        */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB   
+     * to make their lengths equal.   
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally   
+   * divided into three parts according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first part of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second part of the algorithm, srcBLen number of multiplications are done.   
+   * In the third part of the algorithm, the multiplications decrease by one   
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.   
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]   
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
+   * ....   
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* x[1] * y[srcBLen - 3] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* x[2] * y[srcBLen - 2] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* x[3] * y[srcBLen - 1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = sum << 1;
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[0] sample */
+        c0 = *(py++);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[0] * y[0] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc1 +=  x[1] * y[0] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc2 +=  x[2] * y[0] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc3 +=  x[3] * y[0] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+        /* Read y[1] sample */
+        c0 = *(py++);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[1] * y[1] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc1 +=  x[2] * y[1] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc2 +=  x[3] * y[1] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc3 +=  x[4] * y[1] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+        /* Read y[2] sample */
+        c0 = *(py++);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[2] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc1 +=  x[3] * y[2] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc2 +=  x[4] * y[2] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc3 +=  x[5] * y[2] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+        /* Read y[3] sample */
+        c0 = *(py++);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[3] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc1 +=  x[4] * y[3] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc2 +=  x[5] * y[3] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc3 +=  x[6] * y[3] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[4] sample */
+        c0 = *(py++);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[4] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc1 +=  x[5] * y[4] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc2 +=  x[6] * y[4] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc3 +=  x[7] * y[4] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q31_t) (acc0 << 1);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q31_t) (acc1 << 1);
+      pOut += inc;
+
+      *pOut = (q31_t) (acc2 << 1);
+      pOut += inc;
+
+      *pOut = (q31_t) (acc3 << 1);
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pIn2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = sum << 1;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = sum << 1;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
+   * sum +=  x[srcALen-1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = ((pIn1 + srcALen) - srcBLen) + 1u;
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* sum += x[srcALen - srcBLen + 2] * y[1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = sum << 1;
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+}
+
+/**   
+ * @} end of Corr group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c
new file mode 100644
index 000000000..424cc3185
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c
@@ -0,0 +1,714 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_correlate_q15.c   
+*   
+* Description:	Correlation of Q15 sequences. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Corr   
+ * @{   
+ */
+
+/**   
+ * @brief Correlation of Q15 sequences. 
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * This approach provides 33 guard bits and there is no risk of overflow.   
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.   
+ *   
+ * \par   
+ * Refer to arm_correlate_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1;                                  /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+  q31_t *pb;                                     /* 32 bit pointer for inputB buffer */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,   
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB   
+     * to make their lengths equal.   
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally   
+   * divided into three parts according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first part of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second part of the algorithm, srcBLen number of multiplications are done.   
+   * In the third part of the algorithm, the multiplications decrease by one   
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.   
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]   
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
+   * ....   
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first loop starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+      /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */
+      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum = __SMLALD(*px++, *py++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (__SSAT((sum >> 15), 16));
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* Initialize inputB pointer of type q31 */
+  pb = (q31_t *) (py);
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1] samples */
+      x0 = *(q31_t *) (px++);
+      /* read x[1], x[2] samples */
+      x1 = *(q31_t *) (px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the first two inputB samples using SIMD:   
+         * y[0] and y[1] */
+        c0 = *(pb++);
+
+        /* acc0 +=  x[0] * y[0] + x[1] * y[1] */
+        acc0 = __SMLALD(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[0] + x[2] * y[1] */
+        acc1 = __SMLALD(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *(q31_t *) (px++);
+
+        /* Read x[3], x[4] */
+        x3 = *(q31_t *) (px++);
+
+        /* acc2 +=  x[2] * y[0] + x[3] * y[1] */
+        acc2 = __SMLALD(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[0] + x[4] * y[1] */
+        acc3 = __SMLALD(x3, c0, acc3);
+
+        /* Read y[2] and y[3] */
+        c0 = *(pb++);
+
+        /* acc0 +=  x[2] * y[2] + x[3] * y[3] */
+        acc0 = __SMLALD(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[2] + x[4] * y[3] */
+        acc1 = __SMLALD(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = *(q31_t *) (px++);
+
+        /* Read x[5], x[6] */
+        x1 = *(q31_t *) (px++);
+
+        /* acc2 +=  x[4] * y[2] + x[5] * y[3] */
+        acc2 = __SMLALD(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[2] + x[6] * y[3] */
+        acc3 = __SMLALD(x1, c0, acc3);
+
+      } while(--k);
+
+      /* For the next MAC operations, SIMD is not used   
+       * So, the 16 bit pointer if inputB, py is updated */
+      py = (q15_t *) (pb);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[4] */
+        c0 = *py;
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+        /* Read x[7] */
+        x3 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALDX(x1, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[4], y[5] */
+        c0 = *(pb);
+
+        /* Read x[7], x[8] */
+        x3 = *(q31_t *) px++;
+
+        /* Read x[9] */
+        x2 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALD(x3, c0, acc2);
+        acc3 = __SMLALD(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[4], y[5] */
+        c0 = *pb++;
+
+        /* Read x[7], x[8] */
+        x3 = *(q31_t *) px++;
+
+        /* Read x[9] */
+        x2 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALD(x3, c0, acc2);
+        acc3 = __SMLALD(x2, c0, acc3);
+
+        /* Read y[6] */
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = (*pb);
+        c0 = c0 & 0xFFFF0000;
+
+#else
+
+        c0 = (q15_t) (*pb);
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+        /* Read x[10] */
+        x3 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x1, c0, acc0);
+        acc1 = __SMLALD(x2, c0, acc1);
+        acc2 = __SMLALDX(x2, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (__SSAT(acc0 >> 15, 16));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q15_t) (__SSAT(acc1 >> 15, 16));
+      pOut += inc;
+
+      *pOut = (q15_t) (__SSAT(acc2 >> 15, 16));
+      pOut += inc;
+
+      *pOut = (q15_t) (__SSAT(acc3 >> 15, 16));
+      pOut += inc;
+
+      /* Increment the count by 4 as 4 output values are computed */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+      pb = (q31_t *) (py);
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q63_t) * px++ * *py++);
+        sum += ((q63_t) * px++ * *py++);
+        sum += ((q63_t) * px++ * *py++);
+        sum += ((q63_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q63_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (__SSAT(sum >> 15, 16));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment count by 1, as one output value is computed */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q63_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (__SSAT(sum >> 15, 16));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
+   * sum +=  x[srcALen-1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+      /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLALD(*px++, *py++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (__SSAT((sum >> 15), 16));
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q15_t *pIn1 = pSrcA;                           /* inputA pointer               */
+  q15_t *pIn2 = pSrcB + (srcBLen - 1u);          /* inputB pointer               */
+  q63_t sum;                                     /* Accumulators                  */
+  uint32_t i = 0u, j;                            /* loop counters */
+  uint32_t inv = 0u;                             /* Reverse order flag */
+  uint32_t tot = 0u;                             /* Length */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and a varaible, inv is set to 1 */
+  /* If lengths are not equal then zero pad has to be done to  make the two   
+   * inputs of same length. But to improve the performance, we include zeroes   
+   * in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the   
+   * starting of the output buffer */
+  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the  
+   * ending of the output buffer */
+  /* Once the zero padding is done the remaining of the output is calcualted  
+   * using convolution but with the shorter signal time shifted. */
+
+  /* Calculate the length of the remaining sequence */
+  tot = ((srcALen + srcBLen) - 2u);
+
+  if(srcALen > srcBLen)
+  {
+    /* Calculating the number of zeros to be padded to the output */
+    j = srcALen - srcBLen;
+
+    /* Initialise the pointer after zero padding */
+    pDst += j;
+  }
+
+  else if(srcALen < srcBLen)
+  {
+    /* Initialization to inputB pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization to the end of inputA pointer */
+    pIn2 = pSrcA + (srcALen - 1u);
+
+    /* Initialisation of the pointer after zero padding */
+    pDst = pDst + tot;
+
+    /* Swapping the lengths */
+    j = srcALen;
+    srcALen = srcBLen;
+    srcBLen = j;
+
+    /* Setting the reverse flag */
+    inv = 1;
+
+  }
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0u; i <= tot; i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0u; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+      }
+    }
+    /* Store the output in the destination buffer */
+    if(inv == 1)
+      *pDst-- = (q15_t) __SSAT((sum >> 15u), 16u);
+    else
+      *pDst++ = (q15_t) __SSAT((sum >> 15u), 16u);
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of Corr group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c
new file mode 100644
index 000000000..df1a457fe
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c
@@ -0,0 +1,683 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_correlate_q31.c   
+*   
+* Description:	Correlation of Q31 sequences. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Corr   
+ * @{   
+ */
+
+/**   
+ * @brief Correlation of Q31 sequences.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * There is no saturation on intermediate additions.   
+ * Thus, if the accumulator overflows it wraps around and distorts the result.   
+ * The input signals should be scaled down to avoid intermediate overflows.   
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a   
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.   
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.   
+ *   
+ * \par   
+ * See arm_correlate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn1;                                   /* inputA pointer               */
+  q31_t *pIn2;                                   /* inputB pointer               */
+  q31_t *pOut = pDst;                            /* output pointer               */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1;                                  /* Intermediate pointers        */
+  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,   
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB   
+     * to make their lengths equal.   
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally   
+   * divided into three parts according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first part of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second part of the algorithm, srcBLen number of multiplications are done.   
+   * In the third part of the algorithm, the multiplications decrease by one   
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.   
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]   
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
+   * ....   
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] */
+      sum += (q63_t) * px++ * (*py++);
+      /* x[1] * y[srcBLen - 3] */
+      sum += (q63_t) * px++ * (*py++);
+      /* x[2] * y[srcBLen - 2] */
+      sum += (q63_t) * px++ * (*py++);
+      /* x[3] * y[srcBLen - 1] */
+      sum += (q63_t) * px++ * (*py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum += (q63_t) * px++ * (*py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q31_t) (sum >> 31);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[0] sample */
+        c0 = *(py++);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[0] * y[0] */
+        acc0 += ((q63_t) x0 * c0);
+        /* acc1 +=  x[1] * y[0] */
+        acc1 += ((q63_t) x1 * c0);
+        /* acc2 +=  x[2] * y[0] */
+        acc2 += ((q63_t) x2 * c0);
+        /* acc3 +=  x[3] * y[0] */
+        acc3 += ((q63_t) x3 * c0);
+
+        /* Read y[1] sample */
+        c0 = *(py++);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[1] * y[1] */
+        acc0 += ((q63_t) x1 * c0);
+        /* acc1 +=  x[2] * y[1] */
+        acc1 += ((q63_t) x2 * c0);
+        /* acc2 +=  x[3] * y[1] */
+        acc2 += ((q63_t) x3 * c0);
+        /* acc3 +=  x[4] * y[1] */
+        acc3 += ((q63_t) x0 * c0);
+        /* Read y[2] sample */
+        c0 = *(py++);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[2] */
+        acc0 += ((q63_t) x2 * c0);
+        /* acc1 +=  x[3] * y[2] */
+        acc1 += ((q63_t) x3 * c0);
+        /* acc2 +=  x[4] * y[2] */
+        acc2 += ((q63_t) x0 * c0);
+        /* acc3 +=  x[5] * y[2] */
+        acc3 += ((q63_t) x1 * c0);
+
+        /* Read y[3] sample */
+        c0 = *(py++);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[3] */
+        acc0 += ((q63_t) x3 * c0);
+        /* acc1 +=  x[4] * y[3] */
+        acc1 += ((q63_t) x0 * c0);
+        /* acc2 +=  x[5] * y[3] */
+        acc2 += ((q63_t) x1 * c0);
+        /* acc3 +=  x[6] * y[3] */
+        acc3 += ((q63_t) x2 * c0);
+
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[4] sample */
+        c0 = *(py++);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[4] */
+        acc0 += ((q63_t) x0 * c0);
+        /* acc1 +=  x[5] * y[4] */
+        acc1 += ((q63_t) x1 * c0);
+        /* acc2 +=  x[6] * y[4] */
+        acc2 += ((q63_t) x2 * c0);
+        /* acc3 +=  x[7] * y[4] */
+        acc3 += ((q63_t) x3 * c0);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q31_t) (acc0 >> 31);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q31_t) (acc1 >> 31);
+      pOut += inc;
+
+      *pOut = (q31_t) (acc2 >> 31);
+      pOut += inc;
+
+      *pOut = (q31_t) (acc3 >> 31);
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pIn2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += (q63_t) * px++ * (*py++);
+        sum += (q63_t) * px++ * (*py++);
+        sum += (q63_t) * px++ * (*py++);
+        sum += (q63_t) * px++ * (*py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q31_t) (sum >> 31);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q31_t) (sum >> 31);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
+   * sum +=  x[srcALen-1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] */
+      sum += (q63_t) * px++ * (*py++);
+      /* sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum += (q63_t) * px++ * (*py++);
+      /* sum += x[srcALen - srcBLen + 2] * y[1] */
+      sum += (q63_t) * px++ * (*py++);
+      /* sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum += (q63_t) * px++ * (*py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += (q63_t) * px++ * (*py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q31_t) (sum >> 31);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t *pIn1 = pSrcA;                           /* inputA pointer               */
+  q31_t *pIn2 = pSrcB + (srcBLen - 1u);          /* inputB pointer               */
+  q63_t sum;                                     /* Accumulators                  */
+  uint32_t i = 0u, j;                            /* loop counters */
+  uint32_t inv = 0u;                             /* Reverse order flag */
+  uint32_t tot = 0u;                             /* Length */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and a varaible, inv is set to 1 */
+  /* If lengths are not equal then zero pad has to be done to  make the two   
+   * inputs of same length. But to improve the performance, we include zeroes   
+   * in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the   
+   * starting of the output buffer */
+  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the  
+   * ending of the output buffer */
+  /* Once the zero padding is done the remaining of the output is calcualted  
+   * using convolution but with the shorter signal time shifted. */
+
+  /* Calculate the length of the remaining sequence */
+  tot = ((srcALen + srcBLen) - 2u);
+
+  if(srcALen > srcBLen)
+  {
+    /* Calculating the number of zeros to be padded to the output */
+    j = srcALen - srcBLen;
+
+    /* Initialise the pointer after zero padding */
+    pDst += j;
+  }
+
+  else if(srcALen < srcBLen)
+  {
+    /* Initialization to inputB pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization to the end of inputA pointer */
+    pIn2 = pSrcA + (srcALen - 1u);
+
+    /* Initialisation of the pointer after zero padding */
+    pDst = pDst + tot;
+
+    /* Swapping the lengths */
+    j = srcALen;
+    srcALen = srcBLen;
+    srcBLen = j;
+
+    /* Setting the reverse flag */
+    inv = 1;
+
+  }
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0u; i <= tot; i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0u; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += ((q63_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+      }
+    }
+    /* Store the output in the destination buffer */
+    if(inv == 1)
+      *pDst-- = (q31_t) (sum >> 31u);
+    else
+      *pDst++ = (q31_t) (sum >> 31u);
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of Corr group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c
new file mode 100644
index 000000000..2496e2c36
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c
@@ -0,0 +1,780 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_correlate_q7.c   
+*   
+* Description:	Correlation of Q7 sequences. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Corr   
+ * @{   
+ */
+
+/**   
+ * @brief Correlation of Q7 sequences.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 32-bit internal accumulator.   
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.   
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.   
+ * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.   
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format.   
+ */
+
+void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t *pIn1;                                    /* inputA pointer               */
+  q7_t *pIn2;                                    /* inputB pointer               */
+  q7_t *pOut = pDst;                             /* output pointer               */
+  q7_t *px;                                      /* Intermediate inputA pointer  */
+  q7_t *py;                                      /* Intermediate inputB pointer  */
+  q7_t *pSrc1;                                   /* Intermediate pointers        */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q31_t input1, input2;                          /* temporary variables */
+  q15_t in1, in2;                                /* temporary variables */
+  q7_t x0, x1, x2, x3, c0, c1;                   /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,   
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB   
+     * to make their lengths equal.   
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally   
+   * divided into three parts according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first part of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second part of the algorithm, srcBLen number of multiplications are done.   
+   * In the third part of the algorithm, the multiplications decrease by one   
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.   
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]   
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
+   * ....   
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] , x[1] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* y[srcBLen - 4] , y[srcBLen - 3] */
+      in1 = (q15_t) * py++;
+      in2 = (q15_t) * py++;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* x[0] * y[srcBLen - 4] */
+      /* x[1] * y[srcBLen - 3] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* x[2] , x[3] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* y[srcBLen - 2] , y[srcBLen - 1] */
+      in1 = (q15_t) * py++;
+      in2 = (q15_t) * py++;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* x[2] * y[srcBLen - 2] */
+      /* x[3] * y[srcBLen - 1] */
+      sum = __SMLAD(input1, input2, sum);
+
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum += (q31_t) ((q15_t) * px++ * *py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *px++;
+      x1 = *px++;
+      x2 = *px++;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[0] sample */
+        c0 = *py++;
+        /* Read y[1] sample */
+        c1 = *py++;
+
+        /* Read x[3] sample */
+        x3 = *px++;
+
+        /* x[0] and x[1] are packed */
+        in1 = (q15_t) x0;
+        in2 = (q15_t) x1;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* y[0] and y[1] are packed */
+        in1 = (q15_t) c0;
+        in2 = (q15_t) c1;
+
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc0 += x[0] * y[0] + x[1] * y[1]  */
+        acc0 = __SMLAD(input1, input2, acc0);
+
+        /* x[1] and x[2] are packed */
+        in1 = (q15_t) x1;
+        in2 = (q15_t) x2;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc1 += x[1] * y[0] + x[2] * y[1] */
+        acc1 = __SMLAD(input1, input2, acc1);
+
+        /* x[2] and x[3] are packed */
+        in1 = (q15_t) x2;
+        in2 = (q15_t) x3;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc2 += x[2] * y[0] + x[3] * y[1]  */
+        acc2 = __SMLAD(input1, input2, acc2);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* x[3] and x[4] are packed */
+        in1 = (q15_t) x3;
+        in2 = (q15_t) x0;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc3 += x[3] * y[0] + x[4] * y[1]  */
+        acc3 = __SMLAD(input1, input2, acc3);
+
+        /* Read y[2] sample */
+        c0 = *py++;
+        /* Read y[3] sample */
+        c1 = *py++;
+
+        /* Read x[5] sample */
+        x1 = *px++;
+
+        /* x[2] and x[3] are packed */
+        in1 = (q15_t) x2;
+        in2 = (q15_t) x3;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* y[2] and y[3] are packed */
+        in1 = (q15_t) c0;
+        in2 = (q15_t) c1;
+
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc0 += x[2] * y[2] + x[3] * y[3]  */
+        acc0 = __SMLAD(input1, input2, acc0);
+
+        /* x[3] and x[4] are packed */
+        in1 = (q15_t) x3;
+        in2 = (q15_t) x0;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc1 += x[3] * y[2] + x[4] * y[3]  */
+        acc1 = __SMLAD(input1, input2, acc1);
+
+        /* x[4] and x[5] are packed */
+        in1 = (q15_t) x0;
+        in2 = (q15_t) x1;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc2 += x[4] * y[2] + x[5] * y[3]  */
+        acc2 = __SMLAD(input1, input2, acc2);
+
+        /* Read x[6] sample */
+        x2 = *px++;
+
+        /* x[5] and x[6] are packed */
+        in1 = (q15_t) x1;
+        in2 = (q15_t) x2;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc3 += x[5] * y[2] + x[6] * y[3]  */
+        acc3 = __SMLAD(input1, input2, acc3);
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[4] sample */
+        c0 = *py++;
+
+        /* Read x[7] sample */
+        x3 = *px++;
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[4] */
+        acc0 += ((q15_t) x0 * c0);
+        /* acc1 +=  x[5] * y[4] */
+        acc1 += ((q15_t) x1 * c0);
+        /* acc2 +=  x[6] * y[4] */
+        acc2 += ((q15_t) x2 * c0);
+        /* acc3 +=  x[7] * y[4] */
+        acc3 += ((q15_t) x3 * c0);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q7_t) (__SSAT(acc0 >> 7, 8));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q7_t) (__SSAT(acc1 >> 7, 8));
+      pOut += inc;
+
+      *pOut = (q7_t) (__SSAT(acc2 >> 7, 8));
+      pOut += inc;
+
+      *pOut = (q7_t) (__SSAT(acc3 >> 7, 8));
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pIn2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Reading two inputs of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Reading two inputs of SrcB buffer and packing */
+        in1 = (q15_t) * py++;
+        in2 = (q15_t) * py++;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Reading two inputs of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Reading two inputs of SrcB buffer and packing */
+        in1 = (q15_t) * py++;
+        in2 = (q15_t) * py++;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q15_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q15_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
+   * sum +=  x[srcALen-1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[srcALen - srcBLen + 1] , x[srcALen - srcBLen + 2]  */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* y[0] , y[1] */
+      in1 = (q15_t) * py++;
+      in2 = (q15_t) * py++;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* sum += x[srcALen - srcBLen + 1] * y[0] */
+      /* sum += x[srcALen - srcBLen + 2] * y[1] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* x[srcALen - srcBLen + 3] , x[srcALen - srcBLen + 4] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* y[2] , y[3] */
+      in1 = (q15_t) * py++;
+      in2 = (q15_t) * py++;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* sum += x[srcALen - srcBLen + 3] * y[2] */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += ((q15_t) * px++ * *py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q7_t *pIn1 = pSrcA;                            /* inputA pointer */
+  q7_t *pIn2 = pSrcB + (srcBLen - 1u);           /* inputB pointer */
+  q31_t sum;                                     /* Accumulator */
+  uint32_t i = 0u, j;                            /* loop counters */
+  uint32_t inv = 0u;                             /* Reverse order flag */
+  uint32_t tot = 0u;                             /* Length */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and a varaible, inv is set to 1 */
+  /* If lengths are not equal then zero pad has to be done to  make the two   
+   * inputs of same length. But to improve the performance, we include zeroes   
+   * in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the   
+   * starting of the output buffer */
+  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the  
+   * ending of the output buffer */
+  /* Once the zero padding is done the remaining of the output is calcualted  
+   * using convolution but with the shorter signal time shifted. */
+
+  /* Calculate the length of the remaining sequence */
+  tot = ((srcALen + srcBLen) - 2u);
+
+  if(srcALen > srcBLen)
+  {
+    /* Calculating the number of zeros to be padded to the output */
+    j = srcALen - srcBLen;
+
+    /* Initialise the pointer after zero padding */
+    pDst += j;
+  }
+
+  else if(srcALen < srcBLen)
+  {
+    /* Initialization to inputB pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization to the end of inputA pointer */
+    pIn2 = pSrcA + (srcALen - 1u);
+
+    /* Initialisation of the pointer after zero padding */
+    pDst = pDst + tot;
+
+    /* Swapping the lengths */
+    j = srcALen;
+    srcALen = srcBLen;
+    srcBLen = j;
+
+    /* Setting the reverse flag */
+    inv = 1;
+
+  }
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0u; i <= tot; i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0u; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += ((q15_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+      }
+    }
+    /* Store the output in the destination buffer */
+    if(inv == 1)
+      *pDst-- = (q7_t) __SSAT((sum >> 7u), 8u);
+    else
+      *pDst++ = (q7_t) __SSAT((sum >> 7u), 8u);
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of Corr group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c
new file mode 100644
index 000000000..0ee7d160f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c
@@ -0,0 +1,370 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_decimate_f32.c   
+*   
+* Description:	FIR decimation for floating-point sequences.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup FIR_decimate Finite Impulse Response (FIR) Decimator   
+ *   
+ * These functions combine an FIR filter together with a decimator.   
+ * They are used in multirate systems for reducing the sample rate of a signal without introducing aliasing distortion.   
+ * Conceptually, the functions are equivalent to the block diagram below:   
+ * \image html FIRDecimator.gif "Components included in the FIR Decimator functions"   
+ * When decimating by a factor of M, the signal should be prefiltered by a lowpass filter with a normalized   
+ * cutoff frequency of 1/M in order to prevent aliasing distortion.   
+ * The user of the function is responsible for providing the filter coefficients.   
+ *   
+ * The FIR decimator functions provided in the CMSIS DSP Library combine the FIR filter and the decimator in an efficient manner.   
+ * Instead of calculating all of the FIR filter outputs and discarding M-1 out of every M, only the   
+ * samples output by the decimator are computed.   
+ * The functions operate on blocks of input and output data.   
+ * pSrc points to an array of blockSize input values and   
+ * pDst points to an array of blockSize/M output values.   
+ * In order to have an integer number of output samples blockSize   
+ * must always be a multiple of the decimation factor M.   
+ *   
+ * The library provides separate functions for Q15, Q31 and floating-point data types.   
+ *   
+ * \par Algorithm:   
+ * The FIR portion of the algorithm uses the standard form filter:   
+ * 
   
+ *    y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]   
+ * 
   
+ * where, b[n] are the filter coefficients.   
+ * \par  
+ * The pCoeffs points to a coefficient array of size numTaps.   
+ * Coefficients are stored in time reversed order.   
+ * \par   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * \par   
+ * pState points to a state array of size numTaps + blockSize - 1.   
+ * Samples in the state buffer are stored in the order:   
+ * \par   
+ * 
   
+ *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}   
+ * 
   
+ * The state variables are updated after each block of data is processed, the coefficients are untouched.   
+ *   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient arrays may be shared among several instances while state variable array should be allocated separately.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ * - Checks to make sure that the size of the input is a multiple of the decimation factor.   
+ *   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * The code below statically initializes each of the 3 different data type filter instance structures   
+ * 
   
+ *arm_fir_decimate_instance_f32 S = {M, numTaps, pCoeffs, pState};   
+ *arm_fir_decimate_instance_q31 S = {M, numTaps, pCoeffs, pState};   
+ *arm_fir_decimate_instance_q15 S = {M, numTaps, pCoeffs, pState};   
+ * 
   
+ * where M is the decimation factor; numTaps is the number of filter coefficients in the filter;   
+ * pCoeffs is the address of the coefficient buffer;   
+ * pState is the address of the state buffer.   
+ * Be sure to set the values in the state buffer to zeros when doing static initialization.   
+ *   
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the FIR decimate filter functions.   
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+/**   
+ * @addtogroup FIR_decimate   
+ * @{   
+ */
+
+  /**   
+   * @brief Processing function for the floating-point FIR decimator.   
+   * @param[in] *S        points to an instance of the floating-point FIR decimator structure.   
+   * @param[in] *pSrc     points to the block of input data.   
+   * @param[out] *pDst    points to the block of output data.   
+   * @param[in] blockSize number of input samples to process per call.   
+   * @return none.   
+   */
+
+void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+  float32_t sum0;                                /* Accumulator */
+  float32_t x0, c0;                              /* Temporary variables to hold state and coefficient values */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0.0f;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-1] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-2] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor   
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = sum0;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0.0f;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor          
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = sum0;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last numTaps - 1 samples to the start of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy numTaps number of values */
+  i = (numTaps - 1u);
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0        */
+
+}
+
+/**   
+ * @} end of FIR_decimate group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c
new file mode 100644
index 000000000..ae1ddf8b9
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c
@@ -0,0 +1,199 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_decimate_fast_q15.c   
+*   
+* Description:	Fast Q15 FIR Decimator.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_decimate   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.   
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return none   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * This fast version uses a 32-bit accumulator with 2.30 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.   
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (log2 is read as log to the base 2).   
+ * The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.   
+ *   
+ * \par   
+ * Refer to the function arm_fir_decimate_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.   
+ * Both the slow and the fast versions use the same instance structure.   
+ * Use the function arm_fir_decimate_init_q15() to initialize the filter structure.   
+ */
+
+void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  q31_t sum0;                                    /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /*Set sum to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+      x0 = *__SIMD32(px)++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLAD(x0, c0, sum0);
+
+      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+      x0 = *__SIMD32(px)++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLAD(x0, c0, sum0);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLAD(x0, c0, sum0);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor   
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* Store filter output , smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) ((sum0 >> 15));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+}
+
+/**   
+ * @} end of FIR_decimate group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c
new file mode 100644
index 000000000..86833d829
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c
@@ -0,0 +1,220 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_decimate_fast_q31.c   
+*   
+* Description:	Fast Q31 FIR Decimator.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_decimate   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.   
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return none   
+ *   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.   
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.   
+ * These intermediate results are added to a 2.30 accumulator.   
+ * Finally, the accumulator is saturated and converted to a 1.31 result.   
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.   
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).   
+ *   
+ * \par   
+ * Refer to the function arm_fir_decimate_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.   
+ * Both the slow and the fast versions use the same instance structure.   
+ * Use the function arm_fir_decimate_init_q31() to initialize the filter structure.   
+ */
+
+void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  q31_t *px;                                     /* Temporary pointers for state buffer */
+  q31_t *pb;                                     /* Temporary pointers for coefficient buffer */
+  q63_t sum0;                                    /* Accumulator */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-1] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) x0 * c0) + (sum0 << 32)) >> 32);
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-2] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) x0 * c0) + (sum0 << 32)) >> 32);
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) x0 * c0) + (sum0 << 32)) >> 32);
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) x0 * c0) + (sum0 << 32)) >> 32);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) x0 * c0) + (sum0 << 32)) >> 32);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor   
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = (q31_t) (sum0 << 1);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+}
+
+/**   
+ * @} end of FIR_decimate group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c
new file mode 100644
index 000000000..be970ebc1
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c
@@ -0,0 +1,109 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_decimate_init_f32.c   
+*   
+* Description:  Floating-point FIR Decimator initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_decimate   
+ * @{   
+ */
+
+/**   
+ * @brief  Initialization function for the floating-point FIR decimator.   
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.   
+ * @param[in] numTaps  number of coefficients in the filter.   
+ * @param[in] M  decimation factor.   
+ * @param[in] *pCoeffs points to the filter coefficients.   
+ * @param[in] *pState points to the state buffer.   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if   
+ * blockSize is not a multiple of M.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_f32().   
+ * M is the decimation factor.   
+ */
+
+arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The size of the input block must be a multiple of the decimation factor */
+  if((blockSize % M) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+    /* Assign filter taps */
+    S->numTaps = numTaps;
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Clear state buffer and size is always (blockSize + numTaps - 1) */
+    memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    /* Assign Decimation Factor */
+    S->M = M;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+/**   
+ * @} end of FIR_decimate group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c
new file mode 100644
index 000000000..c9f1f3cb7
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c
@@ -0,0 +1,111 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_decimate_init_q15.c   
+*   
+* Description:  Initialization function for the Q15 FIR Decimator.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_decimate   
+ * @{   
+ */
+
+/**   
+ * @brief  Initialization function for the Q15 FIR decimator.   
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.   
+ * @param[in] numTaps  number of coefficients in the filter.   
+ * @param[in] M  decimation factor.   
+ * @param[in] *pCoeffs points to the filter coefficients.   
+ * @param[in] *pState points to the state buffer.   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if   
+ * blockSize is not a multiple of M.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples   
+ * to the call arm_fir_decimate_q15().   
+ * M is the decimation factor.   
+ */
+
+arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize)
+{
+
+  arm_status status;
+
+  /* The size of the input block must be a multiple of the decimation factor */
+  if((blockSize % M) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+    /* Assign filter taps */
+    S->numTaps = numTaps;
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Clear the state buffer.  The size of buffer is always (blockSize + numTaps - 1) */
+    memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    /* Assign Decimation factor */
+    S->M = M;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+/**   
+ * @} end of FIR_decimate group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c
new file mode 100644
index 000000000..7fdb6935f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c
@@ -0,0 +1,109 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_decimate_init_q31.c   
+*   
+* Description:  Initialization function for Q31 FIR Decimation filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_decimate   
+ * @{   
+ */
+
+/**   
+ * @brief  Initialization function for the Q31 FIR decimator.   
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.   
+ * @param[in] numTaps  number of coefficients in the filter.   
+ * @param[in] M  decimation factor.   
+ * @param[in] *pCoeffs points to the filter coefficients.   
+ * @param[in] *pState points to the state buffer.   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if   
+ * blockSize is not a multiple of M.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_q31().   
+ * M is the decimation factor.   
+ */
+
+arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The size of the input block must be a multiple of the decimation factor */
+  if((blockSize % M) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+    /* Assign filter taps */
+    S->numTaps = numTaps;
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
+    memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(q31_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    /* Assign Decimation factor */
+    S->M = M;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+/**   
+ * @} end of FIR_decimate group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c
new file mode 100644
index 000000000..be264594f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c
@@ -0,0 +1,285 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_decimate_q15.c   
+*   
+* Description:	Q15 FIR Decimator.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_decimate   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q15 FIR decimator.   
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the location where the output result is written.   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.   
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.   
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.   
+ *   
+ * \par   
+ * Refer to the function arm_fir_decimate_fast_q15() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  q63_t sum0;                                    /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /*Set sum to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+      x0 = *__SIMD32(px)++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLALD(x0, c0, sum0);
+
+      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+      x0 = *__SIMD32(px)++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLALD(x0, c0, sum0);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLALD(x0, c0, sum0);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor   
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /*Set sum to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q31_t) x0 *c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor          
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /*Store filter output , smlad will return the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last numTaps - 1 samples to the start of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = numTaps - 1u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR_decimate group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c
new file mode 100644
index 000000000..96f7ce1cf
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c
@@ -0,0 +1,303 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_decimate_q31.c   
+*   
+* Description:	Q31 FIR Decimator.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_decimate   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q31 FIR decimator.   
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return none   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around rather than clip.   
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).   
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.   
+ *   
+ * \par   
+ * Refer to the function arm_fir_decimate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  q31_t *px;                                     /* Temporary pointers for state buffer */
+  q31_t *pb;                                     /* Temporary pointers for coefficient buffer */
+  q63_t sum0;                                    /* Accumulator */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-1] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-2] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor   
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = (q31_t) (sum0 >> 31);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor          
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = (q31_t) (sum0 >> 31);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last numTaps - 1 samples to the start of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = numTaps - 1u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR_decimate group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c
new file mode 100644
index 000000000..1a166544e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c
@@ -0,0 +1,436 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_f32.c   
+*   
+* Description:	Floating-point FIR filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup FIR Finite Impulse Response (FIR) Filters   
+ *   
+ * This set of functions implements Finite Impulse Response (FIR) filters   
+ * for Q7, Q15, Q31, and floating-point data types.   
+ * Fast versions of Q15 and Q31 are also provided on Cortex-M4 and Cortex-M3.   
+ * The functions operate on blocks of input and output data and each call to the function processes   
+ * blockSize samples through the filter.  pSrc and   
+ * pDst points to input and output arrays containing blockSize values.   
+ *   
+ * \par Algorithm:   
+ * The FIR filter algorithm is based upon a sequence of multiply-accumulate (MAC) operations.   
+ * Each filter coefficient b[n] is multiplied by a state variable which equals a previous input sample x[n].   
+ * 
   
+ *    y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]   
+ * 
   
+ * \par   
+ * \image html FIR.gif "Finite Impulse Response filter"   
+ * \par   
+ * pCoeffs points to a coefficient array of size numTaps.   
+ * Coefficients are stored in time reversed order.   
+ * \par   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * \par   
+ * pState points to a state array of size numTaps + blockSize - 1.   
+ * Samples in the state buffer are stored in the following order.   
+ * \par   
+ * 
   
+ *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}   
+ * 
   
+ * \par   
+ * Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1.   
+ * The increased state buffer length allows circular addressing, which is traditionally used in the FIR filters,   
+ * to be avoided and yields a significant speed improvement.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.   
+ * There are separate instance structure declarations for each of the 4 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ *   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Set the values in the state buffer to zeros before static initialization.   
+ * The code below statically initializes each of the 4 different data type filter instance structures   
+ * 
   
+ *arm_fir_instance_f32 S = {numTaps, pState, pCoeffs};   
+ *arm_fir_instance_q31 S = {numTaps, pState, pCoeffs};   
+ *arm_fir_instance_q15 S = {numTaps, pState, pCoeffs};   
+ *arm_fir_instance_q7 S =  {numTaps, pState, pCoeffs};   
+ * 
   
+ *   
+ * where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer;   
+ * pCoeffs is the address of the coefficient buffer.   
+ *   
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the FIR filter functions.   
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ *   
+ * @param[in]  *S points to an instance of the floating-point FIR filter structure.   
+ * @param[in]  *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in]  blockSize number of samples to process per call.   
+ * @return     none.   
+ *   
+ */
+
+void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t acc0, acc1, acc2, acc3;              /* Accumulators */
+  float32_t x0, x1, x2, x3, c0;                  /* Temporary variables to hold state and coefficient values */
+
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.   
+   * The variables acc0 ... acc3 hold output values that are being computed:   
+   *   
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]   
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]   
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]   
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]   
+   */
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0.0f;
+    acc1 = 0.0f;
+    acc2 = 0.0f;
+    acc3 = 0.0f;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Read the first three samples from the state buffer:  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+    x0 = *px++;
+    x1 = *px++;
+    x2 = *px++;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2u;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x3 = *(px++);
+
+      /* acc0 +=  b[numTaps-1] * x[n-numTaps] */
+      acc0 += x0 * c0;
+
+      /* acc1 +=  b[numTaps-1] * x[n-numTaps-1] */
+      acc1 += x1 * c0;
+
+      /* acc2 +=  b[numTaps-1] * x[n-numTaps-2] */
+      acc2 += x2 * c0;
+
+      /* acc3 +=  b[numTaps-1] * x[n-numTaps-3] */
+      acc3 += x3 * c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      acc0 += x1 * c0;
+      acc1 += x2 * c0;
+      acc2 += x3 * c0;
+      acc3 += x0 * c0;
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-5] sample */
+      x1 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += x2 * c0;
+      acc1 += x3 * c0;
+      acc2 += x0 * c0;
+      acc3 += x1 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-6] sample */
+      x2 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += x3 * c0;
+      acc1 += x0 * c0;
+      acc2 += x1 * c0;
+      acc3 += x2 * c0;
+
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x3 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+      acc2 += x2 * c0;
+      acc3 += x3 * c0;
+
+      /* Reuse the present sample states for next sample */
+      x0 = x1;
+      x1 = x2;
+      x2 = x3;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* The results in the 4 accumulators, store in the destination buffer. */
+    *pDst++ = acc0;
+    *pDst++ = acc1;
+    *pDst++ = acc2;
+    *pDst++ = acc3;
+
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0.0f;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = (pCoeffs);
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      acc0 += *px++ * *pb++;
+      i--;
+
+    } while(i > 0u);
+
+    /* The result is store in the destination buffer. */
+    *pDst++ = acc0;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t acc;
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Initialize blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc = 0.0f;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = pCoeffs;
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+      acc += *px++ * *pb++;
+      i--;
+
+    } while(i > 0u);
+
+    /* The result is store in the destination buffer. */
+    *pDst++ = acc;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last numTaps - 1 samples to the starting of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy numTaps number of values */
+  tapCnt = numTaps - 1u;
+
+  /* Copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c
new file mode 100644
index 000000000..cbd0827df
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c
@@ -0,0 +1,279 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_fast_q15.c   
+*   
+* Description:  Q15 Fast FIR filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.9  2010/08/16    
+*    Initial version   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in] blockSize number of samples to process per call.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * This fast version uses a 32-bit accumulator with 2.30 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.   
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.   
+ * The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.   
+ *   
+ * \par   
+ * Refer to the function arm_fir_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.  Both the slow and the fast versions use the same instance structure.   
+ * Use the function arm_fir_init_q15() to initialize the filter structure.   
+ */
+
+void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px1;                                    /* Temporary q15 pointer for state buffer */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q31_t *px2;                                    /* Temporary q31 pointer for SIMD state buffer accesses */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold SIMD state and coefficient values */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.   
+   * The variables acc0 ... acc3 hold output values that are being computed:   
+   *   
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]   
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]   
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]   
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]   
+   */
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer.   
+     ** Use 32-bit SIMD to move the 16-bit data.  Only requires two copies. */
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Initialize state pointer of type q15 */
+    px1 = pState;
+
+    /* Initialize coeff pointer of type q31 */
+    pb = (q31_t *) (pCoeffs);
+
+    /* Read the first two samples from the state buffer:  x[n-N], x[n-N-1] */
+    x0 = *(q31_t *) (px1++);
+
+    /* Read the third and forth samples from the state buffer: x[n-N-1], x[n-N-2] */
+    x1 = *(q31_t *) (px1++);
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    tapCnt = numTaps >> 2;
+    do
+    {
+      /* Read the first two coefficients using SIMD:  b[N] and b[N-1] coefficients */
+      c0 = *(pb++);
+
+      /* acc0 +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+      acc0 = __SMLAD(x0, c0, acc0);
+
+      /* acc1 +=  b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
+      acc1 = __SMLAD(x1, c0, acc1);
+
+      /* Read state x[n-N-2], x[n-N-3] */
+      x2 = *(q31_t *) (px1++);
+
+      /* Read state x[n-N-3], x[n-N-4] */
+      x3 = *(q31_t *) (px1++);
+
+      /* acc2 +=  b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
+      acc2 = __SMLAD(x2, c0, acc2);
+
+      /* acc3 +=  b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
+      acc3 = __SMLAD(x3, c0, acc3);
+
+      /* Read coefficients b[N-2], b[N-3] */
+      c0 = *(pb++);
+
+      /* acc0 +=  b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
+      acc0 = __SMLAD(x2, c0, acc0);
+
+      /* acc1 +=  b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
+      acc1 = __SMLAD(x3, c0, acc1);
+
+      /* Read state x[n-N-4], x[n-N-5] */
+      x0 = *(q31_t *) (px1++);
+
+      /* Read state x[n-N-5], x[n-N-6] */
+      x1 = *(q31_t *) (px1++);
+
+      /* acc2 +=  b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
+      acc2 = __SMLAD(x0, c0, acc2);
+
+      /* acc3 +=  b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
+      acc3 = __SMLAD(x1, c0, acc3);
+      tapCnt--;
+
+    }
+    while(tapCnt > 0u);
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps.   
+     ** This is always 2 taps since the filter length is always even. */
+    if((numTaps & 0x3u) != 0u)
+    {
+      /* Read 2 coefficients */
+      c0 = *(pb++);
+      /* Fetch 4 state variables */
+      x2 = *(q31_t *) (px1++);
+      x3 = *(q31_t *) (px1++);
+
+      /* Perform the multiply-accumulates */
+      acc0 = __SMLAD(x0, c0, acc0);
+      acc1 = __SMLAD(x1, c0, acc1);
+      acc2 = __SMLAD(x2, c0, acc2);
+      acc3 = __SMLAD(x3, c0, acc3);
+    }
+
+    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.15 with saturation.   
+     ** Then store the 4 outputs in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ = __PKHBT((acc0 >> 15), (acc1 >> 15), 16u);
+    *__SIMD32(pDst)++ = __PKHBT((acc2 >> 15), (acc3 >> 15), 16u);
+
+#else
+
+    *__SIMD32(pDst)++ = __PKHBT((acc1 >> 15), (acc0 >> 15), 16u);
+    *__SIMD32(pDst)++ = __PKHBT((acc3 >> 15), (acc2 >> 15), 16u);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+  while(blkCnt > 0u)
+  {
+    /* Copy two samples into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Use SIMD to hold states and coefficients */
+    px2 = (q31_t *) pState;
+    pb = (q31_t *) (pCoeffs);
+    tapCnt = numTaps >> 1;
+
+    do
+    {
+      acc0 = __SMLAD(*px2++, *(pb++), acc0);
+      tapCnt--;
+    }
+    while(tapCnt > 0u);
+
+    /* The result is in 2.30 format.  Convert to 1.15 with saturation.   
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q15_t) ((acc0 >> 15));
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1u) >> 2;
+
+  while(tapCnt > 0u)
+  {
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    tapCnt--;
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* copy remaining data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c
new file mode 100644
index 000000000..6cbfa7f9d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c
@@ -0,0 +1,303 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_fast_q31.c   
+*   
+* Description:	Processing function for the Q31 Fast FIR filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.9  2010/08/27    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ * @param[in] *S points to an instance of the Q31 structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block output data.   
+ * @param[in] blockSize number of samples to process per call.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.   
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.   
+ * These intermediate results are added to a 2.30 accumulator.   
+ * Finally, the accumulator is saturated and converted to a 1.31 result.   
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.   
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.   
+ *   
+ * \par   
+ * Refer to the function arm_fir_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.  Both the slow and the fast versions use the same instance structure.   
+ * Use the function arm_fir_init_q31() to initialize the filter structure.   
+ */
+
+void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t x0, x1, x2, x3;                          /* Temporary variables to hold state */
+  q31_t c0;                                      /* Temporary variable to hold coefficient value */
+  q31_t *px;                                     /* Temporary pointer for state */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.   
+   * The variables acc0 ... acc3 hold output values that are being computed:   
+   *   
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]   
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]   
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]   
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]   
+   */
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Read the first three samples from the state buffer:   
+     *  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+    x0 = *(px++);
+    x1 = *(px++);
+    x2 = *(px++);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+    i = tapCnt;
+
+    while(i > 0u)
+    {
+      /* Read the b[numTaps] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x3 = *(px++);
+
+      /* acc0 +=  b[numTaps] * x[n-numTaps] */
+      acc0 = (q31_t) ((((q63_t) x0 * c0) + (acc0 << 32)) >> 32);
+
+      /* acc1 +=  b[numTaps] * x[n-numTaps-1] */
+      acc1 = (q31_t) ((((q63_t) x1 * c0) + (acc1 << 32)) >> 32);
+
+      /* acc2 +=  b[numTaps] * x[n-numTaps-2] */
+      acc2 = (q31_t) ((((q63_t) x2 * c0) + (acc2 << 32)) >> 32);
+
+      /* acc3 +=  b[numTaps] * x[n-numTaps-3] */
+      acc3 = (q31_t) ((((q63_t) x3 * c0) + (acc3 << 32)) >> 32);
+
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 = (q31_t) ((((q63_t) x1 * c0) + (acc0 << 32)) >> 32);
+      acc1 = (q31_t) ((((q63_t) x2 * c0) + (acc1 << 32)) >> 32);
+      acc2 = (q31_t) ((((q63_t) x3 * c0) + (acc2 << 32)) >> 32);
+      acc3 = (q31_t) ((((q63_t) x0 * c0) + (acc3 << 32)) >> 32);
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-5] sample */
+      x1 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 = (q31_t) ((((q63_t) x2 * c0) + (acc0 << 32)) >> 32);
+      acc1 = (q31_t) ((((q63_t) x3 * c0) + (acc1 << 32)) >> 32);
+      acc2 = (q31_t) ((((q63_t) x0 * c0) + (acc2 << 32)) >> 32);
+      acc3 = (q31_t) ((((q63_t) x1 * c0) + (acc3 << 32)) >> 32);
+
+      /* Read the b[numTaps-3] coefficients */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-6] sample */
+      x2 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 = (q31_t) ((((q63_t) x3 * c0) + (acc0 << 32)) >> 32);
+      acc1 = (q31_t) ((((q63_t) x0 * c0) + (acc1 << 32)) >> 32);
+      acc2 = (q31_t) ((((q63_t) x1 * c0) + (acc2 << 32)) >> 32);
+      acc3 = (q31_t) ((((q63_t) x2 * c0) + (acc3 << 32)) >> 32);
+      i--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+
+    i = numTaps - (tapCnt * 4u);
+    while(i > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x3 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 = (q31_t) ((((q63_t) x0 * c0) + (acc0 << 32)) >> 32);
+      acc1 = (q31_t) ((((q63_t) x1 * c0) + (acc1 << 32)) >> 32);
+      acc2 = (q31_t) ((((q63_t) x2 * c0) + (acc2 << 32)) >> 32);
+      acc3 = (q31_t) ((((q63_t) x3 * c0) + (acc3 << 32)) >> 32);
+
+      /* Reuse the present sample states for next sample */
+      x0 = x1;
+      x1 = x2;
+      x2 = x3;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.31   
+     ** Then store the 4 outputs in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 << 1);
+    *pDst++ = (q31_t) (acc1 << 1);
+    *pDst++ = (q31_t) (acc2 << 1);
+    *pDst++ = (q31_t) (acc3 << 1);
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = (pCoeffs);
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      acc0 = (q31_t) ((((q63_t) * (px++) * (*(pb++))) + (acc0 << 32)) >> 32);
+      i--;
+    } while(i > 0u);
+
+    /* The result is in 2.30 format.  Convert to 1.31   
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 << 1);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c
new file mode 100644
index 000000000..100d4ac34
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c
@@ -0,0 +1,91 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_init_f32.c   
+*   
+* Description:  Floating-point FIR filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ * @details   
+ *   
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.   
+ * @param[in] 	  numTaps  Number of filter coefficients in the filter.   
+ * @param[in]     *pCoeffs points to the filter coefficients buffer.   
+ * @param[in]     *pState points to the state buffer.   
+ * @param[in] 	  blockSize number of samples that are processed per call.   
+ * @return 		  none.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_f32().   
+ */
+
+void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and the size of state buffer is (blockSize + numTaps - 1) */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c
new file mode 100644
index 000000000..9d01aa13a
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c
@@ -0,0 +1,149 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_init_q15.c   
+*   
+* Description:  Q15 FIR filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ * @param[in,out]  *S points to an instance of the Q15 FIR filter structure.   
+ * @param[in] 	   numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.   
+ * @param[in]      *pCoeffs points to the filter coefficients buffer.   
+ * @param[in]      *pState points to the state buffer.   
+ * @param[in]      blockSize is number of samples processed per call.   
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if   
+ * numTaps is not greater than or equal to 4 and even.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * Note that numTaps must be even and greater than or equal to 4.   
+ * To implement an odd length filter simply increase numTaps by 1 and set the last coefficient to zero.   
+ * For example, to implement a filter with numTaps=3 and coefficients   
+ * 
   
+ *     {0.3, -0.8, 0.3}   
+ * 
   
+ * set numTaps=4 and use the coefficients:   
+ * 
   
+ *     {0.3, -0.8, 0.3, 0}.   
+ * 
   
+ * Similarly, to implement a two point filter   
+ * 
   
+ *     {0.3, -0.3}   
+ * 
   
+ * set numTaps=4 and use the coefficients:   
+ * 
   
+ *     {0.3, -0.3, 0, 0}.   
+ * 
   
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length numTaps+blockSize-1, where blockSize is the number of input samples processed by each call to arm_fir_q15().   
+ */
+
+arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* The Number of filter coefficients in the filter must be even and at least 4 */
+  if((numTaps < 4u) || (numTaps & 0x1u))
+  {
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Assign filter taps */
+    S->numTaps = numTaps;
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
+    memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  status = ARM_MATH_SUCCESS;
+
+  return (status);
+
+#endif /*  #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c
new file mode 100644
index 000000000..19762289e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c
@@ -0,0 +1,91 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_init_q31.c   
+*   
+* Description:	Q31 FIR filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ * @details   
+ *   
+ * @param[in,out] *S points to an instance of the Q31 FIR filter structure.   
+ * @param[in] 	  numTaps  Number of filter coefficients in the filter.   
+ * @param[in] 	  *pCoeffs points to the filter coefficients buffer.   
+ * @param[in] 	  *pState points to the state buffer.   
+ * @param[in] 	  blockSize number of samples that are processed per call.   
+ * @return        none.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q31().   
+ */
+
+void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and state array size is (blockSize + numTaps - 1) */
+  memset(pState, 0, (blockSize + ((uint32_t) numTaps - 1u)) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c
new file mode 100644
index 000000000..33b80a6dd
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c
@@ -0,0 +1,89 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_init_q7.c   
+*   
+* Description:  Q7 FIR filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+/**   
+ * @param[in,out] *S points to an instance of the Q7 FIR filter structure.   
+ * @param[in] 	  numTaps  Number of filter coefficients in the filter.   
+ * @param[in] 	  *pCoeffs points to the filter coefficients buffer.   
+ * @param[in]     *pState points to the state buffer.   
+ * @param[in]     blockSize number of samples that are processed per call.   
+ * @return     	  none   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q7().   
+ */
+
+void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize)
+{
+
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q7_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c
new file mode 100644
index 000000000..abee5bfba
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c
@@ -0,0 +1,399 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_interpolate_f32.c   
+*   
+* Description:	FIR interpolation for floating-point sequences.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @defgroup FIR_Interpolate Finite Impulse Response (FIR) Interpolator   
+ *   
+ * These functions combine an upsampler (zero stuffer) and an FIR filter.   
+ * They are used in multirate systems for increasing the sample rate of a signal without introducing high frequency images.   
+ * Conceptually, the functions are equivalent to the block diagram below:   
+ * \image html FIRInterpolator.gif "Components included in the FIR Interpolator functions"   
+ * After upsampling by a factor of L, the signal should be filtered by a lowpass filter with a normalized   
+ * cutoff frequency of 1/L in order to eliminate high frequency copies of the spectrum.   
+ * The user of the function is responsible for providing the filter coefficients.   
+ *   
+ * The FIR interpolator functions provided in the CMSIS DSP Library combine the upsampler and FIR filter in an efficient manner.   
+ * The upsampler inserts L-1 zeros between each sample.   
+ * Instead of multiplying by these zero values, the FIR filter is designed to skip them.   
+ * This leads to an efficient implementation without any wasted effort.   
+ * The functions operate on blocks of input and output data.   
+ * pSrc points to an array of blockSize input values and   
+ * pDst points to an array of blockSize*L output values.   
+ *   
+ * The library provides separate functions for Q15, Q31, and floating-point data types.   
+ *   
+ * \par Algorithm:   
+ * The functions use a polyphase filter structure:   
+ * 
   
+ *    y[n] = b[0] * x[n] + b[L]   * x[n-1] + ... + b[L*(phaseLength-1)] * x[n-phaseLength+1]   
+ *    y[n+1] = b[1] * x[n] + b[L+1] * x[n-1] + ... + b[L*(phaseLength-1)+1] * x[n-phaseLength+1]   
+ *    ...   
+ *    y[n+(L-1)] = b[L-1] * x[n] + b[2*L-1] * x[n-1] + ....+ b[L*(phaseLength-1)+(L-1)] * x[n-phaseLength+1]   
+ * 
   
+ * This approach is more efficient than straightforward upsample-then-filter algorithms.   
+ * With this method the computation is reduced by a factor of 1/L when compared to using a standard FIR filter.   
+ * \par   
+ * pCoeffs points to a coefficient array of size numTaps.   
+ * numTaps must be a multiple of the interpolation factor L and this is checked by the   
+ * initialization functions.   
+ * Internally, the function divides the FIR filter's impulse response into shorter filters of length   
+ * phaseLength=numTaps/L.   
+ * Coefficients are stored in time reversed order.   
+ * \par   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * \par   
+ * pState points to a state array of size blockSize + phaseLength - 1.   
+ * Samples in the state buffer are stored in the order:   
+ * \par   
+ * 
   
+ *    {x[n-phaseLength+1], x[n-phaseLength], x[n-phaseLength-1], x[n-phaseLength-2]....x[0], x[1], ..., x[blockSize-1]}   
+ * 
   
+ * The state variables are updated after each block of data is processed, the coefficients are untouched.   
+ *   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient arrays may be shared among several instances while state variable array should be allocated separately.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ * - Checks to make sure that the length of the filter is a multiple of the interpolation factor.   
+ *   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * The code below statically initializes each of the 3 different data type filter instance structures   
+ * 
   
+ * arm_fir_interpolate_instance_f32 S = {L, phaseLength, pCoeffs, pState};   
+ * arm_fir_interpolate_instance_q31 S = {L, phaseLength, pCoeffs, pState};   
+ * arm_fir_interpolate_instance_q15 S = {L, phaseLength, pCoeffs, pState};   
+ * 
   
+ * where L is the interpolation factor; phaseLength=numTaps/L is the   
+ * length of each of the shorter FIR filters used internally,   
+ * pCoeffs is the address of the coefficient buffer;   
+ * pState is the address of the state buffer.   
+ * Be sure to set the values in the state buffer to zeros when doing static initialization.   
+ *   
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the FIR interpolate filter functions.   
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+/**   
+ * @addtogroup FIR_Interpolate   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the floating-point FIR interpolator.   
+ * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.   
+ * @param[in] *pSrc     points to the block of input data.   
+ * @param[out] *pDst    points to the block of output data.   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return none.   
+ */
+
+void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *ptr1, *ptr2;                        /* Temporary pointers for state and coefficient buffers */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t sum0;                                /* Accumulators */
+  float32_t x0, c0;                              /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt, j;                         /* Loop counters */
+  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (phaseLen - 1u);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1u;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum0 = 0.0f;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.   
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = phaseLen >> 2u;
+      while(tapCnt > 0u)
+      {
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.   
+         * So instead of multiplying zeros with coefficients,   
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += x0 * c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += x0 * c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += x0 * c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += x0 * c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = phaseLen % 0x4u;
+
+      while(tapCnt > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum0 += *(ptr1++) * (*ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = sum0;
+
+      /* Increment the address modifier index of coefficient buffer */
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1   
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (phaseLen - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  tapCnt = (phaseLen - 1u) % 0x04u;
+
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t sum;                                 /* Accumulator */
+  uint32_t i, blkCnt;                            /* Loop counters */
+  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (phaseLen - 1u);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum = 0.0f;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (i - 1u);
+
+      /* Loop over the polyPhase length */
+      tapCnt = phaseLen;
+
+      while(tapCnt > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *ptr1++ * *ptr2;
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = sum;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1          
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last phaseLen - 1 samples to the start of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = phaseLen - 1u;
+
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+ /**   
+  * @} end of FIR_Interpolate group   
+  */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c
new file mode 100644
index 000000000..59802b24d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c
@@ -0,0 +1,113 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_interpolate_init_f32.c   
+*   
+* Description:  Floating-point FIR interpolator initialization function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Interpolate   
+ * @{   
+ */
+
+/**   
+ * @brief  Initialization function for the floating-point FIR interpolator.   
+ * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.   
+ * @param[in]     L         upsample factor.   
+ * @param[in]     numTaps   number of filter coefficients in the filter.   
+ * @param[in]     *pCoeffs  points to the filter coefficient buffer.   
+ * @param[in]     *pState   points to the state buffer.   
+ * @param[in]     blockSize number of input samples to process per call.   
+ * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if   
+ * the filter length numTaps is not a multiple of the interpolation factor L.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}   
+ * 
   
+ * The length of the filter numTaps must be a multiple of the interpolation factor L.   
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length (numTaps/L)+blockSize-1 words   
+ * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_f32().   
+ */
+
+arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The filter length must be a multiple of the interpolation factor */
+  if((numTaps % L) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Assign Interpolation factor */
+    S->L = L;
+
+    /* Assign polyPhaseLength */
+    S->phaseLength = numTaps / L;
+
+    /* Clear state buffer and size of state array is always phaseLength + blockSize - 1 */
+    memset(pState, 0,
+           (blockSize +
+            ((uint32_t) S->phaseLength - 1u)) * sizeof(float32_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+ /**   
+  * @} end of FIR_Interpolate group   
+  */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c
new file mode 100644
index 000000000..0ab6e6bc5
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c
@@ -0,0 +1,112 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_interpolate_init_q15.c   
+*   
+* Description:  Q15 FIR interpolator initialization function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Interpolate   
+ * @{   
+ */
+
+/**   
+ * @brief  Initialization function for the Q15 FIR interpolator.   
+ * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.   
+ * @param[in]     L         upsample factor.   
+ * @param[in]     numTaps   number of filter coefficients in the filter.   
+ * @param[in]     *pCoeffs  points to the filter coefficient buffer.   
+ * @param[in]     *pState   points to the state buffer.   
+ * @param[in]     blockSize number of input samples to process per call.   
+ * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if   
+ * the filter length numTaps is not a multiple of the interpolation factor L.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}   
+ * 
   
+ * The length of the filter numTaps must be a multiple of the interpolation factor L.   
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length (numTaps/L)+blockSize-1 words   
+ * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q15().   
+ */
+
+arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The filter length must be a multiple of the interpolation factor */
+  if((numTaps % L) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Assign Interpolation factor */
+    S->L = L;
+
+    /* Assign polyPhaseLength */
+    S->phaseLength = numTaps / L;
+
+    /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
+    memset(pState, 0,
+           (blockSize + ((uint32_t) S->phaseLength - 1u)) * sizeof(q15_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+ /**   
+  * @} end of FIR_Interpolate group   
+  */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c
new file mode 100644
index 000000000..92906c11e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c
@@ -0,0 +1,113 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_interpolate_init_q31.c   
+*   
+* Description:  Q31 FIR interpolator initialization function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Interpolate   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Initialization function for the Q31 FIR interpolator.   
+ * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.   
+ * @param[in]     L         upsample factor.   
+ * @param[in]     numTaps   number of filter coefficients in the filter.   
+ * @param[in]     *pCoeffs  points to the filter coefficient buffer.   
+ * @param[in]     *pState   points to the state buffer.   
+ * @param[in]     blockSize number of input samples to process per call.   
+ * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if   
+ * the filter length numTaps is not a multiple of the interpolation factor L.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}   
+ * 
   
+ * The length of the filter numTaps must be a multiple of the interpolation factor L.   
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length (numTaps/L)+blockSize-1 words   
+ * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q31().   
+ */
+
+arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The filter length must be a multiple of the interpolation factor */
+  if((numTaps % L) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Assign Interpolation factor */
+    S->L = L;
+
+    /* Assign polyPhaseLength */
+    S->phaseLength = numTaps / L;
+
+    /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
+    memset(pState, 0,
+           (blockSize + ((uint32_t) S->phaseLength - 1u)) * sizeof(q31_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+ /**   
+  * @} end of FIR_Interpolate group   
+  */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c
new file mode 100644
index 000000000..56dddcc17
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c
@@ -0,0 +1,349 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_fir_interpolate_q15.c   
+*   
+* Description:	Q15 FIR interpolation.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Interpolate   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q15 FIR interpolator.   
+ * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.   
+ * @param[in] *pSrc     points to the block of input data.   
+ * @param[out] *pDst    points to the block of output data.   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.   
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.   
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.   
+ */
+
+void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer                                            */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer                                      */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state                */
+  q15_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers     */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q63_t sum0;                                    /* Accumulators                                             */
+  q15_t x0, c0, c1;                              /* Temporary variables to hold state and coefficient values */
+  q31_t c, x;
+  uint32_t i, blkCnt, j, tapCnt;                 /* Loop counters                                            */
+  uint16_t phaseLen = S->phaseLength;            /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (phaseLen - 1u);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1u;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum0 = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.   
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = (uint32_t) phaseLen >> 2u;
+      while(tapCnt > 0u)
+      {
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.   
+         * So instead of multiplying zeros with coefficients,   
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the coefficient */
+        c1 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Pack the coefficients */
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+        c = __PKHBT(c0, c1, 16);
+
+#else
+
+        c = __PKHBT(c1, c0, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+        /* Read twp consecutive input samples */
+        x = *__SIMD32(ptr1)++;
+
+        /* Perform the multiply-accumulate */
+        sum0 = __SMLALD(x, c, sum0);
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.   
+         * So insted of multiplying zeros with coefficients,   
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the coefficient */
+        c1 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Pack the coefficients */
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+        c = __PKHBT(c0, c1, 16);
+
+#else
+
+        c = __PKHBT(c1, c0, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN            */
+
+        /* Read twp consecutive input samples */
+        x = *__SIMD32(ptr1)++;
+
+        /* Perform the multiply-accumulate */
+        sum0 = __SMLALD(x, c, sum0);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = (uint32_t) phaseLen & 0x3u;
+
+      while(tapCnt > 0u)
+      {
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 = __SMLALD(x0, c0, sum0);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+      /* Increment the address modifier index of coefficient buffer */
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1   
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = ((uint32_t) phaseLen - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = ((uint32_t) phaseLen - 1u) % 0x04u;
+
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q63_t sum;                                     /* Accumulator */
+  q15_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt, tapCnt;                    /* Loop counters                                            */
+  uint16_t phaseLen = S->phaseLength;            /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (phaseLen - 1u);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (i - 1u);
+
+      /* Loop over the polyPhase length */
+      tapCnt = (uint32_t) phaseLen;
+
+      while(tapCnt > 0u)
+      {
+        /* Read the coefficient */
+        c0 = *ptr2;
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *ptr1++;
+
+        /* Perform the multiply-accumulate */
+        sum += ((q31_t) x0 * c0);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* Store the result after converting to 1.15 format in the destination buffer */
+      *pDst++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1          
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last phaseLen - 1 samples to the start of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (uint32_t) phaseLen - 1u;
+
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+ /**   
+  * @} end of FIR_Interpolate group   
+  */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c
new file mode 100644
index 000000000..660b7dd5b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c
@@ -0,0 +1,340 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_fir_interpolate_q31.c   
+*   
+* Description:	Q31 FIR interpolation.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Interpolate   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q31 FIR interpolator.   
+ * @param[in] *S        points to an instance of the Q31 FIR interpolator structure.   
+ * @param[in] *pSrc     points to the block of input data.   
+ * @param[out] *pDst    points to the block of output data.   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around rather than clip.   
+ * In order to avoid overflows completely the input signal must be scaled down by 1/(numTaps/L).   
+ * since numTaps/L additions occur per output sample.   
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.   
+ */
+
+
+void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q63_t sum0;                                    /* Accumulators */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt, j;                         /* Loop counters */
+  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1u;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum0 = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.   
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = phaseLen >> 2;
+      while(tapCnt > 0u)
+      {
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.   
+         * So instead of multiplying zeros with coefficients,   
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = phaseLen & 0x3u;
+
+      while(tapCnt > 0u)
+      {
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = (q31_t) (sum0 >> 31);
+
+      /* Increment the address modifier index of coefficient buffer */
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1   
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (phaseLen - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  tapCnt = (phaseLen - 1u) % 0x04u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q63_t sum;                                     /* Accumulator */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt;                            /* Loop counters */
+  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (i - 1u);
+
+      tapCnt = phaseLen;
+
+      while(tapCnt > 0u)
+      {
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *ptr1++;
+
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) x0 *c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = (q31_t) (sum >> 31);
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1          
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = phaseLen - 1u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+ /**   
+  * @} end of FIR_Interpolate group   
+  */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c
new file mode 100644
index 000000000..4192992f9
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c
@@ -0,0 +1,496 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_lattice_f32.c   
+*   
+* Description:	Processing function for the floating-point FIR Lattice filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup FIR_Lattice Finite Impulse Response (FIR) Lattice Filters   
+ *   
+ * This set of functions implements Finite Impulse Response (FIR) lattice filters   
+ * for Q15, Q31 and floating-point data types.  Lattice filters are used in a    
+ * variety of adaptive filter applications.  The filter structure is feedforward and   
+ * the net impulse response is finite length.   
+ * The functions operate on blocks   
+ * of input and output data and each call to the function processes   
+ * blockSize samples through the filter.  pSrc and   
+ * pDst point to input and output arrays containing blockSize values.   
+ *   
+ * \par Algorithm:   
+ * \image html FIRLattice.gif "Finite Impulse Response Lattice filter"   
+ * The following difference equation is implemented:   
+ * 
   
+ *    f0[n] = g0[n] = x[n]   
+ *    fm[n] = fm-1[n] + km * gm-1[n-1] for m = 1, 2, ...M   
+ *    gm[n] = km * fm-1[n] + gm-1[n-1] for m = 1, 2, ...M   
+ *    y[n] = fM[n]   
+ * 
   
+ * \par   
+ * pCoeffs points to tha array of reflection coefficients of size numStages.   
+ * Reflection Coefficients are stored in the following order.   
+ * \par   
+ * 
   
+ *    {k1, k2, ..., kM}   
+ * 
   
+ * where M is number of stages   
+ * \par   
+ * pState points to a state array of size numStages.   
+ * The state variables (g values) hold previous inputs and are stored in the following order.   
+ * 
   
+ *    {g0[n], g1[n], g2[n] ...gM-1[n]}   
+ * 
   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ *   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:   
+ * 
   
+ *arm_fir_lattice_instance_f32 S = {numStages, pState, pCoeffs};   
+ *arm_fir_lattice_instance_q31 S = {numStages, pState, pCoeffs};   
+ *arm_fir_lattice_instance_q15 S = {numStages, pState, pCoeffs};   
+ * 
   
+ * \par   
+ * where numStages is the number of stages in the filter; pState is the address of the state buffer;   
+ * pCoeffs is the address of the coefficient buffer.   
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the FIR Lattice filter functions.   
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+/**   
+ * @addtogroup FIR_Lattice   
+ * @{   
+ */
+
+
+  /**   
+   * @brief Processing function for the floating-point FIR lattice filter.   
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.   
+   * @param[in]  *pSrc     points to the block of input data.   
+   * @param[out] *pDst     points to the block of output data   
+   * @param[in]  blockSize number of samples to process.   
+   * @return none.   
+   */
+
+void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pState;                             /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *px;                                 /* temporary state pointer */
+  float32_t *pk;                                 /* temporary coefficient pointer */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t fcurr1, fnext1, gcurr1, gnext1;      /* temporary variables for first sample in loop unrolling */
+  float32_t fcurr2, fnext2, gnext2;              /* temporary variables for second sample in loop unrolling */
+  float32_t fcurr3, fnext3, gnext3;              /* temporary variables for third sample in loop unrolling */
+  float32_t fcurr4, fnext4, gnext4;              /* temporary variables for fourth sample in loop unrolling */
+  uint32_t numStages = S->numStages;             /* Number of stages in the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  gcurr1 = 0.0f;
+  pState = &S->pState[0];
+
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+    /* Read two samples from input buffer */
+    /* f0(n) = x(n) */
+    fcurr1 = *pSrc++;
+    fcurr2 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Read g0(n-1) from state */
+    gcurr1 = *px;
+
+    /* Process first sample for first tap */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = fcurr1 + ((*pk) * gcurr1);
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (fcurr1 * (*pk)) + gcurr1;
+
+    /* Process second sample for first tap */
+    /* for sample 2 processing */
+    fnext2 = fcurr2 + ((*pk) * fcurr1);
+    gnext2 = (fcurr2 * (*pk)) + fcurr1;
+
+    /* Read next two samples from input buffer */
+    /* f0(n+2) = x(n+2) */
+    fcurr3 = *pSrc++;
+    fcurr4 = *pSrc++;
+
+    /* Copy only last input samples into the state buffer   
+       which will be used for next four samples processing */
+    *px++ = fcurr4;
+
+    /* Process third sample for first tap */
+    fnext3 = fcurr3 + ((*pk) * fcurr2);
+    gnext3 = (fcurr3 * (*pk)) + fcurr2;
+
+    /* Process fourth sample for first tap */
+    fnext4 = fcurr4 + ((*pk) * fcurr3);
+    gnext4 = (fcurr4 * (*pk++)) + fcurr3;
+
+    /* Update of f values for next coefficient set processing */
+    fcurr1 = fnext1;
+    fcurr2 = fnext2;
+    fcurr3 = fnext3;
+    fcurr4 = fnext4;
+
+    /* Loop unrolling.  Process 4 taps at a time . */
+    stageCnt = (numStages - 1u) >> 2u;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numStages-3 coefficients. */
+
+    /* Process 2nd, 3rd, 4th and 5th taps ... here */
+    while(stageCnt > 0u)
+    {
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext4;
+
+      /* Process first sample for 2nd, 6th .. tap */
+      /* Sample processing for K2, K6.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = fcurr1 + ((*pk) * gcurr1);
+      /* Process second sample for 2nd, 6th .. tap */
+      /* for sample 2 processing */
+      fnext2 = fcurr2 + ((*pk) * gnext1);
+      /* Process third sample for 2nd, 6th .. tap */
+      fnext3 = fcurr3 + ((*pk) * gnext2);
+      /* Process fourth sample for 2nd, 6th .. tap */
+      fnext4 = fcurr4 + ((*pk) * gnext3);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (fcurr4 * (*pk)) + gnext3;
+      gnext3 = (fcurr3 * (*pk)) + gnext2;
+      gnext2 = (fcurr2 * (*pk)) + gnext1;
+      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g2(n) in state buffer */
+      *px++ = gnext4;
+
+      /* Sample processing for K3, K7.... */
+      /* Process first sample for 3rd, 7th .. tap */
+      /* f3(n) = f2(n) +  K3 * g2(n-1) */
+      fcurr1 = fnext1 + ((*pk) * gcurr1);
+      /* Process second sample for 3rd, 7th .. tap */
+      fcurr2 = fnext2 + ((*pk) * gnext1);
+      /* Process third sample for 3rd, 7th .. tap */
+      fcurr3 = fnext3 + ((*pk) * gnext2);
+      /* Process fourth sample for 3rd, 7th .. tap */
+      fcurr4 = fnext4 + ((*pk) * gnext3);
+
+      /* Calculation of state values for next stage */
+      /* g3(n) = f2(n) * K3  +  g2(n-1) */
+      gnext4 = (fnext4 * (*pk)) + gnext3;
+      gnext3 = (fnext3 * (*pk)) + gnext2;
+      gnext2 = (fnext2 * (*pk)) + gnext1;
+      gnext1 = (fnext1 * (*pk++)) + gcurr1;
+
+
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g3(n) in state buffer */
+      *px++ = gnext4;
+
+      /* Sample processing for K4, K8.... */
+      /* Process first sample for 4th, 8th .. tap */
+      /* f4(n) = f3(n) +  K4 * g3(n-1) */
+      fnext1 = fcurr1 + ((*pk) * gcurr1);
+      /* Process second sample for 4th, 8th .. tap */
+      /* for sample 2 processing */
+      fnext2 = fcurr2 + ((*pk) * gnext1);
+      /* Process third sample for 4th, 8th .. tap */
+      fnext3 = fcurr3 + ((*pk) * gnext2);
+      /* Process fourth sample for 4th, 8th .. tap */
+      fnext4 = fcurr4 + ((*pk) * gnext3);
+
+      /* g4(n) = f3(n) * K4  +  g3(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (fcurr4 * (*pk)) + gnext3;
+      gnext3 = (fcurr3 * (*pk)) + gnext2;
+      gnext2 = (fcurr2 * (*pk)) + gnext1;
+      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g4(n) in state buffer */
+      *px++ = gnext4;
+
+      /* Sample processing for K5, K9.... */
+      /* Process first sample for 5th, 9th .. tap */
+      /* f5(n) = f4(n) +  K5 * g4(n-1) */
+      fcurr1 = fnext1 + ((*pk) * gcurr1);
+      /* Process second sample for 5th, 9th .. tap */
+      fcurr2 = fnext2 + ((*pk) * gnext1);
+      /* Process third sample for 5th, 9th .. tap */
+      fcurr3 = fnext3 + ((*pk) * gnext2);
+      /* Process fourth sample for 5th, 9th .. tap */
+      fcurr4 = fnext4 + ((*pk) * gnext3);
+
+      /* Calculation of state values for next stage */
+      /* g5(n) = f4(n) * K5  +  g4(n-1) */
+      gnext4 = (fnext4 * (*pk)) + gnext3;
+      gnext3 = (fnext3 * (*pk)) + gnext2;
+      gnext2 = (fnext2 * (*pk)) + gnext1;
+      gnext1 = (fnext1 * (*pk++)) + gcurr1;
+
+      stageCnt--;
+    }
+
+    /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
+    stageCnt = (numStages - 1u) % 0x4u;
+
+    while(stageCnt > 0u)
+    {
+      gcurr1 = *px;
+
+      /* save g value in state buffer */
+      *px++ = gnext4;
+
+      /* Process four samples for last three taps here */
+      fnext1 = fcurr1 + ((*pk) * gcurr1);
+      fnext2 = fcurr2 + ((*pk) * gnext1);
+      fnext3 = fcurr3 + ((*pk) * gnext2);
+      fnext4 = fcurr4 + ((*pk) * gnext3);
+
+      /* g1(n) = f0(n) * K1  +  g0(n-1) */
+      gnext4 = (fcurr4 * (*pk)) + gnext3;
+      gnext3 = (fcurr3 * (*pk)) + gnext2;
+      gnext2 = (fcurr2 * (*pk)) + gnext1;
+      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+      /* Update of f values for next coefficient set processing */
+      fcurr1 = fnext1;
+      fcurr2 = fnext2;
+      fcurr3 = fnext3;
+      fcurr4 = fnext4;
+
+      stageCnt--;
+
+    }
+
+    /* The results in the 4 accumulators, store in the destination buffer. */
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr1;
+    *pDst++ = fcurr2;
+    *pDst++ = fcurr3;
+    *pDst++ = fcurr4;
+
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurr1 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g2(n) from state buffer */
+    gcurr1 = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = fcurr1 + ((*pk) * gcurr1);
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+    /* save g1(n) in state buffer */
+    *px++ = fcurr1;
+
+    /* f1(n) is saved in fcurr1   
+       for next stage processing */
+    fcurr1 = fnext1;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g2(n) from state buffer */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext1;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = fcurr1 + ((*pk) * gcurr1);
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+      /* f1(n) is saved in fcurr1   
+         for next stage processing */
+      fcurr1 = fnext1;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr1;
+
+    blkCnt--;
+
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t fcurr, fnext, gcurr, gnext;          /* temporary variables */
+  uint32_t numStages = S->numStages;             /* Length of the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = pCoeffs;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g0(n-1) from state buffer */
+    gcurr = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext = fcurr + ((*pk) * gcurr);
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext = (fcurr * (*pk++)) + gcurr;
+
+    /* save f0(n) in state buffer */
+    *px++ = fcurr;
+
+    /* f1(n) is saved in fcurr           
+       for next stage processing */
+    fcurr = fnext;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g2(n) from state buffer */
+      gcurr = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext = fcurr + ((*pk) * gcurr);
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext = (fcurr * (*pk++)) + gcurr;
+
+      /* f1(n) is saved in fcurr1           
+         for next stage processing */
+      fcurr = fnext;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr;
+
+    blkCnt--;
+
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR_Lattice group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c
new file mode 100644
index 000000000..36e19c2bd
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c
@@ -0,0 +1,75 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_lattice_init_f32.c   
+*   
+* Description:  Floating-point FIR Lattice filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Lattice   
+ * @{   
+ */
+
+/**   
+ * @brief Initialization function for the floating-point FIR lattice filter.   
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.   
+ * @param[in] numStages  number of filter stages.   
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.   
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.   
+ * @return none.   
+ */
+
+void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always numStages */
+  memset(pState, 0, (numStages) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR_Lattice group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c
new file mode 100644
index 000000000..905e7183e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c
@@ -0,0 +1,75 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_lattice_init_q15.c   
+*   
+* Description:  Q15 FIR Lattice filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Lattice   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for the Q15 FIR lattice filter.   
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.   
+   * @param[in] numStages  number of filter stages.   
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.    
+   * @param[in] *pState points to the state buffer.  The array is of length numStages.    
+   * @return none.   
+   */
+
+void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always numStages */
+  memset(pState, 0, (numStages) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR_Lattice group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c
new file mode 100644
index 000000000..43ba1af5f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c
@@ -0,0 +1,75 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_lattice_init_q31.c   
+*   
+* Description:  Q31 FIR lattice filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Lattice   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for the Q31 FIR lattice filter.   
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.   
+   * @param[in] numStages  number of filter stages.   
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.   
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.   
+   * @return none.   
+   */
+
+void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always numStages */
+  memset(pState, 0, (numStages) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR_Lattice group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c
new file mode 100644
index 000000000..3aff889f6
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c
@@ -0,0 +1,528 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_lattice_q15.c   
+*   
+* Description:	Q15 FIR lattice filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Lattice   
+ * @{   
+ */
+
+
+/**   
+ * @brief Processing function for the Q15 FIR lattice filter.   
+ * @param[in]  *S        points to an instance of the Q15 FIR lattice structure.   
+ * @param[in]  *pSrc     points to the block of input data.   
+ * @param[out] *pDst     points to the block of output data   
+ * @param[in]  blockSize number of samples to process.   
+ * @return none.   
+ */
+
+void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState;                                 /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *px;                                     /* temporary state pointer */
+  q15_t *pk;                                     /* temporary coefficient pointer */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t fcurnt1, fnext1, gcurnt1 = 0, gnext1;    /* temporary variables for first sample in loop unrolling */
+  q31_t fcurnt2, fnext2, gnext2;                 /* temporary variables for second sample in loop unrolling */
+  q31_t fcurnt3, fnext3, gnext3;                 /* temporary variables for third sample in loop unrolling */
+  q31_t fcurnt4, fnext4, gnext4;                 /* temporary variables for fourth sample in loop unrolling */
+  uint32_t numStages = S->numStages;             /* Number of stages in the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+    /* Read two samples from input buffer */
+    /* f0(n) = x(n) */
+    fcurnt1 = *pSrc++;
+    fcurnt2 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Read g0(n-1) from state */
+    gcurnt1 = *px;
+
+    /* Process first sample for first tap */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+    fnext1 = __SSAT(fnext1, 16);
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (q31_t) ((fcurnt1 * (*pk)) >> 15u) + gcurnt1;
+    gnext1 = __SSAT(gnext1, 16);
+
+    /* Process second sample for first tap */
+    /* for sample 2 processing */
+    fnext2 = (q31_t) ((fcurnt1 * (*pk)) >> 15u) + fcurnt2;
+    fnext2 = __SSAT(fnext2, 16);
+
+    gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + fcurnt1;
+    gnext2 = __SSAT(gnext2, 16);
+
+
+    /* Read next two samples from input buffer */
+    /* f0(n+2) = x(n+2) */
+    fcurnt3 = *pSrc++;
+    fcurnt4 = *pSrc++;
+
+    /* Copy only last input samples into the state buffer   
+       which is used for next four samples processing */
+    *px++ = (q15_t) fcurnt4;
+
+    /* Process third sample for first tap */
+    fnext3 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + fcurnt3;
+    fnext3 = __SSAT(fnext3, 16);
+    gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + fcurnt2;
+    gnext3 = __SSAT(gnext3, 16);
+
+    /* Process fourth sample for first tap */
+    fnext4 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + fcurnt4;
+    fnext4 = __SSAT(fnext4, 16);
+    gnext4 = (q31_t) ((fcurnt4 * (*pk++)) >> 15u) + fcurnt3;
+    gnext4 = __SSAT(gnext4, 16);
+
+    /* Update of f values for next coefficient set processing */
+    fcurnt1 = fnext1;
+    fcurnt2 = fnext2;
+    fcurnt3 = fnext3;
+    fcurnt4 = fnext4;
+
+
+    /* Loop unrolling.  Process 4 taps at a time . */
+    stageCnt = (numStages - 1u) >> 2;
+
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numStages-3 coefficients. */
+
+    /* Process 2nd, 3rd, 4th and 5th taps ... here */
+    while(stageCnt > 0u)
+    {
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurnt1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Process first sample for 2nd, 6th .. tap */
+      /* Sample processing for K2, K6.... */
+      /* f1(n) = f0(n) +  K1 * g0(n-1) */
+      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+      fnext1 = __SSAT(fnext1, 16);
+
+
+      /* Process second sample for 2nd, 6th .. tap */
+      /* for sample 2 processing */
+      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
+      fnext2 = __SSAT(fnext2, 16);
+      /* Process third sample for 2nd, 6th .. tap */
+      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
+      fnext3 = __SSAT(fnext3, 16);
+      /* Process fourth sample for 2nd, 6th .. tap */
+      /* fnext4 = fcurnt4 + (*pk) * gnext3; */
+      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
+      fnext4 = __SSAT(fnext4, 16);
+
+      /* g1(n) = f0(n) * K1  +  g0(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+
+      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+
+      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurnt1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Sample processing for K3, K7.... */
+      /* Process first sample for 3rd, 7th .. tap */
+      /* f3(n) = f2(n) +  K3 * g2(n-1) */
+      fcurnt1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fnext1;
+      fcurnt1 = __SSAT(fcurnt1, 16);
+
+      /* Process second sample for 3rd, 7th .. tap */
+      fcurnt2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fnext2;
+      fcurnt2 = __SSAT(fcurnt2, 16);
+
+      /* Process third sample for 3rd, 7th .. tap */
+      fcurnt3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fnext3;
+      fcurnt3 = __SSAT(fcurnt3, 16);
+
+      /* Process fourth sample for 3rd, 7th .. tap */
+      fcurnt4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fnext4;
+      fcurnt4 = __SSAT(fcurnt4, 16);
+
+      /* Calculation of state values for next stage */
+      /* g3(n) = f2(n) * K3  +  g2(n-1) */
+      gnext4 = (q31_t) ((fnext4 * (*pk)) >> 15u) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+
+      gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15u) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+
+      gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15u) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+
+      gnext1 = (q31_t) ((fnext1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurnt1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Sample processing for K4, K8.... */
+      /* Process first sample for 4th, 8th .. tap */
+      /* f4(n) = f3(n) +  K4 * g3(n-1) */
+      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+      fnext1 = __SSAT(fnext1, 16);
+
+      /* Process second sample for 4th, 8th .. tap */
+      /* for sample 2 processing */
+      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
+      fnext2 = __SSAT(fnext2, 16);
+
+      /* Process third sample for 4th, 8th .. tap */
+      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
+      fnext3 = __SSAT(fnext3, 16);
+
+      /* Process fourth sample for 4th, 8th .. tap */
+      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
+      fnext4 = __SSAT(fnext4, 16);
+
+      /* g4(n) = f3(n) * K4  +  g3(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+
+      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+
+      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurnt1 = *px;
+
+      /* save g4(n) in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Sample processing for K5, K9.... */
+      /* Process first sample for 5th, 9th .. tap */
+      /* f5(n) = f4(n) +  K5 * g4(n-1) */
+      fcurnt1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fnext1;
+      fcurnt1 = __SSAT(fcurnt1, 16);
+
+      /* Process second sample for 5th, 9th .. tap */
+      fcurnt2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fnext2;
+      fcurnt2 = __SSAT(fcurnt2, 16);
+
+      /* Process third sample for 5th, 9th .. tap */
+      fcurnt3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fnext3;
+      fcurnt3 = __SSAT(fcurnt3, 16);
+
+      /* Process fourth sample for 5th, 9th .. tap */
+      fcurnt4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fnext4;
+      fcurnt4 = __SSAT(fcurnt4, 16);
+
+      /* Calculation of state values for next stage */
+      /* g5(n) = f4(n) * K5  +  g4(n-1) */
+      gnext4 = (q31_t) ((fnext4 * (*pk)) >> 15u) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+      gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15u) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+      gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15u) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+      gnext1 = (q31_t) ((fnext1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+      stageCnt--;
+    }
+
+    /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
+    stageCnt = (numStages - 1u) % 0x4u;
+
+    while(stageCnt > 0u)
+    {
+      gcurnt1 = *px;
+
+      /* save g value in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Process four samples for last three taps here */
+      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+      fnext1 = __SSAT(fnext1, 16);
+      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
+      fnext2 = __SSAT(fnext2, 16);
+
+      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
+      fnext3 = __SSAT(fnext3, 16);
+
+      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
+      fnext4 = __SSAT(fnext4, 16);
+
+      /* g1(n) = f0(n) * K1  +  g0(n-1) */
+      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+      /* Update of f values for next coefficient set processing */
+      fcurnt1 = fnext1;
+      fcurnt2 = fnext2;
+      fcurnt3 = fnext3;
+      fcurnt4 = fnext4;
+
+      stageCnt--;
+
+    }
+
+    /* The results in the 4 accumulators, store in the destination buffer. */
+    /* y(n) = fN(n) */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ = __PKHBT(fcurnt1, fcurnt2, 16);
+    *__SIMD32(pDst)++ = __PKHBT(fcurnt3, fcurnt4, 16);
+
+#else
+
+    *__SIMD32(pDst)++ = __PKHBT(fcurnt2, fcurnt1, 16);
+    *__SIMD32(pDst)++ = __PKHBT(fcurnt4, fcurnt3, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurnt1 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g2(n) from state buffer */
+    gcurnt1 = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = (((q31_t) gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+    fnext1 = __SSAT(fnext1, 16);
+
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (((q31_t) fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+    gnext1 = __SSAT(gnext1, 16);
+
+    /* save g1(n) in state buffer */
+    *px++ = (q15_t) fcurnt1;
+
+    /* f1(n) is saved in fcurnt1   
+       for next stage processing */
+    fcurnt1 = fnext1;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g2(n) from state buffer */
+      gcurnt1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q15_t) gnext1;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = (((q31_t) gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+      fnext1 = __SSAT(fnext1, 16);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext1 = (((q31_t) fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+
+      /* f1(n) is saved in fcurnt1   
+         for next stage processing */
+      fcurnt1 = fnext1;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = __SSAT(fcurnt1, 16);
+
+
+    blkCnt--;
+
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t fcurnt, fnext, gcurnt, gnext;            /* temporary variables */
+  uint32_t numStages = S->numStages;             /* Length of the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurnt = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g0(n-1) from state buffer */
+    gcurnt = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext = ((gcurnt * (*pk)) >> 15u) + fcurnt;
+    fnext = __SSAT(fnext, 16);
+
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext = ((fcurnt * (*pk++)) >> 15u) + gcurnt;
+    gnext = __SSAT(gnext, 16);
+
+    /* save f0(n) in state buffer */
+    *px++ = (q15_t) fcurnt;
+
+    /* f1(n) is saved in fcurnt           
+       for next stage processing */
+    fcurnt = fnext;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g1(n-1) from state buffer */
+      gcurnt = *px;
+
+      /* save g0(n-1) in state buffer */
+      *px++ = (q15_t) gnext;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext = ((gcurnt * (*pk)) >> 15u) + fcurnt;
+      fnext = __SSAT(fnext, 16);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext = ((fcurnt * (*pk++)) >> 15u) + gcurnt;
+      gnext = __SSAT(gnext, 16);
+
+
+      /* f1(n) is saved in fcurnt           
+         for next stage processing */
+      fcurnt = fnext;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = __SSAT(fcurnt, 16);
+
+
+    blkCnt--;
+
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR_Lattice group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c
new file mode 100644
index 000000000..99c9a87a1
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c
@@ -0,0 +1,440 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_lattice_q31.c   
+*   
+* Description:	Q31 FIR lattice filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Lattice   
+ * @{   
+ */
+
+
+/**   
+ * @brief Processing function for the Q31 FIR lattice filter.   
+ * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.   
+ * @param[in]  *pSrc     points to the block of input data.   
+ * @param[out] *pDst     points to the block of output data   
+ * @param[in]  blockSize number of samples to process.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ * In order to avoid overflows the input signal must be scaled down by 2*log2(numStages) bits.   
+ */
+
+void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState;                                 /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *px;                                     /* temporary state pointer */
+  q31_t *pk;                                     /* temporary coefficient pointer */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t fcurr1, fnext1, gcurr1 = 0, gnext1;      /* temporary variables for first sample in loop unrolling */
+  q63_t fcurr2, fnext2, gnext2;                  /* temporary variables for second sample in loop unrolling */
+  q63_t fcurr3, fnext3, gnext3;                  /* temporary variables for third sample in loop unrolling */
+  q63_t fcurr4, fnext4, gnext4;                  /* temporary variables for fourth sample in loop unrolling */
+  uint32_t numStages = S->numStages;             /* Length of the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+    /* Read two samples from input buffer */
+    /* f0(n) = x(n) */
+    fcurr1 = *pSrc++;
+    /* f0(n) = x(n) */
+    fcurr2 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Read g0(n-1) from state */
+    gcurr1 = *px;
+
+    /* Process first sample for first tap */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = (q31_t) (((q63_t) gcurr1 * (*pk)) >> 31) + fcurr1;
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 31) + gcurr1;
+
+    /* Process second sample for first tap */
+    /* for sample 2 processing */
+    fnext2 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 31) + fcurr2;
+    gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 31) + fcurr1;
+
+
+    /* Read next two samples from input buffer */
+    /* f0(n+2) = x(n+2) */
+    fcurr3 = *pSrc++;
+    fcurr4 = *pSrc++;
+
+    /* Copy only last input samples into the state buffer   
+       which will be used for next four samples processing */
+    *px++ = (q31_t) fcurr4;
+
+    /* Process third sample for first tap */
+    fnext3 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 31) + fcurr3;
+    gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 31) + fcurr2;
+
+    /* Process fourth sample for first tap */
+    fnext4 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 31) + fcurr4;
+    gnext4 = (q31_t) (((q63_t) fcurr4 * (*pk++)) >> 31) + fcurr3;
+
+    /* save g1(n) in state buffer for next sample processing */
+    /* *px++ = gnext4;       */
+
+    /* Update of f values for next coefficient set processing */
+    fcurr1 = fnext1;
+    fcurr2 = fnext2;
+    fcurr3 = fnext3;
+    fcurr4 = fnext4;
+
+
+    /* Loop unrolling.  Process 4 taps at a time . */
+    stageCnt = (numStages - 1u) >> 2u;
+
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numStages-3 coefficients. */
+
+    /* Process 2nd, 3rd, 4th and 5th taps ... here */
+    while(stageCnt > 0u)
+    {
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q31_t) gnext4;
+
+      /* Process first sample for 2nd, 6th .. tap */
+      /* Sample processing for K2, K6.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = (q31_t) (((q63_t) gcurr1 * (*pk)) >> 31) + fcurr1;
+      /* Process second sample for 2nd, 6th .. tap */
+      /* for sample 2 processing */
+      fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 31) + fcurr2;
+      /* Process third sample for 2nd, 6th .. tap */
+      fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 31) + fcurr3;
+      /* Process fourth sample for 2nd, 6th .. tap */
+      fnext4 = (q31_t) (((q63_t) gnext3 * (*pk)) >> 31) + fcurr4;
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (q31_t) (((q63_t) fcurr4 * (*pk)) >> 31) + gnext3;
+      gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 31) + gnext2;
+      gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 31) + gnext1;
+      gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk++)) >> 31) + gcurr1;
+
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g2(n) in state buffer */
+      *px++ = (q31_t) gnext4;
+
+      /* Sample processing for K3, K7.... */
+      /* Process first sample for 3rd, 7th .. tap */
+      /* f3(n) = f2(n) +  K3 * g2(n-1) */
+      fcurr1 = (q31_t) (((q63_t) gcurr1 * (*pk)) >> 31) + fnext1;
+      /* Process second sample for 3rd, 7th .. tap */
+      fcurr2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 31) + fnext2;
+      /* Process third sample for 3rd, 7th .. tap */
+      fcurr3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 31) + fnext3;
+      /* Process fourth sample for 3rd, 7th .. tap */
+      fcurr4 = (q31_t) (((q63_t) gnext3 * (*pk)) >> 31) + fnext4;
+
+      /* Calculation of state values for next stage */
+      /*  gnext4 = fnext4 * (*pk) +  gnext3; */
+      gnext4 = (q31_t) (((q63_t) fnext4 * (*pk)) >> 31) + gnext3;
+      gnext3 = (q31_t) (((q63_t) fnext3 * (*pk)) >> 31) + gnext2;
+      /*  gnext2 = fnext2 * (*pk) +  gnext1; */
+      gnext2 = (q31_t) (((q63_t) fnext2 * (*pk)) >> 31) + gnext1;
+
+      /* g1(n) = f0(n) * K1  +  g0(n-1) */
+      /*  gnext1 = fnext1 * (*pk++) +  gcurr1; */
+      gnext1 = (q31_t) (((q63_t) fnext1 * (*pk++)) >> 31) + gcurr1;
+
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q31_t) gnext4;
+
+      /* Sample processing for K4, K8.... */
+      /* Process first sample for 4th, 8th .. tap */
+      /* f4(n) = f3(n) +  K4 * g3(n-1) */
+      fnext1 = (q31_t) (((q63_t) gcurr1 * (*pk)) >> 31) + fcurr1;
+      /* Process second sample for 4th, 8th .. tap */
+      /* for sample 2 processing */
+      fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 31) + fcurr2;
+      /* Process third sample for 4th, 8th .. tap */
+      fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 31) + fcurr3;
+      /* Process fourth sample for 4th, 8th .. tap */
+      fnext4 = (q31_t) (((q63_t) gnext3 * (*pk)) >> 31) + fcurr4;
+
+      /* g4(n) = f3(n) * K4  +  g3(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (q31_t) (((q63_t) fcurr4 * (*pk)) >> 31) + gnext3;
+      gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 31) + gnext2;
+      gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 31) + gnext1;
+      gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk++)) >> 31) + gcurr1;
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g4(n) in state buffer */
+      *px++ = (q31_t) gnext4;
+
+      /* Sample processing for K5, K9.... */
+      /* Process first sample for 5th, 9th .. tap */
+      /* f5(n) = f4(n) +  K5 * g4(n-1) */
+      fcurr1 = (q31_t) (((q63_t) gcurr1 * (*pk)) >> 31) + fnext1;
+      /* Process second sample for 5th, 9th .. tap */
+      fcurr2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 31) + fnext2;
+      /* Process third sample for 5th, 9th .. tap */
+      fcurr3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 31) + fnext3;
+      /* Process fourth sample for 5th, 9th .. tap */
+      fcurr4 = (q31_t) (((q63_t) gnext3 * (*pk)) >> 31) + fnext4;
+
+      /* Calculation of state values for next stage */
+      /* g5(n) = f4(n) * K5  +  g4(n-1) */
+      gnext4 = (q31_t) (((q63_t) fnext4 * (*pk)) >> 31) + gnext3;
+      gnext3 = (q31_t) (((q63_t) fnext3 * (*pk)) >> 31) + gnext2;
+      gnext2 = (q31_t) (((q63_t) fnext2 * (*pk)) >> 31) + gnext1;
+      gnext1 = (q31_t) (((q63_t) fnext1 * (*pk++)) >> 31) + gcurr1;
+
+      stageCnt--;
+    }
+
+    /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
+    stageCnt = (numStages - 1u) % 0x4u;
+
+    while(stageCnt > 0u)
+    {
+      gcurr1 = *px;
+
+      /* save g value in state buffer */
+      *px++ = (q31_t) gnext4;
+
+      /* Process four samples for last three taps here */
+      fnext1 = (q31_t) (((q63_t) gcurr1 * (*pk)) >> 31) + fcurr1;
+      fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 31) + fcurr2;
+      fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 31) + fcurr3;
+      fnext4 = (q31_t) (((q63_t) gnext3 * (*pk)) >> 31) + fcurr4;
+
+      /* g1(n) = f0(n) * K1  +  g0(n-1) */
+      gnext4 = (q31_t) (((q63_t) fcurr4 * (*pk)) >> 31) + gnext3;
+      gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 31) + gnext2;
+      gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 31) + gnext1;
+      gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk++)) >> 31) + gcurr1;
+
+      /* Update of f values for next coefficient set processing */
+      fcurr1 = fnext1;
+      fcurr2 = fnext2;
+      fcurr3 = fnext3;
+      fcurr4 = fnext4;
+
+      stageCnt--;
+
+    }
+
+    /* The results in the 4 accumulators, store in the destination buffer. */
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr1;
+    *pDst++ = (q31_t) fcurr2;
+    *pDst++ = (q31_t) fcurr3;
+    *pDst++ = (q31_t) fcurr4;
+
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurr1 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g2(n) from state buffer */
+    gcurr1 = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = (q31_t) (((q63_t) gcurr1 * (*pk)) >> 31) + fcurr1;
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk++)) >> 31) + gcurr1;
+    /* save g1(n) in state buffer */
+    *px++ = fcurr1;
+
+    /* f1(n) is saved in fcurr1   
+       for next stage processing */
+    fcurr1 = fnext1;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g2(n) from state buffer */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext1;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = (q31_t) (((q63_t) gcurr1 * (*pk)) >> 31) + fcurr1;
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk++)) >> 31) + gcurr1;
+
+      /* f1(n) is saved in fcurr1   
+         for next stage processing */
+      fcurr1 = fnext1;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr1;
+
+    blkCnt--;
+
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q31_t fcurr, fnext, gcurr, gnext;              /* temporary variables */
+  uint32_t numStages = S->numStages;             /* Length of the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g0(n-1) from state buffer */
+    gcurr = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;
+    /* save g1(n) in state buffer */
+    *px++ = fcurr;
+
+    /* f1(n) is saved in fcurr1           
+       for next stage processing */
+    fcurr = fnext;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g2(n) from state buffer */
+      gcurr = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;
+
+      /* f1(n) is saved in fcurr1           
+         for next stage processing */
+      fcurr = fnext;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr;
+
+    blkCnt--;
+
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR_Lattice group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c
new file mode 100644
index 000000000..ea011d50f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c
@@ -0,0 +1,368 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_q15.c   
+*   
+* Description:  Q15 FIR filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q15 FIR filter.   
+ * @param[in] *S points to an instance of the Q15 FIR structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in]  blockSize number of samples to process per call.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.   
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.   
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.   
+ *   
+ * \par   
+ * Refer to the function arm_fir_fast_q15() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *px1;                                    /* Temporary q15 pointer for state buffer */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q31_t *px2;                                    /* Temporary q31 pointer for SIMD state buffer accesses */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold SIMD state and coefficient values */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.   
+   * The variables acc0 ... acc3 hold output values that are being computed:   
+   *   
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]   
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]   
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]   
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]   
+   */
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer.   
+     ** Use 32-bit SIMD to move the 16-bit data.  Only requires two copies. */
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Initialize state pointer of type q15 */
+    px1 = pState;
+
+    /* Initialize coeff pointer of type q31 */
+    pb = (q31_t *) (pCoeffs);
+
+    /* Read the first two samples from the state buffer:  x[n-N], x[n-N-1] */
+    x0 = *(q31_t *) (px1++);
+
+    /* Read the third and forth samples from the state buffer: x[n-N-1], x[n-N-2] */
+    x1 = *(q31_t *) (px1++);
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    tapCnt = numTaps >> 2;
+    do
+    {
+      /* Read the first two coefficients using SIMD:  b[N] and b[N-1] coefficients */
+      c0 = *(pb++);
+
+      /* acc0 +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+      acc0 = __SMLALD(x0, c0, acc0);
+
+      /* acc1 +=  b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
+      acc1 = __SMLALD(x1, c0, acc1);
+
+      /* Read state x[n-N-2], x[n-N-3] */
+      x2 = *(q31_t *) (px1++);
+
+      /* Read state x[n-N-3], x[n-N-4] */
+      x3 = *(q31_t *) (px1++);
+
+      /* acc2 +=  b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
+      acc2 = __SMLALD(x2, c0, acc2);
+
+      /* acc3 +=  b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
+      acc3 = __SMLALD(x3, c0, acc3);
+
+      /* Read coefficients b[N-2], b[N-3] */
+      c0 = *(pb++);
+
+      /* acc0 +=  b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
+      acc0 = __SMLALD(x2, c0, acc0);
+
+      /* acc1 +=  b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
+      acc1 = __SMLALD(x3, c0, acc1);
+
+      /* Read state x[n-N-4], x[n-N-5] */
+      x0 = *(q31_t *) (px1++);
+
+      /* Read state x[n-N-5], x[n-N-6] */
+      x1 = *(q31_t *) (px1++);
+
+      /* acc2 +=  b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
+      acc2 = __SMLALD(x0, c0, acc2);
+
+      /* acc3 +=  b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
+      acc3 = __SMLALD(x1, c0, acc3);
+      tapCnt--;
+
+    }
+    while(tapCnt > 0u);
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps.   
+     ** This is always be 2 taps since the filter length is even. */
+    if((numTaps & 0x3u) != 0u)
+    {
+      /* Read 2 coefficients */
+      c0 = *(pb++);
+      /* Fetch 4 state variables */
+      x2 = *(q31_t *) (px1++);
+      x3 = *(q31_t *) (px1++);
+
+      /* Perform the multiply-accumulates */
+      acc0 = __SMLALD(x0, c0, acc0);
+      acc1 = __SMLALD(x1, c0, acc1);
+      acc2 = __SMLALD(x2, c0, acc2);
+      acc3 = __SMLALD(x3, c0, acc3);
+    }
+
+    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.15 with saturation.   
+     ** Then store the 4 outputs in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+  while(blkCnt > 0u)
+  {
+    /* Copy two samples into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Use SIMD to hold states and coefficients */
+    px2 = (q31_t *) pState;
+    pb = (q31_t *) (pCoeffs);
+    tapCnt = numTaps >> 1;
+
+    do
+    {
+      acc0 = __SMLALD(*px2++, *(pb++), acc0);
+      tapCnt--;
+    }
+    while(tapCnt > 0u);
+
+    /* The result is in 2.30 format.  Convert to 1.15 with saturation.   
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1u) >> 2;
+
+  while(tapCnt > 0u)
+  {
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    tapCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* copy remaining data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q63_t acc;                                     /* Accumulator */
+  uint32_t numTaps = S->numTaps;                 /* Number of nTaps in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Initialize blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = pCoeffs;
+
+    tapCnt = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+      acc += (q31_t) * px++ * *pb++;
+      tapCnt--;
+    } while(tapCnt > 0u);
+
+    /* The result is in 2.30 format.  Convert to 1.15        
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q15_t) __SSAT((acc >> 15u), 16);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy numTaps number of values */
+  tapCnt = (numTaps - 1u);
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c
new file mode 100644
index 000000000..0891a7631
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c
@@ -0,0 +1,383 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_q31.c   
+*   
+* Description:	Q31 FIR filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in] blockSize number of samples to process per call.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around rather than clip.   
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.   
+ * After all multiply-accumulates are performed, the 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. 
+ *   
+ * \par   
+ * Refer to the function arm_fir_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t x0, x1, x2, x3;                          /* Temporary variables to hold state */
+  q31_t c0;                                      /* Temporary variable to hold coefficient value */
+  q31_t *px;                                     /* Temporary pointer for state */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.   
+   * The variables acc0 ... acc3 hold output values that are being computed:   
+   *   
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]   
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]   
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]   
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]   
+   */
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Read the first three samples from the state buffer:   
+     *  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+    x0 = *(px++);
+    x1 = *(px++);
+    x2 = *(px++);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+    i = tapCnt;
+
+    while(i > 0u)
+    {
+      /* Read the b[numTaps] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x3 = *(px++);
+
+      /* acc0 +=  b[numTaps] * x[n-numTaps] */
+      acc0 += ((q63_t) x0 * c0);
+
+      /* acc1 +=  b[numTaps] * x[n-numTaps-1] */
+      acc1 += ((q63_t) x1 * c0);
+
+      /* acc2 +=  b[numTaps] * x[n-numTaps-2] */
+      acc2 += ((q63_t) x2 * c0);
+
+      /* acc3 +=  b[numTaps] * x[n-numTaps-3] */
+      acc3 += ((q63_t) x3 * c0);
+
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q63_t) x1 * c0);
+      acc1 += ((q63_t) x2 * c0);
+      acc2 += ((q63_t) x3 * c0);
+      acc3 += ((q63_t) x0 * c0);
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-5] sample */
+      x1 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q63_t) x2 * c0);
+      acc1 += ((q63_t) x3 * c0);
+      acc2 += ((q63_t) x0 * c0);
+      acc3 += ((q63_t) x1 * c0);
+      /* Read the b[numTaps-3] coefficients */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-6] sample */
+      x2 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q63_t) x3 * c0);
+      acc1 += ((q63_t) x0 * c0);
+      acc2 += ((q63_t) x1 * c0);
+      acc3 += ((q63_t) x2 * c0);
+      i--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+
+    i = numTaps - (tapCnt * 4u);
+    while(i > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x3 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q63_t) x0 * c0);
+      acc1 += ((q63_t) x1 * c0);
+      acc2 += ((q63_t) x2 * c0);
+      acc3 += ((q63_t) x3 * c0);
+
+      /* Reuse the present sample states for next sample */
+      x0 = x1;
+      x1 = x2;
+      x2 = x3;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* The results in the 4 accumulators are in 2.62 format.  Convert to 1.31   
+     ** Then store the 4 outputs in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 >> 31u);
+    *pDst++ = (q31_t) (acc1 >> 31u);
+    *pDst++ = (q31_t) (acc2 >> 31u);
+    *pDst++ = (q31_t) (acc3 >> 31u);
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = (pCoeffs);
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      acc0 += (q63_t) * (px++) * (*(pb++));
+      i--;
+    } while(i > 0u);
+
+    /* The result is in 2.62 format.  Convert to 1.31   
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 >> 31u);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q31_t *px;                                     /* Temporary pointer for state */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q63_t acc;                                     /* Accumulator */
+  uint32_t numTaps = S->numTaps;                 /* Length of the filter */
+  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Initialize blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = pCoeffs;
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+      acc += (q63_t) * px++ * *pb++;
+      i--;
+    } while(i > 0u);
+
+    /* The result is in 2.62 format.  Convert to 1.31        
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q31_t) (acc >> 31u);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last numTaps - 1 samples to the starting of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy numTaps number of values */
+  tapCnt = numTaps - 1u;
+
+  /* Copy the data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+
+#endif /*  #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c
new file mode 100644
index 000000000..42529d095
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c
@@ -0,0 +1,385 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_q7.c   
+*   
+* Description:  Q7 FIR filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ * @param[in]   *S points to an instance of the Q7 FIR filter structure.   
+ * @param[in]   *pSrc points to the block of input data.   
+ * @param[out]  *pDst points to the block of output data.   
+ * @param[in]   blockSize number of samples to process per call.   
+ * @return 	none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 32-bit internal accumulator.   
+ * Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.   
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.   
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.   
+ * The accumulator is converted to 18.7 format by discarding the low 7 bits.   
+ * Finally, the result is truncated to 1.7 format.   
+ */
+
+void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t *pState = S->pState;                      /* State pointer */
+  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */
+  q7_t *pStateCurnt;                             /* Points to the current sample of the state */
+  q7_t x0, x1, x2, x3;                           /* Temporary variables to hold state */
+  q7_t c0;                                       /* Temporary variable to hold coefficient value */
+  q7_t *px;                                      /* Temporary pointer for state */
+  q7_t *pb;                                      /* Temporary pointer for coefficient buffer */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.   
+   * The variables acc0 ... acc3 hold output values that are being computed:   
+   *   
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]   
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]   
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]   
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]   
+   */
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Read the first three samples from the state buffer:   
+     *  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+    x0 = *(px++);
+    x1 = *(px++);
+    x2 = *(px++);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+    i = tapCnt;
+
+    while(i > 0u)
+    {
+      /* Read the b[numTaps] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x3 = *(px++);
+
+      /* acc0 +=  b[numTaps] * x[n-numTaps] */
+      acc0 += ((q15_t) x0 * c0);
+
+      /* acc1 +=  b[numTaps] * x[n-numTaps-1] */
+      acc1 += ((q15_t) x1 * c0);
+
+      /* acc2 +=  b[numTaps] * x[n-numTaps-2] */
+      acc2 += ((q15_t) x2 * c0);
+
+      /* acc3 +=  b[numTaps] * x[n-numTaps-3] */
+      acc3 += ((q15_t) x3 * c0);
+
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q15_t) x1 * c0);
+      acc1 += ((q15_t) x2 * c0);
+      acc2 += ((q15_t) x3 * c0);
+      acc3 += ((q15_t) x0 * c0);
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-5] sample */
+      x1 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q15_t) x2 * c0);
+      acc1 += ((q15_t) x3 * c0);
+      acc2 += ((q15_t) x0 * c0);
+      acc3 += ((q15_t) x1 * c0);
+      /* Read the b[numTaps-3] coefficients */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-6] sample */
+      x2 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q15_t) x3 * c0);
+      acc1 += ((q15_t) x0 * c0);
+      acc2 += ((q15_t) x1 * c0);
+      acc3 += ((q15_t) x2 * c0);
+      i--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+
+    i = numTaps - (tapCnt * 4u);
+    while(i > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x3 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q15_t) x0 * c0);
+      acc1 += ((q15_t) x1 * c0);
+      acc2 += ((q15_t) x2 * c0);
+      acc3 += ((q15_t) x3 * c0);
+
+      /* Reuse the present sample states for next sample */
+      x0 = x1;
+      x1 = x2;
+      x2 = x3;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* The results in the 4 accumulators are in 2.62 format.  Convert to 1.31   
+     ** Then store the 4 outputs in the destination buffer. */
+    acc0 = __SSAT((acc0 >> 7u), 8);
+    *pDst++ = acc0;
+    acc1 = __SSAT((acc1 >> 7u), 8);
+    *pDst++ = acc1;
+    acc2 = __SSAT((acc2 >> 7u), 8);
+    *pDst++ = acc2;
+    acc3 = __SSAT((acc3 >> 7u), 8);
+    *pDst++ = acc3;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = (pCoeffs);
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      acc0 += (q15_t) * (px++) * (*(pb++));
+      i--;
+    } while(i > 0u);
+
+    /* The result is in 2.14 format.  Convert to 1.7   
+     ** Then store the output in the destination buffer. */
+    *pDst++ = __SSAT((acc0 >> 7u), 8);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
+  uint32_t i, blkCnt;                            /* Loop counters */
+  q7_t *pState = S->pState;                      /* State pointer */
+  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */
+  q7_t *px, *pb;                                 /* Temporary pointers to state and coeff */
+  q31_t acc = 0;                                 /* Accumlator */
+  q7_t *pStateCurnt;                             /* Points to the current sample of the state */
+
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Initialize blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  /* Perform filtering upto BlockSize - BlockSize%4  */
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set accumulator to zero */
+    acc = 0;
+
+    /* Initialize state pointer of type q7 */
+    px = pState;
+
+    /* Initialize coeff pointer of type q7 */
+    pb = pCoeffs;
+
+
+    i = numTaps;
+
+    while(i > 0u)
+    {
+      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+      acc += (q15_t) * px++ * *pb++;
+      i--;
+    }
+
+    /* Store the 1.7 format filter output in destination buffer */
+    *pDst++ = (q7_t) __SSAT((acc >> 7), 8);
+
+    /* Advance the state pointer by 1 to process the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+
+  /* Copy numTaps number of values */
+  i = (numTaps - 1u);
+
+  /* Copy q7_t data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    i--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c
new file mode 100644
index 000000000..aaede629a
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c
@@ -0,0 +1,362 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_sparse_f32.c   
+*   
+* Description:	Floating-point sparse FIR filter processing function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup FIR_Sparse Finite Impulse Response (FIR) Sparse Filters   
+ *   
+ * This group of functions implements sparse FIR filters.    
+ * Sparse FIR filters are equivalent to standard FIR filters except that most of the coefficients are equal to zero.  
+ * Sparse filters are used for simulating reflections in communications and audio applications.  
+ *  
+ * There are separate functions for Q7, Q15, Q31, and floating-point data types.   
+ * The functions operate on blocks  of input and output data and each call to the function processes   
+ * blockSize samples through the filter.  pSrc and   
+ * pDst points to input and output arrays respectively containing blockSize values.   
+ *   
+ * \par Algorithm:   
+ * The sparse filter instant structure contains an array of tap indices pTapDelay which specifies the locations of the non-zero coefficients.  
+ * This is in addition to the coefficient array b.  
+ * The implementation essentially skips the multiplications by zero and leads to an efficient realization.  
+ * 
  
+ *     y[n] = b[0] * x[n-pTapDelay[0]] + b[1] * x[n-pTapDelay[1]] + b[2] * x[n-pTapDelay[2]] + ...+ b[numTaps-1] * x[n-pTapDelay[numTaps-1]]   
+ * 
   
+ * \par   
+ * \image html FIRSparse.gif "Sparse FIR filter.  b[n] represents the filter coefficients"  
+ * \par   
+ * pCoeffs points to a coefficient array of size numTaps;   
+ * pTapDelay points to an array of nonzero indices and is also of size numTaps;  
+ * pState points to a state array of size maxDelay + blockSize, where  
+ * maxDelay is the largest offset value that is ever used in the pTapDelay array.  
+ * Some of the processing functions also require temporary working buffers.  
+ *  
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient and offset arrays may be shared among several instances while state variable arrays cannot be shared.   
+ * There are separate instance structure declarations for each of the 4 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ *   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Set the values in the state buffer to zeros before static initialization.   
+ * The code below statically initializes each of the 4 different data type filter instance structures   
+ * 
   
+ *arm_fir_sparse_instance_f32 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};   
+ *arm_fir_sparse_instance_q31 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};   
+ *arm_fir_sparse_instance_q15 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};   
+ *arm_fir_sparse_instance_q7 S =  {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};   
+ * 
   
+ * \par   
+ *   
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the sparse FIR filter functions.   
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+/**   
+ * @addtogroup FIR_Sparse   
+ * @{   
+ */
+
+/**  
+ * @brief Processing function for the floating-point sparse FIR filter.  
+ * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.  
+ * @param[in]  *pSrc       points to the block of input data.  
+ * @param[out] *pDst       points to the block of output data  
+ * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.  
+ * @param[in]  blockSize   number of input samples to process per call.  
+ * @return none.  
+ */
+
+void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize)
+{
+
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *px;                                 /* Scratch buffer pointer */
+  float32_t *py = pState;                        /* Temporary pointers for state buffer */
+  float32_t *pb = pScratchIn;                    /* Temporary pointers for scratch buffer */
+  float32_t *pOut;                               /* Destination pointer */
+  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
+  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
+  uint16_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter  */
+  int32_t readIndex;                             /* Read index of the state buffer */
+  uint32_t tapCnt, blkCnt;                       /* loop counters */
+  float32_t coeff = *pCoeffs++;                  /* Read the first coefficient value */
+
+
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
+                        (int32_t *) pSrc, 1, blockSize);
+
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                       (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                       blockSize);
+
+  /* Working pointer for the scratch buffer */
+  px = pb;
+
+  /* Working pointer for destination buffer */
+  pOut = pDst;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Loop over the blockSize. Unroll by a factor of 4.   
+   * Compute 4 Multiplications at a time. */
+  blkCnt = blockSize >> 2u;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in destination buffer */
+    *pOut++ = *px++ * coeff;
+    *pOut++ = *px++ * coeff;
+    *pOut++ = *px++ * coeff;
+    *pOut++ = *px++ * coeff;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,   
+   * compute the remaining samples */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in destination buffer */
+    *pOut++ = *px++ * coeff;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and   
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                         blockSize);
+
+    /* Working pointer for the scratch buffer */
+    px = pb;
+
+    /* Working pointer for destination buffer */
+    pOut = pDst;
+
+    /* Loop over the blockSize. Unroll by a factor of 4.   
+     * Compute 4 MACS at a time. */
+    blkCnt = blockSize >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pOut++ += *px++ * coeff;
+      *pOut++ += *px++ * coeff;
+      *pOut++ += *px++ * coeff;
+      *pOut++ += *px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4,   
+     * compute the remaining samples */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pOut++ += *px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and   
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = ((int32_t) S->stateIndex -
+                 (int32_t) blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in destination buffer */
+    *pOut++ = *px++ * coeff;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and          
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                         blockSize);
+
+    /* Working pointer for the scratch buffer */
+    px = pb;
+
+    /* Working pointer for destination buffer */
+    pOut = pDst;
+
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pOut++ += *px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and          
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex =
+      ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0        */
+
+}
+
+/**   
+ * @} end of FIR_Sparse group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c
new file mode 100644
index 000000000..3e423a1bf
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c
@@ -0,0 +1,99 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_sparse_init_f32.c   
+*   
+* Description:	Floating-point sparse FIR filter initialization function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Sparse   
+ * @{   
+ */
+
+/**  
+ * @brief  Initialization function for the floating-point sparse FIR filter.  
+ * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.  
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.  
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.  
+ * @param[in]     *pState    points to the state buffer.  
+ * @param[in]     *pTapDelay points to the array of offset times.  
+ * @param[in]     maxDelay   maximum offset time supported.  
+ * @param[in]     blockSize  number of samples that will be processed per block.  
+ * @return none  
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs holds the filter coefficients and has length numTaps.   
+ * pState holds the filter's state variables and must be of length   
+ * maxDelay + blockSize, where maxDelay   
+ * is the maximum number of delay line values.   
+ * blockSize is the   
+ * number of samples processed by the arm_fir_sparse_f32() function.   
+ */
+
+void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Assign TapDelay pointer */
+  S->pTapDelay = pTapDelay;
+
+  /* Assign MaxDelay */
+  S->maxDelay = maxDelay;
+
+  /* reset the stateIndex to 0 */
+  S->stateIndex = 0u;
+
+  /* Clear state buffer and size is always maxDelay + blockSize */
+  memset(pState, 0, (maxDelay + blockSize) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR_Sparse group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c
new file mode 100644
index 000000000..196b45eec
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c
@@ -0,0 +1,99 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_sparse_init_q15.c   
+*   
+* Description:	Q15 sparse FIR filter initialization function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Sparse   
+ * @{   
+ */
+
+/**  
+ * @brief  Initialization function for the Q15 sparse FIR filter.  
+ * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.  
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.  
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.  
+ * @param[in]     *pState    points to the state buffer.  
+ * @param[in]     *pTapDelay points to the array of offset times.  
+ * @param[in]     maxDelay   maximum offset time supported.  
+ * @param[in]     blockSize  number of samples that will be processed per block.  
+ * @return none  
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs holds the filter coefficients and has length numTaps.   
+ * pState holds the filter's state variables and must be of length   
+ * maxDelay + blockSize, where maxDelay   
+ * is the maximum number of delay line values.   
+ * blockSize is the   
+ * number of words processed by arm_fir_sparse_q15() function.   
+ */
+
+void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Assign TapDelay pointer */
+  S->pTapDelay = pTapDelay;
+
+  /* Assign MaxDelay */
+  S->maxDelay = maxDelay;
+
+  /* reset the stateIndex to 0 */
+  S->stateIndex = 0u;
+
+  /* Clear state buffer and size is always maxDelay + blockSize */
+  memset(pState, 0, (maxDelay + blockSize) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR_Sparse group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c
new file mode 100644
index 000000000..7d1f35d13
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c
@@ -0,0 +1,98 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_sparse_init_q31.c   
+*   
+* Description:	Q31 sparse FIR filter initialization function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Sparse   
+ * @{   
+ */
+
+/**  
+ * @brief  Initialization function for the Q31 sparse FIR filter.  
+ * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.  
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.  
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.  
+ * @param[in]     *pState    points to the state buffer.  
+ * @param[in]     *pTapDelay points to the array of offset times.  
+ * @param[in]     maxDelay   maximum offset time supported.  
+ * @param[in]     blockSize  number of samples that will be processed per block.  
+ * @return none  
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs holds the filter coefficients and has length numTaps.   
+ * pState holds the filter's state variables and must be of length   
+ * maxDelay + blockSize, where maxDelay   
+ * is the maximum number of delay line values.   
+ * blockSize is the number of words processed by arm_fir_sparse_q31() function.   
+ */
+
+void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Assign TapDelay pointer */
+  S->pTapDelay = pTapDelay;
+
+  /* Assign MaxDelay */
+  S->maxDelay = maxDelay;
+
+  /* reset the stateIndex to 0 */
+  S->stateIndex = 0u;
+
+  /* Clear state buffer and size is always maxDelay + blockSize */
+  memset(pState, 0, (maxDelay + blockSize) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR_Sparse group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c
new file mode 100644
index 000000000..c93d6a2c2
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c
@@ -0,0 +1,99 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_sparse_init_q7.c   
+*   
+* Description:	Q7 sparse FIR filter initialization function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Sparse   
+ * @{   
+ */
+
+/**  
+ * @brief  Initialization function for the Q7 sparse FIR filter.  
+ * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.  
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.  
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.  
+ * @param[in]     *pState    points to the state buffer.  
+ * @param[in]     *pTapDelay points to the array of offset times.  
+ * @param[in]     maxDelay   maximum offset time supported.  
+ * @param[in]     blockSize  number of samples that will be processed per block.  
+ * @return none  
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs holds the filter coefficients and has length numTaps.   
+ * pState holds the filter's state variables and must be of length   
+ * maxDelay + blockSize, where maxDelay   
+ * is the maximum number of delay line values.   
+ * blockSize is the   
+ * number of samples processed by the arm_fir_sparse_q7() function.   
+ */
+
+void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Assign TapDelay pointer */
+  S->pTapDelay = pTapDelay;
+
+  /* Assign MaxDelay */
+  S->maxDelay = maxDelay;
+
+  /* reset the stateIndex to 0 */
+  S->stateIndex = 0u;
+
+  /* Clear state buffer and size is always maxDelay + blockSize */
+  memset(pState, 0, (maxDelay + blockSize) * sizeof(q7_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR_Sparse group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c
new file mode 100644
index 000000000..28abfa52c
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c
@@ -0,0 +1,403 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_sparse_q15.c   
+*   
+* Description:	Q15 sparse FIR filter processing function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**   
+ * @addtogroup FIR_Sparse   
+ * @{   
+ */
+
+/**  
+ * @brief Processing function for the Q15 sparse FIR filter.  
+ * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.  
+ * @param[in]  *pSrc        points to the block of input data.  
+ * @param[out] *pDst        points to the block of output data  
+ * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.  
+ * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.  
+ * @param[in]  blockSize    number of input samples to process per call.  
+ * @return none.  
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 32-bit accumulator.  
+ * The 1.15 x 1.15 multiplications yield a 2.30 result and these are added to a 2.30 accumulator.  
+ * Thus the full precision of the multiplications is maintained but there is only a single guard bit in the accumulator.  
+ * If the accumulator result overflows it will wrap around rather than saturate.  
+ * After all multiply-accumulates are performed, the 2.30 accumulator is truncated to 2.15 format and then saturated to 1.15 format.   
+ * In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.  
+ */
+
+
+void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize)
+{
+
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pIn = pSrc;                             /* Working pointer for input */
+  q15_t *pOut = pDst;                            /* Working pointer for output */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *px;                                     /* Temporary pointers for scratch buffer */
+  q15_t *pb = pScratchIn;                        /* Temporary pointers for scratch buffer */
+  q15_t *py = pState;                            /* Temporary pointers for state buffer */
+  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
+  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
+  uint16_t numTaps = S->numTaps;                 /* Filter order */
+  int32_t readIndex;                             /* Read index of the state buffer */
+  uint32_t tapCnt, blkCnt;                       /* loop counters */
+  q15_t coeff = *pCoeffs++;                      /* Read the first coefficient value */
+  q31_t *pScr2 = pScratchOut;                    /* Working pointer for pScratchOut */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in1, in2;                                /* Temporary variables */
+
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);
+
+  /* Loop over the number of taps. */
+  tapCnt = numTaps;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_q15(py, delaySize, &readIndex, 1,
+                       pb, pb, blockSize, 1, blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pScratchOut = pScr2;
+
+  /* Loop over the blockSize. Unroll by a factor of 4.   
+   * Compute 4 multiplications at a time. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,   
+   * compute the remaining samples */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and   
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_q15(py, delaySize, &readIndex, 1,
+                         pb, pb, blockSize, 1, blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pScratchOut = pScr2;
+
+    /* Loop over the blockSize. Unroll by a factor of 4.   
+     * Compute 4 MACS at a time. */
+    blkCnt = blockSize >> 2;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4,   
+     * compute the remaining samples */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and   
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+  /* All the output values are in pScratchOut buffer.   
+     Convert them into 1.15 format, saturate and store in the destination buffer. */
+  /* Loop over the blockSize. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    in1 = *pScr2++;
+    in2 = *pScr2++;
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pOut)++ =
+      __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16),
+              16);
+
+#else
+    *__SIMD32(pOut)++ =
+      __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16),
+              16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    in1 = *pScr2++;
+
+    in2 = *pScr2++;
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pOut)++ =
+      __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16),
+              16);
+
+#else
+
+    *__SIMD32(pOut)++ =
+      __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16),
+              16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+
+    blkCnt--;
+
+  }
+
+  /* If the blockSize is not a multiple of 4,   
+     remaining samples are processed in the below loop */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);
+
+  /* Loop over the number of taps. */
+  tapCnt = numTaps;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_q15(py, delaySize, &readIndex, 1,
+                       pb, pb, blockSize, 1, blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pScratchOut = pScr2;
+
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and          
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_q15(py, delaySize, &readIndex, 1,
+                         pb, pb, blockSize, 1, blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pScratchOut = pScr2;
+
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and          
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+  /* All the output values are in pScratchOut buffer.      
+     Convert them into 1.15 format, saturate and store in the destination buffer. */
+  /* Loop over the blockSize. */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);
+    blkCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR_Sparse group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c
new file mode 100644
index 000000000..5bbd110cf
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c
@@ -0,0 +1,367 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_sparse_q31.c   
+*   
+* Description:	Q31 sparse FIR filter processing function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+
+/**   
+ * @addtogroup FIR_Sparse   
+ * @{   
+ */
+
+/**  
+ * @brief Processing function for the Q31 sparse FIR filter.  
+ * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.  
+ * @param[in]  *pSrc       points to the block of input data.  
+ * @param[out] *pDst       points to the block of output data  
+ * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.  
+ * @param[in]  blockSize   number of input samples to process per call.  
+ * @return none.  
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 32-bit accumulator.  
+ * The 1.31 x 1.31 multiplications are truncated to 2.30 format.  
+ * This leads to loss of precision on the intermediate multiplications and provides only a single guard bit.   
+ * If the accumulator result overflows, it wraps around rather than saturate.  
+ * In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.  
+ */
+
+void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize)
+{
+
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *px;                                     /* Scratch buffer pointer */
+  q31_t *py = pState;                            /* Temporary pointers for state buffer */
+  q31_t *pb = pScratchIn;                        /* Temporary pointers for scratch buffer */
+  q31_t *pOut;                                   /* Destination pointer */
+  q63_t out;                                     /* Temporary output variable */
+  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
+  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
+  uint16_t numTaps = S->numTaps;                 /* Filter order */
+  int32_t readIndex;                             /* Read index of the state buffer */
+  uint32_t tapCnt, blkCnt;                       /* loop counters */
+  q31_t coeff = *pCoeffs++;                      /* Read the first coefficient value */
+  q31_t in;
+
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
+                        (int32_t *) pSrc, 1, blockSize);
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                       (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                       blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pOut = pDst;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Loop over the blockSize. Unroll by a factor of 4.   
+   * Compute 4 Multiplications at a time. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in the destination buffer */
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,   
+   * compute the remaining samples */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in the destination buffer */
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and   
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                         blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pOut = pDst;
+
+    /* Loop over the blockSize. Unroll by a factor of 4.   
+     * Compute 4 MACS at a time. */
+    blkCnt = blockSize >> 2;
+
+    while(blkCnt > 0u)
+    {
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4,   
+     * compute the remaining samples */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and   
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+  /* Working output pointer is updated */
+  pOut = pDst;
+
+  /* Output is converted into 1.31 format. */
+  /* Loop over the blockSize. Unroll by a factor of 4.   
+   * process 4 output samples at a time. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    in = *pOut << 1;
+    *pOut++ = in;
+    in = *pOut << 1;
+    *pOut++ = in;
+    in = *pOut << 1;
+    *pOut++ = in;
+    in = *pOut << 1;
+    *pOut++ = in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,   
+   * process the remaining output samples */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    in = *pOut << 1;
+    *pOut++ = in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in the destination buffer */
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and          
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                         blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pOut = pDst;
+
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and          
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+  /* Working output pointer is updated */
+  pOut = pDst;
+
+  /* Output is converted into 1.31 format. */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    in = *pOut << 1;
+    *pOut++ = in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR_Sparse group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c
new file mode 100644
index 000000000..bcba31a74
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c
@@ -0,0 +1,395 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_sparse_q7.c   
+*   
+* Description:	Q7 sparse FIR filter processing function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Sparse   
+ * @{   
+ */
+
+
+/**  
+ * @brief Processing function for the Q7 sparse FIR filter.  
+ * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.  
+ * @param[in]  *pSrc        points to the block of input data.  
+ * @param[out] *pDst        points to the block of output data  
+ * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.  
+ * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.  
+ * @param[in]  blockSize    number of input samples to process per call.  
+ * @return none.  
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 32-bit internal accumulator.   
+ * Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.   
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.   
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.   
+ * The accumulator is then converted to 18.7 format by discarding the low 7 bits.  
+ * Finally, the result is truncated to 1.7 format.  
+ */
+
+void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize)
+{
+
+  q7_t *pState = S->pState;                      /* State pointer */
+  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */
+  q7_t *px;                                      /* Scratch buffer pointer */
+  q7_t *py = pState;                             /* Temporary pointers for state buffer */
+  q7_t *pb = pScratchIn;                         /* Temporary pointers for scratch buffer */
+  q7_t *pOut = pDst;                             /* Destination pointer */
+  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
+  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
+  uint16_t numTaps = S->numTaps;                 /* Filter order */
+  int32_t readIndex;                             /* Read index of the state buffer */
+  uint32_t tapCnt, blkCnt;                       /* loop counters */
+  q7_t coeff = *pCoeffs++;                       /* Read the coefficient value */
+  q31_t *pScr2 = pScratchOut;                    /* Working pointer for scratch buffer of output values */
+  q31_t in;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t in1, in2, in3, in4;
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,
+                       blockSize);
+
+  /* Loop over the number of taps. */
+  tapCnt = numTaps;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+                      (int32_t) blockSize, 1, blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pScratchOut = pScr2;
+
+  /* Loop over the blockSize. Unroll by a factor of 4.   
+   * Compute 4 multiplications at a time. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,   
+   * compute the remaining samples */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and   
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+                        (int32_t) blockSize, 1, blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pScratchOut = pScr2;
+
+    /* Loop over the blockSize. Unroll by a factor of 4.   
+     * Compute 4 MACS at a time. */
+    blkCnt = blockSize >> 2;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4,   
+     * compute the remaining samples */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and   
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = ((int32_t) S->stateIndex -
+                 (int32_t) blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+  /* All the output values are in pScratchOut buffer.   
+     Convert them into 1.15 format, saturate and store in the destination buffer. */
+  /* Loop over the blockSize. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    in1 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+    in2 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+    in3 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+    in4 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+    *__SIMD32(pOut)++ = __PACKq7(in1, in2, in3, in4);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,   
+     remaining samples are processed in the below loop */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,
+                       blockSize);
+
+  /* Loop over the number of taps. */
+  tapCnt = numTaps;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+                      (int32_t) blockSize, 1, blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pScratchOut = pScr2;
+
+  /* Loop over the blockSize */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and          
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+                        (int32_t) blockSize, 1, blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pScratchOut = pScr2;
+
+    /* Loop over the blockSize */
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and          
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex =
+      ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+  /* All the output values are in pScratchOut buffer.      
+     Convert them into 1.15 format, saturate and store in the destination buffer. */
+  /* Loop over the blockSize. */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR_Sparse group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c
new file mode 100644
index 000000000..6185ccdc2
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c
@@ -0,0 +1,402 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_iir_lattice_f32.c   
+*   
+* Description:	Floating-point IIR Lattice filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup IIR_Lattice Infinite Impulse Response (IIR) Lattice Filters   
+ *   
+ * This set of functions implements lattice filters   
+ * for Q15, Q31 and floating-point data types.  Lattice filters are used in a    
+ * variety of adaptive filter applications.  The filter structure has feedforward and   
+ * feedback components and the net impulse response is infinite length.   
+ * The functions operate on blocks   
+ * of input and output data and each call to the function processes   
+ * blockSize samples through the filter.  pSrc and   
+ * pDst point to input and output arrays containing blockSize values.   
+   
+ * \par Algorithm:   
+ * \image html IIRLattice.gif "Infinite Impulse Response Lattice filter"   
+ * 
   
+ *    fN(n)   =  x(n)   
+ *    fm-1(n) = fm(n) - km * gm-1(n-1)   for m = N, N-1, ...1   
+ *    gm(n)   = km * fm-1(n) + gm-1(n-1) for m = N, N-1, ...1   
+ *    y(n)    = vN * gN(n) + vN-1 * gN-1(n) + ...+ v0 * g0(n)   
+ * 
   
+ * \par   
+ * pkCoeffs points to array of reflection coefficients of size numStages.    
+ * Reflection coefficients are stored in time-reversed order.   
+ * \par   
+ * 
   
+ *    {kN, kN-1, ....k1}   
+ * 
   
+ * pvCoeffs points to the array of ladder coefficients of size (numStages+1).    
+ * Ladder coefficients are stored in time-reversed order.   
+ * \par   
+ * 
   
+ *    {vN, vN-1, ...v0}   
+ * 
   
+ * pState points to a state array of size numStages + blockSize.   
+ * The state variables shown in the figure above (the g values) are stored in the pState array.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+  *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ *   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:   
+ * 
   
+ *arm_iir_lattice_instance_f32 S = {numStages, pState, pkCoeffs, pvCoeffs};   
+ *arm_iir_lattice_instance_q31 S = {numStages, pState, pkCoeffs, pvCoeffs};   
+ *arm_iir_lattice_instance_q15 S = {numStages, pState, pkCoeffs, pvCoeffs};   
+ * 
   
+ * \par   
+ * where numStages is the number of stages in the filter; pState points to the state buffer array;   
+ * pkCoeffs points to array of the reflection coefficients; pvCoeffs points to the array of ladder coefficients.   
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the IIR lattice filter functions.   
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+/**   
+ * @addtogroup IIR_Lattice   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the floating-point IIR lattice filter.   
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in] blockSize number of samples to process.   
+ * @return none.   
+ */
+
+void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t fcurr, fnext = 0, gcurr, gnext;      /* Temporary variables for lattice stages */
+  float32_t acc;                                 /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* temporary variables for counts */
+  float32_t *px1, *px2, *pk, *pv;                /* temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  float32_t *pState;                             /* State pointer */
+  float32_t *pStateCurnt;                        /* State current pointer */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  gcurr = 0.0f;
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0.0f;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+
+    /* Process sample for first tap */
+    gcurr = *px1++;
+    /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+    fnext = fcurr - ((*pk) * gcurr);
+    /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+    gnext = (fnext * (*pk++)) + gcurr;
+    /* write gN(n) into state for next sample processing */
+    *px2++ = gnext;
+    /* y(n) += gN(n) * vN  */
+    acc += (gnext * (*pv++));
+
+    /* Update f values for next coefficient processing */
+    fcurr = fnext;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = (numStages - 1u) >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Process sample for 2nd, 6th ...taps */
+      /* Read gN-2(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 2nd, 6th .. taps */
+      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+      fnext = fcurr - ((*pk) * gcurr);
+      /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+      gnext = (fnext * (*pk++)) + gcurr;
+      /* y(n) += gN-1(n) * vN-1  */
+      /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
+      acc += (gnext * (*pv++));
+      /* write gN-1(n) into state for next sample processing */
+      *px2++ = gnext;
+
+
+      /* Process sample for 3nd, 7th ...taps */
+      /* Read gN-3(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 3rd, 7th .. taps */
+      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+      fcurr = fnext - ((*pk) * gcurr);
+      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+      gnext = (fcurr * (*pk++)) + gcurr;
+      /* y(n) += gN-2(n) * vN-2  */
+      /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
+      acc += (gnext * (*pv++));
+      /* write gN-2(n) into state for next sample processing */
+      *px2++ = gnext;
+
+
+      /* Process sample for 4th, 8th ...taps */
+      /* Read gN-4(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 4th, 8th .. taps */
+      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+      fnext = fcurr - ((*pk) * gcurr);
+      /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */
+      gnext = (fnext * (*pk++)) + gcurr;
+      /* y(n) += gN-3(n) * vN-3  */
+      /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
+      acc += (gnext * (*pv++));
+      /* write gN-3(n) into state for next sample processing */
+      *px2++ = gnext;
+
+
+      /* Process sample for 5th, 9th ...taps */
+      /* Read gN-5(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 5th, 9th .. taps */
+      /* fN-5(n) = fN-4(n) - kN-4 * gN-1(n-1) */
+      fcurr = fnext - ((*pk) * gcurr);
+      /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
+      gnext = (fcurr * (*pk++)) + gcurr;
+      /* y(n) += gN-4(n) * vN-4  */
+      /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
+      acc += (gnext * (*pv++));
+      /* write gN-4(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      tapCnt--;
+
+    }
+
+    fnext = fcurr;
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = (numStages - 1u) % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample for last taps */
+      fnext = fcurr - ((*pk) * gcurr);
+      gnext = (fnext * (*pk++)) + gcurr;
+      /* Output samples for last taps */
+      acc += (gnext * (*pv++));
+      *px2++ = gnext;
+      fcurr = fnext;
+
+      tapCnt--;
+
+    }
+
+
+    /* y(n) += g0(n) * v0 */
+    acc += (fnext * (*pv));
+
+    *px2++ = fnext;
+
+    /* write out into pDst */
+    *pDst++ = acc;
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer   
+     for the preperation of next frame process */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  tapCnt = numStages >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numStages) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0.0f;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+
+    /* Process sample for numStages */
+    tapCnt = numStages;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample for last taps */
+      fnext = fcurr - ((*pk) * gcurr);
+      gnext = (fnext * (*pk++)) + gcurr;
+
+      /* Output samples for last taps */
+      acc += (gnext * (*pv++));
+      *px2++ = gnext;
+      fcurr = fnext;
+
+      /* Decrementing loop counter */
+      tapCnt--;
+
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (fnext * (*pv));
+
+    *px2++ = fnext;
+
+    /* write out into pDst */
+    *pDst++ = acc;
+
+    /* Advance the state pointer by 1 to process the next group of samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer          
+     for the preperation of next frame process */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  tapCnt = numStages;
+
+  /* Copy the data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+
+
+
+/**   
+ * @} end of IIR_Lattice group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c
new file mode 100644
index 000000000..07f58b991
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c
@@ -0,0 +1,83 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_iir_lattice_init_f32.c   
+*   
+* Description:  Floating-point IIR lattice filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup IIR_Lattice   
+ * @{   
+ */
+
+/**   
+ * @brief Initialization function for the floating-point IIR lattice filter.   
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.   
+ * @param[in] numStages number of stages in the filter.   
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.   
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.   
+ * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.   
+ * @param[in] blockSize number of samples to process.   
+ * @return none.   
+ */
+
+void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign reflection coefficient pointer */
+  S->pkCoeffs = pkCoeffs;
+
+  /* Assign ladder coefficient pointer */
+  S->pvCoeffs = pvCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numStages */
+  memset(pState, 0, (numStages + blockSize) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+
+}
+
+  /**   
+   * @} end of IIR_Lattice group   
+   */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c
new file mode 100644
index 000000000..d346a93fc
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c
@@ -0,0 +1,83 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_iir_lattice_init_q15.c   
+*   
+* Description:  Q15 IIR lattice filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup IIR_Lattice   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for the Q15 IIR lattice filter.   
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.   
+   * @param[in] numStages  number of stages in the filter.   
+   * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.   
+   * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.   
+   * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.   
+   * @param[in] blockSize number of samples to process per call.   
+   * @return none.   
+   */
+
+void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign reflection coefficient pointer */
+  S->pkCoeffs = pkCoeffs;
+
+  /* Assign ladder coefficient pointer */
+  S->pvCoeffs = pvCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numStages */
+  memset(pState, 0, (numStages + blockSize) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+
+}
+
+/**   
+ * @} end of IIR_Lattice group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c
new file mode 100644
index 000000000..d3fe2df64
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c
@@ -0,0 +1,83 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_iir_lattice_init_q31.c   
+*   
+* Description:  Initialization function for the Q31 IIR lattice filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup IIR_Lattice   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for the Q31 IIR lattice filter.   
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.   
+   * @param[in] numStages number of stages in the filter.   
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.   
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.   
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.   
+   * @param[in] blockSize number of samples to process.   
+   * @return none.   
+   */
+
+void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign reflection coefficient pointer */
+  S->pkCoeffs = pkCoeffs;
+
+  /* Assign ladder coefficient pointer */
+  S->pvCoeffs = pvCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numStages */
+  memset(pState, 0, (numStages + blockSize) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+
+}
+
+/**   
+ * @} end of IIR_Lattice group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c
new file mode 100644
index 000000000..d8233373e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c
@@ -0,0 +1,403 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_iir_lattice_q15.c   
+*   
+* Description:	Q15 IIR lattice filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup IIR_Lattice   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q15 IIR lattice filter.   
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in] blockSize number of samples to process.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.   
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.   
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.   
+ */
+
+void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t fcurr, fnext, gcurr = 0, gnext;          /* Temporary variables for lattice stages */
+  q15_t gnext1, gnext2;                          /* Temporary variables for lattice stages */
+  uint32_t stgCnt;                               /* Temporary variables for counts */
+  q63_t acc;                                     /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */
+  q15_t *px1, *px2, *pk, *pv;                    /* temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  q15_t *pState;                                 /* State pointer */
+  q15_t *pStateCurnt;                            /* State current pointer */
+  q15_t out;                                     /* Temporary variable for output */
+  q31_t v;                                       /* Temporary variable for ladder coefficient */
+
+
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+
+    /* Process sample for first tap */
+    gcurr = *px1++;
+    /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+    fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+    fnext = __SSAT(fnext, 16);
+    /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+    gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+    gnext = __SSAT(gnext, 16);
+    /* write gN(n) into state for next sample processing */
+    *px2++ = (q15_t) gnext;
+    /* y(n) += gN(n) * vN  */
+    acc += (q31_t) ((gnext * (*pv++)));
+
+
+    /* Update f values for next coefficient processing */
+    fcurr = fnext;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = (numStages - 1u) >> 2;
+
+    while(tapCnt > 0u)
+    {
+
+      /* Process sample for 2nd, 6th ...taps */
+      /* Read gN-2(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 2nd, 6th .. taps */
+      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+      fnext = __SSAT(fnext, 16);
+      /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+      gnext1 = (q15_t) __SSAT(gnext, 16);
+      /* write gN-1(n) into state */
+      *px2++ = (q15_t) gnext1;
+
+
+      /* Process sample for 3nd, 7th ...taps */
+      /* Read gN-3(n-1) from state */
+      gcurr = *px1++;
+      /* Process sample for 3rd, 7th .. taps */
+      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+      fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
+      fcurr = __SSAT(fcurr, 16);
+      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+      gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
+      gnext2 = (q15_t) __SSAT(gnext, 16);
+      /* write gN-2(n) into state */
+      *px2++ = (q15_t) gnext2;
+
+      /* Read vN-1 and vN-2 at a time */
+      v = *__SIMD32(pv)++;
+
+
+      /* Pack gN-1(n) and gN-2(n) */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      gnext = __PKHBT(gnext1, gnext2, 16);
+
+#else
+
+      gnext = __PKHBT(gnext2, gnext1, 16);
+
+#endif /*   #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* y(n) += gN-1(n) * vN-1  */
+      /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
+      /* y(n) += gN-2(n) * vN-2  */
+      /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
+      acc = __SMLALD(gnext, v, acc);
+
+
+      /* Process sample for 4th, 8th ...taps */
+      /* Read gN-4(n-1) from state */
+      gcurr = *px1++;
+      /* Process sample for 4th, 8th .. taps */
+      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+      fnext = __SSAT(fnext, 16);
+      /* gN-3(n) = kN-3 * fN-1(n) + gN-1(n-1) */
+      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+      gnext1 = (q15_t) __SSAT(gnext, 16);
+      /* write  gN-3(n) for the next sample process */
+      *px2++ = (q15_t) gnext1;
+
+
+      /* Process sample for 5th, 9th ...taps */
+      /* Read gN-5(n-1) from state */
+      gcurr = *px1++;
+      /* Process sample for 5th, 9th .. taps */
+      /* fN-5(n) = fN-4(n) - kN-4 * gN-5(n-1) */
+      fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
+      fcurr = __SSAT(fcurr, 16);
+      /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
+      gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
+      gnext2 = (q15_t) __SSAT(gnext, 16);
+      /* write      gN-4(n) for the next sample process */
+      *px2++ = (q15_t) gnext2;
+
+      /* Read vN-3 and vN-4 at a time */
+      v = *__SIMD32(pv)++;
+
+      /* Pack gN-3(n) and gN-4(n) */
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      gnext = __PKHBT(gnext1, gnext2, 16);
+
+#else
+
+      gnext = __PKHBT(gnext2, gnext1, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* y(n) += gN-4(n) * vN-4  */
+      /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
+      /* y(n) += gN-3(n) * vN-3  */
+      /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
+      acc = __SMLALD(gnext, v, acc);
+
+      tapCnt--;
+
+    }
+
+    fnext = fcurr;
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = (numStages - 1u) % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample for last taps */
+      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+      fnext = __SSAT(fnext, 16);
+      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+      gnext = __SSAT(gnext, 16);
+      /* Output samples for last taps */
+      acc += (q31_t) (((q31_t) gnext * (*pv++)));
+      *px2++ = (q15_t) gnext;
+      fcurr = fnext;
+
+      tapCnt--;
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (q31_t) (((q31_t) fnext * (*pv++)));
+
+    out = (q15_t) __SSAT(acc >> 15, 16);
+    *px2++ = (q15_t) fnext;
+
+    /* write out into pDst */
+    *pDst++ = out;
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer   
+     for the preperation of next frame process */
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  stgCnt = (numStages >> 2u);
+
+  /* copy data */
+  while(stgCnt > 0u)
+  {
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    /* Decrement the loop counter */
+    stgCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  stgCnt = (numStages) % 0x4u;
+
+  /* copy data */
+  while(stgCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    stgCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t fcurr, fnext = 0, gcurr = 0, gnext;      /* Temporary variables for lattice stages */
+  uint32_t stgCnt;                               /* Temporary variables for counts */
+  q63_t acc;                                     /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */
+  q15_t *px1, *px2, *pk, *pv;                    /* temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  q15_t *pState;                                 /* State pointer */
+  q15_t *pStateCurnt;                            /* State current pointer */
+  q15_t out;                                     /* Temporary variable for output */
+
+
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+    tapCnt = numStages;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample */
+      /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+      fnext = fcurr - ((gcurr * (*pk)) >> 15);
+      fnext = __SSAT(fnext, 16);
+      /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+      gnext = ((fnext * (*pk++)) >> 15) + gcurr;
+      gnext = __SSAT(gnext, 16);
+      /* Output samples */
+      /* y(n) += gN(n) * vN */
+      acc += (q31_t) ((gnext * (*pv++)));
+      /* write gN(n) into state for next sample processing */
+      *px2++ = (q15_t) gnext;
+      /* Update f values for next coefficient processing */
+      fcurr = fnext;
+
+      tapCnt--;
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (q31_t) ((fnext * (*pv++)));
+
+    out = (q15_t) __SSAT(acc >> 15, 16);
+    *px2++ = (q15_t) fnext;
+
+    /* write out into pDst */
+    *pDst++ = out;
+
+    /* Advance the state pointer by 1 to process the next group of samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer          
+     for the preperation of next frame process */
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  stgCnt = numStages;
+
+  /* copy data */
+  while(stgCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    stgCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+
+
+
+/**   
+ * @} end of IIR_Lattice group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c
new file mode 100644
index 000000000..115224645
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c
@@ -0,0 +1,342 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_iir_lattice_q31.c   
+*   
+* Description:	Q31 IIR lattice filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup IIR_Lattice   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q31 IIR lattice filter.   
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in] blockSize number of samples to process.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around rather than clip.   
+ * In order to avoid overflows completely the input signal must be scaled down by 2*log2(numStages) bits.   
+ * After all multiply-accumulates are performed, the 2.62 accumulator is saturated to 1.32 format and then truncated to 1.31 format.   
+ */
+
+void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t fcurr, fnext = 0, gcurr = 0, gnext;      /* Temporary variables for lattice stages */
+  q63_t acc;                                     /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */
+  q31_t *px1, *px2, *pk, *pv;                    /* Temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  q31_t *pState;                                 /* State pointer */
+  q31_t *pStateCurnt;                            /* State current pointer */
+
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+
+    /* Process sample for first tap */
+    gcurr = *px1++;
+    /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+    fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+    /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+    gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+    /* write gN-1(n-1) into state for next sample processing */
+    *px2++ = gnext;
+    /* y(n) += gN(n) * vN  */
+    acc += ((q63_t) gnext * *pv++);
+
+    /* Update f values for next coefficient processing */
+    fcurr = fnext;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = (numStages - 1u) >> 2;
+
+    while(tapCnt > 0u)
+    {
+
+      /* Process sample for 2nd, 6th .. taps */
+      /* Read gN-2(n-1) from state buffer */
+      gcurr = *px1++;
+      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+      /* y(n) += gN-1(n) * vN-1  */
+      /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-1(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      /* Process sample for 3nd, 7th ...taps */
+      /* Read gN-3(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 3rd, 7th .. taps */
+      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+      fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));
+      /* y(n) += gN-2(n) * vN-2  */
+      /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-2(n) into state for next sample processing */
+      *px2++ = gnext;
+
+
+      /* Process sample for 4th, 8th ...taps */
+      /* Read gN-4(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 4th, 8th .. taps */
+      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+      /* y(n) += gN-3(n) * vN-3  */
+      /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-3(n) into state for next sample processing */
+      *px2++ = gnext;
+
+
+      /* Process sample for 5th, 9th ...taps */
+      /* Read gN-5(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 5th, 9th .. taps */
+      /* fN-5(n) = fN-4(n) - kN-4 * gN-1(n-1) */
+      fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));
+      /* y(n) += gN-4(n) * vN-4  */
+      /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-4(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      tapCnt--;
+
+    }
+
+    fnext = fcurr;
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = (numStages - 1u) % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample for last taps */
+      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+      /* Output samples for last taps */
+      acc += ((q63_t) gnext * *pv++);
+      *px2++ = gnext;
+      fcurr = fnext;
+
+      tapCnt--;
+
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (q63_t) fnext *(
+  *pv++);
+
+    *px2++ = fnext;
+
+    /* write out into pDst */
+    *pDst++ = (q31_t) (acc >> 31u);
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer   
+     for the preperation of next frame process */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  tapCnt = numStages >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numStages) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  };
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+    tapCnt = numStages;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample */
+      /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+      fnext =
+        clip_q63_to_q31(((q63_t) fcurr -
+                         ((q31_t) (((q63_t) gcurr * (*pk)) >> 31))));
+      /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+      gnext =
+        clip_q63_to_q31(((q63_t) gcurr +
+                         ((q31_t) (((q63_t) fnext * (*pk++)) >> 31))));
+      /* Output samples */
+      /* y(n) += gN(n) * vN  */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-1(n-1) into state for next sample processing */
+      *px2++ = gnext;
+      /* Update f values for next coefficient processing */
+      fcurr = fnext;
+
+      tapCnt--;
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (q63_t) fnext *(
+  *pv++);
+
+    *px2++ = fnext;
+
+    /* write out into pDst */
+    *pDst++ = (q31_t) (acc >> 31u);
+
+    /* Advance the state pointer by 1 to process the next group of samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer          
+     for the preperation of next frame process */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  tapCnt = numStages;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+
+
+
+/**   
+ * @} end of IIR_Lattice group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c
new file mode 100644
index 000000000..13053219d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c
@@ -0,0 +1,431 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_lms_f32.c   
+*   
+* Description:	Processing function for the floating-point LMS filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup LMS Least Mean Square (LMS) Filters   
+ *   
+ * LMS filters are a class of adaptive filters that are able to "learn" an unknown transfer functions.   
+ * LMS filters use a gradient descent method in which the filter coefficients are updated based on the instantaneous error signal.   
+ * Adaptive filters are often used in communication systems, equalizers, and noise removal.   
+ * The CMSIS DSP Library contains LMS filter functions that operate on Q15, Q31, and floating-point data types.   
+ * The library also contains normalized LMS filters in which the filter coefficient adaptation is indepedent of the level of the input signal.   
+ *   
+ * An LMS filter consists of two components as shown below.   
+ * The first component is a standard transversal or FIR filter.   
+ * The second component is a coefficient update mechanism.   
+ * The LMS filter has two input signals.   
+ * The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter.   
+ * That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.   
+ * The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.   
+ * This "error signal" tends towards zero as the filter adapts.   
+ * The LMS processing functions accept the input and reference input signals and generate the filter output and error signal.   
+ * \image html LMS.gif "Internal structure of the Least Mean Square filter"   
+ *   
+ * The functions operate on blocks of data and each call to the function processes   
+ * blockSize samples through the filter.   
+ * pSrc points to input signal, pRef points to reference signal,   
+ * pOut points to output signal and pErr points to error signal.   
+ * All arrays contain blockSize values.   
+ *   
+ * The functions operate on a block-by-block basis.   
+ * Internally, the filter coefficients b[n] are updated on a sample-by-sample basis.   
+ * The convergence of the LMS filter is slower compared to the normalized LMS algorithm.   
+ *   
+ * \par Algorithm:   
+ * The output signal y[n] is computed by a standard FIR filter:   
+ * 
   
+ *     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]   
+ * 
   
+ *   
+ * \par   
+ * The error signal equals the difference between the reference signal d[n] and the filter output:   
+ * 
   
+ *     e[n] = d[n] - y[n].   
+ * 
   
+ *   
+ * \par   
+ * After each sample of the error signal is computed, the filter coefficients b[k] are updated on a sample-by-sample basis:   
+ * 
   
+ *     b[k] = b[k] + e[n] * mu * x[n-k],  for k=0, 1, ..., numTaps-1   
+ * 
   
+ * where mu is the step size and controls the rate of coefficient convergence.   
+ *\par   
+ * In the APIs, pCoeffs points to a coefficient array of size numTaps.   
+ * Coefficients are stored in time reversed order.   
+ * \par   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * \par   
+ * pState points to a state array of size numTaps + blockSize - 1.   
+ * Samples in the state buffer are stored in the order:   
+ * \par   
+ * 
   
+ *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}   
+ * 
   
+ * \par   
+ * Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples.   
+ * The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,   
+ * to be avoided and yields a significant speed improvement.   
+ * The state variables are updated after each block of data is processed.   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter and   
+ * coefficient and state arrays cannot be shared among instances.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Set the values in the state buffer to zeros before static initialization.   
+ * The code below statically initializes each of the 3 different data type filter instance structures   
+ * 
   
+ *    arm_lms_instance_f32 S = {numTaps, pState, pCoeffs, mu};   
+ *    arm_lms_instance_q31 S = {numTaps, pState, pCoeffs, mu, postShift};   
+ *    arm_lms_instance_q15 S = {numTaps, pState, pCoeffs, mu, postShift};   
+ * 
   
+ * where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer;   
+ * pCoeffs is the address of the coefficient buffer; mu is the step size parameter; and postShift is the shift applied to coefficients.   
+ *   
+ * \par Fixed-Point Behavior:   
+ * Care must be taken when using the Q15 and Q31 versions of the LMS filter.   
+ * The following issues must be considered:   
+ * - Scaling of coefficients   
+ * - Overflow and saturation   
+ *   
+ * \par Scaling of Coefficients:   
+ * Filter coefficients are represented as fractional values and   
+ * coefficients are restricted to lie in the range [-1 +1).   
+ * The fixed-point functions have an additional scaling parameter postShift.   
+ * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.   
+ * This essentially scales the filter coefficients by 2^postShift and   
+ * allows the filter coefficients to exceed the range [+1 -1).   
+ * The value of postShift is set by the user based on the expected gain through the system being modeled.   
+ *   
+ * \par Overflow and Saturation:   
+ * Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are   
+ * described separately as part of the function specific documentation below.   
+ */
+
+/**   
+ * @addtogroup LMS   
+ * @{   
+ */
+
+/**          
+ * @details          
+ * This function operates on floating-point data types.      
+ *   
+ * @brief Processing function for floating-point LMS filter.   
+ * @param[in]  *S points to an instance of the floating-point LMS filter structure.   
+ * @param[in]  *pSrc points to the block of input data.   
+ * @param[in]  *pRef points to the block of reference data.   
+ * @param[out] *pOut points to the block of output data.   
+ * @param[out] *pErr points to the block of error data.   
+ * @param[in]  blockSize number of samples to process.   
+ * @return     none.   
+ */
+
+void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+  float32_t mu = S->mu;                          /* Adaptive factor */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  float32_t sum, e, d;                           /* accumulator, error, reference data sample */
+  float32_t w = 0.0f;                            /* weight factor */
+
+  e = 0.0f;
+  d = 0.0f;
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Set the accumulator to zero */
+    sum = 0.0f;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* The result in the accumulator, store in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Compute and store error */
+    d = (float32_t) (*pRef++);
+    e = d - sum;
+    *pErr++ = e;
+
+    /* Calculation of Weighting factor for the updating filter coefficients */
+    w = e * mu;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the   
+     satrt of the state buffer. This prepares the state buffer for the   
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop unrolling for (numTaps - 1u) samples copy */
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    sum = 0.0f;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* The result is stored in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Compute and store error */
+    d = (float32_t) (*pRef++);
+    e = d - sum;
+    *pErr++ = e;
+
+    /* Weighting factor for the LMS version */
+    w = e * mu;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the       
+   * start of the state buffer. This prepares the state buffer for the       
+   * next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /*  Copy (numTaps - 1u) samples  */
+  tapCnt = (numTaps - 1u);
+
+  /* Copy the data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+   * @} end of LMS group   
+   */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c
new file mode 100644
index 000000000..46c01044e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c
@@ -0,0 +1,87 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_lms_init_f32.c   
+*   
+* Description:  Floating-point LMS filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @addtogroup LMS   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for floating-point LMS filter.   
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.   
+   * @param[in] numTaps  number of filter coefficients.   
+   * @param[in] *pCoeffs points to the coefficient buffer.   
+   * @param[in] *pState points to state buffer.   
+   * @param[in] mu step size that controls filter coefficient updates.   
+   * @param[in] blockSize number of samples to process.   
+   * @return none.   
+   */
+
+/**   
+ * \par Description:   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * The initial filter coefficients serve as a starting point for the adaptive filter.   
+ * pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_f32().   
+ */
+
+void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps */
+  memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+}
+
+/**   
+ * @} end of LMS group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c
new file mode 100644
index 000000000..5caa0a3cd
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c
@@ -0,0 +1,97 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_lms_init_q15.c   
+*   
+* Description:  Q15 LMS filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup LMS   
+ * @{   
+ */
+
+/**   
+* @brief Initialization function for the Q15 LMS filter.   
+* @param[in] *S points to an instance of the Q15 LMS filter structure.   
+* @param[in] numTaps  number of filter coefficients.   
+* @param[in] *pCoeffs points to the coefficient buffer.   
+* @param[in] *pState points to the state buffer.   
+* @param[in] mu step size that controls filter coefficient updates.   
+* @param[in] blockSize number of samples to process.   
+* @param[in] postShift bit shift applied to coefficients.   
+* @return    none.   
+*   
+* \par Description:   
+* pCoeffs points to the array of filter coefficients stored in time reversed order:   
+* 
   
+*    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+* 
   
+* The initial filter coefficients serve as a starting point for the adaptive filter.   
+* pState points to the array of state variables and size of array is   
+* numTaps+blockSize-1 samples, where blockSize is the number of   
+* input samples processed by each call to arm_lms_q15().   
+*/
+
+void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1 */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Assign postShift value to be applied */
+  S->postShift = postShift;
+
+}
+
+/**   
+ * @} end of LMS group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c
new file mode 100644
index 000000000..7d8fd49e7
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c
@@ -0,0 +1,97 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_lms_init_q31.c   
+*   
+* Description:  Q31 LMS filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup LMS   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for Q31 LMS filter.   
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.   
+   * @param[in] numTaps  number of filter coefficients.   
+   * @param[in] *pCoeffs points to coefficient buffer.   
+   * @param[in] *pState points to state buffer.   
+   * @param[in] mu step size that controls filter coefficient updates.   
+   * @param[in] blockSize number of samples to process.   
+   * @param[in] postShift bit shift applied to coefficients.   
+   * @return none.   
+ *   
+ * \par Description:   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * The initial filter coefficients serve as a starting point for the adaptive filter.   
+ * pState points to an array of length numTaps+blockSize-1 samples,   
+ * where blockSize is the number of input samples processed by each call to   
+ * arm_lms_q31().   
+ */
+
+void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1 */
+  memset(pState, 0, ((uint32_t) numTaps + (blockSize - 1u)) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Assign postShift value to be applied */
+  S->postShift = postShift;
+
+}
+
+/**   
+ * @} end of LMS group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c
new file mode 100644
index 000000000..ee6022921
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c
@@ -0,0 +1,453 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_lms_norm_f32.c   
+*   
+* Description:	Processing function for the floating-point Normalised LMS.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup LMS_NORM Normalized LMS Filters   
+ *   
+ * This set of functions implements a commonly used adaptive filter.   
+ * It is related to the Least Mean Square (LMS) adaptive filter and includes an additional normalization   
+ * factor which increases the adaptation rate of the filter.   
+ * The CMSIS DSP Library contains normalized LMS filter functions that operate on Q15, Q31, and floating-point data types.   
+ *   
+ * A normalized least mean square (NLMS) filter consists of two components as shown below.   
+ * The first component is a standard transversal or FIR filter.   
+ * The second component is a coefficient update mechanism.   
+ * The NLMS filter has two input signals.   
+ * The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter.   
+ * That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.   
+ * The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.   
+ * This "error signal" tends towards zero as the filter adapts.   
+ * The NLMS processing functions accept the input and reference input signals and generate the filter output and error signal.   
+ * \image html LMS.gif "Internal structure of the NLMS adaptive filter"   
+ *   
+ * The functions operate on blocks of data and each call to the function processes   
+ * blockSize samples through the filter.   
+ * pSrc points to input signal, pRef points to reference signal,   
+ * pOut points to output signal and pErr points to error signal.   
+ * All arrays contain blockSize values.   
+ *   
+ * The functions operate on a block-by-block basis.   
+ * Internally, the filter coefficients b[n] are updated on a sample-by-sample basis.   
+ * The convergence of the LMS filter is slower compared to the normalized LMS algorithm.   
+ *   
+ * \par Algorithm:   
+ * The output signal y[n] is computed by a standard FIR filter:   
+ * 
   
+ *     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]   
+ * 
   
+ *   
+ * \par   
+ * The error signal equals the difference between the reference signal d[n] and the filter output:   
+ * 
   
+ *     e[n] = d[n] - y[n].   
+ * 
   
+ *   
+ * \par   
+ * After each sample of the error signal is computed the instanteous energy of the filter state variables is calculated:   
+ * 
   
+ *    E = x[n]^2 + x[n-1]^2 + ... + x[n-numTaps+1]^2.   
+ * 
   
+ * The filter coefficients b[k] are then updated on a sample-by-sample basis:   
+ * 
   
+ *     b[k] = b[k] + e[n] * (mu/E) * x[n-k],  for k=0, 1, ..., numTaps-1   
+ * 
   
+ * where mu is the step size and controls the rate of coefficient convergence.   
+ *\par   
+ * In the APIs, pCoeffs points to a coefficient array of size numTaps.   
+ * Coefficients are stored in time reversed order.   
+ * \par   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * \par   
+ * pState points to a state array of size numTaps + blockSize - 1.   
+ * Samples in the state buffer are stored in the order:   
+ * \par   
+ * 
   
+ *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}   
+ * 
   
+ * \par   
+ * Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples.   
+ * The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,   
+ * to be avoided and yields a significant speed improvement.   
+ * The state variables are updated after each block of data is processed.   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter and   
+ * coefficient and state arrays cannot be shared among instances.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ * \par   
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.   
+ * \par Fixed-Point Behavior:   
+ * Care must be taken when using the Q15 and Q31 versions of the normalised LMS filter.   
+ * The following issues must be considered:   
+ * - Scaling of coefficients   
+ * - Overflow and saturation   
+ *   
+ * \par Scaling of Coefficients:   
+ * Filter coefficients are represented as fractional values and   
+ * coefficients are restricted to lie in the range [-1 +1).   
+ * The fixed-point functions have an additional scaling parameter postShift.   
+ * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.   
+ * This essentially scales the filter coefficients by 2^postShift and   
+ * allows the filter coefficients to exceed the range [+1 -1).   
+ * The value of postShift is set by the user based on the expected gain through the system being modeled.   
+ *   
+ * \par Overflow and Saturation:   
+ * Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are   
+ * described separately as part of the function specific documentation below.   
+ */
+
+
+/**   
+ * @addtogroup LMS_NORM   
+ * @{   
+ */
+
+
+  /**   
+   * @brief Processing function for floating-point normalized LMS filter.   
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.   
+   * @param[in] *pSrc points to the block of input data.   
+   * @param[in] *pRef points to the block of reference data.   
+   * @param[out] *pOut points to the block of output data.   
+   * @param[out] *pErr points to the block of error data.   
+   * @param[in] blockSize number of samples to process.   
+   * @return none.   
+   */
+
+void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+  float32_t mu = S->mu;                          /* Adaptive factor */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  float32_t energy;                              /* Energy of the input */
+  float32_t sum, e, d;                           /* accumulator, error, reference data sample */
+  float32_t w, x0, in;                           /* weight factor, temporary variable to hold input sample and state */
+
+  /* Initializations of error,  difference, Coefficient update */
+  e = 0.0f;
+  d = 0.0f;
+  w = 0.0f;
+
+  energy = S->energy;
+  x0 = S->x0;
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy -= x0 * x0;
+    energy += in * in;
+
+    /* Set the accumulator to zero */
+    sum = 0.0f;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* The result in the accumulator, store in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Compute and store error */
+    d = (float32_t) (*pRef++);
+    e = d - sum;
+    *pErr++ = e;
+
+    /* Calculation of Weighting factor for updating filter coefficients */
+    /* epsilon value 0.000000119209289f */
+    w = (e * mu) / (energy + 0.000000119209289f);
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb += w * (*px++);
+      pb++;
+
+      *pb += w * (*px++);
+      pb++;
+
+      *pb += w * (*px++);
+      pb++;
+
+      *pb += w * (*px++);
+      pb++;
+
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb += w * (*px++);
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  S->energy = energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the   
+     satrt of the state buffer. This prepares the state buffer for the   
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop unrolling for (numTaps - 1u)/4 samples copy */
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy -= x0 * x0;
+    energy += in * in;
+
+    /* Set the accumulator to zero */
+    sum = 0.0f;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* The result in the accumulator is stored in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Compute and store error */
+    d = (float32_t) (*pRef++);
+    e = d - sum;
+    *pErr++ = e;
+
+    /* Calculation of Weighting factor for updating filter coefficients */
+    /* epsilon value 0.000000119209289f */
+    w = (e * mu) / (energy + 0.000000119209289f);
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCcoeffs pointer */
+    pb = pCoeffs;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb += w * (*px++);
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  S->energy = energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the       
+     satrt of the state buffer. This prepares the state buffer for the       
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy (numTaps - 1u) samples  */
+  tapCnt = (numTaps - 1u);
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+   * @} end of LMS_NORM group   
+   */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c
new file mode 100644
index 000000000..7621ca136
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c
@@ -0,0 +1,97 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_lms_norm_init_f32.c   
+*   
+* Description:  Floating-point NLMS filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup LMS_NORM   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for floating-point normalized LMS filter.   
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.   
+   * @param[in] numTaps  number of filter coefficients.   
+   * @param[in] *pCoeffs points to coefficient buffer.   
+   * @param[in] *pState points to state buffer.   
+   * @param[in] mu step size that controls filter coefficient updates.   
+   * @param[in] blockSize number of samples to process.   
+   * @return none.   
+   *   
+ * \par Description:   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * The initial filter coefficients serve as a starting point for the adaptive filter.   
+ * pState points to an array of length numTaps+blockSize-1 samples,   
+ * where blockSize is the number of input samples processed by each call to arm_lms_norm_f32().   
+ */
+
+void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1 */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Initialise Energy to zero */
+  S->energy = 0.0f;
+
+  /* Initialise x0 to zero */
+  S->x0 = 0.0f;
+
+}
+
+/**   
+ * @} end of LMS_NORM group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c
new file mode 100644
index 000000000..758a578a4
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c
@@ -0,0 +1,104 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_lms_norm_init_q15.c   
+*   
+* Description:  Q15 NLMS initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**   
+ * @addtogroup LMS_NORM   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for Q15 normalized LMS filter.   
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.   
+   * @param[in] numTaps  number of filter coefficients.   
+   * @param[in] *pCoeffs points to coefficient buffer.   
+   * @param[in] *pState points to state buffer.   
+   * @param[in] mu step size that controls filter coefficient updates.   
+   * @param[in] blockSize number of samples to process.   
+   * @param[in] postShift bit shift applied to coefficients.   
+   * @return none.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * The initial filter coefficients serve as a starting point for the adaptive filter.   
+ * pState points to the array of state variables and size of array is   
+ * numTaps+blockSize-1 samples, where blockSize is the number of input samples processed   
+ * by each call to arm_lms_norm_q15().   
+ */
+
+void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1 */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+  /* Assign post Shift value applied to coefficients */
+  S->postShift = postShift;
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Initialize reciprocal pointer table */
+  S->recipTable = armRecipTableQ15;
+
+  /* Initialise Energy to zero */
+  S->energy = 0;
+
+  /* Initialise x0 to zero */
+  S->x0 = 0;
+
+}
+
+/**   
+ * @} end of LMS_NORM group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c
new file mode 100644
index 000000000..781201ef6
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c
@@ -0,0 +1,103 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_lms_norm_init_q31.c   
+*   
+* Description:  Q31 NLMS initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**   
+ * @addtogroup LMS_NORM   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for Q31 normalized LMS filter.   
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.   
+   * @param[in] numTaps  number of filter coefficients.   
+   * @param[in] *pCoeffs points to coefficient buffer.   
+   * @param[in] *pState points to state buffer.   
+   * @param[in] mu step size that controls filter coefficient updates.   
+   * @param[in] blockSize number of samples to process.   
+   * @param[in] postShift bit shift applied to coefficients.   
+   * @return none.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * The initial filter coefficients serve as a starting point for the adaptive filter.   
+ * pState points to an array of length numTaps+blockSize-1 samples,   
+ * where blockSize is the number of input samples processed by each call to arm_lms_norm_q31().   
+ */
+
+void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1  */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q31_t));
+
+  /* Assign post Shift value applied to coefficients */
+  S->postShift = postShift;
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Initialize reciprocal pointer table */
+  S->recipTable = armRecipTableQ31;
+
+  /* Initialise Energy to zero */
+  S->energy = 0;
+
+  /* Initialise x0 to zero */
+  S->x0 = 0;
+
+}
+
+/**   
+ * @} end of LMS_NORM group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c
new file mode 100644
index 000000000..6417fe485
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c
@@ -0,0 +1,386 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_lms_norm_q15.c   
+*   
+* Description:	Q15 NLMS filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup LMS_NORM   
+ * @{   
+ */
+
+/**   
+* @brief Processing function for Q15 normalized LMS filter.   
+* @param[in] *S points to an instance of the Q15 normalized LMS filter structure.   
+* @param[in] *pSrc points to the block of input data.   
+* @param[in] *pRef points to the block of reference data.   
+* @param[out] *pOut points to the block of output data.   
+* @param[out] *pErr points to the block of error data.   
+* @param[in] blockSize number of samples to process.   
+* @return none.   
+*   
+* Scaling and Overflow Behavior:    
+* \par    
+* The function is implemented using a 64-bit internal accumulator.    
+* Both coefficients and state variables are represented in 1.15 format and   
+* multiplications yield a 2.30 result. The 2.30 intermediate results are   
+* accumulated in a 64-bit accumulator in 34.30 format.    
+* There is no risk of internal overflow with this approach and the full   
+* precision of intermediate multiplications is preserved. After all additions   
+* have been performed, the accumulator is truncated to 34.15 format by   
+* discarding low 15 bits. Lastly, the accumulator is saturated to yield a   
+* result in 1.15 format.   
+*   
+* \par  
+* 	In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.   
+*   
+ */
+
+void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px, *pb;                                /* Temporary pointers for state and coefficient buffers */
+  q15_t mu = S->mu;                              /* Adaptive factor */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  q31_t energy;                                  /* Energy of the input */
+  q63_t acc;                                     /* Accumulator */
+  q15_t e = 0, d = 0;                            /* error, reference data sample */
+  q15_t w = 0, in;                               /* weight factor and state */
+  q15_t x0;                                      /* temporary variable to hold input sample */
+  uint32_t shift = (uint32_t) S->postShift + 1u; /* Shift to be applied to the output */
+  q15_t errorXmu, oneByEnergy;                   /* Temporary variables to store error and mu product and reciprocal of energy */
+  q15_t postShift;                               /* Post shift to be applied to weight after reciprocal calculation */
+  q31_t coef;                                    /* Teporary variable for coefficient */
+
+  energy = S->energy;
+  x0 = S->x0;
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy -= (((q31_t) x0 * (x0)) >> 15);
+    energy += (((q31_t) in * (in)) >> 15);
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+
+      /* Perform the multiply-accumulate */
+      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += (((q31_t) * px++ * (*pb++)));
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.15 format */
+    acc = __SSAT((acc >> (16u - shift)), 16u);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q15_t) acc;
+
+    /* Compute and store error */
+    d = *pRef++;
+    e = d - (q15_t) acc;
+    *pErr++ = e;
+
+    /* Calculation of 1/energy */
+    postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,
+                              &oneByEnergy, S->recipTable);
+
+    /* Calculation of e * mu value */
+    errorXmu = (q15_t) (((q31_t) e * mu) >> 15);
+
+    /* Calculation of (e * mu) * (1/energy) value */
+    acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));
+
+    /* Weighting factor for the normalized version */
+    w = (q15_t) __SSAT((q31_t) acc, 16);
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Read the sample from state buffer */
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Save energy and x0 values for the next frame */
+  S->energy = (q15_t) energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the   
+     satrt of the state buffer. This prepares the state buffer for the   
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1u) >> 2;
+
+  while(tapCnt > 0u)
+  {
+
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    tapCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy -= (((q31_t) x0 * (x0)) >> 15);
+    energy += (((q31_t) in * (in)) >> 15);
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += (((q31_t) * px++ * (*pb++)));
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.15 format */
+    acc = __SSAT((acc >> (16u - shift)), 16u);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q15_t) acc;
+
+    /* Compute and store error */
+    d = *pRef++;
+    e = d - (q15_t) acc;
+    *pErr++ = e;
+
+    /* Calculation of 1/energy */
+    postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,
+                              &oneByEnergy, S->recipTable);
+
+    /* Calculation of e * mu value */
+    errorXmu = (q15_t) (((q31_t) e * mu) >> 15);
+
+    /* Calculation of (e * mu) * (1/energy) value */
+    acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));
+
+    /* Weighting factor for the normalized version */
+    w = (q15_t) __SSAT((q31_t) acc, 16);
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Read the sample from state buffer */
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Save energy and x0 values for the next frame */
+  S->energy = (q15_t) energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the       
+     satrt of the state buffer. This prepares the state buffer for the       
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* copy (numTaps - 1u) data */
+  tapCnt = (numTaps - 1u);
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+
+/**   
+   * @} end of LMS_NORM group   
+   */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c
new file mode 100644
index 000000000..05e732961
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c
@@ -0,0 +1,404 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_lms_norm_q31.c   
+*   
+* Description:	Processing function for the Q31 NLMS filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup LMS_NORM   
+ * @{   
+ */
+
+/**   
+* @brief Processing function for Q31 normalized LMS filter.   
+* @param[in] *S points to an instance of the Q31 normalized LMS filter structure.   
+* @param[in] *pSrc points to the block of input data.   
+* @param[in] *pRef points to the block of reference data.   
+* @param[out] *pOut points to the block of output data.   
+* @param[out] *pErr points to the block of error data.   
+* @param[in] blockSize number of samples to process.   
+* @return none.   
+*   
+* Scaling and Overflow Behavior:    
+* \par    
+* The function is implemented using an internal 64-bit accumulator.    
+* The accumulator has a 2.62 format and maintains full precision of the intermediate  
+* multiplication results but provides only a single guard bit.    
+* Thus, if the accumulator result overflows it wraps around rather than clip.    
+* In order to avoid overflows completely the input signal must be scaled down by   
+* log2(numTaps) bits. The reference signal should not be scaled down.    
+* After all multiply-accumulates are performed, the 2.62 accumulator is shifted   
+* and saturated to 1.31 format to yield the final result.    
+* The output signal and error signal are in 1.31 format.    
+*   
+* \par   
+* 	In this filter, filter coefficients are updated for each sample and the   
+* updation of filter cofficients are saturted.   
+*    
+*/
+
+void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t *px, *pb;                                /* Temporary pointers for state and coefficient buffers */
+  q31_t mu = S->mu;                              /* Adaptive factor */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  q63_t energy;                                  /* Energy of the input */
+  q63_t acc;                                     /* Accumulator */
+  q31_t e = 0, d = 0;                            /* error, reference data sample */
+  q31_t w = 0, in;                               /* weight factor and state */
+  q31_t x0;                                      /* temporary variable to hold input sample */
+  uint32_t shift = 32u - ((uint32_t) S->postShift + 1u);        /* Shift to be applied to the output */
+  q31_t errorXmu, oneByEnergy;                   /* Temporary variables to store error and mu product and reciprocal of energy */
+  q31_t postShift;                               /* Post shift to be applied to weight after reciprocal calculation */
+  q31_t coef;                                    /* Temporary variable for coef */
+
+  energy = S->energy;
+  x0 = S->x0;
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while(blkCnt > 0u)
+  {
+
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy = (q31_t) ((((q63_t) energy << 32) -
+                       (((q63_t) x0 * x0) << 1)) >> 32);
+    energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+      acc += ((q63_t) (*px++)) * (*pb++);
+      acc += ((q63_t) (*px++)) * (*pb++);
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.31 format */
+    acc = (q31_t) (acc >> shift);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q31_t) acc;
+
+    /* Compute and store error */
+    d = *pRef++;
+    e = d - (q31_t) acc;
+    *pErr++ = e;
+
+    /* Calculates the reciprocal of energy */
+    postShift = arm_recip_q31(energy + DELTA_Q31,
+                              &oneByEnergy, &S->recipTable[0]);
+
+    /* Calculation of product of (e * mu) */
+    errorXmu = (q31_t) (((q63_t) e * mu) >> 31);
+
+    /* Weighting factor for the normalized version */
+    w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+
+      /* coef is in 2.30 format */
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      /* get coef in 1.31 format by left shifting */
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      /* update coefficient buffer to next coefficient */
+      pb++;
+
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Read the sample from state buffer */
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Save energy and x0 values for the next frame */
+  S->energy = (q31_t) energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the   
+     satrt of the state buffer. This prepares the state buffer for the   
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop unrolling for (numTaps - 1u) samples copy */
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy =
+      (q31_t) ((((q63_t) energy << 32) - (((q63_t) x0 * x0) << 1)) >> 32);
+    energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.31 format */
+    acc = (q31_t) (acc >> shift);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q31_t) acc;
+
+    /* Compute and store error */
+    d = *pRef++;
+    e = d - (q31_t) acc;
+    *pErr++ = e;
+
+    /* Calculates the reciprocal of energy */
+    postShift =
+      arm_recip_q31(energy + DELTA_Q31, &oneByEnergy, &S->recipTable[0]);
+
+    /* Calculation of product of (e * mu) */
+    errorXmu = (q31_t) (((q63_t) e * mu) >> 31);
+
+    /* Weighting factor for the normalized version */
+    w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      /* coef is in 2.30 format */
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      /* get coef in 1.31 format by left shifting */
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      /* update coefficient buffer to next coefficient */
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Read the sample from state buffer */
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Save energy and x0 values for the next frame */
+  S->energy = (q31_t) energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
+     start of the state buffer. This prepares the state buffer for the       
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop for (numTaps - 1u) samples copy */
+  tapCnt = (numTaps - 1u);
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of LMS_NORM group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c
new file mode 100644
index 000000000..eb62f1fc2
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c
@@ -0,0 +1,331 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_lms_q15.c   
+*   
+* Description:	Processing function for the Q15 LMS filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup LMS   
+ * @{   
+ */
+
+ /**   
+ * @brief Processing function for Q15 LMS filter.   
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[in] *pRef points to the block of reference data.   
+ * @param[out] *pOut points to the block of output data.   
+ * @param[out] *pErr points to the block of error data.   
+ * @param[in] blockSize number of samples to process.   
+ * @return none.   
+ *   
+ * \par Scaling and Overflow Behavior:   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.   
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.   
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.   
+ *  
+ * \par  
+ * 	In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.  
+ *   
+ */
+
+void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t mu = S->mu;                              /* Adaptive factor */
+  q15_t *px;                                     /* Temporary pointer for state */
+  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  q63_t acc;                                     /* Accumulator */
+  q15_t e = 0;                                   /* error of data sample */
+  q15_t alpha;                                   /* Intermediate constant for taps update */
+  uint32_t shift = S->postShift + 1u;            /* Shift to be applied to the output */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t coef;                                    /* Teporary variable for coefficient */
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Initializing blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2u;
+
+    while(tapCnt > 0u)
+    {
+      /* acc +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+      /* Perform the multiply-accumulate */
+      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.15 format and saturate the output */
+    acc = __SSAT((acc >> (16 - shift)), 16);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q15_t) acc;
+
+    /* Compute and store error */
+    e = *pRef++ - (q15_t) acc;
+
+    *pErr++ = (q15_t) e;
+
+    /* Compute alpha i.e. intermediate constant for taps update */
+    alpha = (q15_t) (((q31_t) e * (mu)) >> 15);
+
+    /* Initialize state pointer */
+    /* Advance state pointer by 1 for the next sample */
+    px = pState++;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2u;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the   
+     satrt of the state buffer. This prepares the state buffer for the   
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1u) >> 2;
+
+  while(tapCnt > 0u)
+  {
+
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    tapCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += (q63_t) ((q31_t) (*px++) * (*pb++));
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.15 format and saturate the output */
+    acc = __SSAT((acc >> (16 - shift)), 16);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q15_t) acc;
+
+    /* Compute and store error */
+    e = *pRef++ - (q15_t) acc;
+
+    *pErr++ = (q15_t) e;
+
+    /* Compute alpha i.e. intermediate constant for taps update */
+    alpha = (q15_t) (((q31_t) e * (mu)) >> 15);
+
+    /* Initialize pState pointer */
+    /* Advance state pointer by 1 for the next sample */
+    px = pState++;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb++ += (q15_t) (((q31_t) alpha * (*px++)) >> 15);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the       
+     start of the state buffer. This prepares the state buffer for the  
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /*  Copy (numTaps - 1u) samples  */
+  tapCnt = (numTaps - 1u);
+
+  /* Copy the data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+   * @} end of LMS group   
+   */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c
new file mode 100644
index 000000000..dced45214
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c
@@ -0,0 +1,347 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_lms_q31.c   
+*   
+* Description:	Processing function for the Q31 LMS filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup LMS   
+ * @{   
+ */
+
+ /**   
+ * @brief Processing function for Q31 LMS filter.   
+ * @param[in]  *S points to an instance of the Q15 LMS filter structure.   
+ * @param[in]  *pSrc points to the block of input data.   
+ * @param[in]  *pRef points to the block of reference data.   
+ * @param[out] *pOut points to the block of output data.   
+ * @param[out] *pErr points to the block of error data.   
+ * @param[in]  blockSize number of samples to process.   
+ * @return     none.   
+ *   
+ * \par Scaling and Overflow Behavior:    
+ * The function is implemented using an internal 64-bit accumulator.    
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate   
+ * multiplication results but provides only a single guard bit.    
+ * Thus, if the accumulator result overflows it wraps around rather than clips.    
+ * In order to avoid overflows completely the input signal must be scaled down by   
+ * log2(numTaps) bits.    
+ * The reference signal should not be scaled down.    
+ * After all multiply-accumulates are performed, the 2.62 accumulator is shifted   
+ * and saturated to 1.31 format to yield the final result.    
+ * The output signal and error signal are in 1.31 format.    
+ *   
+ * \par   
+ * 	In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.   
+ */
+
+void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t mu = S->mu;                              /* Adaptive factor */
+  q31_t *px;                                     /* Temporary pointer for state */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  q63_t acc;                                     /* Accumulator */
+  q31_t e = 0;                                   /* error of data sample */
+  q31_t alpha;                                   /* Intermediate constant for taps update */
+  uint8_t shift = (uint8_t) (32u - (S->postShift + 1u));        /* Shift to be applied to the output */
+  q31_t coef;                                    /* Temporary variable for coef */
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Initializing blkCnt with blockSize */
+  blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      /* acc +=  b[N] * x[n-N] */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* acc +=  b[N-1] * x[n-N-1] */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* acc +=  b[N-2] * x[n-N-2] */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* acc +=  b[N-3] * x[n-N-3] */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.31 format */
+    /* Store the result from accumulator into the destination buffer. */
+    acc = (q31_t) (acc >> shift);
+
+    *pOut++ = (q31_t) acc;
+
+    /* Compute and store error */
+    e = *pRef++ - (q31_t) acc;
+
+    *pErr++ = (q31_t) e;
+
+    /* Compute alpha i.e. intermediate constant for taps update */
+    alpha = (q31_t) (((q63_t) e * mu) >> 31);
+
+    /* Initialize state pointer */
+    /* Advance state pointer by 1 for the next sample */
+    px = pState++;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      /* coef is in 2.30 format */
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      /* get coef in 1.31 format by left shifting */
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      /* update coefficient buffer to next coefficient */
+      pb++;
+
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the   
+     satrt of the state buffer. This prepares the state buffer for the   
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop unrolling for (numTaps - 1u) samples copy */
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.31 format */
+    /* Store the result from accumulator into the destination buffer. */
+    acc = (q31_t) (acc >> shift);
+
+    *pOut++ = (q31_t) acc;
+
+    /* Compute and store error */
+    e = *pRef++ - (q31_t) acc;
+
+    *pErr++ = (q31_t) e;
+
+    /* Weighting factor for the LMS version */
+    alpha = (q31_t) (((q63_t) e * mu) >> 31);
+
+    /* Initialize pState pointer */
+    /* Advance state pointer by 1 for the next sample */
+    px = pState++;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb += (coef << 1u);
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
+     start of the state buffer. This prepares the state buffer for the  
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /*  Copy (numTaps - 1u) samples  */
+  tapCnt = (numTaps - 1u);
+
+  /* Copy the data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+   * @} end of LMS group   
+   */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/GCC/arm_cortexM0x_math.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Source/GCC/arm_cortexM0x_math.uvopt
new file mode 100644
index 000000000..ff9c4eb84
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/GCC/arm_cortexM0x_math.uvopt
@@ -0,0 +1,3582 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
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diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/GCC/arm_cortexM0x_math.uvproj b/hardware/sam/system/CMSIS/DSP_Lib/Source/GCC/arm_cortexM0x_math.uvproj
new file mode 100644
index 000000000..3d89fa16e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/GCC/arm_cortexM0x_math.uvproj
@@ -0,0 +1,1550 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      DSP_Lib CM0 LE
+      0x3
+      ARM-GNU
+      
+        
+          Cortex-M0
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE
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+            1
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+            cmd.exe /C copy ".\intermediateFiles\lib@L.a" "..\..\..\Lib\GCC\"
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+          SARMCM3.DLL
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+          TARMCM1.DLL
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+            
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+            1
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+            1
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+              -fno-strict-aliasing -ffunction-sections
+              ARM_MATH_CM0, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING
+              
+              ..\..\..\Include
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+              arm_fir_interpolate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
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+            
+            
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+              1
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+            
+            
+              arm_fir_interpolate_q31.c
+              1
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+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ../FilteringFunctions/arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
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+            
+            
+              arm_fir_q31.c
+              1
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+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_f32.c
+            
+            
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+              1
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+            
+            
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+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q15.c
+            
+            
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+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ../FilteringFunctions/arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ../FilteringFunctions/arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ../FilteringFunctions/arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ../MatrixFunctions/arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ../MatrixFunctions/arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ../MatrixFunctions/arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ../MatrixFunctions/arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ../MatrixFunctions/arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ../MatrixFunctions/arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ../MatrixFunctions/arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ../MatrixFunctions/arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ../MatrixFunctions/arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ../MatrixFunctions/arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              ../MatrixFunctions/arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_cfft_radix4_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_f32.c
+            
+            
+              arm_cfft_radix4_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q15.c
+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q31.c
+            
+            
+              arm_cfft_radix4_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              ../TransformFunctions/arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
+              1
+              ../TransformFunctions/arm_dct4_init_f32.c
+            
+            
+              arm_dct4_init_q15.c
+              1
+              ../TransformFunctions/arm_dct4_init_q15.c
+            
+            
+              arm_dct4_init_q31.c
+              1
+              ../TransformFunctions/arm_dct4_init_q31.c
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+            
+              arm_dct4_q15.c
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+            
+            
+              arm_dct4_q31.c
+              1
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+            
+            
+              arm_rfft_f32.c
+              1
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+            
+            
+              arm_rfft_init_f32.c
+              1
+              ../TransformFunctions/arm_rfft_init_f32.c
+            
+            
+              arm_rfft_init_q15.c
+              1
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+            
+            
+              arm_rfft_init_q31.c
+              1
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+            
+            
+              arm_rfft_q15.c
+              1
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+            
+            
+              arm_rfft_q31.c
+              1
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+            
+          
+        
+        
+          ControllerFunctions
+          
+            
+              arm_pid_init_f32.c
+              1
+              ../ControllerFunctions/arm_pid_init_f32.c
+            
+            
+              arm_pid_init_q15.c
+              1
+              ../ControllerFunctions/arm_pid_init_q15.c
+            
+            
+              arm_pid_init_q31.c
+              1
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+            
+            
+              arm_pid_reset_f32.c
+              1
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+            
+            
+              arm_pid_reset_q15.c
+              1
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+            
+            
+              arm_pid_reset_q31.c
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+            
+            
+              arm_sin_cos_f32.c
+              1
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+            
+            
+              arm_sin_cos_q31.c
+              1
+              ../ControllerFunctions/arm_sin_cos_q31.c
+            
+          
+        
+        
+          StatisticsFunctions
+          
+            
+              arm_max_f32.c
+              1
+              ../StatisticsFunctions/arm_max_f32.c
+            
+            
+              arm_max_q7.c
+              1
+              ../StatisticsFunctions/arm_max_q7.c
+            
+            
+              arm_max_q15.c
+              1
+              ../StatisticsFunctions/arm_max_q15.c
+            
+            
+              arm_max_q31.c
+              1
+              ../StatisticsFunctions/arm_max_q31.c
+            
+            
+              arm_mean_f32.c
+              1
+              ../StatisticsFunctions/arm_mean_f32.c
+            
+            
+              arm_mean_q7.c
+              1
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+            
+            
+              arm_mean_q15.c
+              1
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+            
+            
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+            
+            
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+            
+            
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+            
+            
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+            
+            
+              arm_power_f32.c
+              1
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+            
+            
+              arm_power_q7.c
+              1
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+            
+            
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+            
+            
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+            
+            
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+            
+            
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+            
+            
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+            
+            
+              arm_std_f32.c
+              1
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+            
+            
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+            
+            
+              arm_std_q31.c
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+            
+            
+              arm_var_f32.c
+              1
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+            
+              arm_var_q15.c
+              1
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+            
+            
+              arm_var_q31.c
+              1
+              ../StatisticsFunctions/arm_var_q31.c
+            
+          
+        
+        
+          SupportFunctions
+          
+            
+              arm_copy_f32.c
+              1
+              ../SupportFunctions/arm_copy_f32.c
+            
+            
+              arm_copy_q7.c
+              1
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+            
+            
+              arm_copy_q15.c
+              1
+              ../SupportFunctions/arm_copy_q15.c
+            
+            
+              arm_copy_q31.c
+              1
+              ../SupportFunctions/arm_copy_q31.c
+            
+            
+              arm_fill_f32.c
+              1
+              ../SupportFunctions/arm_fill_f32.c
+            
+            
+              arm_fill_q7.c
+              1
+              ../SupportFunctions/arm_fill_q7.c
+            
+            
+              arm_fill_q15.c
+              1
+              ../SupportFunctions/arm_fill_q15.c
+            
+            
+              arm_fill_q31.c
+              1
+              ../SupportFunctions/arm_fill_q31.c
+            
+            
+              arm_float_to_q7.c
+              1
+              ../SupportFunctions/arm_float_to_q7.c
+            
+            
+              arm_float_to_q15.c
+              1
+              ../SupportFunctions/arm_float_to_q15.c
+            
+            
+              arm_float_to_q31.c
+              1
+              ../SupportFunctions/arm_float_to_q31.c
+            
+            
+              arm_q7_to_float.c
+              1
+              ../SupportFunctions/arm_q7_to_float.c
+            
+            
+              arm_q7_to_q15.c
+              1
+              ../SupportFunctions/arm_q7_to_q15.c
+            
+            
+              arm_q7_to_q31.c
+              1
+              ../SupportFunctions/arm_q7_to_q31.c
+            
+            
+              arm_q15_to_float.c
+              1
+              ../SupportFunctions/arm_q15_to_float.c
+            
+            
+              arm_q15_to_q7.c
+              1
+              ../SupportFunctions/arm_q15_to_q7.c
+            
+            
+              arm_q15_to_q31.c
+              1
+              ../SupportFunctions/arm_q15_to_q31.c
+            
+            
+              arm_q31_to_float.c
+              1
+              ../SupportFunctions/arm_q31_to_float.c
+            
+            
+              arm_q31_to_q7.c
+              1
+              ../SupportFunctions/arm_q31_to_q7.c
+            
+            
+              arm_q31_to_q15.c
+              1
+              ../SupportFunctions/arm_q31_to_q15.c
+            
+          
+        
+        
+          CommonTables
+          
+            
+              arm_common_tables.c
+              1
+              ../CommonTables/arm_common_tables.c
+            
+          
+        
+      
+    
+  
+
+
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/GCC/arm_cortexM3x_math.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Source/GCC/arm_cortexM3x_math.uvopt
new file mode 100644
index 000000000..aac0be604
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/GCC/arm_cortexM3x_math.uvopt
@@ -0,0 +1,3582 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
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diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/GCC/arm_cortexM3x_math.uvproj b/hardware/sam/system/CMSIS/DSP_Lib/Source/GCC/arm_cortexM3x_math.uvproj
new file mode 100644
index 000000000..936116c48
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/GCC/arm_cortexM3x_math.uvproj
@@ -0,0 +1,1550 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      DSP_Lib CM3 LE
+      0x3
+      ARM-GNU
+      
+        
+          Cortex-M3
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+              -fno-strict-aliasing -ffunction-sections
+              ARM_MATH_CM3, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING
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+              ../BasicMathFunctions/arm_shift_q15.c
+            
+            
+              arm_shift_q31.c
+              1
+              ../BasicMathFunctions/arm_shift_q31.c
+            
+            
+              arm_sub_f32.c
+              1
+              ../BasicMathFunctions/arm_sub_f32.c
+            
+            
+              arm_sub_q7.c
+              1
+              ../BasicMathFunctions/arm_sub_q7.c
+            
+            
+              arm_sub_q15.c
+              1
+              ../BasicMathFunctions/arm_sub_q15.c
+            
+            
+              arm_sub_q31.c
+              1
+              ../BasicMathFunctions/arm_sub_q31.c
+            
+          
+        
+        
+          FastMathFunctions
+          
+            
+              arm_cos_f32.c
+              1
+              ../FastMathFunctions/arm_cos_f32.c
+            
+            
+              arm_cos_q15.c
+              1
+              ../FastMathFunctions/arm_cos_q15.c
+            
+            
+              arm_cos_q31.c
+              1
+              ../FastMathFunctions/arm_cos_q31.c
+            
+            
+              arm_sin_f32.c
+              1
+              ../FastMathFunctions/arm_sin_f32.c
+            
+            
+              arm_sin_q15.c
+              1
+              ../FastMathFunctions/arm_sin_q15.c
+            
+            
+              arm_sin_q31.c
+              1
+              ../FastMathFunctions/arm_sin_q31.c
+            
+            
+              arm_sqrt_q15.c
+              1
+              ../FastMathFunctions/arm_sqrt_q15.c
+            
+            
+              arm_sqrt_q31.c
+              1
+              ../FastMathFunctions/arm_sqrt_q31.c
+            
+          
+        
+        
+          ComplexMathFunctions
+          
+            
+              arm_cmplx_conj_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_f32.c
+            
+            
+              arm_cmplx_conj_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_q15.c
+            
+            
+              arm_cmplx_conj_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_q31.c
+            
+            
+              arm_cmplx_dot_prod_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
+            
+            
+              arm_cmplx_dot_prod_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
+            
+            
+              arm_cmplx_dot_prod_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
+            
+            
+              arm_cmplx_mag_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_f32.c
+            
+            
+              arm_cmplx_mag_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_q15.c
+            
+            
+              arm_cmplx_mag_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_q31.c
+            
+            
+              arm_cmplx_mag_squared_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
+            
+            
+              arm_cmplx_mag_squared_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
+            
+            
+              arm_cmplx_mag_squared_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
+            
+            
+              arm_cmplx_mult_cmplx_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
+            
+            
+              arm_cmplx_mult_cmplx_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
+            
+            
+              arm_cmplx_mult_cmplx_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
+            
+            
+              arm_cmplx_mult_real_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_f32.c
+            
+            
+              arm_cmplx_mult_real_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_q15.c
+            
+            
+              arm_cmplx_mult_real_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_q31.c
+            
+          
+        
+        
+          FilteringFunctions
+          
+            
+              arm_biquad_cascade_df1_32x64_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_32x64_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
+            
+            
+              arm_biquad_cascade_df1_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_f32.c
+            
+            
+              arm_biquad_cascade_df1_fast_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
+            
+            
+              arm_biquad_cascade_df1_fast_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
+            
+            
+              arm_biquad_cascade_df1_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
+            
+            
+              arm_biquad_cascade_df1_init_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
+            
+            
+              arm_biquad_cascade_df1_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q15.c
+            
+            
+              arm_biquad_cascade_df1_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q31.c
+            
+            
+              arm_biquad_cascade_df2T_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_f32.c
+            
+            
+              arm_biquad_cascade_df2T_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
+            
+            
+              arm_conv_f32.c
+              1
+              ../FilteringFunctions/arm_conv_f32.c
+            
+            
+              arm_conv_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q15.c
+            
+            
+              arm_conv_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q31.c
+            
+            
+              arm_conv_partial_f32.c
+              1
+              ../FilteringFunctions/arm_conv_partial_f32.c
+            
+            
+              arm_conv_partial_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q15.c
+            
+            
+              arm_conv_partial_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q31.c
+            
+            
+              arm_conv_partial_q7.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q7.c
+            
+            
+              arm_conv_partial_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q15.c
+            
+            
+              arm_conv_partial_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q31.c
+            
+            
+              arm_conv_q7.c
+              1
+              ../FilteringFunctions/arm_conv_q7.c
+            
+            
+              arm_conv_q15.c
+              1
+              ../FilteringFunctions/arm_conv_q15.c
+            
+            
+              arm_conv_q31.c
+              1
+              ../FilteringFunctions/arm_conv_q31.c
+            
+            
+              arm_correlate_f32.c
+              1
+              ../FilteringFunctions/arm_correlate_f32.c
+            
+            
+              arm_correlate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q15.c
+            
+            
+              arm_correlate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q31.c
+            
+            
+              arm_correlate_q7.c
+              1
+              ../FilteringFunctions/arm_correlate_q7.c
+            
+            
+              arm_correlate_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_q15.c
+            
+            
+              arm_correlate_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_q31.c
+            
+            
+              arm_fir_decimate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_f32.c
+            
+            
+              arm_fir_decimate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q15.c
+            
+            
+              arm_fir_decimate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q31.c
+            
+            
+              arm_fir_decimate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_f32.c
+            
+            
+              arm_fir_decimate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q15.c
+            
+            
+              arm_fir_decimate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q31.c
+            
+            
+              arm_fir_decimate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q15.c
+            
+            
+              arm_fir_decimate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q31.c
+            
+            
+              arm_fir_f32.c
+              1
+              ../FilteringFunctions/arm_fir_f32.c
+            
+            
+              arm_fir_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q15.c
+            
+            
+              arm_fir_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q31.c
+            
+            
+              arm_fir_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_init_q7.c
+            
+            
+              arm_fir_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_init_q15.c
+            
+            
+              arm_fir_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_init_q31.c
+            
+            
+              arm_fir_interpolate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_f32.c
+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ../FilteringFunctions/arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ../FilteringFunctions/arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ../FilteringFunctions/arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ../FilteringFunctions/arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ../FilteringFunctions/arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ../FilteringFunctions/arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ../MatrixFunctions/arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ../MatrixFunctions/arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ../MatrixFunctions/arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ../MatrixFunctions/arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ../MatrixFunctions/arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ../MatrixFunctions/arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ../MatrixFunctions/arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ../MatrixFunctions/arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ../MatrixFunctions/arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ../MatrixFunctions/arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              ../MatrixFunctions/arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_cfft_radix4_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_f32.c
+            
+            
+              arm_cfft_radix4_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q15.c
+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q31.c
+            
+            
+              arm_cfft_radix4_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              ../TransformFunctions/arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
+              1
+              ../TransformFunctions/arm_dct4_init_f32.c
+            
+            
+              arm_dct4_init_q15.c
+              1
+              ../TransformFunctions/arm_dct4_init_q15.c
+            
+            
+              arm_dct4_init_q31.c
+              1
+              ../TransformFunctions/arm_dct4_init_q31.c
+            
+            
+              arm_dct4_q15.c
+              1
+              ../TransformFunctions/arm_dct4_q15.c
+            
+            
+              arm_dct4_q31.c
+              1
+              ../TransformFunctions/arm_dct4_q31.c
+            
+            
+              arm_rfft_f32.c
+              1
+              ../TransformFunctions/arm_rfft_f32.c
+            
+            
+              arm_rfft_init_f32.c
+              1
+              ../TransformFunctions/arm_rfft_init_f32.c
+            
+            
+              arm_rfft_init_q15.c
+              1
+              ../TransformFunctions/arm_rfft_init_q15.c
+            
+            
+              arm_rfft_init_q31.c
+              1
+              ../TransformFunctions/arm_rfft_init_q31.c
+            
+            
+              arm_rfft_q15.c
+              1
+              ../TransformFunctions/arm_rfft_q15.c
+            
+            
+              arm_rfft_q31.c
+              1
+              ../TransformFunctions/arm_rfft_q31.c
+            
+          
+        
+        
+          ControllerFunctions
+          
+            
+              arm_pid_init_f32.c
+              1
+              ../ControllerFunctions/arm_pid_init_f32.c
+            
+            
+              arm_pid_init_q15.c
+              1
+              ../ControllerFunctions/arm_pid_init_q15.c
+            
+            
+              arm_pid_init_q31.c
+              1
+              ../ControllerFunctions/arm_pid_init_q31.c
+            
+            
+              arm_pid_reset_f32.c
+              1
+              ../ControllerFunctions/arm_pid_reset_f32.c
+            
+            
+              arm_pid_reset_q15.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q15.c
+            
+            
+              arm_pid_reset_q31.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q31.c
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diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/GCC/arm_cortexM4x_math.uvopt b/hardware/sam/system/CMSIS/DSP_Lib/Source/GCC/arm_cortexM4x_math.uvopt
new file mode 100644
index 000000000..b0b708620
--- /dev/null
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diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/GCC/arm_cortexM4x_math.uvproj b/hardware/sam/system/CMSIS/DSP_Lib/Source/GCC/arm_cortexM4x_math.uvproj
new file mode 100644
index 000000000..6e5a24037
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/GCC/arm_cortexM4x_math.uvproj
@@ -0,0 +1,3089 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      DSP_Lib CM4 LE
+      0x3
+      ARM-GNU
+      
+        
+          Cortex-M4
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE
+          
+          
+          
+          5125
+          
+          
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+          
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+            
+            
+            0
+            0
+          
+          
+            1
+            0
+            cmd.exe /C copy ".\intermediateFiles\lib@L.a" "..\..\..\Lib\GCC\"
+            
+            0
+            0
+          
+          0
+          
+        
+        
+          0
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+          0
+          0
+          0
+          3
+          
+          
+        
+        
+          SARMCM3.DLL
+          
+          DLM.DLL
+          -pEMBER
+          SARMCM3.DLL
+          
+          TLM.DLL
+          -pEMBER
+        
+        
+          
+            1
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+            0
+            16
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+          
+            1
+            1
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+          
+          0
+          -1
+          
+            
+            
+            
+            
+            .\Simulator.ini
+          
+          
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
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+            1
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+            "Cortex-M4"
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+            0
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            
+              
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+            
+          
+          
+            1
+            0
+            0
+            1
+            0
+            0
+            5
+            2
+            1
+            
+              -mcpu=cortex-m4 -fno-strict-aliasing -ffunction-sections
+              ARM_MATH_CM4, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING
+              
+              ..\..\..\Include
+            
+          
+          
+            0
+            1
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+              
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+              
+              
+            
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+          
+            1
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+            
+            
+            
+            
+            
+            -mcpu=cortex-m4 -Wl,--gc-sections
+            
+          
+        
+      
+      
+        
+          BasicMathFunctions
+          
+            
+              arm_abs_f32.c
+              1
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+            
+              arm_abs_q7.c
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+            
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+            
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+            
+            
+              arm_add_f32.c
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+            
+            
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+            
+            
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+            
+            
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+            
+            
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+            
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+              ../BasicMathFunctions/arm_dot_prod_q7.c
+            
+            
+              arm_dot_prod_q15.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_q15.c
+            
+            
+              arm_dot_prod_q31.c
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+            
+            
+              arm_mult_f32.c
+              1
+              ../BasicMathFunctions/arm_mult_f32.c
+            
+            
+              arm_mult_q7.c
+              1
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+            
+            
+              arm_mult_q15.c
+              1
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+            
+            
+              arm_mult_q31.c
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+            
+            
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+              1
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+            
+            
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+            
+            
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+              1
+              ../BasicMathFunctions/arm_negate_q15.c
+            
+            
+              arm_negate_q31.c
+              1
+              ../BasicMathFunctions/arm_negate_q31.c
+            
+            
+              arm_offset_f32.c
+              1
+              ../BasicMathFunctions/arm_offset_f32.c
+            
+            
+              arm_offset_q7.c
+              1
+              ../BasicMathFunctions/arm_offset_q7.c
+            
+            
+              arm_offset_q15.c
+              1
+              ../BasicMathFunctions/arm_offset_q15.c
+            
+            
+              arm_offset_q31.c
+              1
+              ../BasicMathFunctions/arm_offset_q31.c
+            
+            
+              arm_scale_f32.c
+              1
+              ../BasicMathFunctions/arm_scale_f32.c
+            
+            
+              arm_scale_q7.c
+              1
+              ../BasicMathFunctions/arm_scale_q7.c
+            
+            
+              arm_scale_q15.c
+              1
+              ../BasicMathFunctions/arm_scale_q15.c
+            
+            
+              arm_scale_q31.c
+              1
+              ../BasicMathFunctions/arm_scale_q31.c
+            
+            
+              arm_shift_q7.c
+              1
+              ../BasicMathFunctions/arm_shift_q7.c
+            
+            
+              arm_shift_q15.c
+              1
+              ../BasicMathFunctions/arm_shift_q15.c
+            
+            
+              arm_shift_q31.c
+              1
+              ../BasicMathFunctions/arm_shift_q31.c
+            
+            
+              arm_sub_f32.c
+              1
+              ../BasicMathFunctions/arm_sub_f32.c
+            
+            
+              arm_sub_q7.c
+              1
+              ../BasicMathFunctions/arm_sub_q7.c
+            
+            
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+              1
+              ../BasicMathFunctions/arm_sub_q15.c
+            
+            
+              arm_sub_q31.c
+              1
+              ../BasicMathFunctions/arm_sub_q31.c
+            
+          
+        
+        
+          FastMathFunctions
+          
+            
+              arm_cos_f32.c
+              1
+              ../FastMathFunctions/arm_cos_f32.c
+            
+            
+              arm_cos_q15.c
+              1
+              ../FastMathFunctions/arm_cos_q15.c
+            
+            
+              arm_cos_q31.c
+              1
+              ../FastMathFunctions/arm_cos_q31.c
+            
+            
+              arm_sin_f32.c
+              1
+              ../FastMathFunctions/arm_sin_f32.c
+            
+            
+              arm_sin_q15.c
+              1
+              ../FastMathFunctions/arm_sin_q15.c
+            
+            
+              arm_sin_q31.c
+              1
+              ../FastMathFunctions/arm_sin_q31.c
+            
+            
+              arm_sqrt_q15.c
+              1
+              ../FastMathFunctions/arm_sqrt_q15.c
+            
+            
+              arm_sqrt_q31.c
+              1
+              ../FastMathFunctions/arm_sqrt_q31.c
+            
+          
+        
+        
+          ComplexMathFunctions
+          
+            
+              arm_cmplx_conj_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_f32.c
+            
+            
+              arm_cmplx_conj_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_q15.c
+            
+            
+              arm_cmplx_conj_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_q31.c
+            
+            
+              arm_cmplx_dot_prod_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
+            
+            
+              arm_cmplx_dot_prod_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
+            
+            
+              arm_cmplx_dot_prod_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
+            
+            
+              arm_cmplx_mag_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_f32.c
+            
+            
+              arm_cmplx_mag_q15.c
+              1
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+            
+            
+              arm_cmplx_mag_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_q31.c
+            
+            
+              arm_cmplx_mag_squared_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
+            
+            
+              arm_cmplx_mag_squared_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
+            
+            
+              arm_cmplx_mag_squared_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
+            
+            
+              arm_cmplx_mult_cmplx_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
+            
+            
+              arm_cmplx_mult_cmplx_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
+            
+            
+              arm_cmplx_mult_cmplx_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
+            
+            
+              arm_cmplx_mult_real_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_f32.c
+            
+            
+              arm_cmplx_mult_real_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_q15.c
+            
+            
+              arm_cmplx_mult_real_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_q31.c
+            
+          
+        
+        
+          FilteringFunctions
+          
+            
+              arm_biquad_cascade_df1_32x64_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
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+            
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+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
+            
+            
+              arm_biquad_cascade_df1_f32.c
+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+            
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+            
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+              1
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+            
+            
+              arm_biquad_cascade_df2T_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_f32.c
+            
+            
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+            
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+            
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+            
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+            
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+            
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+            
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+            
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+            
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+              1
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+            
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+            
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+            
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+            
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+            
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+            
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+            
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+            
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+              1
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+            
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+              1
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+            
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+              1
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+            
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+            
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+            
+              arm_fir_decimate_init_q31.c
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+            
+            
+              arm_fir_decimate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q15.c
+            
+            
+              arm_fir_decimate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q31.c
+            
+            
+              arm_fir_f32.c
+              1
+              ../FilteringFunctions/arm_fir_f32.c
+            
+            
+              arm_fir_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q15.c
+            
+            
+              arm_fir_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q31.c
+            
+            
+              arm_fir_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_init_q7.c
+            
+            
+              arm_fir_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_init_q15.c
+            
+            
+              arm_fir_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_init_q31.c
+            
+            
+              arm_fir_interpolate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_f32.c
+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ../FilteringFunctions/arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ../FilteringFunctions/arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ../FilteringFunctions/arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ../FilteringFunctions/arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ../FilteringFunctions/arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ../FilteringFunctions/arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ../MatrixFunctions/arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ../MatrixFunctions/arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ../MatrixFunctions/arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ../MatrixFunctions/arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ../MatrixFunctions/arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ../MatrixFunctions/arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ../MatrixFunctions/arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ../MatrixFunctions/arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ../MatrixFunctions/arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ../MatrixFunctions/arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              ../MatrixFunctions/arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_cfft_radix4_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_f32.c
+            
+            
+              arm_cfft_radix4_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q15.c
+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q31.c
+            
+            
+              arm_cfft_radix4_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              ../TransformFunctions/arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
+              1
+              ../TransformFunctions/arm_dct4_init_f32.c
+            
+            
+              arm_dct4_init_q15.c
+              1
+              ../TransformFunctions/arm_dct4_init_q15.c
+            
+            
+              arm_dct4_init_q31.c
+              1
+              ../TransformFunctions/arm_dct4_init_q31.c
+            
+            
+              arm_dct4_q15.c
+              1
+              ../TransformFunctions/arm_dct4_q15.c
+            
+            
+              arm_dct4_q31.c
+              1
+              ../TransformFunctions/arm_dct4_q31.c
+            
+            
+              arm_rfft_f32.c
+              1
+              ../TransformFunctions/arm_rfft_f32.c
+            
+            
+              arm_rfft_init_f32.c
+              1
+              ../TransformFunctions/arm_rfft_init_f32.c
+            
+            
+              arm_rfft_init_q15.c
+              1
+              ../TransformFunctions/arm_rfft_init_q15.c
+            
+            
+              arm_rfft_init_q31.c
+              1
+              ../TransformFunctions/arm_rfft_init_q31.c
+            
+            
+              arm_rfft_q15.c
+              1
+              ../TransformFunctions/arm_rfft_q15.c
+            
+            
+              arm_rfft_q31.c
+              1
+              ../TransformFunctions/arm_rfft_q31.c
+            
+          
+        
+        
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+          
+            
+              arm_pid_init_f32.c
+              1
+              ../ControllerFunctions/arm_pid_init_f32.c
+            
+            
+              arm_pid_init_q15.c
+              1
+              ../ControllerFunctions/arm_pid_init_q15.c
+            
+            
+              arm_pid_init_q31.c
+              1
+              ../ControllerFunctions/arm_pid_init_q31.c
+            
+            
+              arm_pid_reset_f32.c
+              1
+              ../ControllerFunctions/arm_pid_reset_f32.c
+            
+            
+              arm_pid_reset_q15.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q15.c
+            
+            
+              arm_pid_reset_q31.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q31.c
+            
+            
+              arm_sin_cos_f32.c
+              1
+              ../ControllerFunctions/arm_sin_cos_f32.c
+            
+            
+              arm_sin_cos_q31.c
+              1
+              ../ControllerFunctions/arm_sin_cos_q31.c
+            
+          
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+            
+              arm_max_f32.c
+              1
+              ../StatisticsFunctions/arm_max_f32.c
+            
+            
+              arm_max_q7.c
+              1
+              ../StatisticsFunctions/arm_max_q7.c
+            
+            
+              arm_max_q15.c
+              1
+              ../StatisticsFunctions/arm_max_q15.c
+            
+            
+              arm_max_q31.c
+              1
+              ../StatisticsFunctions/arm_max_q31.c
+            
+            
+              arm_mean_f32.c
+              1
+              ../StatisticsFunctions/arm_mean_f32.c
+            
+            
+              arm_mean_q7.c
+              1
+              ../StatisticsFunctions/arm_mean_q7.c
+            
+            
+              arm_mean_q15.c
+              1
+              ../StatisticsFunctions/arm_mean_q15.c
+            
+            
+              arm_mean_q31.c
+              1
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+            
+            
+              arm_min_f32.c
+              1
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+            
+            
+              arm_min_q7.c
+              1
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+            
+            
+              arm_min_q15.c
+              1
+              ../StatisticsFunctions/arm_min_q15.c
+            
+            
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+              1
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+            
+            
+              arm_power_f32.c
+              1
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+            
+            
+              arm_power_q7.c
+              1
+              ../StatisticsFunctions/arm_power_q7.c
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+            
+              arm_power_q15.c
+              1
+              ../StatisticsFunctions/arm_power_q15.c
+            
+            
+              arm_power_q31.c
+              1
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+            
+            
+              arm_rms_f32.c
+              1
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+            
+            
+              arm_rms_q15.c
+              1
+              ../StatisticsFunctions/arm_rms_q15.c
+            
+            
+              arm_rms_q31.c
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+            
+            
+              arm_std_f32.c
+              1
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+            
+              arm_std_q15.c
+              1
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+            
+            
+              arm_std_q31.c
+              1
+              ../StatisticsFunctions/arm_std_q31.c
+            
+            
+              arm_var_f32.c
+              1
+              ../StatisticsFunctions/arm_var_f32.c
+            
+            
+              arm_var_q15.c
+              1
+              ../StatisticsFunctions/arm_var_q15.c
+            
+            
+              arm_var_q31.c
+              1
+              ../StatisticsFunctions/arm_var_q31.c
+            
+          
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+              1
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+            
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+              1
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+            
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+            
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+              1
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+            
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+              1
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+            
+            
+              arm_fill_q7.c
+              1
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+            
+              arm_fill_q15.c
+              1
+              ../SupportFunctions/arm_fill_q15.c
+            
+            
+              arm_fill_q31.c
+              1
+              ../SupportFunctions/arm_fill_q31.c
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+            
+              arm_float_to_q7.c
+              1
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+            
+            
+              arm_float_to_q15.c
+              1
+              ../SupportFunctions/arm_float_to_q15.c
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+            
+              arm_float_to_q31.c
+              1
+              ../SupportFunctions/arm_float_to_q31.c
+            
+            
+              arm_q7_to_float.c
+              1
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+            
+              arm_q7_to_q15.c
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+            
+              arm_q7_to_q31.c
+              1
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+            
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+              1
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+              arm_q15_to_q7.c
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+            
+              arm_q15_to_q31.c
+              1
+              ../SupportFunctions/arm_q15_to_q31.c
+            
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+              -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -fno-strict-aliasing -ffunction-sections
+              ARM_MATH_CM4, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, __FPU_PRESENT = 1
+              
+              ..\..\..\Include
+            
+          
+          
+            0
+            1
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+              
+              
+              
+            
+          
+          
+            1
+            0
+            1
+            0
+            1
+            
+            
+            
+            
+            
+            -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -Wl,--gc-sections
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+          
+        
+      
+      
+        
+          BasicMathFunctions
+          
+            
+              arm_abs_f32.c
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+            
+              arm_abs_q7.c
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+            
+            
+              arm_abs_q15.c
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+              ../BasicMathFunctions/arm_abs_q15.c
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+            
+              arm_abs_q31.c
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+              ../BasicMathFunctions/arm_abs_q31.c
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+            
+              arm_add_f32.c
+              1
+              ../BasicMathFunctions/arm_add_f32.c
+            
+            
+              arm_add_q7.c
+              1
+              ../BasicMathFunctions/arm_add_q7.c
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+            
+              arm_add_q15.c
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+              ../BasicMathFunctions/arm_add_q15.c
+            
+            
+              arm_add_q31.c
+              1
+              ../BasicMathFunctions/arm_add_q31.c
+            
+            
+              arm_dot_prod_f32.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_f32.c
+            
+            
+              arm_dot_prod_q7.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_q7.c
+            
+            
+              arm_dot_prod_q15.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_q15.c
+            
+            
+              arm_dot_prod_q31.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_q31.c
+            
+            
+              arm_mult_f32.c
+              1
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+            
+              arm_mult_q7.c
+              1
+              ../BasicMathFunctions/arm_mult_q7.c
+            
+            
+              arm_mult_q15.c
+              1
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+            
+            
+              arm_mult_q31.c
+              1
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+            
+              arm_negate_f32.c
+              1
+              ../BasicMathFunctions/arm_negate_f32.c
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+              arm_negate_q31.c
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+            
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+              1
+              ../BasicMathFunctions/arm_offset_q7.c
+            
+            
+              arm_offset_q15.c
+              1
+              ../BasicMathFunctions/arm_offset_q15.c
+            
+            
+              arm_offset_q31.c
+              1
+              ../BasicMathFunctions/arm_offset_q31.c
+            
+            
+              arm_scale_f32.c
+              1
+              ../BasicMathFunctions/arm_scale_f32.c
+            
+            
+              arm_scale_q7.c
+              1
+              ../BasicMathFunctions/arm_scale_q7.c
+            
+            
+              arm_scale_q15.c
+              1
+              ../BasicMathFunctions/arm_scale_q15.c
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+            
+              arm_scale_q31.c
+              1
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+              1
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+              1
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+            
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+              1
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+            
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+            
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+            
+            
+              arm_sub_q31.c
+              1
+              ../BasicMathFunctions/arm_sub_q31.c
+            
+          
+        
+        
+          FastMathFunctions
+          
+            
+              arm_cos_f32.c
+              1
+              ../FastMathFunctions/arm_cos_f32.c
+            
+            
+              arm_cos_q15.c
+              1
+              ../FastMathFunctions/arm_cos_q15.c
+            
+            
+              arm_cos_q31.c
+              1
+              ../FastMathFunctions/arm_cos_q31.c
+            
+            
+              arm_sin_f32.c
+              1
+              ../FastMathFunctions/arm_sin_f32.c
+            
+            
+              arm_sin_q15.c
+              1
+              ../FastMathFunctions/arm_sin_q15.c
+            
+            
+              arm_sin_q31.c
+              1
+              ../FastMathFunctions/arm_sin_q31.c
+            
+            
+              arm_sqrt_q15.c
+              1
+              ../FastMathFunctions/arm_sqrt_q15.c
+            
+            
+              arm_sqrt_q31.c
+              1
+              ../FastMathFunctions/arm_sqrt_q31.c
+            
+          
+        
+        
+          ComplexMathFunctions
+          
+            
+              arm_cmplx_conj_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_f32.c
+            
+            
+              arm_cmplx_conj_q15.c
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+            
+            
+              arm_cmplx_conj_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_q31.c
+            
+            
+              arm_cmplx_dot_prod_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
+            
+            
+              arm_cmplx_dot_prod_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
+            
+            
+              arm_cmplx_dot_prod_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
+            
+            
+              arm_cmplx_mag_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_f32.c
+            
+            
+              arm_cmplx_mag_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_q15.c
+            
+            
+              arm_cmplx_mag_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_q31.c
+            
+            
+              arm_cmplx_mag_squared_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
+            
+            
+              arm_cmplx_mag_squared_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
+            
+            
+              arm_cmplx_mag_squared_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
+            
+            
+              arm_cmplx_mult_cmplx_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
+            
+            
+              arm_cmplx_mult_cmplx_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
+            
+            
+              arm_cmplx_mult_cmplx_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
+            
+            
+              arm_cmplx_mult_real_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_f32.c
+            
+            
+              arm_cmplx_mult_real_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_q15.c
+            
+            
+              arm_cmplx_mult_real_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_q31.c
+            
+          
+        
+        
+          FilteringFunctions
+          
+            
+              arm_biquad_cascade_df1_32x64_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_32x64_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
+            
+            
+              arm_biquad_cascade_df1_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_f32.c
+            
+            
+              arm_biquad_cascade_df1_fast_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
+            
+            
+              arm_biquad_cascade_df1_fast_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
+            
+            
+              arm_biquad_cascade_df1_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
+            
+            
+              arm_biquad_cascade_df1_init_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
+            
+            
+              arm_biquad_cascade_df1_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q15.c
+            
+            
+              arm_biquad_cascade_df1_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q31.c
+            
+            
+              arm_biquad_cascade_df2T_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_f32.c
+            
+            
+              arm_biquad_cascade_df2T_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
+            
+            
+              arm_conv_f32.c
+              1
+              ../FilteringFunctions/arm_conv_f32.c
+            
+            
+              arm_conv_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q15.c
+            
+            
+              arm_conv_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q31.c
+            
+            
+              arm_conv_partial_f32.c
+              1
+              ../FilteringFunctions/arm_conv_partial_f32.c
+            
+            
+              arm_conv_partial_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q15.c
+            
+            
+              arm_conv_partial_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q31.c
+            
+            
+              arm_conv_partial_q7.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q7.c
+            
+            
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+              1
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+            
+            
+              arm_conv_partial_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q31.c
+            
+            
+              arm_conv_q7.c
+              1
+              ../FilteringFunctions/arm_conv_q7.c
+            
+            
+              arm_conv_q15.c
+              1
+              ../FilteringFunctions/arm_conv_q15.c
+            
+            
+              arm_conv_q31.c
+              1
+              ../FilteringFunctions/arm_conv_q31.c
+            
+            
+              arm_correlate_f32.c
+              1
+              ../FilteringFunctions/arm_correlate_f32.c
+            
+            
+              arm_correlate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q15.c
+            
+            
+              arm_correlate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q31.c
+            
+            
+              arm_correlate_q7.c
+              1
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+            
+            
+              arm_correlate_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_q15.c
+            
+            
+              arm_correlate_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_q31.c
+            
+            
+              arm_fir_decimate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_f32.c
+            
+            
+              arm_fir_decimate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q15.c
+            
+            
+              arm_fir_decimate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q31.c
+            
+            
+              arm_fir_decimate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_f32.c
+            
+            
+              arm_fir_decimate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q15.c
+            
+            
+              arm_fir_decimate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q31.c
+            
+            
+              arm_fir_decimate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q15.c
+            
+            
+              arm_fir_decimate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q31.c
+            
+            
+              arm_fir_f32.c
+              1
+              ../FilteringFunctions/arm_fir_f32.c
+            
+            
+              arm_fir_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q15.c
+            
+            
+              arm_fir_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q31.c
+            
+            
+              arm_fir_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
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+            
+            
+              arm_fir_init_q15.c
+              1
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+            
+            
+              arm_fir_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_init_q31.c
+            
+            
+              arm_fir_interpolate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_f32.c
+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ../FilteringFunctions/arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ../FilteringFunctions/arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ../FilteringFunctions/arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ../FilteringFunctions/arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ../FilteringFunctions/arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ../FilteringFunctions/arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ../MatrixFunctions/arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ../MatrixFunctions/arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ../MatrixFunctions/arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ../MatrixFunctions/arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ../MatrixFunctions/arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ../MatrixFunctions/arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ../MatrixFunctions/arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ../MatrixFunctions/arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ../MatrixFunctions/arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ../MatrixFunctions/arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              ../MatrixFunctions/arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_cfft_radix4_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_f32.c
+            
+            
+              arm_cfft_radix4_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q15.c
+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q31.c
+            
+            
+              arm_cfft_radix4_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              ../TransformFunctions/arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
+              1
+              ../TransformFunctions/arm_dct4_init_f32.c
+            
+            
+              arm_dct4_init_q15.c
+              1
+              ../TransformFunctions/arm_dct4_init_q15.c
+            
+            
+              arm_dct4_init_q31.c
+              1
+              ../TransformFunctions/arm_dct4_init_q31.c
+            
+            
+              arm_dct4_q15.c
+              1
+              ../TransformFunctions/arm_dct4_q15.c
+            
+            
+              arm_dct4_q31.c
+              1
+              ../TransformFunctions/arm_dct4_q31.c
+            
+            
+              arm_rfft_f32.c
+              1
+              ../TransformFunctions/arm_rfft_f32.c
+            
+            
+              arm_rfft_init_f32.c
+              1
+              ../TransformFunctions/arm_rfft_init_f32.c
+            
+            
+              arm_rfft_init_q15.c
+              1
+              ../TransformFunctions/arm_rfft_init_q15.c
+            
+            
+              arm_rfft_init_q31.c
+              1
+              ../TransformFunctions/arm_rfft_init_q31.c
+            
+            
+              arm_rfft_q15.c
+              1
+              ../TransformFunctions/arm_rfft_q15.c
+            
+            
+              arm_rfft_q31.c
+              1
+              ../TransformFunctions/arm_rfft_q31.c
+            
+          
+        
+        
+          ControllerFunctions
+          
+            
+              arm_pid_init_f32.c
+              1
+              ../ControllerFunctions/arm_pid_init_f32.c
+            
+            
+              arm_pid_init_q15.c
+              1
+              ../ControllerFunctions/arm_pid_init_q15.c
+            
+            
+              arm_pid_init_q31.c
+              1
+              ../ControllerFunctions/arm_pid_init_q31.c
+            
+            
+              arm_pid_reset_f32.c
+              1
+              ../ControllerFunctions/arm_pid_reset_f32.c
+            
+            
+              arm_pid_reset_q15.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q15.c
+            
+            
+              arm_pid_reset_q31.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q31.c
+            
+            
+              arm_sin_cos_f32.c
+              1
+              ../ControllerFunctions/arm_sin_cos_f32.c
+            
+            
+              arm_sin_cos_q31.c
+              1
+              ../ControllerFunctions/arm_sin_cos_q31.c
+            
+          
+        
+        
+          StatisticsFunctions
+          
+            
+              arm_max_f32.c
+              1
+              ../StatisticsFunctions/arm_max_f32.c
+            
+            
+              arm_max_q7.c
+              1
+              ../StatisticsFunctions/arm_max_q7.c
+            
+            
+              arm_max_q15.c
+              1
+              ../StatisticsFunctions/arm_max_q15.c
+            
+            
+              arm_max_q31.c
+              1
+              ../StatisticsFunctions/arm_max_q31.c
+            
+            
+              arm_mean_f32.c
+              1
+              ../StatisticsFunctions/arm_mean_f32.c
+            
+            
+              arm_mean_q7.c
+              1
+              ../StatisticsFunctions/arm_mean_q7.c
+            
+            
+              arm_mean_q15.c
+              1
+              ../StatisticsFunctions/arm_mean_q15.c
+            
+            
+              arm_mean_q31.c
+              1
+              ../StatisticsFunctions/arm_mean_q31.c
+            
+            
+              arm_min_f32.c
+              1
+              ../StatisticsFunctions/arm_min_f32.c
+            
+            
+              arm_min_q7.c
+              1
+              ../StatisticsFunctions/arm_min_q7.c
+            
+            
+              arm_min_q15.c
+              1
+              ../StatisticsFunctions/arm_min_q15.c
+            
+            
+              arm_min_q31.c
+              1
+              ../StatisticsFunctions/arm_min_q31.c
+            
+            
+              arm_power_f32.c
+              1
+              ../StatisticsFunctions/arm_power_f32.c
+            
+            
+              arm_power_q7.c
+              1
+              ../StatisticsFunctions/arm_power_q7.c
+            
+            
+              arm_power_q15.c
+              1
+              ../StatisticsFunctions/arm_power_q15.c
+            
+            
+              arm_power_q31.c
+              1
+              ../StatisticsFunctions/arm_power_q31.c
+            
+            
+              arm_rms_f32.c
+              1
+              ../StatisticsFunctions/arm_rms_f32.c
+            
+            
+              arm_rms_q15.c
+              1
+              ../StatisticsFunctions/arm_rms_q15.c
+            
+            
+              arm_rms_q31.c
+              1
+              ../StatisticsFunctions/arm_rms_q31.c
+            
+            
+              arm_std_f32.c
+              1
+              ../StatisticsFunctions/arm_std_f32.c
+            
+            
+              arm_std_q15.c
+              1
+              ../StatisticsFunctions/arm_std_q15.c
+            
+            
+              arm_std_q31.c
+              1
+              ../StatisticsFunctions/arm_std_q31.c
+            
+            
+              arm_var_f32.c
+              1
+              ../StatisticsFunctions/arm_var_f32.c
+            
+            
+              arm_var_q15.c
+              1
+              ../StatisticsFunctions/arm_var_q15.c
+            
+            
+              arm_var_q31.c
+              1
+              ../StatisticsFunctions/arm_var_q31.c
+            
+          
+        
+        
+          SupportFunctions
+          
+            
+              arm_copy_f32.c
+              1
+              ../SupportFunctions/arm_copy_f32.c
+            
+            
+              arm_copy_q7.c
+              1
+              ../SupportFunctions/arm_copy_q7.c
+            
+            
+              arm_copy_q15.c
+              1
+              ../SupportFunctions/arm_copy_q15.c
+            
+            
+              arm_copy_q31.c
+              1
+              ../SupportFunctions/arm_copy_q31.c
+            
+            
+              arm_fill_f32.c
+              1
+              ../SupportFunctions/arm_fill_f32.c
+            
+            
+              arm_fill_q7.c
+              1
+              ../SupportFunctions/arm_fill_q7.c
+            
+            
+              arm_fill_q15.c
+              1
+              ../SupportFunctions/arm_fill_q15.c
+            
+            
+              arm_fill_q31.c
+              1
+              ../SupportFunctions/arm_fill_q31.c
+            
+            
+              arm_float_to_q7.c
+              1
+              ../SupportFunctions/arm_float_to_q7.c
+            
+            
+              arm_float_to_q15.c
+              1
+              ../SupportFunctions/arm_float_to_q15.c
+            
+            
+              arm_float_to_q31.c
+              1
+              ../SupportFunctions/arm_float_to_q31.c
+            
+            
+              arm_q7_to_float.c
+              1
+              ../SupportFunctions/arm_q7_to_float.c
+            
+            
+              arm_q7_to_q15.c
+              1
+              ../SupportFunctions/arm_q7_to_q15.c
+            
+            
+              arm_q7_to_q31.c
+              1
+              ../SupportFunctions/arm_q7_to_q31.c
+            
+            
+              arm_q15_to_float.c
+              1
+              ../SupportFunctions/arm_q15_to_float.c
+            
+            
+              arm_q15_to_q7.c
+              1
+              ../SupportFunctions/arm_q15_to_q7.c
+            
+            
+              arm_q15_to_q31.c
+              1
+              ../SupportFunctions/arm_q15_to_q31.c
+            
+            
+              arm_q31_to_float.c
+              1
+              ../SupportFunctions/arm_q31_to_float.c
+            
+            
+              arm_q31_to_q7.c
+              1
+              ../SupportFunctions/arm_q31_to_q7.c
+            
+            
+              arm_q31_to_q15.c
+              1
+              ../SupportFunctions/arm_q31_to_q15.c
+            
+          
+        
+        
+          CommonTables
+          
+            
+              arm_common_tables.c
+              1
+              ../CommonTables/arm_common_tables.c
+            
+          
+        
+      
+    
+  
+
+
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/GCC/arm_cortexMx_math_Build.bat b/hardware/sam/system/CMSIS/DSP_Lib/Source/GCC/arm_cortexMx_math_Build.bat
new file mode 100644
index 000000000..a194c70a4
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/GCC/arm_cortexMx_math_Build.bat
@@ -0,0 +1,10 @@
+
+SET TMP=C:\Temp
+SET TEMP=C:\Temp
+
+SET UVEXE=C:\Keil\UV4\UV4.EXE
+
+%UVEXE% -rb arm_cortexM0x_math.uvproj -t"DSP_Lib CM0 LE" -o"DSP_Lib CM0 LE.txt"
+%UVEXE% -rb arm_cortexM3x_math.uvproj -t"DSP_Lib CM3 LE" -o"DSP_Lib CM3 LE.txt"
+%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 LE" -o"DSP_Lib CM4 LE.txt"
+%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 LE FPU" -o"DSP_Lib CM4 LE FPU.txt"
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c
new file mode 100644
index 000000000..23348a1ec
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c
@@ -0,0 +1,154 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_mat_add_f32.c   
+*   
+* Description:	Floating-point matrix addition   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @defgroup MatrixAdd Matrix Addition   
+ *   
+ * Adds two matrices.   
+ * \image html MatrixAddition.gif "Addition of two 3 x 3 matrices"   
+ *   
+ * The functions check to make sure that   
+ * pSrcA, pSrcB, and pDst have the same   
+ * number of rows and columns.   
+ */
+
+/**   
+ * @addtogroup MatrixAdd   
+ * @{   
+ */
+
+
+/**   
+ * @brief Floating-point matrix addition.   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ */
+
+arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A  */
+  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B  */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer   */
+  uint32_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix addition */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop unrolling */
+    blkCnt = numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add and then store the results in the destination buffer. */
+      *pOut++ = (*pIn1++) + (*pIn2++);
+      *pOut++ = (*pIn1++) + (*pIn2++);
+      *pOut++ = (*pIn1++) + (*pIn2++);
+      *pOut++ = (*pIn1++) + (*pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add and then store the results in the destination buffer. */
+      *pOut++ = (*pIn1++) + (*pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixAdd group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c
new file mode 100644
index 000000000..b96feb4b7
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c
@@ -0,0 +1,158 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_add_q15.c   
+*   
+* Description:	Q15 matrix addition   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixAdd   
+ * @{   
+ */
+
+/**   
+ * @brief Q15 matrix addition.   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.   
+ */
+
+arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst)
+{
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A  */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint16_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters  */
+  arm_status status;                             /* status of matrix addition  */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint16_t) (pSrcA->numRows * pSrcA->numCols);
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop unrolling */
+    blkCnt = (uint32_t) numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, Saturate and then store the results in the destination buffer. */
+      *__SIMD32(pOut)++ = __QADD16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+      *__SIMD32(pOut)++ = __QADD16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = (uint32_t) numSamples % 0x4u;
+
+    /* q15 pointers of input and output are initialized */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, Saturate and then store the results in the destination buffer. */
+      *pOut++ = (q15_t) __QADD16(*pInA++, *pInB++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = (uint32_t) numSamples;
+
+
+    /* q15 pointers of input and output are initialized */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, Saturate and then store the results in the destination buffer. */
+      *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ + *pInB++), 16);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixAdd group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c
new file mode 100644
index 000000000..af4ada0ae
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c
@@ -0,0 +1,157 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_add_q31.c   
+*   
+* Description:	Q31 matrix addition   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixAdd   
+ * @{   
+ */
+
+/**   
+ * @brief Q31 matrix addition.   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.   
+ */
+
+arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix addition */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2u;
+
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, saturate and then store the results in the destination buffer. */
+      *pOut++ = __QADD(*pIn1++, *pIn2++);
+      *pOut++ = __QADD(*pIn1++, *pIn2++);
+      *pOut++ = __QADD(*pIn1++, *pIn2++);
+      *pOut++ = __QADD(*pIn1++, *pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, saturate and then store the results in the destination buffer. */
+      *pOut++ = __QADD(*pIn1++, *pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, saturate and then store the results in the destination buffer. */
+      *pOut++ = clip_q63_to_q31(((q63_t) (*pIn1++)) + (*pIn2++));
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixAdd group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c
new file mode 100644
index 000000000..e27a685b8
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c
@@ -0,0 +1,83 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_mat_init_f32.c   
+*   
+* Description:	Floating-point matrix initialization.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @defgroup MatrixInit Matrix Initialization   
+ *   
+ * Initializes the underlying matrix data structure.   
+ * The functions set the numRows,   
+ * numCols, and pData fields   
+ * of the matrix data structure.   
+ */
+
+/**   
+ * @addtogroup MatrixInit   
+ * @{   
+ */
+
+/**   
+   * @brief  Floating-point matrix initialization.   
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.   
+   * @param[in]     nRows          number of rows in the matrix.   
+   * @param[in]     nColumns       number of columns in the matrix.   
+   * @param[in]     *pData	   points to the matrix data array.   
+   * @return        none   
+   */
+
+void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData)
+{
+  /* Assign Number of Rows */
+  S->numRows = nRows;
+
+  /* Assign Number of Columns */
+  S->numCols = nColumns;
+
+  /* Assign Data pointer */
+  S->pData = pData;
+}
+
+/**   
+ * @} end of MatrixInit group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c
new file mode 100644
index 000000000..addc2b0f1
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c
@@ -0,0 +1,75 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_mat_init_q15.c   
+*   
+* Description:	Q15 matrix initialization.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixInit   
+ * @{   
+ */
+
+  /**   
+   * @brief  Q15 matrix initialization.   
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.   
+   * @param[in]     nRows          number of rows in the matrix.   
+   * @param[in]     nColumns       number of columns in the matrix.   
+   * @param[in]     *pData	   points to the matrix data array.   
+   * @return        none   
+   */
+
+void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData)
+{
+  /* Assign Number of Rows */
+  S->numRows = nRows;
+
+  /* Assign Number of Columns */
+  S->numCols = nColumns;
+
+  /* Assign Data pointer */
+  S->pData = pData;
+}
+
+/**   
+ * @} end of MatrixInit group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c
new file mode 100644
index 000000000..7e116590a
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_mat_init_q31.c   
+*   
+* Description:	Q31 matrix initialization.   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @defgroup MatrixInit Matrix Initialization   
+ *   
+ */
+
+/**   
+ * @addtogroup MatrixInit   
+ * @{   
+ */
+
+  /**   
+   * @brief  Q31 matrix initialization.   
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.   
+   * @param[in]     nRows          number of rows in the matrix.   
+   * @param[in]     nColumns       number of columns in the matrix.   
+   * @param[in]     *pData	   points to the matrix data array.   
+   * @return        none   
+   */
+
+void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData)
+{
+  /* Assign Number of Rows */
+  S->numRows = nRows;
+
+  /* Assign Number of Columns */
+  S->numCols = nColumns;
+
+  /* Assign Data pointer */
+  S->pData = pData;
+}
+
+/**   
+ * @} end of MatrixInit group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c
new file mode 100644
index 000000000..6a1e0e441
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c
@@ -0,0 +1,665 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_inverse_f32.c   
+*   
+* Description:	Floating-point matrix inverse.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @defgroup MatrixInv Matrix Inverse   
+ *   
+ * Computes the inverse of a matrix.   
+ *   
+ * The inverse is defined only if the input matrix is square and non-singular (the determinant   
+ * is non-zero). The function checks that the input and output matrices are square and of the   
+ * same size.   
+ *   
+ * Matrix inversion is numerically sensitive and the CMSIS DSP library only supports matrix   
+ * inversion of floating-point matrices.   
+ *   
+ * \par Algorithm   
+ * The Gauss-Jordan method is used to find the inverse.   
+ * The algorithm performs a sequence of elementary row-operations till it   
+ * reduces the input matrix to an identity matrix. Applying the same sequence   
+ * of elementary row-operations to an identity matrix yields the inverse matrix.   
+ * If the input matrix is singular, then the algorithm terminates and returns error status   
+ * ARM_MATH_SINGULAR.   
+ * \image html MatrixInverse.gif "Matrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method"   
+ */
+
+/**   
+ * @addtogroup MatrixInv   
+ * @{   
+ */
+
+/**   
+ * @brief Floating-point matrix inverse.   
+ * @param[in]       *pSrc points to input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns   
+ * ARM_MATH_SIZE_MISMATCH if the input matrix is not square or if the size   
+ * of the output matrix does not match the size of the input matrix.   
+ * If the input matrix is found to be singular (non-invertible), then the function returns   
+ * ARM_MATH_SINGULAR.  Otherwise, the function returns ARM_MATH_SUCCESS.   
+ */
+
+arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  float32_t *pInT1, *pInT2;                      /* Temporary input data matrix pointer */
+  float32_t *pInT3, *pInT4;                      /* Temporary output data matrix pointer */
+  float32_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst;  /* Temporary input and output data matrix pointer */
+  uint32_t numRows = pSrc->numRows;              /* Number of rows in the matrix  */
+  uint32_t numCols = pSrc->numCols;              /* Number of Cols in the matrix  */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t Xchg, in = 0.0f, in1;                /* Temporary input values  */
+  uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l;      /* loop counters */
+  arm_status status;                             /* status of matrix inverse */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
+     || (pSrc->numRows != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+
+    /*--------------------------------------------------------------------------------------------------------------   
+	 * Matrix Inverse can be solved using elementary row operations.   
+	 *   
+	 *	Gauss-Jordan Method:   
+	 *   
+	 *	   1. First combine the identity matrix and the input matrix separated by a bar to form an   
+	 *        augmented matrix as follows:   
+	 *				        _ 	      	       _         _	       _   
+	 *					   |  a11  a12 | 1   0  |       |  X11 X12  |   
+	 *					   |           |        |   =   |           |   
+	 *					   |_ a21  a22 | 0   1 _|       |_ X21 X21 _|   
+	 *   
+	 *		2. In our implementation, pDst Matrix is used as identity matrix.   
+	 *   
+	 *		3. Begin with the first row. Let i = 1.   
+	 *   
+	 *	    4. Check to see if the pivot for row i is zero.   
+	 *		   The pivot is the element of the main diagonal that is on the current row.   
+	 *		   For instance, if working with row i, then the pivot element is aii.   
+	 *		   If the pivot is zero, exchange that row with a row below it that does not   
+	 *		   contain a zero in column i. If this is not possible, then an inverse   
+	 *		   to that matrix does not exist.   
+	 *   
+	 *	    5. Divide every element of row i by the pivot.   
+	 *   
+	 *	    6. For every row below and  row i, replace that row with the sum of that row and   
+	 *		   a multiple of row i so that each new element in column i below row i is zero.   
+	 *   
+	 *	    7. Move to the next row and column and repeat steps 2 through 5 until you have zeros   
+	 *		   for every element below and above the main diagonal.   
+	 *   
+	 *		8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc).   
+	 *		   Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst).   
+	 *----------------------------------------------------------------------------------------------------------------*/
+
+    /* Working pointer for destination matrix */
+    pInT2 = pOut;
+
+    /* Loop over the number of rows */
+    rowCnt = numRows;
+
+    /* Making the destination matrix as identity matrix */
+    while(rowCnt > 0u)
+    {
+      /* Writing all zeroes in lower triangle of the destination matrix */
+      j = numRows - rowCnt;
+      while(j > 0u)
+      {
+        *pInT2++ = 0.0f;
+        j--;
+      }
+
+      /* Writing all ones in the diagonal of the destination matrix */
+      *pInT2++ = 1.0f;
+
+      /* Writing all zeroes in upper triangle of the destination matrix */
+      j = rowCnt - 1u;
+      while(j > 0u)
+      {
+        *pInT2++ = 0.0f;
+        j--;
+      }
+
+      /* Decrement the loop counter */
+      rowCnt--;
+    }
+
+    /* Loop over the number of columns of the input matrix.   
+       All the elements in each column are processed by the row operations */
+    loopCnt = numCols;
+
+    /* Index modifier to navigate through the columns */
+    l = 0u;
+
+    while(loopCnt > 0u)
+    {
+      /* Check if the pivot element is zero..   
+       * If it is zero then interchange the row with non zero row below.   
+       * If there is no non zero element to replace in the rows below,   
+       * then the matrix is Singular. */
+
+      /* Working pointer for the input matrix that points   
+       * to the pivot element of the particular row  */
+      pInT1 = pIn + (l * numCols);
+
+      /* Working pointer for the destination matrix that points   
+       * to the pivot element of the particular row  */
+      pInT3 = pOut + (l * numCols);
+
+      /* Temporary variable to hold the pivot value */
+      in = *pInT1;
+
+      /* Destination pointer modifier */
+      k = 1u;
+
+      /* Check if the pivot element is zero */
+      if(*pInT1 == 0.0f)
+      {
+        /* Loop over the number rows present below */
+        i = numRows - (l + 1u);
+
+        while(i > 0u)
+        {
+          /* Update the input and destination pointers */
+          pInT2 = pInT1 + (numCols * l);
+          pInT4 = pInT3 + (numCols * k);
+
+          /* Check if there is a non zero pivot element to   
+           * replace in the rows below */
+          if(*pInT2 != 0.0f)
+          {
+            /* Loop over number of columns   
+             * to the right of the pilot element */
+            j = numCols - l;
+
+            while(j > 0u)
+            {
+              /* Exchange the row elements of the input matrix */
+              Xchg = *pInT2;
+              *pInT2++ = *pInT1;
+              *pInT1++ = Xchg;
+
+              /* Decrement the loop counter */
+              j--;
+            }
+
+            /* Loop over number of columns of the destination matrix */
+            j = numCols;
+
+            while(j > 0u)
+            {
+              /* Exchange the row elements of the destination matrix */
+              Xchg = *pInT4;
+              *pInT4++ = *pInT3;
+              *pInT3++ = Xchg;
+
+              /* Decrement the loop counter */
+              j--;
+            }
+
+            /* Flag to indicate whether exchange is done or not */
+            flag = 1u;
+
+            /* Break after exchange is done */
+            break;
+          }
+
+          /* Update the destination pointer modifier */
+          k++;
+
+          /* Decrement the loop counter */
+          i--;
+        }
+      }
+
+      /* Update the status if the matrix is singular */
+      if((flag != 1u) && (in == 0.0f))
+      {
+        status = ARM_MATH_SINGULAR;
+
+        break;
+      }
+
+      /* Points to the pivot row of input and destination matrices */
+      pPivotRowIn = pIn + (l * numCols);
+      pPivotRowDst = pOut + (l * numCols);
+
+      /* Temporary pointers to the pivot row pointers */
+      pInT1 = pPivotRowIn;
+      pInT2 = pPivotRowDst;
+
+      /* Pivot element of the row */
+      in = *(pIn + (l * numCols));
+
+      /* Loop over number of columns   
+       * to the right of the pilot element */
+      j = (numCols - l);
+
+      while(j > 0u)
+      {
+        /* Divide each element of the row of the input matrix   
+         * by the pivot element */
+        in1 = *pInT1;
+        *pInT1++ = in1 / in;
+
+        /* Decrement the loop counter */
+        j--;
+      }
+
+      /* Loop over number of columns of the destination matrix */
+      j = numCols;
+
+      while(j > 0u)
+      {
+        /* Divide each element of the row of the destination matrix   
+         * by the pivot element */
+        in1 = *pInT2;
+        *pInT2++ = in1 / in;
+
+        /* Decrement the loop counter */
+        j--;
+      }
+
+      /* Replace the rows with the sum of that row and a multiple of row i   
+       * so that each new element in column i above row i is zero.*/
+
+      /* Temporary pointers for input and destination matrices */
+      pInT1 = pIn;
+      pInT2 = pOut;
+
+      /* index used to check for pivot element */
+      i = 0u;
+
+      /* Loop over number of rows */
+      /*  to be replaced by the sum of that row and a multiple of row i */
+      k = numRows;
+
+      while(k > 0u)
+      {
+        /* Check for the pivot element */
+        if(i == l)
+        {
+          /* If the processing element is the pivot element,   
+             only the columns to the right are to be processed */
+          pInT1 += numCols - l;
+
+          pInT2 += numCols;
+        }
+        else
+        {
+          /* Element of the reference row */
+          in = *pInT1;
+
+          /* Working pointers for input and destination pivot rows */
+          pPRT_in = pPivotRowIn;
+          pPRT_pDst = pPivotRowDst;
+
+          /* Loop over the number of columns to the right of the pivot element,   
+             to replace the elements in the input matrix */
+          j = (numCols - l);
+
+          while(j > 0u)
+          {
+            /* Replace the element by the sum of that row   
+               and a multiple of the reference row  */
+            in1 = *pInT1;
+            *pInT1++ = in1 - (in * *pPRT_in++);
+
+            /* Decrement the loop counter */
+            j--;
+          }
+
+          /* Loop over the number of columns to   
+             replace the elements in the destination matrix */
+          j = numCols;
+
+          while(j > 0u)
+          {
+            /* Replace the element by the sum of that row   
+               and a multiple of the reference row  */
+            in1 = *pInT2;
+            *pInT2++ = in1 - (in * *pPRT_pDst++);
+
+            /* Decrement the loop counter */
+            j--;
+          }
+
+        }
+
+        /* Increment the temporary input pointer */
+        pInT1 = pInT1 + l;
+
+        /* Decrement the loop counter */
+        k--;
+
+        /* Increment the pivot index */
+        i++;
+      }
+
+      /* Increment the input pointer */
+      pIn++;
+
+      /* Decrement the loop counter */
+      loopCnt--;
+
+      /* Increment the index modifier */
+      l++;
+    }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t Xchg, in = 0.0f;                     /* Temporary input values  */
+  uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l;      /* loop counters */
+  arm_status status;                             /* status of matrix inverse */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
+     || (pSrc->numRows != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+  {
+
+    /*--------------------------------------------------------------------------------------------------------------      
+	 * Matrix Inverse can be solved using elementary row operations.       
+	 *       
+	 *	Gauss-Jordan Method:      
+	 *	 	      
+	 *	   1. First combine the identity matrix and the input matrix separated by a bar to form an       
+	 *        augmented matrix as follows:       
+	 *				        _  _	      _	    _	   _   _         _	       _      
+	 *					   |  |  a11  a12  | | | 1   0  |   |       |  X11 X12  |        
+	 *					   |  |            | | |        |   |   =   |           |       
+	 *					   |_ |_ a21  a22 _| | |_0   1 _|  _|       |_ X21 X21 _|      
+	 *					         
+	 *		2. In our implementation, pDst Matrix is used as identity matrix.   
+	 *      
+	 *		3. Begin with the first row. Let i = 1.      
+	 *      
+	 *	    4. Check to see if the pivot for row i is zero.      
+	 *		   The pivot is the element of the main diagonal that is on the current row.      
+	 *		   For instance, if working with row i, then the pivot element is aii.      
+	 *		   If the pivot is zero, exchange that row with a row below it that does not       
+	 *		   contain a zero in column i. If this is not possible, then an inverse       
+	 *		   to that matrix does not exist.      
+	 *	      
+	 *	    5. Divide every element of row i by the pivot.      
+	 *	      
+	 *	    6. For every row below and  row i, replace that row with the sum of that row and       
+	 *		   a multiple of row i so that each new element in column i below row i is zero.      
+	 *	      
+	 *	    7. Move to the next row and column and repeat steps 2 through 5 until you have zeros      
+	 *		   for every element below and above the main diagonal.       
+	 *		   		         
+	 *		8. Now an identical matrix is formed to the left of the bar(input matrix, src).      
+	 *		   Therefore, the matrix to the right of the bar is our solution(dst matrix, dst).        
+	 *----------------------------------------------------------------------------------------------------------------*/
+
+    /* Working pointer for destination matrix */
+    pInT2 = pOut;
+
+    /* Loop over the number of rows */
+    rowCnt = numRows;
+
+    /* Making the destination matrix as identity matrix */
+    while(rowCnt > 0u)
+    {
+      /* Writing all zeroes in lower triangle of the destination matrix */
+      j = numRows - rowCnt;
+      while(j > 0u)
+      {
+        *pInT2++ = 0.0f;
+        j--;
+      }
+
+      /* Writing all ones in the diagonal of the destination matrix */
+      *pInT2++ = 1.0f;
+
+      /* Writing all zeroes in upper triangle of the destination matrix */
+      j = rowCnt - 1u;
+      while(j > 0u)
+      {
+        *pInT2++ = 0.0f;
+        j--;
+      }
+
+      /* Decrement the loop counter */
+      rowCnt--;
+    }
+
+    /* Loop over the number of columns of the input matrix.    
+       All the elements in each column are processed by the row operations */
+    loopCnt = numCols;
+
+    /* Index modifier to navigate through the columns */
+    l = 0u;
+    //for(loopCnt = 0u; loopCnt < numCols; loopCnt++)  
+    while(loopCnt > 0u)
+    {
+      /* Check if the pivot element is zero..   
+       * If it is zero then interchange the row with non zero row below.  
+       * If there is no non zero element to replace in the rows below,  
+       * then the matrix is Singular. */
+
+      /* Working pointer for the input matrix that points    
+       * to the pivot element of the particular row  */
+      pInT1 = pIn + (l * numCols);
+
+      /* Working pointer for the destination matrix that points    
+       * to the pivot element of the particular row  */
+      pInT3 = pOut + (l * numCols);
+
+      /* Temporary variable to hold the pivot value */
+      in = *pInT1;
+
+      /* Destination pointer modifier */
+      k = 1u;
+
+      /* Check if the pivot element is zero */
+      if(*pInT1 == 0.0f)
+      {
+        /* Loop over the number rows present below */
+        for (i = (l + 1u); i < numRows; i++)
+        {
+          /* Update the input and destination pointers */
+          pInT2 = pInT1 + (numCols * l);
+          pInT4 = pInT3 + (numCols * k);
+
+          /* Check if there is a non zero pivot element to    
+           * replace in the rows below */
+          if(*pInT2 != 0.0f)
+          {
+            /* Loop over number of columns    
+             * to the right of the pilot element */
+            for (j = 0u; j < (numCols - l); j++)
+            {
+              /* Exchange the row elements of the input matrix */
+              Xchg = *pInT2;
+              *pInT2++ = *pInT1;
+              *pInT1++ = Xchg;
+            }
+
+            for (j = 0u; j < numCols; j++)
+            {
+              Xchg = *pInT4;
+              *pInT4++ = *pInT3;
+              *pInT3++ = Xchg;
+            }
+
+            /* Flag to indicate whether exchange is done or not */
+            flag = 1u;
+
+            /* Break after exchange is done */
+            break;
+          }
+
+          /* Update the destination pointer modifier */
+          k++;
+        }
+      }
+
+      /* Update the status if the matrix is singular */
+      if((flag != 1u) && (in == 0.0f))
+      {
+        status = ARM_MATH_SINGULAR;
+
+        break;
+      }
+
+      /* Points to the pivot row of input and destination matrices */
+      pPivotRowIn = pIn + (l * numCols);
+      pPivotRowDst = pOut + (l * numCols);
+
+      /* Temporary pointers to the pivot row pointers */
+      pInT1 = pPivotRowIn;
+      pInT2 = pPivotRowDst;
+
+      /* Pivot element of the row */
+      in = *(pIn + (l * numCols));
+
+      /* Loop over number of columns    
+       * to the right of the pilot element */
+      for (j = 0u; j < (numCols - l); j++)
+      {
+        /* Divide each element of the row of the input matrix    
+         * by the pivot element */
+        *pInT1++ = *pInT1 / in;
+      }
+      for (j = 0u; j < numCols; j++)
+      {
+        /* Divide each element of the row of the destination matrix    
+         * by the pivot element */
+        *pInT2++ = *pInT2 / in;
+      }
+
+      /* Replace the rows with the sum of that row and a multiple of row i    
+       * so that each new element in column i above row i is zero.*/
+
+      /* Temporary pointers for input and destination matrices */
+      pInT1 = pIn;
+      pInT2 = pOut;
+
+      for (i = 0u; i < numRows; i++)
+      {
+        /* Check for the pivot element */
+        if(i == l)
+        {
+          /* If the processing element is the pivot element,    
+             only the columns to the right are to be processed */
+          pInT1 += numCols - l;
+          pInT2 += numCols;
+        }
+        else
+        {
+          /* Element of the reference row */
+          in = *pInT1;
+
+          /* Working pointers for input and destination pivot rows */
+          pPRT_in = pPivotRowIn;
+          pPRT_pDst = pPivotRowDst;
+
+          /* Loop over the number of columns to the right of the pivot element,    
+             to replace the elements in the input matrix */
+          for (j = 0u; j < (numCols - l); j++)
+          {
+            /* Replace the element by the sum of that row    
+               and a multiple of the reference row  */
+            *pInT1++ = *pInT1 - (in * *pPRT_in++);
+          }
+          /* Loop over the number of columns to    
+             replace the elements in the destination matrix */
+          for (j = 0u; j < numCols; j++)
+          {
+            /* Replace the element by the sum of that row    
+               and a multiple of the reference row  */
+            *pInT2++ = *pInT2 - (in * *pPRT_pDst++);
+          }
+
+        }
+        /* Increment the temporary input pointer */
+        pInT1 = pInT1 + l;
+      }
+      /* Increment the input pointer */
+      pIn++;
+
+      /* Decrement the loop counter */
+      loopCnt--;
+      /* Increment the index modifier */
+      l++;
+    }
+
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+    if((flag != 1u) && (in == 0.0f))
+    {
+      status = ARM_MATH_SINGULAR;
+    }
+  }
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixInv group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c
new file mode 100644
index 000000000..c91603249
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c
@@ -0,0 +1,270 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_mult_f32.c   
+*   
+* Description:  Floating-point matrix multiplication.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @defgroup MatrixMult Matrix Multiplication   
+ *   
+ * Multiplies two matrices.   
+ *   
+ * \image html MatrixMultiplication.gif "Multiplication of two 3 x 3 matrices"   
+   
+ * Matrix multiplication is only defined if the number of columns of the   
+ * first matrix equals the number of rows of the second matrix.   
+ * Multiplying an M x N matrix with an N x P matrix results   
+ * in an M x P matrix.   
+ * When matrix size checking is enabled, the functions check: (1) that the inner dimensions of   
+ * pSrcA and pSrcB are equal; and (2) that the size of the output   
+ * matrix equals the outer dimensions of pSrcA and pSrcB.   
+ */
+
+
+/**   
+ * @addtogroup MatrixMult   
+ * @{   
+ */
+
+/**   
+ * @brief Floating-point matrix multiplication.   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ */
+
+arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A */
+  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B */
+  float32_t *pInA = pSrcA->pData;                /* input data matrix pointer A  */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  float32_t *px;                                 /* Temporary output data matrix pointer */
+  float32_t sum;                                 /* Accumulator */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set   
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      j = 0u;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0.0f;
+
+        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+        pIn1 = pInA;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        colCnt = numColsA >> 2;
+
+        /* matrix multiplication        */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += *pIn1++ * (*pIn2);
+          pIn2 += numColsB;
+          sum += *pIn1++ * (*pIn2);
+          pIn2 += numColsB;
+          sum += *pIn1++ * (*pIn2);
+          pIn2 += numColsB;
+          sum += *pIn1++ * (*pIn2);
+          pIn2 += numColsB;
+
+          /* Decrement the loop count */
+          colCnt--;
+        }
+
+        /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        colCnt = numColsA % 0x4u;
+
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += *pIn1++ * (*pIn2);
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Store the result in the destination buffer */
+        *px++ = sum;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        j++;
+        pIn2 = pSrcB->pData + j;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t *pInB = pSrcB->pData;                /* input data matrix pointer B */
+  uint16_t col, i = 0u, row = numRowsA, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pInA with each column in pInB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set    
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0.0f;
+
+        /* Initialize the pointer pIn1 to point to the starting address of the row being processed */
+        pIn1 = pInA;
+
+        /* Matrix A columns number of MAC operations are to be performed */
+        colCnt = numColsA;
+
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += *pIn1++ * (*pIn2);
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Store the result in the destination buffer */
+        *px++ = sum;
+
+        /* Decrement the column loop counter */
+        col--;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        pIn2 = pInB + (numColsB - col);
+
+      } while(col > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+      /* Update the pointer pInA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixMult group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c
new file mode 100644
index 000000000..e97c88844
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c
@@ -0,0 +1,284 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_mult_fast_q15.c   
+*   
+* Description:	 Q15 matrix multiplication (fast variant)   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixMult   
+ * @{   
+ */
+
+
+/**   
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @param[in]		*pState points to the array for storing intermediate results   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The difference between the function arm_mat_mult_q15() and this fast variant is that   
+ * the fast variant use a 32-bit rather than a 64-bit accumulator.   
+ * The result of each 1.15 x 1.15 multiplication is truncated to   
+ * 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30   
+ * format. Finally, the accumulator is saturated and converted to a 1.15 result.   
+ *   
+ * \par   
+ * The fast version has the same overflow behavior as the standard version but provides   
+ * less precision since it discards the low 16 bits of each multiplication result.   
+ * In order to avoid overflows completely the input signals must be scaled down.   
+ * Scale down one of the input matrices by log2(numColsA) bits to   
+ * avoid overflows, as a total of numColsA additions are computed internally for each   
+ * output element.   
+ *   
+ * \par   
+ * See arm_mat_mult_q15() for a slower implementation of this function   
+ * which uses 64-bit accumulation to provide higher precision.   
+ */
+
+arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState)
+{
+  q31_t sum;                                     /* accumulator */
+  q31_t in;                                      /* Temporary variable to hold the input value */
+  q15_t *pSrcBT = pState;                        /* input data matrix pointer for transpose */
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
+//  q15_t *pDst = pDst->pData;                   /* output data matrix pointer */   
+  q15_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  uint16_t numRowsB = pSrcB->numRows;            /* number of rows of input matrix A    */
+  uint16_t col, i = 0u, row = numRowsB, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose */
+    do
+    {
+      /* Apply loop unrolling and exchange the columns with row elements */
+      col = numColsB >> 2;
+
+      /* The pointer px is set to starting address of the column being processed */
+      px = pSrcBT + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while(col > 0u)
+      {
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) in;
+
+#else
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *px = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) in;
+
+#else
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *px = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      col = numColsB % 0x4u;
+
+      while(col > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pInB++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* Reset the variables for the usage in the following multiplication process */
+    row = numRowsA;
+    i = 0u;
+    px = pDst->pData;
+
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set   
+       ** to the starting address of the transposed pSrcB data */
+      pInB = pSrcBT;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 2 MACs simultaneously. */
+        colCnt = numColsA >> 1;
+
+        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+        pInA = pSrcA->pData + i;
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum = __SMLAD(*__SIMD32(pInA)++, *__SIMD32(pInB)++, sum);
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* process odd column samples */
+        if((numColsA & 0x1u) > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += ((q31_t) * pInA * (*pInB++));
+        }
+
+        /* Saturate and store the result in the destination buffer */
+        *px = (q15_t) (sum >> 15);
+        px++;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+      i = i + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixMult group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c
new file mode 100644
index 000000000..8a6ff617e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c
@@ -0,0 +1,202 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_mult_fast_q31.c   
+*   
+* Description:	 Q31 matrix multiplication (fast variant).   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixMult   
+ * @{   
+ */
+
+/**   
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The difference between the function arm_mat_mult_q31() and this fast variant is that   
+ * the fast variant use a 32-bit rather than a 64-bit accumulator.   
+ * The result of each 1.31 x 1.31 multiplication is truncated to   
+ * 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30   
+ * format. Finally, the accumulator is saturated and converted to a 1.31 result.   
+ *   
+ * \par   
+ * The fast version has the same overflow behavior as the standard version but provides   
+ * less precision since it discards the low 32 bits of each multiplication result.   
+ * In order to avoid overflows completely the input signals must be scaled down.   
+ * Scale down one of the input matrices by log2(numColsA) bits to   
+ * avoid overflows, as a total of numColsA additions are computed internally for each   
+ * output element.   
+ *   
+ * \par   
+ * See arm_mat_mult_q31() for a slower implementation of this function   
+ * which uses 64-bit accumulation to provide higher precision.   
+ */
+
+arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q31_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */
+//  q31_t *pSrcB = pSrcB->pData;                    /* input data matrix pointer B */   
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q31_t *px;                                     /* Temporary output data matrix pointer */
+  q31_t sum;                                     /* Accumulator */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set   
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      j = 0u;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Initiate the pointer pIn1 to point to the starting address of pInA */
+        pIn1 = pInA;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        colCnt = numColsA >> 2;
+
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * pIn1++ * (*pIn2))) >> 32);
+          pIn2 += numColsB;
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * pIn1++ * (*pIn2))) >> 32);
+          pIn2 += numColsB;
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * pIn1++ * (*pIn2))) >> 32);
+          pIn2 += numColsB;
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * pIn1++ * (*pIn2))) >> 32);
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* If the columns of pSrcA is not a multiple of 4, compute any remaining output samples here.   
+         ** No loop unrolling is used. */
+        colCnt = numColsA % 0x4u;
+
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * pIn1++ * (*pIn2))) >> 32);
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Convert the result from 2.30 to 1.31 format and store in destination buffer */
+        *px++ = sum << 1;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        j++;
+        pIn2 = pSrcB->pData + j;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+      /* Update the pointer pInA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixMult group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c
new file mode 100644
index 000000000..224d81519
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c
@@ -0,0 +1,378 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_mult_q15.c   
+*   
+* Description:	 Q15 matrix multiplication.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixMult   
+ * @{   
+ */
+
+
+/**   
+ * @brief Q15 matrix multiplication   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @param[in]		*pState points to the array for storing intermediate results  
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator. The inputs to the   
+ * multiplications are in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate   
+ * results are accumulated in a 64-bit accumulator in 34.30 format. This approach   
+ * provides 33 guard bits and there is no risk of overflow. The 34.30 result is then   
+ * truncated to 34.15 format by discarding the low 15 bits and then saturated to   
+ * 1.15 format.   
+ *   
+ * \par   
+ * Refer to arm_mat_mult_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.   
+ *   
+ */
+
+arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState)
+{
+  q63_t sum;                                     /* accumulator */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in;                                      /* Temporary variable to hold the input value */
+  q15_t *pSrcBT = pState;                        /* input data matrix pointer for transpose */
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
+  q15_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  uint16_t numRowsB = pSrcB->numRows;            /* number of rows of input matrix A    */
+  uint16_t col, i = 0u, row = numRowsB, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose */
+    do
+    {
+      /* Apply loop unrolling and exchange the columns with row elements */
+      col = numColsB >> 2;
+
+      /* The pointer px is set to starting address of the column being processed */
+      px = pSrcBT + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while(col > 0u)
+      {
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) in;
+
+#else
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *px = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) in;
+
+#else
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *px = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      col = numColsB % 0x4u;
+
+      while(col > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pInB++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* Reset the variables for the usage in the following multiplication process */
+    row = numRowsA;
+    i = 0u;
+    px = pDst->pData;
+
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set   
+       ** to the starting address of the transposed pSrcB data */
+      pInB = pSrcBT;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 2 MACs simultaneously. */
+        colCnt = numColsA >> 1;
+
+        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+        pInA = pSrcA->pData + i;
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum = __SMLALD(*__SIMD32(pInA)++, *__SIMD32(pInB)++, sum);
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* process odd column samples */
+        if((numColsA & 0x1u) > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += ((q31_t) * pInA * (*pInB++));
+        }
+
+        /* Saturate and store the result in the destination buffer */
+        *px = (q15_t) (__SSAT((sum >> 15), 16));
+        px++;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+      i = i + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q15_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q15_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t col, i = 0u, row = numRowsA, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set         
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Initiate the pointer pIn1 to point to the starting address of pSrcA */
+        pIn1 = pInA;
+
+        /* Matrix A columns number of MAC operations are to be performed */
+        colCnt = numColsA;
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum += (q31_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Convert the result from 34.30 to 1.15 format and store the saturated value in destination buffer */
+        /* Saturate and store the result in the destination buffer */
+        *px++ = (q15_t) __SSAT((sum >> 15), 16);
+
+        /* Decrement the column loop counter */
+        col--;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        pIn2 = pInB + (numColsB - col);
+
+      } while(col > 0u);
+
+      /* Update the pointer pSrcA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixMult group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c
new file mode 100644
index 000000000..51999ebbc
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c
@@ -0,0 +1,278 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_mult_q31.c   
+*   
+* Description:	 Q31 matrix multiplication.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixMult   
+ * @{   
+ */
+
+/**   
+ * @brief Q31 matrix multiplication   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate   
+ * multiplication results but provides only a single guard bit. There is no saturation   
+ * on intermediate additions. Thus, if the accumulator overflows it wraps around and   
+ * distorts the result. The input signals should be scaled down to avoid intermediate   
+ * overflows. The input is thus scaled down by log2(numColsA) bits   
+ * to avoid overflows, as a total of numColsA additions are performed internally.   
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.   
+ *   
+ * \par   
+ * See arm_mat_mult_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.   
+ *   
+ */
+
+arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q31_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q31_t *px;                                     /* Temporary output data matrix pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set   
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      j = 0u;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Initiate the pointer pIn1 to point to the starting address of pInA */
+        pIn1 = pInA;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        colCnt = numColsA >> 2;
+
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          sum += (q63_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          sum += (q63_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          sum += (q63_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* If the columns of pSrcA is not a multiple of 4, compute any remaining output samples here.   
+         ** No loop unrolling is used. */
+        colCnt = numColsA % 0x4u;
+
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Convert the result from 2.62 to 1.31 format and store in destination buffer */
+        *px++ = (q31_t) (sum >> 31);
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        j++;
+        pIn2 = (pSrcB->pData) + j;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */
+  uint16_t col, i = 0u, row = numRowsA, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set         
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Initiate the pointer pIn1 to point to the starting address of pInA */
+        pIn1 = pInA;
+
+        /* Matrix A columns number of MAC operations are to be performed */
+        colCnt = numColsA;
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Convert the result from 2.62 to 1.31 format and store in destination buffer */
+        *px++ = (q31_t) (sum >> 31);
+
+        /* Decrement the column loop counter */
+        col--;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        pIn2 = pInB + (numColsB - col);
+
+      } while(col > 0u);
+
+#endif
+
+      /* Update the pointer pInA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixMult group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c
new file mode 100644
index 000000000..39d1ff9cf
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c
@@ -0,0 +1,156 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_mat_scale_f32.c   
+*   
+* Description:	Multiplies a floating-point matrix by a scalar.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @defgroup MatrixScale Matrix Scale   
+ *   
+ * Multiplies a matrix by a scalar.  This is accomplished by multiplying each element in the   
+ * matrix by the scalar.  For example:   
+ * \image html MatrixScale.gif "Matrix Scaling of a 3 x 3 matrix"   
+ *   
+ * The function checks to make sure that the input and output matrices are of the same size.   
+ *   
+ * In the fixed-point Q15 and Q31 functions, scale is represented by   
+ * a fractional multiplication scaleFract and an arithmetic shift shift.   
+ * The shift allows the gain of the scaling operation to exceed 1.0.   
+ * The overall scale factor applied to the fixed-point data is   
+ * 
   
+ *     scale = scaleFract * 2^shift.   
+ * 
   
+ */
+
+/**   
+ * @addtogroup MatrixScale   
+ * @{   
+ */
+
+/**   
+ * @brief Floating-point matrix scaling.   
+ * @param[in]       *pSrc points to input matrix structure   
+ * @param[in]       scale scale factor to be applied    
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either ARM_MATH_SIZE_MISMATCH    
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ */
+
+arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix scaling     */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * scale */
+      /* Scaling and results are stored in the destination buffer. */
+      *pOut++ = (*pIn++) * scale;
+      *pOut++ = (*pIn++) * scale;
+      *pOut++ = (*pIn++) * scale;
+      *pOut++ = (*pIn++) * scale;
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * scale */
+      /* The results are stored in the destination buffer. */
+      *pOut++ = (*pIn++) * scale;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixScale group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c
new file mode 100644
index 000000000..aec990412
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c
@@ -0,0 +1,150 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_scale_q15.c   
+*   
+* Description:	Multiplies a Q15 matrix by a scalar.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixScale   
+ * @{   
+ */
+
+/**   
+ * @brief Q15 matrix scaling.   
+ * @param[in]       *pSrc points to input matrix   
+ * @param[in]       scaleFract fractional portion of the scale factor   
+ * @param[in]       shift number of bits to shift the result by   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The input data *pSrc and scaleFract are in 1.15 format.   
+ * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format.   
+ */
+
+arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst)
+{
+  q15_t *pIn = pSrc->pData;                      /* input data matrix pointer */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix */
+  int32_t totShift = 15 - shift;                 /* total shift to apply after scaling */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix scaling     */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch */
+  if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * k */
+      /* Scale, saturate and then store the results in the destination buffer. */
+      *pOut++ =
+        (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> totShift, 16));
+      *pOut++ =
+        (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> totShift, 16));
+      *pOut++ =
+        (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> totShift, 16));
+      *pOut++ =
+        (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> totShift, 16));
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * k */
+      /* Scale, saturate and then store the results in the destination buffer. */
+      *pOut++ =
+        (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> totShift, 16));
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixScale group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c
new file mode 100644
index 000000000..4b894af1e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c
@@ -0,0 +1,152 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_scale_q31.c   
+*   
+* Description:	Multiplies a Q31 matrix by a scalar.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixScale   
+ * @{   
+ */
+
+/**   
+ * @brief Q31 matrix scaling.   
+ * @param[in]       *pSrc points to input matrix   
+ * @param[in]       scaleFract fractional portion of the scale factor   
+ * @param[in]       shift number of bits to shift the result by   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The input data *pSrc and scaleFract are in 1.31 format.   
+ * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format.   
+ */
+
+arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn = pSrc->pData;                      /* input data matrix pointer */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q63_t out;                                     /* temporary variable to hold output value */
+  uint32_t numSamples;                           /* total number of elements in the matrix */
+  int32_t totShift = 31 - shift;                 /* shift to apply after scaling */
+  uint32_t blkCnt;                               /* loop counters  */
+  arm_status status;                             /* status of matrix scaling      */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch  */
+  if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * k */
+      /* Scale, saturate and then store the results in the destination buffer. */
+      out = ((q63_t) * pIn++ * scaleFract) >> totShift;
+      *pOut++ = clip_q63_to_q31(out);
+      out = ((q63_t) * pIn++ * scaleFract) >> totShift;
+      *pOut++ = clip_q63_to_q31(out);
+      out = ((q63_t) * pIn++ * scaleFract) >> totShift;
+      *pOut++ = clip_q63_to_q31(out);
+      out = ((q63_t) * pIn++ * scaleFract) >> totShift;
+      *pOut++ = clip_q63_to_q31(out);
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * k */
+      /* Scale, saturate and then store the results in the destination buffer. */
+      out = ((q63_t) * pIn++ * scaleFract) >> totShift;
+      *pOut++ = clip_q63_to_q31(out);
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixScale group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c
new file mode 100644
index 000000000..d2cce6820
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c
@@ -0,0 +1,151 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_sub_f32.c   
+*   
+* Description:	Floating-point matrix subtraction.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @defgroup MatrixSub Matrix Subtraction   
+ *   
+ * Subtract two matrices.   
+ * \image html MatrixSubtraction.gif "Subraction of two 3 x 3 matrices"   
+ *   
+ * The functions check to make sure that   
+ * pSrcA, pSrcB, and pDst have the same   
+ * number of rows and columns.   
+ */
+
+/**   
+ * @addtogroup MatrixSub   
+ * @{   
+ */
+
+/**   
+ * @brief Floating-point matrix subtraction   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ */
+
+arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A */
+  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer  */
+  uint32_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix subtraction */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract and then store the results in the destination buffer. */
+      *pOut++ = (*pIn1++) - (*pIn2++);
+      *pOut++ = (*pIn1++) - (*pIn2++);
+      *pOut++ = (*pIn1++) - (*pIn2++);
+      *pOut++ = (*pIn1++) - (*pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract and then store the results in the destination buffer. */
+      *pOut++ = (*pIn1++) - (*pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixSub group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c
new file mode 100644
index 000000000..5f6dd58d3
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c
@@ -0,0 +1,155 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_sub_q15.c   
+*   
+* Description:	Q15 Matrix subtraction   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixSub   
+ * @{   
+ */
+
+/**   
+ * @brief Q15 matrix subtraction.   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.   
+ */
+
+arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst)
+{
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix */
+  uint32_t blkCnt;                               /* loop counters  */
+  arm_status status;                             /* status of matrix subtraction  */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Apply loop unrolling */
+    blkCnt = numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract, Saturate and then store the results in the destination buffer. */
+      *__SIMD32(pOut)++ = __QSUB16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+      *__SIMD32(pOut)++ = __QSUB16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract and then store the results in the destination buffer. */
+      *pOut++ = (q15_t) __QSUB16(*pInA++, *pInB++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract and then store the results in the destination buffer. */
+      *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixSub group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c
new file mode 100644
index 000000000..3de675c5f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c
@@ -0,0 +1,158 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_sub_q31.c   
+*   
+* Description:	Q31 matrix subtraction   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixSub   
+ * @{   
+ */
+
+/**   
+ * @brief Q31 matrix subtraction.   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.   
+ */
+
+
+arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix subtraction */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition  */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract, saturate and then store the results in the destination buffer. */
+      *pOut++ = __QSUB(*pIn1++, *pIn2++);
+      *pOut++ = __QSUB(*pIn1++, *pIn2++);
+      *pOut++ = __QSUB(*pIn1++, *pIn2++);
+      *pOut++ = __QSUB(*pIn1++, *pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract, saturate and then store the results in the destination buffer. */
+      *pOut++ = __QSUB(*pIn1++, *pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract, saturate and then store the results in the destination buffer. */
+      *pOut++ = clip_q63_to_q31(((q63_t) (*pIn1++)) - (*pIn2++));
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixSub group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c
new file mode 100644
index 000000000..876fab68b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c
@@ -0,0 +1,213 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_trans_f32.c   
+*   
+* Description:	Floating-point matrix transpose.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+/**   
+ * @defgroup MatrixTrans Matrix Transpose   
+ *   
+ * Tranposes a matrix.   
+ * Transposing an M x N matrix flips it around the center diagonal and results in an N x M matrix.   
+ * \image html MatrixTranspose.gif "Transpose of a 3 x 3 matrix"   
+ */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixTrans   
+ * @{   
+ */
+
+/**   
+  * @brief Floating-point matrix transpose.   
+  * @param[in]  *pSrc points to the input matrix   
+  * @param[out] *pDst points to the output matrix   
+  * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH   
+  * or ARM_MATH_SUCCESS based on the outcome of size checking.   
+  */
+
+
+arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  float32_t *px;                                 /* Temporary output data matrix pointer */
+  uint16_t nRows = pSrc->numRows;                /* number of rows */
+  uint16_t nColumns = pSrc->numCols;             /* number of columns */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  uint16_t blkCnt, i = 0u, row = nRows;          /* loop counters */
+  arm_status status;                             /* status of matrix transpose  */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* Loop Unrolling */
+      blkCnt = nColumns >> 2;
+
+      /* The pointer px is set to starting address of the column being processed */
+      px = pOut + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while(blkCnt > 0u)        /* column loop */
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        blkCnt--;
+      }
+
+      /* Perform matrix transpose for last 3 samples here. */
+      blkCnt = nColumns % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        blkCnt--;
+      }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  uint16_t col, i = 0u, row = nRows;             /* loop counters */
+  arm_status status;                             /* status of matrix transpose  */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* The pointer px is set to starting address of the column being processed */
+      px = pOut + i;
+
+      /* Initialize column loop counter */
+      col = nColumns;
+
+      while(col > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);          /* row loop end  */
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixTrans group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c
new file mode 100644
index 000000000..44cb0f351
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c
@@ -0,0 +1,234 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_trans_q15.c   
+*   
+* Description:	Q15 matrix transpose.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixTrans   
+ * @{   
+ */
+
+/*   
+ * @brief Q15 matrix transpose.   
+ * @param[in]  *pSrc points to the input matrix   
+ * @param[out] *pDst points to the output matrix   
+ * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH   
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ */
+
+arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst)
+{
+  q15_t *pSrcA = pSrc->pData;                    /* input data matrix pointer */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint16_t nRows = pSrc->numRows;                /* number of nRows */
+  uint16_t nColumns = pSrc->numCols;             /* number of nColumns */
+  uint16_t col, row = nRows, i = 0u;             /* row and column loop counters */
+  arm_status status;                             /* status of matrix transpose */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in;                                      /* variable to hold temporary output  */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* Apply loop unrolling and exchange the columns with row elements */
+      col = nColumns >> 2u;
+
+      /* The pointer pOut is set to starting address of the column being processed */
+      pOut = pDst->pData + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while(col > 0u)
+      {
+        /* Read two elements from the row */
+        in = *__SIMD32(pSrcA)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *pOut = (q15_t) in;
+
+#else
+
+        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *pOut = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Read two elements from the row */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        in = *__SIMD32(pSrcA)++;
+
+#else
+
+        in = *__SIMD32(pSrcA)++;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *pOut = (q15_t) in;
+
+#else
+
+        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *pOut = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      /* Perform matrix transpose for last 3 samples here. */
+      col = nColumns % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* The pointer pOut is set to starting address of the column being processed */
+      pOut = pDst->pData + i;
+
+      /* Initialize column loop counter */
+      col = nColumns;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+      while(col > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *pOut = *pSrcA++;
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixTrans group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c
new file mode 100644
index 000000000..ef81039fb
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c
@@ -0,0 +1,205 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_trans_q31.c   
+*   
+* Description:	Q31 matrix transpose.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixTrans   
+ * @{   
+ */
+
+/*   
+  * @brief Q31 matrix transpose.   
+  * @param[in]  *pSrc points to the input matrix   
+  * @param[out] *pDst points to the output matrix   
+  * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH   
+  * or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ */
+
+arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn = pSrc->pData;                      /* input data matrix pointer  */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer  */
+  q31_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t nRows = pSrc->numRows;                /* number of nRows */
+  uint16_t nColumns = pSrc->numCols;             /* number of nColumns  */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  uint16_t blkCnt, i = 0u, row = nRows;          /* loop counters */
+  arm_status status;                             /* status of matrix transpose */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* Apply loop unrolling and exchange the columns with row elements */
+      blkCnt = nColumns >> 2u;
+
+      /* The pointer px is set to starting address of the column being processed */
+      px = pOut + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while(blkCnt > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        blkCnt--;
+      }
+
+      /* Perform matrix transpose for last 3 samples here. */
+      blkCnt = nColumns % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        blkCnt--;
+      }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  uint16_t col, i = 0u, row = nRows;             /* loop counters */
+  arm_status status;                             /* status of matrix transpose */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* The pointer px is set to starting address of the column being processed */
+      px = pOut + i;
+
+      /* Initialize column loop counter */
+      col = nColumns;
+
+      while(col > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    }
+    while(row > 0u);            /* row loop end */
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixTrans group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c
new file mode 100644
index 000000000..eb3fc24dd
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c
@@ -0,0 +1,127 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_max_f32.c   
+*   
+* Description:	Maximum value of a floating-point vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @defgroup Max Maximum   
+ *   
+ * Computes the maximum value of an array of data.    
+ * The function returns both the maximum value and its position within the array.    
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.   
+ */
+
+/**   
+ * @addtogroup Max   
+ * @{   
+ */
+
+
+/**   
+ * @brief Maximum value of a floating-point vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult maximum value returned here   
+ * @param[out]      *pIndex index of maximum value returned here   
+ * @return none.   
+ */
+
+void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex)
+{
+  float32_t maxVal, out;                         /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop over blockSize number of values */
+  blkCnt = (blockSize - 1u);
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal)
+    {
+      /* Update the maximum value and it's index */
+      out = maxVal;
+      outIndex = blockSize - blkCnt;
+    }
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  } while(blkCnt > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal)
+    {
+      /* Update the maximum value and it's index */
+      out = maxVal;
+      outIndex = blockSize - blkCnt;
+    }
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  /* Store the maximum value and it's index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**   
+ * @} end of Max group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c
new file mode 100644
index 000000000..371e5970a
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c
@@ -0,0 +1,119 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_max_q15.c   
+*   
+* Description:	Maximum value of a Q15 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup Max   
+ * @{   
+ */
+
+
+/**   
+ * @brief Maximum value of a Q15 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult maximum value returned here   
+ * @param[out]      *pIndex index of maximum value returned here   
+ * @return none.   
+ */
+
+void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex)
+{
+  q15_t maxVal, out;                             /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop over blockSize number of values */
+  blkCnt = (blockSize - 1u);
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    blkCnt--;
+
+  } while(blkCnt > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal;
+      outIndex = blockSize - blkCnt;
+    }
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Store the maximum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**   
+ * @} end of Max group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c
new file mode 100644
index 000000000..38451b0df
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c
@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_max_q31.c   
+*   
+* Description:	Maximum value of a Q31 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup Max   
+ * @{   
+ */
+
+
+/**   
+ * @brief Maximum value of a Q31 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult maximum value returned here   
+ * @param[out]      *pIndex index of maximum value returned here   
+ * @return none.   
+ */
+
+void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex)
+{
+  q31_t maxVal, out;                             /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop over blockSize number of values */
+  blkCnt = (blockSize - 1u);
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  } while(blkCnt > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal = *pSrc++;
+
+    /* Compare for the maximum value */
+    if(out < maxVal)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Store the maximum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**   
+ * @} end of Max group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c
new file mode 100644
index 000000000..ff9a7c071
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c
@@ -0,0 +1,206 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_max_q7.c   
+*   
+* Description:	Maximum value of a Q7 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup Max   
+ * @{   
+ */
+
+
+/**   
+ * @brief Maximum value of a Q7 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult maximum value returned here   
+ * @param[out]      *pIndex index of maximum value returned here   
+  * @return none.   
+ */
+
+void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t res, maxVal, x0, x1, maxVal2, maxVal1;    /* Temporary variables to store the output value. */
+  uint32_t blkCnt, index1, index2, index3, indx, indxMod;       /* loop counter */
+
+  /* Initialise the index value to zero. */
+  indx = 0u;
+
+  /* Load first input value that act as reference value for comparision */
+  res = *pSrc++;
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1u) >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.  
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    indxMod = blockSize - (blkCnt * 4u);
+
+    /* Load two input values for comparision */
+    x0 = *pSrc++;
+    x1 = *pSrc++;
+
+    if(x0 < x1)
+    {
+      /* Update the maximum value and its index */
+      maxVal1 = x1;
+      index1 = indxMod + 1u;
+    }
+    else
+    {
+      /* Update the maximum value and its index */
+      maxVal1 = x0;
+      index1 = indxMod;
+    }
+
+    /* Load two input values for comparision */
+    x0 = *pSrc++;
+    x1 = *pSrc++;
+
+    if(x0 < x1)
+    {
+      /* Update the maximum value and its index */
+      maxVal2 = x1;
+      index2 = indxMod + 3u;
+    }
+    else
+    {
+      /* Update the maximum value and its index */
+      maxVal2 = x0;
+      index2 = indxMod + 2u;
+    }
+
+    if(maxVal1 < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      maxVal = maxVal2;
+      index3 = index2;
+    }
+    else
+    {
+      /* Update the maximum value and its index */
+      maxVal = maxVal1;
+      index3 = index1;
+    }
+
+    if(res < maxVal)
+    {
+      /* Update the maximum value and its index */
+      res = maxVal;
+      indx = index3;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  /* If the blockSize - 1 is not a multiple of 4, compute any remaining output samples here.  
+   ** No loop unrolling is used. */
+  blkCnt = (blockSize - 1u) % 0x04u;
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal = *pSrc++;
+
+    /* compare for the maximum value */
+    if(res < maxVal)
+    {
+      /* Update the maximum value and its index */
+      res = maxVal;
+      indx = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the maximum value and its index into destination pointers */
+  *pResult = res;
+  *pIndex = indx;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q7_t maxVal, out;                              /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop over blockSize - 1 number of values */
+  blkCnt = (blockSize - 1u);
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal;
+      outIndex = blockSize - blkCnt;
+    }
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  /* Store the maximum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of Max group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c
new file mode 100644
index 000000000..fdda942af
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c
@@ -0,0 +1,122 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_mean_f32.c   
+*   
+* Description:	Mean value of a floating-point vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @defgroup mean Mean   
+ *   
+ * Calculates the mean of the input vector. Mean is defined as the average of the elements in the vector.   
+ * The underlying algorithm is used:   
+ *   
+ * 
   
+ * 	Result = (pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]) / blockSize;   
+ * 
   
+ *   
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.   
+ */
+
+/**   
+ * @addtogroup mean   
+ * @{   
+ */
+
+
+/**   
+ * @brief Mean value of a floating-point vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult mean value returned here   
+ * @return none.   
+ */
+
+
+void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+  float32_t sum = 0.0f;                          /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
+  /* Store the result to the destination */
+  *pResult = sum / (float32_t) blockSize;
+}
+
+/**   
+ * @} end of mean group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c
new file mode 100644
index 000000000..2f31a4d5d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c
@@ -0,0 +1,119 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_mean_q15.c   
+*   
+* Description:	Mean value of a Q15 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup mean   
+ * @{   
+ */
+
+/**   
+ * @brief Mean value of a Q15 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult mean value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 32-bit internal accumulator.   
+ * The input is represented in 1.15 format and is accumulated in a 32-bit    
+ * accumulator in 17.15 format.    
+ * There is no risk of internal overflow with this approach, and the    
+ * full precision of intermediate result is preserved.    
+ * Finally, the accumulator is saturated and truncated to yield a result of 1.15 format.   
+ *   
+ */
+
+
+void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult)
+{
+  q31_t sum = 0;                                 /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
+  /* Store the result to the destination */
+  *pResult = (q15_t) (sum / blockSize);
+}
+
+/**   
+ * @} end of mean group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c
new file mode 100644
index 000000000..6692c7cfa
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c
@@ -0,0 +1,119 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_mean_q31.c   
+*   
+* Description:	Mean value of a Q31 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup mean   
+ * @{   
+ */
+
+/**   
+ * @brief Mean value of a Q31 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult mean value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *\par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * The input is represented in 1.31 format and is accumulated in a 64-bit   
+ * accumulator in 33.31 format.   
+ * There is no risk of internal overflow with this approach, and the    
+ * full precision of intermediate result is preserved.    
+ * Finally, the accumulator is truncated to yield a result of 1.31 format.   
+ *   
+ */
+
+
+void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q63_t sum = 0;                                 /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
+  /* Store the result to the destination */
+  *pResult = (q31_t) (sum / (int32_t) blockSize);
+}
+
+/**   
+ * @} end of mean group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c
new file mode 100644
index 000000000..b61d1041a
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c
@@ -0,0 +1,119 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_mean_q7.c   
+*   
+* Description:	Mean value of a Q7 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup mean   
+ * @{   
+ */
+
+/**   
+ * @brief Mean value of a Q7 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult mean value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 32-bit internal accumulator.    
+ * The input is represented in 1.7 format and is accumulated in a 32-bit   
+ * accumulator in 25.7 format.   
+ * There is no risk of internal overflow with this approach, and the    
+ * full precision of intermediate result is preserved.    
+ * Finally, the accumulator is truncated to yield a result of 1.7 format.   
+ *   
+ */
+
+
+void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult)
+{
+  q31_t sum = 0;                                 /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
+  /* Store the result to the destination */
+  *pResult = (q7_t) (sum / (int32_t) blockSize);
+}
+
+/**   
+ * @} end of mean group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c
new file mode 100644
index 000000000..b6846bc1a
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c
@@ -0,0 +1,133 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_min_f32.c   
+*   
+* Description:	Minimum value of a floating-point vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @defgroup Min Minimum   
+ *   
+ * Computes the minimum value of an array of data.    
+ * The function returns both the minimum value and its position within the array.    
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.   
+ */
+
+/**   
+ * @addtogroup Min   
+ * @{   
+ */
+
+
+/**   
+ * @brief Minimum value of a floating-point vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult minimum value returned here   
+ * @param[out]      *pIndex index of minimum value returned here   
+  * @return none.   
+ *   
+ */
+
+void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex)
+{
+  float32_t minVal, out;                         /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+
+  /* Loop over blockSize number of values */
+  blkCnt = (blockSize - 1u);
+
+  do
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal)
+    {
+      /* Update the minimum value and it's index */
+      out = minVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    blkCnt--;
+
+  } while(blkCnt > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize - 1 number of values */
+  blkCnt = (blockSize - 1u);
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal)
+    {
+      /* Update the minimum value and it's index */
+      out = minVal;
+      outIndex = blockSize - blkCnt;
+    }
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  /* Store the minimum value and it's index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**   
+ * @} end of Min group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c
new file mode 100644
index 000000000..788c8f13d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c
@@ -0,0 +1,127 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_min_q15.c   
+*   
+* Description:	Minimum value of a Q15 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+
+/**   
+ * @addtogroup Min   
+ * @{   
+ */
+
+
+/**   
+ * @brief Minimum value of a Q15 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult minimum value returned here   
+ * @param[out]      *pIndex index of minimum value returned here   
+ * @return none.   
+ *   
+ */
+
+void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex)
+{
+  q15_t minVal, out;                             /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+
+  /* Loop over blockSize number of values */
+  blkCnt = (blockSize - 1u);
+
+  do
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal)
+    {
+      /* Update the minimum value and its index */
+      out = minVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    blkCnt--;
+
+  } while(blkCnt > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize - 1 number of values */
+  blkCnt = (blockSize - 1u);
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal)
+    {
+      /* Update the minimum value and its index */
+      out = minVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  /* Store the minimum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**   
+ * @} end of Min group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c
new file mode 100644
index 000000000..5d285d00b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c
@@ -0,0 +1,125 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_min_q31.c   
+*   
+* Description:	Minimum value of a Q31 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+
+/**   
+ * @addtogroup Min   
+ * @{   
+ */
+
+
+/**   
+ * @brief Minimum value of a Q31 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult minimum value returned here   
+ * @param[out]      *pIndex index of minimum value returned here   
+ * @return none.   
+ *   
+ */
+
+void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex)
+{
+  q31_t minVal, out;                             /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = (blockSize - 1u);
+
+  do
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal)
+    {
+      /* Update the minimum value and its index */
+      out = minVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    blkCnt--;
+
+  } while(blkCnt > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize -1 number of values */
+  blkCnt = (blockSize - 1u);
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal)
+    {
+      /* Update the minimum value and its index */
+      out = minVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Store the minimum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**   
+ * @} end of Min group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c
new file mode 100644
index 000000000..da6dc7571
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c
@@ -0,0 +1,204 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_min_q7.c   
+*   
+* Description:	Minimum value of a Q7 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup Min   
+ * @{   
+ */
+
+
+/**   
+ * @brief Minimum value of a Q7 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult minimum value returned here   
+ * @param[out]      *pIndex index of minimum value returned here   
+ * @return none.   
+ *   
+ */
+
+void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t minVal, minVal1, minVal2, res, x0, x1;    /* Temporary variables to store the output value. */
+  uint32_t blkCnt, indx, index1, index2, index3, indxMod;       /* loop counter */
+
+  /* Initialise the index value to zero. */
+  indx = 0u;
+
+  /* Load first input value that act as reference value for comparision */
+  res = *pSrc++;
+
+  /* Loop over blockSize number of values */
+  blkCnt = (blockSize - 1u) >> 2u;
+
+  while(blkCnt > 0u)
+  {
+    indxMod = blockSize - (blkCnt * 4u);
+
+    /* Load two input values for comparision */
+    x0 = *pSrc++;
+    x1 = *pSrc++;
+
+    if(x0 > x1)
+    {
+      /* Update the minimum value and its index */
+      minVal1 = x1;
+      index1 = indxMod + 1u;
+    }
+    else
+    {
+      /* Update the minimum value and its index */
+      minVal1 = x0;
+      index1 = indxMod;
+    }
+
+    /* Load two input values for comparision */
+    x0 = *pSrc++;
+    x1 = *pSrc++;
+
+    if(x0 > x1)
+    {
+      /* Update the minimum value and its index */
+      minVal2 = x1;
+      index2 = indxMod + 3u;
+    }
+    else
+    {
+      /* Update the minimum value and its index */
+      minVal2 = x0;
+      index2 = indxMod + 2u;
+    }
+
+    if(minVal1 > minVal2)
+    {
+      /* Update the minimum value and its index */
+      minVal = minVal2;
+      index3 = index2;
+    }
+    else
+    {
+      /* Update the minimum value and its index */
+      minVal = minVal1;
+      index3 = index1;
+    }
+
+    if(res > minVal)
+    {
+      /* Update the minimum value and its index */
+      res = minVal;
+      indx = index3;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  blkCnt = (blockSize - 1u) % 0x04u;
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal = *pSrc++;
+
+    /* compare for the minimum value */
+    if(res > minVal)
+    {
+      /* Update the minimum value and its index */
+      res = minVal;
+      indx = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the minimum value and its index into destination pointers */
+  *pResult = res;
+  *pIndex = indx;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q7_t minVal, out;                              /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop over blockSize - 1 number of values */
+  blkCnt = (blockSize - 1u);
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal)
+    {
+      /* Update the minimum value and its index */
+      out = minVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the minimum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of Min group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c
new file mode 100644
index 000000000..70a188bce
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c
@@ -0,0 +1,135 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_power_f32.c   
+*   
+* Description:	Sum of the squares of the elements of a floating-point vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @defgroup power Power   
+ *   
+ * Calculates the sum of the squares of the elements in the input vector.   
+ * The underlying algorithm is used:   
+ *   
+ * 
   
+ * 	Result = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + pSrc[2] * pSrc[2] + ... + pSrc[blockSize-1] * pSrc[blockSize-1];   
+ * 
   
+ *  
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.    
+ */
+
+/**   
+ * @addtogroup power   
+ * @{   
+ */
+
+
+/**   
+ * @brief Sum of the squares of the elements of a floating-point vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult sum of the squares value returned here   
+ * @return none.   
+ *   
+ */
+
+
+void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+  float32_t sum = 0.0f;                          /* accumulator */
+  float32_t in;                                  /* Temporary variable to store input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* compute power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the result to the destination */
+  *pResult = sum;
+}
+
+/**   
+ * @} end of power group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c
new file mode 100644
index 000000000..3b5b8482e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c
@@ -0,0 +1,141 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_power_q15.c   
+*   
+* Description:	Sum of the squares of the elements of a Q15 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup power   
+ * @{   
+ */
+
+/**   
+ * @brief Sum of the squares of the elements of a Q15 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult sum of the squares value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.    
+ * The input is represented in 1.15 format.  
+ * Intermediate multiplication yields a 2.30 format, and this   
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.   
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the   
+ * full precision of the intermediate multiplication is preserved.   
+ * Finally, the return result is in 34.30 format.    
+ *   
+ */
+
+void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult)
+{
+  q63_t sum = 0;                                 /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in32;                                    /* Temporary variable to store input value */
+  q15_t in16;                                    /* Temporary variable to store input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in32 = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in32, in32, sum);
+    in32 = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in32, in32, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in16 = *pSrc++;
+    sum = __SMLALD(in16, in16, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t in;                                      /* Temporary variable to store input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q31_t) in * in);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Store the results in 34.30 format  */
+  *pResult = sum;
+}
+
+/**   
+ * @} end of power group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c
new file mode 100644
index 000000000..c25621ee1
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c
@@ -0,0 +1,132 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_power_q31.c   
+*   
+* Description:	Sum of the squares of the elements of a Q31 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup power   
+ * @{   
+ */
+
+/**   
+ * @brief Sum of the squares of the elements of a Q31 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult sum of the squares value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * The input is represented in 1.31 format.   
+ * Intermediate multiplication yields a 2.62 format, and this   
+ * result is truncated to 2.48 format by discarding the lower 14 bits.   
+ * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.   
+ * With 15 guard bits in the accumulator, there is no risk of overflow, and the   
+ * full precision of the intermediate multiplication is preserved.   
+ * Finally, the return result is in 16.48 format.    
+ *   
+ */
+
+void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult)
+{
+  q63_t sum = 0;                                 /* Temporary result storage */
+  q31_t in;
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power then shift intermediate results by 14 bits to maintain 16.48 format and then store the result in a temporary variable sum, providing 15 guard bits. */
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14u;
+
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14u;
+
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14u;
+
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the results in 16.48 format  */
+  *pResult = sum;
+}
+
+/**   
+ * @} end of power group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c
new file mode 100644
index 000000000..457950e2b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c
@@ -0,0 +1,137 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_power_q7.c   
+*   
+* Description:	Sum of the squares of the elements of a Q7 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup power   
+ * @{   
+ */
+
+/**   
+ * @brief Sum of the squares of the elements of a Q7 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult sum of the squares value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 32-bit internal accumulator.    
+ * The input is represented in 1.7 format.  
+ * Intermediate multiplication yields a 2.14 format, and this   
+ * result is added without saturation to an accumulator in 18.14 format.   
+ * With 17 guard bits in the accumulator, there is no risk of overflow, and the   
+ * full precision of the intermediate multiplication is preserved.   
+ * Finally, the return result is in 18.14 format.    
+ *   
+ */
+
+void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q31_t sum = 0;                                 /* Temporary result storage */
+  q7_t in;                                       /* Temporary variable to store input */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t input1;                                  /* Temporary variable to store packed input */
+  q15_t in1, in2;                                /* Temporary variables to store input */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Reading two inputs of pSrc vector and packing */
+    in1 = (q15_t) * pSrc++;
+    in2 = (q15_t) * pSrc++;
+    input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    sum = __SMLAD(input1, input1, sum);
+
+    /* Reading two inputs of pSrc vector and packing */
+    in1 = (q15_t) * pSrc++;
+    in2 = (q15_t) * pSrc++;
+    input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    sum = __SMLAD(input1, input1, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q15_t) in * in);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the result in 18.14 format  */
+  *pResult = sum;
+}
+
+/**   
+ * @} end of power group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c
new file mode 100644
index 000000000..de3ea396c
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c
@@ -0,0 +1,130 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_rms_f32.c   
+*   
+* Description:	Root mean square value of an array of F32 type   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @defgroup RMS Root mean square (RMS)   
+ *   
+ *    
+ * Calculates the Root Mean Sqaure of the elements in the input vector.   
+ * The underlying algorithm is used:   
+ *   
+ * 
   
+ * 	Result = sqrt(((pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]) / blockSize));   
+ * 
   
+ *  
+ * There are separate functions for floating point, Q31, and Q15 data types.    
+ */
+
+/**   
+ * @addtogroup RMS   
+ * @{   
+ */
+
+
+/**   
+ * @brief Root Mean Square of the elements of a floating-point vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult rms value returned here   
+ * @return none.   
+ *   
+ */
+
+void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+  float32_t sum = 0.0f;                          /* Accumulator */
+  float32_t in;                                  /* Tempoprary variable to store input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the result in a temporary variable, sum  */
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum  */
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Rms and store the result in the destination */
+  arm_sqrt_f32(sum / (float32_t) blockSize, pResult);
+}
+
+/**   
+ * @} end of RMS group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c
new file mode 100644
index 000000000..e57485fc0
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c
@@ -0,0 +1,150 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_rms_q15.c   
+*   
+* Description:	Root Mean Square of the elements of a Q15 vector. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @addtogroup RMS   
+ * @{   
+ */
+
+/**   
+ * @brief Root Mean Square of the elements of a Q15 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult rms value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * The input is represented in 1.15 format.   
+ * Intermediate multiplication yields a 2.30 format, and this   
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.   
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the   
+ * full precision of the intermediate multiplication is preserved.   
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower    
+ * 15 bits, and then saturated to yield a result in 1.15 format.   
+ *   
+ */
+
+void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult)
+{
+  q63_t sum = 0;                                 /* accumulator */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in;                                      /* temporary variable to store the input value */
+  q15_t in1;                                     /* temporary variable to store the input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in, in, sum);
+    in = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in, in, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in1 = *pSrc++;
+    sum = __SMLALD(in1, in1, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Truncating and saturating the accumulator to 1.15 format */
+  sum = __SSAT((q31_t) (sum >> 15), 16);
+
+  in1 = (q15_t) (sum / blockSize);
+
+  /* Store the result in the destination */
+  arm_sqrt_q15(in1, pResult);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t in;                                      /* temporary variable to store the input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in = *pSrc++;
+    sum += ((q31_t) in * in);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Truncating and saturating the accumulator to 1.15 format */
+  sum = __SSAT((q31_t) (sum >> 15), 16);
+
+  in = (q15_t) (sum / blockSize);
+
+  /* Store the result in the destination */
+  arm_sqrt_q15(in, pResult);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of RMS group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c
new file mode 100644
index 000000000..a2533b129
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c
@@ -0,0 +1,143 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_rms_q31.c   
+*   
+* Description:	Root Mean Square of the elements of a Q31 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @addtogroup RMS   
+ * @{   
+ */
+
+
+/**   
+ * @brief Root Mean Square of the elements of a Q31 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult rms value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ *\par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The input is represented in 1.31 format, and intermediate multiplication   
+ * yields a 2.62 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results,    
+ * but provides only a single guard bit.   
+ * There is no saturation on intermediate additions.   
+ * If the accumulator overflows, it wraps around and distorts the result.    
+ * In order to avoid overflows completely, the input signal must be scaled down by    
+ * log2(blockSize) bits, as a total of blockSize additions are performed internally.    
+ * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.   
+ *   
+ */
+
+void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q63_t sum = 0;                                 /* accumulator */
+  q31_t in;                                      /* Temporary variable to store the input */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn1 = pSrc;                            /* SrcA pointer */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the result in a temporary variable, sum */
+    in = *pIn1++;
+    sum += (q63_t) in *in;
+    in = *pIn1++;
+    sum += (q63_t) in *in;
+    in = *pIn1++;
+    sum += (q63_t) in *in;
+    in = *pIn1++;
+    sum += (q63_t) in *in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in = *pIn1++;
+    sum += (q63_t) in *in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in = *pSrc++;
+    sum += (q63_t) in *in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Convert data in 2.62 to 1.31 by 31 right shifts */
+  sum = sum >> 31;
+
+  /* Compute Rms and store the result in the destination vector */
+  arm_sqrt_q31((q31_t) (sum / (int32_t) blockSize), pResult);
+}
+
+/**   
+ * @} end of RMS group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c
new file mode 100644
index 000000000..800969702
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c
@@ -0,0 +1,222 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_std_f32.c   
+*   
+* Description:	Standard deviation of the elements of a floating-point vector. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @defgroup STD Standard deviation   
+ *   
+ * Calculates the standard deviation of the elements in the input vector.    
+ * The underlying algorithm is used:   
+ *  
+ * 
   
+ * 	Result = sqrt((sumOfSquares - sum2 / blockSize) / (blockSize - 1))  
+ *  
+ *	   where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]  
+ *  
+ *	                   sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]  
+ * 
  
+ *   
+ * There are separate functions for floating point, Q31, and Q15 data types.   
+ */
+
+/**   
+ * @addtogroup STD   
+ * @{   
+ */
+
+
+/**   
+ * @brief Standard deviation of the elements of a floating-point vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult standard deviation value returned here   
+ * @return none.   
+ *   
+ */
+
+
+void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+  float32_t sum = 0.0f;                          /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t meanOfSquares, mean, in, squareOfMean;
+  uint32_t blkCnt;                               /* loop counter */
+  float32_t *pIn;                                /* Temporary pointer */
+
+  pIn = pSrc;
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples   
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = sum / ((float32_t) blockSize - 1.0f);
+
+  /* Reset the accumulator */
+  sum = 0.0f;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Reset the input working pointer */
+  pSrc = pIn;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+  /* Compute mean of all input values */
+  mean = sum / (float32_t) blockSize;
+
+  /* Compute square of mean */
+  squareOfMean = (mean * mean) * (((float32_t) blockSize) /
+                                  ((float32_t) blockSize - 1.0f));
+
+  /* Compute standard deviation and then store the result to the destination */
+  arm_sqrt_f32((meanOfSquares - squareOfMean), pResult);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t sumOfSquares = 0.0f;                 /* Sum of squares */
+  float32_t squareOfSum;                         /* Square of Sum */
+  float32_t in;                                  /* input value */
+  float32_t var;                                 /* Temporary varaince storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += in * in;
+
+    /* C = (A[0] + A[1] + ... + A[blockSize-1]) */
+    /* Compute Sum of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute the square of sum */
+  squareOfSum = ((sum * sum) / (float32_t) blockSize);
+
+  /* Compute the variance */
+  var = ((sumOfSquares - squareOfSum) / (float32_t) (blockSize - 1.0f));
+
+  /* Compute standard deviation and then store the result to the destination */
+  arm_sqrt_f32(var, pResult);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of STD group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c
new file mode 100644
index 000000000..19d9884d3
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c
@@ -0,0 +1,229 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_std_q15.c   
+*   
+* Description:	Standard deviation of an array of Q15 type.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup STD   
+ * @{   
+ */
+
+/**   
+ * @brief Standard deviation of the elements of a Q15 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult standard deviation value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * The input is represented in 1.15 format.  
+ * Intermediate multiplication yields a 2.30 format, and this   
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.   
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the   
+ * full precision of the intermediate multiplication is preserved.   
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower    
+ * 15 bits, and then saturated to yield a result in 1.15 format.   
+ */
+
+void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult)
+{
+  q63_t sum = 0;                                 /* Accumulator */
+  q31_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */
+  q15_t mean;                                    /* mean */
+  uint32_t blkCnt;                               /* loop counter */
+  q15_t t;                                       /* Temporary variable */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn;                                    /* Temporary pointer */
+  q31_t in;                                      /* input value */
+  q15_t in1;                                     /* input value */
+
+  pIn = pSrc;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in, in, sum);
+    in = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in, in, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in1 = *pSrc++;
+    sum = __SMLALD(in1, in1, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples   
+   * and then store the result in a temporary variable, meanOfSquares. */
+  t = (q15_t) ((1.0 / (blockSize - 1)) * 16384LL);
+  sum = __SSAT((sum >> 15u), 16u);
+
+  meanOfSquares = (q31_t) ((sum * t) >> 14u);
+
+  /* Reset the accumulator */
+  sum = 0;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Reset the input working pointer */
+  pSrc = pIn;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+  /* Compute mean of all input values */
+  t = (q15_t) ((1.0 / (blockSize * (blockSize - 1))) * 32768LL);
+  mean = (q15_t) __SSAT(sum, 16u);
+
+  /* Compute square of mean */
+  squareOfMean = ((q31_t) mean * mean) >> 15;
+  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 15);
+
+  /* mean of the squares minus the square of the mean. */
+  in1 = (q15_t) (meanOfSquares - squareOfMean);
+
+  /* Compute standard deviation and store the result to the destination */
+  arm_sqrt_q15(in1, pResult);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q63_t sumOfSquares = 0;                        /* Accumulator */
+  q15_t in;                                      /* input value */
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += (in * in);
+
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples    
+   * and then store the result in a temporary variable, meanOfSquares. */
+  t = (q15_t) ((1.0 / (blockSize - 1)) * 16384LL);
+  sumOfSquares = __SSAT((sumOfSquares >> 15u), 16u);
+  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 14u);
+
+  /* Compute mean of all input values */
+  mean = (q15_t) __SSAT(sum, 16u);
+
+  /* Compute square of mean of the input samples  
+   * and then store the result in a temporary variable, squareOfMean.*/
+  t = (q15_t) ((1.0 / (blockSize * (blockSize - 1))) * 32768LL);
+  squareOfMean = ((q31_t) mean * mean) >> 15;
+  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 15);
+
+  /* mean of the squares minus the square of the mean. */
+  in = (q15_t) (meanOfSquares - squareOfMean);
+
+  /* Compute standard deviation and store the result to the destination */
+  arm_sqrt_q15(in, pResult);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+}
+
+/**   
+ * @} end of STD group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c
new file mode 100644
index 000000000..d167ed730
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c
@@ -0,0 +1,219 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_std_q31.c   
+*   
+* Description:	Standard deviation of an array of Q31 type.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup STD   
+ * @{   
+ */
+
+
+/**   
+ * @brief Standard deviation of the elements of a Q31 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult standard deviation value returned here   
+ * @return none.   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ *\par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The input is represented in 1.31 format, and intermediate multiplication   
+ * yields a 2.62 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results,    
+ * but provides only a single guard bit.   
+ * There is no saturation on intermediate additions.   
+ * If the accumulator overflows it wraps around and distorts the result.   
+ * In order to avoid overflows completely the input signal must be scaled down by    
+ * log2(blockSize) bits, as a total of blockSize additions are performed internally.    
+ * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.   
+ *   
+ */
+
+
+void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q63_t sum = 0;                                 /* Accumulator */
+  q31_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */
+  q31_t mean;                                    /* mean */
+  q31_t in;                                      /* input value */
+  q31_t t;                                       /* Temporary variable */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn;                                    /* Temporary pointer */
+
+  pIn = pSrc;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  t = (q31_t) ((1.0f / (float32_t) (blockSize - 1u)) * 1073741824.0f);
+
+  /* Compute Mean of squares of the input samples   
+   * and then store the result in a temporary variable, meanOfSquares. */
+  sum = (sum >> 31);
+  meanOfSquares = (q31_t) ((sum * t) >> 30);
+
+  /* Reset the accumulator */
+  sum = 0;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Reset the input working pointer */
+  pSrc = pIn;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q63_t sumOfSquares = 0;                        /* Accumulator */
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += ((q63_t) (in) * (in));
+
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples    
+   * and then store the result in a temporary variable, meanOfSquares. */
+  t = (q31_t) ((1.0f / (float32_t) (blockSize - 1u)) * 1073741824.0f);
+  sumOfSquares = (sumOfSquares >> 31);
+  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 30);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Compute mean of all input values */
+  t = (q31_t) ((1.0f / (blockSize * (blockSize - 1u))) * 2147483648.0f);
+  mean = (q31_t) (sum);
+
+  /* Compute square of mean */
+  squareOfMean = (q31_t) (((q63_t) mean * mean) >> 31);
+  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 31);
+
+
+  /* Compute standard deviation and then store the result to the destination */
+  arm_sqrt_q31(meanOfSquares - squareOfMean, pResult);
+
+}
+
+/**   
+ * @} end of STD group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c
new file mode 100644
index 000000000..9b6a5a89d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c
@@ -0,0 +1,219 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_var_f32.c   
+*   
+* Description:	Variance of the elements of a floating-point vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @defgroup variance  Variance   
+ *   
+ * Calculates the variance of the elements in the input vector.   
+ * The underlying algorithm is used:   
+ *   
+ * 
   
+ * 	Result = (sumOfSquares - sum2 / blockSize) / (blockSize - 1)  
+ *  
+ *	   where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]  
+ *  
+ *	                   sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]  
+ * 
  
+ *   
+ * There are separate functions for floating point, Q31, and Q15 data types.   
+ */
+
+/**   
+ * @addtogroup variance   
+ * @{   
+ */
+
+
+/**   
+ * @brief Variance of the elements of a floating-point vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult variance value returned here   
+ * @return none.   
+ *   
+ */
+
+
+void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t sum = (float32_t) 0.0;               /* Accumulator */
+  float32_t meanOfSquares, mean, in, squareOfMean;      /* Temporary variables */
+  uint32_t blkCnt;                               /* loop counter */
+  float32_t *pIn;                                /* Temporary pointer */
+
+  /* updating temporary pointer */
+  pIn = pSrc;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples   
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = sum / ((float32_t) blockSize - 1.0f);
+
+  /* Reset the accumulator */
+  sum = 0.0f;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Reset the input working pointer */
+  pSrc = pIn;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+  /* Compute mean of all input values */
+  mean = sum / (float32_t) blockSize;
+
+  /* Compute square of mean */
+  squareOfMean = (mean * mean) * (((float32_t) blockSize) /
+                                  ((float32_t) blockSize - 1.0f));
+
+  /* Compute variance and then store the result to the destination */
+  *pResult = meanOfSquares - squareOfMean;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t sum = 0.0f;                          /* Temporary result storage */
+  float32_t sumOfSquares = 0.0f;                 /* Sum of squares */
+  float32_t squareOfSum;                         /* Square of Sum */
+  float32_t in;                                  /* input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += in * in;
+
+    /* C = (A[0] + A[1] + ... + A[blockSize-1]) */
+    /* Compute Sum of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute the square of sum */
+  squareOfSum = ((sum * sum) / (float32_t) blockSize);
+
+  /* Compute the variance */
+  *pResult = ((sumOfSquares - squareOfSum) / (float32_t) (blockSize - 1.0f));
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of variance group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c
new file mode 100644
index 000000000..e557a0d85
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c
@@ -0,0 +1,214 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_var_q15.c   
+*   
+* Description:	Variance of an array of Q15 type.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup variance   
+ * @{   
+ */
+
+/**   
+ * @brief Variance of the elements of a Q15 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult variance value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * The input is represented in 1.15 format.  
+ * Intermediate multiplication yields a 2.30 format, and this   
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.   
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the   
+ * full precision of the intermediate multiplication is preserved.   
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower    
+ * 15 bits, and then saturated to yield a result in 1.15 format.   
+ *   
+ */
+
+
+void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q63_t sum = 0;                                 /* Accumulator */
+  q31_t meanOfSquares, squareOfMean;             /* Mean of square and square of mean */
+  q15_t mean;                                    /* mean */
+  uint32_t blkCnt;                               /* loop counter */
+  q15_t t;                                       /* Temporary variable */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in;                                      /* Input variable */
+  q15_t in1;                                     /* Temporary variable */
+  q15_t *pIn;                                    /* Temporary pointer */
+
+  pIn = pSrc;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in, in, sum);
+    in = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in, in, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in1 = *pSrc++;
+    sum = __SMLALD(in1, in1, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples   
+   * and then store the result in a temporary variable, meanOfSquares. */
+  t = (q15_t) ((1.0f / (float32_t) (blockSize - 1u)) * 16384);
+  sum = __SSAT((sum >> 15u), 16u);
+
+  meanOfSquares = (q31_t) ((sum * t) >> 14u);
+
+  /* Reset the accumulator */
+  sum = 0;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Reset the input working pointer */
+  pSrc = pIn;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q63_t sumOfSquares = 0;                        /* Accumulator */
+  q15_t in;                                      /* Temporary variable */
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += (in * in);
+
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples    
+   * and then store the result in a temporary variable, meanOfSquares. */
+  t = (q15_t) ((1.0f / (float32_t) (blockSize - 1u)) * 16384);
+  sumOfSquares = __SSAT((sumOfSquares >> 15u), 16u);
+  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 14u);
+
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Compute mean of all input values */
+  t = (q15_t) ((1.0f / (float32_t) (blockSize * (blockSize - 1u))) * 32768);
+  mean = __SSAT(sum, 16u);
+
+  /* Compute square of mean */
+  squareOfMean = ((q31_t) mean * mean) >> 15;
+  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 15);
+
+  /* Compute variance and then store the result to the destination */
+  *pResult = (meanOfSquares - squareOfMean);
+
+}
+
+/**   
+ * @} end of variance group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c
new file mode 100644
index 000000000..c22f0224e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c
@@ -0,0 +1,216 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_var_q31.c   
+*   
+* Description:	Variance of an array of Q31 type.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup variance   
+ * @{   
+ */
+
+/**   
+ * @brief Variance of the elements of a Q31 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult variance value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ *\par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The input is represented in 1.31 format, and intermediate multiplication   
+ * yields a 2.62 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results,    
+ * but provides only a single guard bit.   
+ * There is no saturation on intermediate additions.   
+ * If the accumulator overflows it wraps around and distorts the result.   
+ * In order to avoid overflows completely the input signal must be scaled down by    
+ * log2(blockSize) bits, as a total of blockSize additions are performed internally.    
+ * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.   
+ *   
+ */
+
+
+void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult)
+{
+  q63_t sum = 0;                                 /* Accumulator */
+  q31_t meanOfSquares, squareOfMean;             /* Mean of square and square of mean */
+  q31_t mean;                                    /* Mean */
+  q31_t in;                                      /* Input variable */
+  q31_t t;                                       /* Temporary variable */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn;                                    /* Temporary pointer */
+
+  pIn = pSrc;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples   
+   * and then store the result in a temporary variable, meanOfSquares. */
+  t = (q31_t) ((1.0 / (blockSize - 1)) * 1073741824LL);
+  sum = (sum >> 31);
+  meanOfSquares = (q31_t) ((sum * t) >> 30);
+
+  /* Reset the accumulator */
+  sum = 0;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Reset the input working pointer */
+  pSrc = pIn;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q63_t sumOfSquares = 0;                        /* Accumulator */
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += ((q63_t) (in) * (in));
+
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples    
+   * and then store the result in a temporary variable, meanOfSquares. */
+  t = (q31_t) ((1.0 / (blockSize - 1)) * 1073741824LL);
+  sumOfSquares = (sumOfSquares >> 31);
+  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 30);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Compute mean of all input values */
+  t = (q31_t) ((1.0 / (blockSize * (blockSize - 1u))) * 2147483648LL);
+  mean = (q31_t) (sum);
+
+  /* Compute square of mean */
+  squareOfMean = (q31_t) (((q63_t) mean * mean) >> 31);
+  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 31);
+
+  /* Compute variance and then store the result to the destination */
+  *pResult = (q63_t) meanOfSquares - squareOfMean;
+
+}
+
+/**   
+ * @} end of variance group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c
new file mode 100644
index 000000000..86652cd35
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c
@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_copy_f32.c   
+*   
+* Description:	Copies the elements of a floating-point vector. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @defgroup copy Vector Copy   
+ *   
+ * Copies sample by sample from source vector to destination vector.   
+ *   
+ * 
   
+ * 	pDst[n] = pSrc[n];   0 <= n < blockSize.   
+ * 
   
+ *  
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.    
+ */
+
+/**   
+ * @addtogroup copy   
+ * @{   
+ */
+
+/**   
+ * @brief Copies the elements of a floating-point vector.    
+ * @param[in]       *pSrc points to input vector   
+ * @param[out]      *pDst points to output vector   
+ * @param[in]       blockSize length of the input vector  
+ * @return none.   
+ *   
+ */
+
+
+void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the results in the destination buffer */
+    *pDst++ = *pSrc++;
+    *pDst++ = *pSrc++;
+    *pDst++ = *pSrc++;
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the results in the destination buffer */
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of BasicCopy group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c
new file mode 100644
index 000000000..d1a9c48a6
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c
@@ -0,0 +1,130 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_copy_q15.c   
+*   
+* Description:	Copies the elements of a Q15 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup copy   
+ * @{   
+ */
+/**   
+ * @brief Copies the elements of a Q15 vector.    
+ * @param[in]       *pSrc points to input vector   
+ * @param[out]      *pDst points to output vector   
+ * @param[in]       blockSize length of the input vector  
+ * @return none.   
+ *   
+ */
+
+void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t in1, in2;                                /* Temporary variables */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Read two inputs */
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* Store the values in the destination buffer by packing the two inputs */
+    *__SIMD32(pDst)++ = __PKHBT(in1, in2, 16);
+
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    *__SIMD32(pDst)++ = __PKHBT(in1, in2, 16);
+
+#else
+
+    /* Store the values in the destination buffer by packing the two inputs */
+    *__SIMD32(pDst)++ = __PKHBT(in2, in1, 16);
+
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    *__SIMD32(pDst)++ = __PKHBT(in2, in1, 16);
+
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the value in the destination buffer */
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of BasicCopy group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c
new file mode 100644
index 000000000..db445b305
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c
@@ -0,0 +1,109 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_copy_q31.c   
+*   
+* Description:	Copies the elements of a Q31 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup copy   
+ * @{   
+ */
+
+/**   
+ * @brief Copies the elements of a Q31 vector.    
+ * @param[in]       *pSrc points to input vector   
+ * @param[out]      *pDst points to output vector   
+ * @param[in]       blockSize length of the input vector  
+ * @return none.   
+ *   
+ */
+
+void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the values in the destination buffer */
+    *pDst++ = *pSrc++;
+    *pDst++ = *pSrc++;
+    *pDst++ = *pSrc++;
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the value in the destination buffer */
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of BasicCopy group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c
new file mode 100644
index 000000000..57647d864
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_copy_q7.c   
+*   
+* Description:	Copies the elements of a Q7 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup copy   
+ * @{   
+ */
+
+/**   
+ * @brief Copies the elements of a Q7 vector.   
+ * @param[in]       *pSrc points to input vector   
+ * @param[out]      *pDst points to output vector   
+ * @param[in]       blockSize length of the input vector  
+ * @return none.   
+ *   
+ */
+
+void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the results in the destination buffer */
+    /* 4 samples are copied and stored at a time using SIMD */
+    *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the results in the destination buffer */
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of BasicCopy group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c
new file mode 100644
index 000000000..ec9e2a153
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c
@@ -0,0 +1,122 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_fill_f32.c   
+*   
+* Description:	Fills a constant value into a floating-point vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @defgroup Fill Vector Fill   
+ *   
+ * Fills the destination vector with a constant value.   
+ *   
+ * 
   
+ * 	pDst[n] = value;   0 <= n < blockSize.   
+ * 
   
+ *  
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.    
+ */
+
+/**   
+ * @addtogroup Fill   
+ * @{   
+ */
+
+/**   
+ * @brief Fills a constant value into a floating-point vector.    
+ * @param[in]       value input value to be filled  
+ * @param[out]      *pDst points to output vector   
+ * @param[in]       blockSize length of the output vector  
+ * @return none.   
+ *   
+ */
+
+
+void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+    *pDst++ = value;
+    *pDst++ = value;
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of Fill group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c
new file mode 100644
index 000000000..2d8d7ad71
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c
@@ -0,0 +1,112 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_fill_q15.c   
+*   
+* Description:	Fills a constant value into a Q15 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup Fill   
+ * @{   
+ */
+
+/**   
+ * @brief Fills a constant value into a Q15 vector.   
+ * @param[in]       value input value to be filled  
+ * @param[out]      *pDst points to output vector   
+ * @param[in]       blockSize length of the output vector  
+ * @return none.   
+ *   
+ */
+
+void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t packedValue;                             /* value packed to 32 bits */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Packing two 16 bit values to 32 bit value in order to use SIMD */
+  packedValue = __PKHBT(value, value, 16u);
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *__SIMD32(pDst)++ = packedValue;
+    *__SIMD32(pDst)++ = packedValue;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of Fill group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c
new file mode 100644
index 000000000..559f671d4
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c
@@ -0,0 +1,109 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_fill_q31.c   
+*   
+* Description:	Fills a constant value into a Q31 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup Fill   
+ * @{   
+ */
+
+/**   
+ * @brief Fills a constant value into a Q31 vector.   
+ * @param[in]       value input value to be filled  
+ * @param[out]      *pDst points to output vector   
+ * @param[in]       blockSize length of the output vector  
+ * @return none.   
+ *   
+ */
+
+void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+    *pDst++ = value;
+    *pDst++ = value;
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of Fill group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c
new file mode 100644
index 000000000..277f918b6
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c
@@ -0,0 +1,110 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_fill_q7.c   
+*   
+* Description:	Fills a constant value into a Q7 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup Fill   
+ * @{   
+ */
+
+/**   
+ * @brief Fills a constant value into a Q7 vector.   
+ * @param[in]       value input value to be filled  
+ * @param[out]      *pDst points to output vector   
+ * @param[in]       blockSize length of the output vector  
+ * @return none.   
+ *   
+ */
+
+void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t packedValue;                             /* value packed to 32 bits */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Packing four 8 bit values to 32 bit value in order to use SIMD */
+  packedValue = __PACKq7(value, value, value, value);
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *__SIMD32(pDst)++ = packedValue;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of Fill group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c
new file mode 100644
index 000000000..c0f354d09
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c
@@ -0,0 +1,193 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_float_to_q15.c   
+*   
+* Description:	Converts the elements of the floating-point vector to Q15 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup float_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the floating-point vector to Q15 vector.   
+ * @param[in]       *pSrc points to the floating-point input vector   
+ * @param[out]      *pDst points to the Q15 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ * \par Description:   
+ * \par  
+ * The equation used for the conversion process is:   
+ * 
   
+ * 	pDst[n] = (q15_t)(pSrc[n] * 32768);   0 <= n < blockSize.   
+ * 
   
+ * \par Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.   
+ * \note  
+ * In order to apply rounding, the library should be rebuilt with the ROUNDING macro    
+ * defined in the preprocessor section of project options.    
+ *   
+ */
+
+
+void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pIn = pSrc;                         /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+  float32_t in;
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0 ? 0.5f : -0.5f;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of float_to_x group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c
new file mode 100644
index 000000000..4d77624c7
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c
@@ -0,0 +1,200 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_float_to_q31.c   
+*   
+* Description:	Converts the elements of the floating-point vector to Q31 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @defgroup float_to_x  Convert 32-bit floating point value   
+ */
+
+/**   
+ * @addtogroup float_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the floating-point vector to Q31 vector.   
+ * @param[in]       *pSrc points to the floating-point input vector   
+ * @param[out]      *pDst points to the Q31 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ *\par Description:   
+ * \par  
+ * The equation used for the conversion process is:   
+ *  
+ * 
   
+ * 	pDst[n] = (q31_t)(pSrc[n] * 2147483648);   0 <= n < blockSize.   
+ * 
   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.   
+ *  
+ * \note In order to apply rounding, the library should be rebuilt with the ROUNDING macro    
+ * defined in the preprocessor section of project options.    
+ */
+
+
+void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pIn = pSrc;                         /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+  float32_t in;
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+
+    /* C = A * 32768 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0 ? 0.5f : -0.5f;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of float_to_x group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c
new file mode 100644
index 000000000..1a8a4a5a0
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c
@@ -0,0 +1,192 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_float_to_q7.c   
+*   
+* Description:	Converts the elements of the floating-point vector to Q7 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup float_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the floating-point vector to Q7 vector.   
+ * @param[in]       *pSrc points to the floating-point input vector   
+ * @param[out]      *pDst points to the Q7 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ *\par Description:   
+ * \par  
+ * The equation used for the conversion process is:   
+ * 
   
+ * 	pDst[n] = (q7_t)(pSrc[n] * 128);   0 <= n < blockSize.   
+ * 
   
+ * \par Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.   
+ * \note  
+ * In order to apply rounding, the library should be rebuilt with the ROUNDING macro    
+ * defined in the preprocessor section of project options.    
+ */
+
+
+void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pIn = pSrc;                         /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+  float32_t in;
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+#else
+
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+#else
+
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 128.0f);
+    in += in > 0 ? 0.5f : -0.5f;
+    *pDst++ = (q7_t) (__SSAT((q31_t) (in), 8));
+
+#else
+
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    *pDst++ = (q7_t) __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of float_to_x group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c
new file mode 100644
index 000000000..42aa0727c
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c
@@ -0,0 +1,123 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q15_to_float.c   
+*   
+* Description:	Converts the elements of the Q15 vector to floating-point vector.    
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @defgroup q15_to_x  Convert 16-bit Integer value   
+ */
+
+/**   
+ * @addtogroup q15_to_x   
+ * @{   
+ */
+
+
+
+
+/**   
+ * @brief  Converts the elements of the Q15 vector to floating-point vector.    
+ * @param[in]       *pSrc points to the Q15 input vector   
+ * @param[out]      *pDst points to the floating-point output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:   
+ *  
+ * 
   
+ * 	pDst[n] = (float32_t) pSrc[n] / 32768;   0 <= n < blockSize.   
+ * 
   
+ *  
+ */
+
+
+void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 32768 */
+    /* convert from q15 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 32768 */
+    /* convert from q15 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of q15_to_x group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c
new file mode 100644
index 000000000..16043e058
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c
@@ -0,0 +1,116 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q15_to_q31.c   
+*   
+* Description:	Converts the elements of the Q15 vector to Q31 vector. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup q15_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the Q15 vector to Q31 vector.    
+ * @param[in]       *pSrc points to the Q15 input vector   
+ * @param[out]      *pDst points to the Q31 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:  
+ *  
+ * 
   
+ * 	pDst[n] = (q31_t) pSrc[n] << 16;   0 <= n < blockSize.   
+ * 
   
+ *  
+ */
+
+
+void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q31_t)A << 16 */
+    /* convert from q15 to q31 and then store the results in the destination buffer */
+    *pDst++ = (q31_t) * pIn++ << 16;
+    *pDst++ = (q31_t) * pIn++ << 16;
+    *pDst++ = (q31_t) * pIn++ << 16;
+    *pDst++ = (q31_t) * pIn++ << 16;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q31_t)A << 16 */
+    /* convert from q15 to q31 and then store the results in the destination buffer */
+    *pDst++ = (q31_t) * pIn++ << 16;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**   
+ * @} end of q15_to_x group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c
new file mode 100644
index 000000000..0ca22df2c
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c
@@ -0,0 +1,117 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q15_to_q7.c   
+*   
+* Description:	Converts the elements of the Q15 vector to Q7 vector. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup q15_to_x   
+ * @{   
+ */
+
+
+/**   
+ * @brief Converts the elements of the Q15 vector to Q7 vector.    
+ * @param[in]       *pSrc points to the Q15 input vector   
+ * @param[out]      *pDst points to the Q7 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:   
+ *  
+ * 
   
+ * 	pDst[n] = (q7_t) pSrc[n] >> 8;   0 <= n < blockSize.   
+ * 
  
+ *  
+ */
+
+
+void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q7_t) A >> 8 */
+    /* convert from q15 to q7 and then store the results in the destination buffer */
+    *pDst++ = (q7_t) (*pIn++ >> 8);
+    *pDst++ = (q7_t) (*pIn++ >> 8);
+    *pDst++ = (q7_t) (*pIn++ >> 8);
+    *pDst++ = (q7_t) (*pIn++ >> 8);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q7_t) A >> 8 */
+    /* convert from q15 to q7 and then store the results in the destination buffer */
+    *pDst++ = (q7_t) (*pIn++ >> 8);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**   
+ * @} end of q15_to_x group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c
new file mode 100644
index 000000000..48a76946a
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q31_to_float.c   
+*   
+* Description:	Converts the elements of the Q31 vector to floating-point vector.     
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @defgroup q31_to_x  Convert 32-bit Integer value   
+ */
+
+/**   
+ * @addtogroup q31_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the Q31 vector to floating-point vector.   
+ * @param[in]       *pSrc points to the Q31 input vector   
+ * @param[out]      *pDst points to the floating-point output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:   
+ *  
+ * 
   
+ * 	pDst[n] = (float32_t) pSrc[n] / 2147483648;   0 <= n < blockSize.   
+ * 
   
+ *  
+ */
+
+
+void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 2147483648 */
+    /* convert from q31 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 2147483648 */
+    /* convert from q31 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of q31_to_x group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c
new file mode 100644
index 000000000..dafc1d888
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c
@@ -0,0 +1,116 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q31_to_q15.c   
+*   
+* Description:	Converts the elements of the Q31 vector to Q15 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup q31_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the Q31 vector to Q15 vector.   
+ * @param[in]       *pSrc points to the Q31 input vector   
+ * @param[out]      *pDst points to the Q15 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *    
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:   
+ *  
+ * 
   
+ * 	pDst[n] = (q15_t) pSrc[n] >> 16;   0 <= n < blockSize.   
+ * 
   
+ *  
+ */
+
+
+void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q15_t) A >> 16 */
+    /* convert from q31 to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) (*pIn++ >> 16);
+    *pDst++ = (q15_t) (*pIn++ >> 16);
+    *pDst++ = (q15_t) (*pIn++ >> 16);
+    *pDst++ = (q15_t) (*pIn++ >> 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q15_t) A >> 16 */
+    /* convert from q31 to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) (*pIn++ >> 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**   
+ * @} end of q31_to_x group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c
new file mode 100644
index 000000000..c7aedb04f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c
@@ -0,0 +1,116 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q31_to_q7.c   
+*   
+* Description:	Converts the elements of the Q31 vector to Q7 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup q31_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the Q31 vector to Q7 vector.   
+ * @param[in]       *pSrc points to the Q31 input vector   
+ * @param[out]      *pDst points to the Q7 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:   
+ *  
+ * 
   
+ * 	pDst[n] = (q7_t) pSrc[n] >> 24;   0 <= n < blockSize.    
+ * 
   
+ *  
+ */
+
+
+void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q7_t) A >> 24 */
+    /* convert from q31 to q7 and then store the results in the destination buffer */
+    *pDst++ = (q7_t) (*pIn++ >> 24);
+    *pDst++ = (q7_t) (*pIn++ >> 24);
+    *pDst++ = (q7_t) (*pIn++ >> 24);
+    *pDst++ = (q7_t) (*pIn++ >> 24);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q7_t) A >> 24 */
+    /* convert from q31 to q7 and then store the results in the destination buffer */
+    *pDst++ = (q7_t) (*pIn++ >> 24);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**   
+ * @} end of q31_to_x group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c
new file mode 100644
index 000000000..866996925
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q7_to_float.c   
+*   
+* Description:	Converts the elements of the Q7 vector to floating-point vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @defgroup q7_to_x  Convert 8-bit Integer value   
+ */
+
+/**   
+ * @addtogroup q7_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the Q7 vector to floating-point vector.   
+ * @param[in]       *pSrc points to the Q7 input vector   
+ * @param[out]      *pDst points to the floating-point output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *		    
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:   
+ *  
+ * 
   
+ * 	pDst[n] = (float32_t) pSrc[n] / 128;   0 <= n < blockSize.   
+ * 
   
+ *  
+ */
+
+
+void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  q7_t *pIn = pSrc;                              /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 128 */
+    /* convert from q7 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 128 */
+    /* convert from q7 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of q7_to_x group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c
new file mode 100644
index 000000000..9d3b29283
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c
@@ -0,0 +1,119 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q7_to_q15.c   
+*   
+* Description:	Converts the elements of the Q7 vector to Q15 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup q7_to_x   
+ * @{   
+ */
+
+
+
+
+/**   
+ * @brief Converts the elements of the Q7 vector to Q15 vector.   
+ * @param[in]       *pSrc points to the Q7 input vector   
+ * @param[out]      *pDst points to the Q15 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:   
+ *  
+ * 
   
+ * 	pDst[n] = (q15_t) pSrc[n] << 8;   0 <= n < blockSize.   
+ * 
   
+ *  
+ */
+
+
+void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q7_t *pIn = pSrc;                              /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q15_t) A << 8 */
+    /* convert from q7 to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) * pIn++ << 8;
+    *pDst++ = (q15_t) * pIn++ << 8;
+    *pDst++ = (q15_t) * pIn++ << 8;
+    *pDst++ = (q15_t) * pIn++ << 8;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q15_t) A << 8 */
+    /* convert from q7 to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) * pIn++ << 8;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**   
+ * @} end of q7_to_x group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c
new file mode 100644
index 000000000..11f265619
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c
@@ -0,0 +1,116 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q7_to_q31.c   
+*   
+* Description:	Converts the elements of the Q7 vector to Q31 vector. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup q7_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the Q7 vector to Q31 vector.   
+ * @param[in]       *pSrc points to the Q7 input vector   
+ * @param[out]      *pDst points to the Q31 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:   
+ *  
+ * 
   
+ * 	pDst[n] = (q31_t) pSrc[n] << 24;   0 <= n < blockSize.  
+ * 
    
+ *  
+ */
+
+
+void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q7_t *pIn = pSrc;                              /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q31_t) A << 24 */
+    /* convert from q7 to q31 and then store the results in the destination buffer */
+    *pDst++ = (q31_t) * pIn++ << 24;
+    *pDst++ = (q31_t) * pIn++ << 24;
+    *pDst++ = (q31_t) * pIn++ << 24;
+    *pDst++ = (q31_t) * pIn++ << 24;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q31_t) A << 24 */
+    /* convert from q7 to q31 and then store the results in the destination buffer */
+    *pDst++ = (q31_t) * pIn++ << 24;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**   
+ * @} end of q7_to_x group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c
new file mode 100644
index 000000000..7dfe4c349
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c
@@ -0,0 +1,1236 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix4_f32.c   
+*   
+* Description:	Radix-4 Decimation in Frequency CFFT & CIFFT Floating point processing function   
+*   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @defgroup CFFT_CIFFT Complex FFT Functions   
+ *   
+ * \par   
+ * Complex Fast Fourier Transform(CFFT) and Complex Inverse Fast Fourier Transform(CIFFT) is an efficient algorithm to compute Discrete Fourier Transform(DFT) and Inverse Discrete Fourier Transform(IDFT).   
+ * Computational complexity of CFFT reduces drastically when compared to DFT.   
+ * \par   
+ * This set of functions implements CFFT/CIFFT   
+ * for Q15, Q31, and floating-point data types.  The functions operates on in-place buffer which uses same buffer for input and output.   
+ * Complex input is stored in input buffer in an interleaved fashion.   
+ *   
+ * \par   
+ * The functions operate on blocks of input and output data and each call to the function processes   
+ * 2*fftLen samples through the transform.  pSrc  points to In-place arrays containing 2*fftLen values.   
+ * \par  
+ * The pSrc points to the array of in-place buffer of size 2*fftLen and inputs and outputs are stored in an interleaved fashion as shown below.   
+ * 
 {real[0], imag[0], real[1], imag[1],..} 
   
+ *   
+ * \par Lengths supported by the transform:  
+ * \par   
+ * Internally, the function utilize a radix-4 decimation in frequency(DIF) algorithm   
+ * and the size of the FFT supported are of the lengths [16, 64, 256, 1024].  
+ *    
+ *   
+ * \par Algorithm:   
+ *   
+ * Complex Fast Fourier Transform:   
+ * \par    
+ * Input real and imaginary data:   
+ * 
   
+ * x(n) = xa + j * ya   
+ * x(n+N/4 ) = xb + j * yb   
+ * x(n+N/2 ) = xc + j * yc   
+ * x(n+3N 4) = xd + j * yd   
+ * 
   
+ * where N is length of FFT   
+ * \par   
+ * Output real and imaginary data:   
+ * 
   
+ * X(4r) = xa'+ j * ya'   
+ * X(4r+1) = xb'+ j * yb'   
+ * X(4r+2) = xc'+ j * yc'   
+ * X(4r+3) = xd'+ j * yd'   
+ * 
   
+ * \par   
+ * Twiddle factors for radix-4 FFT:   
+ * 
   
+ * Wn = co1 + j * (- si1)   
+ * W2n = co2 + j * (- si2)   
+ * W3n = co3 + j * (- si3)   
+ * 
   
+ *   
+ * \par   
+ * \image html CFFT.gif "Radix-4 Decimation-in Frequency Complex Fast Fourier Transform"   
+ *   
+ * \par   
+ * Output from Radix-4 CFFT Results in Digit reversal order. Interchange middle two branches of every butterfly results in Bit reversed output.   
+ * \par   
+ *  Butterfly CFFT equations:   
+ * 
   
+ * xa' = xa + xb + xc + xd   
+ * ya' = ya + yb + yc + yd   
+ * xc' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)   
+ * yc' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)   
+ * xb' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)   
+ * yb' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)   
+ * xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)   
+ * yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)   
+ * 
   
+ *   
+ *   
+ * Complex Inverse Fast Fourier Transform:   
+ * \par   
+ * CIFFT uses same twiddle factor table as CFFT with modifications in the design equation as shown below.   
+ *   
+ * \par   
+ *  Modified Butterfly CIFFT equations:   
+ * 
   
+ * xa' = xa + xb + xc + xd   
+ * ya' = ya + yb + yc + yd   
+ * xc' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)   
+ * yc' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)   
+ * xb' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)   
+ * yb' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)   
+ * xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)   
+ * yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)   
+ * 
   
+ *   
+ * \par Instance Structure   
+ * A separate instance structure must be defined for each Instance but the twiddle factors and bit reversal tables can be reused.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Initializes twiddle factor table and bit reversal table pointers   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Manually initialize the instance structure as follows:   
+ * 
   
+ *arm_cfft_radix4_instance_f32 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor, onebyfftLen};   
+ *arm_cfft_radix4_instance_q31 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};   
+ *arm_cfft_radix4_instance_q15 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};   
+ * 
   
+ * \par   
+ * where fftLen length of CFFT/CIFFT; ifftFlag Flag for selection of CFFT or CIFFT(Set ifftFlag to calculate CIFFT otherwise calculates CFFT);   
+ * bitReverseFlag Flag for selection of output order(Set bitReverseFlag to output in normal order otherwise output in bit reversed order);    
+ * pTwiddlepoints to array of twiddle coefficients; pBitRevTable points to the array of bit reversal table.   
+ * twidCoefModifier modifier for twiddle factor table which supports all FFT lengths with same table;    
+ * pBitRevTable modifier for bit reversal table which supports all FFT lengths with same table.   
+ * onebyfftLen value of 1/fftLen to calculate CIFFT;   
+ *  
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the CFFT/CIFFT function.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+
+/**   
+ * @addtogroup CFFT_CIFFT   
+ * @{   
+ */
+
+/**   
+ * @details   
+ * @brief Processing function for the floating-point CFFT/CIFFT.  
+ * @param[in]      *S    points to an instance of the floating-point CFFT/CIFFT structure.  
+ * @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.  
+ * @return none.  
+ */
+
+void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc)
+{
+
+  if(S->ifftFlag == 1u)
+  {
+    /*  Complex IFFT radix-4  */
+    arm_radix4_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle,
+                                     S->twidCoefModifier, S->onebyfftLen);
+  }
+  else
+  {
+    /*  Complex FFT radix-4  */
+    arm_radix4_butterfly_f32(pSrc, S->fftLen, S->pTwiddle,
+                             S->twidCoefModifier);
+  }
+
+  if(S->bitReverseFlag == 1u)
+  {
+    /*  Bit Reversal */
+    arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+  }
+
+}
+
+
+/**   
+ * @} end of CFFT_CIFFT group   
+ */
+
+
+
+/* ----------------------------------------------------------------------   
+** Internal helper function used by the FFTs   
+** ------------------------------------------------------------------- */
+
+/*   
+ * @brief  Core function for the floating-point CFFT butterfly process.  
+ * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.  
+ * @param[in]      fftLen           length of the FFT.  
+ * @param[in]      *pCoef           points to the twiddle coefficient buffer.  
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.  
+ */
+
+void arm_radix4_butterfly_f32(
+  float32_t * pSrc,
+  uint16_t fftLen,
+  float32_t * pCoef,
+  uint16_t twidCoefModifier)
+{
+
+  float32_t co1, co2, co3, si1, si2, si3;
+  float32_t t1, t2, r1, r2, s1, s2;
+  uint32_t ia1, ia2, ia3;
+  uint32_t i0, i1, i2, i3;
+  uint32_t n1, n2, j, k;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+  i0 = 0u;
+  ia1 = 0u;
+
+  j = n2;
+
+  /*  Calculation of first stage */
+  do
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+
+    /* xa + xc */
+    r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+    /* xa - xc */
+    r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+    /* ya + yc */
+    s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+    /* ya - yc */
+    s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+    /* xb + xd */
+    t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = r1 + t1;
+
+    /* (xa + xc) - (xb + xd) */
+    r1 = r1 - t1;
+
+    /* yb + yd */
+    t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = s1 + t2;
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* yb - yd */
+    t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+    /* xb - xd */
+    t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+    /*  index calculation for the coefficients */
+    ia2 = ia1 + ia1;
+    co2 = pCoef[ia2 * 2u];
+    si2 = pCoef[(ia2 * 2u) + 1u];
+
+    /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = (r1 * co2) + (s1 * si2);
+
+    /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = (s1 * co2) - (r1 * si2);
+
+    /* (xa - xc) + (yb - yd) */
+    r1 = r2 + t1;
+
+    /* (xa - xc) - (yb - yd) */
+    r2 = r2 - t1;
+
+    /* (ya - yc) - (xb - xd) */
+    s1 = s2 - t2;
+
+    /* (ya - yc) + (xb - xd) */
+    s2 = s2 + t2;
+
+    co1 = pCoef[ia1 * 2u];
+    si1 = pCoef[(ia1 * 2u) + 1u];
+
+    /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = (r1 * co1) + (s1 * si1);
+
+    /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = (s1 * co1) - (r1 * si1);
+
+    /*  index calculation for the coefficients */
+    ia3 = ia2 + ia1;
+    co3 = pCoef[ia3 * 2u];
+    si3 = pCoef[(ia3 * 2u) + 1u];
+
+
+    /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = (r2 * co3) + (s2 * si3);
+
+    /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = (s2 * co3) - (r2 * si3);
+
+    /*  Twiddle coefficients index modifier */
+    ia1 = ia1 + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  }
+  while(--j);
+
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of second stage to excluding last stage */
+  for (k = fftLen / 4; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    /*  Calculation of first stage */
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /* xa + xc */
+        r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+        /* xa - xc */
+        r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
+
+        /* ya + yc */
+        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+        /* ya - yc */
+        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+        /* xb + xd */
+        t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+        /* xa' = xa + xb + xc + xd */
+        pSrc[2u * i0] = r1 + t1;
+
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+
+        /* yb + yd */
+        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+        /* ya' = ya + yb + yc + yd */
+        pSrc[(2u * i0) + 1u] = s1 + t2;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+        /* (xb - xd) */
+        t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+        /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+        pSrc[2u * i1] = (r1 * co2) + (s1 * si2);
+
+        /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+        pSrc[(2u * i1) + 1u] = (s1 * co2) - (r1 * si2);
+
+        /* (xa - xc) + (yb - yd) */
+        r1 = r2 + t1;
+
+        /* (xa - xc) - (yb - yd) */
+        r2 = r2 - t1;
+
+        /* (ya - yc) -  (xb - xd) */
+        s1 = s2 - t2;
+
+        /* (ya - yc) +  (xb - xd) */
+        s2 = s2 + t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+        pSrc[2u * i2] = (r1 * co1) + (s1 * si1);
+
+        /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+        pSrc[(2u * i2) + 1u] = (s1 * co1) - (r1 * si1);
+
+        /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+        pSrc[2u * i3] = (r2 * co3) + (s2 * si3);
+
+        /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+        pSrc[(2u * i3) + 1u] = (s2 * co3) - (r2 * si3);
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+
+  /*  Initializations of last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /*  Calculations of last stage */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+
+    /* xa + xb */
+    r1 = pSrc[2u * i0] + pSrc[2u * i2];
+
+    /* xa - xb */
+    r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+    /* ya + yc */
+    s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+    /* ya - yc */
+    s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+    /* xc + xd */
+    t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = r1 + t1;
+
+    /* (xa + xb) - (xc + xd) */
+    r1 = r1 - t1;
+
+    /* yb + yd */
+    t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = s1 + t2;
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* (yb-yd) */
+    t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+    /* (xb-xd) */
+    t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+    /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = r1;
+
+    /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = s1;
+
+    /* (xa+yb-xc-yd) */
+    r1 = r2 + t1;
+
+    /* (xa-yb-xc+yd) */
+    r2 = r2 - t1;
+
+    /* (ya-xb-yc+xd) */
+    s1 = s2 - t2;
+
+    /* (ya+xb-yc-xd) */
+    s2 = s2 + t2;
+
+    /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = r1;
+
+    /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = s1;
+
+    /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = r2;
+
+    /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = s2;
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /*  Initializations for the fft calculation */
+  n2 = fftLen;
+  n1 = n2;
+  for (k = fftLen; k > 1u; k >>= 2u)
+  {
+    /*  Initializations for the fft calculation */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    /*  FFT Calculation */
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /* xa + xc */
+        r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+        /* xa - xc */
+        r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
+
+        /* ya + yc */
+        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+        /* ya - yc */
+        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+        /* xb + xd */
+        t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+        /* xa' = xa + xb + xc + xd */
+        pSrc[2u * i0] = r1 + t1;
+
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+
+        /* yb + yd */
+        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+        /* ya' = ya + yb + yc + yd */
+        pSrc[(2u * i0) + 1u] = s1 + t2;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+        /* (xb - xd) */
+        t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+        /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+        pSrc[2u * i1] = (r1 * co2) + (s1 * si2);
+
+        /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+        pSrc[(2u * i1) + 1u] = (s1 * co2) - (r1 * si2);
+
+        /* (xa - xc) + (yb - yd) */
+        r1 = r2 + t1;
+
+        /* (xa - xc) - (yb - yd) */
+        r2 = r2 - t1;
+
+        /* (ya - yc) -  (xb - xd) */
+        s1 = s2 - t2;
+
+        /* (ya - yc) +  (xb - xd) */
+        s2 = s2 + t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+        pSrc[2u * i2] = (r1 * co1) + (s1 * si1);
+
+        /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+        pSrc[(2u * i2) + 1u] = (s1 * co1) - (r1 * si1);
+
+        /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+        pSrc[2u * i3] = (r2 * co3) + (s2 * si3);
+
+        /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+        pSrc[(2u * i3) + 1u] = (s2 * co3) - (r2 * si3);
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/*   
+ * @brief  Core function for the floating-point CIFFT butterfly process.  
+ * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.  
+ * @param[in]      fftLen           length of the FFT.  
+ * @param[in]      *pCoef           points to twiddle coefficient buffer.  
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @param[in]      onebyfftLen      value of 1/fftLen.  
+ * @return none.  
+ */
+
+void arm_radix4_butterfly_inverse_f32(
+  float32_t * pSrc,
+  uint16_t fftLen,
+  float32_t * pCoef,
+  uint16_t twidCoefModifier,
+  float32_t onebyfftLen)
+{
+  float32_t co1, co2, co3, si1, si2, si3;
+  float32_t t1, t2, r1, r2, s1, s2;
+  uint32_t ia1, ia2, ia3;
+  uint32_t i0, i1, i2, i3;
+  uint32_t n1, n2, j, k;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+  i0 = 0u;
+  ia1 = 0u;
+
+  j = n2;
+
+  /*  Calculation of first stage */
+  do
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+    /* xa - xc */
+    r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+    /* ya + yc */
+    s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+    /* ya - yc */
+    s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+    /* xb + xd */
+    t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = r1 + t1;
+
+    /* (xa + xc) - (xb + xd) */
+    r1 = r1 - t1;
+
+    /* yb + yd */
+    t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = s1 + t2;
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* yb - yd */
+    t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+    /* xb - xd */
+    t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+    /*  index calculation for the coefficients */
+    ia2 = ia1 + ia1;
+    co2 = pCoef[ia2 * 2u];
+    si2 = pCoef[(ia2 * 2u) + 1u];
+
+    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = (r1 * co2) - (s1 * si2);
+
+    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = (s1 * co2) + (r1 * si2);
+
+    /* (xa - xc) - (yb - yd) */
+    r1 = r2 - t1;
+
+    /* (xa - xc) + (yb - yd) */
+    r2 = r2 + t1;
+
+    /* (ya - yc) + (xb - xd) */
+    s1 = s2 + t2;
+
+    /* (ya - yc) - (xb - xd) */
+    s2 = s2 - t2;
+
+    co1 = pCoef[ia1 * 2u];
+    si1 = pCoef[(ia1 * 2u) + 1u];
+
+    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = (r1 * co1) - (s1 * si1);
+
+    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = (s1 * co1) + (r1 * si1);
+
+    /*  index calculation for the coefficients */
+    ia3 = ia2 + ia1;
+    co3 = pCoef[ia3 * 2u];
+    si3 = pCoef[(ia3 * 2u) + 1u];
+
+    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = (r2 * co3) - (s2 * si3);
+
+    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = (s2 * co3) + (r2 * si3);
+
+    /*  Twiddle coefficients index modifier */
+    ia1 = ia1 + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  }
+  while(--j);
+
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of second stage to excluding last stage */
+  for (k = fftLen / 4; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    /*  Calculation of first stage */
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /* xa + xc */
+        r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+        /* xa - xc */
+        r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
+
+        /* ya + yc */
+        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+        /* ya - yc */
+        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+        /* xb + xd */
+        t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+        /* xa' = xa + xb + xc + xd */
+        pSrc[2u * i0] = r1 + t1;
+
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+
+        /* yb + yd */
+        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+        /* ya' = ya + yb + yc + yd */
+        pSrc[(2u * i0) + 1u] = s1 + t2;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+        /* (xb - xd) */
+        t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+        /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+        pSrc[2u * i1] = (r1 * co2) - (s1 * si2);
+
+        /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+        pSrc[(2u * i1) + 1u] = (s1 * co2) + (r1 * si2);
+
+        /* (xa - xc) - (yb - yd) */
+        r1 = r2 - t1;
+
+        /* (xa - xc) + (yb - yd) */
+        r2 = r2 + t1;
+
+        /* (ya - yc) +  (xb - xd) */
+        s1 = s2 + t2;
+
+        /* (ya - yc) -  (xb - xd) */
+        s2 = s2 - t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+        pSrc[2u * i2] = (r1 * co1) - (s1 * si1);
+
+        /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+        pSrc[(2u * i2) + 1u] = (s1 * co1) + (r1 * si1);
+
+        /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+        pSrc[2u * i3] = (r2 * co3) - (s2 * si3);
+
+        /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+        pSrc[(2u * i3) + 1u] = (s2 * co3) + (r2 * si3);
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+
+  /*  Initializations of last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /*  Calculations of last stage */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = pSrc[2u * i0] + pSrc[2u * i2];
+
+    /* xa - xc */
+    r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+    /* ya + yc */
+    s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+    /* ya - yc */
+    s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+    /* xc + xd */
+    t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = (r1 + t1) * onebyfftLen;
+
+    /* (xa + xb) - (xc + xd) */
+    r1 = r1 - t1;
+
+    /* yb + yd */
+    t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = (s1 + t2) * onebyfftLen;
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* (yb-yd) */
+    t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+    /* (xb-xd) */
+    t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = r1 * onebyfftLen;
+
+    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = s1 * onebyfftLen;
+
+
+    /* (xa - xc) - (yb-yd) */
+    r1 = r2 - t1;
+
+    /* (xa - xc) + (yb-yd) */
+    r2 = r2 + t1;
+
+    /* (ya - yc) + (xb-xd) */
+    s1 = s2 + t2;
+
+    /* (ya - yc) - (xb-xd) */
+    s2 = s2 - t2;
+
+    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = r1 * onebyfftLen;
+
+    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = s1 * onebyfftLen;
+
+    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = r2 * onebyfftLen;
+
+    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = s2 * onebyfftLen;
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /*  Calculation of first stage */
+  for (k = fftLen; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    /*  Calculation of first stage */
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /* xa + xc */
+        r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+        /* xa - xc */
+        r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
+
+        /* ya + yc */
+        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+        /* ya - yc */
+        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+        /* xb + xd */
+        t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+        /* xa' = xa + xb + xc + xd */
+        pSrc[2u * i0] = r1 + t1;
+
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+
+        /* yb + yd */
+        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+        /* ya' = ya + yb + yc + yd */
+        pSrc[(2u * i0) + 1u] = s1 + t2;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+        /* (xb - xd) */
+        t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+        /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+        pSrc[2u * i1] = (r1 * co2) - (s1 * si2);
+
+        /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+        pSrc[(2u * i1) + 1u] = (s1 * co2) + (r1 * si2);
+
+        /* (xa - xc) - (yb - yd) */
+        r1 = r2 - t1;
+
+        /* (xa - xc) + (yb - yd) */
+        r2 = r2 + t1;
+
+        /* (ya - yc) +  (xb - xd) */
+        s1 = s2 + t2;
+
+        /* (ya - yc) -  (xb - xd) */
+        s2 = s2 - t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+        pSrc[2u * i2] = (r1 * co1) - (s1 * si1);
+
+        /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+        pSrc[(2u * i2) + 1u] = (s1 * co1) + (r1 * si1);
+
+        /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+        pSrc[2u * i3] = (r2 * co3) - (s2 * si3);
+
+        /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+        pSrc[(2u * i3) + 1u] = (s2 * co3) + (r2 * si3);
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+  /*  Initializations of last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /*  Calculations of last stage */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = pSrc[2u * i0] + pSrc[2u * i2];
+
+    /* xa - xc */
+    r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+    /* ya + yc */
+    s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+    /* ya - yc */
+    s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+    /* xc + xd */
+    t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = (r1 + t1) * onebyfftLen;
+
+    /* (xa + xb) - (xc + xd) */
+    r1 = r1 - t1;
+
+    /* yb + yd */
+    t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = (s1 + t2) * onebyfftLen;
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* (yb-yd) */
+    t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+    /* (xb-xd) */
+    t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = r1 * onebyfftLen;
+
+    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = s1 * onebyfftLen;
+
+
+    /* (xa - xc) - (yb-yd) */
+    r1 = r2 - t1;
+
+    /* (xa - xc) + (yb-yd) */
+    r2 = r2 + t1;
+
+    /* (ya - yc) + (xb-xd) */
+    s1 = s2 + t2;
+
+    /* (ya - yc) - (xb-xd) */
+    s2 = s2 - t2;
+
+    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = r1 * onebyfftLen;
+
+    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = s1 * onebyfftLen;
+
+    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = r2 * onebyfftLen;
+
+    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = s2 * onebyfftLen;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/*   
+ * @brief  In-place bit reversal function.  
+ * @param[in, out] *pSrc        points to the in-place buffer of floating-point data type.  
+ * @param[in]      fftSize      length of the FFT.  
+ * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.  
+ * @param[in]      *pBitRevTab  points to the bit reversal table.  
+ * @return none.  
+ */
+
+void arm_bitreversal_f32(
+  float32_t * pSrc,
+  uint16_t fftSize,
+  uint16_t bitRevFactor,
+  uint16_t * pBitRevTab)
+{
+  uint16_t fftLenBy2, fftLenBy2p1;
+  uint16_t i, j;
+  float32_t in;
+
+  /*  Initializations */
+  j = 0u;
+  fftLenBy2 = fftSize >> 1u;
+  fftLenBy2p1 = (fftSize >> 1u) + 1u;
+
+  /* Bit Reversal Implementation */
+  for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
+  {
+    if(i < j)
+    {
+      /*  pSrc[i] <-> pSrc[j]; */
+      in = pSrc[2u * i];
+      pSrc[2u * i] = pSrc[2u * j];
+      pSrc[2u * j] = in;
+
+      /*  pSrc[i+1u] <-> pSrc[j+1u] */
+      in = pSrc[(2u * i) + 1u];
+      pSrc[(2u * i) + 1u] = pSrc[(2u * j) + 1u];
+      pSrc[(2u * j) + 1u] = in;
+
+      /*  pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */
+      in = pSrc[2u * (i + fftLenBy2p1)];
+      pSrc[2u * (i + fftLenBy2p1)] = pSrc[2u * (j + fftLenBy2p1)];
+      pSrc[2u * (j + fftLenBy2p1)] = in;
+
+      /*  pSrc[i+fftLenBy2p1+1u] <-> pSrc[j+fftLenBy2p1+1u] */
+      in = pSrc[(2u * (i + fftLenBy2p1)) + 1u];
+      pSrc[(2u * (i + fftLenBy2p1)) + 1u] =
+        pSrc[(2u * (j + fftLenBy2p1)) + 1u];
+      pSrc[(2u * (j + fftLenBy2p1)) + 1u] = in;
+
+    }
+
+    /*  pSrc[i+1u] <-> pSrc[j+1u] */
+    in = pSrc[2u * (i + 1u)];
+    pSrc[2u * (i + 1u)] = pSrc[2u * (j + fftLenBy2)];
+    pSrc[2u * (j + fftLenBy2)] = in;
+
+    /*  pSrc[i+2u] <-> pSrc[j+2u] */
+    in = pSrc[(2u * (i + 1u)) + 1u];
+    pSrc[(2u * (i + 1u)) + 1u] = pSrc[(2u * (j + fftLenBy2)) + 1u];
+    pSrc[(2u * (j + fftLenBy2)) + 1u] = in;
+
+    /*  Reading the index for the bit reversal */
+    j = *pBitRevTab;
+
+    /*  Updating the bit reversal index depending on the fft length  */
+    pBitRevTab += bitRevFactor;
+  }
+}
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c
new file mode 100644
index 000000000..c18654184
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c
@@ -0,0 +1,1551 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2011 ARM Limited. All rights reserved.   
+*   
+* $Date:        17. August 2011  
+* $Revision: 	V1.0.11  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix4_init_f32.c   
+*   
+* Description:	Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+** Version 1.0.11 2011/08/17 
+*    Updated to support 4096 CFFT length.  
+*
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup CFFT_CIFFT   
+ * @{   
+ */
+
+/*   
+* @brief  Floating-point Twiddle factors Table Generation   
+*/
+
+
+/**   
+* \par   
+* Example code for Floating-point Twiddle factors Generation:   
+* \par   
+* 
for(i = 0; i< N; i++)   
+* {   
+*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);   
+*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);   
+* } 
   
+* \par   
+* where N = 1024	and PI = 3.14159265358979   
+* \par   
+* Cos and Sin values are in interleaved fashion   
+*    
+*/
+
+static const float32_t twiddleCoef[4096*2] = {
+			1.000000000000000000f,	0.000000000000000000f,	0.999998823451701880f,	0.001533980186284766f,	0.999995293809576190f,	0.003067956762965976f,
+	0.999989411081928400f,	0.004601926120448571f,	0.999981175282601110f,	0.006135884649154475f,	0.999970586430974140f,	0.007669828739531097f,
+	0.999957644551963900f,	0.009203754782059819f,	0.999942349676023910f,	0.010737659167264491f,	0.999924701839144500f,	0.012271538285719925f,
+	0.999904701082852900f,	0.013805388528060391f,	0.999882347454212560f,	0.015339206284988100f,	0.999857641005823860f,	0.016872987947281710f,
+	0.999830581795823400f,	0.018406729905804820f,	0.999801169887884260f,	0.019940428551514441f,	0.999769405351215280f,	0.021474080275469508f,
+	0.999735288260561680f,	0.023007681468839369f,	0.999698818696204250f,	0.024541228522912288f,	0.999659996743959220f,	0.026074717829103901f,
+	0.999618822495178640f,	0.027608145778965740f,	0.999575296046749220f,	0.029141508764193722f,	0.999529417501093140f,	0.030674803176636626f,
+	0.999481186966166950f,	0.032208025408304586f,	0.999430604555461730f,	0.033741171851377580f,	0.999377670388002850f,	0.035274238898213947f,
+	0.999322384588349540f,	0.036807222941358832f,	0.999264747286594420f,	0.038340120373552694f,	0.999204758618363890f,	0.039872927587739811f,
+	0.999142418724816910f,	0.041405640977076739f,	0.999077727752645360f,	0.042938256934940820f,	0.999010685854073380f,	0.044470771854938668f,
+	0.998941293186856870f,	0.046003182130914623f,	0.998869549914283560f,	0.047535484156959303f,	0.998795456205172410f,	0.049067674327418015f,
+	0.998719012233872940f,	0.050599749036899282f,	0.998640218180265270f,	0.052131704680283324f,	0.998559074229759310f,	0.053663537652730520f,
+	0.998475580573294770f,	0.055195244349689934f,	0.998389737407340160f,	0.056726821166907748f,	0.998301544933892890f,	0.058258264500435752f,
+	0.998211003360478190f,	0.059789570746639868f,	0.998118112900149180f,	0.061320736302208578f,	0.998022873771486240f,	0.062851757564161406f,
+	0.997925286198596000f,	0.064382630929857465f,	0.997825350411111640f,	0.065913352797003805f,	0.997723066644191640f,	0.067443919563664051f,
+	0.997618435138519550f,	0.068974327628266746f,	0.997511456140303450f,	0.070504573389613856f,	0.997402129901275300f,	0.072034653246889332f,
+	0.997290456678690210f,	0.073564563599667426f,	0.997176436735326190f,	0.075094300847921305f,	0.997060070339482960f,	0.076623861392031492f,
+	0.996941357764982160f,	0.078153241632794232f,	0.996820299291165670f,	0.079682437971430126f,	0.996696895202896060f,	0.081211446809592441f,
+	0.996571145790554840f,	0.082740264549375692f,	0.996443051350042630f,	0.084268887593324071f,	0.996312612182778000f,	0.085797312344439894f,
+	0.996179828595696980f,	0.087325535206192059f,	0.996044700901251970f,	0.088853552582524600f,	0.995907229417411720f,	0.090381360877864983f,
+	0.995767414467659820f,	0.091908956497132724f,	0.995625256380994310f,	0.093436335845747787f,	0.995480755491926940f,	0.094963495329638992f,
+	0.995333912140482280f,	0.096490431355252593f,	0.995184726672196930f,	0.098017140329560604f,	0.995033199438118630f,	0.099543618660069319f,
+	0.994879330794805620f,	0.101069862754827820f,	0.994723121104325700f,	0.102595869022436280f,	0.994564570734255420f,	0.104121633872054590f,
+	0.994403680057679100f,	0.105647153713410620f,	0.994240449453187900f,	0.107172424956808840f,	0.994074879304879370f,	0.108697444013138720f,
+	0.993906970002356060f,	0.110222207293883060f,	0.993736721940724600f,	0.111746711211126590f,	0.993564135520595300f,	0.113270952177564350f,
+	0.993389211148080650f,	0.114794926606510080f,	0.993211949234794500f,	0.116318630911904750f,	0.993032350197851410f,	0.117842061508324980f,
+	0.992850414459865100f,	0.119365214810991350f,	0.992666142448948020f,	0.120888087235777080f,	0.992479534598709970f,	0.122410675199216200f,
+	0.992290591348257370f,	0.123932975118512160f,	0.992099313142191800f,	0.125454983411546230f,	0.991905700430609330f,	0.126976696496885870f,
+	0.991709753669099530f,	0.128498110793793170f,	0.991511473318743900f,	0.130019222722233350f,	0.991310859846115440f,	0.131540028702883120f,
+	0.991107913723276890f,	0.133060525157139060f,	0.990902635427780010f,	0.134580708507126170f,	0.990695025442664630f,	0.136100575175706200f,
+	0.990485084256457090f,	0.137620121586486040f,	0.990272812363169110f,	0.139139344163826200f,	0.990058210262297120f,	0.140658239332849210f,
+	0.989841278458820530f,	0.142176803519448030f,	0.989622017463200890f,	0.143695033150294470f,	0.989400427791380380f,	0.145212924652847460f,
+	0.989176509964781010f,	0.146730474455361750f,	0.988950264510302990f,	0.148247678986896030f,	0.988721691960323780f,	0.149764534677321510f,
+	0.988490792852696590f,	0.151281037957330220f,	0.988257567730749460f,	0.152797185258443440f,	0.988022017143283530f,	0.154312973013020100f,
+	0.987784141644572180f,	0.155828397654265230f,	0.987543941794359230f,	0.157343455616238250f,	0.987301418157858430f,	0.158858143333861450f,
+	0.987056571305750970f,	0.160372457242928280f,	0.986809401814185530f,	0.161886393780111830f,	0.986559910264775410f,	0.163399949382973230f,
+	0.986308097244598670f,	0.164913120489969890f,	0.986053963346195440f,	0.166425903540464100f,	0.985797509167567480f,	0.167938294974731170f,
+	0.985538735312176060f,	0.169450291233967960f,	0.985277642388941220f,	0.170961888760301220f,	0.985014231012239840f,	0.172473083996795950f,
+	0.984748501801904210f,	0.173983873387463820f,	0.984480455383220930f,	0.175494253377271430f,	0.984210092386929030f,	0.177004220412148750f,
+	0.983937413449218920f,	0.178513770938997510f,	0.983662419211730250f,	0.180022901405699510f,	0.983385110321551180f,	0.181531608261124970f,
+	0.983105487431216290f,	0.183039887955140950f,	0.982823551198705240f,	0.184547736938619620f,	0.982539302287441240f,	0.186055151663446630f,
+	0.982252741366289370f,	0.187562128582529600f,	0.981963869109555240f,	0.189068664149806190f,	0.981672686196983110f,	0.190574754820252740f,
+	0.981379193313754560f,	0.192080397049892440f,	0.981083391150486710f,	0.193585587295803610f,	0.980785280403230430f,	0.195090322016128250f,
+	0.980484861773469380f,	0.196594597670080220f,	0.980182135968117430f,	0.198098410717953560f,	0.979877103699517640f,	0.199601757621130970f,
+	0.979569765685440520f,	0.201104634842091900f,	0.979260122649082020f,	0.202607038844421130f,	0.978948175319062200f,	0.204108966092816870f,
+	0.978633924429423210f,	0.205610413053099240f,	0.978317370719627650f,	0.207111376192218560f,	0.977998514934557140f,	0.208611851978263490f,
+	0.977677357824509930f,	0.210111836880469610f,	0.977353900145199960f,	0.211611327369227550f,	0.977028142657754390f,	0.213110319916091360f,
+	0.976700086128711840f,	0.214608810993786760f,	0.976369731330021140f,	0.216106797076219520f,	0.976037079039039020f,	0.217604274638483640f,
+	0.975702130038528570f,	0.219101240156869800f,	0.975364885116656980f,	0.220597690108873510f,	0.975025345066994120f,	0.222093620973203510f,
+	0.974683510688510670f,	0.223589029229789990f,	0.974339382785575860f,	0.225083911359792830f,	0.973992962167955830f,	0.226578263845610000f,
+	0.973644249650811980f,	0.228072083170885730f,	0.973293246054698250f,	0.229565365820518870f,	0.972939952205560180f,	0.231058108280671110f,
+	0.972584368934732210f,	0.232550307038775240f,	0.972226497078936270f,	0.234041958583543430f,	0.971866337480279400f,	0.235533059404975490f,
+	0.971503890986251780f,	0.237023605994367200f,	0.971139158449725090f,	0.238513594844318420f,	0.970772140728950350f,	0.240003022448741500f,
+	0.970402838687555500f,	0.241491885302869330f,	0.970031253194543970f,	0.242980179903263870f,	0.969657385124292450f,	0.244467902747824150f,
+	0.969281235356548530f,	0.245955050335794590f,	0.968902804776428870f,	0.247441619167773270f,	0.968522094274417380f,	0.248927605745720150f,
+	0.968139104746362440f,	0.250413006572965220f,	0.967753837093475510f,	0.251897818154216970f,	0.967366292222328510f,	0.253382036995570160f,
+	0.966976471044852070f,	0.254865659604514570f,	0.966584374478333120f,	0.256348682489942910f,	0.966190003445412500f,	0.257831102162158990f,
+	0.965793358874083680f,	0.259312915132886230f,	0.965394441697689400f,	0.260794117915275510f,	0.964993252854920320f,	0.262274707023913590f,
+	0.964589793289812760f,	0.263754678974831350f,	0.964184063951745830f,	0.265234030285511790f,	0.963776065795439840f,	0.266712757474898370f,
+	0.963365799780954050f,	0.268190857063403180f,	0.962953266873683880f,	0.269668325572915090f,	0.962538468044359160f,	0.271145159526808010f,
+	0.962121404269041580f,	0.272621355449948980f,	0.961702076529122540f,	0.274096909868706380f,	0.961280485811320640f,	0.275571819310958140f,
+	0.960856633107679660f,	0.277046080306099900f,	0.960430519415565790f,	0.278519689385053060f,	0.960002145737665960f,	0.279992643080273220f,
+	0.959571513081984520f,	0.281464937925757940f,	0.959138622461841890f,	0.282936570457055390f,	0.958703474895871600f,	0.284407537211271880f,
+	0.958266071408017670f,	0.285877834727080620f,	0.957826413027532910f,	0.287347459544729510f,	0.957384500788975860f,	0.288816408206049480f,
+	0.956940335732208820f,	0.290284677254462330f,	0.956493918902395100f,	0.291752263234989260f,	0.956045251349996410f,	0.293219162694258630f,
+	0.955594334130771110f,	0.294685372180514330f,	0.955141168305770780f,	0.296150888243623790f,	0.954685754941338340f,	0.297615707435086200f,
+	0.954228095109105670f,	0.299079826308040480f,	0.953768189885990330f,	0.300543241417273450f,	0.953306040354193860f,	0.302005949319228080f,
+	0.952841647601198720f,	0.303467946572011320f,	0.952375012719765880f,	0.304929229735402370f,	0.951906136807932350f,	0.306389795370860920f,
+	0.951435020969008340f,	0.307849640041534870f,	0.950961666311575080f,	0.309308760312268730f,	0.950486073949481700f,	0.310767152749611470f,
+	0.950008245001843000f,	0.312224813921824880f,	0.949528180593036670f,	0.313681740398891520f,	0.949045881852700560f,	0.315137928752522440f,
+	0.948561349915730270f,	0.316593375556165850f,	0.948074585922276230f,	0.318048077385014950f,	0.947585591017741090f,	0.319502030816015690f,
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+	0.944100258491272660f,	0.329658462528587490f,	0.943593458161960390f,	0.331106305759876430f,	0.943084437466093490f,	0.332553369866044220f,
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+	0.941026175050889260f,	0.338333766965541130f,	0.940506070593268300f,	0.339776884406826850f,	0.939983753034014050f,	0.341219202320282360f,
+	0.939459223602189920f,	0.342660717311994380f,	0.938932483532064600f,	0.344101425989938810f,	0.938403534063108060f,	0.345541324963989090f,
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+	0.934639129819680780f,	0.355597661704783850f,	0.934092550404258980f,	0.357030961233429980f,	0.933543772978836170f,	0.358463420633736540f,
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+	0.931326709081180430f,	0.364184789567079890f,	0.930766961078983710f,	0.365612997804773850f,	0.930205022892219070f,	0.367040345719767180f,
+	0.929640895843181330f,	0.368466829953372320f,	0.929074581259315860f,	0.369892447148934100f,	0.928506080473215590f,	0.371317193951837540f,
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+	0.926210242138311380f,	0.377007410216418260f,	0.925630830509872720f,	0.378427754808765560f,	0.925049240782677580f,	0.379847208924051160f,
+	0.924465474325262600f,	0.381265769222162380f,	0.923879532511286740f,	0.382683432365089780f,	0.923291416719527640f,	0.384100195016935040f,
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+	0.911706032005429880f,	0.410843171057903910f,	0.911074734055176360f,	0.412241226669882890f,	0.910441292258067250f,	0.413638312238434500f,
+	0.909805708104652220f,	0.415034424476081630f,	0.909167983090522380f,	0.416429560097637150f,	0.908528118716306120f,	0.417823715820212270f,
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+	0.905947297807268460f,	0.423390474143796050f,	0.905296759318118820f,	0.424779681209108810f,	0.904644090578246240f,	0.426167888726799620f,
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+	0.900015892016160280f,	0.435857079922255470f,	0.899346236979341570f,	0.437237173661044090f,	0.898674465693953820f,	0.438616238538527660f,
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+	0.998118112900149180f,	-0.061320736302209057f,	0.998211003360478190f,	-0.059789570746640187f,	0.998301544933892780f,	-0.058258264500435912f,
+	0.998389737407340160f,	-0.056726821166907741f,	0.998475580573294770f,	-0.055195244349689775f,	0.998559074229759310f,	-0.053663537652731082f,
+	0.998640218180265160f,	-0.052131704680283719f,	0.998719012233872940f,	-0.050599749036899518f,	0.998795456205172410f,	-0.049067674327418091f,
+	0.998869549914283560f,	-0.047535484156959219f,	0.998941293186856870f,	-0.046003182130915268f,	0.999010685854073270f,	-0.044470771854939146f,
+	0.999077727752645360f,	-0.042938256934941139f,	0.999142418724816910f,	-0.041405640977076899f,	0.999204758618363890f,	-0.039872927587739811f,
+	0.999264747286594420f,	-0.038340120373552534f,	0.999322384588349430f,	-0.036807222941359394f,	0.999377670388002850f,	-0.035274238898214350f,
+	0.999430604555461730f,	-0.033741171851377823f,	0.999481186966166950f,	-0.032208025408304662f,	0.999529417501093140f,	-0.030674803176636543f,
+	0.999575296046749220f,	-0.029141508764194368f,	0.999618822495178640f,	-0.027608145778966225f,	0.999659996743959220f,	-0.026074717829104220f,
+	0.999698818696204250f,	-0.024541228522912448f,	0.999735288260561680f,	-0.023007681468839372f,	0.999769405351215280f,	-0.021474080275469345f,
+	0.999801169887884260f,	-0.019940428551515003f,	0.999830581795823400f,	-0.018406729905805226f,	0.999857641005823860f,	-0.016872987947281957f,
+	0.999882347454212560f,	-0.015339206284988182f,	0.999904701082852900f,	-0.013805388528060311f,	0.999924701839144500f,	-0.012271538285720572f,
+	0.999942349676023910f,	-0.010737659167264976f,	0.999957644551963900f,	-0.009203754782060144f,	0.999970586430974140f,	-0.007669828739531261f,
+	0.999981175282601110f,	-0.006135884649154477f,	0.999989411081928400f,	-0.004601926120448411f,	0.999995293809576190f,	-0.003067956762966544f,
+	0.999998823451701880f,	-0.001533980186285172f,
+  };
+
+/**   
+* @brief  Initialization function for the floating-point CFFT/CIFFT.  
+* @param[in,out] *S             points to an instance of the floating-point CFFT/CIFFT structure.  
+* @param[in]     fftLen         length of the FFT.  
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.  
+*   
+* \par Description:  
+* \par   
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.   
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated  
+* \par   
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
+* \par   
+* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.   
+* \par   
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   
+*/
+
+arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (float32_t *) twiddleCoef;
+
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of structure parameters depending on the FFT length */
+  switch (S->fftLen)
+  {
+
+  case 4096u:
+    /*  Initializations of structure parameters for 4096 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = armBitRevTable;
+    /*  Initialise the 1/N Value */
+    S->onebyfftLen = 0.000244140625;
+    break;
+
+  case 1024u:
+    /*  Initializations of structure parameters for 1024 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 4u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 4u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = &armBitRevTable[3];
+    /*  Initialise the 1/fftLen Value */
+    S->onebyfftLen = 0.0009765625f;
+    break;
+
+
+  case 256u:
+    /*  Initializations of structure parameters for 256 point FFT */
+    S->twidCoefModifier = 16u;
+    S->bitRevFactor = 16u;
+    S->pBitRevTable = &armBitRevTable[15];
+    S->onebyfftLen = 0.00390625f;
+    break;
+
+  case 64u:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 64u;
+    S->bitRevFactor = 64u;
+    S->pBitRevTable = &armBitRevTable[63];
+    S->onebyfftLen = 0.015625f;
+    break;
+
+  case 16u:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 256u;
+    S->bitRevFactor = 256u;
+    S->pBitRevTable = &armBitRevTable[255];
+    S->onebyfftLen = 0.0625f;
+    break;
+
+
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**   
+ * @} end of CFFT_CIFFT group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c
new file mode 100644
index 000000000..96ae68202
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c
@@ -0,0 +1,415 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix4_init_q15.c   
+*   
+* Description:	Radix-4 Decimation in Frequency Q15 FFT & IFFT initialization function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+
+/**   
+ * @addtogroup CFFT_CIFFT   
+ * @{   
+ */
+
+/*   
+* @brief  Twiddle factors Table   
+*/
+
+/**  
+* \par   
+* Example code for Q15 Twiddle factors Generation::   
+* \par   
+* 
for(i = 0; i< N; i++)   
+* {   
+*	twiddleCoefQ15[2*i]= cos(i * 2*PI/(float)N);   
+*	twiddleCoefQ15[2*i+1]= sin(i * 2*PI/(float)N);   
+* } 
   
+* \par   
+* where N = 1024	and PI = 3.14159265358979   
+* \par   
+* Cos and Sin values are interleaved fashion   
+* \par   
+* Convert Floating point to Q15(Fixed point 1.15):   
+*	round(twiddleCoefQ15(i) * pow(2, 15))   
+*   
+*/
+
+static const q15_t twiddleCoefQ15[2048] = {
+  0x7fff, 0x0, 0x7fff, 0xc9, 0x7ffe, 0x192, 0x7ffa, 0x25b,
+  0x7ff6, 0x324, 0x7ff1, 0x3ed, 0x7fea, 0x4b6, 0x7fe2, 0x57f,
+  0x7fd9, 0x648, 0x7fce, 0x711, 0x7fc2, 0x7d9, 0x7fb5, 0x8a2,
+  0x7fa7, 0x96b, 0x7f98, 0xa33, 0x7f87, 0xafb, 0x7f75, 0xbc4,
+  0x7f62, 0xc8c, 0x7f4e, 0xd54, 0x7f38, 0xe1c, 0x7f22, 0xee4,
+  0x7f0a, 0xfab, 0x7ef0, 0x1073, 0x7ed6, 0x113a, 0x7eba, 0x1201,
+  0x7e9d, 0x12c8, 0x7e7f, 0x138f, 0x7e60, 0x1455, 0x7e3f, 0x151c,
+  0x7e1e, 0x15e2, 0x7dfb, 0x16a8, 0x7dd6, 0x176e, 0x7db1, 0x1833,
+  0x7d8a, 0x18f9, 0x7d63, 0x19be, 0x7d3a, 0x1a83, 0x7d0f, 0x1b47,
+  0x7ce4, 0x1c0c, 0x7cb7, 0x1cd0, 0x7c89, 0x1d93, 0x7c5a, 0x1e57,
+  0x7c2a, 0x1f1a, 0x7bf9, 0x1fdd, 0x7bc6, 0x209f, 0x7b92, 0x2162,
+  0x7b5d, 0x2224, 0x7b27, 0x22e5, 0x7aef, 0x23a7, 0x7ab7, 0x2467,
+  0x7a7d, 0x2528, 0x7a42, 0x25e8, 0x7a06, 0x26a8, 0x79c9, 0x2768,
+  0x798a, 0x2827, 0x794a, 0x28e5, 0x790a, 0x29a4, 0x78c8, 0x2a62,
+  0x7885, 0x2b1f, 0x7840, 0x2bdc, 0x77fb, 0x2c99, 0x77b4, 0x2d55,
+  0x776c, 0x2e11, 0x7723, 0x2ecc, 0x76d9, 0x2f87, 0x768e, 0x3042,
+  0x7642, 0x30fc, 0x75f4, 0x31b5, 0x75a6, 0x326e, 0x7556, 0x3327,
+  0x7505, 0x33df, 0x74b3, 0x3497, 0x7460, 0x354e, 0x740b, 0x3604,
+  0x73b6, 0x36ba, 0x735f, 0x3770, 0x7308, 0x3825, 0x72af, 0x38d9,
+  0x7255, 0x398d, 0x71fa, 0x3a40, 0x719e, 0x3af3, 0x7141, 0x3ba5,
+  0x70e3, 0x3c57, 0x7083, 0x3d08, 0x7023, 0x3db8, 0x6fc2, 0x3e68,
+  0x6f5f, 0x3f17, 0x6efb, 0x3fc6, 0x6e97, 0x4074, 0x6e31, 0x4121,
+  0x6dca, 0x41ce, 0x6d62, 0x427a, 0x6cf9, 0x4326, 0x6c8f, 0x43d1,
+  0x6c24, 0x447b, 0x6bb8, 0x4524, 0x6b4b, 0x45cd, 0x6add, 0x4675,
+  0x6a6e, 0x471d, 0x69fd, 0x47c4, 0x698c, 0x486a, 0x691a, 0x490f,
+  0x68a7, 0x49b4, 0x6832, 0x4a58, 0x67bd, 0x4afb, 0x6747, 0x4b9e,
+  0x66d0, 0x4c40, 0x6657, 0x4ce1, 0x65de, 0x4d81, 0x6564, 0x4e21,
+  0x64e9, 0x4ec0, 0x646c, 0x4f5e, 0x63ef, 0x4ffb, 0x6371, 0x5098,
+  0x62f2, 0x5134, 0x6272, 0x51cf, 0x61f1, 0x5269, 0x616f, 0x5303,
+  0x60ec, 0x539b, 0x6068, 0x5433, 0x5fe4, 0x54ca, 0x5f5e, 0x5560,
+  0x5ed7, 0x55f6, 0x5e50, 0x568a, 0x5dc8, 0x571e, 0x5d3e, 0x57b1,
+  0x5cb4, 0x5843, 0x5c29, 0x58d4, 0x5b9d, 0x5964, 0x5b10, 0x59f4,
+  0x5a82, 0x5a82, 0x59f4, 0x5b10, 0x5964, 0x5b9d, 0x58d4, 0x5c29,
+  0x5843, 0x5cb4, 0x57b1, 0x5d3e, 0x571e, 0x5dc8, 0x568a, 0x5e50,
+  0x55f6, 0x5ed7, 0x5560, 0x5f5e, 0x54ca, 0x5fe4, 0x5433, 0x6068,
+  0x539b, 0x60ec, 0x5303, 0x616f, 0x5269, 0x61f1, 0x51cf, 0x6272,
+  0x5134, 0x62f2, 0x5098, 0x6371, 0x4ffb, 0x63ef, 0x4f5e, 0x646c,
+  0x4ec0, 0x64e9, 0x4e21, 0x6564, 0x4d81, 0x65de, 0x4ce1, 0x6657,
+  0x4c40, 0x66d0, 0x4b9e, 0x6747, 0x4afb, 0x67bd, 0x4a58, 0x6832,
+  0x49b4, 0x68a7, 0x490f, 0x691a, 0x486a, 0x698c, 0x47c4, 0x69fd,
+  0x471d, 0x6a6e, 0x4675, 0x6add, 0x45cd, 0x6b4b, 0x4524, 0x6bb8,
+  0x447b, 0x6c24, 0x43d1, 0x6c8f, 0x4326, 0x6cf9, 0x427a, 0x6d62,
+  0x41ce, 0x6dca, 0x4121, 0x6e31, 0x4074, 0x6e97, 0x3fc6, 0x6efb,
+  0x3f17, 0x6f5f, 0x3e68, 0x6fc2, 0x3db8, 0x7023, 0x3d08, 0x7083,
+  0x3c57, 0x70e3, 0x3ba5, 0x7141, 0x3af3, 0x719e, 0x3a40, 0x71fa,
+  0x398d, 0x7255, 0x38d9, 0x72af, 0x3825, 0x7308, 0x3770, 0x735f,
+  0x36ba, 0x73b6, 0x3604, 0x740b, 0x354e, 0x7460, 0x3497, 0x74b3,
+  0x33df, 0x7505, 0x3327, 0x7556, 0x326e, 0x75a6, 0x31b5, 0x75f4,
+  0x30fc, 0x7642, 0x3042, 0x768e, 0x2f87, 0x76d9, 0x2ecc, 0x7723,
+  0x2e11, 0x776c, 0x2d55, 0x77b4, 0x2c99, 0x77fb, 0x2bdc, 0x7840,
+  0x2b1f, 0x7885, 0x2a62, 0x78c8, 0x29a4, 0x790a, 0x28e5, 0x794a,
+  0x2827, 0x798a, 0x2768, 0x79c9, 0x26a8, 0x7a06, 0x25e8, 0x7a42,
+  0x2528, 0x7a7d, 0x2467, 0x7ab7, 0x23a7, 0x7aef, 0x22e5, 0x7b27,
+  0x2224, 0x7b5d, 0x2162, 0x7b92, 0x209f, 0x7bc6, 0x1fdd, 0x7bf9,
+  0x1f1a, 0x7c2a, 0x1e57, 0x7c5a, 0x1d93, 0x7c89, 0x1cd0, 0x7cb7,
+  0x1c0c, 0x7ce4, 0x1b47, 0x7d0f, 0x1a83, 0x7d3a, 0x19be, 0x7d63,
+  0x18f9, 0x7d8a, 0x1833, 0x7db1, 0x176e, 0x7dd6, 0x16a8, 0x7dfb,
+  0x15e2, 0x7e1e, 0x151c, 0x7e3f, 0x1455, 0x7e60, 0x138f, 0x7e7f,
+  0x12c8, 0x7e9d, 0x1201, 0x7eba, 0x113a, 0x7ed6, 0x1073, 0x7ef0,
+  0xfab, 0x7f0a, 0xee4, 0x7f22, 0xe1c, 0x7f38, 0xd54, 0x7f4e,
+  0xc8c, 0x7f62, 0xbc4, 0x7f75, 0xafb, 0x7f87, 0xa33, 0x7f98,
+  0x96b, 0x7fa7, 0x8a2, 0x7fb5, 0x7d9, 0x7fc2, 0x711, 0x7fce,
+  0x648, 0x7fd9, 0x57f, 0x7fe2, 0x4b6, 0x7fea, 0x3ed, 0x7ff1,
+  0x324, 0x7ff6, 0x25b, 0x7ffa, 0x192, 0x7ffe, 0xc9, 0x7fff,
+  0x0, 0x7fff, 0xff37, 0x7fff, 0xfe6e, 0x7ffe, 0xfda5, 0x7ffa,
+  0xfcdc, 0x7ff6, 0xfc13, 0x7ff1, 0xfb4a, 0x7fea, 0xfa81, 0x7fe2,
+  0xf9b8, 0x7fd9, 0xf8ef, 0x7fce, 0xf827, 0x7fc2, 0xf75e, 0x7fb5,
+  0xf695, 0x7fa7, 0xf5cd, 0x7f98, 0xf505, 0x7f87, 0xf43c, 0x7f75,
+  0xf374, 0x7f62, 0xf2ac, 0x7f4e, 0xf1e4, 0x7f38, 0xf11c, 0x7f22,
+  0xf055, 0x7f0a, 0xef8d, 0x7ef0, 0xeec6, 0x7ed6, 0xedff, 0x7eba,
+  0xed38, 0x7e9d, 0xec71, 0x7e7f, 0xebab, 0x7e60, 0xeae4, 0x7e3f,
+  0xea1e, 0x7e1e, 0xe958, 0x7dfb, 0xe892, 0x7dd6, 0xe7cd, 0x7db1,
+  0xe707, 0x7d8a, 0xe642, 0x7d63, 0xe57d, 0x7d3a, 0xe4b9, 0x7d0f,
+  0xe3f4, 0x7ce4, 0xe330, 0x7cb7, 0xe26d, 0x7c89, 0xe1a9, 0x7c5a,
+  0xe0e6, 0x7c2a, 0xe023, 0x7bf9, 0xdf61, 0x7bc6, 0xde9e, 0x7b92,
+  0xdddc, 0x7b5d, 0xdd1b, 0x7b27, 0xdc59, 0x7aef, 0xdb99, 0x7ab7,
+  0xdad8, 0x7a7d, 0xda18, 0x7a42, 0xd958, 0x7a06, 0xd898, 0x79c9,
+  0xd7d9, 0x798a, 0xd71b, 0x794a, 0xd65c, 0x790a, 0xd59e, 0x78c8,
+  0xd4e1, 0x7885, 0xd424, 0x7840, 0xd367, 0x77fb, 0xd2ab, 0x77b4,
+  0xd1ef, 0x776c, 0xd134, 0x7723, 0xd079, 0x76d9, 0xcfbe, 0x768e,
+  0xcf04, 0x7642, 0xce4b, 0x75f4, 0xcd92, 0x75a6, 0xccd9, 0x7556,
+  0xcc21, 0x7505, 0xcb69, 0x74b3, 0xcab2, 0x7460, 0xc9fc, 0x740b,
+  0xc946, 0x73b6, 0xc890, 0x735f, 0xc7db, 0x7308, 0xc727, 0x72af,
+  0xc673, 0x7255, 0xc5c0, 0x71fa, 0xc50d, 0x719e, 0xc45b, 0x7141,
+  0xc3a9, 0x70e3, 0xc2f8, 0x7083, 0xc248, 0x7023, 0xc198, 0x6fc2,
+  0xc0e9, 0x6f5f, 0xc03a, 0x6efb, 0xbf8c, 0x6e97, 0xbedf, 0x6e31,
+  0xbe32, 0x6dca, 0xbd86, 0x6d62, 0xbcda, 0x6cf9, 0xbc2f, 0x6c8f,
+  0xbb85, 0x6c24, 0xbadc, 0x6bb8, 0xba33, 0x6b4b, 0xb98b, 0x6add,
+  0xb8e3, 0x6a6e, 0xb83c, 0x69fd, 0xb796, 0x698c, 0xb6f1, 0x691a,
+  0xb64c, 0x68a7, 0xb5a8, 0x6832, 0xb505, 0x67bd, 0xb462, 0x6747,
+  0xb3c0, 0x66d0, 0xb31f, 0x6657, 0xb27f, 0x65de, 0xb1df, 0x6564,
+  0xb140, 0x64e9, 0xb0a2, 0x646c, 0xb005, 0x63ef, 0xaf68, 0x6371,
+  0xaecc, 0x62f2, 0xae31, 0x6272, 0xad97, 0x61f1, 0xacfd, 0x616f,
+  0xac65, 0x60ec, 0xabcd, 0x6068, 0xab36, 0x5fe4, 0xaaa0, 0x5f5e,
+  0xaa0a, 0x5ed7, 0xa976, 0x5e50, 0xa8e2, 0x5dc8, 0xa84f, 0x5d3e,
+  0xa7bd, 0x5cb4, 0xa72c, 0x5c29, 0xa69c, 0x5b9d, 0xa60c, 0x5b10,
+  0xa57e, 0x5a82, 0xa4f0, 0x59f4, 0xa463, 0x5964, 0xa3d7, 0x58d4,
+  0xa34c, 0x5843, 0xa2c2, 0x57b1, 0xa238, 0x571e, 0xa1b0, 0x568a,
+  0xa129, 0x55f6, 0xa0a2, 0x5560, 0xa01c, 0x54ca, 0x9f98, 0x5433,
+  0x9f14, 0x539b, 0x9e91, 0x5303, 0x9e0f, 0x5269, 0x9d8e, 0x51cf,
+  0x9d0e, 0x5134, 0x9c8f, 0x5098, 0x9c11, 0x4ffb, 0x9b94, 0x4f5e,
+  0x9b17, 0x4ec0, 0x9a9c, 0x4e21, 0x9a22, 0x4d81, 0x99a9, 0x4ce1,
+  0x9930, 0x4c40, 0x98b9, 0x4b9e, 0x9843, 0x4afb, 0x97ce, 0x4a58,
+  0x9759, 0x49b4, 0x96e6, 0x490f, 0x9674, 0x486a, 0x9603, 0x47c4,
+  0x9592, 0x471d, 0x9523, 0x4675, 0x94b5, 0x45cd, 0x9448, 0x4524,
+  0x93dc, 0x447b, 0x9371, 0x43d1, 0x9307, 0x4326, 0x929e, 0x427a,
+  0x9236, 0x41ce, 0x91cf, 0x4121, 0x9169, 0x4074, 0x9105, 0x3fc6,
+  0x90a1, 0x3f17, 0x903e, 0x3e68, 0x8fdd, 0x3db8, 0x8f7d, 0x3d08,
+  0x8f1d, 0x3c57, 0x8ebf, 0x3ba5, 0x8e62, 0x3af3, 0x8e06, 0x3a40,
+  0x8dab, 0x398d, 0x8d51, 0x38d9, 0x8cf8, 0x3825, 0x8ca1, 0x3770,
+  0x8c4a, 0x36ba, 0x8bf5, 0x3604, 0x8ba0, 0x354e, 0x8b4d, 0x3497,
+  0x8afb, 0x33df, 0x8aaa, 0x3327, 0x8a5a, 0x326e, 0x8a0c, 0x31b5,
+  0x89be, 0x30fc, 0x8972, 0x3042, 0x8927, 0x2f87, 0x88dd, 0x2ecc,
+  0x8894, 0x2e11, 0x884c, 0x2d55, 0x8805, 0x2c99, 0x87c0, 0x2bdc,
+  0x877b, 0x2b1f, 0x8738, 0x2a62, 0x86f6, 0x29a4, 0x86b6, 0x28e5,
+  0x8676, 0x2827, 0x8637, 0x2768, 0x85fa, 0x26a8, 0x85be, 0x25e8,
+  0x8583, 0x2528, 0x8549, 0x2467, 0x8511, 0x23a7, 0x84d9, 0x22e5,
+  0x84a3, 0x2224, 0x846e, 0x2162, 0x843a, 0x209f, 0x8407, 0x1fdd,
+  0x83d6, 0x1f1a, 0x83a6, 0x1e57, 0x8377, 0x1d93, 0x8349, 0x1cd0,
+  0x831c, 0x1c0c, 0x82f1, 0x1b47, 0x82c6, 0x1a83, 0x829d, 0x19be,
+  0x8276, 0x18f9, 0x824f, 0x1833, 0x822a, 0x176e, 0x8205, 0x16a8,
+  0x81e2, 0x15e2, 0x81c1, 0x151c, 0x81a0, 0x1455, 0x8181, 0x138f,
+  0x8163, 0x12c8, 0x8146, 0x1201, 0x812a, 0x113a, 0x8110, 0x1073,
+  0x80f6, 0xfab, 0x80de, 0xee4, 0x80c8, 0xe1c, 0x80b2, 0xd54,
+  0x809e, 0xc8c, 0x808b, 0xbc4, 0x8079, 0xafb, 0x8068, 0xa33,
+  0x8059, 0x96b, 0x804b, 0x8a2, 0x803e, 0x7d9, 0x8032, 0x711,
+  0x8027, 0x648, 0x801e, 0x57f, 0x8016, 0x4b6, 0x800f, 0x3ed,
+  0x800a, 0x324, 0x8006, 0x25b, 0x8002, 0x192, 0x8001, 0xc9,
+  0x8000, 0x0, 0x8001, 0xff37, 0x8002, 0xfe6e, 0x8006, 0xfda5,
+  0x800a, 0xfcdc, 0x800f, 0xfc13, 0x8016, 0xfb4a, 0x801e, 0xfa81,
+  0x8027, 0xf9b8, 0x8032, 0xf8ef, 0x803e, 0xf827, 0x804b, 0xf75e,
+  0x8059, 0xf695, 0x8068, 0xf5cd, 0x8079, 0xf505, 0x808b, 0xf43c,
+  0x809e, 0xf374, 0x80b2, 0xf2ac, 0x80c8, 0xf1e4, 0x80de, 0xf11c,
+  0x80f6, 0xf055, 0x8110, 0xef8d, 0x812a, 0xeec6, 0x8146, 0xedff,
+  0x8163, 0xed38, 0x8181, 0xec71, 0x81a0, 0xebab, 0x81c1, 0xeae4,
+  0x81e2, 0xea1e, 0x8205, 0xe958, 0x822a, 0xe892, 0x824f, 0xe7cd,
+  0x8276, 0xe707, 0x829d, 0xe642, 0x82c6, 0xe57d, 0x82f1, 0xe4b9,
+  0x831c, 0xe3f4, 0x8349, 0xe330, 0x8377, 0xe26d, 0x83a6, 0xe1a9,
+  0x83d6, 0xe0e6, 0x8407, 0xe023, 0x843a, 0xdf61, 0x846e, 0xde9e,
+  0x84a3, 0xdddc, 0x84d9, 0xdd1b, 0x8511, 0xdc59, 0x8549, 0xdb99,
+  0x8583, 0xdad8, 0x85be, 0xda18, 0x85fa, 0xd958, 0x8637, 0xd898,
+  0x8676, 0xd7d9, 0x86b6, 0xd71b, 0x86f6, 0xd65c, 0x8738, 0xd59e,
+  0x877b, 0xd4e1, 0x87c0, 0xd424, 0x8805, 0xd367, 0x884c, 0xd2ab,
+  0x8894, 0xd1ef, 0x88dd, 0xd134, 0x8927, 0xd079, 0x8972, 0xcfbe,
+  0x89be, 0xcf04, 0x8a0c, 0xce4b, 0x8a5a, 0xcd92, 0x8aaa, 0xccd9,
+  0x8afb, 0xcc21, 0x8b4d, 0xcb69, 0x8ba0, 0xcab2, 0x8bf5, 0xc9fc,
+  0x8c4a, 0xc946, 0x8ca1, 0xc890, 0x8cf8, 0xc7db, 0x8d51, 0xc727,
+  0x8dab, 0xc673, 0x8e06, 0xc5c0, 0x8e62, 0xc50d, 0x8ebf, 0xc45b,
+  0x8f1d, 0xc3a9, 0x8f7d, 0xc2f8, 0x8fdd, 0xc248, 0x903e, 0xc198,
+  0x90a1, 0xc0e9, 0x9105, 0xc03a, 0x9169, 0xbf8c, 0x91cf, 0xbedf,
+  0x9236, 0xbe32, 0x929e, 0xbd86, 0x9307, 0xbcda, 0x9371, 0xbc2f,
+  0x93dc, 0xbb85, 0x9448, 0xbadc, 0x94b5, 0xba33, 0x9523, 0xb98b,
+  0x9592, 0xb8e3, 0x9603, 0xb83c, 0x9674, 0xb796, 0x96e6, 0xb6f1,
+  0x9759, 0xb64c, 0x97ce, 0xb5a8, 0x9843, 0xb505, 0x98b9, 0xb462,
+  0x9930, 0xb3c0, 0x99a9, 0xb31f, 0x9a22, 0xb27f, 0x9a9c, 0xb1df,
+  0x9b17, 0xb140, 0x9b94, 0xb0a2, 0x9c11, 0xb005, 0x9c8f, 0xaf68,
+  0x9d0e, 0xaecc, 0x9d8e, 0xae31, 0x9e0f, 0xad97, 0x9e91, 0xacfd,
+  0x9f14, 0xac65, 0x9f98, 0xabcd, 0xa01c, 0xab36, 0xa0a2, 0xaaa0,
+  0xa129, 0xaa0a, 0xa1b0, 0xa976, 0xa238, 0xa8e2, 0xa2c2, 0xa84f,
+  0xa34c, 0xa7bd, 0xa3d7, 0xa72c, 0xa463, 0xa69c, 0xa4f0, 0xa60c,
+  0xa57e, 0xa57e, 0xa60c, 0xa4f0, 0xa69c, 0xa463, 0xa72c, 0xa3d7,
+  0xa7bd, 0xa34c, 0xa84f, 0xa2c2, 0xa8e2, 0xa238, 0xa976, 0xa1b0,
+  0xaa0a, 0xa129, 0xaaa0, 0xa0a2, 0xab36, 0xa01c, 0xabcd, 0x9f98,
+  0xac65, 0x9f14, 0xacfd, 0x9e91, 0xad97, 0x9e0f, 0xae31, 0x9d8e,
+  0xaecc, 0x9d0e, 0xaf68, 0x9c8f, 0xb005, 0x9c11, 0xb0a2, 0x9b94,
+  0xb140, 0x9b17, 0xb1df, 0x9a9c, 0xb27f, 0x9a22, 0xb31f, 0x99a9,
+  0xb3c0, 0x9930, 0xb462, 0x98b9, 0xb505, 0x9843, 0xb5a8, 0x97ce,
+  0xb64c, 0x9759, 0xb6f1, 0x96e6, 0xb796, 0x9674, 0xb83c, 0x9603,
+  0xb8e3, 0x9592, 0xb98b, 0x9523, 0xba33, 0x94b5, 0xbadc, 0x9448,
+  0xbb85, 0x93dc, 0xbc2f, 0x9371, 0xbcda, 0x9307, 0xbd86, 0x929e,
+  0xbe32, 0x9236, 0xbedf, 0x91cf, 0xbf8c, 0x9169, 0xc03a, 0x9105,
+  0xc0e9, 0x90a1, 0xc198, 0x903e, 0xc248, 0x8fdd, 0xc2f8, 0x8f7d,
+  0xc3a9, 0x8f1d, 0xc45b, 0x8ebf, 0xc50d, 0x8e62, 0xc5c0, 0x8e06,
+  0xc673, 0x8dab, 0xc727, 0x8d51, 0xc7db, 0x8cf8, 0xc890, 0x8ca1,
+  0xc946, 0x8c4a, 0xc9fc, 0x8bf5, 0xcab2, 0x8ba0, 0xcb69, 0x8b4d,
+  0xcc21, 0x8afb, 0xccd9, 0x8aaa, 0xcd92, 0x8a5a, 0xce4b, 0x8a0c,
+  0xcf04, 0x89be, 0xcfbe, 0x8972, 0xd079, 0x8927, 0xd134, 0x88dd,
+  0xd1ef, 0x8894, 0xd2ab, 0x884c, 0xd367, 0x8805, 0xd424, 0x87c0,
+  0xd4e1, 0x877b, 0xd59e, 0x8738, 0xd65c, 0x86f6, 0xd71b, 0x86b6,
+  0xd7d9, 0x8676, 0xd898, 0x8637, 0xd958, 0x85fa, 0xda18, 0x85be,
+  0xdad8, 0x8583, 0xdb99, 0x8549, 0xdc59, 0x8511, 0xdd1b, 0x84d9,
+  0xdddc, 0x84a3, 0xde9e, 0x846e, 0xdf61, 0x843a, 0xe023, 0x8407,
+  0xe0e6, 0x83d6, 0xe1a9, 0x83a6, 0xe26d, 0x8377, 0xe330, 0x8349,
+  0xe3f4, 0x831c, 0xe4b9, 0x82f1, 0xe57d, 0x82c6, 0xe642, 0x829d,
+  0xe707, 0x8276, 0xe7cd, 0x824f, 0xe892, 0x822a, 0xe958, 0x8205,
+  0xea1e, 0x81e2, 0xeae4, 0x81c1, 0xebab, 0x81a0, 0xec71, 0x8181,
+  0xed38, 0x8163, 0xedff, 0x8146, 0xeec6, 0x812a, 0xef8d, 0x8110,
+  0xf055, 0x80f6, 0xf11c, 0x80de, 0xf1e4, 0x80c8, 0xf2ac, 0x80b2,
+  0xf374, 0x809e, 0xf43c, 0x808b, 0xf505, 0x8079, 0xf5cd, 0x8068,
+  0xf695, 0x8059, 0xf75e, 0x804b, 0xf827, 0x803e, 0xf8ef, 0x8032,
+  0xf9b8, 0x8027, 0xfa81, 0x801e, 0xfb4a, 0x8016, 0xfc13, 0x800f,
+  0xfcdc, 0x800a, 0xfda5, 0x8006, 0xfe6e, 0x8002, 0xff37, 0x8001,
+  0x0, 0x8000, 0xc9, 0x8001, 0x192, 0x8002, 0x25b, 0x8006,
+  0x324, 0x800a, 0x3ed, 0x800f, 0x4b6, 0x8016, 0x57f, 0x801e,
+  0x648, 0x8027, 0x711, 0x8032, 0x7d9, 0x803e, 0x8a2, 0x804b,
+  0x96b, 0x8059, 0xa33, 0x8068, 0xafb, 0x8079, 0xbc4, 0x808b,
+  0xc8c, 0x809e, 0xd54, 0x80b2, 0xe1c, 0x80c8, 0xee4, 0x80de,
+  0xfab, 0x80f6, 0x1073, 0x8110, 0x113a, 0x812a, 0x1201, 0x8146,
+  0x12c8, 0x8163, 0x138f, 0x8181, 0x1455, 0x81a0, 0x151c, 0x81c1,
+  0x15e2, 0x81e2, 0x16a8, 0x8205, 0x176e, 0x822a, 0x1833, 0x824f,
+  0x18f9, 0x8276, 0x19be, 0x829d, 0x1a83, 0x82c6, 0x1b47, 0x82f1,
+  0x1c0c, 0x831c, 0x1cd0, 0x8349, 0x1d93, 0x8377, 0x1e57, 0x83a6,
+  0x1f1a, 0x83d6, 0x1fdd, 0x8407, 0x209f, 0x843a, 0x2162, 0x846e,
+  0x2224, 0x84a3, 0x22e5, 0x84d9, 0x23a7, 0x8511, 0x2467, 0x8549,
+  0x2528, 0x8583, 0x25e8, 0x85be, 0x26a8, 0x85fa, 0x2768, 0x8637,
+  0x2827, 0x8676, 0x28e5, 0x86b6, 0x29a4, 0x86f6, 0x2a62, 0x8738,
+  0x2b1f, 0x877b, 0x2bdc, 0x87c0, 0x2c99, 0x8805, 0x2d55, 0x884c,
+  0x2e11, 0x8894, 0x2ecc, 0x88dd, 0x2f87, 0x8927, 0x3042, 0x8972,
+  0x30fc, 0x89be, 0x31b5, 0x8a0c, 0x326e, 0x8a5a, 0x3327, 0x8aaa,
+  0x33df, 0x8afb, 0x3497, 0x8b4d, 0x354e, 0x8ba0, 0x3604, 0x8bf5,
+  0x36ba, 0x8c4a, 0x3770, 0x8ca1, 0x3825, 0x8cf8, 0x38d9, 0x8d51,
+  0x398d, 0x8dab, 0x3a40, 0x8e06, 0x3af3, 0x8e62, 0x3ba5, 0x8ebf,
+  0x3c57, 0x8f1d, 0x3d08, 0x8f7d, 0x3db8, 0x8fdd, 0x3e68, 0x903e,
+  0x3f17, 0x90a1, 0x3fc6, 0x9105, 0x4074, 0x9169, 0x4121, 0x91cf,
+  0x41ce, 0x9236, 0x427a, 0x929e, 0x4326, 0x9307, 0x43d1, 0x9371,
+  0x447b, 0x93dc, 0x4524, 0x9448, 0x45cd, 0x94b5, 0x4675, 0x9523,
+  0x471d, 0x9592, 0x47c4, 0x9603, 0x486a, 0x9674, 0x490f, 0x96e6,
+  0x49b4, 0x9759, 0x4a58, 0x97ce, 0x4afb, 0x9843, 0x4b9e, 0x98b9,
+  0x4c40, 0x9930, 0x4ce1, 0x99a9, 0x4d81, 0x9a22, 0x4e21, 0x9a9c,
+  0x4ec0, 0x9b17, 0x4f5e, 0x9b94, 0x4ffb, 0x9c11, 0x5098, 0x9c8f,
+  0x5134, 0x9d0e, 0x51cf, 0x9d8e, 0x5269, 0x9e0f, 0x5303, 0x9e91,
+  0x539b, 0x9f14, 0x5433, 0x9f98, 0x54ca, 0xa01c, 0x5560, 0xa0a2,
+  0x55f6, 0xa129, 0x568a, 0xa1b0, 0x571e, 0xa238, 0x57b1, 0xa2c2,
+  0x5843, 0xa34c, 0x58d4, 0xa3d7, 0x5964, 0xa463, 0x59f4, 0xa4f0,
+  0x5a82, 0xa57e, 0x5b10, 0xa60c, 0x5b9d, 0xa69c, 0x5c29, 0xa72c,
+  0x5cb4, 0xa7bd, 0x5d3e, 0xa84f, 0x5dc8, 0xa8e2, 0x5e50, 0xa976,
+  0x5ed7, 0xaa0a, 0x5f5e, 0xaaa0, 0x5fe4, 0xab36, 0x6068, 0xabcd,
+  0x60ec, 0xac65, 0x616f, 0xacfd, 0x61f1, 0xad97, 0x6272, 0xae31,
+  0x62f2, 0xaecc, 0x6371, 0xaf68, 0x63ef, 0xb005, 0x646c, 0xb0a2,
+  0x64e9, 0xb140, 0x6564, 0xb1df, 0x65de, 0xb27f, 0x6657, 0xb31f,
+  0x66d0, 0xb3c0, 0x6747, 0xb462, 0x67bd, 0xb505, 0x6832, 0xb5a8,
+  0x68a7, 0xb64c, 0x691a, 0xb6f1, 0x698c, 0xb796, 0x69fd, 0xb83c,
+  0x6a6e, 0xb8e3, 0x6add, 0xb98b, 0x6b4b, 0xba33, 0x6bb8, 0xbadc,
+  0x6c24, 0xbb85, 0x6c8f, 0xbc2f, 0x6cf9, 0xbcda, 0x6d62, 0xbd86,
+  0x6dca, 0xbe32, 0x6e31, 0xbedf, 0x6e97, 0xbf8c, 0x6efb, 0xc03a,
+  0x6f5f, 0xc0e9, 0x6fc2, 0xc198, 0x7023, 0xc248, 0x7083, 0xc2f8,
+  0x70e3, 0xc3a9, 0x7141, 0xc45b, 0x719e, 0xc50d, 0x71fa, 0xc5c0,
+  0x7255, 0xc673, 0x72af, 0xc727, 0x7308, 0xc7db, 0x735f, 0xc890,
+  0x73b6, 0xc946, 0x740b, 0xc9fc, 0x7460, 0xcab2, 0x74b3, 0xcb69,
+  0x7505, 0xcc21, 0x7556, 0xccd9, 0x75a6, 0xcd92, 0x75f4, 0xce4b,
+  0x7642, 0xcf04, 0x768e, 0xcfbe, 0x76d9, 0xd079, 0x7723, 0xd134,
+  0x776c, 0xd1ef, 0x77b4, 0xd2ab, 0x77fb, 0xd367, 0x7840, 0xd424,
+  0x7885, 0xd4e1, 0x78c8, 0xd59e, 0x790a, 0xd65c, 0x794a, 0xd71b,
+  0x798a, 0xd7d9, 0x79c9, 0xd898, 0x7a06, 0xd958, 0x7a42, 0xda18,
+  0x7a7d, 0xdad8, 0x7ab7, 0xdb99, 0x7aef, 0xdc59, 0x7b27, 0xdd1b,
+  0x7b5d, 0xdddc, 0x7b92, 0xde9e, 0x7bc6, 0xdf61, 0x7bf9, 0xe023,
+  0x7c2a, 0xe0e6, 0x7c5a, 0xe1a9, 0x7c89, 0xe26d, 0x7cb7, 0xe330,
+  0x7ce4, 0xe3f4, 0x7d0f, 0xe4b9, 0x7d3a, 0xe57d, 0x7d63, 0xe642,
+  0x7d8a, 0xe707, 0x7db1, 0xe7cd, 0x7dd6, 0xe892, 0x7dfb, 0xe958,
+  0x7e1e, 0xea1e, 0x7e3f, 0xeae4, 0x7e60, 0xebab, 0x7e7f, 0xec71,
+  0x7e9d, 0xed38, 0x7eba, 0xedff, 0x7ed6, 0xeec6, 0x7ef0, 0xef8d,
+  0x7f0a, 0xf055, 0x7f22, 0xf11c, 0x7f38, 0xf1e4, 0x7f4e, 0xf2ac,
+  0x7f62, 0xf374, 0x7f75, 0xf43c, 0x7f87, 0xf505, 0x7f98, 0xf5cd,
+  0x7fa7, 0xf695, 0x7fb5, 0xf75e, 0x7fc2, 0xf827, 0x7fce, 0xf8ef,
+  0x7fd9, 0xf9b8, 0x7fe2, 0xfa81, 0x7fea, 0xfb4a, 0x7ff1, 0xfc13,
+  0x7ff6, 0xfcdc, 0x7ffa, 0xfda5, 0x7ffe, 0xfe6e, 0x7fff, 0xff37
+};
+
+
+/**   
+* @brief Initialization function for the Q15 CFFT/CIFFT.  
+* @param[in,out] *S             points to an instance of the Q15 CFFT/CIFFT structure.  
+* @param[in]     fftLen         length of the FFT.  
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.  
+*   
+* \par Description:  
+* \par   
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.   
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated  
+* \par   
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
+* \par   
+* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.   
+* \par   
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   
+*/
+
+arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (q15_t *) twiddleCoefQ15;
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of structure parameters depending on the FFT length */
+  switch (S->fftLen)
+  {
+    /*  Initializations of structure parameters for 1024 point FFT */
+  case 1024u:
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = armBitRevTable;
+
+    break;
+  case 256u:
+    /*  Initializations of structure parameters for 2566 point FFT */
+    S->twidCoefModifier = 4u;
+    S->bitRevFactor = 4u;
+    S->pBitRevTable = &armBitRevTable[3];
+
+    break;
+  case 64u:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 16u;
+    S->bitRevFactor = 16u;
+    S->pBitRevTable = &armBitRevTable[15];
+
+    break;
+  case 16u:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 64u;
+    S->bitRevFactor = 64u;
+    S->pBitRevTable = &armBitRevTable[63];
+
+    break;
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**   
+ * @} end of CFFT_CIFFT group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c
new file mode 100644
index 000000000..fb12905e5
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c
@@ -0,0 +1,1197 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix4_init_q31.c   
+*   
+* Description:	Radix-4 Decimation in Frequency Q31 FFT & IFFT initialization function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+* 
+** Version 1.0.11 2011/08/17 
+*    Updated to support 4096 CFFT length.  
+*
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup CFFT_CIFFT   
+ * @{   
+ */
+
+/*   
+* @brief  Twiddle factors Table   
+*/
+
+/**   
+* \par  
+* Example code for Q31 Twiddle factors Generation::   
+* \par   
+* 
for(i = 0; i< N; i++)   
+* {   
+*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);   
+*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);   
+* } 
   
+* \par   
+* where N = 1024	and PI = 3.14159265358979   
+* \par   
+* Cos and Sin values are interleaved fashion   
+* \par   
+* Convert Floating point to Q31(Fixed point 1.31):   
+*	round(twiddleCoefQ31(i) * pow(2, 31))   
+*   
+*/
+
+static const q31_t twiddleCoefQ31[4096*2] = {
+  0x7fffffff,	0x0,	0x7ffff621,	0x3243f5,	0x7fffd886,	0x6487e3,	0x7fffa72c,	0x96cbc1,
+	0x7fff6216,	0xc90f88,	0x7fff0943,	0xfb5330,	0x7ffe9cb2,	0x12d96b1,	0x7ffe1c65,	0x15fda03,
+	0x7ffd885a,	0x1921d20,	0x7ffce093,	0x1c45ffe,	0x7ffc250f,	0x1f6a297,	0x7ffb55ce,	0x228e4e2,
+	0x7ffa72d1,	0x25b26d7,	0x7ff97c18,	0x28d6870,	0x7ff871a2,	0x2bfa9a4,	0x7ff75370,	0x2f1ea6c,
+	0x7ff62182,	0x3242abf,	0x7ff4dbd9,	0x3566a96,	0x7ff38274,	0x388a9ea,	0x7ff21553,	0x3bae8b2,
+	0x7ff09478,	0x3ed26e6,	0x7feeffe1,	0x41f6480,	0x7fed5791,	0x451a177,	0x7feb9b85,	0x483ddc3,
+	0x7fe9cbc0,	0x4b6195d,	0x7fe7e841,	0x4e8543e,	0x7fe5f108,	0x51a8e5c,	0x7fe3e616,	0x54cc7b1,
+	0x7fe1c76b,	0x57f0035,	0x7fdf9508,	0x5b137df,	0x7fdd4eec,	0x5e36ea9,	0x7fdaf519,	0x615a48b,
+	0x7fd8878e,	0x647d97c,	0x7fd6064c,	0x67a0d76,	0x7fd37153,	0x6ac406f,	0x7fd0c8a3,	0x6de7262,
+	0x7fce0c3e,	0x710a345,	0x7fcb3c23,	0x742d311,	0x7fc85854,	0x77501be,	0x7fc560cf,	0x7a72f45,
+	0x7fc25596,	0x7d95b9e,	0x7fbf36aa,	0x80b86c2,	0x7fbc040a,	0x83db0a7,	0x7fb8bdb8,	0x86fd947,
+	0x7fb563b3,	0x8a2009a,	0x7fb1f5fc,	0x8d42699,	0x7fae7495,	0x9064b3a,	0x7faadf7c,	0x9386e78,
+	0x7fa736b4,	0x96a9049,	0x7fa37a3c,	0x99cb0a7,	0x7f9faa15,	0x9cecf89,	0x7f9bc640,	0xa00ece8,
+	0x7f97cebd,	0xa3308bd,	0x7f93c38c,	0xa6522fe,	0x7f8fa4b0,	0xa973ba5,	0x7f8b7227,	0xac952aa,
+	0x7f872bf3,	0xafb6805,	0x7f82d214,	0xb2d7baf,	0x7f7e648c,	0xb5f8d9f,	0x7f79e35a,	0xb919dcf,
+	0x7f754e80,	0xbc3ac35,	0x7f70a5fe,	0xbf5b8cb,	0x7f6be9d4,	0xc27c389,	0x7f671a05,	0xc59cc68,
+	0x7f62368f,	0xc8bd35e,	0x7f5d3f75,	0xcbdd865,	0x7f5834b7,	0xcefdb76,	0x7f531655,	0xd21dc87,
+	0x7f4de451,	0xd53db92,	0x7f489eaa,	0xd85d88f,	0x7f434563,	0xdb7d376,	0x7f3dd87c,	0xde9cc40,
+	0x7f3857f6,	0xe1bc2e4,	0x7f32c3d1,	0xe4db75b,	0x7f2d1c0e,	0xe7fa99e,	0x7f2760af,	0xeb199a4,
+	0x7f2191b4,	0xee38766,	0x7f1baf1e,	0xf1572dc,	0x7f15b8ee,	0xf475bff,	0x7f0faf25,	0xf7942c7,
+	0x7f0991c4,	0xfab272b,	0x7f0360cb,	0xfdd0926,	0x7efd1c3c,	0x100ee8ad,	0x7ef6c418,	0x1040c5bb,
+	0x7ef05860,	0x1072a048,	0x7ee9d914,	0x10a4784b,	0x7ee34636,	0x10d64dbd,	0x7edc9fc6,	0x11082096,
+	0x7ed5e5c6,	0x1139f0cf,	0x7ecf1837,	0x116bbe60,	0x7ec8371a,	0x119d8941,	0x7ec14270,	0x11cf516a,
+	0x7eba3a39,	0x120116d5,	0x7eb31e78,	0x1232d979,	0x7eabef2c,	0x1264994e,	0x7ea4ac58,	0x1296564d,
+	0x7e9d55fc,	0x12c8106f,	0x7e95ec1a,	0x12f9c7aa,	0x7e8e6eb2,	0x132b7bf9,	0x7e86ddc6,	0x135d2d53,
+	0x7e7f3957,	0x138edbb1,	0x7e778166,	0x13c0870a,	0x7e6fb5f4,	0x13f22f58,	0x7e67d703,	0x1423d492,
+	0x7e5fe493,	0x145576b1,	0x7e57dea7,	0x148715ae,	0x7e4fc53e,	0x14b8b17f,	0x7e47985b,	0x14ea4a1f,
+	0x7e3f57ff,	0x151bdf86,	0x7e37042a,	0x154d71aa,	0x7e2e9cdf,	0x157f0086,	0x7e26221f,	0x15b08c12,
+	0x7e1d93ea,	0x15e21445,	0x7e14f242,	0x16139918,	0x7e0c3d29,	0x16451a83,	0x7e0374a0,	0x1676987f,
+	0x7dfa98a8,	0x16a81305,	0x7df1a942,	0x16d98a0c,	0x7de8a670,	0x170afd8d,	0x7ddf9034,	0x173c6d80,
+	0x7dd6668f,	0x176dd9de,	0x7dcd2981,	0x179f429f,	0x7dc3d90d,	0x17d0a7bc,	0x7dba7534,	0x1802092c,
+	0x7db0fdf8,	0x183366e9,	0x7da77359,	0x1864c0ea,	0x7d9dd55a,	0x18961728,	0x7d9423fc,	0x18c7699b,
+	0x7d8a5f40,	0x18f8b83c,	0x7d808728,	0x192a0304,	0x7d769bb5,	0x195b49ea,	0x7d6c9ce9,	0x198c8ce7,
+	0x7d628ac6,	0x19bdcbf3,	0x7d58654d,	0x19ef0707,	0x7d4e2c7f,	0x1a203e1b,	0x7d43e05e,	0x1a517128,
+	0x7d3980ec,	0x1a82a026,	0x7d2f0e2b,	0x1ab3cb0d,	0x7d24881b,	0x1ae4f1d6,	0x7d19eebf,	0x1b161479,
+	0x7d0f4218,	0x1b4732ef,	0x7d048228,	0x1b784d30,	0x7cf9aef0,	0x1ba96335,	0x7ceec873,	0x1bda74f6,
+	0x7ce3ceb2,	0x1c0b826a,	0x7cd8c1ae,	0x1c3c8b8c,	0x7ccda169,	0x1c6d9053,	0x7cc26de5,	0x1c9e90b8,
+	0x7cb72724,	0x1ccf8cb3,	0x7cabcd28,	0x1d00843d,	0x7ca05ff1,	0x1d31774d,	0x7c94df83,	0x1d6265dd,
+	0x7c894bde,	0x1d934fe5,	0x7c7da505,	0x1dc4355e,	0x7c71eaf9,	0x1df5163f,	0x7c661dbc,	0x1e25f282,
+	0x7c5a3d50,	0x1e56ca1e,	0x7c4e49b7,	0x1e879d0d,	0x7c4242f2,	0x1eb86b46,	0x7c362904,	0x1ee934c3,
+	0x7c29fbee,	0x1f19f97b,	0x7c1dbbb3,	0x1f4ab968,	0x7c116853,	0x1f7b7481,	0x7c0501d2,	0x1fac2abf,
+	0x7bf88830,	0x1fdcdc1b,	0x7bebfb70,	0x200d888d,	0x7bdf5b94,	0x203e300d,	0x7bd2a89e,	0x206ed295,
+	0x7bc5e290,	0x209f701c,	0x7bb9096b,	0x20d0089c,	0x7bac1d31,	0x21009c0c,	0x7b9f1de6,	0x21312a65,
+	0x7b920b89,	0x2161b3a0,	0x7b84e61f,	0x219237b5,	0x7b77ada8,	0x21c2b69c,	0x7b6a6227,	0x21f3304f,
+	0x7b5d039e,	0x2223a4c5,	0x7b4f920e,	0x225413f8,	0x7b420d7a,	0x22847de0,	0x7b3475e5,	0x22b4e274,
+	0x7b26cb4f,	0x22e541af,	0x7b190dbc,	0x23159b88,	0x7b0b3d2c,	0x2345eff8,	0x7afd59a4,	0x23763ef7,
+	0x7aef6323,	0x23a6887f,	0x7ae159ae,	0x23d6cc87,	0x7ad33d45,	0x24070b08,	0x7ac50dec,	0x243743fa,
+	0x7ab6cba4,	0x24677758,	0x7aa8766f,	0x2497a517,	0x7a9a0e50,	0x24c7cd33,	0x7a8b9348,	0x24f7efa2,
+	0x7a7d055b,	0x25280c5e,	0x7a6e648a,	0x2558235f,	0x7a5fb0d8,	0x2588349d,	0x7a50ea47,	0x25b84012,
+	0x7a4210d8,	0x25e845b6,	0x7a332490,	0x26184581,	0x7a24256f,	0x26483f6c,	0x7a151378,	0x26783370,
+	0x7a05eead,	0x26a82186,	0x79f6b711,	0x26d809a5,	0x79e76ca7,	0x2707ebc7,	0x79d80f6f,	0x2737c7e3,
+	0x79c89f6e,	0x27679df4,	0x79b91ca4,	0x27976df1,	0x79a98715,	0x27c737d3,	0x7999dec4,	0x27f6fb92,
+	0x798a23b1,	0x2826b928,	0x797a55e0,	0x2856708d,	0x796a7554,	0x288621b9,	0x795a820e,	0x28b5cca5,
+	0x794a7c12,	0x28e5714b,	0x793a6361,	0x29150fa1,	0x792a37fe,	0x2944a7a2,	0x7919f9ec,	0x29743946,
+	0x7909a92d,	0x29a3c485,	0x78f945c3,	0x29d34958,	0x78e8cfb2,	0x2a02c7b8,	0x78d846fb,	0x2a323f9e,
+	0x78c7aba2,	0x2a61b101,	0x78b6fda8,	0x2a911bdc,	0x78a63d11,	0x2ac08026,	0x789569df,	0x2aefddd8,
+	0x78848414,	0x2b1f34eb,	0x78738bb3,	0x2b4e8558,	0x786280bf,	0x2b7dcf17,	0x7851633b,	0x2bad1221,
+	0x78403329,	0x2bdc4e6f,	0x782ef08b,	0x2c0b83fa,	0x781d9b65,	0x2c3ab2b9,	0x780c33b8,	0x2c69daa6,
+	0x77fab989,	0x2c98fbba,	0x77e92cd9,	0x2cc815ee,	0x77d78daa,	0x2cf72939,	0x77c5dc01,	0x2d263596,
+	0x77b417df,	0x2d553afc,	0x77a24148,	0x2d843964,	0x7790583e,	0x2db330c7,	0x777e5cc3,	0x2de2211e,
+	0x776c4edb,	0x2e110a62,	0x775a2e89,	0x2e3fec8b,	0x7747fbce,	0x2e6ec792,	0x7735b6af,	0x2e9d9b70,
+	0x77235f2d,	0x2ecc681e,	0x7710f54c,	0x2efb2d95,	0x76fe790e,	0x2f29ebcc,	0x76ebea77,	0x2f58a2be,
+	0x76d94989,	0x2f875262,	0x76c69647,	0x2fb5fab2,	0x76b3d0b4,	0x2fe49ba7,	0x76a0f8d2,	0x30133539,
+	0x768e0ea6,	0x3041c761,	0x767b1231,	0x30705217,	0x76680376,	0x309ed556,	0x7654e279,	0x30cd5115,
+	0x7641af3d,	0x30fbc54d,	0x762e69c4,	0x312a31f8,	0x761b1211,	0x3158970e,	0x7607a828,	0x3186f487,
+	0x75f42c0b,	0x31b54a5e,	0x75e09dbd,	0x31e39889,	0x75ccfd42,	0x3211df04,	0x75b94a9c,	0x32401dc6,
+	0x75a585cf,	0x326e54c7,	0x7591aedd,	0x329c8402,	0x757dc5ca,	0x32caab6f,	0x7569ca99,	0x32f8cb07,
+	0x7555bd4c,	0x3326e2c3,	0x75419de7,	0x3354f29b,	0x752d6c6c,	0x3382fa88,	0x751928e0,	0x33b0fa84,
+	0x7504d345,	0x33def287,	0x74f06b9e,	0x340ce28b,	0x74dbf1ef,	0x343aca87,	0x74c7663a,	0x3468aa76,
+	0x74b2c884,	0x34968250,	0x749e18cd,	0x34c4520d,	0x7489571c,	0x34f219a8,	0x74748371,	0x351fd918,
+	0x745f9dd1,	0x354d9057,	0x744aa63f,	0x357b3f5d,	0x74359cbd,	0x35a8e625,	0x74208150,	0x35d684a6,
+	0x740b53fb,	0x36041ad9,	0x73f614c0,	0x3631a8b8,	0x73e0c3a3,	0x365f2e3b,	0x73cb60a8,	0x368cab5c,
+	0x73b5ebd1,	0x36ba2014,	0x73a06522,	0x36e78c5b,	0x738acc9e,	0x3714f02a,	0x73752249,	0x37424b7b,
+	0x735f6626,	0x376f9e46,	0x73499838,	0x379ce885,	0x7333b883,	0x37ca2a30,	0x731dc70a,	0x37f76341,
+	0x7307c3d0,	0x382493b0,	0x72f1aed9,	0x3851bb77,	0x72db8828,	0x387eda8e,	0x72c54fc1,	0x38abf0ef,
+	0x72af05a7,	0x38d8fe93,	0x7298a9dd,	0x39060373,	0x72823c67,	0x3932ff87,	0x726bbd48,	0x395ff2c9,
+	0x72552c85,	0x398cdd32,	0x723e8a20,	0x39b9bebc,	0x7227d61c,	0x39e6975e,	0x7211107e,	0x3a136712,
+	0x71fa3949,	0x3a402dd2,	0x71e35080,	0x3a6ceb96,	0x71cc5626,	0x3a99a057,	0x71b54a41,	0x3ac64c0f,
+	0x719e2cd2,	0x3af2eeb7,	0x7186fdde,	0x3b1f8848,	0x716fbd68,	0x3b4c18ba,	0x71586b74,	0x3b78a007,
+	0x71410805,	0x3ba51e29,	0x7129931f,	0x3bd19318,	0x71120cc5,	0x3bfdfecd,	0x70fa74fc,	0x3c2a6142,
+	0x70e2cbc6,	0x3c56ba70,	0x70cb1128,	0x3c830a50,	0x70b34525,	0x3caf50da,	0x709b67c0,	0x3cdb8e09,
+	0x708378ff,	0x3d07c1d6,	0x706b78e3,	0x3d33ec39,	0x70536771,	0x3d600d2c,	0x703b44ad,	0x3d8c24a8,
+	0x7023109a,	0x3db832a6,	0x700acb3c,	0x3de4371f,	0x6ff27497,	0x3e10320d,	0x6fda0cae,	0x3e3c2369,
+	0x6fc19385,	0x3e680b2c,	0x6fa90921,	0x3e93e950,	0x6f906d84,	0x3ebfbdcd,	0x6f77c0b3,	0x3eeb889c,
+	0x6f5f02b2,	0x3f1749b8,	0x6f463383,	0x3f430119,	0x6f2d532c,	0x3f6eaeb8,	0x6f1461b0,	0x3f9a5290,
+	0x6efb5f12,	0x3fc5ec98,	0x6ee24b57,	0x3ff17cca,	0x6ec92683,	0x401d0321,	0x6eaff099,	0x40487f94,
+	0x6e96a99d,	0x4073f21d,	0x6e7d5193,	0x409f5ab6,	0x6e63e87f,	0x40cab958,	0x6e4a6e66,	0x40f60dfb,
+	0x6e30e34a,	0x4121589b,	0x6e174730,	0x414c992f,	0x6dfd9a1c,	0x4177cfb1,	0x6de3dc11,	0x41a2fc1a,
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+	0x2d553afc,	0x884be821,	0x2d843964,	0x885dbeb8,	0x2db330c7,	0x886fa7c2,	0x2de2211e,	0x8881a33d,
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+	0x2f875262,	0x8926b677,	0x2fb5fab2,	0x893969b9,	0x2fe49ba7,	0x894c2f4c,	0x30133539,	0x895f072e,
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+	0x3326e2c3,	0x8aaa42b4,	0x3354f29b,	0x8abe6219,	0x3382fa88,	0x8ad29394,	0x33b0fa84,	0x8ae6d720,
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+	0x77235f2d,	0xd13397e2,	0x7735b6af,	0xd1626490,	0x7747fbce,	0xd191386e,	0x775a2e89,	0xd1c01375,
+	0x776c4edb,	0xd1eef59e,	0x777e5cc3,	0xd21ddee2,	0x7790583e,	0xd24ccf39,	0x77a24148,	0xd27bc69c,
+	0x77b417df,	0xd2aac504,	0x77c5dc01,	0xd2d9ca6a,	0x77d78daa,	0xd308d6c7,	0x77e92cd9,	0xd337ea12,
+	0x77fab989,	0xd3670446,	0x780c33b8,	0xd396255a,	0x781d9b65,	0xd3c54d47,	0x782ef08b,	0xd3f47c06,
+	0x78403329,	0xd423b191,	0x7851633b,	0xd452eddf,	0x786280bf,	0xd48230e9,	0x78738bb3,	0xd4b17aa8,
+	0x78848414,	0xd4e0cb15,	0x789569df,	0xd5102228,	0x78a63d11,	0xd53f7fda,	0x78b6fda8,	0xd56ee424,
+	0x78c7aba2,	0xd59e4eff,	0x78d846fb,	0xd5cdc062,	0x78e8cfb2,	0xd5fd3848,	0x78f945c3,	0xd62cb6a8,
+	0x7909a92d,	0xd65c3b7b,	0x7919f9ec,	0xd68bc6ba,	0x792a37fe,	0xd6bb585e,	0x793a6361,	0xd6eaf05f,
+	0x794a7c12,	0xd71a8eb5,	0x795a820e,	0xd74a335b,	0x796a7554,	0xd779de47,	0x797a55e0,	0xd7a98f73,
+	0x798a23b1,	0xd7d946d8,	0x7999dec4,	0xd809046e,	0x79a98715,	0xd838c82d,	0x79b91ca4,	0xd868920f,
+	0x79c89f6e,	0xd898620c,	0x79d80f6f,	0xd8c8381d,	0x79e76ca7,	0xd8f81439,	0x79f6b711,	0xd927f65b,
+	0x7a05eead,	0xd957de7a,	0x7a151378,	0xd987cc90,	0x7a24256f,	0xd9b7c094,	0x7a332490,	0xd9e7ba7f,
+	0x7a4210d8,	0xda17ba4a,	0x7a50ea47,	0xda47bfee,	0x7a5fb0d8,	0xda77cb63,	0x7a6e648a,	0xdaa7dca1,
+	0x7a7d055b,	0xdad7f3a2,	0x7a8b9348,	0xdb08105e,	0x7a9a0e50,	0xdb3832cd,	0x7aa8766f,	0xdb685ae9,
+	0x7ab6cba4,	0xdb9888a8,	0x7ac50dec,	0xdbc8bc06,	0x7ad33d45,	0xdbf8f4f8,	0x7ae159ae,	0xdc293379,
+	0x7aef6323,	0xdc597781,	0x7afd59a4,	0xdc89c109,	0x7b0b3d2c,	0xdcba1008,	0x7b190dbc,	0xdcea6478,
+	0x7b26cb4f,	0xdd1abe51,	0x7b3475e5,	0xdd4b1d8c,	0x7b420d7a,	0xdd7b8220,	0x7b4f920e,	0xddabec08,
+	0x7b5d039e,	0xdddc5b3b,	0x7b6a6227,	0xde0ccfb1,	0x7b77ada8,	0xde3d4964,	0x7b84e61f,	0xde6dc84b,
+	0x7b920b89,	0xde9e4c60,	0x7b9f1de6,	0xdeced59b,	0x7bac1d31,	0xdeff63f4,	0x7bb9096b,	0xdf2ff764,
+	0x7bc5e290,	0xdf608fe4,	0x7bd2a89e,	0xdf912d6b,	0x7bdf5b94,	0xdfc1cff3,	0x7bebfb70,	0xdff27773,
+	0x7bf88830,	0xe02323e5,	0x7c0501d2,	0xe053d541,	0x7c116853,	0xe0848b7f,	0x7c1dbbb3,	0xe0b54698,
+	0x7c29fbee,	0xe0e60685,	0x7c362904,	0xe116cb3d,	0x7c4242f2,	0xe14794ba,	0x7c4e49b7,	0xe17862f3,
+	0x7c5a3d50,	0xe1a935e2,	0x7c661dbc,	0xe1da0d7e,	0x7c71eaf9,	0xe20ae9c1,	0x7c7da505,	0xe23bcaa2,
+	0x7c894bde,	0xe26cb01b,	0x7c94df83,	0xe29d9a23,	0x7ca05ff1,	0xe2ce88b3,	0x7cabcd28,	0xe2ff7bc3,
+	0x7cb72724,	0xe330734d,	0x7cc26de5,	0xe3616f48,	0x7ccda169,	0xe3926fad,	0x7cd8c1ae,	0xe3c37474,
+	0x7ce3ceb2,	0xe3f47d96,	0x7ceec873,	0xe4258b0a,	0x7cf9aef0,	0xe4569ccb,	0x7d048228,	0xe487b2d0,
+	0x7d0f4218,	0xe4b8cd11,	0x7d19eebf,	0xe4e9eb87,	0x7d24881b,	0xe51b0e2a,	0x7d2f0e2b,	0xe54c34f3,
+	0x7d3980ec,	0xe57d5fda,	0x7d43e05e,	0xe5ae8ed8,	0x7d4e2c7f,	0xe5dfc1e5,	0x7d58654d,	0xe610f8f9,
+	0x7d628ac6,	0xe642340d,	0x7d6c9ce9,	0xe6737319,	0x7d769bb5,	0xe6a4b616,	0x7d808728,	0xe6d5fcfc,
+	0x7d8a5f40,	0xe70747c4,	0x7d9423fc,	0xe7389665,	0x7d9dd55a,	0xe769e8d8,	0x7da77359,	0xe79b3f16,
+	0x7db0fdf8,	0xe7cc9917,	0x7dba7534,	0xe7fdf6d4,	0x7dc3d90d,	0xe82f5844,	0x7dcd2981,	0xe860bd61,
+	0x7dd6668f,	0xe8922622,	0x7ddf9034,	0xe8c39280,	0x7de8a670,	0xe8f50273,	0x7df1a942,	0xe92675f4,
+	0x7dfa98a8,	0xe957ecfb,	0x7e0374a0,	0xe9896781,	0x7e0c3d29,	0xe9bae57d,	0x7e14f242,	0xe9ec66e8,
+	0x7e1d93ea,	0xea1debbb,	0x7e26221f,	0xea4f73ee,	0x7e2e9cdf,	0xea80ff7a,	0x7e37042a,	0xeab28e56,
+	0x7e3f57ff,	0xeae4207a,	0x7e47985b,	0xeb15b5e1,	0x7e4fc53e,	0xeb474e81,	0x7e57dea7,	0xeb78ea52,
+	0x7e5fe493,	0xebaa894f,	0x7e67d703,	0xebdc2b6e,	0x7e6fb5f4,	0xec0dd0a8,	0x7e778166,	0xec3f78f6,
+	0x7e7f3957,	0xec71244f,	0x7e86ddc6,	0xeca2d2ad,	0x7e8e6eb2,	0xecd48407,	0x7e95ec1a,	0xed063856,
+	0x7e9d55fc,	0xed37ef91,	0x7ea4ac58,	0xed69a9b3,	0x7eabef2c,	0xed9b66b2,	0x7eb31e78,	0xedcd2687,
+	0x7eba3a39,	0xedfee92b,	0x7ec14270,	0xee30ae96,	0x7ec8371a,	0xee6276bf,	0x7ecf1837,	0xee9441a0,
+	0x7ed5e5c6,	0xeec60f31,	0x7edc9fc6,	0xeef7df6a,	0x7ee34636,	0xef29b243,	0x7ee9d914,	0xef5b87b5,
+	0x7ef05860,	0xef8d5fb8,	0x7ef6c418,	0xefbf3a45,	0x7efd1c3c,	0xeff11753,	0x7f0360cb,	0xf022f6da,
+	0x7f0991c4,	0xf054d8d5,	0x7f0faf25,	0xf086bd39,	0x7f15b8ee,	0xf0b8a401,	0x7f1baf1e,	0xf0ea8d24,
+	0x7f2191b4,	0xf11c789a,	0x7f2760af,	0xf14e665c,	0x7f2d1c0e,	0xf1805662,	0x7f32c3d1,	0xf1b248a5,
+	0x7f3857f6,	0xf1e43d1c,	0x7f3dd87c,	0xf21633c0,	0x7f434563,	0xf2482c8a,	0x7f489eaa,	0xf27a2771,
+	0x7f4de451,	0xf2ac246e,	0x7f531655,	0xf2de2379,	0x7f5834b7,	0xf310248a,	0x7f5d3f75,	0xf342279b,
+	0x7f62368f,	0xf3742ca2,	0x7f671a05,	0xf3a63398,	0x7f6be9d4,	0xf3d83c77,	0x7f70a5fe,	0xf40a4735,
+	0x7f754e80,	0xf43c53cb,	0x7f79e35a,	0xf46e6231,	0x7f7e648c,	0xf4a07261,	0x7f82d214,	0xf4d28451,
+	0x7f872bf3,	0xf50497fb,	0x7f8b7227,	0xf536ad56,	0x7f8fa4b0,	0xf568c45b,	0x7f93c38c,	0xf59add02,
+	0x7f97cebd,	0xf5ccf743,	0x7f9bc640,	0xf5ff1318,	0x7f9faa15,	0xf6313077,	0x7fa37a3c,	0xf6634f59,
+	0x7fa736b4,	0xf6956fb7,	0x7faadf7c,	0xf6c79188,	0x7fae7495,	0xf6f9b4c6,	0x7fb1f5fc,	0xf72bd967,
+	0x7fb563b3,	0xf75dff66,	0x7fb8bdb8,	0xf79026b9,	0x7fbc040a,	0xf7c24f59,	0x7fbf36aa,	0xf7f4793e,
+	0x7fc25596,	0xf826a462,	0x7fc560cf,	0xf858d0bb,	0x7fc85854,	0xf88afe42,	0x7fcb3c23,	0xf8bd2cef,
+	0x7fce0c3e,	0xf8ef5cbb,	0x7fd0c8a3,	0xf9218d9e,	0x7fd37153,	0xf953bf91,	0x7fd6064c,	0xf985f28a,
+	0x7fd8878e,	0xf9b82684,	0x7fdaf519,	0xf9ea5b75,	0x7fdd4eec,	0xfa1c9157,	0x7fdf9508,	0xfa4ec821,
+	0x7fe1c76b,	0xfa80ffcb,	0x7fe3e616,	0xfab3384f,	0x7fe5f108,	0xfae571a4,	0x7fe7e841,	0xfb17abc2,
+	0x7fe9cbc0,	0xfb49e6a3,	0x7feb9b85,	0xfb7c223d,	0x7fed5791,	0xfbae5e89,	0x7feeffe1,	0xfbe09b80,
+	0x7ff09478,	0xfc12d91a,	0x7ff21553,	0xfc45174e,	0x7ff38274,	0xfc775616,	0x7ff4dbd9,	0xfca9956a,
+	0x7ff62182,	0xfcdbd541,	0x7ff75370,	0xfd0e1594,	0x7ff871a2,	0xfd40565c,	0x7ff97c18,	0xfd729790,
+	0x7ffa72d1,	0xfda4d929,	0x7ffb55ce,	0xfdd71b1e,	0x7ffc250f,	0xfe095d69,	0x7ffce093,	0xfe3ba002,
+	0x7ffd885a,	0xfe6de2e0,	0x7ffe1c65,	0xfea025fd,	0x7ffe9cb2,	0xfed2694f,	0x7fff0943,	0xff04acd0,
+	0x7fff6216,	0xff36f078,	0x7fffa72c,	0xff69343f,	0x7fffd886,	0xff9b781d,	0x7ffff621,	0xffcdbc0b
+
+};
+
+/**   
+*   
+* @brief  Initialization function for the Q31 CFFT/CIFFT.  
+* @param[in,out] *S             points to an instance of the Q31 CFFT/CIFFT structure.  
+* @param[in]     fftLen         length of the FFT.  
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.  
+*   
+* \par Description:  
+* \par   
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.   
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated  
+* \par   
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
+* \par   
+* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.   
+* \par   
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   
+*/
+
+arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (q31_t *) twiddleCoefQ31;
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of Instance structure depending on the FFT length */
+  switch (S->fftLen)
+  {
+
+  /*  Initializations of structure parameters for 4096 point FFT */
+  case 4096u:
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = armBitRevTable;
+    break;
+
+    /*  Initializations of structure parameters for 1024 point FFT */
+  case 1024u:
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 4u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 4u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+    break;
+
+  case 256u:
+    /*  Initializations of structure parameters for 256 point FFT */
+    S->twidCoefModifier = 16u;
+    S->bitRevFactor = 16u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+    break;
+
+  case 64u:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 64u;
+    S->bitRevFactor = 64u;
+    S->pBitRevTable = &armBitRevTable[63];
+    break;
+
+  case 16u:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 256u;
+    S->bitRevFactor = 256u;
+    S->pBitRevTable = &armBitRevTable[255];
+    break;
+
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**   
+ * @} end of CFFT_CIFFT group   
+ */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c
new file mode 100644
index 000000000..d855a10e0
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c
@@ -0,0 +1,1952 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix4_q15.c   
+*   
+* Description:	This file has function definition of Radix-4 FFT & IFFT function and   
+*				In-place bit reversal using bit reversal table   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup CFFT_CIFFT   
+ * @{   
+ */
+
+
+/**   
+ * @details   
+ * @brief Processing function for the Q15 CFFT/CIFFT.  
+ * @param[in]      *S    points to an instance of the Q15 CFFT/CIFFT structure.  
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.  
+ * @return none.  
+ *    
+ * \par Input and output formats:   
+ * \par   
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.  
+ * Hence the output format is different for different FFT sizes.   
+ * The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT:  
+ * \par  
+ * \image html CFFTQ15.gif "Input and Output Formats for Q15 CFFT"   
+ * \image html CIFFTQ15.gif "Input and Output Formats for Q15 CIFFT"   
+ */
+
+void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc)
+{
+  if(S->ifftFlag == 1u)
+  {
+    /*  Complex IFFT radix-4  */
+    arm_radix4_butterfly_inverse_q15(pSrc, S->fftLen, S->pTwiddle,
+                                     S->twidCoefModifier);
+  }
+  else
+  {
+    /*  Complex FFT radix-4  */
+    arm_radix4_butterfly_q15(pSrc, S->fftLen, S->pTwiddle,
+                             S->twidCoefModifier);
+  }
+
+  if(S->bitReverseFlag == 1u)
+  {
+    /*  Bit Reversal */
+    arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+  }
+
+}
+
+/**   
+ * @} end of CFFT_CIFFT group   
+ */
+
+/*   
+* Radix-4 FFT algorithm used is :   
+*   
+* Input real and imaginary data:   
+* x(n) = xa + j * ya   
+* x(n+N/4 ) = xb + j * yb   
+* x(n+N/2 ) = xc + j * yc   
+* x(n+3N 4) = xd + j * yd   
+*   
+*   
+* Output real and imaginary data:   
+* x(4r) = xa'+ j * ya'   
+* x(4r+1) = xb'+ j * yb'   
+* x(4r+2) = xc'+ j * yc'   
+* x(4r+3) = xd'+ j * yd'   
+*   
+*   
+* Twiddle factors for radix-4 FFT:   
+* Wn = co1 + j * (- si1)   
+* W2n = co2 + j * (- si2)   
+* W3n = co3 + j * (- si3)   
+   
+* The real and imaginary output values for the radix-4 butterfly are   
+* xa' = xa + xb + xc + xd   
+* ya' = ya + yb + yc + yd   
+* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)   
+* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)   
+* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)   
+* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)   
+* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)   
+* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)   
+*   
+*/
+
+/**   
+ * @brief  Core function for the Q15 CFFT butterfly process.  
+ * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.  
+ * @param[in]      fftLen           length of the FFT.  
+ * @param[in]      *pCoef16         points to twiddle coefficient buffer.  
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.  
+ */
+
+void arm_radix4_butterfly_q15(
+  q15_t * pSrc16,
+  uint32_t fftLen,
+  q15_t * pCoef16,
+  uint32_t twidCoefModifier)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t R, S, T, U;
+  q31_t C1, C2, C3, out1, out2;
+  q31_t *pSrc, *pCoeff;
+  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+  q15_t in;
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+  /*  pointer initializations for SIMD calculations */
+  pSrc = (q31_t *) pSrc16;
+  pCoeff = (q31_t *) pCoef16;
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+
+  /* Index for twiddle coefficient */
+  ic = 0u;
+
+  /* Index for input read and output write */
+  i0 = 0u;
+  j = n2;
+
+  /* Input is in 1.15(q15) format */
+
+  /*  start of first stage process */
+  do
+  {
+    /*  Butterfly implementation */
+
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T = pSrc[i0];
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+    /* Read yc (real), xc(imag) input */
+    S = pSrc[i2];
+    in = ((int16_t) (S & 0xFFFF)) >> 2;
+    S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+    /* R = packed((ya + yc), (xa + xc) ) */
+    R = __QADD16(T, S);
+    /* S = packed((ya - yc), (xa - xc) ) */
+    S = __QSUB16(T, S);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T = pSrc[i1];
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+    /* Read yd (real), xd(imag) input */
+    U = pSrc[i3];
+    in = ((int16_t) (U & 0xFFFF)) >> 2;
+    U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+    /* T = packed((yb + yd), (xb + xd) ) */
+    T = __QADD16(T, U);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc[i0] = __SHADD16(R, T);
+
+    /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */
+    R = __QSUB16(R, T);
+
+    /* co2 & si2 are read from SIMD Coefficient pointer */
+    C2 = pCoeff[2u * ic];
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+    out1 = __SMUAD(C2, R) >> 16u;
+    /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+    out2 = __SMUSDX(C2, R);
+
+#else
+
+    /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+    out1 = __SMUSDX(R, C2) >> 16u;
+    /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+    out2 = __SMUAD(C2, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /*  Reading i0+fftLen/4 */
+    /* T = packed(yb, xb) */
+    T = pSrc[i1];
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* writing the butterfly processed i0 + fftLen/4 sample */
+    /* writing output(xc', yc') in little endian format */
+    pSrc[i1] = (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+    /*  Butterfly calculations */
+    /* U = packed(yd, xd) */
+    U = pSrc[i3];
+    in = ((int16_t) (U & 0xFFFF)) >> 2;
+    U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+    /* T = packed(yb-yd, xb-xd) */
+    T = __QSUB16(T, U);
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+    R = __QASX(S, T);
+    /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+    S = __QSAX(S, T);
+
+#else
+
+    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+    R = __QSAX(S, T);
+    /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+    S = __QASX(S, T);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* co1 & si1 are read from SIMD Coefficient pointer */
+    C1 = pCoeff[ic];
+    /*  Butterfly process for the i0+fftLen/2 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+    out1 = __SMUAD(C1, S) >> 16u;
+    /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+    out2 = __SMUSDX(C1, S);
+
+#else
+
+    /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+    out1 = __SMUSDX(S, C1) >> 16u;
+    /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+    out2 = __SMUAD(C1, S);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* writing output(xb', yb') in little endian format */
+    pSrc[i2] = ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF);
+
+
+    /* co3 & si3 are read from SIMD Coefficient pointer */
+    C3 = pCoeff[3u * ic];
+    /*  Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+    out1 = __SMUAD(C3, R) >> 16u;
+    /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+    out2 = __SMUSDX(C3, R);
+
+#else
+
+    /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+    out1 = __SMUSDX(R, C3) >> 16u;
+    /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+    out2 = __SMUAD(C3, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* writing output(xd', yd') in little endian format */
+    pSrc[i3] = ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+    /*  Twiddle coefficients index modifier */
+    ic = ic + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+  /* data is in 4.11(q11) format */
+
+  /* end of first stage process */
+
+
+  /* start of middle stage process */
+
+  /*  Twiddle coefficients index modifier */
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of Middle stage */
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the middle stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ic = 0u;
+
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      C1 = pCoeff[ic];
+      C2 = pCoeff[2u * ic];
+      C3 = pCoeff[3u * ic];
+
+      /*  Twiddle coefficients index modifier */
+      ic = ic + twidCoefModifier;
+
+      /*  Butterfly implementation */
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Reading i0, i0+fftLen/2 inputs */
+        /* Read ya (real), xa(imag) input */
+        T = pSrc[i0];
+
+        /* Read yc (real), xc(imag) input */
+        S = pSrc[i2];
+
+        /* R = packed( (ya + yc), (xa + xc)) */
+        R = __QADD16(T, S);
+
+        /* S = packed((ya - yc), (xa - xc)) */
+        S = __QSUB16(T, S);
+
+        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+        /* Read yb (real), xb(imag) input */
+        T = pSrc[i1];
+
+        /* Read yd (real), xd(imag) input */
+        U = pSrc[i3];
+
+
+        /* T = packed( (yb + yd), (xb + xd)) */
+        T = __QADD16(T, U);
+
+
+        /*  writing the butterfly processed i0 sample */
+
+        /* xa' = xa + xb + xc + xd */
+        /* ya' = ya + yb + yc + yd */
+        out1 = __SHADD16(R, T);
+        in = ((int16_t) (out1 & 0xFFFF)) >> 1;
+        out1 = ((out1 >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+        pSrc[i0] = out1;
+
+        /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
+        R = __SHSUB16(R, T);
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+        out1 = __SMUAD(C2, R) >> 16u;
+
+        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        out2 = __SMUSDX(C2, R);
+
+#else
+
+        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        out1 = __SMUSDX(R, C2) >> 16u;
+
+        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+        out2 = __SMUAD(C2, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /*  Reading i0+3fftLen/4 */
+        /* Read yb (real), xb(imag) input */
+        T = pSrc[i1];
+
+        /*  writing the butterfly processed i0 + fftLen/4 sample */
+        /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+        /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        pSrc[i1] = ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+        /*  Butterfly calculations */
+
+        /* Read yd (real), xd(imag) input */
+        U = pSrc[i3];
+
+        /* T = packed(yb-yd, xb-xd) */
+        T = __QSUB16(T, U);
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+        R = __SHASX(S, T);
+
+        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+        S = __SHSAX(S, T);
+
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = __SMUAD(C1, S) >> 16u;
+        out2 = __SMUSDX(C1, S);
+
+#else
+
+        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+        R = __SHSAX(S, T);
+
+        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+        S = __SHASX(S, T);
+
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = __SMUSDX(S, C1) >> 16u;
+        out2 = __SMUAD(C1, S);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+        /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+        pSrc[i2] = ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+        /*  Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUAD(C3, R) >> 16u;
+        out2 = __SMUSDX(C3, R);
+
+#else
+
+        out1 = __SMUSDX(R, C3) >> 16u;
+        out2 = __SMUAD(C3, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+        /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+        pSrc[i3] = ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+      }
+    }
+    /*  Twiddle coefficients index modifier */
+    twidCoefModifier <<= 2u;
+  }
+  /* end of middle stage process */
+
+
+  /* data is in 10.6(q6) format for the 1024 point */
+  /* data is in 8.8(q8) format for the 256 point */
+  /* data is in 6.10(q10) format for the 64 point */
+  /* data is in 4.12(q12) format for the 16 point */
+
+  /*  Initializations for the last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /* start of last stage process */
+
+  /*  Butterfly implementation */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T = pSrc[i0];
+    /* Read yc (real), xc(imag) input */
+    S = pSrc[i2];
+
+    /* R = packed((ya + yc), (xa + xc)) */
+    R = __QADD16(T, S);
+    /* S = packed((ya - yc), (xa - xc)) */
+    S = __QSUB16(T, S);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T = pSrc[i1];
+    /* Read yd (real), xd(imag) input */
+    U = pSrc[i3];
+
+    /* T = packed((yb + yd), (xb + xd)) */
+    T = __QADD16(T, U);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc[i0] = __SHADD16(R, T);
+
+    /* R = packed((ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
+    R = __SHSUB16(R, T);
+
+    /* Read yb (real), xb(imag) input */
+    T = pSrc[i1];
+
+    /*  writing the butterfly processed i0 + fftLen/4 sample */
+    /* xc' = (xa-xb+xc-xd) */
+    /* yc' = (ya-yb+yc-yd) */
+    pSrc[i1] = R;
+
+    /* Read yd (real), xd(imag) input */
+    U = pSrc[i3];
+    /* T = packed( (yb - yd), (xb - xd))  */
+    T = __QSUB16(T, U);
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /*  writing the butterfly processed i0 + fftLen/2 sample */
+    /* xb' = (xa+yb-xc-yd) */
+    /* yb' = (ya-xb-yc+xd) */
+    pSrc[i2] = __SHSAX(S, T);
+
+    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
+    /* xd' = (xa-yb-xc+yd) */
+    /* yd' = (ya+xb-yc-xd) */
+    pSrc[i3] = __SHASX(S, T);
+
+#else
+
+    /*  writing the butterfly processed i0 + fftLen/2 sample */
+    /* xb' = (xa+yb-xc-yd) */
+    /* yb' = (ya-xb-yc+xd) */
+    pSrc[i2] = __SHASX(S, T);
+
+    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
+    /* xd' = (xa-yb-xc+yd) */
+    /* yd' = (ya+xb-yc-xd) */
+    pSrc[i3] = __SHSAX(S, T);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+  }
+
+  /* end of last stage process */
+
+  /* output is in 11.5(q5) format for the 1024 point */
+  /* output is in 9.7(q7) format for the 256 point   */
+  /* output is in 7.9(q9) format for the 64 point  */
+  /* output is in 5.11(q11) format for the 16 point  */
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t R0, R1, S0, S1, T0, T1, U0, U1;
+  q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2;
+  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+
+  /* Index for twiddle coefficient */
+  ic = 0u;
+
+  /* Index for input read and output write */
+  i0 = 0u;
+  j = n2;
+
+  /* Input is in 1.15(q15) format */
+
+  /*  start of first stage process */
+  do
+  {
+    /*  Butterfly implementation */
+
+    /*  index calculation for the input as, */
+    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+
+    /* input is down scale by 4 to avoid overflow */
+    /* Read ya (real), xa(imag) input */
+    T0 = pSrc16[i0 * 2u] >> 2u;
+    T1 = pSrc16[(i0 * 2u) + 1u] >> 2u;
+
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yc (real), xc(imag) input */
+    S0 = pSrc16[i2 * 2u] >> 2u;
+    S1 = pSrc16[(i2 * 2u) + 1u] >> 2u;
+
+    /* R0 = (ya + yc) */
+    R0 = __SSAT(T0 + S0, 16u);
+    /* R1 = (xa + xc) */
+    R1 = __SSAT(T1 + S1, 16u);
+
+    /* S0 = (ya - yc) */
+    S0 = __SSAT(T0 - S0, 16);
+    /* S1 = (xa - xc) */
+    S1 = __SSAT(T1 - S1, 16);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u] >> 2u;
+    T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
+
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2u] >> 2u;
+    U1 = pSrc16[(i3 * 2u) + 1] >> 2u;
+
+    /* T0 = (yb + yd) */
+    T0 = __SSAT(T0 + U0, 16u);
+    /* T1 = (xb + xd) */
+    T1 = __SSAT(T1 + U1, 16u);
+
+    /*  writing the butterfly processed i0 sample */
+    /* ya' = ya + yb + yc + yd */
+    /* xa' = xa + xb + xc + xd */
+    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+    /* R0 = (ya + yc) - (yb + yd) */
+    /* R1 = (xa + xc) - (xb + xd) */
+    R0 = __SSAT(R0 - T0, 16u);
+    R1 = __SSAT(R1 - T1, 16u);
+
+    /* co2 & si2 are read from Coefficient pointer */
+    Co2 = pCoef16[2u * ic * 2u];
+    Si2 = pCoef16[(2u * ic * 2u) + 1];
+
+    /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+    out1 = (short) ((Co2 * R0 + Si2 * R1) >> 16u);
+    /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+    out2 = (short) ((-Si2 * R0 + Co2 * R1) >> 16u);
+
+    /*  Reading i0+fftLen/4 */
+    /* input is down scale by 4 to avoid overflow */
+    /* T0 = yb, T1 =  xb */
+    T0 = pSrc16[i1 * 2u] >> 2;
+    T1 = pSrc16[(i1 * 2u) + 1] >> 2;
+
+    /* writing the butterfly processed i0 + fftLen/4 sample */
+    /* writing output(xc', yc') in little endian format */
+    pSrc16[i1 * 2u] = out1;
+    pSrc16[(i1 * 2u) + 1] = out2;
+
+    /*  Butterfly calculations */
+    /* input is down scale by 4 to avoid overflow */
+    /* U0 = yd, U1 = xd */
+    U0 = pSrc16[i3 * 2u] >> 2;
+    U1 = pSrc16[(i3 * 2u) + 1] >> 2;
+    /* T0 = yb-yd */
+    T0 = __SSAT(T0 - U0, 16);
+    /* T1 = xb-xd */
+    T1 = __SSAT(T1 - U1, 16);
+
+    /* R1 = (ya-yc) + (xb- xd),  R0 = (xa-xc) - (yb-yd)) */
+    R0 = (short) __SSAT((q31_t) (S0 - T1), 16);
+    R1 = (short) __SSAT((q31_t) (S1 + T0), 16);
+
+    /* S1 = (ya-yc) - (xb- xd), S0 = (xa-xc) + (yb-yd)) */
+    S0 = (short) __SSAT(((q31_t) S0 + T1), 16u);
+    S1 = (short) __SSAT(((q31_t) S1 - T0), 16u);
+
+    /* co1 & si1 are read from Coefficient pointer */
+    Co1 = pCoef16[ic * 2u];
+    Si1 = pCoef16[(ic * 2u) + 1];
+    /*  Butterfly process for the i0+fftLen/2 sample */
+    /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+    out1 = (short) ((Si1 * S1 + Co1 * S0) >> 16);
+    /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+    out2 = (short) ((-Si1 * S0 + Co1 * S1) >> 16);
+
+    /* writing output(xb', yb') in little endian format */
+    pSrc16[i2 * 2u] = out1;
+    pSrc16[(i2 * 2u) + 1] = out2;
+
+    /* Co3 & si3 are read from Coefficient pointer */
+    Co3 = pCoef16[3u * (ic * 2u)];
+    Si3 = pCoef16[(3u * (ic * 2u)) + 1];
+    /*  Butterfly process for the i0+3fftLen/4 sample */
+    /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */
+    out1 = (short) ((Si3 * R1 + Co3 * R0) >> 16u);
+    /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */
+    out2 = (short) ((-Si3 * R0 + Co3 * R1) >> 16u);
+    /* writing output(xd', yd') in little endian format */
+    pSrc16[i3 * 2u] = out1;
+    pSrc16[(i3 * 2u) + 1] = out2;
+
+    /*  Twiddle coefficients index modifier */
+    ic = ic + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+  /* data is in 4.11(q11) format */
+
+  /* end of first stage process */
+
+
+  /* start of middle stage process */
+
+  /*  Twiddle coefficients index modifier */
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of Middle stage */
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the middle stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ic = 0u;
+
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      Co1 = pCoef16[ic * 2u];
+      Si1 = pCoef16[(ic * 2u) + 1u];
+      Co2 = pCoef16[2u * (ic * 2u)];
+      Si2 = pCoef16[(2u * (ic * 2u)) + 1u];
+      Co3 = pCoef16[3u * (ic * 2u)];
+      Si3 = pCoef16[(3u * (ic * 2u)) + 1u];
+
+      /*  Twiddle coefficients index modifier */
+      ic = ic + twidCoefModifier;
+
+      /*  Butterfly implementation */
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Reading i0, i0+fftLen/2 inputs */
+        /* Read ya (real), xa(imag) input */
+        T0 = pSrc16[i0 * 2u];
+        T1 = pSrc16[(i0 * 2u) + 1u];
+
+        /* Read yc (real), xc(imag) input */
+        S0 = pSrc16[i2 * 2u];
+        S1 = pSrc16[(i2 * 2u) + 1u];
+
+        /* R0 = (ya + yc), R1 = (xa + xc) */
+        R0 = __SSAT(T0 + S0, 16);
+        R1 = __SSAT(T1 + S1, 16);
+
+        /* S0 = (ya - yc), S1 =(xa - xc) */
+        S0 = __SSAT(T0 - S0, 16);
+        S1 = __SSAT(T1 - S1, 16);
+
+        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+        /* Read yb (real), xb(imag) input */
+        T0 = pSrc16[i1 * 2u];
+        T1 = pSrc16[(i1 * 2u) + 1u];
+
+        /* Read yd (real), xd(imag) input */
+        U0 = pSrc16[i3 * 2u];
+        U1 = pSrc16[(i3 * 2u) + 1u];
+
+
+        /* T0 = (yb + yd), T1 = (xb + xd) */
+        T0 = __SSAT(T0 + U0, 16);
+        T1 = __SSAT(T1 + U1, 16);
+
+        /*  writing the butterfly processed i0 sample */
+
+        /* xa' = xa + xb + xc + xd */
+        /* ya' = ya + yb + yc + yd */
+        out1 = ((R0 >> 1u) + (T0 >> 1u)) >> 1u;
+        out2 = ((R1 >> 1u) + (T1 >> 1u)) >> 1u;
+
+        pSrc16[i0 * 2u] = out1;
+        pSrc16[(2u * i0) + 1u] = out2;
+
+        /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+        R0 = (R0 >> 1u) - (T0 >> 1u);
+        R1 = (R1 >> 1u) - (T1 >> 1u);
+
+        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+        out1 = (short) ((Co2 * R0 + Si2 * R1) >> 16u);
+
+        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        out2 = (short) ((-Si2 * R0 + Co2 * R1) >> 16u);
+
+        /*  Reading i0+3fftLen/4 */
+        /* Read yb (real), xb(imag) input */
+        T0 = pSrc16[i1 * 2u];
+        T1 = pSrc16[(i1 * 2u) + 1u];
+
+        /*  writing the butterfly processed i0 + fftLen/4 sample */
+        /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+        /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        pSrc16[i1 * 2u] = out1;
+        pSrc16[(i1 * 2u) + 1u] = out2;
+
+        /*  Butterfly calculations */
+
+        /* Read yd (real), xd(imag) input */
+        U0 = pSrc16[i3 * 2u];
+        U1 = pSrc16[(i3 * 2u) + 1u];
+
+        /* T0 = yb-yd, T1 = xb-xd */
+        T0 = __SSAT(T0 - U0, 16);
+        T1 = __SSAT(T1 - U1, 16);
+
+        /* R0 = (ya-yc) + (xb- xd), R1 = (xa-xc) - (yb-yd)) */
+        R0 = (S0 >> 1u) - (T1 >> 1u);
+        R1 = (S1 >> 1u) + (T0 >> 1u);
+
+        /* S0 = (ya-yc) - (xb- xd), S1 = (xa-xc) + (yb-yd)) */
+        S0 = (S0 >> 1u) + (T1 >> 1u);
+        S1 = (S1 >> 1u) - (T0 >> 1u);
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = (short) ((Co1 * S0 + Si1 * S1) >> 16u);
+
+        out2 = (short) ((-Si1 * S0 + Co1 * S1) >> 16u);
+
+        /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+        /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+        pSrc16[i2 * 2u] = out1;
+        pSrc16[(i2 * 2u) + 1u] = out2;
+
+        /*  Butterfly process for the i0+3fftLen/4 sample */
+        out1 = (short) ((Si3 * R1 + Co3 * R0) >> 16u);
+
+        out2 = (short) ((-Si3 * R0 + Co3 * R1) >> 16u);
+        /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */
+        /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */
+        pSrc16[i3 * 2u] = out1;
+        pSrc16[(i3 * 2u) + 1u] = out2;
+      }
+    }
+    /*  Twiddle coefficients index modifier */
+    twidCoefModifier <<= 2u;
+  }
+  /* end of middle stage process */
+
+
+  /* data is in 10.6(q6) format for the 1024 point */
+  /* data is in 8.8(q8) format for the 256 point */
+  /* data is in 6.10(q10) format for the 64 point */
+  /* data is in 4.12(q12) format for the 16 point */
+
+  /*  Initializations for the last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /* start of last stage process */
+
+  /*  Butterfly implementation */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T0 = pSrc16[i0 * 2u];
+    T1 = pSrc16[(i0 * 2u) + 1u];
+
+    /* Read yc (real), xc(imag) input */
+    S0 = pSrc16[i2 * 2u];
+    S1 = pSrc16[(i2 * 2u) + 1u];
+
+    /* R0 = (ya + yc), R1 = (xa + xc) */
+    R0 = __SSAT(T0 + S0, 16u);
+    R1 = __SSAT(T1 + S1, 16u);
+
+    /* S0 = (ya - yc), S1 = (xa - xc) */
+    S0 = __SSAT(T0 - S0, 16u);
+    S1 = __SSAT(T1 - S1, 16u);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u];
+    T1 = pSrc16[(i1 * 2u) + 1u];
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2u];
+    U1 = pSrc16[(i3 * 2u) + 1u];
+
+    /* T0 = (yb + yd), T1 = (xb + xd)) */
+    T0 = __SSAT(T0 + U0, 16u);
+    T1 = __SSAT(T1 + U1, 16u);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+    R0 = (R0 >> 1u) - (T0 >> 1u);
+    R1 = (R1 >> 1u) - (T1 >> 1u);
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u];
+    T1 = pSrc16[(i1 * 2u) + 1u];
+
+    /*  writing the butterfly processed i0 + fftLen/4 sample */
+    /* xc' = (xa-xb+xc-xd) */
+    /* yc' = (ya-yb+yc-yd) */
+    pSrc16[i1 * 2u] = R0;
+    pSrc16[(i1 * 2u) + 1u] = R1;
+
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2u];
+    U1 = pSrc16[(i3 * 2u) + 1u];
+    /* T0 = (yb - yd), T1 = (xb - xd)  */
+    T0 = __SSAT(T0 - U0, 16u);
+    T1 = __SSAT(T1 - U1, 16u);
+
+    /*  writing the butterfly processed i0 + fftLen/2 sample */
+    /* xb' = (xa+yb-xc-yd) */
+    /* yb' = (ya-xb-yc+xd) */
+    pSrc16[i2 * 2u] = (S0 >> 1u) + (T1 >> 1u);
+    pSrc16[(i2 * 2u) + 1u] = (S1 >> 1u) - (T0 >> 1u);
+
+    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
+    /* xd' = (xa-yb-xc+yd) */
+    /* yd' = (ya+xb-yc-xd) */
+    pSrc16[i3 * 2u] = (S0 >> 1u) - (T1 >> 1u);
+    pSrc16[(i3 * 2u) + 1u] = (S1 >> 1u) + (T0 >> 1u);
+
+  }
+
+  /* end of last stage process */
+
+  /* output is in 11.5(q5) format for the 1024 point */
+  /* output is in 9.7(q7) format for the 256 point   */
+  /* output is in 7.9(q9) format for the 64 point  */
+  /* output is in 5.11(q11) format for the 16 point  */
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+
+/**   
+ * @brief  Core function for the Q15 CIFFT butterfly process.  
+ * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.  
+ * @param[in]      fftLen           length of the FFT.  
+ * @param[in]      *pCoef16         points to twiddle coefficient buffer.  
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.  
+ */
+
+/*   
+* Radix-4 IFFT algorithm used is :   
+*   
+* CIFFT uses same twiddle coefficients as CFFT function   
+*  x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4]   
+*   
+*   
+* IFFT is implemented with following changes in equations from FFT   
+*   
+* Input real and imaginary data:   
+* x(n) = xa + j * ya   
+* x(n+N/4 ) = xb + j * yb   
+* x(n+N/2 ) = xc + j * yc   
+* x(n+3N 4) = xd + j * yd   
+*   
+*   
+* Output real and imaginary data:   
+* x(4r) = xa'+ j * ya'   
+* x(4r+1) = xb'+ j * yb'   
+* x(4r+2) = xc'+ j * yc'   
+* x(4r+3) = xd'+ j * yd'   
+*   
+*   
+* Twiddle factors for radix-4 IFFT:   
+* Wn = co1 + j * (si1)   
+* W2n = co2 + j * (si2)   
+* W3n = co3 + j * (si3)   
+   
+* The real and imaginary output values for the radix-4 butterfly are   
+* xa' = xa + xb + xc + xd   
+* ya' = ya + yb + yc + yd   
+* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)   
+* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)   
+* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)   
+* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)   
+* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)   
+* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)   
+*   
+*/
+
+void arm_radix4_butterfly_inverse_q15(
+  q15_t * pSrc16,
+  uint32_t fftLen,
+  q15_t * pCoef16,
+  uint32_t twidCoefModifier)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t R, S, T, U;
+  q31_t C1, C2, C3, out1, out2;
+  q31_t *pSrc, *pCoeff;
+  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+  q15_t in;
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+  /*  pointer initializations for SIMD calculations */
+  pSrc = (q31_t *) pSrc16;
+  pCoeff = (q31_t *) pCoef16;
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+
+  /* Index for twiddle coefficient */
+  ic = 0u;
+
+  /* Index for input read and output write */
+  i0 = 0u;
+
+  j = n2;
+
+  /* Input is in 1.15(q15) format */
+
+  /*  Start of first stage process */
+  do
+  {
+    /*  Butterfly implementation */
+
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T = pSrc[i0];
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+    /* Read yc (real), xc(imag) input */
+    S = pSrc[i2];
+    in = ((int16_t) (S & 0xFFFF)) >> 2;
+    S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* R = packed((ya + yc), (xa + xc) ) */
+    R = __QADD16(T, S);
+    /* S = packed((ya - yc), (xa - xc) ) */
+    S = __QSUB16(T, S);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T = pSrc[i1];
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+    /* Read yd (real), xd(imag) input */
+    U = pSrc[i3];
+    in = ((int16_t) (U & 0xFFFF)) >> 2;
+    U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* T = packed((yb + yd), (xb + xd) ) */
+    T = __QADD16(T, U);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc[i0] = __SHADD16(R, T);
+
+    /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */
+    R = __QSUB16(R, T);
+    /* co2 & si2 are read from SIMD Coefficient pointer */
+    C2 = pCoeff[2u * ic];
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+    out1 = __SMUSD(C2, R) >> 16u;
+    /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+    out2 = __SMUADX(C2, R);
+
+#else
+
+    /* xc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+    out1 = __SMUADX(C2, R) >> 16u;
+    /* yc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+    out2 = __SMUSD(-C2, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /*  Reading i0+fftLen/4 */
+    /* T = packed(yb, xb) */
+    T = pSrc[i1];
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* writing the butterfly processed i0 + fftLen/4 sample */
+    /* writing output(xc', yc') in little endian format */
+    pSrc[i1] = (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+    /*  Butterfly calculations */
+    /* U = packed(yd, xd) */
+    U = pSrc[i3];
+    in = ((int16_t) (U & 0xFFFF)) >> 2;
+    U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* T = packed(yb-yd, xb-xd) */
+    T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* R = packed((ya-yc) - (xb- xd) , (xa-xc) + (yb-yd)) */
+    R = __QSAX(S, T);
+    /* S = packed((ya-yc) + (xb- xd),  (xa-xc) - (yb-yd)) */
+    S = __QASX(S, T);
+
+#else
+
+    /* R = packed((ya-yc) - (xb- xd) , (xa-xc) + (yb-yd)) */
+    R = __QASX(S, T);
+    /* S = packed((ya-yc) + (xb- xd),  (xa-xc) - (yb-yd)) */
+    S = __QSAX(S, T);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* co1 & si1 are read from SIMD Coefficient pointer */
+    C1 = pCoeff[ic];
+    /*  Butterfly process for the i0+fftLen/2 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+    out1 = __SMUSD(C1, S) >> 16u;
+    /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+    out2 = __SMUADX(C1, S);
+
+#else
+
+    /* xb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+    out1 = __SMUADX(C1, S) >> 16u;
+    /* yb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+    out2 = __SMUSD(-C1, S);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* writing output(xb', yb') in little endian format */
+    pSrc[i2] = ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF);
+
+    /* co3 & si3 are read from SIMD Coefficient pointer */
+    C3 = pCoeff[3u * ic];
+    /*  Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3) */
+    out1 = __SMUSD(C3, R) >> 16u;
+    /* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3) */
+    out2 = __SMUADX(C3, R);
+
+#else
+
+    /* xd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3) */
+    out1 = __SMUADX(C3, R) >> 16u;
+    /* yd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3) */
+    out2 = __SMUSD(-C3, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* writing output(xd', yd') in little endian format */
+    pSrc[i3] = ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+    /*  Twiddle coefficients index modifier */
+    ic = ic + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+
+  /*  End of first stage process */
+
+  /* data is in 4.11(q11) format */
+
+
+  /*  Start of Middle stage process */
+
+  /*  Twiddle coefficients index modifier */
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of Middle stage */
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the middle stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ic = 0u;
+
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      C1 = pCoeff[ic];
+      C2 = pCoeff[2u * ic];
+      C3 = pCoeff[3u * ic];
+
+      /*  Twiddle coefficients index modifier */
+      ic = ic + twidCoefModifier;
+
+      /*  Butterfly implementation */
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Reading i0, i0+fftLen/2 inputs */
+        /* Read ya (real), xa(imag) input */
+        T = pSrc[i0];
+
+        /* Read yc (real), xc(imag) input */
+        S = pSrc[i2];
+
+
+        /* R = packed( (ya + yc), (xa + xc)) */
+        R = __QADD16(T, S);
+        /* S = packed((ya - yc), (xa - xc)) */
+        S = __QSUB16(T, S);
+
+        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+        /* Read yb (real), xb(imag) input */
+        T = pSrc[i1];
+
+        /* Read yd (real), xd(imag) input */
+        U = pSrc[i3];
+
+
+        /* T = packed( (yb + yd), (xb + xd)) */
+        T = __QADD16(T, U);
+
+        /*  writing the butterfly processed i0 sample */
+        /* xa' = xa + xb + xc + xd */
+        /* ya' = ya + yb + yc + yd */
+        out1 = __SHADD16(R, T);
+        in = ((int16_t) (out1 & 0xFFFF)) >> 1;
+        out1 = ((out1 >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+        pSrc[i0] = out1;
+
+
+
+        /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
+        R = __SHSUB16(R, T);
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* (ya-yb+yc-yd)* (si2) - (xa-xb+xc-xd)* co2 */
+        out1 = __SMUSD(C2, R) >> 16u;
+        /* (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+        out2 = __SMUADX(C2, R);
+
+#else
+
+        /* (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+        out1 = __SMUADX(R, C2) >> 16u;
+        /* (ya-yb+yc-yd)* (si2) - (xa-xb+xc-xd)* co2 */
+        out2 = __SMUSD(-C2, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /*  Reading i0+3fftLen/4 */
+        /* Read yb (real), xb(imag) input */
+        T = pSrc[i1];
+
+        /*  writing the butterfly processed i0 + fftLen/4 sample */
+        /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+        /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+        pSrc[i1] = ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+        /*  Butterfly calculations */
+        /* Read yd (real), xd(imag) input */
+        U = pSrc[i3];
+
+        /* T = packed(yb-yd, xb-xd) */
+        T = __QSUB16(T, U);
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* R = packed((ya-yc) - (xb- xd) , (xa-xc) + (yb-yd)) */
+        R = __SHSAX(S, T);
+
+        /* S = packed((ya-yc) + (xb- xd),  (xa-xc) - (yb-yd)) */
+        S = __SHASX(S, T);
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = __SMUSD(C1, S) >> 16u;
+        out2 = __SMUADX(C1, S);
+
+#else
+
+        /* R = packed((ya-yc) - (xb- xd) , (xa-xc) + (yb-yd)) */
+        R = __SHASX(S, T);
+
+        /* S = packed((ya-yc) + (xb- xd),  (xa-xc) - (yb-yd)) */
+        S = __SHSAX(S, T);
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = __SMUADX(S, C1) >> 16u;
+        out2 = __SMUSD(-C1, S);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+        /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+        pSrc[i2] = ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+        /*  Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUSD(C3, R) >> 16u;
+        out2 = __SMUADX(C3, R);
+
+#else
+
+        out1 = __SMUADX(C3, R) >> 16u;
+        out2 = __SMUSD(-C3, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3) */
+        /* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3) */
+        pSrc[i3] = ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+
+      }
+    }
+    /*  Twiddle coefficients index modifier */
+    twidCoefModifier <<= 2u;
+  }
+  /*  End of Middle stages process */
+
+
+  /* data is in 10.6(q6) format for the 1024 point */
+  /* data is in 8.8(q8) format for the 256 point   */
+  /* data is in 6.10(q10) format for the 64 point  */
+  /* data is in 4.12(q12) format for the 16 point  */
+
+  /* start of last stage process */
+
+
+  /*  Initializations for the last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /*  Butterfly implementation */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T = pSrc[i0];
+    /* Read yc (real), xc(imag) input */
+    S = pSrc[i2];
+
+    /* R = packed((ya + yc), (xa + xc)) */
+    R = __QADD16(T, S);
+    /* S = packed((ya - yc), (xa - xc)) */
+    S = __QSUB16(T, S);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T = pSrc[i1];
+    /* Read yd (real), xd(imag) input */
+    U = pSrc[i3];
+
+    /* T = packed((yb + yd), (xb + xd)) */
+    T = __QADD16(T, U);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc[i0] = __SHADD16(R, T);
+
+    /* R = packed((ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
+    R = __SHSUB16(R, T);
+
+    /* Read yb (real), xb(imag) input */
+    T = pSrc[i1];
+
+    /*  writing the butterfly processed i0 + fftLen/4 sample */
+    /* xc' = (xa-xb+xc-xd) */
+    /* yc' = (ya-yb+yc-yd) */
+    pSrc[i1] = R;
+
+    /* Read yd (real), xd(imag) input */
+    U = pSrc[i3];
+    /* T = packed( (yb - yd), (xb - xd))  */
+    T = __QSUB16(T, U);
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /*  writing the butterfly processed i0 + fftLen/2 sample */
+    /* xb' = (xa-yb-xc+yd) */
+    /* yb' = (ya+xb-yc-xd) */
+    pSrc[i2] = __SHASX(S, T);
+
+    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
+    /* xd' = (xa+yb-xc-yd) */
+    /* yd' = (ya-xb-yc+xd) */
+    pSrc[i3] = __SHSAX(S, T);
+
+
+#else
+
+    /*  writing the butterfly processed i0 + fftLen/2 sample */
+    /* xb' = (xa-yb-xc+yd) */
+    /* yb' = (ya+xb-yc-xd) */
+    pSrc[i2] = __SHSAX(S, T);
+
+    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
+    /* xd' = (xa+yb-xc-yd) */
+    /* yd' = (ya-xb-yc+xd) */
+    pSrc[i3] = __SHASX(S, T);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+  }
+  /* end of last stage  process */
+
+  /* output is in 11.5(q5) format for the 1024 point */
+  /* output is in 9.7(q7) format for the 256 point   */
+  /* output is in 7.9(q9) format for the 64 point  */
+  /* output is in 5.11(q11) format for the 16 point  */
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t R0, R1, S0, S1, T0, T1, U0, U1;
+  q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2;
+  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+
+  /* Index for twiddle coefficient */
+  ic = 0u;
+
+  /* Index for input read and output write */
+  i0 = 0u;
+
+  j = n2;
+
+  /* Input is in 1.15(q15) format */
+
+  /*  Start of first stage process */
+  do
+  {
+    /*  Butterfly implementation */
+
+    /*  index calculation for the input as, */
+    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* input is down scale by 4 to avoid overflow */
+    /* Read ya (real), xa(imag) input */
+    T0 = pSrc16[i0 * 2u] >> 2u;
+    T1 = pSrc16[(i0 * 2u) + 1u] >> 2u;
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yc (real), xc(imag) input */
+    S0 = pSrc16[i2 * 2u] >> 2u;
+    S1 = pSrc16[(i2 * 2u) + 1u] >> 2u;
+
+    /* R0 = (ya + yc), R1 = (xa + xc) */
+    R0 = __SSAT(T0 + S0, 16u);
+    R1 = __SSAT(T1 + S1, 16u);
+    /* S0 = (ya - yc), S1 = (xa - xc) */
+    S0 = __SSAT(T0 - S0, 16u);
+    S1 = __SSAT(T1 - S1, 16u);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u] >> 2u;
+    T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
+    /* Read yd (real), xd(imag) input */
+    /* input is down scale by 4 to avoid overflow */
+    U0 = pSrc16[i3 * 2u] >> 2u;
+    U1 = pSrc16[(i3 * 2u) + 1u] >> 2u;
+
+    /* T0 = (yb + yd), T1 = (xb + xd) */
+    T0 = __SSAT(T0 + U0, 16u);
+    T1 = __SSAT(T1 + U1, 16u);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc)- (xb + xd) */
+    R0 = __SSAT(R0 - T0, 16u);
+    R1 = __SSAT(R1 - T1, 16u);
+    /* co2 & si2 are read from Coefficient pointer */
+    Co2 = pCoef16[2u * ic * 2u];
+    Si2 = pCoef16[(2u * ic * 2u) + 1u];
+    /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+    out1 = (short) ((Co2 * R0 - Si2 * R1) >> 16u);
+    /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+    out2 = (short) ((Si2 * R0 + Co2 * R1) >> 16u);
+
+    /*  Reading i0+fftLen/4 */
+    /* input is down scale by 4 to avoid overflow */
+    /* T0 = yb, T1 = xb */
+    T0 = pSrc16[i1 * 2u] >> 2u;
+    T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
+
+    /* writing the butterfly processed i0 + fftLen/4 sample */
+    /* writing output(xc', yc') in little endian format */
+    pSrc16[i1 * 2u] = out1;
+    pSrc16[(i1 * 2u) + 1u] = out2;
+
+    /*  Butterfly calculations */
+    /* input is down scale by 4 to avoid overflow */
+    /* U0 = yd, U1 = xd) */
+    U0 = pSrc16[i3 * 2u] >> 2u;
+    U1 = pSrc16[(i3 * 2u) + 1u] >> 2u;
+
+    /* T0 = yb-yd, T1 = xb-xd) */
+    T0 = __SSAT(T0 - U0, 16u);
+    T1 = __SSAT(T1 - U1, 16u);
+    /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */
+    R0 = (short) __SSAT((q31_t) (S0 + T1), 16);
+    R1 = (short) __SSAT((q31_t) (S1 - T0), 16);
+    /* S = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */
+    S0 = (short) __SSAT((q31_t) (S0 - T1), 16);
+    S1 = (short) __SSAT((q31_t) (S1 + T0), 16);
+
+    /* co1 & si1 are read from Coefficient pointer */
+    Co1 = pCoef16[ic * 2u];
+    Si1 = pCoef16[(ic * 2u) + 1u];
+    /*  Butterfly process for the i0+fftLen/2 sample */
+    /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+    out1 = (short) ((Co1 * S0 - Si1 * S1) >> 16u);
+    /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+    out2 = (short) ((Si1 * S0 + Co1 * S1) >> 16u);
+    /* writing output(xb', yb') in little endian format */
+    pSrc16[i2 * 2u] = out1;
+    pSrc16[(i2 * 2u) + 1u] = out2;
+
+    /* Co3 & si3 are read from Coefficient pointer */
+    Co3 = pCoef16[3u * ic * 2u];
+    Si3 = pCoef16[(3u * ic * 2u) + 1u];
+    /*  Butterfly process for the i0+3fftLen/4 sample */
+    /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */
+    out1 = (short) ((Co3 * R0 - Si3 * R1) >> 16u);
+    /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */
+    out2 = (short) ((Si3 * R0 + Co3 * R1) >> 16u);
+    /* writing output(xd', yd') in little endian format */
+    pSrc16[i3 * 2u] = out1;
+    pSrc16[(i3 * 2u) + 1u] = out2;
+
+    /*  Twiddle coefficients index modifier */
+    ic = ic + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+
+  /*  End of first stage process */
+
+  /* data is in 4.11(q11) format */
+
+
+  /*  Start of Middle stage process */
+
+  /*  Twiddle coefficients index modifier */
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of Middle stage */
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the middle stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ic = 0u;
+
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      Co1 = pCoef16[ic * 2u];
+      Si1 = pCoef16[(ic * 2u) + 1u];
+      Co2 = pCoef16[2u * ic * 2u];
+      Si2 = pCoef16[2u * ic * 2u + 1u];
+      Co3 = pCoef16[3u * ic * 2u];
+      Si3 = pCoef16[(3u * ic * 2u) + 1u];
+
+      /*  Twiddle coefficients index modifier */
+      ic = ic + twidCoefModifier;
+
+      /*  Butterfly implementation */
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Reading i0, i0+fftLen/2 inputs */
+        /* Read ya (real), xa(imag) input */
+        T0 = pSrc16[i0 * 2u];
+        T1 = pSrc16[(i0 * 2u) + 1u];
+
+        /* Read yc (real), xc(imag) input */
+        S0 = pSrc16[i2 * 2u];
+        S1 = pSrc16[(i2 * 2u) + 1u];
+
+
+        /* R0 = (ya + yc), R1 = (xa + xc) */
+        R0 = __SSAT(T0 + S0, 16u);
+        R1 = __SSAT(T1 + S1, 16u);
+        /* S0 = (ya - yc), S1 = (xa - xc) */
+        S0 = __SSAT(T0 - S0, 16u);
+        S1 = __SSAT(T1 - S1, 16u);
+
+        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+        /* Read yb (real), xb(imag) input */
+        T0 = pSrc16[i1 * 2u];
+        T1 = pSrc16[(i1 * 2u) + 1u];
+
+        /* Read yd (real), xd(imag) input */
+        U0 = pSrc16[i3 * 2u];
+        U1 = pSrc16[(i3 * 2u) + 1u];
+
+        /* T0 = (yb + yd), T1 = (xb + xd) */
+        T0 = __SSAT(T0 + U0, 16u);
+        T1 = __SSAT(T1 + U1, 16u);
+
+        /*  writing the butterfly processed i0 sample */
+        /* xa' = xa + xb + xc + xd */
+        /* ya' = ya + yb + yc + yd */
+        pSrc16[i0 * 2u] = ((R0 >> 1u) + (T0 >> 1u)) >> 1u;
+        pSrc16[(i0 * 2u) + 1u] = ((R1 >> 1u) + (T1 >> 1u)) >> 1u;
+
+        /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+        R0 = (R0 >> 1u) - (T0 >> 1u);
+        R1 = (R1 >> 1u) - (T1 >> 1u);
+
+        /* (ya-yb+yc-yd)* (si2) - (xa-xb+xc-xd)* co2 */
+        out1 = (short) ((Co2 * R0 - Si2 * R1) >> 16);
+        /* (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+        out2 = (short) ((Si2 * R0 + Co2 * R1) >> 16);
+
+        /*  Reading i0+3fftLen/4 */
+        /* Read yb (real), xb(imag) input */
+        T0 = pSrc16[i1 * 2u];
+        T1 = pSrc16[(i1 * 2u) + 1u];
+
+        /*  writing the butterfly processed i0 + fftLen/4 sample */
+        /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+        /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+        pSrc16[i1 * 2u] = out1;
+        pSrc16[(i1 * 2u) + 1u] = out2;
+
+        /*  Butterfly calculations */
+        /* Read yd (real), xd(imag) input */
+        U0 = pSrc16[i3 * 2u];
+        U1 = pSrc16[(i3 * 2u) + 1u];
+
+        /* T0 = yb-yd, T1 = xb-xd) */
+        T0 = __SSAT(T0 - U0, 16u);
+        T1 = __SSAT(T1 - U1, 16u);
+
+        /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */
+        R0 = (S0 >> 1u) + (T1 >> 1u);
+        R1 = (S1 >> 1u) - (T0 >> 1u);
+
+        /* S1 = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */
+        S0 = (S0 >> 1u) - (T1 >> 1u);
+        S1 = (S1 >> 1u) + (T0 >> 1u);
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = (short) ((Co1 * S0 - Si1 * S1) >> 16u);
+        out2 = (short) ((Si1 * S0 + Co1 * S1) >> 16u);
+        /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+        /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+        pSrc16[i2 * 2u] = out1;
+        pSrc16[(i2 * 2u) + 1u] = out2;
+
+        /*  Butterfly process for the i0+3fftLen/4 sample */
+        out1 = (short) ((Co3 * R0 - Si3 * R1) >> 16u);
+
+        out2 = (short) ((Si3 * R0 + Co3 * R1) >> 16u);
+        /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */
+        /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */
+        pSrc16[i3 * 2u] = out1;
+        pSrc16[(i3 * 2u) + 1u] = out2;
+
+
+      }
+    }
+    /*  Twiddle coefficients index modifier */
+    twidCoefModifier <<= 2u;
+  }
+  /*  End of Middle stages process */
+
+
+  /* data is in 10.6(q6) format for the 1024 point */
+  /* data is in 8.8(q8) format for the 256 point   */
+  /* data is in 6.10(q10) format for the 64 point  */
+  /* data is in 4.12(q12) format for the 16 point  */
+
+  /* start of last stage process */
+
+
+  /*  Initializations for the last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /*  Butterfly implementation */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T0 = pSrc16[i0 * 2u];
+    T1 = pSrc16[(i0 * 2u) + 1u];
+    /* Read yc (real), xc(imag) input */
+    S0 = pSrc16[i2 * 2u];
+    S1 = pSrc16[(i2 * 2u) + 1u];
+
+    /* R0 = (ya + yc), R1 = (xa + xc) */
+    R0 = __SSAT(T0 + S0, 16u);
+    R1 = __SSAT(T1 + S1, 16u);
+    /* S0 = (ya - yc), S1 = (xa - xc) */
+    S0 = __SSAT(T0 - S0, 16u);
+    S1 = __SSAT(T1 - S1, 16u);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u];
+    T1 = pSrc16[(i1 * 2u) + 1u];
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2u];
+    U1 = pSrc16[(i3 * 2u) + 1u];
+
+    /* T0 = (yb + yd), T1 = (xb + xd) */
+    T0 = __SSAT(T0 + U0, 16u);
+    T1 = __SSAT(T1 + U1, 16u);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+    R0 = (R0 >> 1u) - (T0 >> 1u);
+    R1 = (R1 >> 1u) - (T1 >> 1u);
+
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u];
+    T1 = pSrc16[(i1 * 2u) + 1u];
+
+    /*  writing the butterfly processed i0 + fftLen/4 sample */
+    /* xc' = (xa-xb+xc-xd) */
+    /* yc' = (ya-yb+yc-yd) */
+    pSrc16[i1 * 2u] = R0;
+    pSrc16[(i1 * 2u) + 1u] = R1;
+
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2u];
+    U1 = pSrc16[(i3 * 2u) + 1u];
+    /* T0 = (yb - yd), T1 = (xb - xd) */
+    T0 = __SSAT(T0 - U0, 16u);
+    T1 = __SSAT(T1 - U1, 16u);
+
+    /*  writing the butterfly processed i0 + fftLen/2 sample */
+    /* xb' = (xa-yb-xc+yd) */
+    /* yb' = (ya+xb-yc-xd) */
+    pSrc16[i2 * 2u] = (S0 >> 1u) - (T1 >> 1u);
+    pSrc16[(i2 * 2u) + 1u] = (S1 >> 1u) + (T0 >> 1u);
+
+
+    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
+    /* xd' = (xa+yb-xc-yd) */
+    /* yd' = (ya-xb-yc+xd) */
+    pSrc16[i3 * 2u] = (S0 >> 1u) + (T1 >> 1u);
+    pSrc16[(i3 * 2u) + 1u] = (S1 >> 1u) - (T0 >> 1u);
+  }
+  /* end of last stage  process */
+
+  /* output is in 11.5(q5) format for the 1024 point */
+  /* output is in 9.7(q7) format for the 256 point   */
+  /* output is in 7.9(q9) format for the 64 point  */
+  /* output is in 5.11(q11) format for the 16 point  */
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+
+/*   
+   * @brief  In-place bit reversal function.  
+   * @param[in, out] *pSrc        points to the in-place buffer of Q15 data type.  
+   * @param[in]      fftLen       length of the FFT.  
+   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table  
+   * @param[in]      *pBitRevTab  points to bit reversal table.  
+   * @return none.  
+ */
+
+void arm_bitreversal_q15(
+  q15_t * pSrc16,
+  uint32_t fftLen,
+  uint16_t bitRevFactor,
+  uint16_t * pBitRevTab)
+{
+  q31_t *pSrc = (q31_t *) pSrc16;
+  q31_t in;
+  uint32_t fftLenBy2, fftLenBy2p1;
+  uint32_t i, j;
+
+  /*  Initializations */
+  j = 0u;
+  fftLenBy2 = fftLen / 2u;
+  fftLenBy2p1 = (fftLen / 2u) + 1u;
+
+  /* Bit Reversal Implementation */
+  for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
+  {
+    if(i < j)
+    {
+      /*  pSrc[i] <-> pSrc[j]; */
+      /*  pSrc[i+1u] <-> pSrc[j+1u] */
+      in = pSrc[i];
+      pSrc[i] = pSrc[j];
+      pSrc[j] = in;
+
+      /*  pSrc[i + fftLenBy2p1] <-> pSrc[j + fftLenBy2p1];  */
+      /*  pSrc[i + fftLenBy2p1+1u] <-> pSrc[j + fftLenBy2p1+1u] */
+      in = pSrc[i + fftLenBy2p1];
+      pSrc[i + fftLenBy2p1] = pSrc[j + fftLenBy2p1];
+      pSrc[j + fftLenBy2p1] = in;
+    }
+
+    /*  pSrc[i+1u] <-> pSrc[j+fftLenBy2];         */
+    /*  pSrc[i+2] <-> pSrc[j+fftLenBy2+1u]  */
+    in = pSrc[i + 1u];
+    pSrc[i + 1u] = pSrc[j + fftLenBy2];
+    pSrc[j + fftLenBy2] = in;
+
+    /*  Reading the index for the bit reversal */
+    j = *pBitRevTab;
+
+    /*  Updating the bit reversal index depending on the fft length  */
+    pBitRevTab += bitRevFactor;
+  }
+}
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c
new file mode 100644
index 000000000..ad0265616
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c
@@ -0,0 +1,906 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix4_q31.c   
+*   
+* Description:	This file has function definition of Radix-4 FFT & IFFT function and   
+*				In-place bit reversal using bit reversal table   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup CFFT_CIFFT   
+ * @{   
+ */
+
+/**   
+ * @details   
+ * @brief Processing function for the Q31 CFFT/CIFFT.   
+ * @param[in]      *S    points to an instance of the Q31 CFFT/CIFFT structure.  
+ * @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.  
+ * @return none.   
+ *    
+ * \par Input and output formats:   
+ * \par   
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.  
+ * Hence the output format is different for different FFT sizes.   
+ * The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT:  
+ * \par  
+ * \image html CFFTQ31.gif "Input and Output Formats for Q31 CFFT"   
+ * \image html CIFFTQ31.gif "Input and Output Formats for Q31 CIFFT"   
+ *   
+ */
+
+void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc)
+{
+  if(S->ifftFlag == 1u)
+  {
+    /* Complex IFFT radix-4 */
+    arm_radix4_butterfly_inverse_q31(pSrc, S->fftLen, S->pTwiddle,
+                                     S->twidCoefModifier);
+  }
+  else
+  {
+    /* Complex FFT radix-4 */
+    arm_radix4_butterfly_q31(pSrc, S->fftLen, S->pTwiddle,
+                             S->twidCoefModifier);
+  }
+
+
+  if(S->bitReverseFlag == 1u)
+  {
+    /*  Bit Reversal */
+    arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+  }
+
+}
+
+/**   
+ * @} end of CFFT_CIFFT group   
+ */
+
+/*   
+* Radix-4 FFT algorithm used is :   
+*   
+* Input real and imaginary data:   
+* x(n) = xa + j * ya   
+* x(n+N/4 ) = xb + j * yb   
+* x(n+N/2 ) = xc + j * yc   
+* x(n+3N 4) = xd + j * yd   
+*   
+*   
+* Output real and imaginary data:   
+* x(4r) = xa'+ j * ya'   
+* x(4r+1) = xb'+ j * yb'   
+* x(4r+2) = xc'+ j * yc'   
+* x(4r+3) = xd'+ j * yd'   
+*   
+*   
+* Twiddle factors for radix-4 FFT:   
+* Wn = co1 + j * (- si1)   
+* W2n = co2 + j * (- si2)   
+* W3n = co3 + j * (- si3)   
+*   
+*  Butterfly implementation:   
+* xa' = xa + xb + xc + xd   
+* ya' = ya + yb + yc + yd   
+* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)   
+* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)   
+* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)   
+* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)   
+* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)   
+* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)   
+*   
+*/
+
+/**   
+ * @brief  Core function for the Q31 CFFT butterfly process.  
+ * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.  
+ * @param[in]      fftLen           length of the FFT.  
+ * @param[in]      *pCoef           points to twiddle coefficient buffer.  
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.  
+ */
+
+void arm_radix4_butterfly_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pCoef,
+  uint32_t twidCoefModifier)
+{
+  uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k;
+  q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
+
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+
+  /* start of first stage process */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+  i0 = 0u;
+  ia1 = 0u;
+
+  j = n2;
+
+  /*  Calculation of first stage */
+  do
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /* input is in 1.31(q31) format and provide 4 guard bits for the input */
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = (pSrc[(2u * i0)] >> 4u) + (pSrc[(2u * i2)] >> 4u);
+    /* xa - xc */
+    r2 = (pSrc[2u * i0] >> 4u) - (pSrc[2u * i2] >> 4u);
+
+    /* ya + yc */
+    s1 = (pSrc[(2u * i0) + 1u] >> 4u) + (pSrc[(2u * i2) + 1u] >> 4u);
+    /* ya - yc */
+    s2 = (pSrc[(2u * i0) + 1u] >> 4u) - (pSrc[(2u * i2) + 1u] >> 4u);
+
+    /* xb + xd */
+    t1 = (pSrc[2u * i1] >> 4u) + (pSrc[2u * i3] >> 4u);
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = (r1 + t1);
+    /* (xa + xc) - (xb + xd) */
+    r1 = r1 - t1;
+    /* yb + yd */
+    t2 = (pSrc[(2u * i1) + 1u] >> 4u) + (pSrc[(2u * i3) + 1u] >> 4u);
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = (s1 + t2);
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* yb - yd */
+    t1 = (pSrc[(2u * i1) + 1u] >> 4u) - (pSrc[(2u * i3) + 1u] >> 4u);
+    /* xb - xd */
+    t2 = (pSrc[2u * i1] >> 4u) - (pSrc[2u * i3] >> 4u);
+
+    /*  index calculation for the coefficients */
+    ia2 = 2u * ia1;
+    co2 = pCoef[ia2 * 2u];
+    si2 = pCoef[(ia2 * 2u) + 1u];
+
+    /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
+                     ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
+
+    /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
+                            ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
+
+    /* (xa - xc) + (yb - yd) */
+    r1 = r2 + t1;
+    /* (xa - xc) - (yb - yd) */
+    r2 = r2 - t1;
+
+    /* (ya - yc) - (xb - xd) */
+    s1 = s2 - t2;
+    /* (ya - yc) + (xb - xd) */
+    s2 = s2 + t2;
+
+    co1 = pCoef[ia1 * 2u];
+    si1 = pCoef[(ia1 * 2u) + 1u];
+
+    /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
+                     ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
+
+    /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
+                            ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
+
+    /*  index calculation for the coefficients */
+    ia3 = 3u * ia1;
+    co3 = pCoef[ia3 * 2u];
+    si3 = pCoef[(ia3 * 2u) + 1u];
+
+    /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
+                     ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
+
+    /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
+                            ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
+
+    /*  Twiddle coefficients index modifier */
+    ia1 = ia1 + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+
+  /* end of first stage process */
+
+  /* data is in 5.27(q27) format */
+
+
+  /* start of Middle stages process */
+
+
+  /* each stage in middle stages provides two down scaling of the input */
+
+  twidCoefModifier <<= 2u;
+
+
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    /*  Calculation of first stage */
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Butterfly implementation */
+        /* xa + xc */
+        r1 = pSrc[2u * i0] + pSrc[2u * i2];
+        /* xa - xc */
+        r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+        /* ya + yc */
+        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+        /* ya - yc */
+        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+        /* xb + xd */
+        t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+        /* xa' = xa + xb + xc + xd */
+        pSrc[2u * i0] = (r1 + t1) >> 2u;
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+
+        /* yb + yd */
+        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+        /* ya' = ya + yb + yc + yd */
+        pSrc[(2u * i0) + 1u] = (s1 + t2) >> 2u;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+        /* (xb - xd) */
+        t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+        /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+        pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
+                         ((int32_t) (((q63_t) s1 * si2) >> 32))) >> 1u;
+
+        /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+        pSrc[(2u * i1) + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
+                                ((int32_t) (((q63_t) r1 * si2) >> 32))) >> 1u;
+
+        /* (xa - xc) + (yb - yd) */
+        r1 = r2 + t1;
+        /* (xa - xc) - (yb - yd) */
+        r2 = r2 - t1;
+
+        /* (ya - yc) -  (xb - xd) */
+        s1 = s2 - t2;
+        /* (ya - yc) +  (xb - xd) */
+        s2 = s2 + t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+        pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
+                         ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
+
+        /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+        pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
+                                ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
+
+        /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+        pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
+                         ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
+
+        /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+        pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
+                                ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+
+  /* End of Middle stages process */
+
+  /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */
+  /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */
+  /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */
+  /* data is in 5.27(q27) format for the 16 point as there are no middle stages */
+
+
+  /* start of Last stage process */
+
+  /*  Initializations of last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /*  Calculations of last stage */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+    /* xa + xb */
+    r1 = pSrc[2u * i0] + pSrc[2u * i2];
+    /* xa - xb */
+    r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+    /* ya + yc */
+    s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+    /* ya - yc */
+    s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+    /* xc + xd */
+    t1 = pSrc[2u * i1] + pSrc[2u * i3];
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = (r1 + t1);
+    /* (xa + xb) - (xc + xd) */
+    r1 = r1 - t1;
+
+    /* yb + yd */
+    t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = (s1 + t2);
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* (yb-yd) */
+    t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+    /* (xb-xd) */
+    t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+    /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = r1;
+    /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = s1;
+
+    /* (xa+yb-xc-yd) */
+    r1 = r2 + t1;
+    /* (xa-yb-xc+yd) */
+    r2 = r2 - t1;
+
+    /* (ya-xb-yc+xd) */
+    s1 = s2 - t2;
+    /* (ya+xb-yc-xd) */
+    s2 = s2 + t2;
+
+    /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = r1;
+    /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = s1;
+
+    /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = r2;
+    /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = s2;
+
+
+  }
+
+  /* output is in 11.21(q21) format for the 1024 point */
+  /* output is in 9.23(q23) format for the 256 point */
+  /* output is in 7.25(q25) format for the 64 point */
+  /* output is in 5.27(q27) format for the 16 point */
+
+  /* End of last stage process */
+
+}
+
+
+/**   
+ * @brief  Core function for the Q31 CIFFT butterfly process.  
+ * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.  
+ * @param[in]      fftLen           length of the FFT.  
+ * @param[in]      *pCoef           points to twiddle coefficient buffer.  
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.  
+ */
+
+
+/*   
+* Radix-4 IFFT algorithm used is :   
+*   
+* CIFFT uses same twiddle coefficients as CFFT Function   
+*  x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4]   
+*   
+*   
+* IFFT is implemented with following changes in equations from FFT   
+*   
+* Input real and imaginary data:   
+* x(n) = xa + j * ya   
+* x(n+N/4 ) = xb + j * yb   
+* x(n+N/2 ) = xc + j * yc   
+* x(n+3N 4) = xd + j * yd   
+*   
+*   
+* Output real and imaginary data:   
+* x(4r) = xa'+ j * ya'   
+* x(4r+1) = xb'+ j * yb'   
+* x(4r+2) = xc'+ j * yc'   
+* x(4r+3) = xd'+ j * yd'   
+*   
+*   
+* Twiddle factors for radix-4 IFFT:   
+* Wn = co1 + j * (si1)   
+* W2n = co2 + j * (si2)   
+* W3n = co3 + j * (si3)   
+   
+* The real and imaginary output values for the radix-4 butterfly are   
+* xa' = xa + xb + xc + xd   
+* ya' = ya + yb + yc + yd   
+* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)   
+* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)   
+* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)   
+* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)   
+* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)   
+* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)   
+*   
+*/
+
+void arm_radix4_butterfly_inverse_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pCoef,
+  uint32_t twidCoefModifier)
+{
+  uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k;
+  q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
+
+  /* input is be 1.31(q31) format for all FFT sizes */
+  /* Total process is divided into three stages */
+  /* process first stage, middle stages, & last stage */
+
+  /* Start of first stage process */
+
+  /* Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+  i0 = 0u;
+  ia1 = 0u;
+
+  j = n2;
+
+  do
+  {
+
+    /* input is in 1.31(q31) format and provide 4 guard bits for the input */
+
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = (pSrc[2u * i0] >> 4u) + (pSrc[2u * i2] >> 4u);
+    /* xa - xc */
+    r2 = (pSrc[2u * i0] >> 4u) - (pSrc[2u * i2] >> 4u);
+
+    /* ya + yc */
+    s1 = (pSrc[(2u * i0) + 1u] >> 4u) + (pSrc[(2u * i2) + 1u] >> 4u);
+    /* ya - yc */
+    s2 = (pSrc[(2u * i0) + 1u] >> 4u) - (pSrc[(2u * i2) + 1u] >> 4u);
+
+    /* xb + xd */
+    t1 = (pSrc[2u * i1] >> 4u) + (pSrc[2u * i3] >> 4u);
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = (r1 + t1);
+    /* (xa + xc) - (xb + xd) */
+    r1 = r1 - t1;
+    /* yb + yd */
+    t2 = (pSrc[(2u * i1) + 1u] >> 4u) + (pSrc[(2u * i3) + 1u] >> 4u);
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = (s1 + t2);
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* yb - yd */
+    t1 = (pSrc[(2u * i1) + 1u] >> 4u) - (pSrc[(2u * i3) + 1u] >> 4u);
+    /* xb - xd */
+    t2 = (pSrc[2u * i1] >> 4u) - (pSrc[2u * i3] >> 4u);
+
+    /*  index calculation for the coefficients */
+    ia2 = 2u * ia1;
+    co2 = pCoef[ia2 * 2u];
+    si2 = pCoef[(ia2 * 2u) + 1u];
+
+    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) -
+                     ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
+
+    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+    pSrc[2u * i1 + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) +
+                          ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
+
+    /* (xa - xc) - (yb - yd) */
+    r1 = r2 - t1;
+    /* (xa - xc) + (yb - yd) */
+    r2 = r2 + t1;
+
+    /* (ya - yc) + (xb - xd) */
+    s1 = s2 + t2;
+    /* (ya - yc) - (xb - xd) */
+    s2 = s2 - t2;
+
+    co1 = pCoef[ia1 * 2u];
+    si1 = pCoef[(ia1 * 2u) + 1u];
+
+    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
+                     ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
+
+    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
+                            ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
+
+    /*  index calculation for the coefficients */
+    ia3 = 3u * ia1;
+    co3 = pCoef[ia3 * 2u];
+    si3 = pCoef[(ia3 * 2u) + 1u];
+
+    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
+                     ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
+
+    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
+                            ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
+
+    /*  Twiddle coefficients index modifier */
+    ia1 = ia1 + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+
+  /* data is in 5.27(q27) format */
+  /* each stage provides two down scaling of the input */
+
+
+  /* Start of Middle stages process */
+
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of second stage to excluding last stage */
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    for (j = 0; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Butterfly implementation */
+        /* xa + xc */
+        r1 = pSrc[2u * i0] + pSrc[2u * i2];
+        /* xa - xc */
+        r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+        /* ya + yc */
+        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+        /* ya - yc */
+        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+        /* xb + xd */
+        t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+        /* xa' = xa + xb + xc + xd */
+        pSrc[2u * i0] = (r1 + t1) >> 2u;
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+        /* yb + yd */
+        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+        /* ya' = ya + yb + yc + yd */
+        pSrc[(2u * i0) + 1u] = (s1 + t2) >> 2u;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+        /* (xb - xd) */
+        t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+        /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+        pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32u)) -
+                         ((int32_t) (((q63_t) s1 * si2) >> 32u))) >> 1u;
+
+        /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+        pSrc[(2u * i1) + 1u] =
+          (((int32_t) (((q63_t) s1 * co2) >> 32u)) +
+           ((int32_t) (((q63_t) r1 * si2) >> 32u))) >> 1u;
+
+        /* (xa - xc) - (yb - yd) */
+        r1 = r2 - t1;
+        /* (xa - xc) + (yb - yd) */
+        r2 = r2 + t1;
+
+        /* (ya - yc) +  (xb - xd) */
+        s1 = s2 + t2;
+        /* (ya - yc) -  (xb - xd) */
+        s2 = s2 - t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+        pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
+                         ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
+
+        /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+        pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
+                                ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
+
+        /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+        pSrc[(2u * i3)] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
+                           ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
+
+        /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+        pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
+                                ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+
+  /* End of Middle stages process */
+
+  /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */
+  /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */
+  /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */
+  /* data is in 5.27(q27) format for the 16 point as there are no middle stages */
+
+
+  /* Start of last stage process */
+
+
+  /*  Initializations of last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /*  Calculations of last stage */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = pSrc[2u * i0] + pSrc[2u * i2];
+    /* xa - xc */
+    r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+    /* ya + yc */
+    s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+    /* ya - yc */
+    s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+    /* xc + xd */
+    t1 = pSrc[2u * i1] + pSrc[2u * i3];
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = (r1 + t1);
+    /* (xa + xb) - (xc + xd) */
+    r1 = r1 - t1;
+
+    /* yb + yd */
+    t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = (s1 + t2);
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* (yb-yd) */
+    t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+    /* (xb-xd) */
+    t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = r1;
+    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = s1;
+
+    /* (xa - xc) - (yb-yd) */
+    r1 = r2 - t1;
+
+    /* (xa - xc) + (yb-yd) */
+    r2 = r2 + t1;
+
+    /* (ya - yc) + (xb-xd) */
+    s1 = s2 + t2;
+
+    /* (ya - yc) - (xb-xd) */
+    s2 = s2 - t2;
+
+    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = r1;
+    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = s1;
+
+    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = r2;
+    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = s2;
+
+  }
+
+  /* output is in 11.21(q21) format for the 1024 point */
+  /* output is in 9.23(q23) format for the 256 point */
+  /* output is in 7.25(q25) format for the 64 point */
+  /* output is in 5.27(q27) format for the 16 point */
+
+  /* End of last stage process */
+}
+
+
+/*   
+ * @brief  In-place bit reversal function.  
+ * @param[in, out] *pSrc        points to the in-place buffer of Q31 data type.  
+ * @param[in]      fftLen       length of the FFT.  
+ * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table  
+ * @param[in]      *pBitRevTab  points to bit reversal table.  
+ * @return none.  
+ */
+
+void arm_bitreversal_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  uint16_t bitRevFactor,
+  uint16_t * pBitRevTable)
+{
+  uint32_t fftLenBy2, fftLenBy2p1, i, j;
+  q31_t in;
+
+  /*  Initializations      */
+  j = 0u;
+  fftLenBy2 = fftLen / 2u;
+  fftLenBy2p1 = (fftLen / 2u) + 1u;
+
+  /* Bit Reversal Implementation */
+  for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
+  {
+    if(i < j)
+    {
+      /*  pSrc[i] <-> pSrc[j]; */
+      in = pSrc[2u * i];
+      pSrc[2u * i] = pSrc[2u * j];
+      pSrc[2u * j] = in;
+
+      /*  pSrc[i+1u] <-> pSrc[j+1u] */
+      in = pSrc[(2u * i) + 1u];
+      pSrc[(2u * i) + 1u] = pSrc[(2u * j) + 1u];
+      pSrc[(2u * j) + 1u] = in;
+
+      /*  pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */
+      in = pSrc[2u * (i + fftLenBy2p1)];
+      pSrc[2u * (i + fftLenBy2p1)] = pSrc[2u * (j + fftLenBy2p1)];
+      pSrc[2u * (j + fftLenBy2p1)] = in;
+
+      /*  pSrc[i+fftLenBy2p1+1u] <-> pSrc[j+fftLenBy2p1+1u] */
+      in = pSrc[(2u * (i + fftLenBy2p1)) + 1u];
+      pSrc[(2u * (i + fftLenBy2p1)) + 1u] =
+        pSrc[(2u * (j + fftLenBy2p1)) + 1u];
+      pSrc[(2u * (j + fftLenBy2p1)) + 1u] = in;
+
+    }
+
+    /*  pSrc[i+1u] <-> pSrc[j+1u] */
+    in = pSrc[2u * (i + 1u)];
+    pSrc[2u * (i + 1u)] = pSrc[2u * (j + fftLenBy2)];
+    pSrc[2u * (j + fftLenBy2)] = in;
+
+    /*  pSrc[i+2u] <-> pSrc[j+2u] */
+    in = pSrc[(2u * (i + 1u)) + 1u];
+    pSrc[(2u * (i + 1u)) + 1u] = pSrc[(2u * (j + fftLenBy2)) + 1u];
+    pSrc[(2u * (j + fftLenBy2)) + 1u] = in;
+
+    /*  Reading the index for the bit reversal */
+    j = *pBitRevTable;
+
+    /*  Updating the bit reversal index depending on the fft length */
+    pBitRevTable += bitRevFactor;
+  }
+}
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c
new file mode 100644
index 000000000..c9a3ec5ad
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c
@@ -0,0 +1,450 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_dct4_f32.c   
+*   
+* Description:	Processing function of DCT4 & IDCT4 F32.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @defgroup DCT4_IDCT4 DCT Type IV Functions   
+ * Representation of signals by minimum number of values is important for storage and transmission.   
+ * The possibility of large discontinuity between the beginning and end of a period of a signal   
+ * in DFT can be avoided by extending the signal so that it is even-symmetric.   
+ * Discrete Cosine Transform (DCT) is constructed such that its energy is heavily concentrated in the lower part of the   
+ * spectrum and is very widely used in signal and image coding applications.   
+ * The family of DCTs (DCT type- 1,2,3,4) is the outcome of different combinations of homogeneous boundary conditions.   
+ * DCT has an excellent energy-packing capability, hence has many applications and in data compression in particular.   
+ *   
+ * DCT is essentially the Discrete Fourier Transform(DFT) of an even-extended real signal.   
+ * Reordering of the input data makes the computation of DCT just a problem of   
+ * computing the DFT of a real signal with a few additional operations.   
+ * This approach provides regular, simple, and very efficient DCT algorithms for practical hardware and software implementations.   
+ *    
+ * DCT type-II can be implemented using Fast fourier transform (FFT) internally, as the transform is applied on real values, Real FFT can be used.   
+ * DCT4 is implemented using DCT2 as their implementations are similar except with some added pre-processing and post-processing.   
+ * DCT2 implementation can be described in the following steps:   
+ * - Re-ordering input   
+ * - Calculating Real FFT   
+ * - Multiplication of weights and Real FFT output and getting real part from the product.   
+ *   
+ * This process is explained by the block diagram below:   
+ * \image html DCT4.gif "Discrete Cosine Transform - type-IV"   
+ *   
+ * \par Algorithm:   
+ * The N-point type-IV DCT is defined as a real, linear transformation by the formula:   
+ * \image html DCT4Equation.gif   
+ * where k = 0,1,2,.....N-1   
+ *\par   
+ * Its inverse is defined as follows:   
+ * \image html IDCT4Equation.gif   
+ * where n = 0,1,2,.....N-1   
+ *\par   
+ * The DCT4 matrices become involutory (i.e. they are self-inverse) by multiplying with an overall scale factor of sqrt(2/N).   
+ * The symmetry of the transform matrix indicates that the fast algorithms for the forward   
+ * and inverse transform computation are identical.   
+ * Note that the implementation of Inverse DCT4 and DCT4 is same, hence same process function can be used for both.   
+ *   
+ * \par Lengths supported by the transform:   
+ *  As DCT4 internally uses Real FFT, it supports all the lengths supported by arm_rfft_f32().   
+ * The library provides separate functions for Q15, Q31, and floating-point data types.   
+ * \par Instance Structure   
+ * The instances for Real FFT and FFT, cosine values table and twiddle factor table are stored in an instance data structure.   
+ * A separate instance structure must be defined for each transform.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Initializes Real FFT as its process function is used internally in DCT4, by calling arm_rfft_init_f32().   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Manually initialize the instance structure as follows:   
+ * 
   
+ *arm_dct4_instance_f32 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};   
+ *arm_dct4_instance_q31 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};  
+ *arm_dct4_instance_q15 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};  
+ * 
  
+ * where \c N is the length of the DCT4; \c Nby2 is half of the length of the DCT4;  
+ * \c normalize is normalizing factor used and is equal to sqrt(2/N);   
+ * \c pTwiddle points to the twiddle factor table;  
+ * \c pCosFactor points to the cosFactor table;  
+ * \c pRfft points to the real FFT instance;  
+ * \c pCfft points to the complex FFT instance;  
+ * The CFFT and RFFT structures also needs to be initialized, refer to arm_cfft_radix4_f32()  
+ * and arm_rfft_f32() respectively for details regarding static initialization.  
+ *  
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the DCT4 transform functions.   
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+ /**   
+ * @addtogroup DCT4_IDCT4   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the floating-point DCT4/IDCT4.  
+ * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.  
+ * @param[in]       *pState        points to state buffer.  
+ * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.  
+ * @return none.  
+ */
+
+void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer)
+{
+  uint32_t i;                                    /* Loop counter */
+  float32_t *weights = S->pTwiddle;              /* Pointer to the Weights table */
+  float32_t *cosFact = S->pCosFactor;            /* Pointer to the cos factors table */
+  float32_t *pS1, *pS2, *pbuff;                  /* Temporary pointers for input buffer and pState buffer */
+  float32_t in;                                  /* Temporary variable */
+
+
+  /* DCT4 computation involves DCT2 (which is calculated using RFFT)   
+   * along with some pre-processing and post-processing.   
+   * Computational procedure is explained as follows:   
+   * (a) Pre-processing involves multiplying input with cos factor,   
+   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))   
+   *              where,   
+   *                 r(n) -- output of preprocessing   
+   *                 u(n) -- input to preprocessing(actual Source buffer)   
+   * (b) Calculation of DCT2 using FFT is divided into three steps:   
+   *                  Step1: Re-ordering of even and odd elements of input.   
+   *                  Step2: Calculating FFT of the re-ordered input.   
+   *                  Step3: Taking the real part of the product of FFT output and weights.   
+   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:   
+   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *                        where,   
+   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output   
+   * (d) Multiplying the output with the normalizing factor sqrt(2/N).   
+   */
+
+        /*-------- Pre-processing ------------*/
+  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+  arm_scale_f32(pInlineBuffer, 2.0f, pInlineBuffer, S->N);
+  arm_mult_f32(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+
+  /* ----------------------------------------------------------------   
+   * Step1: Re-ordering of even and odd elements as,   
+   *             pState[i] =  pInlineBuffer[2*i] and   
+   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2   
+   ---------------------------------------------------------------------*/
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+  pS2 = pState + (S->N - 1u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+  i = (uint32_t) S->Nby2 >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = (uint32_t) S->N >> 2u;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.   
+   * Compute 4 outputs at a time */
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------   
+   *     Step2: Calculate RFFT for N-point input   
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_f32(S->pRfft, pInlineBuffer, pState);
+
+        /*----------------------------------------------------------------------   
+	 *  Step3: Multiply the FFT output with the weights.   
+	 *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_f32(pState, weights, pState, S->N);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,   
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+  i = ((uint32_t) S->N - 1u) >> 2u;
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ * (float32_t) 0.5;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  i = ((uint32_t) S->N - 1u) % 0x4u;
+
+  while(i > 0u)
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = (uint32_t) S->N >> 2u;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initializing the loop counter to N/2 */
+  i = (uint32_t) S->Nby2;
+
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter */
+  i = (uint32_t) S->N;
+
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------   
+   *     Step2: Calculate RFFT for N-point input   
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_f32(S->pRfft, pInlineBuffer, pState);
+
+        /*----------------------------------------------------------------------   
+	 *  Step3: Multiply the FFT output with the weights.   
+	 *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_f32(pState, weights, pState, S->N);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,   
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ * (float32_t) 0.5;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* Initializing the loop counter */
+  i = ((uint32_t) S->N - 1u);
+
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter */
+  i = (uint32_t) S->N;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+   * @} end of DCT4_IDCT4 group   
+   */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c
new file mode 100644
index 000000000..af576f22a
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c
@@ -0,0 +1,4208 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_dct4_init_f32.c   
+*   
+* Description:	Initialization function of DCT-4 & IDCT4 F32   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup DCT4_IDCT4   
+ * @{   
+ */
+
+/*   
+* @brief  Weights Table   
+*/
+
+/**   
+* \par   
+* Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
   
+* \par   
+* C command to generate the table   
+* 
   
+* for(i = 0; i< N; i++)   
+* {   
+*    weights[2*i]= cos(i*c);   
+*    weights[(2*i)+1]= -sin(i * c);   
+* } 
   
+* \par   
+* Where N is the Number of weights to be calculated and c is pi/(2*N)   
+* \par   
+* In the tables below the real and imaginary values are placed alternatively, hence the   
+* array length is 2*N.   
+*/
+
+static const float32_t Weights_128[256] = {
+  1.000000000000000000f, 0.000000000000000000f, 0.999924701839144500f,
+  -0.012271538285719925f,
+  0.999698818696204250f, -0.024541228522912288f, 0.999322384588349540f,
+  -0.036807222941358832f,
+  0.998795456205172410f, -0.049067674327418015f, 0.998118112900149180f,
+  -0.061320736302208578f,
+  0.997290456678690210f, -0.073564563599667426f, 0.996312612182778000f,
+  -0.085797312344439894f,
+  0.995184726672196930f, -0.098017140329560604f, 0.993906970002356060f,
+  -0.110222207293883060f,
+  0.992479534598709970f, -0.122410675199216200f, 0.990902635427780010f,
+  -0.134580708507126170f,
+  0.989176509964781010f, -0.146730474455361750f, 0.987301418157858430f,
+  -0.158858143333861450f,
+  0.985277642388941220f, -0.170961888760301220f, 0.983105487431216290f,
+  -0.183039887955140950f,
+  0.980785280403230430f, -0.195090322016128250f, 0.978317370719627650f,
+  -0.207111376192218560f,
+  0.975702130038528570f, -0.219101240156869800f, 0.972939952205560180f,
+  -0.231058108280671110f,
+  0.970031253194543970f, -0.242980179903263870f, 0.966976471044852070f,
+  -0.254865659604514570f,
+  0.963776065795439840f, -0.266712757474898370f, 0.960430519415565790f,
+  -0.278519689385053060f,
+  0.956940335732208820f, -0.290284677254462330f, 0.953306040354193860f,
+  -0.302005949319228080f,
+  0.949528180593036670f, -0.313681740398891520f, 0.945607325380521280f,
+  -0.325310292162262930f,
+  0.941544065183020810f, -0.336889853392220050f, 0.937339011912574960f,
+  -0.348418680249434560f,
+  0.932992798834738960f, -0.359895036534988110f, 0.928506080473215590f,
+  -0.371317193951837540f,
+  0.923879532511286740f, -0.382683432365089780f, 0.919113851690057770f,
+  -0.393992040061048100f,
+  0.914209755703530690f, -0.405241314004989860f, 0.909167983090522380f,
+  -0.416429560097637150f,
+  0.903989293123443340f, -0.427555093430282080f, 0.898674465693953820f,
+  -0.438616238538527660f,
+  0.893224301195515320f, -0.449611329654606540f, 0.887639620402853930f,
+  -0.460538710958240010f,
+  0.881921264348355050f, -0.471396736825997640f, 0.876070094195406600f,
+  -0.482183772079122720f,
+  0.870086991108711460f, -0.492898192229784040f, 0.863972856121586810f,
+  -0.503538383725717580f,
+  0.857728610000272120f, -0.514102744193221660f, 0.851355193105265200f,
+  -0.524589682678468950f,
+  0.844853565249707120f, -0.534997619887097150f, 0.838224705554838080f,
+  -0.545324988422046460f,
+  0.831469612302545240f, -0.555570233019602180f, 0.824589302785025290f,
+  -0.565731810783613120f,
+  0.817584813151583710f, -0.575808191417845340f, 0.810457198252594770f,
+  -0.585797857456438860f,
+  0.803207531480644940f, -0.595699304492433360f, 0.795836904608883570f,
+  -0.605511041404325550f,
+  0.788346427626606340f, -0.615231590580626820f, 0.780737228572094490f,
+  -0.624859488142386340f,
+  0.773010453362736990f, -0.634393284163645490f, 0.765167265622458960f,
+  -0.643831542889791390f,
+  0.757208846506484570f, -0.653172842953776760f, 0.749136394523459370f,
+  -0.662415777590171780f,
+  0.740951125354959110f, -0.671558954847018330f, 0.732654271672412820f,
+  -0.680600997795453020f,
+  0.724247082951467000f, -0.689540544737066830f, 0.715730825283818590f,
+  -0.698376249408972920f,
+  0.707106781186547570f, -0.707106781186547460f, 0.698376249408972920f,
+  -0.715730825283818590f,
+  0.689540544737066940f, -0.724247082951466890f, 0.680600997795453130f,
+  -0.732654271672412820f,
+  0.671558954847018330f, -0.740951125354959110f, 0.662415777590171780f,
+  -0.749136394523459260f,
+  0.653172842953776760f, -0.757208846506484460f, 0.643831542889791500f,
+  -0.765167265622458960f,
+  0.634393284163645490f, -0.773010453362736990f, 0.624859488142386450f,
+  -0.780737228572094380f,
+  0.615231590580626820f, -0.788346427626606230f, 0.605511041404325550f,
+  -0.795836904608883460f,
+  0.595699304492433470f, -0.803207531480644830f, 0.585797857456438860f,
+  -0.810457198252594770f,
+  0.575808191417845340f, -0.817584813151583710f, 0.565731810783613230f,
+  -0.824589302785025290f,
+  0.555570233019602290f, -0.831469612302545240f, 0.545324988422046460f,
+  -0.838224705554837970f,
+  0.534997619887097260f, -0.844853565249707010f, 0.524589682678468840f,
+  -0.851355193105265200f,
+  0.514102744193221660f, -0.857728610000272120f, 0.503538383725717580f,
+  -0.863972856121586700f,
+  0.492898192229784090f, -0.870086991108711350f, 0.482183772079122830f,
+  -0.876070094195406600f,
+  0.471396736825997810f, -0.881921264348354940f, 0.460538710958240010f,
+  -0.887639620402853930f,
+  0.449611329654606600f, -0.893224301195515320f, 0.438616238538527710f,
+  -0.898674465693953820f,
+  0.427555093430282200f, -0.903989293123443340f, 0.416429560097637320f,
+  -0.909167983090522270f,
+  0.405241314004989860f, -0.914209755703530690f, 0.393992040061048100f,
+  -0.919113851690057770f,
+  0.382683432365089840f, -0.923879532511286740f, 0.371317193951837600f,
+  -0.928506080473215480f,
+  0.359895036534988280f, -0.932992798834738850f, 0.348418680249434510f,
+  -0.937339011912574960f,
+  0.336889853392220050f, -0.941544065183020810f, 0.325310292162262980f,
+  -0.945607325380521280f,
+  0.313681740398891570f, -0.949528180593036670f, 0.302005949319228200f,
+  -0.953306040354193750f,
+  0.290284677254462330f, -0.956940335732208940f, 0.278519689385053060f,
+  -0.960430519415565790f,
+  0.266712757474898420f, -0.963776065795439840f, 0.254865659604514630f,
+  -0.966976471044852070f,
+  0.242980179903263980f, -0.970031253194543970f, 0.231058108280671280f,
+  -0.972939952205560070f,
+  0.219101240156869770f, -0.975702130038528570f, 0.207111376192218560f,
+  -0.978317370719627650f,
+  0.195090322016128330f, -0.980785280403230430f, 0.183039887955141060f,
+  -0.983105487431216290f,
+  0.170961888760301360f, -0.985277642388941220f, 0.158858143333861390f,
+  -0.987301418157858430f,
+  0.146730474455361750f, -0.989176509964781010f, 0.134580708507126220f,
+  -0.990902635427780010f,
+  0.122410675199216280f, -0.992479534598709970f, 0.110222207293883180f,
+  -0.993906970002356060f,
+  0.098017140329560770f, -0.995184726672196820f, 0.085797312344439880f,
+  -0.996312612182778000f,
+  0.073564563599667454f, -0.997290456678690210f, 0.061320736302208648f,
+  -0.998118112900149180f,
+  0.049067674327418126f, -0.998795456205172410f, 0.036807222941358991f,
+  -0.999322384588349540f,
+  0.024541228522912264f, -0.999698818696204250f, 0.012271538285719944f,
+  -0.999924701839144500f
+};
+
+static const float32_t Weights_512[1024] = {
+  1.000000000000000000f, 0.000000000000000000f, 0.999995293809576190f,
+  -0.003067956762965976f,
+  0.999981175282601110f, -0.006135884649154475f, 0.999957644551963900f,
+  -0.009203754782059819f,
+  0.999924701839144500f, -0.012271538285719925f, 0.999882347454212560f,
+  -0.015339206284988100f,
+  0.999830581795823400f, -0.018406729905804820f, 0.999769405351215280f,
+  -0.021474080275469508f,
+  0.999698818696204250f, -0.024541228522912288f, 0.999618822495178640f,
+  -0.027608145778965740f,
+  0.999529417501093140f, -0.030674803176636626f, 0.999430604555461730f,
+  -0.033741171851377580f,
+  0.999322384588349540f, -0.036807222941358832f, 0.999204758618363890f,
+  -0.039872927587739811f,
+  0.999077727752645360f, -0.042938256934940820f, 0.998941293186856870f,
+  -0.046003182130914623f,
+  0.998795456205172410f, -0.049067674327418015f, 0.998640218180265270f,
+  -0.052131704680283324f,
+  0.998475580573294770f, -0.055195244349689934f, 0.998301544933892890f,
+  -0.058258264500435752f,
+  0.998118112900149180f, -0.061320736302208578f, 0.997925286198596000f,
+  -0.064382630929857465f,
+  0.997723066644191640f, -0.067443919563664051f, 0.997511456140303450f,
+  -0.070504573389613856f,
+  0.997290456678690210f, -0.073564563599667426f, 0.997060070339482960f,
+  -0.076623861392031492f,
+  0.996820299291165670f, -0.079682437971430126f, 0.996571145790554840f,
+  -0.082740264549375692f,
+  0.996312612182778000f, -0.085797312344439894f, 0.996044700901251970f,
+  -0.088853552582524600f,
+  0.995767414467659820f, -0.091908956497132724f, 0.995480755491926940f,
+  -0.094963495329638992f,
+  0.995184726672196930f, -0.098017140329560604f, 0.994879330794805620f,
+  -0.101069862754827820f,
+  0.994564570734255420f, -0.104121633872054590f, 0.994240449453187900f,
+  -0.107172424956808840f,
+  0.993906970002356060f, -0.110222207293883060f, 0.993564135520595300f,
+  -0.113270952177564350f,
+  0.993211949234794500f, -0.116318630911904750f, 0.992850414459865100f,
+  -0.119365214810991350f,
+  0.992479534598709970f, -0.122410675199216200f, 0.992099313142191800f,
+  -0.125454983411546230f,
+  0.991709753669099530f, -0.128498110793793170f, 0.991310859846115440f,
+  -0.131540028702883120f,
+  0.990902635427780010f, -0.134580708507126170f, 0.990485084256457090f,
+  -0.137620121586486040f,
+  0.990058210262297120f, -0.140658239332849210f, 0.989622017463200890f,
+  -0.143695033150294470f,
+  0.989176509964781010f, -0.146730474455361750f, 0.988721691960323780f,
+  -0.149764534677321510f,
+  0.988257567730749460f, -0.152797185258443440f, 0.987784141644572180f,
+  -0.155828397654265230f,
+  0.987301418157858430f, -0.158858143333861450f, 0.986809401814185530f,
+  -0.161886393780111830f,
+  0.986308097244598670f, -0.164913120489969890f, 0.985797509167567480f,
+  -0.167938294974731170f,
+  0.985277642388941220f, -0.170961888760301220f, 0.984748501801904210f,
+  -0.173983873387463820f,
+  0.984210092386929030f, -0.177004220412148750f, 0.983662419211730250f,
+  -0.180022901405699510f,
+  0.983105487431216290f, -0.183039887955140950f, 0.982539302287441240f,
+  -0.186055151663446630f,
+  0.981963869109555240f, -0.189068664149806190f, 0.981379193313754560f,
+  -0.192080397049892440f,
+  0.980785280403230430f, -0.195090322016128250f, 0.980182135968117430f,
+  -0.198098410717953560f,
+  0.979569765685440520f, -0.201104634842091900f, 0.978948175319062200f,
+  -0.204108966092816870f,
+  0.978317370719627650f, -0.207111376192218560f, 0.977677357824509930f,
+  -0.210111836880469610f,
+  0.977028142657754390f, -0.213110319916091360f, 0.976369731330021140f,
+  -0.216106797076219520f,
+  0.975702130038528570f, -0.219101240156869800f, 0.975025345066994120f,
+  -0.222093620973203510f,
+  0.974339382785575860f, -0.225083911359792830f, 0.973644249650811980f,
+  -0.228072083170885730f,
+  0.972939952205560180f, -0.231058108280671110f, 0.972226497078936270f,
+  -0.234041958583543430f,
+  0.971503890986251780f, -0.237023605994367200f, 0.970772140728950350f,
+  -0.240003022448741500f,
+  0.970031253194543970f, -0.242980179903263870f, 0.969281235356548530f,
+  -0.245955050335794590f,
+  0.968522094274417380f, -0.248927605745720150f, 0.967753837093475510f,
+  -0.251897818154216970f,
+  0.966976471044852070f, -0.254865659604514570f, 0.966190003445412500f,
+  -0.257831102162158990f,
+  0.965394441697689400f, -0.260794117915275510f, 0.964589793289812760f,
+  -0.263754678974831350f,
+  0.963776065795439840f, -0.266712757474898370f, 0.962953266873683880f,
+  -0.269668325572915090f,
+  0.962121404269041580f, -0.272621355449948980f, 0.961280485811320640f,
+  -0.275571819310958140f,
+  0.960430519415565790f, -0.278519689385053060f, 0.959571513081984520f,
+  -0.281464937925757940f,
+  0.958703474895871600f, -0.284407537211271880f, 0.957826413027532910f,
+  -0.287347459544729510f,
+  0.956940335732208820f, -0.290284677254462330f, 0.956045251349996410f,
+  -0.293219162694258630f,
+  0.955141168305770780f, -0.296150888243623790f, 0.954228095109105670f,
+  -0.299079826308040480f,
+  0.953306040354193860f, -0.302005949319228080f, 0.952375012719765880f,
+  -0.304929229735402370f,
+  0.951435020969008340f, -0.307849640041534870f, 0.950486073949481700f,
+  -0.310767152749611470f,
+  0.949528180593036670f, -0.313681740398891520f, 0.948561349915730270f,
+  -0.316593375556165850f,
+  0.947585591017741090f, -0.319502030816015690f, 0.946600913083283530f,
+  -0.322407678801069850f,
+  0.945607325380521280f, -0.325310292162262930f, 0.944604837261480260f,
+  -0.328209843579092500f,
+  0.943593458161960390f, -0.331106305759876430f, 0.942573197601446870f,
+  -0.333999651442009380f,
+  0.941544065183020810f, -0.336889853392220050f, 0.940506070593268300f,
+  -0.339776884406826850f,
+  0.939459223602189920f, -0.342660717311994380f, 0.938403534063108060f,
+  -0.345541324963989090f,
+  0.937339011912574960f, -0.348418680249434560f, 0.936265667170278260f,
+  -0.351292756085567090f,
+  0.935183509938947610f, -0.354163525420490340f, 0.934092550404258980f,
+  -0.357030961233429980f,
+  0.932992798834738960f, -0.359895036534988110f, 0.931884265581668150f,
+  -0.362755724367397230f,
+  0.930766961078983710f, -0.365612997804773850f, 0.929640895843181330f,
+  -0.368466829953372320f,
+  0.928506080473215590f, -0.371317193951837540f, 0.927362525650401110f,
+  -0.374164062971457930f,
+  0.926210242138311380f, -0.377007410216418260f, 0.925049240782677580f,
+  -0.379847208924051160f,
+  0.923879532511286740f, -0.382683432365089780f, 0.922701128333878630f,
+  -0.385516053843918850f,
+  0.921514039342042010f, -0.388345046698826250f, 0.920318276709110590f,
+  -0.391170384302253870f,
+  0.919113851690057770f, -0.393992040061048100f, 0.917900775621390500f,
+  -0.396809987416710310f,
+  0.916679059921042700f, -0.399624199845646790f, 0.915448716088267830f,
+  -0.402434650859418430f,
+  0.914209755703530690f, -0.405241314004989860f, 0.912962190428398210f,
+  -0.408044162864978690f,
+  0.911706032005429880f, -0.410843171057903910f, 0.910441292258067250f,
+  -0.413638312238434500f,
+  0.909167983090522380f, -0.416429560097637150f, 0.907886116487666260f,
+  -0.419216888363223910f,
+  0.906595704514915330f, -0.422000270799799680f, 0.905296759318118820f,
+  -0.424779681209108810f,
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+  -0.996571145790554840f,
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+  -0.997060070339482960f,
+  0.073564563599667454f, -0.997290456678690210f, 0.070504573389614009f,
+  -0.997511456140303450f,
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+  -0.997925286198596000f,
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+  -0.998301544933892890f,
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+  -0.998640218180265270f,
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+  -0.998941293186856870f,
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+  -0.999204758618363890f,
+  0.036807222941358991f, -0.999322384588349540f, 0.033741171851377642f,
+  -0.999430604555461730f,
+  0.030674803176636581f, -0.999529417501093140f, 0.027608145778965820f,
+  -0.999618822495178640f,
+  0.024541228522912264f, -0.999698818696204250f, 0.021474080275469605f,
+  -0.999769405351215280f,
+  0.018406729905804820f, -0.999830581795823400f, 0.015339206284988220f,
+  -0.999882347454212560f,
+  0.012271538285719944f, -0.999924701839144500f, 0.009203754782059960f,
+  -0.999957644551963900f,
+  0.006135884649154515f, -0.999981175282601110f, 0.003067956762966138f,
+  -0.999995293809576190f
+};
+
+static const float32_t Weights_2048[4096] = {
+  1.000000000000000000f, 0.000000000000000000f, 0.999999705862882230f,
+  -0.000766990318742704f,
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+  -0.002300969151425805f,
+  0.999995293809576190f, -0.003067956762965976f, 0.999992646580707190f,
+  -0.003834942569706228f,
+  0.999989411081928400f, -0.004601926120448571f, 0.999985587315143200f,
+  -0.005368906963996343f,
+  0.999981175282601110f, -0.006135884649154475f, 0.999976174986897610f,
+  -0.006902858724729756f,
+  0.999970586430974140f, -0.007669828739531097f, 0.999964409618118280f,
+  -0.008436794242369799f,
+  0.999957644551963900f, -0.009203754782059819f, 0.999950291236490480f,
+  -0.009970709907418031f,
+  0.999942349676023910f, -0.010737659167264491f, 0.999933819875236000f,
+  -0.011504602110422714f,
+  0.999924701839144500f, -0.012271538285719925f, 0.999914995573113470f,
+  -0.013038467241987334f,
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+  -0.014572301692779064f,
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+  -0.016106101853537287f,
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+  -0.017639864115082053f,
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+  -0.022240887414024961f,
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+  -0.054429407010919133f,
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+  0.107172424956808870f, -0.994240449453187900f, 0.106409820634187840f,
+  -0.994322357222545810f,
+  0.105647153713410700f, -0.994403680057679100f, 0.104884424643134970f,
+  -0.994484417910747600f,
+  0.104121633872054730f, -0.994564570734255420f, 0.103358781848899700f,
+  -0.994644138481050710f,
+  0.102595869022436280f, -0.994723121104325700f, 0.101832895841466670f,
+  -0.994801518557617110f,
+  0.101069862754827880f, -0.994879330794805620f, 0.100306770211392820f,
+  -0.994956557770116380f,
+  0.099543618660069444f, -0.995033199438118630f, 0.098780408549799664f,
+  -0.995109255753726110f,
+  0.098017140329560770f, -0.995184726672196820f, 0.097253814448363354f,
+  -0.995259612149133390f,
+  0.096490431355252607f, -0.995333912140482280f, 0.095726991499307315f,
+  -0.995407626602534900f,
+  0.094963495329639061f, -0.995480755491926940f, 0.094199943295393190f,
+  -0.995553298765638470f,
+  0.093436335845747912f, -0.995625256380994310f, 0.092672673429913366f,
+  -0.995696628295663520f,
+  0.091908956497132696f, -0.995767414467659820f, 0.091145185496681130f,
+  -0.995837614855341610f,
+  0.090381360877865011f, -0.995907229417411720f, 0.089617483090022917f,
+  -0.995976258112917790f,
+  0.088853552582524684f, -0.996044700901251970f, 0.088089569804770507f,
+  -0.996112557742151130f,
+  0.087325535206192226f, -0.996179828595696870f, 0.086561449236251239f,
+  -0.996246513422315520f,
+  0.085797312344439880f, -0.996312612182778000f, 0.085033124980280414f,
+  -0.996378124838200210f,
+  0.084268887593324127f, -0.996443051350042630f, 0.083504600633152404f,
+  -0.996507391680110820f,
+  0.082740264549375803f, -0.996571145790554840f, 0.081975879791633108f,
+  -0.996634313643869900f,
+  0.081211446809592386f, -0.996696895202896060f, 0.080446966052950097f,
+  -0.996758890430818000f,
+  0.079682437971430126f, -0.996820299291165670f, 0.078917863014785095f,
+  -0.996881121747813850f,
+  0.078153241632794315f, -0.996941357764982160f, 0.077388574275265049f,
+  -0.997001007307235290f,
+  0.076623861392031617f, -0.997060070339482960f, 0.075859103432954503f,
+  -0.997118546826979980f,
+  0.075094300847921291f, -0.997176436735326190f, 0.074329454086845867f,
+  -0.997233740030466160f,
+  0.073564563599667454f, -0.997290456678690210f, 0.072799629836351618f,
+  -0.997346586646633230f,
+  0.072034653246889416f, -0.997402129901275300f, 0.071269634281296415f,
+  -0.997457086409941910f,
+  0.070504573389614009f, -0.997511456140303450f, 0.069739471021907376f,
+  -0.997565239060375750f,
+  0.068974327628266732f, -0.997618435138519550f, 0.068209143658806454f,
+  -0.997671044343441000f,
+  0.067443919563664106f, -0.997723066644191640f, 0.066678655793001543f,
+  -0.997774502010167820f,
+  0.065913352797003930f, -0.997825350411111640f, 0.065148011025878860f,
+  -0.997875611817110150f,
+  0.064382630929857410f, -0.997925286198596000f, 0.063617212959193190f,
+  -0.997974373526346990f,
+  0.062851757564161420f, -0.998022873771486240f, 0.062086265195060247f,
+  -0.998070786905482340f,
+  0.061320736302208648f, -0.998118112900149180f, 0.060555171335947781f,
+  -0.998164851727646240f,
+  0.059789570746640007f, -0.998211003360478190f, 0.059023934984667986f,
+  -0.998256567771495180f,
+  0.058258264500435732f, -0.998301544933892890f, 0.057492559744367684f,
+  -0.998345934821212370f,
+  0.056726821166907783f, -0.998389737407340160f, 0.055961049218520520f,
+  -0.998432952666508440f,
+  0.055195244349690031f, -0.998475580573294770f, 0.054429407010919147f,
+  -0.998517621102622210f,
+  0.053663537652730679f, -0.998559074229759310f, 0.052897636725665401f,
+  -0.998599939930320370f,
+  0.052131704680283317f, -0.998640218180265270f, 0.051365741967162731f,
+  -0.998679908955899090f,
+  0.050599749036899337f, -0.998719012233872940f, 0.049833726340107257f,
+  -0.998757527991183340f,
+  0.049067674327418126f, -0.998795456205172410f, 0.048301593449480172f,
+  -0.998832796853527990f,
+  0.047535484156959261f, -0.998869549914283560f, 0.046769346900537960f,
+  -0.998905715365818290f,
+  0.046003182130914644f, -0.998941293186856870f, 0.045236990298804750f,
+  -0.998976283356469820f,
+  0.044470771854938744f, -0.999010685854073380f, 0.043704527250063421f,
+  -0.999044500659429290f,
+  0.042938256934940959f, -0.999077727752645360f, 0.042171961360348002f,
+  -0.999110367114174890f,
+  0.041405640977076712f, -0.999142418724816910f, 0.040639296235933854f,
+  -0.999173882565716380f,
+  0.039872927587739845f, -0.999204758618363890f, 0.039106535483329839f,
+  -0.999235046864595850f,
+  0.038340120373552791f, -0.999264747286594420f, 0.037573682709270514f,
+  -0.999293859866887790f,
+  0.036807222941358991f, -0.999322384588349540f, 0.036040741520706299f,
+  -0.999350321434199440f,
+  0.035274238898213947f, -0.999377670388002850f, 0.034507715524795889f,
+  -0.999404431433671300f,
+  0.033741171851377642f, -0.999430604555461730f, 0.032974608328897315f,
+  -0.999456189737977340f,
+  0.032208025408304704f, -0.999481186966166950f, 0.031441423540560343f,
+  -0.999505596225325310f,
+  0.030674803176636581f, -0.999529417501093140f, 0.029908164767516655f,
+  -0.999552650779456990f,
+  0.029141508764193740f, -0.999575296046749220f, 0.028374835617672258f,
+  -0.999597353289648380f,
+  0.027608145778965820f, -0.999618822495178640f, 0.026841439699098527f,
+  -0.999639703650710200f,
+  0.026074717829104040f, -0.999659996743959220f, 0.025307980620024630f,
+  -0.999679701762987930f,
+  0.024541228522912264f, -0.999698818696204250f, 0.023774461988827676f,
+  -0.999717347532362190f,
+  0.023007681468839410f, -0.999735288260561680f, 0.022240887414024919f,
+  -0.999752640870248840f,
+  0.021474080275469605f, -0.999769405351215280f, 0.020707260504265912f,
+  -0.999785581693599210f,
+  0.019940428551514598f, -0.999801169887884260f, 0.019173584868322699f,
+  -0.999816169924900410f,
+  0.018406729905804820f, -0.999830581795823400f, 0.017639864115082195f,
+  -0.999844405492175240f,
+  0.016872987947281773f, -0.999857641005823860f, 0.016106101853537263f,
+  -0.999870288328982950f,
+  0.015339206284988220f, -0.999882347454212560f, 0.014572301692779104f,
+  -0.999893818374418490f,
+  0.013805388528060349f, -0.999904701082852900f, 0.013038467241987433f,
+  -0.999914995573113470f,
+  0.012271538285719944f, -0.999924701839144500f, 0.011504602110422875f,
+  -0.999933819875236000f,
+  0.010737659167264572f, -0.999942349676023910f, 0.009970709907418029f,
+  -0.999950291236490480f,
+  0.009203754782059960f, -0.999957644551963900f, 0.008436794242369860f,
+  -0.999964409618118280f,
+  0.007669828739531077f, -0.999970586430974140f, 0.006902858724729877f,
+  -0.999976174986897610f,
+  0.006135884649154515f, -0.999981175282601110f, 0.005368906963996303f,
+  -0.999985587315143200f,
+  0.004601926120448672f, -0.999989411081928400f, 0.003834942569706248f,
+  -0.999992646580707190f,
+  0.003067956762966138f, -0.999995293809576190f, 0.002300969151425887f,
+  -0.999997352766978210f,
+  0.001533980186284766f, -0.999998823451701880f, 0.000766990318742846f,
+  -0.999999705862882230f
+};
+
+/**   
+* \par   
+* cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
   
+* \par   
+* C command to generate the table   
+* \par   
+* 
 for(i = 0; i< N; i++)   
+* {   
+*    cos_factors[i]= 2 * cos((2*i+1)*c/2);   
+* } 
   
+* \par   
+* where N is the number of factors to generate and c is pi/(2*N)   
+*/
+static const float32_t cos_factors_128[128] = {
+  0.999981175282601110f, 0.999830581795823400f, 0.999529417501093140f,
+  0.999077727752645360f,
+  0.998475580573294770f, 0.997723066644191640f, 0.996820299291165670f,
+  0.995767414467659820f,
+  0.994564570734255420f, 0.993211949234794500f, 0.991709753669099530f,
+  0.990058210262297120f,
+  0.988257567730749460f, 0.986308097244598670f, 0.984210092386929030f,
+  0.981963869109555240f,
+  0.979569765685440520f, 0.977028142657754390f, 0.974339382785575860f,
+  0.971503890986251780f,
+  0.968522094274417380f, 0.965394441697689400f, 0.962121404269041580f,
+  0.958703474895871600f,
+  0.955141168305770780f, 0.951435020969008340f, 0.947585591017741090f,
+  0.943593458161960390f,
+  0.939459223602189920f, 0.935183509938947610f, 0.930766961078983710f,
+  0.926210242138311380f,
+  0.921514039342042010f, 0.916679059921042700f, 0.911706032005429880f,
+  0.906595704514915330f,
+  0.901348847046022030f, 0.895966249756185220f, 0.890448723244757880f,
+  0.884797098430937790f,
+  0.879012226428633530f, 0.873094978418290090f, 0.867046245515692650f,
+  0.860866938637767310f,
+  0.854557988365400530f, 0.848120344803297230f, 0.841554977436898440f,
+  0.834862874986380010f,
+  0.828045045257755800f, 0.821102514991104650f, 0.814036329705948410f,
+  0.806847553543799330f,
+  0.799537269107905010f, 0.792106577300212390f, 0.784556597155575240f,
+  0.776888465673232440f,
+  0.769103337645579700f, 0.761202385484261780f, 0.753186799043612520f,
+  0.745057785441466060f,
+  0.736816568877369900f, 0.728464390448225200f, 0.720002507961381650f,
+  0.711432195745216430f,
+  0.702754744457225300f, 0.693971460889654000f, 0.685083667772700360f,
+  0.676092703575316030f,
+  0.666999922303637470f, 0.657806693297078640f, 0.648514401022112550f,
+  0.639124444863775730f,
+  0.629638238914927100f, 0.620057211763289210f, 0.610382806276309480f,
+  0.600616479383868970f,
+  0.590759701858874280f, 0.580813958095764530f, 0.570780745886967370f,
+  0.560661576197336030f,
+  0.550457972936604810f, 0.540171472729892970f, 0.529803624686294830f,
+  0.519355990165589530f,
+  0.508830142543106990f, 0.498227666972781870f, 0.487550160148436050f,
+  0.476799230063322250f,
+  0.465976495767966130f, 0.455083587126343840f, 0.444122144570429260f,
+  0.433093818853152010f,
+  0.422000270799799790f, 0.410843171057903910f, 0.399624199845646790f,
+  0.388345046698826300f,
+  0.377007410216418310f, 0.365612997804773960f, 0.354163525420490510f,
+  0.342660717311994380f,
+  0.331106305759876430f, 0.319502030816015750f, 0.307849640041534980f,
+  0.296150888243623960f,
+  0.284407537211271820f, 0.272621355449948980f, 0.260794117915275570f,
+  0.248927605745720260f,
+  0.237023605994367340f, 0.225083911359792780f, 0.213110319916091360f,
+  0.201104634842091960f,
+  0.189068664149806280f, 0.177004220412148860f, 0.164913120489970090f,
+  0.152797185258443410f,
+  0.140658239332849240f, 0.128498110793793220f, 0.116318630911904880f,
+  0.104121633872054730f,
+  0.091908956497132696f, 0.079682437971430126f, 0.067443919563664106f,
+  0.055195244349690031f,
+  0.042938256934940959f, 0.030674803176636581f, 0.018406729905804820f,
+  0.006135884649154515f
+};
+
+static const float32_t cos_factors_512[512] = {
+  0.999998823451701880f, 0.999989411081928400f, 0.999970586430974140f,
+  0.999942349676023910f,
+  0.999904701082852900f, 0.999857641005823860f, 0.999801169887884260f,
+  0.999735288260561680f,
+  0.999659996743959220f, 0.999575296046749220f, 0.999481186966166950f,
+  0.999377670388002850f,
+  0.999264747286594420f, 0.999142418724816910f, 0.999010685854073380f,
+  0.998869549914283560f,
+  0.998719012233872940f, 0.998559074229759310f, 0.998389737407340160f,
+  0.998211003360478190f,
+  0.998022873771486240f, 0.997825350411111640f, 0.997618435138519550f,
+  0.997402129901275300f,
+  0.997176436735326190f, 0.996941357764982160f, 0.996696895202896060f,
+  0.996443051350042630f,
+  0.996179828595696980f, 0.995907229417411720f, 0.995625256380994310f,
+  0.995333912140482280f,
+  0.995033199438118630f, 0.994723121104325700f, 0.994403680057679100f,
+  0.994074879304879370f,
+  0.993736721940724600f, 0.993389211148080650f, 0.993032350197851410f,
+  0.992666142448948020f,
+  0.992290591348257370f, 0.991905700430609330f, 0.991511473318743900f,
+  0.991107913723276890f,
+  0.990695025442664630f, 0.990272812363169110f, 0.989841278458820530f,
+  0.989400427791380380f,
+  0.988950264510302990f, 0.988490792852696590f, 0.988022017143283530f,
+  0.987543941794359230f,
+  0.987056571305750970f, 0.986559910264775410f, 0.986053963346195440f,
+  0.985538735312176060f,
+  0.985014231012239840f, 0.984480455383220930f, 0.983937413449218920f,
+  0.983385110321551180f,
+  0.982823551198705240f, 0.982252741366289370f, 0.981672686196983110f,
+  0.981083391150486710f,
+  0.980484861773469380f, 0.979877103699517640f, 0.979260122649082020f,
+  0.978633924429423210f,
+  0.977998514934557140f, 0.977353900145199960f, 0.976700086128711840f,
+  0.976037079039039020f,
+  0.975364885116656980f, 0.974683510688510670f, 0.973992962167955830f,
+  0.973293246054698250f,
+  0.972584368934732210f, 0.971866337480279400f, 0.971139158449725090f,
+  0.970402838687555500f,
+  0.969657385124292450f, 0.968902804776428870f, 0.968139104746362440f,
+  0.967366292222328510f,
+  0.966584374478333120f, 0.965793358874083680f, 0.964993252854920320f,
+  0.964184063951745830f,
+  0.963365799780954050f, 0.962538468044359160f, 0.961702076529122540f,
+  0.960856633107679660f,
+  0.960002145737665960f, 0.959138622461841890f, 0.958266071408017670f,
+  0.957384500788975860f,
+  0.956493918902395100f, 0.955594334130771110f, 0.954685754941338340f,
+  0.953768189885990330f,
+  0.952841647601198720f, 0.951906136807932350f, 0.950961666311575080f,
+  0.950008245001843000f,
+  0.949045881852700560f, 0.948074585922276230f, 0.947094366352777220f,
+  0.946105232370403450f,
+  0.945107193285260610f, 0.944100258491272660f, 0.943084437466093490f,
+  0.942059739771017310f,
+  0.941026175050889260f, 0.939983753034014050f, 0.938932483532064600f,
+  0.937872376439989890f,
+  0.936803441735921560f, 0.935725689481080370f, 0.934639129819680780f,
+  0.933543772978836170f,
+  0.932439629268462360f, 0.931326709081180430f, 0.930205022892219070f,
+  0.929074581259315860f,
+  0.927935394822617890f, 0.926787474304581750f, 0.925630830509872720f,
+  0.924465474325262600f,
+  0.923291416719527640f, 0.922108668743345180f, 0.920917241529189520f,
+  0.919717146291227360f,
+  0.918508394325212250f, 0.917290997008377910f, 0.916064965799331720f,
+  0.914830312237946200f,
+  0.913587047945250810f, 0.912335184623322750f, 0.911074734055176360f,
+  0.909805708104652220f,
+  0.908528118716306120f, 0.907241977915295820f, 0.905947297807268460f,
+  0.904644090578246240f,
+  0.903332368494511820f, 0.902012143902493180f, 0.900683429228646970f,
+  0.899346236979341570f,
+  0.898000579740739880f, 0.896646470178680150f, 0.895283921038557580f,
+  0.893912945145203250f,
+  0.892533555402764580f, 0.891145764794583180f, 0.889749586383072780f,
+  0.888345033309596350f,
+  0.886932118794342190f, 0.885510856136199950f, 0.884081258712634990f,
+  0.882643339979562790f,
+  0.881197113471222090f, 0.879742592800047410f, 0.878279791656541580f,
+  0.876808723809145650f,
+  0.875329403104110890f, 0.873841843465366860f, 0.872346058894391540f,
+  0.870842063470078980f,
+  0.869329871348606840f, 0.867809496763303320f, 0.866280954024512990f,
+  0.864744257519462380f,
+  0.863199421712124160f, 0.861646461143081300f, 0.860085390429390140f,
+  0.858516224264442740f,
+  0.856938977417828760f, 0.855353664735196030f, 0.853760301138111410f,
+  0.852158901623919830f,
+  0.850549481265603480f, 0.848932055211639610f, 0.847306638685858320f,
+  0.845673246987299070f,
+  0.844031895490066410f, 0.842382599643185850f, 0.840725374970458070f,
+  0.839060237070312740f,
+  0.837387201615661940f, 0.835706284353752600f, 0.834017501106018130f,
+  0.832320867767929680f,
+  0.830616400308846310f, 0.828904114771864870f, 0.827184027273669130f,
+  0.825456154004377550f,
+  0.823720511227391430f, 0.821977115279241550f, 0.820225982569434690f,
+  0.818467129580298660f,
+  0.816700572866827850f, 0.814926329056526620f, 0.813144414849253590f,
+  0.811354847017063730f,
+  0.809557642404051260f, 0.807752817926190360f, 0.805940390571176280f,
+  0.804120377398265810f,
+  0.802292795538115720f, 0.800457662192622820f, 0.798614994634760820f,
+  0.796764810208418830f,
+  0.794907126328237010f, 0.793041960479443640f, 0.791169330217690200f,
+  0.789289253168885650f,
+  0.787401747029031430f, 0.785506829564053930f, 0.783604518609638200f,
+  0.781694832071059390f,
+  0.779777787923014550f, 0.777853404209453150f, 0.775921699043407690f,
+  0.773982690606822900f,
+  0.772036397150384520f, 0.770082836993347900f, 0.768122028523365420f,
+  0.766153990196312920f,
+  0.764178740536116670f, 0.762196298134578900f, 0.760206681651202420f,
+  0.758209909813015280f,
+  0.756206001414394540f, 0.754194975316889170f, 0.752176850449042810f,
+  0.750151645806215070f,
+  0.748119380450403600f, 0.746080073510063780f, 0.744033744179929290f,
+  0.741980411720831070f,
+  0.739920095459516200f, 0.737852814788465980f, 0.735778589165713590f,
+  0.733697438114660370f,
+  0.731609381223892630f, 0.729514438146997010f, 0.727412628602375770f,
+  0.725303972373060770f,
+  0.723188489306527460f, 0.721066199314508110f, 0.718937122372804490f,
+  0.716801278521099540f,
+  0.714658687862769090f, 0.712509370564692320f, 0.710353346857062420f,
+  0.708190637033195400f,
+  0.706021261449339740f, 0.703845240524484940f, 0.701662594740168570f,
+  0.699473344640283770f,
+  0.697277510830886630f, 0.695075113980000880f, 0.692866174817424740f,
+  0.690650714134534720f,
+  0.688428752784090550f, 0.686200311680038700f, 0.683965411797315510f,
+  0.681724074171649820f,
+  0.679476319899365080f, 0.677222170137180450f, 0.674961646102012040f,
+  0.672694769070772970f,
+  0.670421560380173090f, 0.668142041426518560f, 0.665856233665509720f,
+  0.663564158612039880f,
+  0.661265837839992270f, 0.658961292982037320f, 0.656650545729429050f,
+  0.654333617831800550f,
+  0.652010531096959500f, 0.649681307390683190f, 0.647345968636512060f,
+  0.645004536815544040f,
+  0.642657033966226860f, 0.640303482184151670f, 0.637943903621844170f,
+  0.635578320488556230f,
+  0.633206755050057190f, 0.630829229628424470f, 0.628445766601832710f,
+  0.626056388404343520f,
+  0.623661117525694640f, 0.621259976511087660f, 0.618852987960976320f,
+  0.616440174530853650f,
+  0.614021558931038490f, 0.611597163926462020f, 0.609167012336453210f,
+  0.606731127034524480f,
+  0.604289530948156070f, 0.601842247058580030f, 0.599389298400564540f,
+  0.596930708062196500f,
+  0.594466499184664540f, 0.591996694962040990f, 0.589521318641063940f,
+  0.587040393520918080f,
+  0.584553942953015330f, 0.582061990340775550f, 0.579564559139405740f,
+  0.577061672855679550f,
+  0.574553355047715760f, 0.572039629324757050f, 0.569520519346947250f,
+  0.566996048825108680f,
+  0.564466241520519500f, 0.561931121244689470f, 0.559390711859136140f,
+  0.556845037275160100f,
+  0.554294121453620110f, 0.551737988404707450f, 0.549176662187719770f,
+  0.546610166910834860f,
+  0.544038526730883930f, 0.541461765853123560f, 0.538879908531008420f,
+  0.536292979065963180f,
+  0.533701001807152960f, 0.531104001151255000f, 0.528502001542228480f,
+  0.525895027471084740f,
+  0.523283103475656430f, 0.520666254140367270f, 0.518044504095999340f,
+  0.515417878019463150f,
+  0.512786400633563070f, 0.510150096706766700f, 0.507508991052970870f,
+  0.504863108531267480f,
+  0.502212474045710900f, 0.499557112545081890f, 0.496897049022654640f,
+  0.494232308515959730f,
+  0.491562916106550060f, 0.488888896919763230f, 0.486210276124486530f,
+  0.483527078932918740f,
+  0.480839330600333900f, 0.478147056424843120f, 0.475450281747155870f,
+  0.472749031950342900f,
+  0.470043332459595620f, 0.467333208741988530f, 0.464618686306237820f,
+  0.461899790702462840f,
+  0.459176547521944150f, 0.456448982396883860f, 0.453717121000163930f,
+  0.450980989045103810f,
+  0.448240612285220000f, 0.445496016513981740f, 0.442747227564570130f,
+  0.439994271309633260f,
+  0.437237173661044200f, 0.434475960569655710f, 0.431710658025057370f,
+  0.428941292055329550f,
+  0.426167888726799620f, 0.423390474143796100f, 0.420609074448402510f,
+  0.417823715820212380f,
+  0.415034424476081630f, 0.412241226669883000f, 0.409444148692257590f,
+  0.406643216870369140f,
+  0.403838457567654130f, 0.401029897183575790f, 0.398217562153373620f,
+  0.395401478947816300f,
+  0.392581674072951530f, 0.389758174069856410f, 0.386931005514388690f,
+  0.384100195016935040f,
+  0.381265769222162490f, 0.378427754808765620f, 0.375586178489217330f,
+  0.372741067009515810f,
+  0.369892447148934270f, 0.367040345719767240f, 0.364184789567079840f,
+  0.361325805568454340f,
+  0.358463420633736540f, 0.355597661704783960f, 0.352728555755210730f,
+  0.349856129790135030f,
+  0.346980410845923680f, 0.344101425989938980f, 0.341219202320282410f,
+  0.338333766965541290f,
+  0.335445147084531660f, 0.332553369866044220f, 0.329658462528587550f,
+  0.326760452320131790f,
+  0.323859366517852960f, 0.320955232427875210f, 0.318048077385015060f,
+  0.315137928752522440f,
+  0.312224813921825050f, 0.309308760312268780f, 0.306389795370861080f,
+  0.303467946572011370f,
+  0.300543241417273400f, 0.297615707435086310f, 0.294685372180514330f,
+  0.291752263234989370f,
+  0.288816408206049480f, 0.285877834727080730f, 0.282936570457055390f,
+  0.279992643080273380f,
+  0.277046080306099950f, 0.274096909868706330f, 0.271145159526808070f,
+  0.268190857063403180f,
+  0.265234030285511900f, 0.262274707023913590f, 0.259312915132886350f,
+  0.256348682489942910f,
+  0.253382036995570270f, 0.250413006572965280f, 0.247441619167773440f,
+  0.244467902747824210f,
+  0.241491885302869300f, 0.238513594844318500f, 0.235533059404975460f,
+  0.232550307038775330f,
+  0.229565365820518870f, 0.226578263845610110f, 0.223589029229790020f,
+  0.220597690108873650f,
+  0.217604274638483670f, 0.214608810993786920f, 0.211611327369227610f,
+  0.208611851978263460f,
+  0.205610413053099320f, 0.202607038844421110f, 0.199601757621131050f,
+  0.196594597670080220f,
+  0.193585587295803750f, 0.190574754820252800f, 0.187562128582529740f,
+  0.184547736938619640f,
+  0.181531608261125130f, 0.178513770938997590f, 0.175494253377271400f,
+  0.172473083996796030f,
+  0.169450291233967930f, 0.166425903540464220f, 0.163399949382973230f,
+  0.160372457242928400f,
+  0.157343455616238280f, 0.154312973013020240f, 0.151281037957330250f,
+  0.148247678986896200f,
+  0.145212924652847520f, 0.142176803519448000f, 0.139139344163826280f,
+  0.136100575175706200f,
+  0.133060525157139180f, 0.130019222722233350f, 0.126976696496885980f,
+  0.123932975118512200f,
+  0.120888087235777220f, 0.117842061508325020f, 0.114794926606510250f,
+  0.111746711211126660f,
+  0.108697444013138670f, 0.105647153713410700f, 0.102595869022436280f,
+  0.099543618660069444f,
+  0.096490431355252607f, 0.093436335845747912f, 0.090381360877865011f,
+  0.087325535206192226f,
+  0.084268887593324127f, 0.081211446809592386f, 0.078153241632794315f,
+  0.075094300847921291f,
+  0.072034653246889416f, 0.068974327628266732f, 0.065913352797003930f,
+  0.062851757564161420f,
+  0.059789570746640007f, 0.056726821166907783f, 0.053663537652730679f,
+  0.050599749036899337f,
+  0.047535484156959261f, 0.044470771854938744f, 0.041405640977076712f,
+  0.038340120373552791f,
+  0.035274238898213947f, 0.032208025408304704f, 0.029141508764193740f,
+  0.026074717829104040f,
+  0.023007681468839410f, 0.019940428551514598f, 0.016872987947281773f,
+  0.013805388528060349f,
+  0.010737659167264572f, 0.007669828739531077f, 0.004601926120448672f,
+  0.001533980186284766f
+};
+
+static const float32_t cos_factors_2048[2048] = {
+  0.999999926465717890f, 0.999999338191525530f, 0.999998161643486980f,
+  0.999996396822294350f,
+  0.999994043728985820f, 0.999991102364945590f, 0.999987572731904080f,
+  0.999983454831937730f,
+  0.999978748667468830f, 0.999973454241265940f, 0.999967571556443780f,
+  0.999961100616462820f,
+  0.999954041425129780f, 0.999946393986597460f, 0.999938158305364590f,
+  0.999929334386276070f,
+  0.999919922234522750f, 0.999909921855641540f, 0.999899333255515390f,
+  0.999888156440373320f,
+  0.999876391416790410f, 0.999864038191687680f, 0.999851096772332190f,
+  0.999837567166337090f,
+  0.999823449381661570f, 0.999808743426610520f, 0.999793449309835270f,
+  0.999777567040332940f,
+  0.999761096627446610f, 0.999744038080865430f, 0.999726391410624470f,
+  0.999708156627104880f,
+  0.999689333741033640f, 0.999669922763483760f, 0.999649923705874240f,
+  0.999629336579970110f,
+  0.999608161397882110f, 0.999586398172067070f, 0.999564046915327740f,
+  0.999541107640812940f,
+  0.999517580362016990f, 0.999493465092780590f, 0.999468761847290050f,
+  0.999443470640077770f,
+  0.999417591486021720f, 0.999391124400346050f, 0.999364069398620550f,
+  0.999336426496761240f,
+  0.999308195711029470f, 0.999279377058032710f, 0.999249970554724420f,
+  0.999219976218403530f,
+  0.999189394066714920f, 0.999158224117649430f, 0.999126466389543390f,
+  0.999094120901079070f,
+  0.999061187671284600f, 0.999027666719533690f, 0.998993558065545680f,
+  0.998958861729386080f,
+  0.998923577731465780f, 0.998887706092541290f, 0.998851246833715180f,
+  0.998814199976435390f,
+  0.998776565542495610f, 0.998738343554035230f, 0.998699534033539280f,
+  0.998660137003838490f,
+  0.998620152488108870f, 0.998579580509872500f, 0.998538421092996730f,
+  0.998496674261694640f,
+  0.998454340040524800f, 0.998411418454391300f, 0.998367909528543820f,
+  0.998323813288577560f,
+  0.998279129760433200f, 0.998233858970396850f, 0.998188000945100300f,
+  0.998141555711520520f,
+  0.998094523296980010f, 0.998046903729146840f, 0.997998697036034390f,
+  0.997949903246001190f,
+  0.997900522387751620f, 0.997850554490335110f, 0.997799999583146470f,
+  0.997748857695925690f,
+  0.997697128858758500f, 0.997644813102075420f, 0.997591910456652630f,
+  0.997538420953611340f,
+  0.997484344624417930f, 0.997429681500884180f, 0.997374431615167150f,
+  0.997318594999768600f,
+  0.997262171687536170f, 0.997205161711661850f, 0.997147565105683480f,
+  0.997089381903483400f,
+  0.997030612139289450f, 0.996971255847674320f, 0.996911313063555740f,
+  0.996850783822196610f,
+  0.996789668159204560f, 0.996727966110532490f, 0.996665677712478160f,
+  0.996602803001684130f,
+  0.996539342015137940f, 0.996475294790172160f, 0.996410661364464100f,
+  0.996345441776035900f,
+  0.996279636063254650f, 0.996213244264832040f, 0.996146266419824620f,
+  0.996078702567633980f,
+  0.996010552748005870f, 0.995941817001031350f, 0.995872495367145730f,
+  0.995802587887129160f,
+  0.995732094602106430f, 0.995661015553546910f, 0.995589350783264600f,
+  0.995517100333418110f,
+  0.995444264246510340f, 0.995370842565388990f, 0.995296835333246090f,
+  0.995222242593618360f,
+  0.995147064390386470f, 0.995071300767776170f, 0.994994951770357020f,
+  0.994918017443043200f,
+  0.994840497831093180f, 0.994762392980109930f, 0.994683702936040250f,
+  0.994604427745175660f,
+  0.994524567454151740f, 0.994444122109948040f, 0.994363091759888570f,
+  0.994281476451641550f,
+  0.994199276233218910f, 0.994116491152977070f, 0.994033121259616400f,
+  0.993949166602181130f,
+  0.993864627230059750f, 0.993779503192984580f, 0.993693794541031790f,
+  0.993607501324621610f,
+  0.993520623594518090f, 0.993433161401829360f, 0.993345114798006910f,
+  0.993256483834846440f,
+  0.993167268564487230f, 0.993077469039412300f, 0.992987085312448390f,
+  0.992896117436765980f,
+  0.992804565465879140f, 0.992712429453645460f, 0.992619709454266140f,
+  0.992526405522286100f,
+  0.992432517712593660f, 0.992338046080420420f, 0.992242990681341700f,
+  0.992147351571276090f,
+  0.992051128806485720f, 0.991954322443575950f, 0.991856932539495470f,
+  0.991758959151536110f,
+  0.991660402337333210f, 0.991561262154865290f, 0.991461538662453790f,
+  0.991361231918763460f,
+  0.991260341982802440f, 0.991158868913921350f, 0.991056812771814340f,
+  0.990954173616518500f,
+  0.990850951508413620f, 0.990747146508222710f, 0.990642758677011570f,
+  0.990537788076188750f,
+  0.990432234767505970f, 0.990326098813057330f, 0.990219380275280000f,
+  0.990112079216953770f,
+  0.990004195701200910f, 0.989895729791486660f, 0.989786681551618640f,
+  0.989677051045747210f,
+  0.989566838338365120f, 0.989456043494307710f, 0.989344666578752640f,
+  0.989232707657220050f,
+  0.989120166795572690f, 0.989007044060015270f, 0.988893339517095130f,
+  0.988779053233701520f,
+  0.988664185277066230f, 0.988548735714763200f, 0.988432704614708340f,
+  0.988316092045159690f,
+  0.988198898074717610f, 0.988081122772324070f, 0.987962766207263420f,
+  0.987843828449161740f,
+  0.987724309567986960f, 0.987604209634049160f, 0.987483528717999710f,
+  0.987362266890832400f,
+  0.987240424223882250f, 0.987118000788826280f, 0.986994996657682980f,
+  0.986871411902812470f,
+  0.986747246596916590f, 0.986622500813038480f, 0.986497174624562880f,
+  0.986371268105216030f,
+  0.986244781329065460f, 0.986117714370520090f, 0.985990067304330140f,
+  0.985861840205586980f,
+  0.985733033149723490f, 0.985603646212513400f, 0.985473679470071810f,
+  0.985343132998854790f,
+  0.985212006875659350f, 0.985080301177623800f, 0.984948015982227030f,
+  0.984815151367289140f,
+  0.984681707410970940f, 0.984547684191773960f, 0.984413081788540700f,
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+  0.036423984909444228f, 0.035657492831508264f, 0.034890979777187955f,
+  0.034124446197403423f,
+  0.033357892543086159f, 0.032591319265180385f, 0.031824726814640963f,
+  0.031058115642434700f,
+  0.030291486199539423f, 0.029524838936943035f, 0.028758174305644590f,
+  0.027991492756653365f,
+  0.027224794740987910f, 0.026458080709677145f, 0.025691351113759395f,
+  0.024924606404281485f,
+  0.024157847032300020f, 0.023391073448879338f, 0.022624286105092803f,
+  0.021857485452021874f,
+  0.021090671940755180f, 0.020323846022389572f, 0.019557008148029204f,
+  0.018790158768784596f,
+  0.018023298335773701f, 0.017256427300120978f, 0.016489546112956454f,
+  0.015722655225417017f,
+  0.014955755088644378f, 0.014188846153786343f, 0.013421928871995907f,
+  0.012655003694430301f,
+  0.011888071072252072f, 0.011121131456628141f, 0.010354185298728884f,
+  0.009587233049729183f,
+  0.008820275160807512f, 0.008053312083144991f, 0.007286344267926684f,
+  0.006519372166339549f,
+  0.005752396229573737f, 0.004985416908821652f, 0.004218434655277024f,
+  0.003451449920135975f,
+  0.002684463154596083f, 0.001917474809855460f, 0.001150485337113809f,
+  0.000383495187571497f
+};
+
+/**   
+ * @brief  Initialization function for the floating-point DCT4/IDCT4.  
+ * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.  
+ * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.  
+ * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.  
+ * @param[in]     N			 length of the DCT4.  
+ * @param[in]     Nby2       half of the length of the DCT4.  
+ * @param[in]     normalize  normalizing factor.  
+ * @return        arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.  
+ * \par Normalizing factor:   
+ * The normalizing factor is sqrt(2/N), which depends on the size of transform N.   
+ * Floating-point normalizing factors are mentioned in the table below for different DCT sizes:   
+ * \image html dct4NormalizingF32Table.gif   
+ */
+
+arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize)
+{
+  /*  Initialize the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /* Initializing the pointer array with the weight table base addresses of different lengths */
+  float32_t *twiddlePtr[3] =
+    { (float32_t *) Weights_128, (float32_t *) Weights_512,
+    (float32_t *) Weights_2048
+  };
+
+  /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+  float32_t *pCosFactor[3] =
+    { (float32_t *) cos_factors_128, (float32_t *) cos_factors_512,
+    (float32_t *) cos_factors_2048
+  };
+
+  /* Initialize the DCT4 length */
+  S->N = N;
+
+  /* Initialize the half of DCT4 length */
+  S->Nby2 = Nby2;
+
+  /* Initialize the DCT4 Normalizing factor */
+  S->normalize = normalize;
+
+  /* Initialize Real FFT Instance */
+  S->pRfft = S_RFFT;
+
+  /* Initialize Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  switch (N)
+  {
+    /* Initialize the table modifier values */
+  case 2048u:
+    S->pTwiddle = twiddlePtr[2];
+    S->pCosFactor = pCosFactor[2];
+    break;
+  case 512u:
+    S->pTwiddle = twiddlePtr[1];
+    S->pCosFactor = pCosFactor[1];
+    break;
+  case 128u:
+    S->pTwiddle = twiddlePtr[0];
+    S->pCosFactor = pCosFactor[0];
+    break;
+  default:
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+
+  /* Initialize the RFFT/RIFFT */
+  arm_rfft_init_f32(S->pRfft, S->pCfft, S->N, 0u, 1u);
+
+  /* return the status of DCT4 Init function */
+  return (status);
+}
+
+/**   
+   * @} end of DCT4_IDCT4 group   
+   */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c
new file mode 100644
index 000000000..260f1b77f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c
@@ -0,0 +1,1190 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_dct4_init_q15.c   
+*   
+* Description:	Initialization function of DCT-4 & IDCT4 Q15   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup DCT4_IDCT4   
+ * @{   
+ */
+
+/*   
+* @brief  Weights Table   
+*/
+
+/**   
+* \par   
+* Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
   
+* \par   
+* C command to generate the table   
+* 
   
+* for(i = 0; i< N; i++)   
+* {   
+*   weights[2*i]= cos(i*c);   
+*   weights[(2*i)+1]= -sin(i * c);   
+* } 
   
+* \par   
+* where N is the Number of weights to be calculated and c is pi/(2*N)   
+* \par   
+* Converted the output to q15 format by multiplying with 2^31 and saturated if required.   
+* \par   
+* In the tables below the real and imaginary values are placed alternatively, hence the   
+* array length is 2*N.   
+*/
+
+static const q15_t WeightsQ15_128[256] = {
+  0x7fff, 0x0, 0x7ffd, 0xfe6e, 0x7ff6, 0xfcdc, 0x7fe9, 0xfb4a,
+  0x7fd8, 0xf9b9, 0x7fc2, 0xf827, 0x7fa7, 0xf696, 0x7f87, 0xf505,
+  0x7f62, 0xf375, 0x7f38, 0xf1e5, 0x7f09, 0xf055, 0x7ed5, 0xeec7,
+  0x7e9d, 0xed38, 0x7e5f, 0xebab, 0x7e1d, 0xea1e, 0x7dd6, 0xe893,
+  0x7d8a, 0xe708, 0x7d39, 0xe57e, 0x7ce3, 0xe3f5, 0x7c89, 0xe26d,
+  0x7c29, 0xe0e7, 0x7bc5, 0xdf61, 0x7b5d, 0xdddd, 0x7aef, 0xdc5a,
+  0x7a7d, 0xdad8, 0x7a05, 0xd958, 0x798a, 0xd7da, 0x7909, 0xd65d,
+  0x7884, 0xd4e1, 0x77fa, 0xd368, 0x776c, 0xd1ef, 0x76d9, 0xd079,
+  0x7641, 0xcf05, 0x75a5, 0xcd92, 0x7504, 0xcc22, 0x745f, 0xcab3,
+  0x73b5, 0xc946, 0x7307, 0xc7dc, 0x7255, 0xc674, 0x719e, 0xc50e,
+  0x70e2, 0xc3aa, 0x7023, 0xc248, 0x6f5f, 0xc0e9, 0x6e96, 0xbf8d,
+  0x6dca, 0xbe32, 0x6cf9, 0xbcdb, 0x6c24, 0xbb86, 0x6b4a, 0xba33,
+  0x6a6d, 0xb8e4, 0x698c, 0xb797, 0x68a6, 0xb64c, 0x67bd, 0xb505,
+  0x66cf, 0xb3c1, 0x65dd, 0xb27f, 0x64e8, 0xb141, 0x63ef, 0xb005,
+  0x62f2, 0xaecd, 0x61f1, 0xad97, 0x60ec, 0xac65, 0x5fe3, 0xab36,
+  0x5ed7, 0xaa0b, 0x5dc7, 0xa8e3, 0x5cb4, 0xa7be, 0x5b9d, 0xa69c,
+  0x5a82, 0xa57e, 0x5964, 0xa463, 0x5842, 0xa34c, 0x571d, 0xa239,
+  0x55f5, 0xa129, 0x54ca, 0xa01d, 0x539b, 0x9f14, 0x5269, 0x9e0f,
+  0x5133, 0x9d0e, 0x4ffb, 0x9c11, 0x4ebf, 0x9b18, 0x4d81, 0x9a23,
+  0x4c3f, 0x9931, 0x4afb, 0x9843, 0x49b4, 0x975a, 0x4869, 0x9674,
+  0x471c, 0x9593, 0x45cd, 0x94b6, 0x447a, 0x93dc, 0x4325, 0x9307,
+  0x41ce, 0x9236, 0x4073, 0x916a, 0x3f17, 0x90a1, 0x3db8, 0x8fdd,
+  0x3c56, 0x8f1e, 0x3af2, 0x8e62, 0x398c, 0x8dab, 0x3824, 0x8cf9,
+  0x36ba, 0x8c4b, 0x354d, 0x8ba1, 0x33de, 0x8afc, 0x326e, 0x8a5b,
+  0x30fb, 0x89bf, 0x2f87, 0x8927, 0x2e11, 0x8894, 0x2c98, 0x8806,
+  0x2b1f, 0x877c, 0x29a3, 0x86f7, 0x2826, 0x8676, 0x26a8, 0x85fb,
+  0x2528, 0x8583, 0x23a6, 0x8511, 0x2223, 0x84a3, 0x209f, 0x843b,
+  0x1f19, 0x83d7, 0x1d93, 0x8377, 0x1c0b, 0x831d, 0x1a82, 0x82c7,
+  0x18f8, 0x8276, 0x176d, 0x822a, 0x15e2, 0x81e3, 0x1455, 0x81a1,
+  0x12c8, 0x8163, 0x1139, 0x812b, 0xfab, 0x80f7, 0xe1b, 0x80c8,
+  0xc8b, 0x809e, 0xafb, 0x8079, 0x96a, 0x8059, 0x7d9, 0x803e,
+  0x647, 0x8028, 0x4b6, 0x8017, 0x324, 0x800a, 0x192, 0x8003,
+};
+
+static const q15_t WeightsQ15_512[1024] = {
+  0x7fff, 0x0, 0x7fff, 0xff9c, 0x7fff, 0xff37, 0x7ffe, 0xfed3,
+  0x7ffd, 0xfe6e, 0x7ffc, 0xfe0a, 0x7ffa, 0xfda5, 0x7ff8, 0xfd41,
+  0x7ff6, 0xfcdc, 0x7ff3, 0xfc78, 0x7ff0, 0xfc13, 0x7fed, 0xfbaf,
+  0x7fe9, 0xfb4a, 0x7fe5, 0xfae6, 0x7fe1, 0xfa81, 0x7fdd, 0xfa1d,
+  0x7fd8, 0xf9b9, 0x7fd3, 0xf954, 0x7fce, 0xf8f0, 0x7fc8, 0xf88b,
+  0x7fc2, 0xf827, 0x7fbc, 0xf7c3, 0x7fb5, 0xf75e, 0x7fae, 0xf6fa,
+  0x7fa7, 0xf696, 0x7f9f, 0xf632, 0x7f97, 0xf5cd, 0x7f8f, 0xf569,
+  0x7f87, 0xf505, 0x7f7e, 0xf4a1, 0x7f75, 0xf43d, 0x7f6b, 0xf3d9,
+  0x7f62, 0xf375, 0x7f58, 0xf311, 0x7f4d, 0xf2ad, 0x7f43, 0xf249,
+  0x7f38, 0xf1e5, 0x7f2d, 0xf181, 0x7f21, 0xf11d, 0x7f15, 0xf0b9,
+  0x7f09, 0xf055, 0x7efd, 0xeff2, 0x7ef0, 0xef8e, 0x7ee3, 0xef2a,
+  0x7ed5, 0xeec7, 0x7ec8, 0xee63, 0x7eba, 0xedff, 0x7eab, 0xed9c,
+  0x7e9d, 0xed38, 0x7e8e, 0xecd5, 0x7e7f, 0xec72, 0x7e6f, 0xec0e,
+  0x7e5f, 0xebab, 0x7e4f, 0xeb48, 0x7e3f, 0xeae5, 0x7e2e, 0xea81,
+  0x7e1d, 0xea1e, 0x7e0c, 0xe9bb, 0x7dfa, 0xe958, 0x7de8, 0xe8f6,
+  0x7dd6, 0xe893, 0x7dc3, 0xe830, 0x7db0, 0xe7cd, 0x7d9d, 0xe76a,
+  0x7d8a, 0xe708, 0x7d76, 0xe6a5, 0x7d62, 0xe643, 0x7d4e, 0xe5e0,
+  0x7d39, 0xe57e, 0x7d24, 0xe51c, 0x7d0f, 0xe4b9, 0x7cf9, 0xe457,
+  0x7ce3, 0xe3f5, 0x7ccd, 0xe393, 0x7cb7, 0xe331, 0x7ca0, 0xe2cf,
+  0x7c89, 0xe26d, 0x7c71, 0xe20b, 0x7c5a, 0xe1aa, 0x7c42, 0xe148,
+  0x7c29, 0xe0e7, 0x7c11, 0xe085, 0x7bf8, 0xe024, 0x7bdf, 0xdfc2,
+  0x7bc5, 0xdf61, 0x7bac, 0xdf00, 0x7b92, 0xde9f, 0x7b77, 0xde3e,
+  0x7b5d, 0xdddd, 0x7b42, 0xdd7c, 0x7b26, 0xdd1b, 0x7b0b, 0xdcbb,
+  0x7aef, 0xdc5a, 0x7ad3, 0xdbf9, 0x7ab6, 0xdb99, 0x7a9a, 0xdb39,
+  0x7a7d, 0xdad8, 0x7a5f, 0xda78, 0x7a42, 0xda18, 0x7a24, 0xd9b8,
+  0x7a05, 0xd958, 0x79e7, 0xd8f9, 0x79c8, 0xd899, 0x79a9, 0xd839,
+  0x798a, 0xd7da, 0x796a, 0xd77a, 0x794a, 0xd71b, 0x792a, 0xd6bc,
+  0x7909, 0xd65d, 0x78e8, 0xd5fe, 0x78c7, 0xd59f, 0x78a6, 0xd540,
+  0x7884, 0xd4e1, 0x7862, 0xd483, 0x7840, 0xd424, 0x781d, 0xd3c6,
+  0x77fa, 0xd368, 0x77d7, 0xd309, 0x77b4, 0xd2ab, 0x7790, 0xd24d,
+  0x776c, 0xd1ef, 0x7747, 0xd192, 0x7723, 0xd134, 0x76fe, 0xd0d7,
+  0x76d9, 0xd079, 0x76b3, 0xd01c, 0x768e, 0xcfbf, 0x7668, 0xcf62,
+  0x7641, 0xcf05, 0x761b, 0xcea8, 0x75f4, 0xce4b, 0x75cc, 0xcdef,
+  0x75a5, 0xcd92, 0x757d, 0xcd36, 0x7555, 0xccda, 0x752d, 0xcc7e,
+  0x7504, 0xcc22, 0x74db, 0xcbc6, 0x74b2, 0xcb6a, 0x7489, 0xcb0e,
+  0x745f, 0xcab3, 0x7435, 0xca58, 0x740b, 0xc9fc, 0x73e0, 0xc9a1,
+  0x73b5, 0xc946, 0x738a, 0xc8ec, 0x735f, 0xc891, 0x7333, 0xc836,
+  0x7307, 0xc7dc, 0x72db, 0xc782, 0x72af, 0xc728, 0x7282, 0xc6ce,
+  0x7255, 0xc674, 0x7227, 0xc61a, 0x71fa, 0xc5c0, 0x71cc, 0xc567,
+  0x719e, 0xc50e, 0x716f, 0xc4b4, 0x7141, 0xc45b, 0x7112, 0xc403,
+  0x70e2, 0xc3aa, 0x70b3, 0xc351, 0x7083, 0xc2f9, 0x7053, 0xc2a0,
+  0x7023, 0xc248, 0x6ff2, 0xc1f0, 0x6fc1, 0xc198, 0x6f90, 0xc141,
+  0x6f5f, 0xc0e9, 0x6f2d, 0xc092, 0x6efb, 0xc03b, 0x6ec9, 0xbfe3,
+  0x6e96, 0xbf8d, 0x6e63, 0xbf36, 0x6e30, 0xbedf, 0x6dfd, 0xbe89,
+  0x6dca, 0xbe32, 0x6d96, 0xbddc, 0x6d62, 0xbd86, 0x6d2d, 0xbd30,
+  0x6cf9, 0xbcdb, 0x6cc4, 0xbc85, 0x6c8f, 0xbc30, 0x6c59, 0xbbdb,
+  0x6c24, 0xbb86, 0x6bee, 0xbb31, 0x6bb8, 0xbadc, 0x6b81, 0xba88,
+  0x6b4a, 0xba33, 0x6b13, 0xb9df, 0x6adc, 0xb98b, 0x6aa5, 0xb937,
+  0x6a6d, 0xb8e4, 0x6a35, 0xb890, 0x69fd, 0xb83d, 0x69c4, 0xb7ea,
+  0x698c, 0xb797, 0x6953, 0xb744, 0x6919, 0xb6f1, 0x68e0, 0xb69f,
+  0x68a6, 0xb64c, 0x686c, 0xb5fa, 0x6832, 0xb5a8, 0x67f7, 0xb557,
+  0x67bd, 0xb505, 0x6782, 0xb4b4, 0x6746, 0xb462, 0x670b, 0xb411,
+  0x66cf, 0xb3c1, 0x6693, 0xb370, 0x6657, 0xb31f, 0x661a, 0xb2cf,
+  0x65dd, 0xb27f, 0x65a0, 0xb22f, 0x6563, 0xb1df, 0x6526, 0xb190,
+  0x64e8, 0xb141, 0x64aa, 0xb0f1, 0x646c, 0xb0a2, 0x642d, 0xb054,
+  0x63ef, 0xb005, 0x63b0, 0xafb7, 0x6371, 0xaf69, 0x6331, 0xaf1b,
+  0x62f2, 0xaecd, 0x62b2, 0xae7f, 0x6271, 0xae32, 0x6231, 0xade4,
+  0x61f1, 0xad97, 0x61b0, 0xad4b, 0x616f, 0xacfe, 0x612d, 0xacb2,
+  0x60ec, 0xac65, 0x60aa, 0xac19, 0x6068, 0xabcd, 0x6026, 0xab82,
+  0x5fe3, 0xab36, 0x5fa0, 0xaaeb, 0x5f5e, 0xaaa0, 0x5f1a, 0xaa55,
+  0x5ed7, 0xaa0b, 0x5e93, 0xa9c0, 0x5e50, 0xa976, 0x5e0b, 0xa92c,
+  0x5dc7, 0xa8e3, 0x5d83, 0xa899, 0x5d3e, 0xa850, 0x5cf9, 0xa807,
+  0x5cb4, 0xa7be, 0x5c6e, 0xa775, 0x5c29, 0xa72c, 0x5be3, 0xa6e4,
+  0x5b9d, 0xa69c, 0x5b56, 0xa654, 0x5b10, 0xa60d, 0x5ac9, 0xa5c5,
+  0x5a82, 0xa57e, 0x5a3b, 0xa537, 0x59f3, 0xa4f0, 0x59ac, 0xa4aa,
+  0x5964, 0xa463, 0x591c, 0xa41d, 0x58d4, 0xa3d7, 0x588b, 0xa392,
+  0x5842, 0xa34c, 0x57f9, 0xa307, 0x57b0, 0xa2c2, 0x5767, 0xa27d,
+  0x571d, 0xa239, 0x56d4, 0xa1f5, 0x568a, 0xa1b0, 0x5640, 0xa16d,
+  0x55f5, 0xa129, 0x55ab, 0xa0e6, 0x5560, 0xa0a2, 0x5515, 0xa060,
+  0x54ca, 0xa01d, 0x547e, 0x9fda, 0x5433, 0x9f98, 0x53e7, 0x9f56,
+  0x539b, 0x9f14, 0x534e, 0x9ed3, 0x5302, 0x9e91, 0x52b5, 0x9e50,
+  0x5269, 0x9e0f, 0x521c, 0x9dcf, 0x51ce, 0x9d8f, 0x5181, 0x9d4e,
+  0x5133, 0x9d0e, 0x50e5, 0x9ccf, 0x5097, 0x9c8f, 0x5049, 0x9c50,
+  0x4ffb, 0x9c11, 0x4fac, 0x9bd3, 0x4f5e, 0x9b94, 0x4f0f, 0x9b56,
+  0x4ebf, 0x9b18, 0x4e70, 0x9ada, 0x4e21, 0x9a9d, 0x4dd1, 0x9a60,
+  0x4d81, 0x9a23, 0x4d31, 0x99e6, 0x4ce1, 0x99a9, 0x4c90, 0x996d,
+  0x4c3f, 0x9931, 0x4bef, 0x98f5, 0x4b9e, 0x98ba, 0x4b4c, 0x987e,
+  0x4afb, 0x9843, 0x4aa9, 0x9809, 0x4a58, 0x97ce, 0x4a06, 0x9794,
+  0x49b4, 0x975a, 0x4961, 0x9720, 0x490f, 0x96e7, 0x48bc, 0x96ad,
+  0x4869, 0x9674, 0x4816, 0x963c, 0x47c3, 0x9603, 0x4770, 0x95cb,
+  0x471c, 0x9593, 0x46c9, 0x955b, 0x4675, 0x9524, 0x4621, 0x94ed,
+  0x45cd, 0x94b6, 0x4578, 0x947f, 0x4524, 0x9448, 0x44cf, 0x9412,
+  0x447a, 0x93dc, 0x4425, 0x93a7, 0x43d0, 0x9371, 0x437b, 0x933c,
+  0x4325, 0x9307, 0x42d0, 0x92d3, 0x427a, 0x929e, 0x4224, 0x926a,
+  0x41ce, 0x9236, 0x4177, 0x9203, 0x4121, 0x91d0, 0x40ca, 0x919d,
+  0x4073, 0x916a, 0x401d, 0x9137, 0x3fc5, 0x9105, 0x3f6e, 0x90d3,
+  0x3f17, 0x90a1, 0x3ebf, 0x9070, 0x3e68, 0x903f, 0x3e10, 0x900e,
+  0x3db8, 0x8fdd, 0x3d60, 0x8fad, 0x3d07, 0x8f7d, 0x3caf, 0x8f4d,
+  0x3c56, 0x8f1e, 0x3bfd, 0x8eee, 0x3ba5, 0x8ebf, 0x3b4c, 0x8e91,
+  0x3af2, 0x8e62, 0x3a99, 0x8e34, 0x3a40, 0x8e06, 0x39e6, 0x8dd9,
+  0x398c, 0x8dab, 0x3932, 0x8d7e, 0x38d8, 0x8d51, 0x387e, 0x8d25,
+  0x3824, 0x8cf9, 0x37ca, 0x8ccd, 0x376f, 0x8ca1, 0x3714, 0x8c76,
+  0x36ba, 0x8c4b, 0x365f, 0x8c20, 0x3604, 0x8bf5, 0x35a8, 0x8bcb,
+  0x354d, 0x8ba1, 0x34f2, 0x8b77, 0x3496, 0x8b4e, 0x343a, 0x8b25,
+  0x33de, 0x8afc, 0x3382, 0x8ad3, 0x3326, 0x8aab, 0x32ca, 0x8a83,
+  0x326e, 0x8a5b, 0x3211, 0x8a34, 0x31b5, 0x8a0c, 0x3158, 0x89e5,
+  0x30fb, 0x89bf, 0x309e, 0x8998, 0x3041, 0x8972, 0x2fe4, 0x894d,
+  0x2f87, 0x8927, 0x2f29, 0x8902, 0x2ecc, 0x88dd, 0x2e6e, 0x88b9,
+  0x2e11, 0x8894, 0x2db3, 0x8870, 0x2d55, 0x884c, 0x2cf7, 0x8829,
+  0x2c98, 0x8806, 0x2c3a, 0x87e3, 0x2bdc, 0x87c0, 0x2b7d, 0x879e,
+  0x2b1f, 0x877c, 0x2ac0, 0x875a, 0x2a61, 0x8739, 0x2a02, 0x8718,
+  0x29a3, 0x86f7, 0x2944, 0x86d6, 0x28e5, 0x86b6, 0x2886, 0x8696,
+  0x2826, 0x8676, 0x27c7, 0x8657, 0x2767, 0x8638, 0x2707, 0x8619,
+  0x26a8, 0x85fb, 0x2648, 0x85dc, 0x25e8, 0x85be, 0x2588, 0x85a1,
+  0x2528, 0x8583, 0x24c7, 0x8566, 0x2467, 0x854a, 0x2407, 0x852d,
+  0x23a6, 0x8511, 0x2345, 0x84f5, 0x22e5, 0x84da, 0x2284, 0x84be,
+  0x2223, 0x84a3, 0x21c2, 0x8489, 0x2161, 0x846e, 0x2100, 0x8454,
+  0x209f, 0x843b, 0x203e, 0x8421, 0x1fdc, 0x8408, 0x1f7b, 0x83ef,
+  0x1f19, 0x83d7, 0x1eb8, 0x83be, 0x1e56, 0x83a6, 0x1df5, 0x838f,
+  0x1d93, 0x8377, 0x1d31, 0x8360, 0x1ccf, 0x8349, 0x1c6d, 0x8333,
+  0x1c0b, 0x831d, 0x1ba9, 0x8307, 0x1b47, 0x82f1, 0x1ae4, 0x82dc,
+  0x1a82, 0x82c7, 0x1a20, 0x82b2, 0x19bd, 0x829e, 0x195b, 0x828a,
+  0x18f8, 0x8276, 0x1896, 0x8263, 0x1833, 0x8250, 0x17d0, 0x823d,
+  0x176d, 0x822a, 0x170a, 0x8218, 0x16a8, 0x8206, 0x1645, 0x81f4,
+  0x15e2, 0x81e3, 0x157f, 0x81d2, 0x151b, 0x81c1, 0x14b8, 0x81b1,
+  0x1455, 0x81a1, 0x13f2, 0x8191, 0x138e, 0x8181, 0x132b, 0x8172,
+  0x12c8, 0x8163, 0x1264, 0x8155, 0x1201, 0x8146, 0x119d, 0x8138,
+  0x1139, 0x812b, 0x10d6, 0x811d, 0x1072, 0x8110, 0x100e, 0x8103,
+  0xfab, 0x80f7, 0xf47, 0x80eb, 0xee3, 0x80df, 0xe7f, 0x80d3,
+  0xe1b, 0x80c8, 0xdb7, 0x80bd, 0xd53, 0x80b3, 0xcef, 0x80a8,
+  0xc8b, 0x809e, 0xc27, 0x8095, 0xbc3, 0x808b, 0xb5f, 0x8082,
+  0xafb, 0x8079, 0xa97, 0x8071, 0xa33, 0x8069, 0x9ce, 0x8061,
+  0x96a, 0x8059, 0x906, 0x8052, 0x8a2, 0x804b, 0x83d, 0x8044,
+  0x7d9, 0x803e, 0x775, 0x8038, 0x710, 0x8032, 0x6ac, 0x802d,
+  0x647, 0x8028, 0x5e3, 0x8023, 0x57f, 0x801f, 0x51a, 0x801b,
+  0x4b6, 0x8017, 0x451, 0x8013, 0x3ed, 0x8010, 0x388, 0x800d,
+  0x324, 0x800a, 0x2bf, 0x8008, 0x25b, 0x8006, 0x1f6, 0x8004,
+  0x192, 0x8003, 0x12d, 0x8002, 0xc9, 0x8001, 0x64, 0x8001,
+};
+
+static const q15_t WeightsQ15_2048[4096] = {
+  0x7fff, 0x0, 0x7fff, 0xffe7, 0x7fff, 0xffce, 0x7fff, 0xffb5,
+  0x7fff, 0xff9c, 0x7fff, 0xff83, 0x7fff, 0xff6a, 0x7fff, 0xff51,
+  0x7fff, 0xff37, 0x7fff, 0xff1e, 0x7fff, 0xff05, 0x7ffe, 0xfeec,
+  0x7ffe, 0xfed3, 0x7ffe, 0xfeba, 0x7ffe, 0xfea1, 0x7ffd, 0xfe88,
+  0x7ffd, 0xfe6e, 0x7ffd, 0xfe55, 0x7ffc, 0xfe3c, 0x7ffc, 0xfe23,
+  0x7ffc, 0xfe0a, 0x7ffb, 0xfdf1, 0x7ffb, 0xfdd8, 0x7ffa, 0xfdbe,
+  0x7ffa, 0xfda5, 0x7ff9, 0xfd8c, 0x7ff9, 0xfd73, 0x7ff8, 0xfd5a,
+  0x7ff8, 0xfd41, 0x7ff7, 0xfd28, 0x7ff7, 0xfd0f, 0x7ff6, 0xfcf5,
+  0x7ff6, 0xfcdc, 0x7ff5, 0xfcc3, 0x7ff4, 0xfcaa, 0x7ff4, 0xfc91,
+  0x7ff3, 0xfc78, 0x7ff2, 0xfc5f, 0x7ff2, 0xfc46, 0x7ff1, 0xfc2c,
+  0x7ff0, 0xfc13, 0x7fef, 0xfbfa, 0x7fee, 0xfbe1, 0x7fee, 0xfbc8,
+  0x7fed, 0xfbaf, 0x7fec, 0xfb96, 0x7feb, 0xfb7d, 0x7fea, 0xfb64,
+  0x7fe9, 0xfb4a, 0x7fe8, 0xfb31, 0x7fe7, 0xfb18, 0x7fe6, 0xfaff,
+  0x7fe5, 0xfae6, 0x7fe4, 0xfacd, 0x7fe3, 0xfab4, 0x7fe2, 0xfa9b,
+  0x7fe1, 0xfa81, 0x7fe0, 0xfa68, 0x7fdf, 0xfa4f, 0x7fde, 0xfa36,
+  0x7fdd, 0xfa1d, 0x7fdc, 0xfa04, 0x7fda, 0xf9eb, 0x7fd9, 0xf9d2,
+  0x7fd8, 0xf9b9, 0x7fd7, 0xf9a0, 0x7fd6, 0xf986, 0x7fd4, 0xf96d,
+  0x7fd3, 0xf954, 0x7fd2, 0xf93b, 0x7fd0, 0xf922, 0x7fcf, 0xf909,
+  0x7fce, 0xf8f0, 0x7fcc, 0xf8d7, 0x7fcb, 0xf8be, 0x7fc9, 0xf8a5,
+  0x7fc8, 0xf88b, 0x7fc6, 0xf872, 0x7fc5, 0xf859, 0x7fc3, 0xf840,
+  0x7fc2, 0xf827, 0x7fc0, 0xf80e, 0x7fbf, 0xf7f5, 0x7fbd, 0xf7dc,
+  0x7fbc, 0xf7c3, 0x7fba, 0xf7aa, 0x7fb8, 0xf791, 0x7fb7, 0xf778,
+  0x7fb5, 0xf75e, 0x7fb3, 0xf745, 0x7fb1, 0xf72c, 0x7fb0, 0xf713,
+  0x7fae, 0xf6fa, 0x7fac, 0xf6e1, 0x7faa, 0xf6c8, 0x7fa9, 0xf6af,
+  0x7fa7, 0xf696, 0x7fa5, 0xf67d, 0x7fa3, 0xf664, 0x7fa1, 0xf64b,
+  0x7f9f, 0xf632, 0x7f9d, 0xf619, 0x7f9b, 0xf600, 0x7f99, 0xf5e7,
+  0x7f97, 0xf5cd, 0x7f95, 0xf5b4, 0x7f93, 0xf59b, 0x7f91, 0xf582,
+  0x7f8f, 0xf569, 0x7f8d, 0xf550, 0x7f8b, 0xf537, 0x7f89, 0xf51e,
+  0x7f87, 0xf505, 0x7f85, 0xf4ec, 0x7f82, 0xf4d3, 0x7f80, 0xf4ba,
+  0x7f7e, 0xf4a1, 0x7f7c, 0xf488, 0x7f79, 0xf46f, 0x7f77, 0xf456,
+  0x7f75, 0xf43d, 0x7f72, 0xf424, 0x7f70, 0xf40b, 0x7f6e, 0xf3f2,
+  0x7f6b, 0xf3d9, 0x7f69, 0xf3c0, 0x7f67, 0xf3a7, 0x7f64, 0xf38e,
+  0x7f62, 0xf375, 0x7f5f, 0xf35c, 0x7f5d, 0xf343, 0x7f5a, 0xf32a,
+  0x7f58, 0xf311, 0x7f55, 0xf2f8, 0x7f53, 0xf2df, 0x7f50, 0xf2c6,
+  0x7f4d, 0xf2ad, 0x7f4b, 0xf294, 0x7f48, 0xf27b, 0x7f45, 0xf262,
+  0x7f43, 0xf249, 0x7f40, 0xf230, 0x7f3d, 0xf217, 0x7f3b, 0xf1fe,
+  0x7f38, 0xf1e5, 0x7f35, 0xf1cc, 0x7f32, 0xf1b3, 0x7f2f, 0xf19a,
+  0x7f2d, 0xf181, 0x7f2a, 0xf168, 0x7f27, 0xf14f, 0x7f24, 0xf136,
+  0x7f21, 0xf11d, 0x7f1e, 0xf104, 0x7f1b, 0xf0eb, 0x7f18, 0xf0d2,
+  0x7f15, 0xf0b9, 0x7f12, 0xf0a0, 0x7f0f, 0xf087, 0x7f0c, 0xf06e,
+  0x7f09, 0xf055, 0x7f06, 0xf03c, 0x7f03, 0xf023, 0x7f00, 0xf00b,
+  0x7efd, 0xeff2, 0x7ef9, 0xefd9, 0x7ef6, 0xefc0, 0x7ef3, 0xefa7,
+  0x7ef0, 0xef8e, 0x7eed, 0xef75, 0x7ee9, 0xef5c, 0x7ee6, 0xef43,
+  0x7ee3, 0xef2a, 0x7edf, 0xef11, 0x7edc, 0xeef8, 0x7ed9, 0xeedf,
+  0x7ed5, 0xeec7, 0x7ed2, 0xeeae, 0x7ecf, 0xee95, 0x7ecb, 0xee7c,
+  0x7ec8, 0xee63, 0x7ec4, 0xee4a, 0x7ec1, 0xee31, 0x7ebd, 0xee18,
+  0x7eba, 0xedff, 0x7eb6, 0xede7, 0x7eb3, 0xedce, 0x7eaf, 0xedb5,
+  0x7eab, 0xed9c, 0x7ea8, 0xed83, 0x7ea4, 0xed6a, 0x7ea1, 0xed51,
+  0x7e9d, 0xed38, 0x7e99, 0xed20, 0x7e95, 0xed07, 0x7e92, 0xecee,
+  0x7e8e, 0xecd5, 0x7e8a, 0xecbc, 0x7e86, 0xeca3, 0x7e83, 0xec8a,
+  0x7e7f, 0xec72, 0x7e7b, 0xec59, 0x7e77, 0xec40, 0x7e73, 0xec27,
+  0x7e6f, 0xec0e, 0x7e6b, 0xebf5, 0x7e67, 0xebdd, 0x7e63, 0xebc4,
+  0x7e5f, 0xebab, 0x7e5b, 0xeb92, 0x7e57, 0xeb79, 0x7e53, 0xeb61,
+  0x7e4f, 0xeb48, 0x7e4b, 0xeb2f, 0x7e47, 0xeb16, 0x7e43, 0xeafd,
+  0x7e3f, 0xeae5, 0x7e3b, 0xeacc, 0x7e37, 0xeab3, 0x7e32, 0xea9a,
+  0x7e2e, 0xea81, 0x7e2a, 0xea69, 0x7e26, 0xea50, 0x7e21, 0xea37,
+  0x7e1d, 0xea1e, 0x7e19, 0xea06, 0x7e14, 0xe9ed, 0x7e10, 0xe9d4,
+  0x7e0c, 0xe9bb, 0x7e07, 0xe9a3, 0x7e03, 0xe98a, 0x7dff, 0xe971,
+  0x7dfa, 0xe958, 0x7df6, 0xe940, 0x7df1, 0xe927, 0x7ded, 0xe90e,
+  0x7de8, 0xe8f6, 0x7de4, 0xe8dd, 0x7ddf, 0xe8c4, 0x7dda, 0xe8ab,
+  0x7dd6, 0xe893, 0x7dd1, 0xe87a, 0x7dcd, 0xe861, 0x7dc8, 0xe849,
+  0x7dc3, 0xe830, 0x7dbf, 0xe817, 0x7dba, 0xe7fe, 0x7db5, 0xe7e6,
+  0x7db0, 0xe7cd, 0x7dac, 0xe7b4, 0x7da7, 0xe79c, 0x7da2, 0xe783,
+  0x7d9d, 0xe76a, 0x7d98, 0xe752, 0x7d94, 0xe739, 0x7d8f, 0xe720,
+  0x7d8a, 0xe708, 0x7d85, 0xe6ef, 0x7d80, 0xe6d6, 0x7d7b, 0xe6be,
+  0x7d76, 0xe6a5, 0x7d71, 0xe68d, 0x7d6c, 0xe674, 0x7d67, 0xe65b,
+  0x7d62, 0xe643, 0x7d5d, 0xe62a, 0x7d58, 0xe611, 0x7d53, 0xe5f9,
+  0x7d4e, 0xe5e0, 0x7d49, 0xe5c8, 0x7d43, 0xe5af, 0x7d3e, 0xe596,
+  0x7d39, 0xe57e, 0x7d34, 0xe565, 0x7d2f, 0xe54d, 0x7d29, 0xe534,
+  0x7d24, 0xe51c, 0x7d1f, 0xe503, 0x7d19, 0xe4ea, 0x7d14, 0xe4d2,
+  0x7d0f, 0xe4b9, 0x7d09, 0xe4a1, 0x7d04, 0xe488, 0x7cff, 0xe470,
+  0x7cf9, 0xe457, 0x7cf4, 0xe43f, 0x7cee, 0xe426, 0x7ce9, 0xe40e,
+  0x7ce3, 0xe3f5, 0x7cde, 0xe3dc, 0x7cd8, 0xe3c4, 0x7cd3, 0xe3ab,
+  0x7ccd, 0xe393, 0x7cc8, 0xe37a, 0x7cc2, 0xe362, 0x7cbc, 0xe349,
+  0x7cb7, 0xe331, 0x7cb1, 0xe318, 0x7cab, 0xe300, 0x7ca6, 0xe2e8,
+  0x7ca0, 0xe2cf, 0x7c9a, 0xe2b7, 0x7c94, 0xe29e, 0x7c8f, 0xe286,
+  0x7c89, 0xe26d, 0x7c83, 0xe255, 0x7c7d, 0xe23c, 0x7c77, 0xe224,
+  0x7c71, 0xe20b, 0x7c6c, 0xe1f3, 0x7c66, 0xe1db, 0x7c60, 0xe1c2,
+  0x7c5a, 0xe1aa, 0x7c54, 0xe191, 0x7c4e, 0xe179, 0x7c48, 0xe160,
+  0x7c42, 0xe148, 0x7c3c, 0xe130, 0x7c36, 0xe117, 0x7c30, 0xe0ff,
+  0x7c29, 0xe0e7, 0x7c23, 0xe0ce, 0x7c1d, 0xe0b6, 0x7c17, 0xe09d,
+  0x7c11, 0xe085, 0x7c0b, 0xe06d, 0x7c05, 0xe054, 0x7bfe, 0xe03c,
+  0x7bf8, 0xe024, 0x7bf2, 0xe00b, 0x7beb, 0xdff3, 0x7be5, 0xdfdb,
+  0x7bdf, 0xdfc2, 0x7bd9, 0xdfaa, 0x7bd2, 0xdf92, 0x7bcc, 0xdf79,
+  0x7bc5, 0xdf61, 0x7bbf, 0xdf49, 0x7bb9, 0xdf30, 0x7bb2, 0xdf18,
+  0x7bac, 0xdf00, 0x7ba5, 0xdee8, 0x7b9f, 0xdecf, 0x7b98, 0xdeb7,
+  0x7b92, 0xde9f, 0x7b8b, 0xde87, 0x7b84, 0xde6e, 0x7b7e, 0xde56,
+  0x7b77, 0xde3e, 0x7b71, 0xde26, 0x7b6a, 0xde0d, 0x7b63, 0xddf5,
+  0x7b5d, 0xdddd, 0x7b56, 0xddc5, 0x7b4f, 0xddac, 0x7b48, 0xdd94,
+  0x7b42, 0xdd7c, 0x7b3b, 0xdd64, 0x7b34, 0xdd4c, 0x7b2d, 0xdd33,
+  0x7b26, 0xdd1b, 0x7b1f, 0xdd03, 0x7b19, 0xdceb, 0x7b12, 0xdcd3,
+  0x7b0b, 0xdcbb, 0x7b04, 0xdca2, 0x7afd, 0xdc8a, 0x7af6, 0xdc72,
+  0x7aef, 0xdc5a, 0x7ae8, 0xdc42, 0x7ae1, 0xdc2a, 0x7ada, 0xdc12,
+  0x7ad3, 0xdbf9, 0x7acc, 0xdbe1, 0x7ac5, 0xdbc9, 0x7abd, 0xdbb1,
+  0x7ab6, 0xdb99, 0x7aaf, 0xdb81, 0x7aa8, 0xdb69, 0x7aa1, 0xdb51,
+  0x7a9a, 0xdb39, 0x7a92, 0xdb21, 0x7a8b, 0xdb09, 0x7a84, 0xdaf1,
+  0x7a7d, 0xdad8, 0x7a75, 0xdac0, 0x7a6e, 0xdaa8, 0x7a67, 0xda90,
+  0x7a5f, 0xda78, 0x7a58, 0xda60, 0x7a50, 0xda48, 0x7a49, 0xda30,
+  0x7a42, 0xda18, 0x7a3a, 0xda00, 0x7a33, 0xd9e8, 0x7a2b, 0xd9d0,
+  0x7a24, 0xd9b8, 0x7a1c, 0xd9a0, 0x7a15, 0xd988, 0x7a0d, 0xd970,
+  0x7a05, 0xd958, 0x79fe, 0xd940, 0x79f6, 0xd928, 0x79ef, 0xd911,
+  0x79e7, 0xd8f9, 0x79df, 0xd8e1, 0x79d8, 0xd8c9, 0x79d0, 0xd8b1,
+  0x79c8, 0xd899, 0x79c0, 0xd881, 0x79b9, 0xd869, 0x79b1, 0xd851,
+  0x79a9, 0xd839, 0x79a1, 0xd821, 0x7999, 0xd80a, 0x7992, 0xd7f2,
+  0x798a, 0xd7da, 0x7982, 0xd7c2, 0x797a, 0xd7aa, 0x7972, 0xd792,
+  0x796a, 0xd77a, 0x7962, 0xd763, 0x795a, 0xd74b, 0x7952, 0xd733,
+  0x794a, 0xd71b, 0x7942, 0xd703, 0x793a, 0xd6eb, 0x7932, 0xd6d4,
+  0x792a, 0xd6bc, 0x7922, 0xd6a4, 0x7919, 0xd68c, 0x7911, 0xd675,
+  0x7909, 0xd65d, 0x7901, 0xd645, 0x78f9, 0xd62d, 0x78f1, 0xd615,
+  0x78e8, 0xd5fe, 0x78e0, 0xd5e6, 0x78d8, 0xd5ce, 0x78cf, 0xd5b7,
+  0x78c7, 0xd59f, 0x78bf, 0xd587, 0x78b6, 0xd56f, 0x78ae, 0xd558,
+  0x78a6, 0xd540, 0x789d, 0xd528, 0x7895, 0xd511, 0x788c, 0xd4f9,
+  0x7884, 0xd4e1, 0x787c, 0xd4ca, 0x7873, 0xd4b2, 0x786b, 0xd49a,
+  0x7862, 0xd483, 0x7859, 0xd46b, 0x7851, 0xd453, 0x7848, 0xd43c,
+  0x7840, 0xd424, 0x7837, 0xd40d, 0x782e, 0xd3f5, 0x7826, 0xd3dd,
+  0x781d, 0xd3c6, 0x7814, 0xd3ae, 0x780c, 0xd397, 0x7803, 0xd37f,
+  0x77fa, 0xd368, 0x77f1, 0xd350, 0x77e9, 0xd338, 0x77e0, 0xd321,
+  0x77d7, 0xd309, 0x77ce, 0xd2f2, 0x77c5, 0xd2da, 0x77bc, 0xd2c3,
+  0x77b4, 0xd2ab, 0x77ab, 0xd294, 0x77a2, 0xd27c, 0x7799, 0xd265,
+  0x7790, 0xd24d, 0x7787, 0xd236, 0x777e, 0xd21e, 0x7775, 0xd207,
+  0x776c, 0xd1ef, 0x7763, 0xd1d8, 0x775a, 0xd1c1, 0x7751, 0xd1a9,
+  0x7747, 0xd192, 0x773e, 0xd17a, 0x7735, 0xd163, 0x772c, 0xd14b,
+  0x7723, 0xd134, 0x771a, 0xd11d, 0x7710, 0xd105, 0x7707, 0xd0ee,
+  0x76fe, 0xd0d7, 0x76f5, 0xd0bf, 0x76eb, 0xd0a8, 0x76e2, 0xd091,
+  0x76d9, 0xd079, 0x76cf, 0xd062, 0x76c6, 0xd04b, 0x76bd, 0xd033,
+  0x76b3, 0xd01c, 0x76aa, 0xd005, 0x76a0, 0xcfed, 0x7697, 0xcfd6,
+  0x768e, 0xcfbf, 0x7684, 0xcfa7, 0x767b, 0xcf90, 0x7671, 0xcf79,
+  0x7668, 0xcf62, 0x765e, 0xcf4a, 0x7654, 0xcf33, 0x764b, 0xcf1c,
+  0x7641, 0xcf05, 0x7638, 0xceee, 0x762e, 0xced6, 0x7624, 0xcebf,
+  0x761b, 0xcea8, 0x7611, 0xce91, 0x7607, 0xce7a, 0x75fd, 0xce62,
+  0x75f4, 0xce4b, 0x75ea, 0xce34, 0x75e0, 0xce1d, 0x75d6, 0xce06,
+  0x75cc, 0xcdef, 0x75c3, 0xcdd8, 0x75b9, 0xcdc0, 0x75af, 0xcda9,
+  0x75a5, 0xcd92, 0x759b, 0xcd7b, 0x7591, 0xcd64, 0x7587, 0xcd4d,
+  0x757d, 0xcd36, 0x7573, 0xcd1f, 0x7569, 0xcd08, 0x755f, 0xccf1,
+  0x7555, 0xccda, 0x754b, 0xccc3, 0x7541, 0xccac, 0x7537, 0xcc95,
+  0x752d, 0xcc7e, 0x7523, 0xcc67, 0x7519, 0xcc50, 0x750f, 0xcc39,
+  0x7504, 0xcc22, 0x74fa, 0xcc0b, 0x74f0, 0xcbf4, 0x74e6, 0xcbdd,
+  0x74db, 0xcbc6, 0x74d1, 0xcbaf, 0x74c7, 0xcb98, 0x74bd, 0xcb81,
+  0x74b2, 0xcb6a, 0x74a8, 0xcb53, 0x749e, 0xcb3c, 0x7493, 0xcb25,
+  0x7489, 0xcb0e, 0x747e, 0xcaf8, 0x7474, 0xcae1, 0x746a, 0xcaca,
+  0x745f, 0xcab3, 0x7455, 0xca9c, 0x744a, 0xca85, 0x7440, 0xca6e,
+  0x7435, 0xca58, 0x742b, 0xca41, 0x7420, 0xca2a, 0x7415, 0xca13,
+  0x740b, 0xc9fc, 0x7400, 0xc9e6, 0x73f6, 0xc9cf, 0x73eb, 0xc9b8,
+  0x73e0, 0xc9a1, 0x73d6, 0xc98b, 0x73cb, 0xc974, 0x73c0, 0xc95d,
+  0x73b5, 0xc946, 0x73ab, 0xc930, 0x73a0, 0xc919, 0x7395, 0xc902,
+  0x738a, 0xc8ec, 0x737f, 0xc8d5, 0x7375, 0xc8be, 0x736a, 0xc8a8,
+  0x735f, 0xc891, 0x7354, 0xc87a, 0x7349, 0xc864, 0x733e, 0xc84d,
+  0x7333, 0xc836, 0x7328, 0xc820, 0x731d, 0xc809, 0x7312, 0xc7f3,
+  0x7307, 0xc7dc, 0x72fc, 0xc7c5, 0x72f1, 0xc7af, 0x72e6, 0xc798,
+  0x72db, 0xc782, 0x72d0, 0xc76b, 0x72c5, 0xc755, 0x72ba, 0xc73e,
+  0x72af, 0xc728, 0x72a3, 0xc711, 0x7298, 0xc6fa, 0x728d, 0xc6e4,
+  0x7282, 0xc6ce, 0x7276, 0xc6b7, 0x726b, 0xc6a1, 0x7260, 0xc68a,
+  0x7255, 0xc674, 0x7249, 0xc65d, 0x723e, 0xc647, 0x7233, 0xc630,
+  0x7227, 0xc61a, 0x721c, 0xc603, 0x7211, 0xc5ed, 0x7205, 0xc5d7,
+  0x71fa, 0xc5c0, 0x71ee, 0xc5aa, 0x71e3, 0xc594, 0x71d7, 0xc57d,
+  0x71cc, 0xc567, 0x71c0, 0xc551, 0x71b5, 0xc53a, 0x71a9, 0xc524,
+  0x719e, 0xc50e, 0x7192, 0xc4f7, 0x7186, 0xc4e1, 0x717b, 0xc4cb,
+  0x716f, 0xc4b4, 0x7164, 0xc49e, 0x7158, 0xc488, 0x714c, 0xc472,
+  0x7141, 0xc45b, 0x7135, 0xc445, 0x7129, 0xc42f, 0x711d, 0xc419,
+  0x7112, 0xc403, 0x7106, 0xc3ec, 0x70fa, 0xc3d6, 0x70ee, 0xc3c0,
+  0x70e2, 0xc3aa, 0x70d6, 0xc394, 0x70cb, 0xc37d, 0x70bf, 0xc367,
+  0x70b3, 0xc351, 0x70a7, 0xc33b, 0x709b, 0xc325, 0x708f, 0xc30f,
+  0x7083, 0xc2f9, 0x7077, 0xc2e3, 0x706b, 0xc2cd, 0x705f, 0xc2b7,
+  0x7053, 0xc2a0, 0x7047, 0xc28a, 0x703b, 0xc274, 0x702f, 0xc25e,
+  0x7023, 0xc248, 0x7016, 0xc232, 0x700a, 0xc21c, 0x6ffe, 0xc206,
+  0x6ff2, 0xc1f0, 0x6fe6, 0xc1da, 0x6fda, 0xc1c4, 0x6fcd, 0xc1ae,
+  0x6fc1, 0xc198, 0x6fb5, 0xc183, 0x6fa9, 0xc16d, 0x6f9c, 0xc157,
+  0x6f90, 0xc141, 0x6f84, 0xc12b, 0x6f77, 0xc115, 0x6f6b, 0xc0ff,
+  0x6f5f, 0xc0e9, 0x6f52, 0xc0d3, 0x6f46, 0xc0bd, 0x6f39, 0xc0a8,
+  0x6f2d, 0xc092, 0x6f20, 0xc07c, 0x6f14, 0xc066, 0x6f07, 0xc050,
+  0x6efb, 0xc03b, 0x6eee, 0xc025, 0x6ee2, 0xc00f, 0x6ed5, 0xbff9,
+  0x6ec9, 0xbfe3, 0x6ebc, 0xbfce, 0x6eaf, 0xbfb8, 0x6ea3, 0xbfa2,
+  0x6e96, 0xbf8d, 0x6e89, 0xbf77, 0x6e7d, 0xbf61, 0x6e70, 0xbf4b,
+  0x6e63, 0xbf36, 0x6e57, 0xbf20, 0x6e4a, 0xbf0a, 0x6e3d, 0xbef5,
+  0x6e30, 0xbedf, 0x6e24, 0xbeca, 0x6e17, 0xbeb4, 0x6e0a, 0xbe9e,
+  0x6dfd, 0xbe89, 0x6df0, 0xbe73, 0x6de3, 0xbe5e, 0x6dd6, 0xbe48,
+  0x6dca, 0xbe32, 0x6dbd, 0xbe1d, 0x6db0, 0xbe07, 0x6da3, 0xbdf2,
+  0x6d96, 0xbddc, 0x6d89, 0xbdc7, 0x6d7c, 0xbdb1, 0x6d6f, 0xbd9c,
+  0x6d62, 0xbd86, 0x6d55, 0xbd71, 0x6d48, 0xbd5b, 0x6d3a, 0xbd46,
+  0x6d2d, 0xbd30, 0x6d20, 0xbd1b, 0x6d13, 0xbd06, 0x6d06, 0xbcf0,
+  0x6cf9, 0xbcdb, 0x6cec, 0xbcc5, 0x6cde, 0xbcb0, 0x6cd1, 0xbc9b,
+  0x6cc4, 0xbc85, 0x6cb7, 0xbc70, 0x6ca9, 0xbc5b, 0x6c9c, 0xbc45,
+  0x6c8f, 0xbc30, 0x6c81, 0xbc1b, 0x6c74, 0xbc05, 0x6c67, 0xbbf0,
+  0x6c59, 0xbbdb, 0x6c4c, 0xbbc5, 0x6c3f, 0xbbb0, 0x6c31, 0xbb9b,
+  0x6c24, 0xbb86, 0x6c16, 0xbb70, 0x6c09, 0xbb5b, 0x6bfb, 0xbb46,
+  0x6bee, 0xbb31, 0x6be0, 0xbb1c, 0x6bd3, 0xbb06, 0x6bc5, 0xbaf1,
+  0x6bb8, 0xbadc, 0x6baa, 0xbac7, 0x6b9c, 0xbab2, 0x6b8f, 0xba9d,
+  0x6b81, 0xba88, 0x6b73, 0xba73, 0x6b66, 0xba5d, 0x6b58, 0xba48,
+  0x6b4a, 0xba33, 0x6b3d, 0xba1e, 0x6b2f, 0xba09, 0x6b21, 0xb9f4,
+  0x6b13, 0xb9df, 0x6b06, 0xb9ca, 0x6af8, 0xb9b5, 0x6aea, 0xb9a0,
+  0x6adc, 0xb98b, 0x6ace, 0xb976, 0x6ac1, 0xb961, 0x6ab3, 0xb94c,
+  0x6aa5, 0xb937, 0x6a97, 0xb922, 0x6a89, 0xb90d, 0x6a7b, 0xb8f8,
+  0x6a6d, 0xb8e4, 0x6a5f, 0xb8cf, 0x6a51, 0xb8ba, 0x6a43, 0xb8a5,
+  0x6a35, 0xb890, 0x6a27, 0xb87b, 0x6a19, 0xb866, 0x6a0b, 0xb852,
+  0x69fd, 0xb83d, 0x69ef, 0xb828, 0x69e1, 0xb813, 0x69d3, 0xb7fe,
+  0x69c4, 0xb7ea, 0x69b6, 0xb7d5, 0x69a8, 0xb7c0, 0x699a, 0xb7ab,
+  0x698c, 0xb797, 0x697d, 0xb782, 0x696f, 0xb76d, 0x6961, 0xb758,
+  0x6953, 0xb744, 0x6944, 0xb72f, 0x6936, 0xb71a, 0x6928, 0xb706,
+  0x6919, 0xb6f1, 0x690b, 0xb6dd, 0x68fd, 0xb6c8, 0x68ee, 0xb6b3,
+  0x68e0, 0xb69f, 0x68d1, 0xb68a, 0x68c3, 0xb676, 0x68b5, 0xb661,
+  0x68a6, 0xb64c, 0x6898, 0xb638, 0x6889, 0xb623, 0x687b, 0xb60f,
+  0x686c, 0xb5fa, 0x685e, 0xb5e6, 0x684f, 0xb5d1, 0x6840, 0xb5bd,
+  0x6832, 0xb5a8, 0x6823, 0xb594, 0x6815, 0xb57f, 0x6806, 0xb56b,
+  0x67f7, 0xb557, 0x67e9, 0xb542, 0x67da, 0xb52e, 0x67cb, 0xb519,
+  0x67bd, 0xb505, 0x67ae, 0xb4f1, 0x679f, 0xb4dc, 0x6790, 0xb4c8,
+  0x6782, 0xb4b4, 0x6773, 0xb49f, 0x6764, 0xb48b, 0x6755, 0xb477,
+  0x6746, 0xb462, 0x6737, 0xb44e, 0x6729, 0xb43a, 0x671a, 0xb426,
+  0x670b, 0xb411, 0x66fc, 0xb3fd, 0x66ed, 0xb3e9, 0x66de, 0xb3d5,
+  0x66cf, 0xb3c1, 0x66c0, 0xb3ac, 0x66b1, 0xb398, 0x66a2, 0xb384,
+  0x6693, 0xb370, 0x6684, 0xb35c, 0x6675, 0xb348, 0x6666, 0xb334,
+  0x6657, 0xb31f, 0x6648, 0xb30b, 0x6639, 0xb2f7, 0x6629, 0xb2e3,
+  0x661a, 0xb2cf, 0x660b, 0xb2bb, 0x65fc, 0xb2a7, 0x65ed, 0xb293,
+  0x65dd, 0xb27f, 0x65ce, 0xb26b, 0x65bf, 0xb257, 0x65b0, 0xb243,
+  0x65a0, 0xb22f, 0x6591, 0xb21b, 0x6582, 0xb207, 0x6573, 0xb1f3,
+  0x6563, 0xb1df, 0x6554, 0xb1cc, 0x6545, 0xb1b8, 0x6535, 0xb1a4,
+  0x6526, 0xb190, 0x6516, 0xb17c, 0x6507, 0xb168, 0x64f7, 0xb154,
+  0x64e8, 0xb141, 0x64d9, 0xb12d, 0x64c9, 0xb119, 0x64ba, 0xb105,
+  0x64aa, 0xb0f1, 0x649b, 0xb0de, 0x648b, 0xb0ca, 0x647b, 0xb0b6,
+  0x646c, 0xb0a2, 0x645c, 0xb08f, 0x644d, 0xb07b, 0x643d, 0xb067,
+  0x642d, 0xb054, 0x641e, 0xb040, 0x640e, 0xb02c, 0x63fe, 0xb019,
+  0x63ef, 0xb005, 0x63df, 0xaff1, 0x63cf, 0xafde, 0x63c0, 0xafca,
+  0x63b0, 0xafb7, 0x63a0, 0xafa3, 0x6390, 0xaf90, 0x6380, 0xaf7c,
+  0x6371, 0xaf69, 0x6361, 0xaf55, 0x6351, 0xaf41, 0x6341, 0xaf2e,
+  0x6331, 0xaf1b, 0x6321, 0xaf07, 0x6311, 0xaef4, 0x6301, 0xaee0,
+  0x62f2, 0xaecd, 0x62e2, 0xaeb9, 0x62d2, 0xaea6, 0x62c2, 0xae92,
+  0x62b2, 0xae7f, 0x62a2, 0xae6c, 0x6292, 0xae58, 0x6282, 0xae45,
+  0x6271, 0xae32, 0x6261, 0xae1e, 0x6251, 0xae0b, 0x6241, 0xadf8,
+  0x6231, 0xade4, 0x6221, 0xadd1, 0x6211, 0xadbe, 0x6201, 0xadab,
+  0x61f1, 0xad97, 0x61e0, 0xad84, 0x61d0, 0xad71, 0x61c0, 0xad5e,
+  0x61b0, 0xad4b, 0x619f, 0xad37, 0x618f, 0xad24, 0x617f, 0xad11,
+  0x616f, 0xacfe, 0x615e, 0xaceb, 0x614e, 0xacd8, 0x613e, 0xacc5,
+  0x612d, 0xacb2, 0x611d, 0xac9e, 0x610d, 0xac8b, 0x60fc, 0xac78,
+  0x60ec, 0xac65, 0x60db, 0xac52, 0x60cb, 0xac3f, 0x60ba, 0xac2c,
+  0x60aa, 0xac19, 0x6099, 0xac06, 0x6089, 0xabf3, 0x6078, 0xabe0,
+  0x6068, 0xabcd, 0x6057, 0xabbb, 0x6047, 0xaba8, 0x6036, 0xab95,
+  0x6026, 0xab82, 0x6015, 0xab6f, 0x6004, 0xab5c, 0x5ff4, 0xab49,
+  0x5fe3, 0xab36, 0x5fd3, 0xab24, 0x5fc2, 0xab11, 0x5fb1, 0xaafe,
+  0x5fa0, 0xaaeb, 0x5f90, 0xaad8, 0x5f7f, 0xaac6, 0x5f6e, 0xaab3,
+  0x5f5e, 0xaaa0, 0x5f4d, 0xaa8e, 0x5f3c, 0xaa7b, 0x5f2b, 0xaa68,
+  0x5f1a, 0xaa55, 0x5f0a, 0xaa43, 0x5ef9, 0xaa30, 0x5ee8, 0xaa1d,
+  0x5ed7, 0xaa0b, 0x5ec6, 0xa9f8, 0x5eb5, 0xa9e6, 0x5ea4, 0xa9d3,
+  0x5e93, 0xa9c0, 0x5e82, 0xa9ae, 0x5e71, 0xa99b, 0x5e60, 0xa989,
+  0x5e50, 0xa976, 0x5e3f, 0xa964, 0x5e2d, 0xa951, 0x5e1c, 0xa93f,
+  0x5e0b, 0xa92c, 0x5dfa, 0xa91a, 0x5de9, 0xa907, 0x5dd8, 0xa8f5,
+  0x5dc7, 0xa8e3, 0x5db6, 0xa8d0, 0x5da5, 0xa8be, 0x5d94, 0xa8ab,
+  0x5d83, 0xa899, 0x5d71, 0xa887, 0x5d60, 0xa874, 0x5d4f, 0xa862,
+  0x5d3e, 0xa850, 0x5d2d, 0xa83d, 0x5d1b, 0xa82b, 0x5d0a, 0xa819,
+  0x5cf9, 0xa807, 0x5ce8, 0xa7f4, 0x5cd6, 0xa7e2, 0x5cc5, 0xa7d0,
+  0x5cb4, 0xa7be, 0x5ca2, 0xa7ab, 0x5c91, 0xa799, 0x5c80, 0xa787,
+  0x5c6e, 0xa775, 0x5c5d, 0xa763, 0x5c4b, 0xa751, 0x5c3a, 0xa73f,
+  0x5c29, 0xa72c, 0x5c17, 0xa71a, 0x5c06, 0xa708, 0x5bf4, 0xa6f6,
+  0x5be3, 0xa6e4, 0x5bd1, 0xa6d2, 0x5bc0, 0xa6c0, 0x5bae, 0xa6ae,
+  0x5b9d, 0xa69c, 0x5b8b, 0xa68a, 0x5b79, 0xa678, 0x5b68, 0xa666,
+  0x5b56, 0xa654, 0x5b45, 0xa642, 0x5b33, 0xa630, 0x5b21, 0xa61f,
+  0x5b10, 0xa60d, 0x5afe, 0xa5fb, 0x5aec, 0xa5e9, 0x5adb, 0xa5d7,
+  0x5ac9, 0xa5c5, 0x5ab7, 0xa5b3, 0x5aa5, 0xa5a2, 0x5a94, 0xa590,
+  0x5a82, 0xa57e, 0x5a70, 0xa56c, 0x5a5e, 0xa55b, 0x5a4d, 0xa549,
+  0x5a3b, 0xa537, 0x5a29, 0xa525, 0x5a17, 0xa514, 0x5a05, 0xa502,
+  0x59f3, 0xa4f0, 0x59e1, 0xa4df, 0x59d0, 0xa4cd, 0x59be, 0xa4bb,
+  0x59ac, 0xa4aa, 0x599a, 0xa498, 0x5988, 0xa487, 0x5976, 0xa475,
+  0x5964, 0xa463, 0x5952, 0xa452, 0x5940, 0xa440, 0x592e, 0xa42f,
+  0x591c, 0xa41d, 0x590a, 0xa40c, 0x58f8, 0xa3fa, 0x58e6, 0xa3e9,
+  0x58d4, 0xa3d7, 0x58c1, 0xa3c6, 0x58af, 0xa3b5, 0x589d, 0xa3a3,
+  0x588b, 0xa392, 0x5879, 0xa380, 0x5867, 0xa36f, 0x5855, 0xa35e,
+  0x5842, 0xa34c, 0x5830, 0xa33b, 0x581e, 0xa32a, 0x580c, 0xa318,
+  0x57f9, 0xa307, 0x57e7, 0xa2f6, 0x57d5, 0xa2e5, 0x57c3, 0xa2d3,
+  0x57b0, 0xa2c2, 0x579e, 0xa2b1, 0x578c, 0xa2a0, 0x5779, 0xa28f,
+  0x5767, 0xa27d, 0x5755, 0xa26c, 0x5742, 0xa25b, 0x5730, 0xa24a,
+  0x571d, 0xa239, 0x570b, 0xa228, 0x56f9, 0xa217, 0x56e6, 0xa206,
+  0x56d4, 0xa1f5, 0x56c1, 0xa1e4, 0x56af, 0xa1d3, 0x569c, 0xa1c1,
+  0x568a, 0xa1b0, 0x5677, 0xa1a0, 0x5665, 0xa18f, 0x5652, 0xa17e,
+  0x5640, 0xa16d, 0x562d, 0xa15c, 0x561a, 0xa14b, 0x5608, 0xa13a,
+  0x55f5, 0xa129, 0x55e3, 0xa118, 0x55d0, 0xa107, 0x55bd, 0xa0f6,
+  0x55ab, 0xa0e6, 0x5598, 0xa0d5, 0x5585, 0xa0c4, 0x5572, 0xa0b3,
+  0x5560, 0xa0a2, 0x554d, 0xa092, 0x553a, 0xa081, 0x5528, 0xa070,
+  0x5515, 0xa060, 0x5502, 0xa04f, 0x54ef, 0xa03e, 0x54dc, 0xa02d,
+  0x54ca, 0xa01d, 0x54b7, 0xa00c, 0x54a4, 0x9ffc, 0x5491, 0x9feb,
+  0x547e, 0x9fda, 0x546b, 0x9fca, 0x5458, 0x9fb9, 0x5445, 0x9fa9,
+  0x5433, 0x9f98, 0x5420, 0x9f88, 0x540d, 0x9f77, 0x53fa, 0x9f67,
+  0x53e7, 0x9f56, 0x53d4, 0x9f46, 0x53c1, 0x9f35, 0x53ae, 0x9f25,
+  0x539b, 0x9f14, 0x5388, 0x9f04, 0x5375, 0x9ef3, 0x5362, 0x9ee3,
+  0x534e, 0x9ed3, 0x533b, 0x9ec2, 0x5328, 0x9eb2, 0x5315, 0x9ea2,
+  0x5302, 0x9e91, 0x52ef, 0x9e81, 0x52dc, 0x9e71, 0x52c9, 0x9e61,
+  0x52b5, 0x9e50, 0x52a2, 0x9e40, 0x528f, 0x9e30, 0x527c, 0x9e20,
+  0x5269, 0x9e0f, 0x5255, 0x9dff, 0x5242, 0x9def, 0x522f, 0x9ddf,
+  0x521c, 0x9dcf, 0x5208, 0x9dbf, 0x51f5, 0x9daf, 0x51e2, 0x9d9f,
+  0x51ce, 0x9d8f, 0x51bb, 0x9d7e, 0x51a8, 0x9d6e, 0x5194, 0x9d5e,
+  0x5181, 0x9d4e, 0x516e, 0x9d3e, 0x515a, 0x9d2e, 0x5147, 0x9d1e,
+  0x5133, 0x9d0e, 0x5120, 0x9cff, 0x510c, 0x9cef, 0x50f9, 0x9cdf,
+  0x50e5, 0x9ccf, 0x50d2, 0x9cbf, 0x50bf, 0x9caf, 0x50ab, 0x9c9f,
+  0x5097, 0x9c8f, 0x5084, 0x9c80, 0x5070, 0x9c70, 0x505d, 0x9c60,
+  0x5049, 0x9c50, 0x5036, 0x9c40, 0x5022, 0x9c31, 0x500f, 0x9c21,
+  0x4ffb, 0x9c11, 0x4fe7, 0x9c02, 0x4fd4, 0x9bf2, 0x4fc0, 0x9be2,
+  0x4fac, 0x9bd3, 0x4f99, 0x9bc3, 0x4f85, 0x9bb3, 0x4f71, 0x9ba4,
+  0x4f5e, 0x9b94, 0x4f4a, 0x9b85, 0x4f36, 0x9b75, 0x4f22, 0x9b65,
+  0x4f0f, 0x9b56, 0x4efb, 0x9b46, 0x4ee7, 0x9b37, 0x4ed3, 0x9b27,
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+  0x3ebf, 0x9070, 0x3ea9, 0x9064, 0x3e93, 0x9057, 0x3e7d, 0x904b,
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+  0x3e10, 0x900e, 0x3dfa, 0x9002, 0x3de4, 0x8ff6, 0x3dce, 0x8fea,
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+  0x3d60, 0x8fad, 0x3d49, 0x8fa1, 0x3d33, 0x8f95, 0x3d1d, 0x8f89,
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+  0x3604, 0x8bf5, 0x35ed, 0x8beb, 0x35d6, 0x8be0, 0x35bf, 0x8bd5,
+  0x35a8, 0x8bcb, 0x3592, 0x8bc0, 0x357b, 0x8bb6, 0x3564, 0x8bab,
+  0x354d, 0x8ba1, 0x3536, 0x8b96, 0x351f, 0x8b8c, 0x3508, 0x8b82,
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+  0x3382, 0x8ad3, 0x336b, 0x8ac9, 0x3354, 0x8abf, 0x333d, 0x8ab5,
+  0x3326, 0x8aab, 0x330f, 0x8aa1, 0x32f8, 0x8a97, 0x32e1, 0x8a8d,
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+  0x30fb, 0x89bf, 0x30e4, 0x89b5, 0x30cd, 0x89ac, 0x30b6, 0x89a2,
+  0x309e, 0x8998, 0x3087, 0x898f, 0x3070, 0x8985, 0x3059, 0x897c,
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+  0x2e11, 0x8894, 0x2df9, 0x888b, 0x2de2, 0x8882, 0x2dca, 0x8879,
+  0x2db3, 0x8870, 0x2d9b, 0x8867, 0x2d84, 0x885e, 0x2d6c, 0x8855,
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+  0x2c98, 0x8806, 0x2c81, 0x87fd, 0x2c69, 0x87f4, 0x2c52, 0x87ec,
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+  0x2b7d, 0x879e, 0x2b66, 0x8795, 0x2b4e, 0x878d, 0x2b36, 0x8784,
+  0x2b1f, 0x877c, 0x2b07, 0x8774, 0x2aef, 0x876b, 0x2ad8, 0x8763,
+  0x2ac0, 0x875a, 0x2aa8, 0x8752, 0x2a91, 0x874a, 0x2a79, 0x8741,
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+  0x2a02, 0x8718, 0x29eb, 0x870f, 0x29d3, 0x8707, 0x29bb, 0x86ff,
+  0x29a3, 0x86f7, 0x298b, 0x86ef, 0x2974, 0x86e7, 0x295c, 0x86de,
+  0x2944, 0x86d6, 0x292c, 0x86ce, 0x2915, 0x86c6, 0x28fd, 0x86be,
+  0x28e5, 0x86b6, 0x28cd, 0x86ae, 0x28b5, 0x86a6, 0x289d, 0x869e,
+  0x2886, 0x8696, 0x286e, 0x868e, 0x2856, 0x8686, 0x283e, 0x867e,
+  0x2826, 0x8676, 0x280e, 0x866e, 0x27f6, 0x8667, 0x27df, 0x865f,
+  0x27c7, 0x8657, 0x27af, 0x864f, 0x2797, 0x8647, 0x277f, 0x8640,
+  0x2767, 0x8638, 0x274f, 0x8630, 0x2737, 0x8628, 0x271f, 0x8621,
+  0x2707, 0x8619, 0x26ef, 0x8611, 0x26d8, 0x860a, 0x26c0, 0x8602,
+  0x26a8, 0x85fb, 0x2690, 0x85f3, 0x2678, 0x85eb, 0x2660, 0x85e4,
+  0x2648, 0x85dc, 0x2630, 0x85d5, 0x2618, 0x85cd, 0x2600, 0x85c6,
+  0x25e8, 0x85be, 0x25d0, 0x85b7, 0x25b8, 0x85b0, 0x25a0, 0x85a8,
+  0x2588, 0x85a1, 0x2570, 0x8599, 0x2558, 0x8592, 0x2540, 0x858b,
+  0x2528, 0x8583, 0x250f, 0x857c, 0x24f7, 0x8575, 0x24df, 0x856e,
+  0x24c7, 0x8566, 0x24af, 0x855f, 0x2497, 0x8558, 0x247f, 0x8551,
+  0x2467, 0x854a, 0x244f, 0x8543, 0x2437, 0x853b, 0x241f, 0x8534,
+  0x2407, 0x852d, 0x23ee, 0x8526, 0x23d6, 0x851f, 0x23be, 0x8518,
+  0x23a6, 0x8511, 0x238e, 0x850a, 0x2376, 0x8503, 0x235e, 0x84fc,
+  0x2345, 0x84f5, 0x232d, 0x84ee, 0x2315, 0x84e7, 0x22fd, 0x84e1,
+  0x22e5, 0x84da, 0x22cd, 0x84d3, 0x22b4, 0x84cc, 0x229c, 0x84c5,
+  0x2284, 0x84be, 0x226c, 0x84b8, 0x2254, 0x84b1, 0x223b, 0x84aa,
+  0x2223, 0x84a3, 0x220b, 0x849d, 0x21f3, 0x8496, 0x21da, 0x848f,
+  0x21c2, 0x8489, 0x21aa, 0x8482, 0x2192, 0x847c, 0x2179, 0x8475,
+  0x2161, 0x846e, 0x2149, 0x8468, 0x2131, 0x8461, 0x2118, 0x845b,
+  0x2100, 0x8454, 0x20e8, 0x844e, 0x20d0, 0x8447, 0x20b7, 0x8441,
+  0x209f, 0x843b, 0x2087, 0x8434, 0x206e, 0x842e, 0x2056, 0x8427,
+  0x203e, 0x8421, 0x2025, 0x841b, 0x200d, 0x8415, 0x1ff5, 0x840e,
+  0x1fdc, 0x8408, 0x1fc4, 0x8402, 0x1fac, 0x83fb, 0x1f93, 0x83f5,
+  0x1f7b, 0x83ef, 0x1f63, 0x83e9, 0x1f4a, 0x83e3, 0x1f32, 0x83dd,
+  0x1f19, 0x83d7, 0x1f01, 0x83d0, 0x1ee9, 0x83ca, 0x1ed0, 0x83c4,
+  0x1eb8, 0x83be, 0x1ea0, 0x83b8, 0x1e87, 0x83b2, 0x1e6f, 0x83ac,
+  0x1e56, 0x83a6, 0x1e3e, 0x83a0, 0x1e25, 0x839a, 0x1e0d, 0x8394,
+  0x1df5, 0x838f, 0x1ddc, 0x8389, 0x1dc4, 0x8383, 0x1dab, 0x837d,
+  0x1d93, 0x8377, 0x1d7a, 0x8371, 0x1d62, 0x836c, 0x1d49, 0x8366,
+  0x1d31, 0x8360, 0x1d18, 0x835a, 0x1d00, 0x8355, 0x1ce8, 0x834f,
+  0x1ccf, 0x8349, 0x1cb7, 0x8344, 0x1c9e, 0x833e, 0x1c86, 0x8338,
+  0x1c6d, 0x8333, 0x1c55, 0x832d, 0x1c3c, 0x8328, 0x1c24, 0x8322,
+  0x1c0b, 0x831d, 0x1bf2, 0x8317, 0x1bda, 0x8312, 0x1bc1, 0x830c,
+  0x1ba9, 0x8307, 0x1b90, 0x8301, 0x1b78, 0x82fc, 0x1b5f, 0x82f7,
+  0x1b47, 0x82f1, 0x1b2e, 0x82ec, 0x1b16, 0x82e7, 0x1afd, 0x82e1,
+  0x1ae4, 0x82dc, 0x1acc, 0x82d7, 0x1ab3, 0x82d1, 0x1a9b, 0x82cc,
+  0x1a82, 0x82c7, 0x1a6a, 0x82c2, 0x1a51, 0x82bd, 0x1a38, 0x82b7,
+  0x1a20, 0x82b2, 0x1a07, 0x82ad, 0x19ef, 0x82a8, 0x19d6, 0x82a3,
+  0x19bd, 0x829e, 0x19a5, 0x8299, 0x198c, 0x8294, 0x1973, 0x828f,
+  0x195b, 0x828a, 0x1942, 0x8285, 0x192a, 0x8280, 0x1911, 0x827b,
+  0x18f8, 0x8276, 0x18e0, 0x8271, 0x18c7, 0x826c, 0x18ae, 0x8268,
+  0x1896, 0x8263, 0x187d, 0x825e, 0x1864, 0x8259, 0x184c, 0x8254,
+  0x1833, 0x8250, 0x181a, 0x824b, 0x1802, 0x8246, 0x17e9, 0x8241,
+  0x17d0, 0x823d, 0x17b7, 0x8238, 0x179f, 0x8233, 0x1786, 0x822f,
+  0x176d, 0x822a, 0x1755, 0x8226, 0x173c, 0x8221, 0x1723, 0x821c,
+  0x170a, 0x8218, 0x16f2, 0x8213, 0x16d9, 0x820f, 0x16c0, 0x820a,
+  0x16a8, 0x8206, 0x168f, 0x8201, 0x1676, 0x81fd, 0x165d, 0x81f9,
+  0x1645, 0x81f4, 0x162c, 0x81f0, 0x1613, 0x81ec, 0x15fa, 0x81e7,
+  0x15e2, 0x81e3, 0x15c9, 0x81df, 0x15b0, 0x81da, 0x1597, 0x81d6,
+  0x157f, 0x81d2, 0x1566, 0x81ce, 0x154d, 0x81c9, 0x1534, 0x81c5,
+  0x151b, 0x81c1, 0x1503, 0x81bd, 0x14ea, 0x81b9, 0x14d1, 0x81b5,
+  0x14b8, 0x81b1, 0x149f, 0x81ad, 0x1487, 0x81a9, 0x146e, 0x81a5,
+  0x1455, 0x81a1, 0x143c, 0x819d, 0x1423, 0x8199, 0x140b, 0x8195,
+  0x13f2, 0x8191, 0x13d9, 0x818d, 0x13c0, 0x8189, 0x13a7, 0x8185,
+  0x138e, 0x8181, 0x1376, 0x817d, 0x135d, 0x817a, 0x1344, 0x8176,
+  0x132b, 0x8172, 0x1312, 0x816e, 0x12f9, 0x816b, 0x12e0, 0x8167,
+  0x12c8, 0x8163, 0x12af, 0x815f, 0x1296, 0x815c, 0x127d, 0x8158,
+  0x1264, 0x8155, 0x124b, 0x8151, 0x1232, 0x814d, 0x1219, 0x814a,
+  0x1201, 0x8146, 0x11e8, 0x8143, 0x11cf, 0x813f, 0x11b6, 0x813c,
+  0x119d, 0x8138, 0x1184, 0x8135, 0x116b, 0x8131, 0x1152, 0x812e,
+  0x1139, 0x812b, 0x1121, 0x8127, 0x1108, 0x8124, 0x10ef, 0x8121,
+  0x10d6, 0x811d, 0x10bd, 0x811a, 0x10a4, 0x8117, 0x108b, 0x8113,
+  0x1072, 0x8110, 0x1059, 0x810d, 0x1040, 0x810a, 0x1027, 0x8107,
+  0x100e, 0x8103, 0xff5, 0x8100, 0xfdd, 0x80fd, 0xfc4, 0x80fa,
+  0xfab, 0x80f7, 0xf92, 0x80f4, 0xf79, 0x80f1, 0xf60, 0x80ee,
+  0xf47, 0x80eb, 0xf2e, 0x80e8, 0xf15, 0x80e5, 0xefc, 0x80e2,
+  0xee3, 0x80df, 0xeca, 0x80dc, 0xeb1, 0x80d9, 0xe98, 0x80d6,
+  0xe7f, 0x80d3, 0xe66, 0x80d1, 0xe4d, 0x80ce, 0xe34, 0x80cb,
+  0xe1b, 0x80c8, 0xe02, 0x80c5, 0xde9, 0x80c3, 0xdd0, 0x80c0,
+  0xdb7, 0x80bd, 0xd9e, 0x80bb, 0xd85, 0x80b8, 0xd6c, 0x80b5,
+  0xd53, 0x80b3, 0xd3a, 0x80b0, 0xd21, 0x80ad, 0xd08, 0x80ab,
+  0xcef, 0x80a8, 0xcd6, 0x80a6, 0xcbd, 0x80a3, 0xca4, 0x80a1,
+  0xc8b, 0x809e, 0xc72, 0x809c, 0xc59, 0x8099, 0xc40, 0x8097,
+  0xc27, 0x8095, 0xc0e, 0x8092, 0xbf5, 0x8090, 0xbdc, 0x808e,
+  0xbc3, 0x808b, 0xbaa, 0x8089, 0xb91, 0x8087, 0xb78, 0x8084,
+  0xb5f, 0x8082, 0xb46, 0x8080, 0xb2d, 0x807e, 0xb14, 0x807b,
+  0xafb, 0x8079, 0xae2, 0x8077, 0xac9, 0x8075, 0xab0, 0x8073,
+  0xa97, 0x8071, 0xa7e, 0x806f, 0xa65, 0x806d, 0xa4c, 0x806b,
+  0xa33, 0x8069, 0xa19, 0x8067, 0xa00, 0x8065, 0x9e7, 0x8063,
+  0x9ce, 0x8061, 0x9b5, 0x805f, 0x99c, 0x805d, 0x983, 0x805b,
+  0x96a, 0x8059, 0x951, 0x8057, 0x938, 0x8056, 0x91f, 0x8054,
+  0x906, 0x8052, 0x8ed, 0x8050, 0x8d4, 0x804f, 0x8bb, 0x804d,
+  0x8a2, 0x804b, 0x888, 0x8049, 0x86f, 0x8048, 0x856, 0x8046,
+  0x83d, 0x8044, 0x824, 0x8043, 0x80b, 0x8041, 0x7f2, 0x8040,
+  0x7d9, 0x803e, 0x7c0, 0x803d, 0x7a7, 0x803b, 0x78e, 0x803a,
+  0x775, 0x8038, 0x75b, 0x8037, 0x742, 0x8035, 0x729, 0x8034,
+  0x710, 0x8032, 0x6f7, 0x8031, 0x6de, 0x8030, 0x6c5, 0x802e,
+  0x6ac, 0x802d, 0x693, 0x802c, 0x67a, 0x802a, 0x660, 0x8029,
+  0x647, 0x8028, 0x62e, 0x8027, 0x615, 0x8026, 0x5fc, 0x8024,
+  0x5e3, 0x8023, 0x5ca, 0x8022, 0x5b1, 0x8021, 0x598, 0x8020,
+  0x57f, 0x801f, 0x565, 0x801e, 0x54c, 0x801d, 0x533, 0x801c,
+  0x51a, 0x801b, 0x501, 0x801a, 0x4e8, 0x8019, 0x4cf, 0x8018,
+  0x4b6, 0x8017, 0x49c, 0x8016, 0x483, 0x8015, 0x46a, 0x8014,
+  0x451, 0x8013, 0x438, 0x8012, 0x41f, 0x8012, 0x406, 0x8011,
+  0x3ed, 0x8010, 0x3d4, 0x800f, 0x3ba, 0x800e, 0x3a1, 0x800e,
+  0x388, 0x800d, 0x36f, 0x800c, 0x356, 0x800c, 0x33d, 0x800b,
+  0x324, 0x800a, 0x30b, 0x800a, 0x2f1, 0x8009, 0x2d8, 0x8009,
+  0x2bf, 0x8008, 0x2a6, 0x8008, 0x28d, 0x8007, 0x274, 0x8007,
+  0x25b, 0x8006, 0x242, 0x8006, 0x228, 0x8005, 0x20f, 0x8005,
+  0x1f6, 0x8004, 0x1dd, 0x8004, 0x1c4, 0x8004, 0x1ab, 0x8003,
+  0x192, 0x8003, 0x178, 0x8003, 0x15f, 0x8002, 0x146, 0x8002,
+  0x12d, 0x8002, 0x114, 0x8002, 0xfb, 0x8001, 0xe2, 0x8001,
+  0xc9, 0x8001, 0xaf, 0x8001, 0x96, 0x8001, 0x7d, 0x8001,
+  0x64, 0x8001, 0x4b, 0x8001, 0x32, 0x8001, 0x19, 0x8001,
+};
+
+/**   
+* \par   
+* cosFactor tables are generated using the formula : 
 cos_factors[n] = 2 * cos((2n+1)*pi/(4*N)) 
   
+* \par   
+* C command to generate the table   
+* 
   
+* for(i = 0; i< N; i++)   
+* {   
+*   cos_factors[i]= 2 * cos((2*i+1)*c/2);   
+* } 
   
+* \par   
+* where N is the number of factors to generate and c is pi/(2*N)   
+* \par   
+* Then converted to q15 format by multiplying with 2^31 and saturated if required.   
+   
+*/
+
+static const q15_t cos_factorsQ15_128[128] = {
+  0x7fff, 0x7ffa, 0x7ff0, 0x7fe1, 0x7fce, 0x7fb5, 0x7f97, 0x7f75,
+  0x7f4d, 0x7f21, 0x7ef0, 0x7eba, 0x7e7f, 0x7e3f, 0x7dfa, 0x7db0,
+  0x7d62, 0x7d0f, 0x7cb7, 0x7c5a, 0x7bf8, 0x7b92, 0x7b26, 0x7ab6,
+  0x7a42, 0x79c8, 0x794a, 0x78c7, 0x7840, 0x77b4, 0x7723, 0x768e,
+  0x75f4, 0x7555, 0x74b2, 0x740b, 0x735f, 0x72af, 0x71fa, 0x7141,
+  0x7083, 0x6fc1, 0x6efb, 0x6e30, 0x6d62, 0x6c8f, 0x6bb8, 0x6adc,
+  0x69fd, 0x6919, 0x6832, 0x6746, 0x6657, 0x6563, 0x646c, 0x6371,
+  0x6271, 0x616f, 0x6068, 0x5f5e, 0x5e50, 0x5d3e, 0x5c29, 0x5b10,
+  0x59f3, 0x58d4, 0x57b0, 0x568a, 0x5560, 0x5433, 0x5302, 0x51ce,
+  0x5097, 0x4f5e, 0x4e21, 0x4ce1, 0x4b9e, 0x4a58, 0x490f, 0x47c3,
+  0x4675, 0x4524, 0x43d0, 0x427a, 0x4121, 0x3fc5, 0x3e68, 0x3d07,
+  0x3ba5, 0x3a40, 0x38d8, 0x376f, 0x3604, 0x3496, 0x3326, 0x31b5,
+  0x3041, 0x2ecc, 0x2d55, 0x2bdc, 0x2a61, 0x28e5, 0x2767, 0x25e8,
+  0x2467, 0x22e5, 0x2161, 0x1fdc, 0x1e56, 0x1ccf, 0x1b47, 0x19bd,
+  0x1833, 0x16a8, 0x151b, 0x138e, 0x1201, 0x1072, 0xee3, 0xd53,
+  0xbc3, 0xa33, 0x8a2, 0x710, 0x57f, 0x3ed, 0x25b, 0xc9
+};
+
+static const q15_t cos_factorsQ15_512[512] = {
+  0x7fff, 0x7fff, 0x7fff, 0x7ffe, 0x7ffc, 0x7ffb, 0x7ff9, 0x7ff7,
+  0x7ff4, 0x7ff2, 0x7fee, 0x7feb, 0x7fe7, 0x7fe3, 0x7fdf, 0x7fda,
+  0x7fd6, 0x7fd0, 0x7fcb, 0x7fc5, 0x7fbf, 0x7fb8, 0x7fb1, 0x7faa,
+  0x7fa3, 0x7f9b, 0x7f93, 0x7f8b, 0x7f82, 0x7f79, 0x7f70, 0x7f67,
+  0x7f5d, 0x7f53, 0x7f48, 0x7f3d, 0x7f32, 0x7f27, 0x7f1b, 0x7f0f,
+  0x7f03, 0x7ef6, 0x7ee9, 0x7edc, 0x7ecf, 0x7ec1, 0x7eb3, 0x7ea4,
+  0x7e95, 0x7e86, 0x7e77, 0x7e67, 0x7e57, 0x7e47, 0x7e37, 0x7e26,
+  0x7e14, 0x7e03, 0x7df1, 0x7ddf, 0x7dcd, 0x7dba, 0x7da7, 0x7d94,
+  0x7d80, 0x7d6c, 0x7d58, 0x7d43, 0x7d2f, 0x7d19, 0x7d04, 0x7cee,
+  0x7cd8, 0x7cc2, 0x7cab, 0x7c94, 0x7c7d, 0x7c66, 0x7c4e, 0x7c36,
+  0x7c1d, 0x7c05, 0x7beb, 0x7bd2, 0x7bb9, 0x7b9f, 0x7b84, 0x7b6a,
+  0x7b4f, 0x7b34, 0x7b19, 0x7afd, 0x7ae1, 0x7ac5, 0x7aa8, 0x7a8b,
+  0x7a6e, 0x7a50, 0x7a33, 0x7a15, 0x79f6, 0x79d8, 0x79b9, 0x7999,
+  0x797a, 0x795a, 0x793a, 0x7919, 0x78f9, 0x78d8, 0x78b6, 0x7895,
+  0x7873, 0x7851, 0x782e, 0x780c, 0x77e9, 0x77c5, 0x77a2, 0x777e,
+  0x775a, 0x7735, 0x7710, 0x76eb, 0x76c6, 0x76a0, 0x767b, 0x7654,
+  0x762e, 0x7607, 0x75e0, 0x75b9, 0x7591, 0x7569, 0x7541, 0x7519,
+  0x74f0, 0x74c7, 0x749e, 0x7474, 0x744a, 0x7420, 0x73f6, 0x73cb,
+  0x73a0, 0x7375, 0x7349, 0x731d, 0x72f1, 0x72c5, 0x7298, 0x726b,
+  0x723e, 0x7211, 0x71e3, 0x71b5, 0x7186, 0x7158, 0x7129, 0x70fa,
+  0x70cb, 0x709b, 0x706b, 0x703b, 0x700a, 0x6fda, 0x6fa9, 0x6f77,
+  0x6f46, 0x6f14, 0x6ee2, 0x6eaf, 0x6e7d, 0x6e4a, 0x6e17, 0x6de3,
+  0x6db0, 0x6d7c, 0x6d48, 0x6d13, 0x6cde, 0x6ca9, 0x6c74, 0x6c3f,
+  0x6c09, 0x6bd3, 0x6b9c, 0x6b66, 0x6b2f, 0x6af8, 0x6ac1, 0x6a89,
+  0x6a51, 0x6a19, 0x69e1, 0x69a8, 0x696f, 0x6936, 0x68fd, 0x68c3,
+  0x6889, 0x684f, 0x6815, 0x67da, 0x679f, 0x6764, 0x6729, 0x66ed,
+  0x66b1, 0x6675, 0x6639, 0x65fc, 0x65bf, 0x6582, 0x6545, 0x6507,
+  0x64c9, 0x648b, 0x644d, 0x640e, 0x63cf, 0x6390, 0x6351, 0x6311,
+  0x62d2, 0x6292, 0x6251, 0x6211, 0x61d0, 0x618f, 0x614e, 0x610d,
+  0x60cb, 0x6089, 0x6047, 0x6004, 0x5fc2, 0x5f7f, 0x5f3c, 0x5ef9,
+  0x5eb5, 0x5e71, 0x5e2d, 0x5de9, 0x5da5, 0x5d60, 0x5d1b, 0x5cd6,
+  0x5c91, 0x5c4b, 0x5c06, 0x5bc0, 0x5b79, 0x5b33, 0x5aec, 0x5aa5,
+  0x5a5e, 0x5a17, 0x59d0, 0x5988, 0x5940, 0x58f8, 0x58af, 0x5867,
+  0x581e, 0x57d5, 0x578c, 0x5742, 0x56f9, 0x56af, 0x5665, 0x561a,
+  0x55d0, 0x5585, 0x553a, 0x54ef, 0x54a4, 0x5458, 0x540d, 0x53c1,
+  0x5375, 0x5328, 0x52dc, 0x528f, 0x5242, 0x51f5, 0x51a8, 0x515a,
+  0x510c, 0x50bf, 0x5070, 0x5022, 0x4fd4, 0x4f85, 0x4f36, 0x4ee7,
+  0x4e98, 0x4e48, 0x4df9, 0x4da9, 0x4d59, 0x4d09, 0x4cb8, 0x4c68,
+  0x4c17, 0x4bc6, 0x4b75, 0x4b24, 0x4ad2, 0x4a81, 0x4a2f, 0x49dd,
+  0x498a, 0x4938, 0x48e6, 0x4893, 0x4840, 0x47ed, 0x479a, 0x4746,
+  0x46f3, 0x469f, 0x464b, 0x45f7, 0x45a3, 0x454e, 0x44fa, 0x44a5,
+  0x4450, 0x43fb, 0x43a5, 0x4350, 0x42fa, 0x42a5, 0x424f, 0x41f9,
+  0x41a2, 0x414c, 0x40f6, 0x409f, 0x4048, 0x3ff1, 0x3f9a, 0x3f43,
+  0x3eeb, 0x3e93, 0x3e3c, 0x3de4, 0x3d8c, 0x3d33, 0x3cdb, 0x3c83,
+  0x3c2a, 0x3bd1, 0x3b78, 0x3b1f, 0x3ac6, 0x3a6c, 0x3a13, 0x39b9,
+  0x395f, 0x3906, 0x38ab, 0x3851, 0x37f7, 0x379c, 0x3742, 0x36e7,
+  0x368c, 0x3631, 0x35d6, 0x357b, 0x351f, 0x34c4, 0x3468, 0x340c,
+  0x33b0, 0x3354, 0x32f8, 0x329c, 0x3240, 0x31e3, 0x3186, 0x312a,
+  0x30cd, 0x3070, 0x3013, 0x2fb5, 0x2f58, 0x2efb, 0x2e9d, 0x2e3f,
+  0x2de2, 0x2d84, 0x2d26, 0x2cc8, 0x2c69, 0x2c0b, 0x2bad, 0x2b4e,
+  0x2aef, 0x2a91, 0x2a32, 0x29d3, 0x2974, 0x2915, 0x28b5, 0x2856,
+  0x27f6, 0x2797, 0x2737, 0x26d8, 0x2678, 0x2618, 0x25b8, 0x2558,
+  0x24f7, 0x2497, 0x2437, 0x23d6, 0x2376, 0x2315, 0x22b4, 0x2254,
+  0x21f3, 0x2192, 0x2131, 0x20d0, 0x206e, 0x200d, 0x1fac, 0x1f4a,
+  0x1ee9, 0x1e87, 0x1e25, 0x1dc4, 0x1d62, 0x1d00, 0x1c9e, 0x1c3c,
+  0x1bda, 0x1b78, 0x1b16, 0x1ab3, 0x1a51, 0x19ef, 0x198c, 0x192a,
+  0x18c7, 0x1864, 0x1802, 0x179f, 0x173c, 0x16d9, 0x1676, 0x1613,
+  0x15b0, 0x154d, 0x14ea, 0x1487, 0x1423, 0x13c0, 0x135d, 0x12f9,
+  0x1296, 0x1232, 0x11cf, 0x116b, 0x1108, 0x10a4, 0x1040, 0xfdd,
+  0xf79, 0xf15, 0xeb1, 0xe4d, 0xde9, 0xd85, 0xd21, 0xcbd,
+  0xc59, 0xbf5, 0xb91, 0xb2d, 0xac9, 0xa65, 0xa00, 0x99c,
+  0x938, 0x8d4, 0x86f, 0x80b, 0x7a7, 0x742, 0x6de, 0x67a,
+  0x615, 0x5b1, 0x54c, 0x4e8, 0x483, 0x41f, 0x3ba, 0x356,
+  0x2f1, 0x28d, 0x228, 0x1c4, 0x15f, 0xfb, 0x96, 0x32,
+};
+
+static const q15_t cos_factorsQ15_2048[2048] = {
+  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+  0x7fff, 0x7fff, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffd, 0x7ffd,
+  0x7ffd, 0x7ffd, 0x7ffc, 0x7ffc, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffa,
+  0x7ffa, 0x7ff9, 0x7ff9, 0x7ff8, 0x7ff8, 0x7ff7, 0x7ff7, 0x7ff6,
+  0x7ff5, 0x7ff5, 0x7ff4, 0x7ff3, 0x7ff3, 0x7ff2, 0x7ff1, 0x7ff0,
+  0x7ff0, 0x7fef, 0x7fee, 0x7fed, 0x7fec, 0x7fec, 0x7feb, 0x7fea,
+  0x7fe9, 0x7fe8, 0x7fe7, 0x7fe6, 0x7fe5, 0x7fe4, 0x7fe3, 0x7fe2,
+  0x7fe1, 0x7fe0, 0x7fdf, 0x7fdd, 0x7fdc, 0x7fdb, 0x7fda, 0x7fd9,
+  0x7fd7, 0x7fd6, 0x7fd5, 0x7fd4, 0x7fd2, 0x7fd1, 0x7fd0, 0x7fce,
+  0x7fcd, 0x7fcb, 0x7fca, 0x7fc9, 0x7fc7, 0x7fc6, 0x7fc4, 0x7fc3,
+  0x7fc1, 0x7fc0, 0x7fbe, 0x7fbc, 0x7fbb, 0x7fb9, 0x7fb7, 0x7fb6,
+  0x7fb4, 0x7fb2, 0x7fb1, 0x7faf, 0x7fad, 0x7fab, 0x7fa9, 0x7fa8,
+  0x7fa6, 0x7fa4, 0x7fa2, 0x7fa0, 0x7f9e, 0x7f9c, 0x7f9a, 0x7f98,
+  0x7f96, 0x7f94, 0x7f92, 0x7f90, 0x7f8e, 0x7f8c, 0x7f8a, 0x7f88,
+  0x7f86, 0x7f83, 0x7f81, 0x7f7f, 0x7f7d, 0x7f7b, 0x7f78, 0x7f76,
+  0x7f74, 0x7f71, 0x7f6f, 0x7f6d, 0x7f6a, 0x7f68, 0x7f65, 0x7f63,
+  0x7f60, 0x7f5e, 0x7f5b, 0x7f59, 0x7f56, 0x7f54, 0x7f51, 0x7f4f,
+  0x7f4c, 0x7f49, 0x7f47, 0x7f44, 0x7f41, 0x7f3f, 0x7f3c, 0x7f39,
+  0x7f36, 0x7f34, 0x7f31, 0x7f2e, 0x7f2b, 0x7f28, 0x7f25, 0x7f23,
+  0x7f20, 0x7f1d, 0x7f1a, 0x7f17, 0x7f14, 0x7f11, 0x7f0e, 0x7f0b,
+  0x7f08, 0x7f04, 0x7f01, 0x7efe, 0x7efb, 0x7ef8, 0x7ef5, 0x7ef1,
+  0x7eee, 0x7eeb, 0x7ee8, 0x7ee4, 0x7ee1, 0x7ede, 0x7eda, 0x7ed7,
+  0x7ed4, 0x7ed0, 0x7ecd, 0x7ec9, 0x7ec6, 0x7ec3, 0x7ebf, 0x7ebb,
+  0x7eb8, 0x7eb4, 0x7eb1, 0x7ead, 0x7eaa, 0x7ea6, 0x7ea2, 0x7e9f,
+  0x7e9b, 0x7e97, 0x7e94, 0x7e90, 0x7e8c, 0x7e88, 0x7e84, 0x7e81,
+  0x7e7d, 0x7e79, 0x7e75, 0x7e71, 0x7e6d, 0x7e69, 0x7e65, 0x7e61,
+  0x7e5d, 0x7e59, 0x7e55, 0x7e51, 0x7e4d, 0x7e49, 0x7e45, 0x7e41,
+  0x7e3d, 0x7e39, 0x7e34, 0x7e30, 0x7e2c, 0x7e28, 0x7e24, 0x7e1f,
+  0x7e1b, 0x7e17, 0x7e12, 0x7e0e, 0x7e0a, 0x7e05, 0x7e01, 0x7dfc,
+  0x7df8, 0x7df3, 0x7def, 0x7dea, 0x7de6, 0x7de1, 0x7ddd, 0x7dd8,
+  0x7dd4, 0x7dcf, 0x7dca, 0x7dc6, 0x7dc1, 0x7dbc, 0x7db8, 0x7db3,
+  0x7dae, 0x7da9, 0x7da5, 0x7da0, 0x7d9b, 0x7d96, 0x7d91, 0x7d8c,
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+  0x431b, 0x4305, 0x42f0, 0x42da, 0x42c5, 0x42af, 0x429a, 0x4284,
+  0x426f, 0x425a, 0x4244, 0x422f, 0x4219, 0x4203, 0x41ee, 0x41d8,
+  0x41c3, 0x41ad, 0x4198, 0x4182, 0x416d, 0x4157, 0x4141, 0x412c,
+  0x4116, 0x4100, 0x40eb, 0x40d5, 0x40bf, 0x40aa, 0x4094, 0x407e,
+  0x4069, 0x4053, 0x403d, 0x4027, 0x4012, 0x3ffc, 0x3fe6, 0x3fd0,
+  0x3fbb, 0x3fa5, 0x3f8f, 0x3f79, 0x3f63, 0x3f4d, 0x3f38, 0x3f22,
+  0x3f0c, 0x3ef6, 0x3ee0, 0x3eca, 0x3eb4, 0x3e9e, 0x3e88, 0x3e73,
+  0x3e5d, 0x3e47, 0x3e31, 0x3e1b, 0x3e05, 0x3def, 0x3dd9, 0x3dc3,
+  0x3dad, 0x3d97, 0x3d81, 0x3d6b, 0x3d55, 0x3d3e, 0x3d28, 0x3d12,
+  0x3cfc, 0x3ce6, 0x3cd0, 0x3cba, 0x3ca4, 0x3c8e, 0x3c77, 0x3c61,
+  0x3c4b, 0x3c35, 0x3c1f, 0x3c09, 0x3bf2, 0x3bdc, 0x3bc6, 0x3bb0,
+  0x3b99, 0x3b83, 0x3b6d, 0x3b57, 0x3b40, 0x3b2a, 0x3b14, 0x3afe,
+  0x3ae7, 0x3ad1, 0x3abb, 0x3aa4, 0x3a8e, 0x3a78, 0x3a61, 0x3a4b,
+  0x3a34, 0x3a1e, 0x3a08, 0x39f1, 0x39db, 0x39c4, 0x39ae, 0x3998,
+  0x3981, 0x396b, 0x3954, 0x393e, 0x3927, 0x3911, 0x38fa, 0x38e4,
+  0x38cd, 0x38b7, 0x38a0, 0x388a, 0x3873, 0x385d, 0x3846, 0x382f,
+  0x3819, 0x3802, 0x37ec, 0x37d5, 0x37be, 0x37a8, 0x3791, 0x377a,
+  0x3764, 0x374d, 0x3736, 0x3720, 0x3709, 0x36f2, 0x36dc, 0x36c5,
+  0x36ae, 0x3698, 0x3681, 0x366a, 0x3653, 0x363d, 0x3626, 0x360f,
+  0x35f8, 0x35e1, 0x35cb, 0x35b4, 0x359d, 0x3586, 0x356f, 0x3558,
+  0x3542, 0x352b, 0x3514, 0x34fd, 0x34e6, 0x34cf, 0x34b8, 0x34a1,
+  0x348b, 0x3474, 0x345d, 0x3446, 0x342f, 0x3418, 0x3401, 0x33ea,
+  0x33d3, 0x33bc, 0x33a5, 0x338e, 0x3377, 0x3360, 0x3349, 0x3332,
+  0x331b, 0x3304, 0x32ed, 0x32d6, 0x32bf, 0x32a8, 0x3290, 0x3279,
+  0x3262, 0x324b, 0x3234, 0x321d, 0x3206, 0x31ef, 0x31d8, 0x31c0,
+  0x31a9, 0x3192, 0x317b, 0x3164, 0x314c, 0x3135, 0x311e, 0x3107,
+  0x30f0, 0x30d8, 0x30c1, 0x30aa, 0x3093, 0x307b, 0x3064, 0x304d,
+  0x3036, 0x301e, 0x3007, 0x2ff0, 0x2fd8, 0x2fc1, 0x2faa, 0x2f92,
+  0x2f7b, 0x2f64, 0x2f4c, 0x2f35, 0x2f1e, 0x2f06, 0x2eef, 0x2ed8,
+  0x2ec0, 0x2ea9, 0x2e91, 0x2e7a, 0x2e63, 0x2e4b, 0x2e34, 0x2e1c,
+  0x2e05, 0x2ded, 0x2dd6, 0x2dbe, 0x2da7, 0x2d8f, 0x2d78, 0x2d60,
+  0x2d49, 0x2d31, 0x2d1a, 0x2d02, 0x2ceb, 0x2cd3, 0x2cbc, 0x2ca4,
+  0x2c8d, 0x2c75, 0x2c5e, 0x2c46, 0x2c2e, 0x2c17, 0x2bff, 0x2be8,
+  0x2bd0, 0x2bb8, 0x2ba1, 0x2b89, 0x2b71, 0x2b5a, 0x2b42, 0x2b2b,
+  0x2b13, 0x2afb, 0x2ae4, 0x2acc, 0x2ab4, 0x2a9c, 0x2a85, 0x2a6d,
+  0x2a55, 0x2a3e, 0x2a26, 0x2a0e, 0x29f6, 0x29df, 0x29c7, 0x29af,
+  0x2997, 0x2980, 0x2968, 0x2950, 0x2938, 0x2920, 0x2909, 0x28f1,
+  0x28d9, 0x28c1, 0x28a9, 0x2892, 0x287a, 0x2862, 0x284a, 0x2832,
+  0x281a, 0x2802, 0x27eb, 0x27d3, 0x27bb, 0x27a3, 0x278b, 0x2773,
+  0x275b, 0x2743, 0x272b, 0x2713, 0x26fb, 0x26e4, 0x26cc, 0x26b4,
+  0x269c, 0x2684, 0x266c, 0x2654, 0x263c, 0x2624, 0x260c, 0x25f4,
+  0x25dc, 0x25c4, 0x25ac, 0x2594, 0x257c, 0x2564, 0x254c, 0x2534,
+  0x251c, 0x2503, 0x24eb, 0x24d3, 0x24bb, 0x24a3, 0x248b, 0x2473,
+  0x245b, 0x2443, 0x242b, 0x2413, 0x23fa, 0x23e2, 0x23ca, 0x23b2,
+  0x239a, 0x2382, 0x236a, 0x2352, 0x2339, 0x2321, 0x2309, 0x22f1,
+  0x22d9, 0x22c0, 0x22a8, 0x2290, 0x2278, 0x2260, 0x2247, 0x222f,
+  0x2217, 0x21ff, 0x21e7, 0x21ce, 0x21b6, 0x219e, 0x2186, 0x216d,
+  0x2155, 0x213d, 0x2125, 0x210c, 0x20f4, 0x20dc, 0x20c3, 0x20ab,
+  0x2093, 0x207a, 0x2062, 0x204a, 0x2032, 0x2019, 0x2001, 0x1fe9,
+  0x1fd0, 0x1fb8, 0x1f9f, 0x1f87, 0x1f6f, 0x1f56, 0x1f3e, 0x1f26,
+  0x1f0d, 0x1ef5, 0x1edd, 0x1ec4, 0x1eac, 0x1e93, 0x1e7b, 0x1e62,
+  0x1e4a, 0x1e32, 0x1e19, 0x1e01, 0x1de8, 0x1dd0, 0x1db7, 0x1d9f,
+  0x1d87, 0x1d6e, 0x1d56, 0x1d3d, 0x1d25, 0x1d0c, 0x1cf4, 0x1cdb,
+  0x1cc3, 0x1caa, 0x1c92, 0x1c79, 0x1c61, 0x1c48, 0x1c30, 0x1c17,
+  0x1bff, 0x1be6, 0x1bce, 0x1bb5, 0x1b9d, 0x1b84, 0x1b6c, 0x1b53,
+  0x1b3a, 0x1b22, 0x1b09, 0x1af1, 0x1ad8, 0x1ac0, 0x1aa7, 0x1a8e,
+  0x1a76, 0x1a5d, 0x1a45, 0x1a2c, 0x1a13, 0x19fb, 0x19e2, 0x19ca,
+  0x19b1, 0x1998, 0x1980, 0x1967, 0x194e, 0x1936, 0x191d, 0x1905,
+  0x18ec, 0x18d3, 0x18bb, 0x18a2, 0x1889, 0x1871, 0x1858, 0x183f,
+  0x1827, 0x180e, 0x17f5, 0x17dd, 0x17c4, 0x17ab, 0x1792, 0x177a,
+  0x1761, 0x1748, 0x1730, 0x1717, 0x16fe, 0x16e5, 0x16cd, 0x16b4,
+  0x169b, 0x1682, 0x166a, 0x1651, 0x1638, 0x161f, 0x1607, 0x15ee,
+  0x15d5, 0x15bc, 0x15a4, 0x158b, 0x1572, 0x1559, 0x1541, 0x1528,
+  0x150f, 0x14f6, 0x14dd, 0x14c5, 0x14ac, 0x1493, 0x147a, 0x1461,
+  0x1449, 0x1430, 0x1417, 0x13fe, 0x13e5, 0x13cc, 0x13b4, 0x139b,
+  0x1382, 0x1369, 0x1350, 0x1337, 0x131f, 0x1306, 0x12ed, 0x12d4,
+  0x12bb, 0x12a2, 0x1289, 0x1271, 0x1258, 0x123f, 0x1226, 0x120d,
+  0x11f4, 0x11db, 0x11c2, 0x11a9, 0x1191, 0x1178, 0x115f, 0x1146,
+  0x112d, 0x1114, 0x10fb, 0x10e2, 0x10c9, 0x10b0, 0x1098, 0x107f,
+  0x1066, 0x104d, 0x1034, 0x101b, 0x1002, 0xfe9, 0xfd0, 0xfb7,
+  0xf9e, 0xf85, 0xf6c, 0xf53, 0xf3a, 0xf21, 0xf08, 0xef0,
+  0xed7, 0xebe, 0xea5, 0xe8c, 0xe73, 0xe5a, 0xe41, 0xe28,
+  0xe0f, 0xdf6, 0xddd, 0xdc4, 0xdab, 0xd92, 0xd79, 0xd60,
+  0xd47, 0xd2e, 0xd15, 0xcfc, 0xce3, 0xcca, 0xcb1, 0xc98,
+  0xc7f, 0xc66, 0xc4d, 0xc34, 0xc1b, 0xc02, 0xbe9, 0xbd0,
+  0xbb7, 0xb9e, 0xb85, 0xb6c, 0xb53, 0xb3a, 0xb20, 0xb07,
+  0xaee, 0xad5, 0xabc, 0xaa3, 0xa8a, 0xa71, 0xa58, 0xa3f,
+  0xa26, 0xa0d, 0x9f4, 0x9db, 0x9c2, 0x9a9, 0x990, 0x977,
+  0x95e, 0x944, 0x92b, 0x912, 0x8f9, 0x8e0, 0x8c7, 0x8ae,
+  0x895, 0x87c, 0x863, 0x84a, 0x831, 0x818, 0x7fe, 0x7e5,
+  0x7cc, 0x7b3, 0x79a, 0x781, 0x768, 0x74f, 0x736, 0x71d,
+  0x704, 0x6ea, 0x6d1, 0x6b8, 0x69f, 0x686, 0x66d, 0x654,
+  0x63b, 0x622, 0x609, 0x5ef, 0x5d6, 0x5bd, 0x5a4, 0x58b,
+  0x572, 0x559, 0x540, 0x527, 0x50d, 0x4f4, 0x4db, 0x4c2,
+  0x4a9, 0x490, 0x477, 0x45e, 0x445, 0x42b, 0x412, 0x3f9,
+  0x3e0, 0x3c7, 0x3ae, 0x395, 0x37c, 0x362, 0x349, 0x330,
+  0x317, 0x2fe, 0x2e5, 0x2cc, 0x2b3, 0x299, 0x280, 0x267,
+  0x24e, 0x235, 0x21c, 0x203, 0x1ea, 0x1d0, 0x1b7, 0x19e,
+  0x185, 0x16c, 0x153, 0x13a, 0x121, 0x107, 0xee, 0xd5,
+  0xbc, 0xa3, 0x8a, 0x71, 0x57, 0x3e, 0x25, 0xc,
+
+};
+
+/**   
+ * @brief  Initialization function for the Q15 DCT4/IDCT4.  
+ * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.  
+ * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.  
+ * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.  
+ * @param[in]     N          length of the DCT4.  
+ * @param[in]     Nby2       half of the length of the DCT4.  
+ * @param[in]     normalize  normalizing factor.  
+ * @return  	  arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.  
+ * \par Normalizing factor:   
+ * The normalizing factor is sqrt(2/N), which depends on the size of transform N.   
+ * Normalizing factors in 1.15 format are mentioned in the table below for different DCT sizes:   
+ * \image html dct4NormalizingQ15Table.gif   
+ */
+
+arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /* Initializing the pointer array with the weight table base addresses of different lengths */
+  q15_t *twiddlePtr[3] = { (q15_t *) WeightsQ15_128, (q15_t *) WeightsQ15_512,
+    (q15_t *) WeightsQ15_2048
+  };
+
+  /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+  q15_t *pCosFactor[3] =
+    { (q15_t *) cos_factorsQ15_128, (q15_t *) cos_factorsQ15_512,
+    (q15_t *) cos_factorsQ15_2048
+  };
+
+  /* Initialize the DCT4 length */
+  S->N = N;
+
+  /* Initialize the half of DCT4 length */
+  S->Nby2 = Nby2;
+
+  /* Initialize the DCT4 Normalizing factor */
+  S->normalize = normalize;
+
+  /* Initialize Real FFT Instance */
+  S->pRfft = S_RFFT;
+
+  /* Initialize Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  switch (N)
+  {
+    /* Initialize the table modifier values */
+  case 2048u:
+    S->pTwiddle = twiddlePtr[2];
+    S->pCosFactor = pCosFactor[2];
+    break;
+  case 512u:
+    S->pTwiddle = twiddlePtr[1];
+    S->pCosFactor = pCosFactor[1];
+    break;
+  case 128u:
+    S->pTwiddle = twiddlePtr[0];
+    S->pCosFactor = pCosFactor[0];
+    break;
+  default:
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+
+  /* Initialize the RFFT/RIFFT */
+  arm_rfft_init_q15(S->pRfft, S->pCfft, S->N, 0u, 1u);
+
+  /* return the status of DCT4 Init function */
+  return (status);
+}
+
+/**   
+   * @} end of DCT4_IDCT4 group   
+   */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c
new file mode 100644
index 000000000..62ac374ab
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c
@@ -0,0 +1,2198 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_dct4_init_q31.c   
+*   
+* Description:	Initialization function of DCT-4 & IDCT4 Q31   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup DCT4_IDCT4   
+ * @{   
+ */
+
+/*   
+* @brief  Weights Table   
+*/
+
+/**   
+* \par   
+* Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
   
+* \par   
+* C command to generate the table   
+* 
   
+* for(i = 0; i< N; i++)   
+* {   
+*   weights[2*i]= cos(i*c);   
+*   weights[(2*i)+1]= -sin(i * c);   
+* } 
   
+* \par   
+* where N is the Number of weights to be calculated and c is pi/(2*N)   
+* \par   
+* Convert the output to q31 format by multiplying with 2^31 and saturated if required.   
+* \par   
+* In the tables below the real and imaginary values are placed alternatively, hence the   
+* array length is 2*N.   
+*/
+
+static const q31_t WeightsQ31_128[256] = {
+  0x7fffffff, 0x0, 0x7ffd885a, 0xfe6de2e0, 0x7ff62182, 0xfcdbd541, 0x7fe9cbc0,
+  0xfb49e6a3,
+  0x7fd8878e, 0xf9b82684, 0x7fc25596, 0xf826a462, 0x7fa736b4, 0xf6956fb7,
+  0x7f872bf3, 0xf50497fb,
+  0x7f62368f, 0xf3742ca2, 0x7f3857f6, 0xf1e43d1c, 0x7f0991c4, 0xf054d8d5,
+  0x7ed5e5c6, 0xeec60f31,
+  0x7e9d55fc, 0xed37ef91, 0x7e5fe493, 0xebaa894f, 0x7e1d93ea, 0xea1debbb,
+  0x7dd6668f, 0xe8922622,
+  0x7d8a5f40, 0xe70747c4, 0x7d3980ec, 0xe57d5fda, 0x7ce3ceb2, 0xe3f47d96,
+  0x7c894bde, 0xe26cb01b,
+  0x7c29fbee, 0xe0e60685, 0x7bc5e290, 0xdf608fe4, 0x7b5d039e, 0xdddc5b3b,
+  0x7aef6323, 0xdc597781,
+  0x7a7d055b, 0xdad7f3a2, 0x7a05eead, 0xd957de7a, 0x798a23b1, 0xd7d946d8,
+  0x7909a92d, 0xd65c3b7b,
+  0x78848414, 0xd4e0cb15, 0x77fab989, 0xd3670446, 0x776c4edb, 0xd1eef59e,
+  0x76d94989, 0xd078ad9e,
+  0x7641af3d, 0xcf043ab3, 0x75a585cf, 0xcd91ab39, 0x7504d345, 0xcc210d79,
+  0x745f9dd1, 0xcab26fa9,
+  0x73b5ebd1, 0xc945dfec, 0x7307c3d0, 0xc7db6c50, 0x72552c85, 0xc67322ce,
+  0x719e2cd2, 0xc50d1149,
+  0x70e2cbc6, 0xc3a94590, 0x7023109a, 0xc247cd5a, 0x6f5f02b2, 0xc0e8b648,
+  0x6e96a99d, 0xbf8c0de3,
+  0x6dca0d14, 0xbe31e19b, 0x6cf934fc, 0xbcda3ecb, 0x6c242960, 0xbb8532b0,
+  0x6b4af279, 0xba32ca71,
+  0x6a6d98a4, 0xb8e31319, 0x698c246c, 0xb796199b, 0x68a69e81, 0xb64beacd,
+  0x67bd0fbd, 0xb5049368,
+  0x66cf8120, 0xb3c0200c, 0x65ddfbd3, 0xb27e9d3c, 0x64e88926, 0xb140175b,
+  0x63ef3290, 0xb0049ab3,
+  0x62f201ac, 0xaecc336c, 0x61f1003f, 0xad96ed92, 0x60ec3830, 0xac64d510,
+  0x5fe3b38d, 0xab35f5b5,
+  0x5ed77c8a, 0xaa0a5b2e, 0x5dc79d7c, 0xa8e21106, 0x5cb420e0, 0xa7bd22ac,
+  0x5b9d1154, 0xa69b9b68,
+  0x5a82799a, 0xa57d8666, 0x59646498, 0xa462eeac, 0x5842dd54, 0xa34bdf20,
+  0x571deefa, 0xa2386284,
+  0x55f5a4d2, 0xa1288376, 0x54ca0a4b, 0xa01c4c73, 0x539b2af0, 0x9f13c7d0,
+  0x5269126e, 0x9e0effc1,
+  0x5133cc94, 0x9d0dfe54, 0x4ffb654d, 0x9c10cd70, 0x4ebfe8a5, 0x9b1776da,
+  0x4d8162c4, 0x9a22042d,
+  0x4c3fdff4, 0x99307ee0, 0x4afb6c98, 0x9842f043, 0x49b41533, 0x9759617f,
+  0x4869e665, 0x9673db94,
+  0x471cece7, 0x9592675c, 0x45cd358f, 0x94b50d87, 0x447acd50, 0x93dbd6a0,
+  0x4325c135, 0x9306cb04,
+  0x41ce1e65, 0x9235f2ec, 0x4073f21d, 0x91695663, 0x3f1749b8, 0x90a0fd4e,
+  0x3db832a6, 0x8fdcef66,
+  0x3c56ba70, 0x8f1d343a, 0x3af2eeb7, 0x8e61d32e, 0x398cdd32, 0x8daad37b,
+  0x382493b0, 0x8cf83c30,
+  0x36ba2014, 0x8c4a142f, 0x354d9057, 0x8ba0622f, 0x33def287, 0x8afb2cbb,
+  0x326e54c7, 0x8a5a7a31,
+  0x30fbc54d, 0x89be50c3, 0x2f875262, 0x8926b677, 0x2e110a62, 0x8893b125,
+  0x2c98fbba, 0x88054677,
+  0x2b1f34eb, 0x877b7bec, 0x29a3c485, 0x86f656d3, 0x2826b928, 0x8675dc4f,
+  0x26a82186, 0x85fa1153,
+  0x25280c5e, 0x8582faa5, 0x23a6887f, 0x85109cdd, 0x2223a4c5, 0x84a2fc62,
+  0x209f701c, 0x843a1d70,
+  0x1f19f97b, 0x83d60412, 0x1d934fe5, 0x8376b422, 0x1c0b826a, 0x831c314e,
+  0x1a82a026, 0x82c67f14,
+  0x18f8b83c, 0x8275a0c0, 0x176dd9de, 0x82299971, 0x15e21445, 0x81e26c16,
+  0x145576b1, 0x81a01b6d,
+  0x12c8106f, 0x8162aa04, 0x1139f0cf, 0x812a1a3a, 0xfab272b, 0x80f66e3c,
+  0xe1bc2e4, 0x80c7a80a,
+  0xc8bd35e, 0x809dc971, 0xafb6805, 0x8078d40d, 0x96a9049, 0x8058c94c,
+  0x7d95b9e, 0x803daa6a,
+  0x647d97c, 0x80277872, 0x4b6195d, 0x80163440, 0x3242abf, 0x8009de7e,
+  0x1921d20, 0x800277a6,
+};
+
+static const q31_t WeightsQ31_512[1024] = {
+  0x7fffffff, 0x0, 0x7fffd886, 0xff9b781d, 0x7fff6216, 0xff36f078, 0x7ffe9cb2,
+  0xfed2694f,
+  0x7ffd885a, 0xfe6de2e0, 0x7ffc250f, 0xfe095d69, 0x7ffa72d1, 0xfda4d929,
+  0x7ff871a2, 0xfd40565c,
+  0x7ff62182, 0xfcdbd541, 0x7ff38274, 0xfc775616, 0x7ff09478, 0xfc12d91a,
+  0x7fed5791, 0xfbae5e89,
+  0x7fe9cbc0, 0xfb49e6a3, 0x7fe5f108, 0xfae571a4, 0x7fe1c76b, 0xfa80ffcb,
+  0x7fdd4eec, 0xfa1c9157,
+  0x7fd8878e, 0xf9b82684, 0x7fd37153, 0xf953bf91, 0x7fce0c3e, 0xf8ef5cbb,
+  0x7fc85854, 0xf88afe42,
+  0x7fc25596, 0xf826a462, 0x7fbc040a, 0xf7c24f59, 0x7fb563b3, 0xf75dff66,
+  0x7fae7495, 0xf6f9b4c6,
+  0x7fa736b4, 0xf6956fb7, 0x7f9faa15, 0xf6313077, 0x7f97cebd, 0xf5ccf743,
+  0x7f8fa4b0, 0xf568c45b,
+  0x7f872bf3, 0xf50497fb, 0x7f7e648c, 0xf4a07261, 0x7f754e80, 0xf43c53cb,
+  0x7f6be9d4, 0xf3d83c77,
+  0x7f62368f, 0xf3742ca2, 0x7f5834b7, 0xf310248a, 0x7f4de451, 0xf2ac246e,
+  0x7f434563, 0xf2482c8a,
+  0x7f3857f6, 0xf1e43d1c, 0x7f2d1c0e, 0xf1805662, 0x7f2191b4, 0xf11c789a,
+  0x7f15b8ee, 0xf0b8a401,
+  0x7f0991c4, 0xf054d8d5, 0x7efd1c3c, 0xeff11753, 0x7ef05860, 0xef8d5fb8,
+  0x7ee34636, 0xef29b243,
+  0x7ed5e5c6, 0xeec60f31, 0x7ec8371a, 0xee6276bf, 0x7eba3a39, 0xedfee92b,
+  0x7eabef2c, 0xed9b66b2,
+  0x7e9d55fc, 0xed37ef91, 0x7e8e6eb2, 0xecd48407, 0x7e7f3957, 0xec71244f,
+  0x7e6fb5f4, 0xec0dd0a8,
+  0x7e5fe493, 0xebaa894f, 0x7e4fc53e, 0xeb474e81, 0x7e3f57ff, 0xeae4207a,
+  0x7e2e9cdf, 0xea80ff7a,
+  0x7e1d93ea, 0xea1debbb, 0x7e0c3d29, 0xe9bae57d, 0x7dfa98a8, 0xe957ecfb,
+  0x7de8a670, 0xe8f50273,
+  0x7dd6668f, 0xe8922622, 0x7dc3d90d, 0xe82f5844, 0x7db0fdf8, 0xe7cc9917,
+  0x7d9dd55a, 0xe769e8d8,
+  0x7d8a5f40, 0xe70747c4, 0x7d769bb5, 0xe6a4b616, 0x7d628ac6, 0xe642340d,
+  0x7d4e2c7f, 0xe5dfc1e5,
+  0x7d3980ec, 0xe57d5fda, 0x7d24881b, 0xe51b0e2a, 0x7d0f4218, 0xe4b8cd11,
+  0x7cf9aef0, 0xe4569ccb,
+  0x7ce3ceb2, 0xe3f47d96, 0x7ccda169, 0xe3926fad, 0x7cb72724, 0xe330734d,
+  0x7ca05ff1, 0xe2ce88b3,
+  0x7c894bde, 0xe26cb01b, 0x7c71eaf9, 0xe20ae9c1, 0x7c5a3d50, 0xe1a935e2,
+  0x7c4242f2, 0xe14794ba,
+  0x7c29fbee, 0xe0e60685, 0x7c116853, 0xe0848b7f, 0x7bf88830, 0xe02323e5,
+  0x7bdf5b94, 0xdfc1cff3,
+  0x7bc5e290, 0xdf608fe4, 0x7bac1d31, 0xdeff63f4, 0x7b920b89, 0xde9e4c60,
+  0x7b77ada8, 0xde3d4964,
+  0x7b5d039e, 0xdddc5b3b, 0x7b420d7a, 0xdd7b8220, 0x7b26cb4f, 0xdd1abe51,
+  0x7b0b3d2c, 0xdcba1008,
+  0x7aef6323, 0xdc597781, 0x7ad33d45, 0xdbf8f4f8, 0x7ab6cba4, 0xdb9888a8,
+  0x7a9a0e50, 0xdb3832cd,
+  0x7a7d055b, 0xdad7f3a2, 0x7a5fb0d8, 0xda77cb63, 0x7a4210d8, 0xda17ba4a,
+  0x7a24256f, 0xd9b7c094,
+  0x7a05eead, 0xd957de7a, 0x79e76ca7, 0xd8f81439, 0x79c89f6e, 0xd898620c,
+  0x79a98715, 0xd838c82d,
+  0x798a23b1, 0xd7d946d8, 0x796a7554, 0xd779de47, 0x794a7c12, 0xd71a8eb5,
+  0x792a37fe, 0xd6bb585e,
+  0x7909a92d, 0xd65c3b7b, 0x78e8cfb2, 0xd5fd3848, 0x78c7aba2, 0xd59e4eff,
+  0x78a63d11, 0xd53f7fda,
+  0x78848414, 0xd4e0cb15, 0x786280bf, 0xd48230e9, 0x78403329, 0xd423b191,
+  0x781d9b65, 0xd3c54d47,
+  0x77fab989, 0xd3670446, 0x77d78daa, 0xd308d6c7, 0x77b417df, 0xd2aac504,
+  0x7790583e, 0xd24ccf39,
+  0x776c4edb, 0xd1eef59e, 0x7747fbce, 0xd191386e, 0x77235f2d, 0xd13397e2,
+  0x76fe790e, 0xd0d61434,
+  0x76d94989, 0xd078ad9e, 0x76b3d0b4, 0xd01b6459, 0x768e0ea6, 0xcfbe389f,
+  0x76680376, 0xcf612aaa,
+  0x7641af3d, 0xcf043ab3, 0x761b1211, 0xcea768f2, 0x75f42c0b, 0xce4ab5a2,
+  0x75ccfd42, 0xcdee20fc,
+  0x75a585cf, 0xcd91ab39, 0x757dc5ca, 0xcd355491, 0x7555bd4c, 0xccd91d3d,
+  0x752d6c6c, 0xcc7d0578,
+  0x7504d345, 0xcc210d79, 0x74dbf1ef, 0xcbc53579, 0x74b2c884, 0xcb697db0,
+  0x7489571c, 0xcb0de658,
+  0x745f9dd1, 0xcab26fa9, 0x74359cbd, 0xca5719db, 0x740b53fb, 0xc9fbe527,
+  0x73e0c3a3, 0xc9a0d1c5,
+  0x73b5ebd1, 0xc945dfec, 0x738acc9e, 0xc8eb0fd6, 0x735f6626, 0xc89061ba,
+  0x7333b883, 0xc835d5d0,
+  0x7307c3d0, 0xc7db6c50, 0x72db8828, 0xc7812572, 0x72af05a7, 0xc727016d,
+  0x72823c67, 0xc6cd0079,
+  0x72552c85, 0xc67322ce, 0x7227d61c, 0xc61968a2, 0x71fa3949, 0xc5bfd22e,
+  0x71cc5626, 0xc5665fa9,
+  0x719e2cd2, 0xc50d1149, 0x716fbd68, 0xc4b3e746, 0x71410805, 0xc45ae1d7,
+  0x71120cc5, 0xc4020133,
+  0x70e2cbc6, 0xc3a94590, 0x70b34525, 0xc350af26, 0x708378ff, 0xc2f83e2a,
+  0x70536771, 0xc29ff2d4,
+  0x7023109a, 0xc247cd5a, 0x6ff27497, 0xc1efcdf3, 0x6fc19385, 0xc197f4d4,
+  0x6f906d84, 0xc1404233,
+  0x6f5f02b2, 0xc0e8b648, 0x6f2d532c, 0xc0915148, 0x6efb5f12, 0xc03a1368,
+  0x6ec92683, 0xbfe2fcdf,
+  0x6e96a99d, 0xbf8c0de3, 0x6e63e87f, 0xbf3546a8, 0x6e30e34a, 0xbedea765,
+  0x6dfd9a1c, 0xbe88304f,
+  0x6dca0d14, 0xbe31e19b, 0x6d963c54, 0xbddbbb7f, 0x6d6227fa, 0xbd85be30,
+  0x6d2dd027, 0xbd2fe9e2,
+  0x6cf934fc, 0xbcda3ecb, 0x6cc45698, 0xbc84bd1f, 0x6c8f351c, 0xbc2f6513,
+  0x6c59d0a9, 0xbbda36dd,
+  0x6c242960, 0xbb8532b0, 0x6bee3f62, 0xbb3058c0, 0x6bb812d1, 0xbadba943,
+  0x6b81a3cd, 0xba87246d,
+  0x6b4af279, 0xba32ca71, 0x6b13fef5, 0xb9de9b83, 0x6adcc964, 0xb98a97d8,
+  0x6aa551e9, 0xb936bfa4,
+  0x6a6d98a4, 0xb8e31319, 0x6a359db9, 0xb88f926d, 0x69fd614a, 0xb83c3dd1,
+  0x69c4e37a, 0xb7e9157a,
+  0x698c246c, 0xb796199b, 0x69532442, 0xb7434a67, 0x6919e320, 0xb6f0a812,
+  0x68e06129, 0xb69e32cd,
+  0x68a69e81, 0xb64beacd, 0x686c9b4b, 0xb5f9d043, 0x683257ab, 0xb5a7e362,
+  0x67f7d3c5, 0xb556245e,
+  0x67bd0fbd, 0xb5049368, 0x67820bb7, 0xb4b330b3, 0x6746c7d8, 0xb461fc70,
+  0x670b4444, 0xb410f6d3,
+  0x66cf8120, 0xb3c0200c, 0x66937e91, 0xb36f784f, 0x66573cbb, 0xb31effcc,
+  0x661abbc5, 0xb2ceb6b5,
+  0x65ddfbd3, 0xb27e9d3c, 0x65a0fd0b, 0xb22eb392, 0x6563bf92, 0xb1def9e9,
+  0x6526438f, 0xb18f7071,
+  0x64e88926, 0xb140175b, 0x64aa907f, 0xb0f0eeda, 0x646c59bf, 0xb0a1f71d,
+  0x642de50d, 0xb0533055,
+  0x63ef3290, 0xb0049ab3, 0x63b0426d, 0xafb63667, 0x637114cc, 0xaf6803a2,
+  0x6331a9d4, 0xaf1a0293,
+  0x62f201ac, 0xaecc336c, 0x62b21c7b, 0xae7e965b, 0x6271fa69, 0xae312b92,
+  0x62319b9d, 0xade3f33e,
+  0x61f1003f, 0xad96ed92, 0x61b02876, 0xad4a1aba, 0x616f146c, 0xacfd7ae8,
+  0x612dc447, 0xacb10e4b,
+  0x60ec3830, 0xac64d510, 0x60aa7050, 0xac18cf69, 0x60686ccf, 0xabccfd83,
+  0x60262dd6, 0xab815f8d,
+  0x5fe3b38d, 0xab35f5b5, 0x5fa0fe1f, 0xaaeac02c, 0x5f5e0db3, 0xaa9fbf1e,
+  0x5f1ae274, 0xaa54f2ba,
+  0x5ed77c8a, 0xaa0a5b2e, 0x5e93dc1f, 0xa9bff8a8, 0x5e50015d, 0xa975cb57,
+  0x5e0bec6e, 0xa92bd367,
+  0x5dc79d7c, 0xa8e21106, 0x5d8314b1, 0xa8988463, 0x5d3e5237, 0xa84f2daa,
+  0x5cf95638, 0xa8060d08,
+  0x5cb420e0, 0xa7bd22ac, 0x5c6eb258, 0xa7746ec0, 0x5c290acc, 0xa72bf174,
+  0x5be32a67, 0xa6e3aaf2,
+  0x5b9d1154, 0xa69b9b68, 0x5b56bfbd, 0xa653c303, 0x5b1035cf, 0xa60c21ee,
+  0x5ac973b5, 0xa5c4b855,
+  0x5a82799a, 0xa57d8666, 0x5a3b47ab, 0xa5368c4b, 0x59f3de12, 0xa4efca31,
+  0x59ac3cfd, 0xa4a94043,
+  0x59646498, 0xa462eeac, 0x591c550e, 0xa41cd599, 0x58d40e8c, 0xa3d6f534,
+  0x588b9140, 0xa3914da8,
+  0x5842dd54, 0xa34bdf20, 0x57f9f2f8, 0xa306a9c8, 0x57b0d256, 0xa2c1adc9,
+  0x57677b9d, 0xa27ceb4f,
+  0x571deefa, 0xa2386284, 0x56d42c99, 0xa1f41392, 0x568a34a9, 0xa1affea3,
+  0x56400758, 0xa16c23e1,
+  0x55f5a4d2, 0xa1288376, 0x55ab0d46, 0xa0e51d8c, 0x556040e2, 0xa0a1f24d,
+  0x55153fd4, 0xa05f01e1,
+  0x54ca0a4b, 0xa01c4c73, 0x547ea073, 0x9fd9d22a, 0x5433027d, 0x9f979331,
+  0x53e73097, 0x9f558fb0,
+  0x539b2af0, 0x9f13c7d0, 0x534ef1b5, 0x9ed23bb9, 0x53028518, 0x9e90eb94,
+  0x52b5e546, 0x9e4fd78a,
+  0x5269126e, 0x9e0effc1, 0x521c0cc2, 0x9dce6463, 0x51ced46e, 0x9d8e0597,
+  0x518169a5, 0x9d4de385,
+  0x5133cc94, 0x9d0dfe54, 0x50e5fd6d, 0x9cce562c, 0x5097fc5e, 0x9c8eeb34,
+  0x5049c999, 0x9c4fbd93,
+  0x4ffb654d, 0x9c10cd70, 0x4faccfab, 0x9bd21af3, 0x4f5e08e3, 0x9b93a641,
+  0x4f0f1126, 0x9b556f81,
+  0x4ebfe8a5, 0x9b1776da, 0x4e708f8f, 0x9ad9bc71, 0x4e210617, 0x9a9c406e,
+  0x4dd14c6e, 0x9a5f02f5,
+  0x4d8162c4, 0x9a22042d, 0x4d31494b, 0x99e5443b, 0x4ce10034, 0x99a8c345,
+  0x4c9087b1, 0x996c816f,
+  0x4c3fdff4, 0x99307ee0, 0x4bef092d, 0x98f4bbbc, 0x4b9e0390, 0x98b93828,
+  0x4b4ccf4d, 0x987df449,
+  0x4afb6c98, 0x9842f043, 0x4aa9dba2, 0x98082c3b, 0x4a581c9e, 0x97cda855,
+  0x4a062fbd, 0x979364b5,
+  0x49b41533, 0x9759617f, 0x4961cd33, 0x971f9ed7, 0x490f57ee, 0x96e61ce0,
+  0x48bcb599, 0x96acdbbe,
+  0x4869e665, 0x9673db94, 0x4816ea86, 0x963b1c86, 0x47c3c22f, 0x96029eb6,
+  0x47706d93, 0x95ca6247,
+  0x471cece7, 0x9592675c, 0x46c9405c, 0x955aae17, 0x46756828, 0x9523369c,
+  0x4621647d, 0x94ec010b,
+  0x45cd358f, 0x94b50d87, 0x4578db93, 0x947e5c33, 0x452456bd, 0x9447ed2f,
+  0x44cfa740, 0x9411c09e,
+  0x447acd50, 0x93dbd6a0, 0x4425c923, 0x93a62f57, 0x43d09aed, 0x9370cae4,
+  0x437b42e1, 0x933ba968,
+  0x4325c135, 0x9306cb04, 0x42d0161e, 0x92d22fd9, 0x427a41d0, 0x929dd806,
+  0x42244481, 0x9269c3ac,
+  0x41ce1e65, 0x9235f2ec, 0x4177cfb1, 0x920265e4, 0x4121589b, 0x91cf1cb6,
+  0x40cab958, 0x919c1781,
+  0x4073f21d, 0x91695663, 0x401d0321, 0x9136d97d, 0x3fc5ec98, 0x9104a0ee,
+  0x3f6eaeb8, 0x90d2acd4,
+  0x3f1749b8, 0x90a0fd4e, 0x3ebfbdcd, 0x906f927c, 0x3e680b2c, 0x903e6c7b,
+  0x3e10320d, 0x900d8b69,
+  0x3db832a6, 0x8fdcef66, 0x3d600d2c, 0x8fac988f, 0x3d07c1d6, 0x8f7c8701,
+  0x3caf50da, 0x8f4cbadb,
+  0x3c56ba70, 0x8f1d343a, 0x3bfdfecd, 0x8eedf33b, 0x3ba51e29, 0x8ebef7fb,
+  0x3b4c18ba, 0x8e904298,
+  0x3af2eeb7, 0x8e61d32e, 0x3a99a057, 0x8e33a9da, 0x3a402dd2, 0x8e05c6b7,
+  0x39e6975e, 0x8dd829e4,
+  0x398cdd32, 0x8daad37b, 0x3932ff87, 0x8d7dc399, 0x38d8fe93, 0x8d50fa59,
+  0x387eda8e, 0x8d2477d8,
+  0x382493b0, 0x8cf83c30, 0x37ca2a30, 0x8ccc477d, 0x376f9e46, 0x8ca099da,
+  0x3714f02a, 0x8c753362,
+  0x36ba2014, 0x8c4a142f, 0x365f2e3b, 0x8c1f3c5d, 0x36041ad9, 0x8bf4ac05,
+  0x35a8e625, 0x8bca6343,
+  0x354d9057, 0x8ba0622f, 0x34f219a8, 0x8b76a8e4, 0x34968250, 0x8b4d377c,
+  0x343aca87, 0x8b240e11,
+  0x33def287, 0x8afb2cbb, 0x3382fa88, 0x8ad29394, 0x3326e2c3, 0x8aaa42b4,
+  0x32caab6f, 0x8a823a36,
+  0x326e54c7, 0x8a5a7a31, 0x3211df04, 0x8a3302be, 0x31b54a5e, 0x8a0bd3f5,
+  0x3158970e, 0x89e4edef,
+  0x30fbc54d, 0x89be50c3, 0x309ed556, 0x8997fc8a, 0x3041c761, 0x8971f15a,
+  0x2fe49ba7, 0x894c2f4c,
+  0x2f875262, 0x8926b677, 0x2f29ebcc, 0x890186f2, 0x2ecc681e, 0x88dca0d3,
+  0x2e6ec792, 0x88b80432,
+  0x2e110a62, 0x8893b125, 0x2db330c7, 0x886fa7c2, 0x2d553afc, 0x884be821,
+  0x2cf72939, 0x88287256,
+  0x2c98fbba, 0x88054677, 0x2c3ab2b9, 0x87e2649b, 0x2bdc4e6f, 0x87bfccd7,
+  0x2b7dcf17, 0x879d7f41,
+  0x2b1f34eb, 0x877b7bec, 0x2ac08026, 0x8759c2ef, 0x2a61b101, 0x8738545e,
+  0x2a02c7b8, 0x8717304e,
+  0x29a3c485, 0x86f656d3, 0x2944a7a2, 0x86d5c802, 0x28e5714b, 0x86b583ee,
+  0x288621b9, 0x86958aac,
+  0x2826b928, 0x8675dc4f, 0x27c737d3, 0x865678eb, 0x27679df4, 0x86376092,
+  0x2707ebc7, 0x86189359,
+  0x26a82186, 0x85fa1153, 0x26483f6c, 0x85dbda91, 0x25e845b6, 0x85bdef28,
+  0x2588349d, 0x85a04f28,
+  0x25280c5e, 0x8582faa5, 0x24c7cd33, 0x8565f1b0, 0x24677758, 0x8549345c,
+  0x24070b08, 0x852cc2bb,
+  0x23a6887f, 0x85109cdd, 0x2345eff8, 0x84f4c2d4, 0x22e541af, 0x84d934b1,
+  0x22847de0, 0x84bdf286,
+  0x2223a4c5, 0x84a2fc62, 0x21c2b69c, 0x84885258, 0x2161b3a0, 0x846df477,
+  0x21009c0c, 0x8453e2cf,
+  0x209f701c, 0x843a1d70, 0x203e300d, 0x8420a46c, 0x1fdcdc1b, 0x840777d0,
+  0x1f7b7481, 0x83ee97ad,
+  0x1f19f97b, 0x83d60412, 0x1eb86b46, 0x83bdbd0e, 0x1e56ca1e, 0x83a5c2b0,
+  0x1df5163f, 0x838e1507,
+  0x1d934fe5, 0x8376b422, 0x1d31774d, 0x835fa00f, 0x1ccf8cb3, 0x8348d8dc,
+  0x1c6d9053, 0x83325e97,
+  0x1c0b826a, 0x831c314e, 0x1ba96335, 0x83065110, 0x1b4732ef, 0x82f0bde8,
+  0x1ae4f1d6, 0x82db77e5,
+  0x1a82a026, 0x82c67f14, 0x1a203e1b, 0x82b1d381, 0x19bdcbf3, 0x829d753a,
+  0x195b49ea, 0x8289644b,
+  0x18f8b83c, 0x8275a0c0, 0x18961728, 0x82622aa6, 0x183366e9, 0x824f0208,
+  0x17d0a7bc, 0x823c26f3,
+  0x176dd9de, 0x82299971, 0x170afd8d, 0x82175990, 0x16a81305, 0x82056758,
+  0x16451a83, 0x81f3c2d7,
+  0x15e21445, 0x81e26c16, 0x157f0086, 0x81d16321, 0x151bdf86, 0x81c0a801,
+  0x14b8b17f, 0x81b03ac2,
+  0x145576b1, 0x81a01b6d, 0x13f22f58, 0x81904a0c, 0x138edbb1, 0x8180c6a9,
+  0x132b7bf9, 0x8171914e,
+  0x12c8106f, 0x8162aa04, 0x1264994e, 0x815410d4, 0x120116d5, 0x8145c5c7,
+  0x119d8941, 0x8137c8e6,
+  0x1139f0cf, 0x812a1a3a, 0x10d64dbd, 0x811cb9ca, 0x1072a048, 0x810fa7a0,
+  0x100ee8ad, 0x8102e3c4,
+  0xfab272b, 0x80f66e3c, 0xf475bff, 0x80ea4712, 0xee38766, 0x80de6e4c,
+  0xe7fa99e, 0x80d2e3f2,
+  0xe1bc2e4, 0x80c7a80a, 0xdb7d376, 0x80bcba9d, 0xd53db92, 0x80b21baf,
+  0xcefdb76, 0x80a7cb49,
+  0xc8bd35e, 0x809dc971, 0xc27c389, 0x8094162c, 0xbc3ac35, 0x808ab180,
+  0xb5f8d9f, 0x80819b74,
+  0xafb6805, 0x8078d40d, 0xa973ba5, 0x80705b50, 0xa3308bd, 0x80683143,
+  0x9cecf89, 0x806055eb,
+  0x96a9049, 0x8058c94c, 0x9064b3a, 0x80518b6b, 0x8a2009a, 0x804a9c4d,
+  0x83db0a7, 0x8043fbf6,
+  0x7d95b9e, 0x803daa6a, 0x77501be, 0x8037a7ac, 0x710a345, 0x8031f3c2,
+  0x6ac406f, 0x802c8ead,
+  0x647d97c, 0x80277872, 0x5e36ea9, 0x8022b114, 0x57f0035, 0x801e3895,
+  0x51a8e5c, 0x801a0ef8,
+  0x4b6195d, 0x80163440, 0x451a177, 0x8012a86f, 0x3ed26e6, 0x800f6b88,
+  0x388a9ea, 0x800c7d8c,
+  0x3242abf, 0x8009de7e, 0x2bfa9a4, 0x80078e5e, 0x25b26d7, 0x80058d2f,
+  0x1f6a297, 0x8003daf1,
+  0x1921d20, 0x800277a6, 0x12d96b1, 0x8001634e, 0xc90f88, 0x80009dea,
+  0x6487e3, 0x8000277a,
+};
+
+static const q31_t WeightsQ31_2048[4096] = {
+  0x7fffffff, 0x0, 0x7ffffd88, 0xffe6de05, 0x7ffff621, 0xffcdbc0b, 0x7fffe9cb,
+  0xffb49a12,
+  0x7fffd886, 0xff9b781d, 0x7fffc251, 0xff82562c, 0x7fffa72c, 0xff69343f,
+  0x7fff8719, 0xff501258,
+  0x7fff6216, 0xff36f078, 0x7fff3824, 0xff1dcea0, 0x7fff0943, 0xff04acd0,
+  0x7ffed572, 0xfeeb8b0a,
+  0x7ffe9cb2, 0xfed2694f, 0x7ffe5f03, 0xfeb947a0, 0x7ffe1c65, 0xfea025fd,
+  0x7ffdd4d7, 0xfe870467,
+  0x7ffd885a, 0xfe6de2e0, 0x7ffd36ee, 0xfe54c169, 0x7ffce093, 0xfe3ba002,
+  0x7ffc8549, 0xfe227eac,
+  0x7ffc250f, 0xfe095d69, 0x7ffbbfe6, 0xfdf03c3a, 0x7ffb55ce, 0xfdd71b1e,
+  0x7ffae6c7, 0xfdbdfa18,
+  0x7ffa72d1, 0xfda4d929, 0x7ff9f9ec, 0xfd8bb850, 0x7ff97c18, 0xfd729790,
+  0x7ff8f954, 0xfd5976e9,
+  0x7ff871a2, 0xfd40565c, 0x7ff7e500, 0xfd2735ea, 0x7ff75370, 0xfd0e1594,
+  0x7ff6bcf0, 0xfcf4f55c,
+  0x7ff62182, 0xfcdbd541, 0x7ff58125, 0xfcc2b545, 0x7ff4dbd9, 0xfca9956a,
+  0x7ff4319d, 0xfc9075af,
+  0x7ff38274, 0xfc775616, 0x7ff2ce5b, 0xfc5e36a0, 0x7ff21553, 0xfc45174e,
+  0x7ff1575d, 0xfc2bf821,
+  0x7ff09478, 0xfc12d91a, 0x7fefcca4, 0xfbf9ba39, 0x7feeffe1, 0xfbe09b80,
+  0x7fee2e30, 0xfbc77cf0,
+  0x7fed5791, 0xfbae5e89, 0x7fec7c02, 0xfb95404d, 0x7feb9b85, 0xfb7c223d,
+  0x7feab61a, 0xfb630459,
+  0x7fe9cbc0, 0xfb49e6a3, 0x7fe8dc78, 0xfb30c91b, 0x7fe7e841, 0xfb17abc2,
+  0x7fe6ef1c, 0xfafe8e9b,
+  0x7fe5f108, 0xfae571a4, 0x7fe4ee06, 0xfacc54e0, 0x7fe3e616, 0xfab3384f,
+  0x7fe2d938, 0xfa9a1bf3,
+  0x7fe1c76b, 0xfa80ffcb, 0x7fe0b0b1, 0xfa67e3da, 0x7fdf9508, 0xfa4ec821,
+  0x7fde7471, 0xfa35ac9f,
+  0x7fdd4eec, 0xfa1c9157, 0x7fdc247a, 0xfa037648, 0x7fdaf519, 0xf9ea5b75,
+  0x7fd9c0ca, 0xf9d140de,
+  0x7fd8878e, 0xf9b82684, 0x7fd74964, 0xf99f0c68, 0x7fd6064c, 0xf985f28a,
+  0x7fd4be46, 0xf96cd8ed,
+  0x7fd37153, 0xf953bf91, 0x7fd21f72, 0xf93aa676, 0x7fd0c8a3, 0xf9218d9e,
+  0x7fcf6ce8, 0xf908750a,
+  0x7fce0c3e, 0xf8ef5cbb, 0x7fcca6a7, 0xf8d644b2, 0x7fcb3c23, 0xf8bd2cef,
+  0x7fc9ccb2, 0xf8a41574,
+  0x7fc85854, 0xf88afe42, 0x7fc6df08, 0xf871e759, 0x7fc560cf, 0xf858d0bb,
+  0x7fc3dda9, 0xf83fba68,
+  0x7fc25596, 0xf826a462, 0x7fc0c896, 0xf80d8ea9, 0x7fbf36aa, 0xf7f4793e,
+  0x7fbd9fd0, 0xf7db6423,
+  0x7fbc040a, 0xf7c24f59, 0x7fba6357, 0xf7a93ae0, 0x7fb8bdb8, 0xf79026b9,
+  0x7fb7132b, 0xf77712e5,
+  0x7fb563b3, 0xf75dff66, 0x7fb3af4e, 0xf744ec3b, 0x7fb1f5fc, 0xf72bd967,
+  0x7fb037bf, 0xf712c6ea,
+  0x7fae7495, 0xf6f9b4c6, 0x7facac7f, 0xf6e0a2fa, 0x7faadf7c, 0xf6c79188,
+  0x7fa90d8e, 0xf6ae8071,
+  0x7fa736b4, 0xf6956fb7, 0x7fa55aee, 0xf67c5f59, 0x7fa37a3c, 0xf6634f59,
+  0x7fa1949e, 0xf64a3fb8,
+  0x7f9faa15, 0xf6313077, 0x7f9dbaa0, 0xf6182196, 0x7f9bc640, 0xf5ff1318,
+  0x7f99ccf4, 0xf5e604fc,
+  0x7f97cebd, 0xf5ccf743, 0x7f95cb9a, 0xf5b3e9f0, 0x7f93c38c, 0xf59add02,
+  0x7f91b694, 0xf581d07b,
+  0x7f8fa4b0, 0xf568c45b, 0x7f8d8de1, 0xf54fb8a4, 0x7f8b7227, 0xf536ad56,
+  0x7f895182, 0xf51da273,
+  0x7f872bf3, 0xf50497fb, 0x7f850179, 0xf4eb8def, 0x7f82d214, 0xf4d28451,
+  0x7f809dc5, 0xf4b97b21,
+  0x7f7e648c, 0xf4a07261, 0x7f7c2668, 0xf4876a10, 0x7f79e35a, 0xf46e6231,
+  0x7f779b62, 0xf4555ac5,
+  0x7f754e80, 0xf43c53cb, 0x7f72fcb4, 0xf4234d45, 0x7f70a5fe, 0xf40a4735,
+  0x7f6e4a5e, 0xf3f1419a,
+  0x7f6be9d4, 0xf3d83c77, 0x7f698461, 0xf3bf37cb, 0x7f671a05, 0xf3a63398,
+  0x7f64aabf, 0xf38d2fe0,
+  0x7f62368f, 0xf3742ca2, 0x7f5fbd77, 0xf35b29e0, 0x7f5d3f75, 0xf342279b,
+  0x7f5abc8a, 0xf32925d3,
+  0x7f5834b7, 0xf310248a, 0x7f55a7fa, 0xf2f723c1, 0x7f531655, 0xf2de2379,
+  0x7f507fc7, 0xf2c523b2,
+  0x7f4de451, 0xf2ac246e, 0x7f4b43f2, 0xf29325ad, 0x7f489eaa, 0xf27a2771,
+  0x7f45f47b, 0xf26129ba,
+  0x7f434563, 0xf2482c8a, 0x7f409164, 0xf22f2fe1, 0x7f3dd87c, 0xf21633c0,
+  0x7f3b1aad, 0xf1fd3829,
+  0x7f3857f6, 0xf1e43d1c, 0x7f359057, 0xf1cb429a, 0x7f32c3d1, 0xf1b248a5,
+  0x7f2ff263, 0xf1994f3d,
+  0x7f2d1c0e, 0xf1805662, 0x7f2a40d2, 0xf1675e17, 0x7f2760af, 0xf14e665c,
+  0x7f247ba5, 0xf1356f32,
+  0x7f2191b4, 0xf11c789a, 0x7f1ea2dc, 0xf1038295, 0x7f1baf1e, 0xf0ea8d24,
+  0x7f18b679, 0xf0d19848,
+  0x7f15b8ee, 0xf0b8a401, 0x7f12b67c, 0xf09fb051, 0x7f0faf25, 0xf086bd39,
+  0x7f0ca2e7, 0xf06dcaba,
+  0x7f0991c4, 0xf054d8d5, 0x7f067bba, 0xf03be78a, 0x7f0360cb, 0xf022f6da,
+  0x7f0040f6, 0xf00a06c8,
+  0x7efd1c3c, 0xeff11753, 0x7ef9f29d, 0xefd8287c, 0x7ef6c418, 0xefbf3a45,
+  0x7ef390ae, 0xefa64cae,
+  0x7ef05860, 0xef8d5fb8, 0x7eed1b2c, 0xef747365, 0x7ee9d914, 0xef5b87b5,
+  0x7ee69217, 0xef429caa,
+  0x7ee34636, 0xef29b243, 0x7edff570, 0xef10c883, 0x7edc9fc6, 0xeef7df6a,
+  0x7ed94538, 0xeedef6f9,
+  0x7ed5e5c6, 0xeec60f31, 0x7ed28171, 0xeead2813, 0x7ecf1837, 0xee9441a0,
+  0x7ecbaa1a, 0xee7b5bd9,
+  0x7ec8371a, 0xee6276bf, 0x7ec4bf36, 0xee499253, 0x7ec14270, 0xee30ae96,
+  0x7ebdc0c6, 0xee17cb88,
+  0x7eba3a39, 0xedfee92b, 0x7eb6aeca, 0xede60780, 0x7eb31e78, 0xedcd2687,
+  0x7eaf8943, 0xedb44642,
+  0x7eabef2c, 0xed9b66b2, 0x7ea85033, 0xed8287d7, 0x7ea4ac58, 0xed69a9b3,
+  0x7ea1039b, 0xed50cc46,
+  0x7e9d55fc, 0xed37ef91, 0x7e99a37c, 0xed1f1396, 0x7e95ec1a, 0xed063856,
+  0x7e922fd6, 0xeced5dd0,
+  0x7e8e6eb2, 0xecd48407, 0x7e8aa8ac, 0xecbbaafb, 0x7e86ddc6, 0xeca2d2ad,
+  0x7e830dff, 0xec89fb1e,
+  0x7e7f3957, 0xec71244f, 0x7e7b5fce, 0xec584e41, 0x7e778166, 0xec3f78f6,
+  0x7e739e1d, 0xec26a46d,
+  0x7e6fb5f4, 0xec0dd0a8, 0x7e6bc8eb, 0xebf4fda8, 0x7e67d703, 0xebdc2b6e,
+  0x7e63e03b, 0xebc359fb,
+  0x7e5fe493, 0xebaa894f, 0x7e5be40c, 0xeb91b96c, 0x7e57dea7, 0xeb78ea52,
+  0x7e53d462, 0xeb601c04,
+  0x7e4fc53e, 0xeb474e81, 0x7e4bb13c, 0xeb2e81ca, 0x7e47985b, 0xeb15b5e1,
+  0x7e437a9c, 0xeafceac6,
+  0x7e3f57ff, 0xeae4207a, 0x7e3b3083, 0xeacb56ff, 0x7e37042a, 0xeab28e56,
+  0x7e32d2f4, 0xea99c67e,
+  0x7e2e9cdf, 0xea80ff7a, 0x7e2a61ed, 0xea683949, 0x7e26221f, 0xea4f73ee,
+  0x7e21dd73, 0xea36af69,
+  0x7e1d93ea, 0xea1debbb, 0x7e194584, 0xea0528e5, 0x7e14f242, 0xe9ec66e8,
+  0x7e109a24, 0xe9d3a5c5,
+  0x7e0c3d29, 0xe9bae57d, 0x7e07db52, 0xe9a22610, 0x7e0374a0, 0xe9896781,
+  0x7dff0911, 0xe970a9ce,
+  0x7dfa98a8, 0xe957ecfb, 0x7df62362, 0xe93f3107, 0x7df1a942, 0xe92675f4,
+  0x7ded2a47, 0xe90dbbc2,
+  0x7de8a670, 0xe8f50273, 0x7de41dc0, 0xe8dc4a07, 0x7ddf9034, 0xe8c39280,
+  0x7ddafdce, 0xe8aadbde,
+  0x7dd6668f, 0xe8922622, 0x7dd1ca75, 0xe879714d, 0x7dcd2981, 0xe860bd61,
+  0x7dc883b4, 0xe8480a5d,
+  0x7dc3d90d, 0xe82f5844, 0x7dbf298d, 0xe816a716, 0x7dba7534, 0xe7fdf6d4,
+  0x7db5bc02, 0xe7e5477f,
+  0x7db0fdf8, 0xe7cc9917, 0x7dac3b15, 0xe7b3eb9f, 0x7da77359, 0xe79b3f16,
+  0x7da2a6c6, 0xe782937e,
+  0x7d9dd55a, 0xe769e8d8, 0x7d98ff17, 0xe7513f25, 0x7d9423fc, 0xe7389665,
+  0x7d8f4409, 0xe71fee99,
+  0x7d8a5f40, 0xe70747c4, 0x7d85759f, 0xe6eea1e4, 0x7d808728, 0xe6d5fcfc,
+  0x7d7b93da, 0xe6bd590d,
+  0x7d769bb5, 0xe6a4b616, 0x7d719eba, 0xe68c141a, 0x7d6c9ce9, 0xe6737319,
+  0x7d679642, 0xe65ad315,
+  0x7d628ac6, 0xe642340d, 0x7d5d7a74, 0xe6299604, 0x7d58654d, 0xe610f8f9,
+  0x7d534b50, 0xe5f85cef,
+  0x7d4e2c7f, 0xe5dfc1e5, 0x7d4908d9, 0xe5c727dd, 0x7d43e05e, 0xe5ae8ed8,
+  0x7d3eb30f, 0xe595f6d7,
+  0x7d3980ec, 0xe57d5fda, 0x7d3449f5, 0xe564c9e3, 0x7d2f0e2b, 0xe54c34f3,
+  0x7d29cd8c, 0xe533a10a,
+  0x7d24881b, 0xe51b0e2a, 0x7d1f3dd6, 0xe5027c53, 0x7d19eebf, 0xe4e9eb87,
+  0x7d149ad5, 0xe4d15bc6,
+  0x7d0f4218, 0xe4b8cd11, 0x7d09e489, 0xe4a03f69, 0x7d048228, 0xe487b2d0,
+  0x7cff1af5, 0xe46f2745,
+  0x7cf9aef0, 0xe4569ccb, 0x7cf43e1a, 0xe43e1362, 0x7ceec873, 0xe4258b0a,
+  0x7ce94dfb, 0xe40d03c6,
+  0x7ce3ceb2, 0xe3f47d96, 0x7cde4a98, 0xe3dbf87a, 0x7cd8c1ae, 0xe3c37474,
+  0x7cd333f3, 0xe3aaf184,
+  0x7ccda169, 0xe3926fad, 0x7cc80a0f, 0xe379eeed, 0x7cc26de5, 0xe3616f48,
+  0x7cbcccec, 0xe348f0bd,
+  0x7cb72724, 0xe330734d, 0x7cb17c8d, 0xe317f6fa, 0x7cabcd28, 0xe2ff7bc3,
+  0x7ca618f3, 0xe2e701ac,
+  0x7ca05ff1, 0xe2ce88b3, 0x7c9aa221, 0xe2b610da, 0x7c94df83, 0xe29d9a23,
+  0x7c8f1817, 0xe285248d,
+  0x7c894bde, 0xe26cb01b, 0x7c837ad8, 0xe2543ccc, 0x7c7da505, 0xe23bcaa2,
+  0x7c77ca65, 0xe223599e,
+  0x7c71eaf9, 0xe20ae9c1, 0x7c6c06c0, 0xe1f27b0b, 0x7c661dbc, 0xe1da0d7e,
+  0x7c602fec, 0xe1c1a11b,
+  0x7c5a3d50, 0xe1a935e2, 0x7c5445e9, 0xe190cbd4, 0x7c4e49b7, 0xe17862f3,
+  0x7c4848ba, 0xe15ffb3f,
+  0x7c4242f2, 0xe14794ba, 0x7c3c3860, 0xe12f2f63, 0x7c362904, 0xe116cb3d,
+  0x7c3014de, 0xe0fe6848,
+  0x7c29fbee, 0xe0e60685, 0x7c23de35, 0xe0cda5f5, 0x7c1dbbb3, 0xe0b54698,
+  0x7c179467, 0xe09ce871,
+  0x7c116853, 0xe0848b7f, 0x7c0b3777, 0xe06c2fc4, 0x7c0501d2, 0xe053d541,
+  0x7bfec765, 0xe03b7bf6,
+  0x7bf88830, 0xe02323e5, 0x7bf24434, 0xe00acd0e, 0x7bebfb70, 0xdff27773,
+  0x7be5ade6, 0xdfda2314,
+  0x7bdf5b94, 0xdfc1cff3, 0x7bd9047c, 0xdfa97e0f, 0x7bd2a89e, 0xdf912d6b,
+  0x7bcc47fa, 0xdf78de07,
+  0x7bc5e290, 0xdf608fe4, 0x7bbf7860, 0xdf484302, 0x7bb9096b, 0xdf2ff764,
+  0x7bb295b0, 0xdf17ad0a,
+  0x7bac1d31, 0xdeff63f4, 0x7ba59fee, 0xdee71c24, 0x7b9f1de6, 0xdeced59b,
+  0x7b989719, 0xdeb69059,
+  0x7b920b89, 0xde9e4c60, 0x7b8b7b36, 0xde8609b1, 0x7b84e61f, 0xde6dc84b,
+  0x7b7e4c45, 0xde558831,
+  0x7b77ada8, 0xde3d4964, 0x7b710a49, 0xde250be3, 0x7b6a6227, 0xde0ccfb1,
+  0x7b63b543, 0xddf494ce,
+  0x7b5d039e, 0xdddc5b3b, 0x7b564d36, 0xddc422f8, 0x7b4f920e, 0xddabec08,
+  0x7b48d225, 0xdd93b66a,
+  0x7b420d7a, 0xdd7b8220, 0x7b3b4410, 0xdd634f2b, 0x7b3475e5, 0xdd4b1d8c,
+  0x7b2da2fa, 0xdd32ed43,
+  0x7b26cb4f, 0xdd1abe51, 0x7b1feee5, 0xdd0290b8, 0x7b190dbc, 0xdcea6478,
+  0x7b1227d3, 0xdcd23993,
+  0x7b0b3d2c, 0xdcba1008, 0x7b044dc7, 0xdca1e7da, 0x7afd59a4, 0xdc89c109,
+  0x7af660c2, 0xdc719b96,
+  0x7aef6323, 0xdc597781, 0x7ae860c7, 0xdc4154cd, 0x7ae159ae, 0xdc293379,
+  0x7ada4dd8, 0xdc111388,
+  0x7ad33d45, 0xdbf8f4f8, 0x7acc27f7, 0xdbe0d7cd, 0x7ac50dec, 0xdbc8bc06,
+  0x7abdef25, 0xdbb0a1a4,
+  0x7ab6cba4, 0xdb9888a8, 0x7aafa367, 0xdb807114, 0x7aa8766f, 0xdb685ae9,
+  0x7aa144bc, 0xdb504626,
+  0x7a9a0e50, 0xdb3832cd, 0x7a92d329, 0xdb2020e0, 0x7a8b9348, 0xdb08105e,
+  0x7a844eae, 0xdaf00149,
+  0x7a7d055b, 0xdad7f3a2, 0x7a75b74f, 0xdabfe76a, 0x7a6e648a, 0xdaa7dca1,
+  0x7a670d0d, 0xda8fd349,
+  0x7a5fb0d8, 0xda77cb63, 0x7a584feb, 0xda5fc4ef, 0x7a50ea47, 0xda47bfee,
+  0x7a497feb, 0xda2fbc61,
+  0x7a4210d8, 0xda17ba4a, 0x7a3a9d0f, 0xd9ffb9a9, 0x7a332490, 0xd9e7ba7f,
+  0x7a2ba75a, 0xd9cfbccd,
+  0x7a24256f, 0xd9b7c094, 0x7a1c9ece, 0xd99fc5d4, 0x7a151378, 0xd987cc90,
+  0x7a0d836d, 0xd96fd4c7,
+  0x7a05eead, 0xd957de7a, 0x79fe5539, 0xd93fe9ab, 0x79f6b711, 0xd927f65b,
+  0x79ef1436, 0xd910048a,
+  0x79e76ca7, 0xd8f81439, 0x79dfc064, 0xd8e0256a, 0x79d80f6f, 0xd8c8381d,
+  0x79d059c8, 0xd8b04c52,
+  0x79c89f6e, 0xd898620c, 0x79c0e062, 0xd880794b, 0x79b91ca4, 0xd868920f,
+  0x79b15435, 0xd850ac5a,
+  0x79a98715, 0xd838c82d, 0x79a1b545, 0xd820e589, 0x7999dec4, 0xd809046e,
+  0x79920392, 0xd7f124dd,
+  0x798a23b1, 0xd7d946d8, 0x79823f20, 0xd7c16a5f, 0x797a55e0, 0xd7a98f73,
+  0x797267f2, 0xd791b616,
+  0x796a7554, 0xd779de47, 0x79627e08, 0xd7620808, 0x795a820e, 0xd74a335b,
+  0x79528167, 0xd732603f,
+  0x794a7c12, 0xd71a8eb5, 0x79427210, 0xd702bec0, 0x793a6361, 0xd6eaf05f,
+  0x79325006, 0xd6d32393,
+  0x792a37fe, 0xd6bb585e, 0x79221b4b, 0xd6a38ec0, 0x7919f9ec, 0xd68bc6ba,
+  0x7911d3e2, 0xd674004e,
+  0x7909a92d, 0xd65c3b7b, 0x790179cd, 0xd6447844, 0x78f945c3, 0xd62cb6a8,
+  0x78f10d0f, 0xd614f6a9,
+  0x78e8cfb2, 0xd5fd3848, 0x78e08dab, 0xd5e57b85, 0x78d846fb, 0xd5cdc062,
+  0x78cffba3, 0xd5b606e0,
+  0x78c7aba2, 0xd59e4eff, 0x78bf56f9, 0xd58698c0, 0x78b6fda8, 0xd56ee424,
+  0x78ae9fb0, 0xd557312d,
+  0x78a63d11, 0xd53f7fda, 0x789dd5cb, 0xd527d02e, 0x789569df, 0xd5102228,
+  0x788cf94c, 0xd4f875ca,
+  0x78848414, 0xd4e0cb15, 0x787c0a36, 0xd4c92209, 0x78738bb3, 0xd4b17aa8,
+  0x786b088c, 0xd499d4f2,
+  0x786280bf, 0xd48230e9, 0x7859f44f, 0xd46a8e8d, 0x7851633b, 0xd452eddf,
+  0x7848cd83, 0xd43b4ee0,
+  0x78403329, 0xd423b191, 0x7837942b, 0xd40c15f3, 0x782ef08b, 0xd3f47c06,
+  0x78264849, 0xd3dce3cd,
+  0x781d9b65, 0xd3c54d47, 0x7814e9df, 0xd3adb876, 0x780c33b8, 0xd396255a,
+  0x780378f1, 0xd37e93f4,
+  0x77fab989, 0xd3670446, 0x77f1f581, 0xd34f764f, 0x77e92cd9, 0xd337ea12,
+  0x77e05f91, 0xd3205f8f,
+  0x77d78daa, 0xd308d6c7, 0x77ceb725, 0xd2f14fba, 0x77c5dc01, 0xd2d9ca6a,
+  0x77bcfc3f, 0xd2c246d8,
+  0x77b417df, 0xd2aac504, 0x77ab2ee2, 0xd29344f0, 0x77a24148, 0xd27bc69c,
+  0x77994f11, 0xd2644a0a,
+  0x7790583e, 0xd24ccf39, 0x77875cce, 0xd235562b, 0x777e5cc3, 0xd21ddee2,
+  0x7775581d, 0xd206695d,
+  0x776c4edb, 0xd1eef59e, 0x776340ff, 0xd1d783a6, 0x775a2e89, 0xd1c01375,
+  0x77511778, 0xd1a8a50d,
+  0x7747fbce, 0xd191386e, 0x773edb8b, 0xd179cd99, 0x7735b6af, 0xd1626490,
+  0x772c8d3a, 0xd14afd52,
+  0x77235f2d, 0xd13397e2, 0x771a2c88, 0xd11c343f, 0x7710f54c, 0xd104d26b,
+  0x7707b979, 0xd0ed7267,
+  0x76fe790e, 0xd0d61434, 0x76f5340e, 0xd0beb7d2, 0x76ebea77, 0xd0a75d42,
+  0x76e29c4b, 0xd0900486,
+  0x76d94989, 0xd078ad9e, 0x76cff232, 0xd061588b, 0x76c69647, 0xd04a054e,
+  0x76bd35c7, 0xd032b3e7,
+  0x76b3d0b4, 0xd01b6459, 0x76aa670d, 0xd00416a3, 0x76a0f8d2, 0xcfeccac7,
+  0x76978605, 0xcfd580c6,
+  0x768e0ea6, 0xcfbe389f, 0x768492b4, 0xcfa6f255, 0x767b1231, 0xcf8fade9,
+  0x76718d1c, 0xcf786b5a,
+  0x76680376, 0xcf612aaa, 0x765e7540, 0xcf49ebda, 0x7654e279, 0xcf32aeeb,
+  0x764b4b23, 0xcf1b73de,
+  0x7641af3d, 0xcf043ab3, 0x76380ec8, 0xceed036b, 0x762e69c4, 0xced5ce08,
+  0x7624c031, 0xcebe9a8a,
+  0x761b1211, 0xcea768f2, 0x76115f63, 0xce903942, 0x7607a828, 0xce790b79,
+  0x75fdec60, 0xce61df99,
+  0x75f42c0b, 0xce4ab5a2, 0x75ea672a, 0xce338d97, 0x75e09dbd, 0xce1c6777,
+  0x75d6cfc5, 0xce054343,
+  0x75ccfd42, 0xcdee20fc, 0x75c32634, 0xcdd700a4, 0x75b94a9c, 0xcdbfe23a,
+  0x75af6a7b, 0xcda8c5c1,
+  0x75a585cf, 0xcd91ab39, 0x759b9c9b, 0xcd7a92a2, 0x7591aedd, 0xcd637bfe,
+  0x7587bc98, 0xcd4c674d,
+  0x757dc5ca, 0xcd355491, 0x7573ca75, 0xcd1e43ca, 0x7569ca99, 0xcd0734f9,
+  0x755fc635, 0xccf0281f,
+  0x7555bd4c, 0xccd91d3d, 0x754bafdc, 0xccc21455, 0x75419de7, 0xccab0d65,
+  0x7537876c, 0xcc940871,
+  0x752d6c6c, 0xcc7d0578, 0x75234ce8, 0xcc66047b, 0x751928e0, 0xcc4f057c,
+  0x750f0054, 0xcc38087b,
+  0x7504d345, 0xcc210d79, 0x74faa1b3, 0xcc0a1477, 0x74f06b9e, 0xcbf31d75,
+  0x74e63108, 0xcbdc2876,
+  0x74dbf1ef, 0xcbc53579, 0x74d1ae55, 0xcbae447f, 0x74c7663a, 0xcb97558a,
+  0x74bd199f, 0xcb80689a,
+  0x74b2c884, 0xcb697db0, 0x74a872e8, 0xcb5294ce, 0x749e18cd, 0xcb3badf3,
+  0x7493ba34, 0xcb24c921,
+  0x7489571c, 0xcb0de658, 0x747eef85, 0xcaf7059a, 0x74748371, 0xcae026e8,
+  0x746a12df, 0xcac94a42,
+  0x745f9dd1, 0xcab26fa9, 0x74552446, 0xca9b971e, 0x744aa63f, 0xca84c0a3,
+  0x744023bc, 0xca6dec37,
+  0x74359cbd, 0xca5719db, 0x742b1144, 0xca404992, 0x74208150, 0xca297b5a,
+  0x7415ece2, 0xca12af37,
+  0x740b53fb, 0xc9fbe527, 0x7400b69a, 0xc9e51d2d, 0x73f614c0, 0xc9ce5748,
+  0x73eb6e6e, 0xc9b7937a,
+  0x73e0c3a3, 0xc9a0d1c5, 0x73d61461, 0xc98a1227, 0x73cb60a8, 0xc97354a4,
+  0x73c0a878, 0xc95c993a,
+  0x73b5ebd1, 0xc945dfec, 0x73ab2ab4, 0xc92f28ba, 0x73a06522, 0xc91873a5,
+  0x73959b1b, 0xc901c0ae,
+  0x738acc9e, 0xc8eb0fd6, 0x737ff9ae, 0xc8d4611d, 0x73752249, 0xc8bdb485,
+  0x736a4671, 0xc8a70a0e,
+  0x735f6626, 0xc89061ba, 0x73548168, 0xc879bb89, 0x73499838, 0xc863177b,
+  0x733eaa96, 0xc84c7593,
+  0x7333b883, 0xc835d5d0, 0x7328c1ff, 0xc81f3834, 0x731dc70a, 0xc8089cbf,
+  0x7312c7a5, 0xc7f20373,
+  0x7307c3d0, 0xc7db6c50, 0x72fcbb8c, 0xc7c4d757, 0x72f1aed9, 0xc7ae4489,
+  0x72e69db7, 0xc797b3e7,
+  0x72db8828, 0xc7812572, 0x72d06e2b, 0xc76a992a, 0x72c54fc1, 0xc7540f11,
+  0x72ba2cea, 0xc73d8727,
+  0x72af05a7, 0xc727016d, 0x72a3d9f7, 0xc7107de4, 0x7298a9dd, 0xc6f9fc8d,
+  0x728d7557, 0xc6e37d69,
+  0x72823c67, 0xc6cd0079, 0x7276ff0d, 0xc6b685bd, 0x726bbd48, 0xc6a00d37,
+  0x7260771b, 0xc68996e7,
+  0x72552c85, 0xc67322ce, 0x7249dd86, 0xc65cb0ed, 0x723e8a20, 0xc6464144,
+  0x72333251, 0xc62fd3d6,
+  0x7227d61c, 0xc61968a2, 0x721c7580, 0xc602ffaa, 0x7211107e, 0xc5ec98ee,
+  0x7205a716, 0xc5d6346f,
+  0x71fa3949, 0xc5bfd22e, 0x71eec716, 0xc5a9722c, 0x71e35080, 0xc593146a,
+  0x71d7d585, 0xc57cb8e9,
+  0x71cc5626, 0xc5665fa9, 0x71c0d265, 0xc55008ab, 0x71b54a41, 0xc539b3f1,
+  0x71a9bdba, 0xc523617a,
+  0x719e2cd2, 0xc50d1149, 0x71929789, 0xc4f6c35d, 0x7186fdde, 0xc4e077b8,
+  0x717b5fd3, 0xc4ca2e5b,
+  0x716fbd68, 0xc4b3e746, 0x7164169d, 0xc49da27a, 0x71586b74, 0xc4875ff9,
+  0x714cbbeb, 0xc4711fc2,
+  0x71410805, 0xc45ae1d7, 0x71354fc0, 0xc444a639, 0x7129931f, 0xc42e6ce8,
+  0x711dd220, 0xc41835e6,
+  0x71120cc5, 0xc4020133, 0x7106430e, 0xc3ebced0, 0x70fa74fc, 0xc3d59ebe,
+  0x70eea28e, 0xc3bf70fd,
+  0x70e2cbc6, 0xc3a94590, 0x70d6f0a4, 0xc3931c76, 0x70cb1128, 0xc37cf5b0,
+  0x70bf2d53, 0xc366d140,
+  0x70b34525, 0xc350af26, 0x70a7589f, 0xc33a8f62, 0x709b67c0, 0xc32471f7,
+  0x708f728b, 0xc30e56e4,
+  0x708378ff, 0xc2f83e2a, 0x70777b1c, 0xc2e227cb, 0x706b78e3, 0xc2cc13c7,
+  0x705f7255, 0xc2b6021f,
+  0x70536771, 0xc29ff2d4, 0x70475839, 0xc289e5e7, 0x703b44ad, 0xc273db58,
+  0x702f2ccd, 0xc25dd329,
+  0x7023109a, 0xc247cd5a, 0x7016f014, 0xc231c9ec, 0x700acb3c, 0xc21bc8e1,
+  0x6ffea212, 0xc205ca38,
+  0x6ff27497, 0xc1efcdf3, 0x6fe642ca, 0xc1d9d412, 0x6fda0cae, 0xc1c3dc97,
+  0x6fcdd241, 0xc1ade781,
+  0x6fc19385, 0xc197f4d4, 0x6fb5507a, 0xc182048d, 0x6fa90921, 0xc16c16b0,
+  0x6f9cbd79, 0xc1562b3d,
+  0x6f906d84, 0xc1404233, 0x6f841942, 0xc12a5b95, 0x6f77c0b3, 0xc1147764,
+  0x6f6b63d8, 0xc0fe959f,
+  0x6f5f02b2, 0xc0e8b648, 0x6f529d40, 0xc0d2d960, 0x6f463383, 0xc0bcfee7,
+  0x6f39c57d, 0xc0a726df,
+  0x6f2d532c, 0xc0915148, 0x6f20dc92, 0xc07b7e23, 0x6f1461b0, 0xc065ad70,
+  0x6f07e285, 0xc04fdf32,
+  0x6efb5f12, 0xc03a1368, 0x6eeed758, 0xc0244a14, 0x6ee24b57, 0xc00e8336,
+  0x6ed5bb10, 0xbff8bece,
+  0x6ec92683, 0xbfe2fcdf, 0x6ebc8db0, 0xbfcd3d69, 0x6eaff099, 0xbfb7806c,
+  0x6ea34f3d, 0xbfa1c5ea,
+  0x6e96a99d, 0xbf8c0de3, 0x6e89ffb9, 0xbf765858, 0x6e7d5193, 0xbf60a54a,
+  0x6e709f2a, 0xbf4af4ba,
+  0x6e63e87f, 0xbf3546a8, 0x6e572d93, 0xbf1f9b16, 0x6e4a6e66, 0xbf09f205,
+  0x6e3daaf8, 0xbef44b74,
+  0x6e30e34a, 0xbedea765, 0x6e24175c, 0xbec905d9, 0x6e174730, 0xbeb366d1,
+  0x6e0a72c5, 0xbe9dca4e,
+  0x6dfd9a1c, 0xbe88304f, 0x6df0bd35, 0xbe7298d7, 0x6de3dc11, 0xbe5d03e6,
+  0x6dd6f6b1, 0xbe47717c,
+  0x6dca0d14, 0xbe31e19b, 0x6dbd1f3c, 0xbe1c5444, 0x6db02d29, 0xbe06c977,
+  0x6da336dc, 0xbdf14135,
+  0x6d963c54, 0xbddbbb7f, 0x6d893d93, 0xbdc63856, 0x6d7c3a98, 0xbdb0b7bb,
+  0x6d6f3365, 0xbd9b39ad,
+  0x6d6227fa, 0xbd85be30, 0x6d551858, 0xbd704542, 0x6d48047e, 0xbd5acee5,
+  0x6d3aec6e, 0xbd455b1a,
+  0x6d2dd027, 0xbd2fe9e2, 0x6d20afac, 0xbd1a7b3d, 0x6d138afb, 0xbd050f2c,
+  0x6d066215, 0xbcefa5b0,
+  0x6cf934fc, 0xbcda3ecb, 0x6cec03af, 0xbcc4da7b, 0x6cdece2f, 0xbcaf78c4,
+  0x6cd1947c, 0xbc9a19a5,
+  0x6cc45698, 0xbc84bd1f, 0x6cb71482, 0xbc6f6333, 0x6ca9ce3b, 0xbc5a0be2,
+  0x6c9c83c3, 0xbc44b72c,
+  0x6c8f351c, 0xbc2f6513, 0x6c81e245, 0xbc1a1598, 0x6c748b3f, 0xbc04c8ba,
+  0x6c67300b, 0xbbef7e7c,
+  0x6c59d0a9, 0xbbda36dd, 0x6c4c6d1a, 0xbbc4f1df, 0x6c3f055d, 0xbbafaf82,
+  0x6c319975, 0xbb9a6fc7,
+  0x6c242960, 0xbb8532b0, 0x6c16b521, 0xbb6ff83c, 0x6c093cb6, 0xbb5ac06d,
+  0x6bfbc021, 0xbb458b43,
+  0x6bee3f62, 0xbb3058c0, 0x6be0ba7b, 0xbb1b28e4, 0x6bd3316a, 0xbb05fbb0,
+  0x6bc5a431, 0xbaf0d125,
+  0x6bb812d1, 0xbadba943, 0x6baa7d49, 0xbac6840c, 0x6b9ce39b, 0xbab16180,
+  0x6b8f45c7, 0xba9c41a0,
+  0x6b81a3cd, 0xba87246d, 0x6b73fdae, 0xba7209e7, 0x6b66536b, 0xba5cf210,
+  0x6b58a503, 0xba47dce8,
+  0x6b4af279, 0xba32ca71, 0x6b3d3bcb, 0xba1dbaaa, 0x6b2f80fb, 0xba08ad95,
+  0x6b21c208, 0xb9f3a332,
+  0x6b13fef5, 0xb9de9b83, 0x6b0637c1, 0xb9c99688, 0x6af86c6c, 0xb9b49442,
+  0x6aea9cf8, 0xb99f94b2,
+  0x6adcc964, 0xb98a97d8, 0x6acef1b2, 0xb9759db6, 0x6ac115e2, 0xb960a64c,
+  0x6ab335f4, 0xb94bb19b,
+  0x6aa551e9, 0xb936bfa4, 0x6a9769c1, 0xb921d067, 0x6a897d7d, 0xb90ce3e6,
+  0x6a7b8d1e, 0xb8f7fa21,
+  0x6a6d98a4, 0xb8e31319, 0x6a5fa010, 0xb8ce2ecf, 0x6a51a361, 0xb8b94d44,
+  0x6a43a29a, 0xb8a46e78,
+  0x6a359db9, 0xb88f926d, 0x6a2794c1, 0xb87ab922, 0x6a1987b0, 0xb865e299,
+  0x6a0b7689, 0xb8510ed4,
+  0x69fd614a, 0xb83c3dd1, 0x69ef47f6, 0xb8276f93, 0x69e12a8c, 0xb812a41a,
+  0x69d3090e, 0xb7fddb67,
+  0x69c4e37a, 0xb7e9157a, 0x69b6b9d3, 0xb7d45255, 0x69a88c19, 0xb7bf91f8,
+  0x699a5a4c, 0xb7aad465,
+  0x698c246c, 0xb796199b, 0x697dea7b, 0xb781619c, 0x696fac78, 0xb76cac69,
+  0x69616a65, 0xb757fa01,
+  0x69532442, 0xb7434a67, 0x6944da10, 0xb72e9d9b, 0x69368bce, 0xb719f39e,
+  0x6928397e, 0xb7054c6f,
+  0x6919e320, 0xb6f0a812, 0x690b88b5, 0xb6dc0685, 0x68fd2a3d, 0xb6c767ca,
+  0x68eec7b9, 0xb6b2cbe2,
+  0x68e06129, 0xb69e32cd, 0x68d1f68f, 0xb6899c8d, 0x68c387e9, 0xb6750921,
+  0x68b5153a, 0xb660788c,
+  0x68a69e81, 0xb64beacd, 0x689823bf, 0xb6375fe5, 0x6889a4f6, 0xb622d7d6,
+  0x687b2224, 0xb60e529f,
+  0x686c9b4b, 0xb5f9d043, 0x685e106c, 0xb5e550c1, 0x684f8186, 0xb5d0d41a,
+  0x6840ee9b, 0xb5bc5a50,
+  0x683257ab, 0xb5a7e362, 0x6823bcb7, 0xb5936f53, 0x68151dbe, 0xb57efe22,
+  0x68067ac3, 0xb56a8fd0,
+  0x67f7d3c5, 0xb556245e, 0x67e928c5, 0xb541bbcd, 0x67da79c3, 0xb52d561e,
+  0x67cbc6c0, 0xb518f351,
+  0x67bd0fbd, 0xb5049368, 0x67ae54ba, 0xb4f03663, 0x679f95b7, 0xb4dbdc42,
+  0x6790d2b6, 0xb4c78507,
+  0x67820bb7, 0xb4b330b3, 0x677340ba, 0xb49edf45, 0x676471c0, 0xb48a90c0,
+  0x67559eca, 0xb4764523,
+  0x6746c7d8, 0xb461fc70, 0x6737ecea, 0xb44db6a8, 0x67290e02, 0xb43973ca,
+  0x671a2b20, 0xb42533d8,
+  0x670b4444, 0xb410f6d3, 0x66fc596f, 0xb3fcbcbb, 0x66ed6aa1, 0xb3e88592,
+  0x66de77dc, 0xb3d45157,
+  0x66cf8120, 0xb3c0200c, 0x66c0866d, 0xb3abf1b2, 0x66b187c3, 0xb397c649,
+  0x66a28524, 0xb3839dd3,
+  0x66937e91, 0xb36f784f, 0x66847408, 0xb35b55bf, 0x6675658c, 0xb3473623,
+  0x6666531d, 0xb333197c,
+  0x66573cbb, 0xb31effcc, 0x66482267, 0xb30ae912, 0x66390422, 0xb2f6d550,
+  0x6629e1ec, 0xb2e2c486,
+  0x661abbc5, 0xb2ceb6b5, 0x660b91af, 0xb2baabde, 0x65fc63a9, 0xb2a6a402,
+  0x65ed31b5, 0xb2929f21,
+  0x65ddfbd3, 0xb27e9d3c, 0x65cec204, 0xb26a9e54, 0x65bf8447, 0xb256a26a,
+  0x65b0429f, 0xb242a97e,
+  0x65a0fd0b, 0xb22eb392, 0x6591b38c, 0xb21ac0a6, 0x65826622, 0xb206d0ba,
+  0x657314cf, 0xb1f2e3d0,
+  0x6563bf92, 0xb1def9e9, 0x6554666d, 0xb1cb1304, 0x6545095f, 0xb1b72f23,
+  0x6535a86b, 0xb1a34e47,
+  0x6526438f, 0xb18f7071, 0x6516dacd, 0xb17b95a0, 0x65076e25, 0xb167bdd7,
+  0x64f7fd98, 0xb153e915,
+  0x64e88926, 0xb140175b, 0x64d910d1, 0xb12c48ab, 0x64c99498, 0xb1187d05,
+  0x64ba147d, 0xb104b46a,
+  0x64aa907f, 0xb0f0eeda, 0x649b08a0, 0xb0dd2c56, 0x648b7ce0, 0xb0c96ce0,
+  0x647bed3f, 0xb0b5b077,
+  0x646c59bf, 0xb0a1f71d, 0x645cc260, 0xb08e40d2, 0x644d2722, 0xb07a8d97,
+  0x643d8806, 0xb066dd6d,
+  0x642de50d, 0xb0533055, 0x641e3e38, 0xb03f864f, 0x640e9386, 0xb02bdf5c,
+  0x63fee4f8, 0xb0183b7d,
+  0x63ef3290, 0xb0049ab3, 0x63df7c4d, 0xaff0fcfe, 0x63cfc231, 0xafdd625f,
+  0x63c0043b, 0xafc9cad7,
+  0x63b0426d, 0xafb63667, 0x63a07cc7, 0xafa2a50f, 0x6390b34a, 0xaf8f16d1,
+  0x6380e5f6, 0xaf7b8bac,
+  0x637114cc, 0xaf6803a2, 0x63613fcd, 0xaf547eb3, 0x635166f9, 0xaf40fce1,
+  0x63418a50, 0xaf2d7e2b,
+  0x6331a9d4, 0xaf1a0293, 0x6321c585, 0xaf068a1a, 0x6311dd64, 0xaef314c0,
+  0x6301f171, 0xaedfa285,
+  0x62f201ac, 0xaecc336c, 0x62e20e17, 0xaeb8c774, 0x62d216b3, 0xaea55e9e,
+  0x62c21b7e, 0xae91f8eb,
+  0x62b21c7b, 0xae7e965b, 0x62a219aa, 0xae6b36f0, 0x6292130c, 0xae57daab,
+  0x628208a1, 0xae44818b,
+  0x6271fa69, 0xae312b92, 0x6261e866, 0xae1dd8c0, 0x6251d298, 0xae0a8916,
+  0x6241b8ff, 0xadf73c96,
+  0x62319b9d, 0xade3f33e, 0x62217a72, 0xadd0ad12, 0x6211557e, 0xadbd6a10,
+  0x62012cc2, 0xadaa2a3b,
+  0x61f1003f, 0xad96ed92, 0x61e0cff5, 0xad83b416, 0x61d09be5, 0xad707dc8,
+  0x61c06410, 0xad5d4aaa,
+  0x61b02876, 0xad4a1aba, 0x619fe918, 0xad36edfc, 0x618fa5f7, 0xad23c46e,
+  0x617f5f12, 0xad109e12,
+  0x616f146c, 0xacfd7ae8, 0x615ec603, 0xacea5af2, 0x614e73da, 0xacd73e30,
+  0x613e1df0, 0xacc424a3,
+  0x612dc447, 0xacb10e4b, 0x611d66de, 0xac9dfb29, 0x610d05b7, 0xac8aeb3e,
+  0x60fca0d2, 0xac77de8b,
+  0x60ec3830, 0xac64d510, 0x60dbcbd1, 0xac51cecf, 0x60cb5bb7, 0xac3ecbc7,
+  0x60bae7e1, 0xac2bcbfa,
+  0x60aa7050, 0xac18cf69, 0x6099f505, 0xac05d613, 0x60897601, 0xabf2dffb,
+  0x6078f344, 0xabdfed1f,
+  0x60686ccf, 0xabccfd83, 0x6057e2a2, 0xabba1125, 0x604754bf, 0xaba72807,
+  0x6036c325, 0xab944229,
+  0x60262dd6, 0xab815f8d, 0x601594d1, 0xab6e8032, 0x6004f819, 0xab5ba41a,
+  0x5ff457ad, 0xab48cb46,
+  0x5fe3b38d, 0xab35f5b5, 0x5fd30bbc, 0xab23236a, 0x5fc26038, 0xab105464,
+  0x5fb1b104, 0xaafd88a4,
+  0x5fa0fe1f, 0xaaeac02c, 0x5f90478a, 0xaad7fafb, 0x5f7f8d46, 0xaac53912,
+  0x5f6ecf53, 0xaab27a73,
+  0x5f5e0db3, 0xaa9fbf1e, 0x5f4d4865, 0xaa8d0713, 0x5f3c7f6b, 0xaa7a5253,
+  0x5f2bb2c5, 0xaa67a0e0,
+  0x5f1ae274, 0xaa54f2ba, 0x5f0a0e77, 0xaa4247e1, 0x5ef936d1, 0xaa2fa056,
+  0x5ee85b82, 0xaa1cfc1a,
+  0x5ed77c8a, 0xaa0a5b2e, 0x5ec699e9, 0xa9f7bd92, 0x5eb5b3a2, 0xa9e52347,
+  0x5ea4c9b3, 0xa9d28c4e,
+  0x5e93dc1f, 0xa9bff8a8, 0x5e82eae5, 0xa9ad6855, 0x5e71f606, 0xa99adb56,
+  0x5e60fd84, 0xa98851ac,
+  0x5e50015d, 0xa975cb57, 0x5e3f0194, 0xa9634858, 0x5e2dfe29, 0xa950c8b0,
+  0x5e1cf71c, 0xa93e4c5f,
+  0x5e0bec6e, 0xa92bd367, 0x5dfade20, 0xa9195dc7, 0x5de9cc33, 0xa906eb82,
+  0x5dd8b6a7, 0xa8f47c97,
+  0x5dc79d7c, 0xa8e21106, 0x5db680b4, 0xa8cfa8d2, 0x5da5604f, 0xa8bd43fa,
+  0x5d943c4e, 0xa8aae280,
+  0x5d8314b1, 0xa8988463, 0x5d71e979, 0xa88629a5, 0x5d60baa7, 0xa873d246,
+  0x5d4f883b, 0xa8617e48,
+  0x5d3e5237, 0xa84f2daa, 0x5d2d189a, 0xa83ce06e, 0x5d1bdb65, 0xa82a9693,
+  0x5d0a9a9a, 0xa818501c,
+  0x5cf95638, 0xa8060d08, 0x5ce80e41, 0xa7f3cd59, 0x5cd6c2b5, 0xa7e1910f,
+  0x5cc57394, 0xa7cf582a,
+  0x5cb420e0, 0xa7bd22ac, 0x5ca2ca99, 0xa7aaf094, 0x5c9170bf, 0xa798c1e5,
+  0x5c801354, 0xa786969e,
+  0x5c6eb258, 0xa7746ec0, 0x5c5d4dcc, 0xa7624a4d, 0x5c4be5b0, 0xa7502943,
+  0x5c3a7a05, 0xa73e0ba5,
+  0x5c290acc, 0xa72bf174, 0x5c179806, 0xa719daae, 0x5c0621b2, 0xa707c757,
+  0x5bf4a7d2, 0xa6f5b76d,
+  0x5be32a67, 0xa6e3aaf2, 0x5bd1a971, 0xa6d1a1e7, 0x5bc024f0, 0xa6bf9c4b,
+  0x5bae9ce7, 0xa6ad9a21,
+  0x5b9d1154, 0xa69b9b68, 0x5b8b8239, 0xa689a022, 0x5b79ef96, 0xa677a84e,
+  0x5b68596d, 0xa665b3ee,
+  0x5b56bfbd, 0xa653c303, 0x5b452288, 0xa641d58c, 0x5b3381ce, 0xa62feb8b,
+  0x5b21dd90, 0xa61e0501,
+  0x5b1035cf, 0xa60c21ee, 0x5afe8a8b, 0xa5fa4252, 0x5aecdbc5, 0xa5e8662f,
+  0x5adb297d, 0xa5d68d85,
+  0x5ac973b5, 0xa5c4b855, 0x5ab7ba6c, 0xa5b2e6a0, 0x5aa5fda5, 0xa5a11866,
+  0x5a943d5e, 0xa58f4da8,
+  0x5a82799a, 0xa57d8666, 0x5a70b258, 0xa56bc2a2, 0x5a5ee79a, 0xa55a025b,
+  0x5a4d1960, 0xa5484594,
+  0x5a3b47ab, 0xa5368c4b, 0x5a29727b, 0xa524d683, 0x5a1799d1, 0xa513243b,
+  0x5a05bdae, 0xa5017575,
+  0x59f3de12, 0xa4efca31, 0x59e1faff, 0xa4de2270, 0x59d01475, 0xa4cc7e32,
+  0x59be2a74, 0xa4badd78,
+  0x59ac3cfd, 0xa4a94043, 0x599a4c12, 0xa497a693, 0x598857b2, 0xa486106a,
+  0x59765fde, 0xa4747dc7,
+  0x59646498, 0xa462eeac, 0x595265df, 0xa4516319, 0x594063b5, 0xa43fdb10,
+  0x592e5e19, 0xa42e568f,
+  0x591c550e, 0xa41cd599, 0x590a4893, 0xa40b582e, 0x58f838a9, 0xa3f9de4e,
+  0x58e62552, 0xa3e867fa,
+  0x58d40e8c, 0xa3d6f534, 0x58c1f45b, 0xa3c585fb, 0x58afd6bd, 0xa3b41a50,
+  0x589db5b3, 0xa3a2b234,
+  0x588b9140, 0xa3914da8, 0x58796962, 0xa37fecac, 0x58673e1b, 0xa36e8f41,
+  0x58550f6c, 0xa35d3567,
+  0x5842dd54, 0xa34bdf20, 0x5830a7d6, 0xa33a8c6c, 0x581e6ef1, 0xa3293d4b,
+  0x580c32a7, 0xa317f1bf,
+  0x57f9f2f8, 0xa306a9c8, 0x57e7afe4, 0xa2f56566, 0x57d5696d, 0xa2e4249b,
+  0x57c31f92, 0xa2d2e766,
+  0x57b0d256, 0xa2c1adc9, 0x579e81b8, 0xa2b077c5, 0x578c2dba, 0xa29f4559,
+  0x5779d65b, 0xa28e1687,
+  0x57677b9d, 0xa27ceb4f, 0x57551d80, 0xa26bc3b2, 0x5742bc06, 0xa25a9fb1,
+  0x5730572e, 0xa2497f4c,
+  0x571deefa, 0xa2386284, 0x570b8369, 0xa2274959, 0x56f9147e, 0xa21633cd,
+  0x56e6a239, 0xa20521e0,
+  0x56d42c99, 0xa1f41392, 0x56c1b3a1, 0xa1e308e4, 0x56af3750, 0xa1d201d7,
+  0x569cb7a8, 0xa1c0fe6c,
+  0x568a34a9, 0xa1affea3, 0x5677ae54, 0xa19f027c, 0x566524aa, 0xa18e09fa,
+  0x565297ab, 0xa17d151b,
+  0x56400758, 0xa16c23e1, 0x562d73b2, 0xa15b364d, 0x561adcb9, 0xa14a4c5e,
+  0x5608426e, 0xa1396617,
+  0x55f5a4d2, 0xa1288376, 0x55e303e6, 0xa117a47e, 0x55d05faa, 0xa106c92f,
+  0x55bdb81f, 0xa0f5f189,
+  0x55ab0d46, 0xa0e51d8c, 0x55985f20, 0xa0d44d3b, 0x5585adad, 0xa0c38095,
+  0x5572f8ed, 0xa0b2b79b,
+  0x556040e2, 0xa0a1f24d, 0x554d858d, 0xa09130ad, 0x553ac6ee, 0xa08072ba,
+  0x55280505, 0xa06fb876,
+  0x55153fd4, 0xa05f01e1, 0x5502775c, 0xa04e4efc, 0x54efab9c, 0xa03d9fc8,
+  0x54dcdc96, 0xa02cf444,
+  0x54ca0a4b, 0xa01c4c73, 0x54b734ba, 0xa00ba853, 0x54a45be6, 0x9ffb07e7,
+  0x54917fce, 0x9fea6b2f,
+  0x547ea073, 0x9fd9d22a, 0x546bbdd7, 0x9fc93cdb, 0x5458d7f9, 0x9fb8ab41,
+  0x5445eedb, 0x9fa81d5e,
+  0x5433027d, 0x9f979331, 0x542012e1, 0x9f870cbc, 0x540d2005, 0x9f7689ff,
+  0x53fa29ed, 0x9f660afb,
+  0x53e73097, 0x9f558fb0, 0x53d43406, 0x9f45181f, 0x53c13439, 0x9f34a449,
+  0x53ae3131, 0x9f24342f,
+  0x539b2af0, 0x9f13c7d0, 0x53882175, 0x9f035f2e, 0x537514c2, 0x9ef2fa49,
+  0x536204d7, 0x9ee29922,
+  0x534ef1b5, 0x9ed23bb9, 0x533bdb5d, 0x9ec1e210, 0x5328c1d0, 0x9eb18c26,
+  0x5315a50e, 0x9ea139fd,
+  0x53028518, 0x9e90eb94, 0x52ef61ee, 0x9e80a0ee, 0x52dc3b92, 0x9e705a09,
+  0x52c91204, 0x9e6016e8,
+  0x52b5e546, 0x9e4fd78a, 0x52a2b556, 0x9e3f9bf0, 0x528f8238, 0x9e2f641b,
+  0x527c4bea, 0x9e1f300b,
+  0x5269126e, 0x9e0effc1, 0x5255d5c5, 0x9dfed33e, 0x524295f0, 0x9deeaa82,
+  0x522f52ee, 0x9dde858e,
+  0x521c0cc2, 0x9dce6463, 0x5208c36a, 0x9dbe4701, 0x51f576ea, 0x9dae2d68,
+  0x51e22740, 0x9d9e179a,
+  0x51ced46e, 0x9d8e0597, 0x51bb7e75, 0x9d7df75f, 0x51a82555, 0x9d6decf4,
+  0x5194c910, 0x9d5de656,
+  0x518169a5, 0x9d4de385, 0x516e0715, 0x9d3de482, 0x515aa162, 0x9d2de94d,
+  0x5147388c, 0x9d1df1e9,
+  0x5133cc94, 0x9d0dfe54, 0x51205d7b, 0x9cfe0e8f, 0x510ceb40, 0x9cee229c,
+  0x50f975e6, 0x9cde3a7b,
+  0x50e5fd6d, 0x9cce562c, 0x50d281d5, 0x9cbe75b0, 0x50bf031f, 0x9cae9907,
+  0x50ab814d, 0x9c9ec033,
+  0x5097fc5e, 0x9c8eeb34, 0x50847454, 0x9c7f1a0a, 0x5070e92f, 0x9c6f4cb6,
+  0x505d5af1, 0x9c5f8339,
+  0x5049c999, 0x9c4fbd93, 0x50363529, 0x9c3ffbc5, 0x50229da1, 0x9c303dcf,
+  0x500f0302, 0x9c2083b3,
+  0x4ffb654d, 0x9c10cd70, 0x4fe7c483, 0x9c011b08, 0x4fd420a4, 0x9bf16c7a,
+  0x4fc079b1, 0x9be1c1c8,
+  0x4faccfab, 0x9bd21af3, 0x4f992293, 0x9bc277fa, 0x4f857269, 0x9bb2d8de,
+  0x4f71bf2e, 0x9ba33da0,
+  0x4f5e08e3, 0x9b93a641, 0x4f4a4f89, 0x9b8412c1, 0x4f369320, 0x9b748320,
+  0x4f22d3aa, 0x9b64f760,
+  0x4f0f1126, 0x9b556f81, 0x4efb4b96, 0x9b45eb83, 0x4ee782fb, 0x9b366b68,
+  0x4ed3b755, 0x9b26ef2f,
+  0x4ebfe8a5, 0x9b1776da, 0x4eac16eb, 0x9b080268, 0x4e984229, 0x9af891db,
+  0x4e846a60, 0x9ae92533,
+  0x4e708f8f, 0x9ad9bc71, 0x4e5cb1b9, 0x9aca5795, 0x4e48d0dd, 0x9abaf6a1,
+  0x4e34ecfc, 0x9aab9993,
+  0x4e210617, 0x9a9c406e, 0x4e0d1c30, 0x9a8ceb31, 0x4df92f46, 0x9a7d99de,
+  0x4de53f5a, 0x9a6e4c74,
+  0x4dd14c6e, 0x9a5f02f5, 0x4dbd5682, 0x9a4fbd61, 0x4da95d96, 0x9a407bb9,
+  0x4d9561ac, 0x9a313dfc,
+  0x4d8162c4, 0x9a22042d, 0x4d6d60df, 0x9a12ce4b, 0x4d595bfe, 0x9a039c57,
+  0x4d455422, 0x99f46e51,
+  0x4d31494b, 0x99e5443b, 0x4d1d3b7a, 0x99d61e14, 0x4d092ab0, 0x99c6fbde,
+  0x4cf516ee, 0x99b7dd99,
+  0x4ce10034, 0x99a8c345, 0x4ccce684, 0x9999ace3, 0x4cb8c9dd, 0x998a9a74,
+  0x4ca4aa41, 0x997b8bf8,
+  0x4c9087b1, 0x996c816f, 0x4c7c622d, 0x995d7adc, 0x4c6839b7, 0x994e783d,
+  0x4c540e4e, 0x993f7993,
+  0x4c3fdff4, 0x99307ee0, 0x4c2baea9, 0x99218824, 0x4c177a6e, 0x9912955f,
+  0x4c034345, 0x9903a691,
+  0x4bef092d, 0x98f4bbbc, 0x4bdacc28, 0x98e5d4e0, 0x4bc68c36, 0x98d6f1fe,
+  0x4bb24958, 0x98c81316,
+  0x4b9e0390, 0x98b93828, 0x4b89badd, 0x98aa6136, 0x4b756f40, 0x989b8e40,
+  0x4b6120bb, 0x988cbf46,
+  0x4b4ccf4d, 0x987df449, 0x4b387af9, 0x986f2d4a, 0x4b2423be, 0x98606a49,
+  0x4b0fc99d, 0x9851ab46,
+  0x4afb6c98, 0x9842f043, 0x4ae70caf, 0x98343940, 0x4ad2a9e2, 0x9825863d,
+  0x4abe4433, 0x9816d73b,
+  0x4aa9dba2, 0x98082c3b, 0x4a957030, 0x97f9853d, 0x4a8101de, 0x97eae242,
+  0x4a6c90ad, 0x97dc4349,
+  0x4a581c9e, 0x97cda855, 0x4a43a5b0, 0x97bf1165, 0x4a2f2be6, 0x97b07e7a,
+  0x4a1aaf3f, 0x97a1ef94,
+  0x4a062fbd, 0x979364b5, 0x49f1ad61, 0x9784dddc, 0x49dd282a, 0x97765b0a,
+  0x49c8a01b, 0x9767dc41,
+  0x49b41533, 0x9759617f, 0x499f8774, 0x974aeac6, 0x498af6df, 0x973c7817,
+  0x49766373, 0x972e0971,
+  0x4961cd33, 0x971f9ed7, 0x494d341e, 0x97113847, 0x49389836, 0x9702d5c3,
+  0x4923f97b, 0x96f4774b,
+  0x490f57ee, 0x96e61ce0, 0x48fab391, 0x96d7c682, 0x48e60c62, 0x96c97432,
+  0x48d16265, 0x96bb25f0,
+  0x48bcb599, 0x96acdbbe, 0x48a805ff, 0x969e959b, 0x48935397, 0x96905388,
+  0x487e9e64, 0x96821585,
+  0x4869e665, 0x9673db94, 0x48552b9b, 0x9665a5b4, 0x48406e08, 0x965773e7,
+  0x482badab, 0x9649462d,
+  0x4816ea86, 0x963b1c86, 0x48022499, 0x962cf6f2, 0x47ed5be6, 0x961ed574,
+  0x47d8906d, 0x9610b80a,
+  0x47c3c22f, 0x96029eb6, 0x47aef12c, 0x95f48977, 0x479a1d67, 0x95e67850,
+  0x478546de, 0x95d86b3f,
+  0x47706d93, 0x95ca6247, 0x475b9188, 0x95bc5d66, 0x4746b2bc, 0x95ae5c9f,
+  0x4731d131, 0x95a05ff0,
+  0x471cece7, 0x9592675c, 0x470805df, 0x958472e2, 0x46f31c1a, 0x95768283,
+  0x46de2f99, 0x9568963f,
+  0x46c9405c, 0x955aae17, 0x46b44e65, 0x954cca0c, 0x469f59b4, 0x953eea1e,
+  0x468a624a, 0x95310e4e,
+  0x46756828, 0x9523369c, 0x46606b4e, 0x95156308, 0x464b6bbe, 0x95079394,
+  0x46366978, 0x94f9c83f,
+  0x4621647d, 0x94ec010b, 0x460c5cce, 0x94de3df8, 0x45f7526b, 0x94d07f05,
+  0x45e24556, 0x94c2c435,
+  0x45cd358f, 0x94b50d87, 0x45b82318, 0x94a75afd, 0x45a30df0, 0x9499ac95,
+  0x458df619, 0x948c0252,
+  0x4578db93, 0x947e5c33, 0x4563be60, 0x9470ba39, 0x454e9e80, 0x94631c65,
+  0x45397bf4, 0x945582b7,
+  0x452456bd, 0x9447ed2f, 0x450f2edb, 0x943a5bcf, 0x44fa0450, 0x942cce96,
+  0x44e4d71c, 0x941f4585,
+  0x44cfa740, 0x9411c09e, 0x44ba74bd, 0x94043fdf, 0x44a53f93, 0x93f6c34a,
+  0x449007c4, 0x93e94adf,
+  0x447acd50, 0x93dbd6a0, 0x44659039, 0x93ce668b, 0x4450507e, 0x93c0faa3,
+  0x443b0e21, 0x93b392e6,
+  0x4425c923, 0x93a62f57, 0x44108184, 0x9398cff5, 0x43fb3746, 0x938b74c1,
+  0x43e5ea68, 0x937e1dbb,
+  0x43d09aed, 0x9370cae4, 0x43bb48d4, 0x93637c3d, 0x43a5f41e, 0x935631c5,
+  0x43909ccd, 0x9348eb7e,
+  0x437b42e1, 0x933ba968, 0x4365e65b, 0x932e6b84, 0x4350873c, 0x932131d1,
+  0x433b2585, 0x9313fc51,
+  0x4325c135, 0x9306cb04, 0x43105a50, 0x92f99deb, 0x42faf0d4, 0x92ec7505,
+  0x42e584c3, 0x92df5054,
+  0x42d0161e, 0x92d22fd9, 0x42baa4e6, 0x92c51392, 0x42a5311b, 0x92b7fb82,
+  0x428fbabe, 0x92aae7a8,
+  0x427a41d0, 0x929dd806, 0x4264c653, 0x9290cc9b, 0x424f4845, 0x9283c568,
+  0x4239c7aa, 0x9276c26d,
+  0x42244481, 0x9269c3ac, 0x420ebecb, 0x925cc924, 0x41f93689, 0x924fd2d7,
+  0x41e3abbc, 0x9242e0c4,
+  0x41ce1e65, 0x9235f2ec, 0x41b88e84, 0x9229094f, 0x41a2fc1a, 0x921c23ef,
+  0x418d6729, 0x920f42cb,
+  0x4177cfb1, 0x920265e4, 0x416235b2, 0x91f58d3b, 0x414c992f, 0x91e8b8d0,
+  0x4136fa27, 0x91dbe8a4,
+  0x4121589b, 0x91cf1cb6, 0x410bb48c, 0x91c25508, 0x40f60dfb, 0x91b5919a,
+  0x40e064ea, 0x91a8d26d,
+  0x40cab958, 0x919c1781, 0x40b50b46, 0x918f60d6, 0x409f5ab6, 0x9182ae6d,
+  0x4089a7a8, 0x91760047,
+  0x4073f21d, 0x91695663, 0x405e3a16, 0x915cb0c3, 0x40487f94, 0x91500f67,
+  0x4032c297, 0x91437250,
+  0x401d0321, 0x9136d97d, 0x40074132, 0x912a44f0, 0x3ff17cca, 0x911db4a9,
+  0x3fdbb5ec, 0x911128a8,
+  0x3fc5ec98, 0x9104a0ee, 0x3fb020ce, 0x90f81d7b, 0x3f9a5290, 0x90eb9e50,
+  0x3f8481dd, 0x90df236e,
+  0x3f6eaeb8, 0x90d2acd4, 0x3f58d921, 0x90c63a83, 0x3f430119, 0x90b9cc7d,
+  0x3f2d26a0, 0x90ad62c0,
+  0x3f1749b8, 0x90a0fd4e, 0x3f016a61, 0x90949c28, 0x3eeb889c, 0x90883f4d,
+  0x3ed5a46b, 0x907be6be,
+  0x3ebfbdcd, 0x906f927c, 0x3ea9d4c3, 0x90634287, 0x3e93e950, 0x9056f6df,
+  0x3e7dfb73, 0x904aaf86,
+  0x3e680b2c, 0x903e6c7b, 0x3e52187f, 0x90322dbf, 0x3e3c2369, 0x9025f352,
+  0x3e262bee, 0x9019bd36,
+  0x3e10320d, 0x900d8b69, 0x3dfa35c8, 0x90015dee, 0x3de4371f, 0x8ff534c4,
+  0x3dce3614, 0x8fe90fec,
+  0x3db832a6, 0x8fdcef66, 0x3da22cd7, 0x8fd0d333, 0x3d8c24a8, 0x8fc4bb53,
+  0x3d761a19, 0x8fb8a7c7,
+  0x3d600d2c, 0x8fac988f, 0x3d49fde1, 0x8fa08dab, 0x3d33ec39, 0x8f94871d,
+  0x3d1dd835, 0x8f8884e4,
+  0x3d07c1d6, 0x8f7c8701, 0x3cf1a91c, 0x8f708d75, 0x3cdb8e09, 0x8f649840,
+  0x3cc5709e, 0x8f58a761,
+  0x3caf50da, 0x8f4cbadb, 0x3c992ec0, 0x8f40d2ad, 0x3c830a50, 0x8f34eed8,
+  0x3c6ce38a, 0x8f290f5c,
+  0x3c56ba70, 0x8f1d343a, 0x3c408f03, 0x8f115d72, 0x3c2a6142, 0x8f058b04,
+  0x3c143130, 0x8ef9bcf2,
+  0x3bfdfecd, 0x8eedf33b, 0x3be7ca1a, 0x8ee22de0, 0x3bd19318, 0x8ed66ce1,
+  0x3bbb59c7, 0x8ecab040,
+  0x3ba51e29, 0x8ebef7fb, 0x3b8ee03e, 0x8eb34415, 0x3b78a007, 0x8ea7948c,
+  0x3b625d86, 0x8e9be963,
+  0x3b4c18ba, 0x8e904298, 0x3b35d1a5, 0x8e84a02d, 0x3b1f8848, 0x8e790222,
+  0x3b093ca3, 0x8e6d6877,
+  0x3af2eeb7, 0x8e61d32e, 0x3adc9e86, 0x8e564246, 0x3ac64c0f, 0x8e4ab5bf,
+  0x3aaff755, 0x8e3f2d9b,
+  0x3a99a057, 0x8e33a9da, 0x3a834717, 0x8e282a7b, 0x3a6ceb96, 0x8e1caf80,
+  0x3a568dd4, 0x8e1138ea,
+  0x3a402dd2, 0x8e05c6b7, 0x3a29cb91, 0x8dfa58ea, 0x3a136712, 0x8deeef82,
+  0x39fd0056, 0x8de38a80,
+  0x39e6975e, 0x8dd829e4, 0x39d02c2a, 0x8dcccdaf, 0x39b9bebc, 0x8dc175e0,
+  0x39a34f13, 0x8db6227a,
+  0x398cdd32, 0x8daad37b, 0x39766919, 0x8d9f88e5, 0x395ff2c9, 0x8d9442b8,
+  0x39497a43, 0x8d8900f3,
+  0x3932ff87, 0x8d7dc399, 0x391c8297, 0x8d728aa9, 0x39060373, 0x8d675623,
+  0x38ef821c, 0x8d5c2609,
+  0x38d8fe93, 0x8d50fa59, 0x38c278d9, 0x8d45d316, 0x38abf0ef, 0x8d3ab03f,
+  0x389566d6, 0x8d2f91d5,
+  0x387eda8e, 0x8d2477d8, 0x38684c19, 0x8d196249, 0x3851bb77, 0x8d0e5127,
+  0x383b28a9, 0x8d034474,
+  0x382493b0, 0x8cf83c30, 0x380dfc8d, 0x8ced385b, 0x37f76341, 0x8ce238f6,
+  0x37e0c7cc, 0x8cd73e01,
+  0x37ca2a30, 0x8ccc477d, 0x37b38a6d, 0x8cc1556a, 0x379ce885, 0x8cb667c8,
+  0x37864477, 0x8cab7e98,
+  0x376f9e46, 0x8ca099da, 0x3758f5f2, 0x8c95b98f, 0x37424b7b, 0x8c8addb7,
+  0x372b9ee3, 0x8c800652,
+  0x3714f02a, 0x8c753362, 0x36fe3f52, 0x8c6a64e5, 0x36e78c5b, 0x8c5f9ade,
+  0x36d0d746, 0x8c54d54c,
+  0x36ba2014, 0x8c4a142f, 0x36a366c6, 0x8c3f5788, 0x368cab5c, 0x8c349f58,
+  0x3675edd9, 0x8c29eb9f,
+  0x365f2e3b, 0x8c1f3c5d, 0x36486c86, 0x8c149192, 0x3631a8b8, 0x8c09eb40,
+  0x361ae2d3, 0x8bff4966,
+  0x36041ad9, 0x8bf4ac05, 0x35ed50c9, 0x8bea131e, 0x35d684a6, 0x8bdf7eb0,
+  0x35bfb66e, 0x8bd4eebc,
+  0x35a8e625, 0x8bca6343, 0x359213c9, 0x8bbfdc44, 0x357b3f5d, 0x8bb559c1,
+  0x356468e2, 0x8baadbba,
+  0x354d9057, 0x8ba0622f, 0x3536b5be, 0x8b95ed21, 0x351fd918, 0x8b8b7c8f,
+  0x3508fa66, 0x8b81107b,
+  0x34f219a8, 0x8b76a8e4, 0x34db36df, 0x8b6c45cc, 0x34c4520d, 0x8b61e733,
+  0x34ad6b32, 0x8b578d18,
+  0x34968250, 0x8b4d377c, 0x347f9766, 0x8b42e661, 0x3468aa76, 0x8b3899c6,
+  0x3451bb81, 0x8b2e51ab,
+  0x343aca87, 0x8b240e11, 0x3423d78a, 0x8b19cef8, 0x340ce28b, 0x8b0f9462,
+  0x33f5eb89, 0x8b055e4d,
+  0x33def287, 0x8afb2cbb, 0x33c7f785, 0x8af0ffac, 0x33b0fa84, 0x8ae6d720,
+  0x3399fb85, 0x8adcb318,
+  0x3382fa88, 0x8ad29394, 0x336bf78f, 0x8ac87894, 0x3354f29b, 0x8abe6219,
+  0x333debab, 0x8ab45024,
+  0x3326e2c3, 0x8aaa42b4, 0x330fd7e1, 0x8aa039cb, 0x32f8cb07, 0x8a963567,
+  0x32e1bc36, 0x8a8c358b,
+  0x32caab6f, 0x8a823a36, 0x32b398b3, 0x8a784368, 0x329c8402, 0x8a6e5123,
+  0x32856d5e, 0x8a646365,
+  0x326e54c7, 0x8a5a7a31, 0x32573a3f, 0x8a509585, 0x32401dc6, 0x8a46b564,
+  0x3228ff5c, 0x8a3cd9cc,
+  0x3211df04, 0x8a3302be, 0x31fabcbd, 0x8a29303b, 0x31e39889, 0x8a1f6243,
+  0x31cc7269, 0x8a1598d6,
+  0x31b54a5e, 0x8a0bd3f5, 0x319e2067, 0x8a0213a0, 0x3186f487, 0x89f857d8,
+  0x316fc6be, 0x89eea09d,
+  0x3158970e, 0x89e4edef, 0x31416576, 0x89db3fcf, 0x312a31f8, 0x89d1963c,
+  0x3112fc95, 0x89c7f138,
+  0x30fbc54d, 0x89be50c3, 0x30e48c22, 0x89b4b4dd, 0x30cd5115, 0x89ab1d87,
+  0x30b61426, 0x89a18ac0,
+  0x309ed556, 0x8997fc8a, 0x308794a6, 0x898e72e4, 0x30705217, 0x8984edcf,
+  0x30590dab, 0x897b6d4c,
+  0x3041c761, 0x8971f15a, 0x302a7f3a, 0x896879fb, 0x30133539, 0x895f072e,
+  0x2ffbe95d, 0x895598f3,
+  0x2fe49ba7, 0x894c2f4c, 0x2fcd4c19, 0x8942ca39, 0x2fb5fab2, 0x893969b9,
+  0x2f9ea775, 0x89300dce,
+  0x2f875262, 0x8926b677, 0x2f6ffb7a, 0x891d63b5, 0x2f58a2be, 0x89141589,
+  0x2f41482e, 0x890acbf2,
+  0x2f29ebcc, 0x890186f2, 0x2f128d99, 0x88f84687, 0x2efb2d95, 0x88ef0ab4,
+  0x2ee3cbc1, 0x88e5d378,
+  0x2ecc681e, 0x88dca0d3, 0x2eb502ae, 0x88d372c6, 0x2e9d9b70, 0x88ca4951,
+  0x2e863267, 0x88c12475,
+  0x2e6ec792, 0x88b80432, 0x2e575af3, 0x88aee888, 0x2e3fec8b, 0x88a5d177,
+  0x2e287c5a, 0x889cbf01,
+  0x2e110a62, 0x8893b125, 0x2df996a3, 0x888aa7e3, 0x2de2211e, 0x8881a33d,
+  0x2dcaa9d5, 0x8878a332,
+  0x2db330c7, 0x886fa7c2, 0x2d9bb5f6, 0x8866b0ef, 0x2d843964, 0x885dbeb8,
+  0x2d6cbb10, 0x8854d11e,
+  0x2d553afc, 0x884be821, 0x2d3db928, 0x884303c1, 0x2d263596, 0x883a23ff,
+  0x2d0eb046, 0x883148db,
+  0x2cf72939, 0x88287256, 0x2cdfa071, 0x881fa06f, 0x2cc815ee, 0x8816d327,
+  0x2cb089b1, 0x880e0a7f,
+  0x2c98fbba, 0x88054677, 0x2c816c0c, 0x87fc870f, 0x2c69daa6, 0x87f3cc48,
+  0x2c52478a, 0x87eb1621,
+  0x2c3ab2b9, 0x87e2649b, 0x2c231c33, 0x87d9b7b7, 0x2c0b83fa, 0x87d10f75,
+  0x2bf3ea0d, 0x87c86bd5,
+  0x2bdc4e6f, 0x87bfccd7, 0x2bc4b120, 0x87b7327d, 0x2bad1221, 0x87ae9cc5,
+  0x2b957173, 0x87a60bb1,
+  0x2b7dcf17, 0x879d7f41, 0x2b662b0e, 0x8794f774, 0x2b4e8558, 0x878c744d,
+  0x2b36ddf7, 0x8783f5ca,
+  0x2b1f34eb, 0x877b7bec, 0x2b078a36, 0x877306b4, 0x2aefddd8, 0x876a9621,
+  0x2ad82fd2, 0x87622a35,
+  0x2ac08026, 0x8759c2ef, 0x2aa8ced3, 0x87516050, 0x2a911bdc, 0x87490258,
+  0x2a796740, 0x8740a907,
+  0x2a61b101, 0x8738545e, 0x2a49f920, 0x8730045d, 0x2a323f9e, 0x8727b905,
+  0x2a1a847b, 0x871f7255,
+  0x2a02c7b8, 0x8717304e, 0x29eb0957, 0x870ef2f1, 0x29d34958, 0x8706ba3d,
+  0x29bb87bc, 0x86fe8633,
+  0x29a3c485, 0x86f656d3, 0x298bffb2, 0x86ee2c1e, 0x29743946, 0x86e60614,
+  0x295c7140, 0x86dde4b5,
+  0x2944a7a2, 0x86d5c802, 0x292cdc6d, 0x86cdaffa, 0x29150fa1, 0x86c59c9f,
+  0x28fd4140, 0x86bd8df0,
+  0x28e5714b, 0x86b583ee, 0x28cd9fc1, 0x86ad7e99, 0x28b5cca5, 0x86a57df2,
+  0x289df7f8, 0x869d81f8,
+  0x288621b9, 0x86958aac, 0x286e49ea, 0x868d980e, 0x2856708d, 0x8685aa20,
+  0x283e95a1, 0x867dc0e0,
+  0x2826b928, 0x8675dc4f, 0x280edb23, 0x866dfc6e, 0x27f6fb92, 0x8666213c,
+  0x27df1a77, 0x865e4abb,
+  0x27c737d3, 0x865678eb, 0x27af53a6, 0x864eabcb, 0x27976df1, 0x8646e35c,
+  0x277f86b5, 0x863f1f9e,
+  0x27679df4, 0x86376092, 0x274fb3ae, 0x862fa638, 0x2737c7e3, 0x8627f091,
+  0x271fda96, 0x86203f9c,
+  0x2707ebc7, 0x86189359, 0x26effb76, 0x8610ebca, 0x26d809a5, 0x860948ef,
+  0x26c01655, 0x8601aac7,
+  0x26a82186, 0x85fa1153, 0x26902b39, 0x85f27c93, 0x26783370, 0x85eaec88,
+  0x26603a2c, 0x85e36132,
+  0x26483f6c, 0x85dbda91, 0x26304333, 0x85d458a6, 0x26184581, 0x85ccdb70,
+  0x26004657, 0x85c562f1,
+  0x25e845b6, 0x85bdef28, 0x25d0439f, 0x85b68015, 0x25b84012, 0x85af15b9,
+  0x25a03b11, 0x85a7b015,
+  0x2588349d, 0x85a04f28, 0x25702cb7, 0x8598f2f3, 0x2558235f, 0x85919b76,
+  0x25401896, 0x858a48b1,
+  0x25280c5e, 0x8582faa5, 0x250ffeb7, 0x857bb152, 0x24f7efa2, 0x85746cb8,
+  0x24dfdf20, 0x856d2cd7,
+  0x24c7cd33, 0x8565f1b0, 0x24afb9da, 0x855ebb44, 0x2497a517, 0x85578991,
+  0x247f8eec, 0x85505c99,
+  0x24677758, 0x8549345c, 0x244f5e5c, 0x854210db, 0x243743fa, 0x853af214,
+  0x241f2833, 0x8533d809,
+  0x24070b08, 0x852cc2bb, 0x23eeec78, 0x8525b228, 0x23d6cc87, 0x851ea652,
+  0x23beab33, 0x85179f39,
+  0x23a6887f, 0x85109cdd, 0x238e646a, 0x85099f3e, 0x23763ef7, 0x8502a65c,
+  0x235e1826, 0x84fbb239,
+  0x2345eff8, 0x84f4c2d4, 0x232dc66d, 0x84edd82d, 0x23159b88, 0x84e6f244,
+  0x22fd6f48, 0x84e0111b,
+  0x22e541af, 0x84d934b1, 0x22cd12bd, 0x84d25d06, 0x22b4e274, 0x84cb8a1b,
+  0x229cb0d5, 0x84c4bbf0,
+  0x22847de0, 0x84bdf286, 0x226c4996, 0x84b72ddb, 0x225413f8, 0x84b06df2,
+  0x223bdd08, 0x84a9b2ca,
+  0x2223a4c5, 0x84a2fc62, 0x220b6b32, 0x849c4abd, 0x21f3304f, 0x84959dd9,
+  0x21daf41d, 0x848ef5b7,
+  0x21c2b69c, 0x84885258, 0x21aa77cf, 0x8481b3bb, 0x219237b5, 0x847b19e1,
+  0x2179f64f, 0x847484ca,
+  0x2161b3a0, 0x846df477, 0x21496fa7, 0x846768e7, 0x21312a65, 0x8460e21a,
+  0x2118e3dc, 0x845a6012,
+  0x21009c0c, 0x8453e2cf, 0x20e852f6, 0x844d6a50, 0x20d0089c, 0x8446f695,
+  0x20b7bcfe, 0x844087a0,
+  0x209f701c, 0x843a1d70, 0x208721f9, 0x8433b806, 0x206ed295, 0x842d5762,
+  0x205681f1, 0x8426fb84,
+  0x203e300d, 0x8420a46c, 0x2025dcec, 0x841a521a, 0x200d888d, 0x84140490,
+  0x1ff532f2, 0x840dbbcc,
+  0x1fdcdc1b, 0x840777d0, 0x1fc4840a, 0x8401389b, 0x1fac2abf, 0x83fafe2e,
+  0x1f93d03c, 0x83f4c889,
+  0x1f7b7481, 0x83ee97ad, 0x1f63178f, 0x83e86b99, 0x1f4ab968, 0x83e2444d,
+  0x1f325a0b, 0x83dc21cb,
+  0x1f19f97b, 0x83d60412, 0x1f0197b8, 0x83cfeb22, 0x1ee934c3, 0x83c9d6fc,
+  0x1ed0d09d, 0x83c3c7a0,
+  0x1eb86b46, 0x83bdbd0e, 0x1ea004c1, 0x83b7b746, 0x1e879d0d, 0x83b1b649,
+  0x1e6f342c, 0x83abba17,
+  0x1e56ca1e, 0x83a5c2b0, 0x1e3e5ee5, 0x839fd014, 0x1e25f282, 0x8399e244,
+  0x1e0d84f5, 0x8393f940,
+  0x1df5163f, 0x838e1507, 0x1ddca662, 0x8388359b, 0x1dc4355e, 0x83825afb,
+  0x1dabc334, 0x837c8528,
+  0x1d934fe5, 0x8376b422, 0x1d7adb73, 0x8370e7e9, 0x1d6265dd, 0x836b207d,
+  0x1d49ef26, 0x83655ddf,
+  0x1d31774d, 0x835fa00f, 0x1d18fe54, 0x8359e70d, 0x1d00843d, 0x835432d8,
+  0x1ce80906, 0x834e8373,
+  0x1ccf8cb3, 0x8348d8dc, 0x1cb70f43, 0x83433314, 0x1c9e90b8, 0x833d921b,
+  0x1c861113, 0x8337f5f1,
+  0x1c6d9053, 0x83325e97, 0x1c550e7c, 0x832ccc0d, 0x1c3c8b8c, 0x83273e52,
+  0x1c240786, 0x8321b568,
+  0x1c0b826a, 0x831c314e, 0x1bf2fc3a, 0x8316b205, 0x1bda74f6, 0x8311378d,
+  0x1bc1ec9e, 0x830bc1e6,
+  0x1ba96335, 0x83065110, 0x1b90d8bb, 0x8300e50b, 0x1b784d30, 0x82fb7dd8,
+  0x1b5fc097, 0x82f61b77,
+  0x1b4732ef, 0x82f0bde8, 0x1b2ea43a, 0x82eb652b, 0x1b161479, 0x82e61141,
+  0x1afd83ad, 0x82e0c22a,
+  0x1ae4f1d6, 0x82db77e5, 0x1acc5ef6, 0x82d63274, 0x1ab3cb0d, 0x82d0f1d5,
+  0x1a9b361d, 0x82cbb60b,
+  0x1a82a026, 0x82c67f14, 0x1a6a0929, 0x82c14cf1, 0x1a517128, 0x82bc1fa2,
+  0x1a38d823, 0x82b6f727,
+  0x1a203e1b, 0x82b1d381, 0x1a07a311, 0x82acb4b0, 0x19ef0707, 0x82a79ab3,
+  0x19d669fc, 0x82a2858c,
+  0x19bdcbf3, 0x829d753a, 0x19a52ceb, 0x829869be, 0x198c8ce7, 0x82936317,
+  0x1973ebe6, 0x828e6146,
+  0x195b49ea, 0x8289644b, 0x1942a6f3, 0x82846c26, 0x192a0304, 0x827f78d8,
+  0x19115e1c, 0x827a8a61,
+  0x18f8b83c, 0x8275a0c0, 0x18e01167, 0x8270bbf7, 0x18c7699b, 0x826bdc04,
+  0x18aec0db, 0x826700e9,
+  0x18961728, 0x82622aa6, 0x187d6c82, 0x825d593a, 0x1864c0ea, 0x82588ca7,
+  0x184c1461, 0x8253c4eb,
+  0x183366e9, 0x824f0208, 0x181ab881, 0x824a43fe, 0x1802092c, 0x82458acc,
+  0x17e958ea, 0x8240d673,
+  0x17d0a7bc, 0x823c26f3, 0x17b7f5a3, 0x82377c4c, 0x179f429f, 0x8232d67f,
+  0x17868eb3, 0x822e358b,
+  0x176dd9de, 0x82299971, 0x17552422, 0x82250232, 0x173c6d80, 0x82206fcc,
+  0x1723b5f9, 0x821be240,
+  0x170afd8d, 0x82175990, 0x16f2443e, 0x8212d5b9, 0x16d98a0c, 0x820e56be,
+  0x16c0cef9, 0x8209dc9e,
+  0x16a81305, 0x82056758, 0x168f5632, 0x8200f6ef, 0x1676987f, 0x81fc8b60,
+  0x165dd9f0, 0x81f824ae,
+  0x16451a83, 0x81f3c2d7, 0x162c5a3b, 0x81ef65dc, 0x16139918, 0x81eb0dbe,
+  0x15fad71b, 0x81e6ba7c,
+  0x15e21445, 0x81e26c16, 0x15c95097, 0x81de228d, 0x15b08c12, 0x81d9dde1,
+  0x1597c6b7, 0x81d59e13,
+  0x157f0086, 0x81d16321, 0x15663982, 0x81cd2d0c, 0x154d71aa, 0x81c8fbd6,
+  0x1534a901, 0x81c4cf7d,
+  0x151bdf86, 0x81c0a801, 0x1503153a, 0x81bc8564, 0x14ea4a1f, 0x81b867a5,
+  0x14d17e36, 0x81b44ec4,
+  0x14b8b17f, 0x81b03ac2, 0x149fe3fc, 0x81ac2b9e, 0x148715ae, 0x81a82159,
+  0x146e4694, 0x81a41bf4,
+  0x145576b1, 0x81a01b6d, 0x143ca605, 0x819c1fc5, 0x1423d492, 0x819828fd,
+  0x140b0258, 0x81943715,
+  0x13f22f58, 0x81904a0c, 0x13d95b93, 0x818c61e3, 0x13c0870a, 0x81887e9a,
+  0x13a7b1bf, 0x8184a032,
+  0x138edbb1, 0x8180c6a9, 0x137604e2, 0x817cf201, 0x135d2d53, 0x8179223a,
+  0x13445505, 0x81755754,
+  0x132b7bf9, 0x8171914e, 0x1312a230, 0x816dd02a, 0x12f9c7aa, 0x816a13e6,
+  0x12e0ec6a, 0x81665c84,
+  0x12c8106f, 0x8162aa04, 0x12af33ba, 0x815efc65, 0x1296564d, 0x815b53a8,
+  0x127d7829, 0x8157afcd,
+  0x1264994e, 0x815410d4, 0x124bb9be, 0x815076bd, 0x1232d979, 0x814ce188,
+  0x1219f880, 0x81495136,
+  0x120116d5, 0x8145c5c7, 0x11e83478, 0x81423f3a, 0x11cf516a, 0x813ebd90,
+  0x11b66dad, 0x813b40ca,
+  0x119d8941, 0x8137c8e6, 0x1184a427, 0x813455e6, 0x116bbe60, 0x8130e7c9,
+  0x1152d7ed, 0x812d7e8f,
+  0x1139f0cf, 0x812a1a3a, 0x11210907, 0x8126bac8, 0x11082096, 0x8123603a,
+  0x10ef377d, 0x81200a90,
+  0x10d64dbd, 0x811cb9ca, 0x10bd6356, 0x81196de9, 0x10a4784b, 0x811626ec,
+  0x108b8c9b, 0x8112e4d4,
+  0x1072a048, 0x810fa7a0, 0x1059b352, 0x810c6f52, 0x1040c5bb, 0x81093be8,
+  0x1027d784, 0x81060d63,
+  0x100ee8ad, 0x8102e3c4, 0xff5f938, 0x80ffbf0a, 0xfdd0926, 0x80fc9f35,
+  0xfc41876, 0x80f98446,
+  0xfab272b, 0x80f66e3c, 0xf923546, 0x80f35d19, 0xf7942c7, 0x80f050db,
+  0xf604faf, 0x80ed4984,
+  0xf475bff, 0x80ea4712, 0xf2e67b8, 0x80e74987, 0xf1572dc, 0x80e450e2,
+  0xefc7d6b, 0x80e15d24,
+  0xee38766, 0x80de6e4c, 0xeca90ce, 0x80db845b, 0xeb199a4, 0x80d89f51,
+  0xe98a1e9, 0x80d5bf2e,
+  0xe7fa99e, 0x80d2e3f2, 0xe66b0c3, 0x80d00d9d, 0xe4db75b, 0x80cd3c2f,
+  0xe34bd66, 0x80ca6fa9,
+  0xe1bc2e4, 0x80c7a80a, 0xe02c7d7, 0x80c4e553, 0xde9cc40, 0x80c22784,
+  0xdd0d01f, 0x80bf6e9c,
+  0xdb7d376, 0x80bcba9d, 0xd9ed646, 0x80ba0b85, 0xd85d88f, 0x80b76156,
+  0xd6cda53, 0x80b4bc0e,
+  0xd53db92, 0x80b21baf, 0xd3adc4e, 0x80af8039, 0xd21dc87, 0x80ace9ab,
+  0xd08dc3f, 0x80aa5806,
+  0xcefdb76, 0x80a7cb49, 0xcd6da2d, 0x80a54376, 0xcbdd865, 0x80a2c08b,
+  0xca4d620, 0x80a04289,
+  0xc8bd35e, 0x809dc971, 0xc72d020, 0x809b5541, 0xc59cc68, 0x8098e5fb,
+  0xc40c835, 0x80967b9f,
+  0xc27c389, 0x8094162c, 0xc0ebe66, 0x8091b5a2, 0xbf5b8cb, 0x808f5a02,
+  0xbdcb2bb, 0x808d034c,
+  0xbc3ac35, 0x808ab180, 0xbaaa53b, 0x8088649e, 0xb919dcf, 0x80861ca6,
+  0xb7895f0, 0x8083d998,
+  0xb5f8d9f, 0x80819b74, 0xb4684df, 0x807f623b, 0xb2d7baf, 0x807d2dec,
+  0xb147211, 0x807afe87,
+  0xafb6805, 0x8078d40d, 0xae25d8d, 0x8076ae7e, 0xac952aa, 0x80748dd9,
+  0xab0475c, 0x8072721f,
+  0xa973ba5, 0x80705b50, 0xa7e2f85, 0x806e496c, 0xa6522fe, 0x806c3c74,
+  0xa4c1610, 0x806a3466,
+  0xa3308bd, 0x80683143, 0xa19fb04, 0x8066330c, 0xa00ece8, 0x806439c0,
+  0x9e7de6a, 0x80624560,
+  0x9cecf89, 0x806055eb, 0x9b5c048, 0x805e6b62, 0x99cb0a7, 0x805c85c4,
+  0x983a0a7, 0x805aa512,
+  0x96a9049, 0x8058c94c, 0x9517f8f, 0x8056f272, 0x9386e78, 0x80552084,
+  0x91f5d06, 0x80535381,
+  0x9064b3a, 0x80518b6b, 0x8ed3916, 0x804fc841, 0x8d42699, 0x804e0a04,
+  0x8bb13c5, 0x804c50b2,
+  0x8a2009a, 0x804a9c4d, 0x888ed1b, 0x8048ecd5, 0x86fd947, 0x80474248,
+  0x856c520, 0x80459ca9,
+  0x83db0a7, 0x8043fbf6, 0x8249bdd, 0x80426030, 0x80b86c2, 0x8040c956,
+  0x7f27157, 0x803f376a,
+  0x7d95b9e, 0x803daa6a, 0x7c04598, 0x803c2257, 0x7a72f45, 0x803a9f31,
+  0x78e18a7, 0x803920f8,
+  0x77501be, 0x8037a7ac, 0x75bea8c, 0x8036334e, 0x742d311, 0x8034c3dd,
+  0x729bb4e, 0x80335959,
+  0x710a345, 0x8031f3c2, 0x6f78af6, 0x80309318, 0x6de7262, 0x802f375d,
+  0x6c5598a, 0x802de08e,
+  0x6ac406f, 0x802c8ead, 0x6932713, 0x802b41ba, 0x67a0d76, 0x8029f9b4,
+  0x660f398, 0x8028b69c,
+  0x647d97c, 0x80277872, 0x62ebf22, 0x80263f36, 0x615a48b, 0x80250ae7,
+  0x5fc89b8, 0x8023db86,
+  0x5e36ea9, 0x8022b114, 0x5ca5361, 0x80218b8f, 0x5b137df, 0x80206af8,
+  0x5981c26, 0x801f4f4f,
+  0x57f0035, 0x801e3895, 0x565e40d, 0x801d26c8, 0x54cc7b1, 0x801c19ea,
+  0x533ab20, 0x801b11fa,
+  0x51a8e5c, 0x801a0ef8, 0x5017165, 0x801910e4, 0x4e8543e, 0x801817bf,
+  0x4cf36e5, 0x80172388,
+  0x4b6195d, 0x80163440, 0x49cfba7, 0x801549e6, 0x483ddc3, 0x8014647b,
+  0x46abfb3, 0x801383fe,
+  0x451a177, 0x8012a86f, 0x4388310, 0x8011d1d0, 0x41f6480, 0x8011001f,
+  0x40645c7, 0x8010335c,
+  0x3ed26e6, 0x800f6b88, 0x3d407df, 0x800ea8a3, 0x3bae8b2, 0x800deaad,
+  0x3a1c960, 0x800d31a5,
+  0x388a9ea, 0x800c7d8c, 0x36f8a51, 0x800bce63, 0x3566a96, 0x800b2427,
+  0x33d4abb, 0x800a7edb,
+  0x3242abf, 0x8009de7e, 0x30b0aa4, 0x80094310, 0x2f1ea6c, 0x8008ac90,
+  0x2d8ca16, 0x80081b00,
+  0x2bfa9a4, 0x80078e5e, 0x2a68917, 0x800706ac, 0x28d6870, 0x800683e8,
+  0x27447b0, 0x80060614,
+  0x25b26d7, 0x80058d2f, 0x24205e8, 0x80051939, 0x228e4e2, 0x8004aa32,
+  0x20fc3c6, 0x8004401a,
+  0x1f6a297, 0x8003daf1, 0x1dd8154, 0x80037ab7, 0x1c45ffe, 0x80031f6d,
+  0x1ab3e97, 0x8002c912,
+  0x1921d20, 0x800277a6, 0x178fb99, 0x80022b29, 0x15fda03, 0x8001e39b,
+  0x146b860, 0x8001a0fd,
+  0x12d96b1, 0x8001634e, 0x11474f6, 0x80012a8e, 0xfb5330, 0x8000f6bd,
+  0xe23160, 0x8000c7dc,
+  0xc90f88, 0x80009dea, 0xafeda8, 0x800078e7, 0x96cbc1, 0x800058d4, 0x7da9d4,
+  0x80003daf,
+  0x6487e3, 0x8000277a, 0x4b65ee, 0x80001635, 0x3243f5, 0x800009df, 0x1921fb,
+  0x80000278,
+};
+
+/**   
+* \par   
+* cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
   
+* \par   
+* C command to generate the table   
+* 
   
+* for(i = 0; i< N; i++)   
+* {   
+*   cos_factors[i]= 2 * cos((2*i+1)*c/2);   
+* } 
   
+* \par   
+* where N is the number of factors to generate and c is pi/(2*N)   
+* \par   
+* Then converted to q31 format by multiplying with 2^31 and saturated if required.   
+*/
+
+
+static const q31_t cos_factorsQ31_128[128] = {
+  0x7fff6216, 0x7ffa72d1, 0x7ff09478, 0x7fe1c76b, 0x7fce0c3e, 0x7fb563b3,
+  0x7f97cebd, 0x7f754e80,
+  0x7f4de451, 0x7f2191b4, 0x7ef05860, 0x7eba3a39, 0x7e7f3957, 0x7e3f57ff,
+  0x7dfa98a8, 0x7db0fdf8,
+  0x7d628ac6, 0x7d0f4218, 0x7cb72724, 0x7c5a3d50, 0x7bf88830, 0x7b920b89,
+  0x7b26cb4f, 0x7ab6cba4,
+  0x7a4210d8, 0x79c89f6e, 0x794a7c12, 0x78c7aba2, 0x78403329, 0x77b417df,
+  0x77235f2d, 0x768e0ea6,
+  0x75f42c0b, 0x7555bd4c, 0x74b2c884, 0x740b53fb, 0x735f6626, 0x72af05a7,
+  0x71fa3949, 0x71410805,
+  0x708378ff, 0x6fc19385, 0x6efb5f12, 0x6e30e34a, 0x6d6227fa, 0x6c8f351c,
+  0x6bb812d1, 0x6adcc964,
+  0x69fd614a, 0x6919e320, 0x683257ab, 0x6746c7d8, 0x66573cbb, 0x6563bf92,
+  0x646c59bf, 0x637114cc,
+  0x6271fa69, 0x616f146c, 0x60686ccf, 0x5f5e0db3, 0x5e50015d, 0x5d3e5237,
+  0x5c290acc, 0x5b1035cf,
+  0x59f3de12, 0x58d40e8c, 0x57b0d256, 0x568a34a9, 0x556040e2, 0x5433027d,
+  0x53028518, 0x51ced46e,
+  0x5097fc5e, 0x4f5e08e3, 0x4e210617, 0x4ce10034, 0x4b9e0390, 0x4a581c9e,
+  0x490f57ee, 0x47c3c22f,
+  0x46756828, 0x452456bd, 0x43d09aed, 0x427a41d0, 0x4121589b, 0x3fc5ec98,
+  0x3e680b2c, 0x3d07c1d6,
+  0x3ba51e29, 0x3a402dd2, 0x38d8fe93, 0x376f9e46, 0x36041ad9, 0x34968250,
+  0x3326e2c3, 0x31b54a5e,
+  0x3041c761, 0x2ecc681e, 0x2d553afc, 0x2bdc4e6f, 0x2a61b101, 0x28e5714b,
+  0x27679df4, 0x25e845b6,
+  0x24677758, 0x22e541af, 0x2161b3a0, 0x1fdcdc1b, 0x1e56ca1e, 0x1ccf8cb3,
+  0x1b4732ef, 0x19bdcbf3,
+  0x183366e9, 0x16a81305, 0x151bdf86, 0x138edbb1, 0x120116d5, 0x1072a048,
+  0xee38766, 0xd53db92,
+  0xbc3ac35, 0xa3308bd, 0x8a2009a, 0x710a345, 0x57f0035, 0x3ed26e6, 0x25b26d7,
+  0xc90f88,
+};
+
+static const q31_t cos_factorsQ31_512[512] = {
+  0x7ffff621, 0x7fffa72c, 0x7fff0943, 0x7ffe1c65, 0x7ffce093, 0x7ffb55ce,
+  0x7ff97c18, 0x7ff75370,
+  0x7ff4dbd9, 0x7ff21553, 0x7feeffe1, 0x7feb9b85, 0x7fe7e841, 0x7fe3e616,
+  0x7fdf9508, 0x7fdaf519,
+  0x7fd6064c, 0x7fd0c8a3, 0x7fcb3c23, 0x7fc560cf, 0x7fbf36aa, 0x7fb8bdb8,
+  0x7fb1f5fc, 0x7faadf7c,
+  0x7fa37a3c, 0x7f9bc640, 0x7f93c38c, 0x7f8b7227, 0x7f82d214, 0x7f79e35a,
+  0x7f70a5fe, 0x7f671a05,
+  0x7f5d3f75, 0x7f531655, 0x7f489eaa, 0x7f3dd87c, 0x7f32c3d1, 0x7f2760af,
+  0x7f1baf1e, 0x7f0faf25,
+  0x7f0360cb, 0x7ef6c418, 0x7ee9d914, 0x7edc9fc6, 0x7ecf1837, 0x7ec14270,
+  0x7eb31e78, 0x7ea4ac58,
+  0x7e95ec1a, 0x7e86ddc6, 0x7e778166, 0x7e67d703, 0x7e57dea7, 0x7e47985b,
+  0x7e37042a, 0x7e26221f,
+  0x7e14f242, 0x7e0374a0, 0x7df1a942, 0x7ddf9034, 0x7dcd2981, 0x7dba7534,
+  0x7da77359, 0x7d9423fc,
+  0x7d808728, 0x7d6c9ce9, 0x7d58654d, 0x7d43e05e, 0x7d2f0e2b, 0x7d19eebf,
+  0x7d048228, 0x7ceec873,
+  0x7cd8c1ae, 0x7cc26de5, 0x7cabcd28, 0x7c94df83, 0x7c7da505, 0x7c661dbc,
+  0x7c4e49b7, 0x7c362904,
+  0x7c1dbbb3, 0x7c0501d2, 0x7bebfb70, 0x7bd2a89e, 0x7bb9096b, 0x7b9f1de6,
+  0x7b84e61f, 0x7b6a6227,
+  0x7b4f920e, 0x7b3475e5, 0x7b190dbc, 0x7afd59a4, 0x7ae159ae, 0x7ac50dec,
+  0x7aa8766f, 0x7a8b9348,
+  0x7a6e648a, 0x7a50ea47, 0x7a332490, 0x7a151378, 0x79f6b711, 0x79d80f6f,
+  0x79b91ca4, 0x7999dec4,
+  0x797a55e0, 0x795a820e, 0x793a6361, 0x7919f9ec, 0x78f945c3, 0x78d846fb,
+  0x78b6fda8, 0x789569df,
+  0x78738bb3, 0x7851633b, 0x782ef08b, 0x780c33b8, 0x77e92cd9, 0x77c5dc01,
+  0x77a24148, 0x777e5cc3,
+  0x775a2e89, 0x7735b6af, 0x7710f54c, 0x76ebea77, 0x76c69647, 0x76a0f8d2,
+  0x767b1231, 0x7654e279,
+  0x762e69c4, 0x7607a828, 0x75e09dbd, 0x75b94a9c, 0x7591aedd, 0x7569ca99,
+  0x75419de7, 0x751928e0,
+  0x74f06b9e, 0x74c7663a, 0x749e18cd, 0x74748371, 0x744aa63f, 0x74208150,
+  0x73f614c0, 0x73cb60a8,
+  0x73a06522, 0x73752249, 0x73499838, 0x731dc70a, 0x72f1aed9, 0x72c54fc1,
+  0x7298a9dd, 0x726bbd48,
+  0x723e8a20, 0x7211107e, 0x71e35080, 0x71b54a41, 0x7186fdde, 0x71586b74,
+  0x7129931f, 0x70fa74fc,
+  0x70cb1128, 0x709b67c0, 0x706b78e3, 0x703b44ad, 0x700acb3c, 0x6fda0cae,
+  0x6fa90921, 0x6f77c0b3,
+  0x6f463383, 0x6f1461b0, 0x6ee24b57, 0x6eaff099, 0x6e7d5193, 0x6e4a6e66,
+  0x6e174730, 0x6de3dc11,
+  0x6db02d29, 0x6d7c3a98, 0x6d48047e, 0x6d138afb, 0x6cdece2f, 0x6ca9ce3b,
+  0x6c748b3f, 0x6c3f055d,
+  0x6c093cb6, 0x6bd3316a, 0x6b9ce39b, 0x6b66536b, 0x6b2f80fb, 0x6af86c6c,
+  0x6ac115e2, 0x6a897d7d,
+  0x6a51a361, 0x6a1987b0, 0x69e12a8c, 0x69a88c19, 0x696fac78, 0x69368bce,
+  0x68fd2a3d, 0x68c387e9,
+  0x6889a4f6, 0x684f8186, 0x68151dbe, 0x67da79c3, 0x679f95b7, 0x676471c0,
+  0x67290e02, 0x66ed6aa1,
+  0x66b187c3, 0x6675658c, 0x66390422, 0x65fc63a9, 0x65bf8447, 0x65826622,
+  0x6545095f, 0x65076e25,
+  0x64c99498, 0x648b7ce0, 0x644d2722, 0x640e9386, 0x63cfc231, 0x6390b34a,
+  0x635166f9, 0x6311dd64,
+  0x62d216b3, 0x6292130c, 0x6251d298, 0x6211557e, 0x61d09be5, 0x618fa5f7,
+  0x614e73da, 0x610d05b7,
+  0x60cb5bb7, 0x60897601, 0x604754bf, 0x6004f819, 0x5fc26038, 0x5f7f8d46,
+  0x5f3c7f6b, 0x5ef936d1,
+  0x5eb5b3a2, 0x5e71f606, 0x5e2dfe29, 0x5de9cc33, 0x5da5604f, 0x5d60baa7,
+  0x5d1bdb65, 0x5cd6c2b5,
+  0x5c9170bf, 0x5c4be5b0, 0x5c0621b2, 0x5bc024f0, 0x5b79ef96, 0x5b3381ce,
+  0x5aecdbc5, 0x5aa5fda5,
+  0x5a5ee79a, 0x5a1799d1, 0x59d01475, 0x598857b2, 0x594063b5, 0x58f838a9,
+  0x58afd6bd, 0x58673e1b,
+  0x581e6ef1, 0x57d5696d, 0x578c2dba, 0x5742bc06, 0x56f9147e, 0x56af3750,
+  0x566524aa, 0x561adcb9,
+  0x55d05faa, 0x5585adad, 0x553ac6ee, 0x54efab9c, 0x54a45be6, 0x5458d7f9,
+  0x540d2005, 0x53c13439,
+  0x537514c2, 0x5328c1d0, 0x52dc3b92, 0x528f8238, 0x524295f0, 0x51f576ea,
+  0x51a82555, 0x515aa162,
+  0x510ceb40, 0x50bf031f, 0x5070e92f, 0x50229da1, 0x4fd420a4, 0x4f857269,
+  0x4f369320, 0x4ee782fb,
+  0x4e984229, 0x4e48d0dd, 0x4df92f46, 0x4da95d96, 0x4d595bfe, 0x4d092ab0,
+  0x4cb8c9dd, 0x4c6839b7,
+  0x4c177a6e, 0x4bc68c36, 0x4b756f40, 0x4b2423be, 0x4ad2a9e2, 0x4a8101de,
+  0x4a2f2be6, 0x49dd282a,
+  0x498af6df, 0x49389836, 0x48e60c62, 0x48935397, 0x48406e08, 0x47ed5be6,
+  0x479a1d67, 0x4746b2bc,
+  0x46f31c1a, 0x469f59b4, 0x464b6bbe, 0x45f7526b, 0x45a30df0, 0x454e9e80,
+  0x44fa0450, 0x44a53f93,
+  0x4450507e, 0x43fb3746, 0x43a5f41e, 0x4350873c, 0x42faf0d4, 0x42a5311b,
+  0x424f4845, 0x41f93689,
+  0x41a2fc1a, 0x414c992f, 0x40f60dfb, 0x409f5ab6, 0x40487f94, 0x3ff17cca,
+  0x3f9a5290, 0x3f430119,
+  0x3eeb889c, 0x3e93e950, 0x3e3c2369, 0x3de4371f, 0x3d8c24a8, 0x3d33ec39,
+  0x3cdb8e09, 0x3c830a50,
+  0x3c2a6142, 0x3bd19318, 0x3b78a007, 0x3b1f8848, 0x3ac64c0f, 0x3a6ceb96,
+  0x3a136712, 0x39b9bebc,
+  0x395ff2c9, 0x39060373, 0x38abf0ef, 0x3851bb77, 0x37f76341, 0x379ce885,
+  0x37424b7b, 0x36e78c5b,
+  0x368cab5c, 0x3631a8b8, 0x35d684a6, 0x357b3f5d, 0x351fd918, 0x34c4520d,
+  0x3468aa76, 0x340ce28b,
+  0x33b0fa84, 0x3354f29b, 0x32f8cb07, 0x329c8402, 0x32401dc6, 0x31e39889,
+  0x3186f487, 0x312a31f8,
+  0x30cd5115, 0x30705217, 0x30133539, 0x2fb5fab2, 0x2f58a2be, 0x2efb2d95,
+  0x2e9d9b70, 0x2e3fec8b,
+  0x2de2211e, 0x2d843964, 0x2d263596, 0x2cc815ee, 0x2c69daa6, 0x2c0b83fa,
+  0x2bad1221, 0x2b4e8558,
+  0x2aefddd8, 0x2a911bdc, 0x2a323f9e, 0x29d34958, 0x29743946, 0x29150fa1,
+  0x28b5cca5, 0x2856708d,
+  0x27f6fb92, 0x27976df1, 0x2737c7e3, 0x26d809a5, 0x26783370, 0x26184581,
+  0x25b84012, 0x2558235f,
+  0x24f7efa2, 0x2497a517, 0x243743fa, 0x23d6cc87, 0x23763ef7, 0x23159b88,
+  0x22b4e274, 0x225413f8,
+  0x21f3304f, 0x219237b5, 0x21312a65, 0x20d0089c, 0x206ed295, 0x200d888d,
+  0x1fac2abf, 0x1f4ab968,
+  0x1ee934c3, 0x1e879d0d, 0x1e25f282, 0x1dc4355e, 0x1d6265dd, 0x1d00843d,
+  0x1c9e90b8, 0x1c3c8b8c,
+  0x1bda74f6, 0x1b784d30, 0x1b161479, 0x1ab3cb0d, 0x1a517128, 0x19ef0707,
+  0x198c8ce7, 0x192a0304,
+  0x18c7699b, 0x1864c0ea, 0x1802092c, 0x179f429f, 0x173c6d80, 0x16d98a0c,
+  0x1676987f, 0x16139918,
+  0x15b08c12, 0x154d71aa, 0x14ea4a1f, 0x148715ae, 0x1423d492, 0x13c0870a,
+  0x135d2d53, 0x12f9c7aa,
+  0x1296564d, 0x1232d979, 0x11cf516a, 0x116bbe60, 0x11082096, 0x10a4784b,
+  0x1040c5bb, 0xfdd0926,
+  0xf7942c7, 0xf1572dc, 0xeb199a4, 0xe4db75b, 0xde9cc40, 0xd85d88f, 0xd21dc87,
+  0xcbdd865,
+  0xc59cc68, 0xbf5b8cb, 0xb919dcf, 0xb2d7baf, 0xac952aa, 0xa6522fe, 0xa00ece8,
+  0x99cb0a7,
+  0x9386e78, 0x8d42699, 0x86fd947, 0x80b86c2, 0x7a72f45, 0x742d311, 0x6de7262,
+  0x67a0d76,
+  0x615a48b, 0x5b137df, 0x54cc7b1, 0x4e8543e, 0x483ddc3, 0x41f6480, 0x3bae8b2,
+  0x3566a96,
+  0x2f1ea6c, 0x28d6870, 0x228e4e2, 0x1c45ffe, 0x15fda03, 0xfb5330, 0x96cbc1,
+  0x3243f5,
+};
+
+static const q31_t cos_factorsQ31_2048[2048] = {
+  0x7fffff62, 0x7ffffa73, 0x7ffff094, 0x7fffe1c6, 0x7fffce09, 0x7fffb55c,
+  0x7fff97c1, 0x7fff7536,
+  0x7fff4dbb, 0x7fff2151, 0x7ffeeff8, 0x7ffeb9b0, 0x7ffe7e79, 0x7ffe3e52,
+  0x7ffdf93c, 0x7ffdaf37,
+  0x7ffd6042, 0x7ffd0c5f, 0x7ffcb38c, 0x7ffc55ca, 0x7ffbf319, 0x7ffb8b78,
+  0x7ffb1ee9, 0x7ffaad6a,
+  0x7ffa36fc, 0x7ff9bba0, 0x7ff93b54, 0x7ff8b619, 0x7ff82bef, 0x7ff79cd6,
+  0x7ff708ce, 0x7ff66fd7,
+  0x7ff5d1f1, 0x7ff52f1d, 0x7ff48759, 0x7ff3daa6, 0x7ff32905, 0x7ff27275,
+  0x7ff1b6f6, 0x7ff0f688,
+  0x7ff0312c, 0x7fef66e1, 0x7fee97a7, 0x7fedc37e, 0x7fecea67, 0x7fec0c62,
+  0x7feb296d, 0x7fea418b,
+  0x7fe954ba, 0x7fe862fa, 0x7fe76c4c, 0x7fe670b0, 0x7fe57025, 0x7fe46aac,
+  0x7fe36045, 0x7fe250ef,
+  0x7fe13cac, 0x7fe0237a, 0x7fdf055a, 0x7fdde24d, 0x7fdcba51, 0x7fdb8d67,
+  0x7fda5b8f, 0x7fd924ca,
+  0x7fd7e917, 0x7fd6a875, 0x7fd562e7, 0x7fd4186a, 0x7fd2c900, 0x7fd174a8,
+  0x7fd01b63, 0x7fcebd31,
+  0x7fcd5a11, 0x7fcbf203, 0x7fca8508, 0x7fc91320, 0x7fc79c4b, 0x7fc62089,
+  0x7fc49fda, 0x7fc31a3d,
+  0x7fc18fb4, 0x7fc0003e, 0x7fbe6bdb, 0x7fbcd28b, 0x7fbb344e, 0x7fb99125,
+  0x7fb7e90f, 0x7fb63c0d,
+  0x7fb48a1e, 0x7fb2d343, 0x7fb1177b, 0x7faf56c7, 0x7fad9127, 0x7fabc69b,
+  0x7fa9f723, 0x7fa822bf,
+  0x7fa6496e, 0x7fa46b32, 0x7fa2880b, 0x7fa09ff7, 0x7f9eb2f8, 0x7f9cc10d,
+  0x7f9aca37, 0x7f98ce76,
+  0x7f96cdc9, 0x7f94c831, 0x7f92bdad, 0x7f90ae3f, 0x7f8e99e6, 0x7f8c80a1,
+  0x7f8a6272, 0x7f883f58,
+  0x7f861753, 0x7f83ea64, 0x7f81b88a, 0x7f7f81c6, 0x7f7d4617, 0x7f7b057e,
+  0x7f78bffb, 0x7f76758e,
+  0x7f742637, 0x7f71d1f6, 0x7f6f78cb, 0x7f6d1ab6, 0x7f6ab7b8, 0x7f684fd0,
+  0x7f65e2ff, 0x7f637144,
+  0x7f60faa0, 0x7f5e7f13, 0x7f5bfe9d, 0x7f59793e, 0x7f56eef5, 0x7f545fc5,
+  0x7f51cbab, 0x7f4f32a9,
+  0x7f4c94be, 0x7f49f1eb, 0x7f474a30, 0x7f449d8c, 0x7f41ec01, 0x7f3f358d,
+  0x7f3c7a31, 0x7f39b9ee,
+  0x7f36f4c3, 0x7f342ab1, 0x7f315bb7, 0x7f2e87d6, 0x7f2baf0d, 0x7f28d15d,
+  0x7f25eec7, 0x7f230749,
+  0x7f201ae5, 0x7f1d299a, 0x7f1a3368, 0x7f173850, 0x7f143852, 0x7f11336d,
+  0x7f0e29a3, 0x7f0b1af2,
+  0x7f08075c, 0x7f04eedf, 0x7f01d17d, 0x7efeaf36, 0x7efb8809, 0x7ef85bf7,
+  0x7ef52b00, 0x7ef1f524,
+  0x7eeeba62, 0x7eeb7abc, 0x7ee83632, 0x7ee4ecc3, 0x7ee19e6f, 0x7ede4b38,
+  0x7edaf31c, 0x7ed7961c,
+  0x7ed43438, 0x7ed0cd70, 0x7ecd61c5, 0x7ec9f137, 0x7ec67bc5, 0x7ec3016f,
+  0x7ebf8237, 0x7ebbfe1c,
+  0x7eb8751e, 0x7eb4e73d, 0x7eb1547a, 0x7eadbcd4, 0x7eaa204c, 0x7ea67ee2,
+  0x7ea2d896, 0x7e9f2d68,
+  0x7e9b7d58, 0x7e97c867, 0x7e940e94, 0x7e904fe0, 0x7e8c8c4b, 0x7e88c3d5,
+  0x7e84f67e, 0x7e812447,
+  0x7e7d4d2f, 0x7e797136, 0x7e75905d, 0x7e71aaa4, 0x7e6dc00c, 0x7e69d093,
+  0x7e65dc3b, 0x7e61e303,
+  0x7e5de4ec, 0x7e59e1f5, 0x7e55da20, 0x7e51cd6c, 0x7e4dbbd9, 0x7e49a567,
+  0x7e458a17, 0x7e4169e9,
+  0x7e3d44dd, 0x7e391af3, 0x7e34ec2b, 0x7e30b885, 0x7e2c8002, 0x7e2842a2,
+  0x7e240064, 0x7e1fb94a,
+  0x7e1b6d53, 0x7e171c7f, 0x7e12c6ce, 0x7e0e6c42, 0x7e0a0cd9, 0x7e05a894,
+  0x7e013f74, 0x7dfcd178,
+  0x7df85ea0, 0x7df3e6ee, 0x7def6a60, 0x7deae8f7, 0x7de662b3, 0x7de1d795,
+  0x7ddd479d, 0x7dd8b2ca,
+  0x7dd4191d, 0x7dcf7a96, 0x7dcad736, 0x7dc62efc, 0x7dc181e8, 0x7dbccffc,
+  0x7db81936, 0x7db35d98,
+  0x7dae9d21, 0x7da9d7d2, 0x7da50dab, 0x7da03eab, 0x7d9b6ad3, 0x7d969224,
+  0x7d91b49e, 0x7d8cd240,
+  0x7d87eb0a, 0x7d82fefe, 0x7d7e0e1c, 0x7d791862, 0x7d741dd2, 0x7d6f1e6c,
+  0x7d6a1a31, 0x7d65111f,
+  0x7d600338, 0x7d5af07b, 0x7d55d8e9, 0x7d50bc82, 0x7d4b9b46, 0x7d467536,
+  0x7d414a51, 0x7d3c1a98,
+  0x7d36e60b, 0x7d31acaa, 0x7d2c6e76, 0x7d272b6e, 0x7d21e393, 0x7d1c96e5,
+  0x7d174564, 0x7d11ef11,
+  0x7d0c93eb, 0x7d0733f3, 0x7d01cf29, 0x7cfc658d, 0x7cf6f720, 0x7cf183e1,
+  0x7cec0bd1, 0x7ce68ef0,
+  0x7ce10d3f, 0x7cdb86bd, 0x7cd5fb6a, 0x7cd06b48, 0x7ccad656, 0x7cc53c94,
+  0x7cbf9e03, 0x7cb9faa2,
+  0x7cb45272, 0x7caea574, 0x7ca8f3a7, 0x7ca33d0c, 0x7c9d81a3, 0x7c97c16b,
+  0x7c91fc66, 0x7c8c3294,
+  0x7c8663f4, 0x7c809088, 0x7c7ab84e, 0x7c74db48, 0x7c6ef976, 0x7c6912d7,
+  0x7c63276d, 0x7c5d3737,
+  0x7c574236, 0x7c514869, 0x7c4b49d2, 0x7c45466f, 0x7c3f3e42, 0x7c39314b,
+  0x7c331f8a, 0x7c2d08ff,
+  0x7c26edab, 0x7c20cd8d, 0x7c1aa8a6, 0x7c147ef6, 0x7c0e507e, 0x7c081d3d,
+  0x7c01e534, 0x7bfba863,
+  0x7bf566cb, 0x7bef206b, 0x7be8d544, 0x7be28556, 0x7bdc30a1, 0x7bd5d726,
+  0x7bcf78e5, 0x7bc915dd,
+  0x7bc2ae10, 0x7bbc417e, 0x7bb5d026, 0x7baf5a09, 0x7ba8df28, 0x7ba25f82,
+  0x7b9bdb18, 0x7b9551ea,
+  0x7b8ec3f8, 0x7b883143, 0x7b8199ca, 0x7b7afd8f, 0x7b745c91, 0x7b6db6d0,
+  0x7b670c4d, 0x7b605d09,
+  0x7b59a902, 0x7b52f03a, 0x7b4c32b1, 0x7b457068, 0x7b3ea95d, 0x7b37dd92,
+  0x7b310d07, 0x7b2a37bc,
+  0x7b235db2, 0x7b1c7ee8, 0x7b159b5f, 0x7b0eb318, 0x7b07c612, 0x7b00d44d,
+  0x7af9ddcb, 0x7af2e28b,
+  0x7aebe28d, 0x7ae4ddd2, 0x7addd45b, 0x7ad6c626, 0x7acfb336, 0x7ac89b89,
+  0x7ac17f20, 0x7aba5dfc,
+  0x7ab3381d, 0x7aac0d82, 0x7aa4de2d, 0x7a9daa1d, 0x7a967153, 0x7a8f33d0,
+  0x7a87f192, 0x7a80aa9c,
+  0x7a795eec, 0x7a720e84, 0x7a6ab963, 0x7a635f8a, 0x7a5c00f9, 0x7a549db0,
+  0x7a4d35b0, 0x7a45c8f9,
+  0x7a3e578b, 0x7a36e166, 0x7a2f668c, 0x7a27e6fb, 0x7a2062b5, 0x7a18d9b9,
+  0x7a114c09, 0x7a09b9a4,
+  0x7a02228a, 0x79fa86bc, 0x79f2e63a, 0x79eb4105, 0x79e3971c, 0x79dbe880,
+  0x79d43532, 0x79cc7d31,
+  0x79c4c07e, 0x79bcff19, 0x79b53903, 0x79ad6e3c, 0x79a59ec3, 0x799dca9a,
+  0x7995f1c1, 0x798e1438,
+  0x798631ff, 0x797e4b16, 0x79765f7f, 0x796e6f39, 0x79667a44, 0x795e80a1,
+  0x79568250, 0x794e7f52,
+  0x794677a6, 0x793e6b4e, 0x79365a49, 0x792e4497, 0x79262a3a, 0x791e0b31,
+  0x7915e77c, 0x790dbf1d,
+  0x79059212, 0x78fd605d, 0x78f529fe, 0x78eceef6, 0x78e4af44, 0x78dc6ae8,
+  0x78d421e4, 0x78cbd437,
+  0x78c381e2, 0x78bb2ae5, 0x78b2cf41, 0x78aa6ef5, 0x78a20a03, 0x7899a06a,
+  0x7891322a, 0x7888bf45,
+  0x788047ba, 0x7877cb89, 0x786f4ab4, 0x7866c53a, 0x785e3b1c, 0x7855ac5a,
+  0x784d18f4, 0x784480ea,
+  0x783be43e, 0x783342ef, 0x782a9cfe, 0x7821f26b, 0x78194336, 0x78108f60,
+  0x7807d6e9, 0x77ff19d1,
+  0x77f65819, 0x77ed91c0, 0x77e4c6c9, 0x77dbf732, 0x77d322fc, 0x77ca4a27,
+  0x77c16cb4, 0x77b88aa3,
+  0x77afa3f5, 0x77a6b8a9, 0x779dc8c0, 0x7794d43b, 0x778bdb19, 0x7782dd5c,
+  0x7779db03, 0x7770d40f,
+  0x7767c880, 0x775eb857, 0x7755a394, 0x774c8a36, 0x77436c40, 0x773a49b0,
+  0x77312287, 0x7727f6c6,
+  0x771ec66e, 0x7715917d, 0x770c57f5, 0x770319d6, 0x76f9d721, 0x76f08fd5,
+  0x76e743f4, 0x76ddf37c,
+  0x76d49e70, 0x76cb44cf, 0x76c1e699, 0x76b883d0, 0x76af1c72, 0x76a5b082,
+  0x769c3ffe, 0x7692cae8,
+  0x7689513f, 0x767fd304, 0x76765038, 0x766cc8db, 0x76633ced, 0x7659ac6f,
+  0x76501760, 0x76467dc2,
+  0x763cdf94, 0x76333cd8, 0x7629958c, 0x761fe9b3, 0x7616394c, 0x760c8457,
+  0x7602cad5, 0x75f90cc7,
+  0x75ef4a2c, 0x75e58305, 0x75dbb753, 0x75d1e715, 0x75c8124d, 0x75be38fa,
+  0x75b45b1d, 0x75aa78b6,
+  0x75a091c6, 0x7596a64d, 0x758cb64c, 0x7582c1c2, 0x7578c8b0, 0x756ecb18,
+  0x7564c8f8, 0x755ac251,
+  0x7550b725, 0x7546a772, 0x753c933a, 0x75327a7d, 0x75285d3b, 0x751e3b75,
+  0x7514152b, 0x7509ea5d,
+  0x74ffbb0d, 0x74f58739, 0x74eb4ee3, 0x74e1120c, 0x74d6d0b2, 0x74cc8ad8,
+  0x74c2407d, 0x74b7f1a1,
+  0x74ad9e46, 0x74a3466b, 0x7498ea11, 0x748e8938, 0x748423e0, 0x7479ba0b,
+  0x746f4bb8, 0x7464d8e8,
+  0x745a619b, 0x744fe5d2, 0x7445658d, 0x743ae0cc, 0x74305790, 0x7425c9da,
+  0x741b37a9, 0x7410a0fe,
+  0x740605d9, 0x73fb663c, 0x73f0c226, 0x73e61997, 0x73db6c91, 0x73d0bb13,
+  0x73c6051f, 0x73bb4ab3,
+  0x73b08bd1, 0x73a5c87a, 0x739b00ad, 0x7390346b, 0x738563b5, 0x737a8e8a,
+  0x736fb4ec, 0x7364d6da,
+  0x7359f456, 0x734f0d5f, 0x734421f6, 0x7339321b, 0x732e3dcf, 0x73234512,
+  0x731847e5, 0x730d4648,
+  0x7302403c, 0x72f735c0, 0x72ec26d6, 0x72e1137d, 0x72d5fbb7, 0x72cadf83,
+  0x72bfbee3, 0x72b499d6,
+  0x72a9705c, 0x729e4277, 0x72931027, 0x7287d96c, 0x727c9e47, 0x72715eb8,
+  0x72661abf, 0x725ad25d,
+  0x724f8593, 0x72443460, 0x7238dec5, 0x722d84c4, 0x7222265b, 0x7216c38c,
+  0x720b5c57, 0x71fff0bc,
+  0x71f480bc, 0x71e90c57, 0x71dd938f, 0x71d21662, 0x71c694d2, 0x71bb0edf,
+  0x71af848a, 0x71a3f5d2,
+  0x719862b9, 0x718ccb3f, 0x71812f65, 0x71758f29, 0x7169ea8f, 0x715e4194,
+  0x7152943b, 0x7146e284,
+  0x713b2c6e, 0x712f71fb, 0x7123b32b, 0x7117effe, 0x710c2875, 0x71005c90,
+  0x70f48c50, 0x70e8b7b5,
+  0x70dcdec0, 0x70d10171, 0x70c51fc8, 0x70b939c7, 0x70ad4f6d, 0x70a160ba,
+  0x70956db1, 0x70897650,
+  0x707d7a98, 0x70717a8a, 0x70657626, 0x70596d6d, 0x704d6060, 0x70414efd,
+  0x70353947, 0x70291f3e,
+  0x701d00e1, 0x7010de32, 0x7004b731, 0x6ff88bde, 0x6fec5c3b, 0x6fe02846,
+  0x6fd3f001, 0x6fc7b36d,
+  0x6fbb728a, 0x6faf2d57, 0x6fa2e3d7, 0x6f969608, 0x6f8a43ed, 0x6f7ded84,
+  0x6f7192cf, 0x6f6533ce,
+  0x6f58d082, 0x6f4c68eb, 0x6f3ffd09, 0x6f338cde, 0x6f271868, 0x6f1a9faa,
+  0x6f0e22a3, 0x6f01a155,
+  0x6ef51bbe, 0x6ee891e1, 0x6edc03bc, 0x6ecf7152, 0x6ec2daa2, 0x6eb63fad,
+  0x6ea9a073, 0x6e9cfcf5,
+  0x6e905534, 0x6e83a92f, 0x6e76f8e7, 0x6e6a445d, 0x6e5d8b91, 0x6e50ce84,
+  0x6e440d37, 0x6e3747a9,
+  0x6e2a7ddb, 0x6e1dafce, 0x6e10dd82, 0x6e0406f8, 0x6df72c30, 0x6dea4d2b,
+  0x6ddd69e9, 0x6dd0826a,
+  0x6dc396b0, 0x6db6a6ba, 0x6da9b28a, 0x6d9cba1f, 0x6d8fbd7a, 0x6d82bc9d,
+  0x6d75b786, 0x6d68ae37,
+  0x6d5ba0b0, 0x6d4e8ef2, 0x6d4178fd, 0x6d345ed1, 0x6d274070, 0x6d1a1dda,
+  0x6d0cf70f, 0x6cffcc0f,
+  0x6cf29cdc, 0x6ce56975, 0x6cd831dc, 0x6ccaf610, 0x6cbdb613, 0x6cb071e4,
+  0x6ca32985, 0x6c95dcf6,
+  0x6c888c36, 0x6c7b3748, 0x6c6dde2b, 0x6c6080e0, 0x6c531f67, 0x6c45b9c1,
+  0x6c384fef, 0x6c2ae1f0,
+  0x6c1d6fc6, 0x6c0ff971, 0x6c027ef1, 0x6bf50047, 0x6be77d74, 0x6bd9f677,
+  0x6bcc6b53, 0x6bbedc06,
+  0x6bb14892, 0x6ba3b0f7, 0x6b961536, 0x6b88754f, 0x6b7ad142, 0x6b6d2911,
+  0x6b5f7cbc, 0x6b51cc42,
+  0x6b4417a6, 0x6b365ee7, 0x6b28a206, 0x6b1ae103, 0x6b0d1bdf, 0x6aff529a,
+  0x6af18536, 0x6ae3b3b2,
+  0x6ad5de0f, 0x6ac8044e, 0x6aba266e, 0x6aac4472, 0x6a9e5e58, 0x6a907423,
+  0x6a8285d1, 0x6a749365,
+  0x6a669cdd, 0x6a58a23c, 0x6a4aa381, 0x6a3ca0ad, 0x6a2e99c0, 0x6a208ebb,
+  0x6a127f9f, 0x6a046c6c,
+  0x69f65523, 0x69e839c4, 0x69da1a50, 0x69cbf6c7, 0x69bdcf29, 0x69afa378,
+  0x69a173b5, 0x69933fde,
+  0x698507f6, 0x6976cbfc, 0x69688bf1, 0x695a47d6, 0x694bffab, 0x693db371,
+  0x692f6328, 0x69210ed1,
+  0x6912b66c, 0x690459fb, 0x68f5f97d, 0x68e794f3, 0x68d92c5d, 0x68cabfbd,
+  0x68bc4f13, 0x68adda5f,
+  0x689f61a1, 0x6890e4dc, 0x6882640e, 0x6873df38, 0x6865565c, 0x6856c979,
+  0x68483891, 0x6839a3a4,
+  0x682b0ab1, 0x681c6dbb, 0x680dccc1, 0x67ff27c4, 0x67f07ec5, 0x67e1d1c4,
+  0x67d320c1, 0x67c46bbe,
+  0x67b5b2bb, 0x67a6f5b8, 0x679834b6, 0x67896fb6, 0x677aa6b8, 0x676bd9bd,
+  0x675d08c4, 0x674e33d0,
+  0x673f5ae0, 0x67307df5, 0x67219d10, 0x6712b831, 0x6703cf58, 0x66f4e287,
+  0x66e5f1be, 0x66d6fcfd,
+  0x66c80445, 0x66b90797, 0x66aa06f3, 0x669b0259, 0x668bf9cb, 0x667ced49,
+  0x666ddcd3, 0x665ec86b,
+  0x664fb010, 0x664093c3, 0x66317385, 0x66224f56, 0x66132738, 0x6603fb2a,
+  0x65f4cb2d, 0x65e59742,
+  0x65d65f69, 0x65c723a3, 0x65b7e3f1, 0x65a8a052, 0x659958c9, 0x658a0d54,
+  0x657abdf6, 0x656b6aae,
+  0x655c137d, 0x654cb863, 0x653d5962, 0x652df679, 0x651e8faa, 0x650f24f5,
+  0x64ffb65b, 0x64f043dc,
+  0x64e0cd78, 0x64d15331, 0x64c1d507, 0x64b252fa, 0x64a2cd0c, 0x6493433c,
+  0x6483b58c, 0x647423fb,
+  0x64648e8c, 0x6454f53d, 0x64455810, 0x6435b706, 0x6426121e, 0x6416695a,
+  0x6406bcba, 0x63f70c3f,
+  0x63e757ea, 0x63d79fba, 0x63c7e3b1, 0x63b823cf, 0x63a86015, 0x63989884,
+  0x6388cd1b, 0x6378fddc,
+  0x63692ac7, 0x635953dd, 0x6349791f, 0x63399a8d, 0x6329b827, 0x6319d1ef,
+  0x6309e7e4, 0x62f9fa09,
+  0x62ea085c, 0x62da12df, 0x62ca1992, 0x62ba1c77, 0x62aa1b8d, 0x629a16d5,
+  0x628a0e50, 0x627a01fe,
+  0x6269f1e1, 0x6259ddf8, 0x6249c645, 0x6239aac7, 0x62298b81, 0x62196871,
+  0x62094199, 0x61f916f9,
+  0x61e8e893, 0x61d8b666, 0x61c88074, 0x61b846bc, 0x61a80940, 0x6197c800,
+  0x618782fd, 0x61773a37,
+  0x6166edb0, 0x61569d67, 0x6146495d, 0x6135f193, 0x6125960a, 0x611536c2,
+  0x6104d3bc, 0x60f46cf9,
+  0x60e40278, 0x60d3943b, 0x60c32243, 0x60b2ac8f, 0x60a23322, 0x6091b5fa,
+  0x60813519, 0x6070b080,
+  0x6060282f, 0x604f9c27, 0x603f0c69, 0x602e78f4, 0x601de1ca, 0x600d46ec,
+  0x5ffca859, 0x5fec0613,
+  0x5fdb601b, 0x5fcab670, 0x5fba0914, 0x5fa95807, 0x5f98a34a, 0x5f87eade,
+  0x5f772ec2, 0x5f666ef9,
+  0x5f55ab82, 0x5f44e45e, 0x5f34198e, 0x5f234b12, 0x5f1278eb, 0x5f01a31a,
+  0x5ef0c99f, 0x5edfec7b,
+  0x5ecf0baf, 0x5ebe273b, 0x5ead3f1f, 0x5e9c535e, 0x5e8b63f7, 0x5e7a70ea,
+  0x5e697a39, 0x5e587fe5,
+  0x5e4781ed, 0x5e368053, 0x5e257b17, 0x5e147239, 0x5e0365bb, 0x5df2559e,
+  0x5de141e1, 0x5dd02a85,
+  0x5dbf0f8c, 0x5dadf0f5, 0x5d9ccec2, 0x5d8ba8f3, 0x5d7a7f88, 0x5d695283,
+  0x5d5821e4, 0x5d46edac,
+  0x5d35b5db, 0x5d247a72, 0x5d133b72, 0x5d01f8dc, 0x5cf0b2af, 0x5cdf68ed,
+  0x5cce1b97, 0x5cbccaac,
+  0x5cab762f, 0x5c9a1e1e, 0x5c88c27c, 0x5c776348, 0x5c660084, 0x5c549a30,
+  0x5c43304d, 0x5c31c2db,
+  0x5c2051db, 0x5c0edd4e, 0x5bfd6534, 0x5bebe98e, 0x5bda6a5d, 0x5bc8e7a2,
+  0x5bb7615d, 0x5ba5d78e,
+  0x5b944a37, 0x5b82b958, 0x5b7124f2, 0x5b5f8d06, 0x5b4df193, 0x5b3c529c,
+  0x5b2ab020, 0x5b190a20,
+  0x5b07609d, 0x5af5b398, 0x5ae40311, 0x5ad24f09, 0x5ac09781, 0x5aaedc78,
+  0x5a9d1df1, 0x5a8b5bec,
+  0x5a799669, 0x5a67cd69, 0x5a5600ec, 0x5a4430f5, 0x5a325d82, 0x5a208695,
+  0x5a0eac2e, 0x59fcce4f,
+  0x59eaecf8, 0x59d90829, 0x59c71fe3, 0x59b53427, 0x59a344f6, 0x59915250,
+  0x597f5c36, 0x596d62a9,
+  0x595b65aa, 0x59496538, 0x59376155, 0x59255a02, 0x59134f3e, 0x5901410c,
+  0x58ef2f6b, 0x58dd1a5d,
+  0x58cb01e1, 0x58b8e5f9, 0x58a6c6a5, 0x5894a3e7, 0x58827dbe, 0x5870542c,
+  0x585e2730, 0x584bf6cd,
+  0x5839c302, 0x58278bd1, 0x58155139, 0x5803133c, 0x57f0d1da, 0x57de8d15,
+  0x57cc44ec, 0x57b9f960,
+  0x57a7aa73, 0x57955825, 0x57830276, 0x5770a968, 0x575e4cfa, 0x574bed2f,
+  0x57398a05, 0x5727237f,
+  0x5714b99d, 0x57024c5f, 0x56efdbc7, 0x56dd67d4, 0x56caf088, 0x56b875e4,
+  0x56a5f7e7, 0x56937694,
+  0x5680f1ea, 0x566e69ea, 0x565bde95, 0x56494fec, 0x5636bdef, 0x5624289f,
+  0x56118ffe, 0x55fef40a,
+  0x55ec54c6, 0x55d9b232, 0x55c70c4f, 0x55b4631d, 0x55a1b69d, 0x558f06d0,
+  0x557c53b6, 0x55699d51,
+  0x5556e3a1, 0x554426a7, 0x55316663, 0x551ea2d6, 0x550bdc01, 0x54f911e5,
+  0x54e64482, 0x54d373d9,
+  0x54c09feb, 0x54adc8b8, 0x549aee42, 0x54881089, 0x54752f8d, 0x54624b50,
+  0x544f63d2, 0x543c7914,
+  0x54298b17, 0x541699db, 0x5403a561, 0x53f0adaa, 0x53ddb2b6, 0x53cab486,
+  0x53b7b31c, 0x53a4ae77,
+  0x5391a699, 0x537e9b82, 0x536b8d33, 0x53587bad, 0x534566f0, 0x53324efd,
+  0x531f33d5, 0x530c1579,
+  0x52f8f3e9, 0x52e5cf27, 0x52d2a732, 0x52bf7c0b, 0x52ac4db4, 0x52991c2d,
+  0x5285e777, 0x5272af92,
+  0x525f7480, 0x524c3640, 0x5238f4d4, 0x5225b03d, 0x5212687b, 0x51ff1d8f,
+  0x51ebcf7a, 0x51d87e3c,
+  0x51c529d7, 0x51b1d24a, 0x519e7797, 0x518b19bf, 0x5177b8c2, 0x516454a0,
+  0x5150ed5c, 0x513d82f4,
+  0x512a156b, 0x5116a4c1, 0x510330f7, 0x50efba0d, 0x50dc4005, 0x50c8c2de,
+  0x50b5429a, 0x50a1bf39,
+  0x508e38bd, 0x507aaf25, 0x50672273, 0x505392a8, 0x503fffc4, 0x502c69c8,
+  0x5018d0b4, 0x5005348a,
+  0x4ff1954b, 0x4fddf2f6, 0x4fca4d8d, 0x4fb6a510, 0x4fa2f981, 0x4f8f4ae0,
+  0x4f7b992d, 0x4f67e46a,
+  0x4f542c98, 0x4f4071b6, 0x4f2cb3c7, 0x4f18f2c9, 0x4f052ec0, 0x4ef167aa,
+  0x4edd9d89, 0x4ec9d05e,
+  0x4eb60029, 0x4ea22ceb, 0x4e8e56a5, 0x4e7a7d58, 0x4e66a105, 0x4e52c1ab,
+  0x4e3edf4d, 0x4e2af9ea,
+  0x4e171184, 0x4e03261b, 0x4def37b0, 0x4ddb4644, 0x4dc751d8, 0x4db35a6c,
+  0x4d9f6001, 0x4d8b6298,
+  0x4d776231, 0x4d635ece, 0x4d4f5870, 0x4d3b4f16, 0x4d2742c2, 0x4d133374,
+  0x4cff212e, 0x4ceb0bf0,
+  0x4cd6f3bb, 0x4cc2d88f, 0x4caeba6e, 0x4c9a9958, 0x4c86754e, 0x4c724e50,
+  0x4c5e2460, 0x4c49f77f,
+  0x4c35c7ac, 0x4c2194e9, 0x4c0d5f37, 0x4bf92697, 0x4be4eb08, 0x4bd0ac8d,
+  0x4bbc6b25, 0x4ba826d1,
+  0x4b93df93, 0x4b7f956b, 0x4b6b485a, 0x4b56f861, 0x4b42a580, 0x4b2e4fb8,
+  0x4b19f70a, 0x4b059b77,
+  0x4af13d00, 0x4adcdba5, 0x4ac87767, 0x4ab41046, 0x4a9fa645, 0x4a8b3963,
+  0x4a76c9a2, 0x4a625701,
+  0x4a4de182, 0x4a396926, 0x4a24edee, 0x4a106fda, 0x49fbeeea, 0x49e76b21,
+  0x49d2e47e, 0x49be5b02,
+  0x49a9ceaf, 0x49953f84, 0x4980ad84, 0x496c18ae, 0x49578103, 0x4942e684,
+  0x492e4933, 0x4919a90f,
+  0x4905061a, 0x48f06054, 0x48dbb7be, 0x48c70c59, 0x48b25e25, 0x489dad25,
+  0x4888f957, 0x487442be,
+  0x485f8959, 0x484acd2a, 0x48360e32, 0x48214c71, 0x480c87e8, 0x47f7c099,
+  0x47e2f682, 0x47ce29a7,
+  0x47b95a06, 0x47a487a2, 0x478fb27b, 0x477ada91, 0x4765ffe6, 0x4751227a,
+  0x473c424e, 0x47275f63,
+  0x471279ba, 0x46fd9154, 0x46e8a631, 0x46d3b852, 0x46bec7b8, 0x46a9d464,
+  0x4694de56, 0x467fe590,
+  0x466aea12, 0x4655ebdd, 0x4640eaf2, 0x462be751, 0x4616e0fc, 0x4601d7f3,
+  0x45eccc37, 0x45d7bdc9,
+  0x45c2acaa, 0x45ad98da, 0x4598825a, 0x4583692c, 0x456e4d4f, 0x45592ec6,
+  0x45440d90, 0x452ee9ae,
+  0x4519c321, 0x450499eb, 0x44ef6e0b, 0x44da3f83, 0x44c50e53, 0x44afda7d,
+  0x449aa400, 0x44856adf,
+  0x44702f19, 0x445af0b0, 0x4445afa4, 0x44306bf6, 0x441b25a8, 0x4405dcb9,
+  0x43f0912b, 0x43db42fe,
+  0x43c5f234, 0x43b09ecc, 0x439b48c9, 0x4385f02a, 0x437094f1, 0x435b371f,
+  0x4345d6b3, 0x433073b0,
+  0x431b0e15, 0x4305a5e5, 0x42f03b1e, 0x42dacdc3, 0x42c55dd4, 0x42afeb53,
+  0x429a763f, 0x4284fe99,
+  0x426f8463, 0x425a079e, 0x42448849, 0x422f0667, 0x421981f7, 0x4203fafb,
+  0x41ee7174, 0x41d8e561,
+  0x41c356c5, 0x41adc5a0, 0x419831f3, 0x41829bbe, 0x416d0302, 0x415767c1,
+  0x4141c9fb, 0x412c29b1,
+  0x411686e4, 0x4100e194, 0x40eb39c3, 0x40d58f71, 0x40bfe29f, 0x40aa334e,
+  0x4094817f, 0x407ecd32,
+  0x40691669, 0x40535d24, 0x403da165, 0x4027e32b, 0x40122278, 0x3ffc5f4d,
+  0x3fe699aa, 0x3fd0d191,
+  0x3fbb0702, 0x3fa539fd, 0x3f8f6a85, 0x3f799899, 0x3f63c43b, 0x3f4ded6b,
+  0x3f38142a, 0x3f22387a,
+  0x3f0c5a5a, 0x3ef679cc, 0x3ee096d1, 0x3ecab169, 0x3eb4c995, 0x3e9edf57,
+  0x3e88f2ae, 0x3e73039d,
+  0x3e5d1222, 0x3e471e41, 0x3e3127f9, 0x3e1b2f4a, 0x3e053437, 0x3def36c0,
+  0x3dd936e6, 0x3dc334a9,
+  0x3dad300b, 0x3d97290b, 0x3d811fac, 0x3d6b13ee, 0x3d5505d2, 0x3d3ef559,
+  0x3d28e282, 0x3d12cd51,
+  0x3cfcb5c4, 0x3ce69bde, 0x3cd07f9f, 0x3cba6107, 0x3ca44018, 0x3c8e1cd3,
+  0x3c77f737, 0x3c61cf48,
+  0x3c4ba504, 0x3c35786d, 0x3c1f4983, 0x3c091849, 0x3bf2e4be, 0x3bdcaee3,
+  0x3bc676b9, 0x3bb03c42,
+  0x3b99ff7d, 0x3b83c06c, 0x3b6d7f10, 0x3b573b69, 0x3b40f579, 0x3b2aad3f,
+  0x3b1462be, 0x3afe15f6,
+  0x3ae7c6e7, 0x3ad17593, 0x3abb21fb, 0x3aa4cc1e, 0x3a8e7400, 0x3a78199f,
+  0x3a61bcfd, 0x3a4b5e1b,
+  0x3a34fcf9, 0x3a1e9999, 0x3a0833fc, 0x39f1cc21, 0x39db620b, 0x39c4f5ba,
+  0x39ae872f, 0x3998166a,
+  0x3981a36d, 0x396b2e38, 0x3954b6cd, 0x393e3d2c, 0x3927c155, 0x3911434b,
+  0x38fac30e, 0x38e4409e,
+  0x38cdbbfc, 0x38b7352a, 0x38a0ac29, 0x388a20f8, 0x38739399, 0x385d040d,
+  0x38467255, 0x382fde72,
+  0x38194864, 0x3802b02c, 0x37ec15cb, 0x37d57943, 0x37beda93, 0x37a839be,
+  0x379196c3, 0x377af1a3,
+  0x37644a60, 0x374da0fa, 0x3736f573, 0x372047ca, 0x37099802, 0x36f2e61a,
+  0x36dc3214, 0x36c57bf0,
+  0x36aec3b0, 0x36980954, 0x36814cde, 0x366a8e4d, 0x3653cda3, 0x363d0ae2,
+  0x36264609, 0x360f7f19,
+  0x35f8b614, 0x35e1eafa, 0x35cb1dcc, 0x35b44e8c, 0x359d7d39, 0x3586a9d5,
+  0x356fd461, 0x3558fcde,
+  0x3542234c, 0x352b47ad, 0x35146a00, 0x34fd8a48, 0x34e6a885, 0x34cfc4b7,
+  0x34b8dee1, 0x34a1f702,
+  0x348b0d1c, 0x3474212f, 0x345d333c, 0x34464345, 0x342f5149, 0x34185d4b,
+  0x3401674a, 0x33ea6f48,
+  0x33d37546, 0x33bc7944, 0x33a57b44, 0x338e7b46, 0x3377794b, 0x33607554,
+  0x33496f62, 0x33326776,
+  0x331b5d91, 0x330451b3, 0x32ed43de, 0x32d63412, 0x32bf2250, 0x32a80e99,
+  0x3290f8ef, 0x3279e151,
+  0x3262c7c1, 0x324bac40, 0x32348ecf, 0x321d6f6e, 0x32064e1e, 0x31ef2ae1,
+  0x31d805b7, 0x31c0dea1,
+  0x31a9b5a0, 0x31928ab4, 0x317b5de0, 0x31642f23, 0x314cfe7f, 0x3135cbf4,
+  0x311e9783, 0x3107612e,
+  0x30f028f4, 0x30d8eed8, 0x30c1b2da, 0x30aa74fa, 0x3093353a, 0x307bf39b,
+  0x3064b01d, 0x304d6ac1,
+  0x30362389, 0x301eda75, 0x30078f86, 0x2ff042bd, 0x2fd8f41b, 0x2fc1a3a0,
+  0x2faa514f, 0x2f92fd26,
+  0x2f7ba729, 0x2f644f56, 0x2f4cf5b0, 0x2f359a37, 0x2f1e3ced, 0x2f06ddd1,
+  0x2eef7ce5, 0x2ed81a29,
+  0x2ec0b5a0, 0x2ea94f49, 0x2e91e725, 0x2e7a7d36, 0x2e63117c, 0x2e4ba3f8,
+  0x2e3434ac, 0x2e1cc397,
+  0x2e0550bb, 0x2deddc19, 0x2dd665b2, 0x2dbeed86, 0x2da77397, 0x2d8ff7e5,
+  0x2d787a72, 0x2d60fb3e,
+  0x2d497a4a, 0x2d31f797, 0x2d1a7325, 0x2d02ecf7, 0x2ceb650d, 0x2cd3db67,
+  0x2cbc5006, 0x2ca4c2ed,
+  0x2c8d341a, 0x2c75a390, 0x2c5e114f, 0x2c467d58, 0x2c2ee7ad, 0x2c17504d,
+  0x2bffb73a, 0x2be81c74,
+  0x2bd07ffe, 0x2bb8e1d7, 0x2ba14200, 0x2b89a07b, 0x2b71fd48, 0x2b5a5868,
+  0x2b42b1dd, 0x2b2b09a6,
+  0x2b135fc6, 0x2afbb43c, 0x2ae4070a, 0x2acc5831, 0x2ab4a7b1, 0x2a9cf58c,
+  0x2a8541c3, 0x2a6d8c55,
+  0x2a55d545, 0x2a3e1c93, 0x2a266240, 0x2a0ea64d, 0x29f6e8bb, 0x29df298b,
+  0x29c768be, 0x29afa654,
+  0x2997e24f, 0x29801caf, 0x29685576, 0x29508ca4, 0x2938c23a, 0x2920f63a,
+  0x290928a3, 0x28f15978,
+  0x28d988b8, 0x28c1b666, 0x28a9e281, 0x28920d0a, 0x287a3604, 0x28625d6d,
+  0x284a8349, 0x2832a796,
+  0x281aca57, 0x2802eb8c, 0x27eb0b36, 0x27d32956, 0x27bb45ed, 0x27a360fc,
+  0x278b7a84, 0x27739285,
+  0x275ba901, 0x2743bdf9, 0x272bd16d, 0x2713e35f, 0x26fbf3ce, 0x26e402bd,
+  0x26cc102d, 0x26b41c1d,
+  0x269c268f, 0x26842f84, 0x266c36fe, 0x26543cfb, 0x263c417f, 0x26244489,
+  0x260c461b, 0x25f44635,
+  0x25dc44d9, 0x25c44207, 0x25ac3dc0, 0x25943806, 0x257c30d8, 0x25642839,
+  0x254c1e28, 0x253412a8,
+  0x251c05b8, 0x2503f75a, 0x24ebe78f, 0x24d3d657, 0x24bbc3b4, 0x24a3afa6,
+  0x248b9a2f, 0x2473834f,
+  0x245b6b07, 0x24435158, 0x242b3644, 0x241319ca, 0x23fafbec, 0x23e2dcac,
+  0x23cabc09, 0x23b29a05,
+  0x239a76a0, 0x238251dd, 0x236a2bba, 0x2352043b, 0x2339db5e, 0x2321b126,
+  0x23098593, 0x22f158a7,
+  0x22d92a61, 0x22c0fac4, 0x22a8c9cf, 0x22909785, 0x227863e5, 0x22602ef1,
+  0x2247f8aa, 0x222fc111,
+  0x22178826, 0x21ff4dea, 0x21e71260, 0x21ced586, 0x21b6975f, 0x219e57eb,
+  0x2186172b, 0x216dd521,
+  0x215591cc, 0x213d4d2f, 0x21250749, 0x210cc01d, 0x20f477aa, 0x20dc2df2,
+  0x20c3e2f5, 0x20ab96b5,
+  0x20934933, 0x207afa6f, 0x2062aa6b, 0x204a5927, 0x203206a4, 0x2019b2e4,
+  0x20015de7, 0x1fe907ae,
+  0x1fd0b03a, 0x1fb8578b, 0x1f9ffda4, 0x1f87a285, 0x1f6f462f, 0x1f56e8a2,
+  0x1f3e89e0, 0x1f2629ea,
+  0x1f0dc8c0, 0x1ef56664, 0x1edd02d6, 0x1ec49e17, 0x1eac3829, 0x1e93d10c,
+  0x1e7b68c2, 0x1e62ff4a,
+  0x1e4a94a7, 0x1e3228d9, 0x1e19bbe0, 0x1e014dbf, 0x1de8de75, 0x1dd06e04,
+  0x1db7fc6d, 0x1d9f89b1,
+  0x1d8715d0, 0x1d6ea0cc, 0x1d562aa6, 0x1d3db35e, 0x1d253af5, 0x1d0cc16c,
+  0x1cf446c5, 0x1cdbcb00,
+  0x1cc34e1f, 0x1caad021, 0x1c925109, 0x1c79d0d6, 0x1c614f8b, 0x1c48cd27,
+  0x1c3049ac, 0x1c17c51b,
+  0x1bff3f75, 0x1be6b8ba, 0x1bce30ec, 0x1bb5a80c, 0x1b9d1e1a, 0x1b849317,
+  0x1b6c0705, 0x1b5379e5,
+  0x1b3aebb6, 0x1b225c7b, 0x1b09cc34, 0x1af13ae3, 0x1ad8a887, 0x1ac01522,
+  0x1aa780b6, 0x1a8eeb42,
+  0x1a7654c8, 0x1a5dbd49, 0x1a4524c6, 0x1a2c8b3f, 0x1a13f0b6, 0x19fb552c,
+  0x19e2b8a2, 0x19ca1b17,
+  0x19b17c8f, 0x1998dd09, 0x19803c86, 0x19679b07, 0x194ef88e, 0x1936551b,
+  0x191db0af, 0x19050b4b,
+  0x18ec64f0, 0x18d3bda0, 0x18bb155a, 0x18a26c20, 0x1889c1f3, 0x187116d4,
+  0x18586ac3, 0x183fbdc3,
+  0x18270fd3, 0x180e60f4, 0x17f5b129, 0x17dd0070, 0x17c44ecd, 0x17ab9c3e,
+  0x1792e8c6, 0x177a3466,
+  0x17617f1d, 0x1748c8ee, 0x173011d9, 0x171759df, 0x16fea102, 0x16e5e741,
+  0x16cd2c9f, 0x16b4711b,
+  0x169bb4b7, 0x1682f774, 0x166a3953, 0x16517a55, 0x1638ba7a, 0x161ff9c4,
+  0x16073834, 0x15ee75cb,
+  0x15d5b288, 0x15bcee6f, 0x15a4297f, 0x158b63b9, 0x15729d1f, 0x1559d5b1,
+  0x15410d70, 0x1528445d,
+  0x150f7a7a, 0x14f6afc7, 0x14dde445, 0x14c517f4, 0x14ac4ad7, 0x14937cee,
+  0x147aae3a, 0x1461debc,
+  0x14490e74, 0x14303d65, 0x14176b8e, 0x13fe98f1, 0x13e5c58e, 0x13ccf167,
+  0x13b41c7d, 0x139b46d0,
+  0x13827062, 0x13699933, 0x1350c144, 0x1337e897, 0x131f0f2c, 0x13063505,
+  0x12ed5a21, 0x12d47e83,
+  0x12bba22b, 0x12a2c51b, 0x1289e752, 0x127108d2, 0x1258299c, 0x123f49b2,
+  0x12266913, 0x120d87c1,
+  0x11f4a5bd, 0x11dbc307, 0x11c2dfa2, 0x11a9fb8d, 0x119116c9, 0x11783159,
+  0x115f4b3c, 0x11466473,
+  0x112d7d00, 0x111494e4, 0x10fbac1e, 0x10e2c2b2, 0x10c9d89e, 0x10b0ede5,
+  0x10980287, 0x107f1686,
+  0x106629e1, 0x104d3c9b, 0x10344eb4, 0x101b602d, 0x10027107, 0xfe98143,
+  0xfd090e1, 0xfb79fe4,
+  0xf9eae4c, 0xf85bc19, 0xf6cc94e, 0xf53d5ea, 0xf3ae1ee, 0xf21ed5d, 0xf08f836,
+  0xef0027b,
+  0xed70c2c, 0xebe154b, 0xea51dd8, 0xe8c25d5, 0xe732d42, 0xe5a3421, 0xe413a72,
+  0xe284036,
+  0xe0f456f, 0xdf64a1c, 0xddd4e40, 0xdc451dc, 0xdab54ef, 0xd92577b, 0xd795982,
+  0xd605b03,
+  0xd475c00, 0xd2e5c7b, 0xd155c73, 0xcfc5bea, 0xce35ae1, 0xcca5959, 0xcb15752,
+  0xc9854cf,
+  0xc7f51cf, 0xc664e53, 0xc4d4a5d, 0xc3445ee, 0xc1b4107, 0xc023ba7, 0xbe935d2,
+  0xbd02f87,
+  0xbb728c7, 0xb9e2193, 0xb8519ed, 0xb6c11d5, 0xb53094d, 0xb3a0055, 0xb20f6ee,
+  0xb07ed19,
+  0xaeee2d7, 0xad5d829, 0xabccd11, 0xaa3c18e, 0xa8ab5a2, 0xa71a94f, 0xa589c94,
+  0xa3f8f73,
+  0xa2681ed, 0xa0d7403, 0x9f465b5, 0x9db5706, 0x9c247f5, 0x9a93884, 0x99028b3,
+  0x9771884,
+  0x95e07f8, 0x944f70f, 0x92be5ca, 0x912d42c, 0x8f9c233, 0x8e0afe2, 0x8c79d3a,
+  0x8ae8a3a,
+  0x89576e5, 0x87c633c, 0x8634f3e, 0x84a3aee, 0x831264c, 0x8181159, 0x7fefc16,
+  0x7e5e685,
+  0x7ccd0a5, 0x7b3ba78, 0x79aa400, 0x7818d3c, 0x768762e, 0x74f5ed7, 0x7364738,
+  0x71d2f52,
+  0x7041726, 0x6eafeb4, 0x6d1e5fe, 0x6b8cd05, 0x69fb3c9, 0x6869a4c, 0x66d808f,
+  0x6546692,
+  0x63b4c57, 0x62231de, 0x6091729, 0x5effc38, 0x5d6e10c, 0x5bdc5a7, 0x5a4aa09,
+  0x58b8e34,
+  0x5727228, 0x55955e6, 0x540396f, 0x5271cc4, 0x50dffe7, 0x4f4e2d8, 0x4dbc597,
+  0x4c2a827,
+  0x4a98a88, 0x4906cbb, 0x4774ec1, 0x45e309a, 0x4451249, 0x42bf3cd, 0x412d528,
+  0x3f9b65b,
+  0x3e09767, 0x3c7784d, 0x3ae590d, 0x39539a9, 0x37c1a22, 0x362fa78, 0x349daac,
+  0x330bac1,
+  0x3179ab5, 0x2fe7a8c, 0x2e55a44, 0x2cc39e1, 0x2b31961, 0x299f8c7, 0x280d813,
+  0x267b747,
+  0x24e9662, 0x2357567, 0x21c5457, 0x2033331, 0x1ea11f7, 0x1d0f0ab, 0x1b7cf4d,
+  0x19eaddd,
+  0x1858c5e, 0x16c6ad0, 0x1534934, 0x13a278a, 0x12105d5, 0x107e414, 0xeec249,
+  0xd5a075,
+  0xbc7e99, 0xa35cb5, 0x8a3acb, 0x7118dc, 0x57f6e9, 0x3ed4f2, 0x25b2f8,
+  0xc90fe,
+
+};
+
+/**   
+ * @brief  Initialization function for the Q31 DCT4/IDCT4.  
+ * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.  
+ * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure  
+ * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure  
+ * @param[in]     N          length of the DCT4.  
+ * @param[in]     Nby2       half of the length of the DCT4.  
+ * @param[in]     normalize  normalizing factor.  
+ * @return		  arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.  
+ * \par Normalizing factor:   
+ * The normalizing factor is sqrt(2/N), which depends on the size of transform N.   
+ * Normalizing factors in 1.31 format are mentioned in the table below for different DCT sizes:   
+ * \image html dct4NormalizingQ31Table.gif   
+ */
+
+arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /* Initializing the pointer array with the weight table base addresses of different lengths */
+  q31_t *twiddlePtr[3] = { (q31_t *) WeightsQ31_128, (q31_t *) WeightsQ31_512,
+    (q31_t *) WeightsQ31_2048
+  };
+
+  /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+  q31_t *pCosFactor[3] =
+    { (q31_t *) cos_factorsQ31_128, (q31_t *) cos_factorsQ31_512,
+    (q31_t *) cos_factorsQ31_2048
+  };
+
+  /* Initialize the DCT4 length */
+  S->N = N;
+
+  /* Initialize the half of DCT4 length */
+  S->Nby2 = Nby2;
+
+  /* Initialize the DCT4 Normalizing factor */
+  S->normalize = normalize;
+
+  /* Initialize Real FFT Instance */
+  S->pRfft = S_RFFT;
+
+  /* Initialize Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  switch (N)
+  {
+    /* Initialize the table modifier values */
+  case 2048u:
+    S->pTwiddle = twiddlePtr[2];
+    S->pCosFactor = pCosFactor[2];
+    break;
+  case 512u:
+    S->pTwiddle = twiddlePtr[1];
+    S->pCosFactor = pCosFactor[1];
+    break;
+  case 128u:
+    S->pTwiddle = twiddlePtr[0];
+    S->pCosFactor = pCosFactor[0];
+    break;
+  default:
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+
+  /* Initialize the RFFT/RIFFT Function */
+  arm_rfft_init_q31(S->pRfft, S->pCfft, S->N, 0, 1);
+
+  /* return the status of DCT4 Init function */
+  return (status);
+}
+
+/**   
+   * @} end of DCT4_IDCT4 group   
+   */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c
new file mode 100644
index 000000000..75199b452
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c
@@ -0,0 +1,383 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_dct4_q15.c   
+*   
+* Description:	Processing function of DCT4 & IDCT4 Q15.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @addtogroup DCT4_IDCT4   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q15 DCT4/IDCT4.  
+ * @param[in]       *S             points to an instance of the Q15 DCT4 structure.  
+ * @param[in]       *pState        points to state buffer.  
+ * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.  
+ * @return none.  
+ *    
+ * \par Input an output formats:   
+ * Internally inputs are downscaled in the RFFT process function to avoid overflows.   
+ * Number of bits downscaled, depends on the size of the transform.   
+ * The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:    
+ *   
+ * \image html dct4FormatsQ15Table.gif   
+ */
+
+void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer)
+{
+  uint32_t i;                                    /* Loop counter */
+  q15_t *weights = S->pTwiddle;                  /* Pointer to the Weights table */
+  q15_t *cosFact = S->pCosFactor;                /* Pointer to the cos factors table */
+  q15_t *pS1, *pS2, *pbuff;                      /* Temporary pointers for input buffer and pState buffer */
+  q15_t in;                                      /* Temporary variable */
+
+
+  /* DCT4 computation involves DCT2 (which is calculated using RFFT)   
+   * along with some pre-processing and post-processing.   
+   * Computational procedure is explained as follows:   
+   * (a) Pre-processing involves multiplying input with cos factor,   
+   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))   
+   *              where,   
+   *                 r(n) -- output of preprocessing   
+   *                 u(n) -- input to preprocessing(actual Source buffer)   
+   * (b) Calculation of DCT2 using FFT is divided into three steps:   
+   *                  Step1: Re-ordering of even and odd elements of input.   
+   *                  Step2: Calculating FFT of the re-ordered input.   
+   *                  Step3: Taking the real part of the product of FFT output and weights.   
+   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:   
+   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *                        where,   
+   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output   
+   * (d) Multiplying the output with the normalizing factor sqrt(2/N).   
+   */
+
+        /*-------- Pre-processing ------------*/
+  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+  arm_mult_q15(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+  arm_shift_q15(pInlineBuffer, 1, pInlineBuffer, S->N);
+
+  /* ----------------------------------------------------------------   
+   * Step1: Re-ordering of even and odd elements as   
+   *             pState[i] =  pInlineBuffer[2*i] and   
+   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2   
+   ---------------------------------------------------------------------*/
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+  pS2 = pState + (S->N - 1u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+  i = (uint32_t) S->Nby2 >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = (uint32_t) S->N >> 2u;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.   
+   * Compute 4 outputs at a time */
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------   
+   *     Step2: Calculate RFFT for N-point input   
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_q15(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------   
+  *  Step3: Multiply the FFT output with the weights.   
+  *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_q15(pState, weights, pState, S->N);
+
+  /* The output of complex multiplication is in 3.13 format.   
+   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */
+  arm_shift_q15(pState, 2, pState, S->N * 2);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,   
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+  i = ((uint32_t) S->N - 1u) >> 2u;
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ >> 1u;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  i = ((uint32_t) S->N - 1u) % 0x4u;
+
+  while(i > 0u)
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+   /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = (uint32_t) S->N >> 2u;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initializing the loop counter to N/2 */
+  i = (uint32_t) S->Nby2;
+
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter */
+  i = (uint32_t) S->N;
+
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------   
+   *     Step2: Calculate RFFT for N-point input   
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_q15(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------   
+  *  Step3: Multiply the FFT output with the weights.   
+  *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_q15(pState, weights, pState, S->N);
+
+  /* The output of complex multiplication is in 3.13 format.   
+   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */
+  arm_shift_q15(pState, 2, pState, S->N * 2);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,   
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* Initializing the loop counter */
+  i = ((uint32_t) S->N - 1u);
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ >> 1u;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+   /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter */
+  i = (uint32_t) S->N;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+   * @} end of DCT4_IDCT4 group   
+   */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c
new file mode 100644
index 000000000..1f2c8ce43
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c
@@ -0,0 +1,384 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_dct4_q31.c   
+*   
+* Description:	Processing function of DCT4 & IDCT4 Q31.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @addtogroup DCT4_IDCT4   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q31 DCT4/IDCT4.  
+ * @param[in]       *S             points to an instance of the Q31 DCT4 structure.  
+ * @param[in]       *pState        points to state buffer.  
+ * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.  
+ * @return none.  
+ * \par Input an output formats:   
+ * Input samples need to be downscaled by 1 bit to avoid saturations in the Q31 DCT process,   
+ * as the conversion from DCT2 to DCT4 involves one subtraction.   
+ * Internally inputs are downscaled in the RFFT process function to avoid overflows.   
+ * Number of bits downscaled, depends on the size of the transform.   
+ * The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:    
+ *   
+ * \image html dct4FormatsQ31Table.gif   
+ */
+
+void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer)
+{
+  uint16_t i;                                    /* Loop counter */
+  q31_t *weights = S->pTwiddle;                  /* Pointer to the Weights table */
+  q31_t *cosFact = S->pCosFactor;                /* Pointer to the cos factors table */
+  q31_t *pS1, *pS2, *pbuff;                      /* Temporary pointers for input buffer and pState buffer */
+  q31_t in;                                      /* Temporary variable */
+
+
+  /* DCT4 computation involves DCT2 (which is calculated using RFFT)   
+   * along with some pre-processing and post-processing.   
+   * Computational procedure is explained as follows:   
+   * (a) Pre-processing involves multiplying input with cos factor,   
+   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))   
+   *              where,   
+   *                 r(n) -- output of preprocessing   
+   *                 u(n) -- input to preprocessing(actual Source buffer)   
+   * (b) Calculation of DCT2 using FFT is divided into three steps:   
+   *                  Step1: Re-ordering of even and odd elements of input.   
+   *                  Step2: Calculating FFT of the re-ordered input.   
+   *                  Step3: Taking the real part of the product of FFT output and weights.   
+   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:   
+   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *                        where,   
+   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output   
+   * (d) Multiplying the output with the normalizing factor sqrt(2/N).   
+   */
+
+        /*-------- Pre-processing ------------*/
+  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+  arm_mult_q31(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+  arm_shift_q31(pInlineBuffer, 1, pInlineBuffer, S->N);
+
+  /* ----------------------------------------------------------------   
+   * Step1: Re-ordering of even and odd elements as   
+   *             pState[i] =  pInlineBuffer[2*i] and   
+   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2   
+   ---------------------------------------------------------------------*/
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+  pS2 = pState + (S->N - 1u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+  i = S->Nby2 >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = S->N >> 2u;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.   
+   * Compute 4 outputs at a time */
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------   
+   *     Step2: Calculate RFFT for N-point input   
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_q31(S->pRfft, pInlineBuffer, pState);
+
+  /*----------------------------------------------------------------------   
+   *  Step3: Multiply the FFT output with the weights.   
+   *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_q31(pState, weights, pState, S->N);
+
+  /* The output of complex multiplication is in 3.29 format.   
+   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */
+  arm_shift_q31(pState, 2, pState, S->N * 2);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,   
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+  i = (S->N - 1u) >> 2u;
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ >> 1u;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  i = (S->N - 1u) % 0x4u;
+
+  while(i > 0u)
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = S->N >> 2u;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initializing the loop counter to N/2 */
+  i = S->Nby2;
+
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter */
+  i = S->N;
+
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------   
+   *     Step2: Calculate RFFT for N-point input   
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_q31(S->pRfft, pInlineBuffer, pState);
+
+  /*----------------------------------------------------------------------   
+   *  Step3: Multiply the FFT output with the weights.   
+   *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_q31(pState, weights, pState, S->N);
+
+  /* The output of complex multiplication is in 3.29 format.   
+   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */
+  arm_shift_q31(pState, 2, pState, S->N * 2);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,   
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ >> 1u;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* Initializing the loop counter */
+  i = (S->N - 1u);
+
+  while(i > 0u)
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter */
+  i = S->N;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+   * @} end of DCT4_IDCT4 group   
+   */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c
new file mode 100644
index 000000000..c3c2f7697
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c
@@ -0,0 +1,383 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_rfft_f32.c   
+*   
+* Description:	RFFT & RIFFT Floating point process function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @defgroup RFFT_RIFFT Real FFT Functions   
+ *   
+ * \par   
+ * Complex FFT/IFFT typically assumes complex input and output. However many applications use real valued data in time domain.    
+ * Real FFT/IFFT efficiently process real valued sequences with the advantage of requirement of low memory and with less complexity.   
+ *   
+ * \par   
+ * This set of functions implements Real Fast Fourier Transforms(RFFT) and Real Inverse Fast Fourier Transform(RIFFT)   
+ * for Q15, Q31, and floating-point data types.     
+ *   
+ *   
+ * \par Algorithm:   
+ *   
+ * Real Fast Fourier Transform:   
+ * \par   
+ * Real FFT of N-point is calculated using CFFT of N/2-point and Split RFFT process as shown below figure.   
+ * \par   
+ * \image html RFFT.gif "Real Fast Fourier Transform"   
+ * \par   
+ * The RFFT functions operate on blocks of input and output data and each call to the function processes   
+ * fftLenR samples through the transform.  pSrc  points to input array containing fftLenR values.   
+ * pDst  points to output array containing 2*fftLenR values. \n  
+ * Input for real FFT is in the order of    
+ * 
{real[0], real[1], real[2], real[3], ..}
   
+ * Output for real FFT is complex and are in the order of   
+ * 
{real(0), imag(0), real(1), imag(1), ...}
    
+ *   
+ * Real Inverse Fast Fourier Transform:   
+ * \par   
+ * Real IFFT of N-point is calculated using Split RIFFT process and CFFT of N/2-point as shown below figure.   
+ * \par   
+ * \image html RIFFT.gif "Real Inverse Fast Fourier Transform"   
+ * \par   
+ * The RIFFT functions operate on blocks of input and output data and each call to the function processes   
+ * 2*fftLenR samples through the transform.  pSrc  points to input array containing 2*fftLenR values.   
+ * pDst  points to output array containing fftLenR values. \n   
+ * Input for real IFFT is complex and are in the order of  
+ * 
{real(0), imag(0), real(1), imag(1), ...}
  
+ *  Output for real IFFT is real and in the order of    
+ * 
{real[0], real[1], real[2], real[3], ..}
  
+ *   
+ * \par Lengths supported by the transform:  
+ * \par   
+ * Real FFT/IFFT supports the lengths [128, 512, 2048], as it internally uses CFFT/CIFFT.   
+ *   
+ * \par Instance Structure   
+ * A separate instance structure must be defined for each Instance but the twiddle factors can be reused.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Initializes twiddle factor tables.  
+ * - Initializes CFFT data structure fields.    
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Manually initialize the instance structure as follows:   
+ * 
   
+ *arm_rfft_instance_f32 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};   
+ *arm_rfft_instance_q31 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};   
+ *arm_rfft_instance_q15 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};   
+ * 
   
+ * where fftLenReal length of RFFT/RIFFT; fftLenBy2 length of CFFT/CIFFT.    
+ * ifftFlagR Flag for selection of RFFT or RIFFT(Set ifftFlagR to calculate RIFFT otherwise calculates RFFT);   
+ * bitReverseFlagR Flag for selection of output order(Set bitReverseFlagR to output in normal order otherwise output in bit reversed order);    
+ * twidCoefRModifier modifier for twiddle factor table which supports 128, 512, 2048 RFFT lengths with same table;   
+ * pTwiddleARealpoints to A array of twiddle coefficients; pTwiddleBRealpoints to B array of twiddle coefficients;   
+ * pCfft points to the CFFT Instance structure. The CFFT structure also needs to be initialized, refer to arm_cfft_radix4_f32() for details regarding   
+ * static initialization of cfft structure.   
+ *   
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the RFFT/RIFFT function.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+/*--------------------------------------------------------------------   
+ *		Internal functions prototypes   
+ *--------------------------------------------------------------------*/
+
+void arm_split_rfft_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pATable,
+  float32_t * pBTable,
+  float32_t * pDst,
+  uint32_t modifier);
+void arm_split_rifft_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pATable,
+  float32_t * pBTable,
+  float32_t * pDst,
+  uint32_t modifier);
+
+/**   
+ * @addtogroup RFFT_RIFFT   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the floating-point RFFT/RIFFT.  
+ * @param[in]  *S    points to an instance of the floating-point RFFT/RIFFT structure.  
+ * @param[in]  *pSrc points to the input buffer.  
+ * @param[out] *pDst points to the output buffer.  
+ * @return none.  
+ */
+
+void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst)
+{
+  const arm_cfft_radix4_instance_f32 *S_CFFT = S->pCfft;
+
+
+  /* Calculation of Real IFFT of input */
+  if(S->ifftFlagR == 1u)
+  {
+    /*  Real IFFT core process */
+    arm_split_rifft_f32(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                        S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+
+
+    /* Complex radix-4 IFFT process */
+    arm_radix4_butterfly_inverse_f32(pDst, S_CFFT->fftLen,
+                                     S_CFFT->pTwiddle,
+                                     S_CFFT->twidCoefModifier,
+                                     S_CFFT->onebyfftLen);
+
+    /* Bit reversal process */
+    if(S->bitReverseFlagR == 1u)
+    {
+      arm_bitreversal_f32(pDst, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+  }
+  else
+  {
+
+    /* Calculation of RFFT of input */
+
+    /* Complex radix-4 FFT process */
+    arm_radix4_butterfly_f32(pSrc, S_CFFT->fftLen,
+                             S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
+
+    /* Bit reversal process */
+    if(S->bitReverseFlagR == 1u)
+    {
+      arm_bitreversal_f32(pSrc, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+
+
+    /*  Real FFT core process */
+    arm_split_rfft_f32(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                       S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+  }
+
+}
+
+/**   
+   * @} end of RFFT_RIFFT group   
+   */
+
+/**   
+ * @brief  Core Real FFT process   
+ * @param[in]   *pSrc 				points to the input buffer.   
+ * @param[in]   fftLen  			length of FFT.   
+ * @param[in]   *pATable 			points to the twiddle Coef A buffer.   
+ * @param[in]   *pBTable 			points to the twiddle Coef B buffer.   
+ * @param[out]  *pDst 				points to the output buffer.   
+ * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.   
+ */
+
+void arm_split_rfft_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pATable,
+  float32_t * pBTable,
+  float32_t * pDst,
+  uint32_t modifier)
+{
+  uint32_t i;                                    /* Loop Counter */
+  float32_t outR, outI;                          /* Temporary variables for output */
+  float32_t *pCoefA, *pCoefB;                    /* Temporary pointers for twiddle factors */
+  float32_t CoefA1, CoefA2, CoefB1;              /* Temporary variables for twiddle coefficients */
+  float32_t *pDst1 = &pDst[2], *pDst2 = &pDst[(4u * fftLen) - 1u];      /* temp pointers for output buffer */
+  float32_t *pSrc1 = &pSrc[2], *pSrc2 = &pSrc[(2u * fftLen) - 1u];      /* temp pointers for input buffer */
+
+
+  pSrc[2u * fftLen] = pSrc[0];
+  pSrc[(2u * fftLen) + 1u] = pSrc[1];
+
+  /* Init coefficient pointers */
+  pCoefA = &pATable[modifier * 2u];
+  pCoefB = &pBTable[modifier * 2u];
+
+  i = fftLen - 1u;
+
+  while(i > 0u)
+  {
+    /*   
+       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]   
+       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +   
+       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);   
+     */
+
+    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+    /* read pATable[2 * i] */
+    CoefA1 = *pCoefA++;
+    /* pATable[2 * i + 1] */
+    CoefA2 = *pCoefA;
+
+    /* pSrc[2 * i] * pATable[2 * i] */
+    outR = *pSrc1 * CoefA1;
+    /* pSrc[2 * i] * CoefA2 */
+    outI = *pSrc1++ * CoefA2;
+
+    /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */
+    outR -= (*pSrc1 + *pSrc2) * CoefA2;
+    /* pSrc[2 * i + 1] * CoefA1 */
+    outI += *pSrc1++ * CoefA1;
+
+    CoefB1 = *pCoefB;
+
+    /* pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */
+    outI -= *pSrc2-- * CoefB1;
+    /* pSrc[2 * fftLen - 2 * i] * CoefA2 */
+    outI -= *pSrc2 * CoefA2;
+
+    /* pSrc[2 * fftLen - 2 * i] * CoefB1 */
+    outR += *pSrc2-- * CoefB1;
+
+    /* write output */
+    *pDst1++ = outR;
+    *pDst1++ = outI;
+
+    /* write complex conjugate output */
+    *pDst2-- = -outI;
+    *pDst2-- = outR;
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (modifier * 2u);
+    pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+    i--;
+
+  }
+
+  pDst[2u * fftLen] = pSrc[0] - pSrc[1];
+  pDst[(2u * fftLen) + 1u] = 0.0f;
+
+  pDst[0] = pSrc[0] + pSrc[1];
+  pDst[1] = 0.0f;
+
+}
+
+
+/**   
+ * @brief  Core Real IFFT process   
+ * @param[in]   *pSrc 				points to the input buffer.   
+ * @param[in]   fftLen  			length of FFT.  
+ * @param[in]   *pATable 			points to the twiddle Coef A buffer.  
+ * @param[in]   *pBTable 			points to the twiddle Coef B buffer.  
+ * @param[out]  *pDst 				points to the output buffer.  
+ * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+ * @return none.   
+ */
+
+void arm_split_rifft_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pATable,
+  float32_t * pBTable,
+  float32_t * pDst,
+  uint32_t modifier)
+{
+  float32_t outR, outI;                          /* Temporary variables for output */
+  float32_t *pCoefA, *pCoefB;                    /* Temporary pointers for twiddle factors */
+  float32_t CoefA1, CoefA2, CoefB1;              /* Temporary variables for twiddle coefficients */
+  float32_t *pSrc1 = &pSrc[0], *pSrc2 = &pSrc[(2u * fftLen) + 1u];
+
+  pCoefA = &pATable[0];
+  pCoefB = &pBTable[0];
+
+  while(fftLen > 0u)
+  {
+    /*   
+       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);   
+
+       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -   
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);   
+
+     */
+
+    CoefA1 = *pCoefA++;
+    CoefA2 = *pCoefA;
+
+    /* outR = (pSrc[2 * i] * CoefA1 */
+    outR = *pSrc1 * CoefA1;
+
+    /* - pSrc[2 * i] * CoefA2 */
+    outI = -(*pSrc1++) * CoefA2;
+
+    /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */
+    outR += (*pSrc1 + *pSrc2) * CoefA2;
+
+    /* pSrc[2 * i + 1] * CoefA1 */
+    outI += (*pSrc1++) * CoefA1;
+
+    CoefB1 = *pCoefB;
+
+    /* - pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */
+    outI -= *pSrc2-- * CoefB1;
+
+    /* pSrc[2 * fftLen - 2 * i] * CoefB1 */
+    outR += *pSrc2 * CoefB1;
+
+    /* pSrc[2 * fftLen - 2 * i] * CoefA2 */
+    outI += *pSrc2-- * CoefA2;
+
+    /* write output */
+    *pDst++ = outR;
+    *pDst++ = outI;
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (modifier * 2u);
+    pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+    /* Decrement loop count */
+    fftLen--;
+  }
+
+}
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c
new file mode 100644
index 000000000..de0a47abc
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c
@@ -0,0 +1,1707 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_rfft_init_f32.c   
+*   
+* Description:	RFFT & RIFFT Floating point initialisation function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup RFFT_RIFFT   
+ * @{   
+ */
+
+/**   
+* \par   
+* Generation of realCoefA array:   
+* \par   
+* 	n = 1024   
+* 
for (i = 0; i < n; i++)   
+*  {   
+*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));   
+*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+*  } 
   
+*/
+
+
+
+static const float32_t realCoefA[2048] = {
+  0.500000000000000000f, -0.500000000000000000f, 0.498466014862060550f,
+  -0.499997645616531370f, 0.496932059526443480f, -0.499990582466125490f,
+  0.495398133993148800f, -0.499978810548782350f,
+  0.493864238262176510f, -0.499962359666824340f, 0.492330402135849000f,
+  -0.499941170215606690f, 0.490796625614166260f, -0.499915301799774170f,
+  0.489262968301773070f, -0.499884694814682010f,
+  0.487729400396347050f, -0.499849408864974980f, 0.486195921897888180f,
+  -0.499809414148330690f, 0.484662592411041260f, -0.499764710664749150f,
+  0.483129411935806270f, -0.499715298414230350f,
+  0.481596380472183230f, -0.499661177396774290f, 0.480063527822494510f,
+  -0.499602377414703370f, 0.478530883789062500f, -0.499538868665695190f,
+  0.476998418569564820f, -0.499470651149749760f,
+  0.475466161966323850f, -0.499397724866867070f, 0.473934143781661990f,
+  -0.499320119619369510f, 0.472402364015579220f, -0.499237775802612300f,
+  0.470870882272720340f, -0.499150782823562620f,
+  0.469339638948440550f, -0.499059051275253300f, 0.467808693647384640f,
+  -0.498962640762329100f, 0.466278046369552610f, -0.498861521482467650f,
+  0.464747726917266850f, -0.498755723237991330f,
+  0.463217705488204960f, -0.498645216226577760f, 0.461688071489334110f,
+  -0.498530030250549320f, 0.460158795118331910f, -0.498410135507583620f,
+  0.458629876375198360f, -0.498285561800003050f,
+  0.457101345062255860f, -0.498156309127807620f, 0.455573230981826780f,
+  -0.498022347688674930f, 0.454045534133911130f, -0.497883707284927370f,
+  0.452518254518508910f, -0.497740387916564940f,
+  0.450991421937942500f, -0.497592359781265260f, 0.449465066194534300f,
+  -0.497439652681350710f, 0.447939187288284300f, -0.497282296419143680f,
+  0.446413785219192500f, -0.497120231389999390f,
+  0.444888889789581300f, -0.496953487396240230f, 0.443364530801773070f,
+  -0.496782064437866210f, 0.441840678453445430f, -0.496605962514877320f,
+  0.440317392349243160f, -0.496425211429595950f,
+  0.438794672489166260f, -0.496239781379699710f, 0.437272518873214720f,
+  -0.496049642562866210f, 0.435750931501388550f, -0.495854884386062620f,
+  0.434229999780654910f, -0.495655417442321780f,
+  0.432709634304046630f, -0.495451331138610840f, 0.431189924478530880f,
+  -0.495242536067962650f, 0.429670870304107670f, -0.495029091835021970f,
+  0.428152471780776980f, -0.494810998439788820f,
+  0.426634758710861210f, -0.494588255882263180f, 0.425117731094360350f,
+  -0.494360834360122680f, 0.423601418733596800f, -0.494128793478012080f,
+  0.422085791826248170f, -0.493892073631286620f,
+  0.420570939779281620f, -0.493650704622268680f, 0.419056802988052370f,
+  -0.493404686450958250f, 0.417543441057205200f, -0.493154048919677730f,
+  0.416030853986740110f, -0.492898762226104740f,
+  0.414519041776657100f, -0.492638826370239260f, 0.413008064031600950f,
+  -0.492374241352081300f, 0.411497890949249270f, -0.492105036973953250f,
+  0.409988552331924440f, -0.491831213235855100f,
+  0.408480048179626460f, -0.491552740335464480f, 0.406972438097000120f,
+  -0.491269648075103760f, 0.405465662479400630f, -0.490981936454772950f,
+  0.403959810733795170f, -0.490689605474472050f,
+  0.402454853057861330f, -0.490392625331878660f, 0.400950789451599120f,
+  -0.490091055631637570f, 0.399447679519653320f, -0.489784896373748780f,
+  0.397945523262023930f, -0.489474087953567500f,
+  0.396444320678710940f, -0.489158689975738530f, 0.394944071769714360f,
+  -0.488838672637939450f, 0.393444836139678960f, -0.488514065742492680f,
+  0.391946613788604740f, -0.488184869289398190f,
+  0.390449374914169310f, -0.487851053476333620f, 0.388953179121017460f,
+  -0.487512677907943730f, 0.387458056211471560f, -0.487169682979583740f,
+  0.385963946580886840f, -0.486822128295898440f,
+  0.384470939636230470f, -0.486469984054565430f, 0.382979035377502440f,
+  -0.486113250255584720f, 0.381488204002380370f, -0.485751956701278690f,
+  0.379998475313186650f, -0.485386073589324950f,
+  0.378509908914566040f, -0.485015630722045900f, 0.377022475004196170f,
+  -0.484640628099441530f, 0.375536203384399410f, -0.484261035919189450f,
+  0.374051094055175780f, -0.483876913785934450f,
+  0.372567176818847660f, -0.483488231897354130f, 0.371084451675415040f,
+  -0.483094990253448490f, 0.369602948427200320f, -0.482697218656539920f,
+  0.368122667074203490f, -0.482294887304306030f,
+  0.366643607616424560f, -0.481888025999069210f, 0.365165829658508300f,
+  -0.481476634740829470f, 0.363689333200454710f, -0.481060713529586790f,
+  0.362214088439941410f, -0.480640232563018800f,
+  0.360740154981613160f, -0.480215251445770260f, 0.359267532825469970f,
+  -0.479785770177841190f, 0.357796221971511840f, -0.479351729154586790f,
+  0.356326282024383540f, -0.478913217782974240f,
+  0.354857653379440310f, -0.478470176458358760f, 0.353390425443649290f,
+  -0.478022634983062740f, 0.351924568414688110f, -0.477570593357086180f,
+  0.350460082292556760f, -0.477114051580429080f,
+  0.348997026681900020f, -0.476653009653091430f, 0.347535371780395510f,
+  -0.476187497377395630f, 0.346075177192687990f, -0.475717514753341670f,
+  0.344616413116455080f, -0.475243031978607180f,
+  0.343159139156341550f, -0.474764078855514530f, 0.341703325510025020f,
+  -0.474280685186386110f, 0.340248972177505490f, -0.473792791366577150f,
+  0.338796168565750120f, -0.473300457000732420f,
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+  0.499884694814682010f, 0.490796625614166260f, 0.499915301799774170f,
+  0.492330402135849000f, 0.499941170215606690f,
+  0.493864238262176510f, 0.499962359666824340f, 0.495398133993148800f,
+  0.499978810548782350f, 0.496932059526443480f, 0.499990582466125490f,
+  0.498466014862060550f, 0.499997645616531370f
+};
+
+
+/**   
+* \par  
+* Generation of realCoefB array:   
+* \par  
+* n = 1024   
+* 
for (i = 0; i < n; i++)   
+* {   
+*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));   
+*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+*  } 
   
+*   
+*/
+static const float32_t realCoefB[2048] = {
+  0.500000000000000000f, 0.500000000000000000f, 0.501533985137939450f,
+  0.499997645616531370f, 0.503067970275878910f, 0.499990582466125490f,
+  0.504601895809173580f, 0.499978810548782350f,
+  0.506135761737823490f, 0.499962359666824340f, 0.507669627666473390f,
+  0.499941170215606690f, 0.509203374385833740f, 0.499915301799774170f,
+  0.510737061500549320f, 0.499884694814682010f,
+  0.512270629405975340f, 0.499849408864974980f, 0.513804078102111820f,
+  0.499809414148330690f, 0.515337407588958740f, 0.499764710664749150f,
+  0.516870558261871340f, 0.499715298414230350f,
+  0.518403589725494380f, 0.499661177396774290f, 0.519936442375183110f,
+  0.499602377414703370f, 0.521469116210937500f, 0.499538868665695190f,
+  0.523001611232757570f, 0.499470651149749760f,
+  0.524533808231353760f, 0.499397724866867070f, 0.526065826416015630f,
+  0.499320119619369510f, 0.527597606182098390f, 0.499237775802612300f,
+  0.529129147529602050f, 0.499150782823562620f,
+  0.530660390853881840f, 0.499059051275253300f, 0.532191336154937740f,
+  0.498962640762329100f, 0.533721983432769780f, 0.498861521482467650f,
+  0.535252273082733150f, 0.498755723237991330f,
+  0.536782264709472660f, 0.498645216226577760f, 0.538311958312988280f,
+  0.498530030250549320f, 0.539841234683990480f, 0.498410135507583620f,
+  0.541370153427124020f, 0.498285561800003050f,
+  0.542898654937744140f, 0.498156309127807620f, 0.544426798820495610f,
+  0.498022347688674930f, 0.545954465866088870f, 0.497883707284927370f,
+  0.547481775283813480f, 0.497740387916564940f,
+  0.549008548259735110f, 0.497592359781265260f, 0.550534904003143310f,
+  0.497439652681350710f, 0.552060842514038090f, 0.497282296419143680f,
+  0.553586184978485110f, 0.497120231389999390f,
+  0.555111110210418700f, 0.496953487396240230f, 0.556635499000549320f,
+  0.496782064437866210f, 0.558159291744232180f, 0.496605962514877320f,
+  0.559682607650756840f, 0.496425211429595950f,
+  0.561205327510833740f, 0.496239781379699710f, 0.562727510929107670f,
+  0.496049642562866210f, 0.564249038696289060f, 0.495854884386062620f,
+  0.565770030021667480f, 0.495655417442321780f,
+  0.567290365695953370f, 0.495451331138610840f, 0.568810045719146730f,
+  0.495242536067962650f, 0.570329129695892330f, 0.495029091835021970f,
+  0.571847498416900630f, 0.494810998439788820f,
+  0.573365211486816410f, 0.494588255882263180f, 0.574882268905639650f,
+  0.494360834360122680f, 0.576398611068725590f, 0.494128793478012080f,
+  0.577914178371429440f, 0.493892073631286620f,
+  0.579429090023040770f, 0.493650704622268680f, 0.580943167209625240f,
+  0.493404686450958250f, 0.582456588745117190f, 0.493154048919677730f,
+  0.583969175815582280f, 0.492898762226104740f,
+  0.585480928421020510f, 0.492638826370239260f, 0.586991965770721440f,
+  0.492374241352081300f, 0.588502109050750730f, 0.492105036973953250f,
+  0.590011477470397950f, 0.491831213235855100f,
+  0.591519951820373540f, 0.491552740335464480f, 0.593027591705322270f,
+  0.491269648075103760f, 0.594534337520599370f, 0.490981936454772950f,
+  0.596040189266204830f, 0.490689605474472050f,
+  0.597545146942138670f, 0.490392625331878660f, 0.599049210548400880f,
+  0.490091055631637570f, 0.600552320480346680f, 0.489784896373748780f,
+  0.602054476737976070f, 0.489474087953567500f,
+  0.603555679321289060f, 0.489158689975738530f, 0.605055928230285640f,
+  0.488838672637939450f, 0.606555163860321040f, 0.488514065742492680f,
+  0.608053386211395260f, 0.488184869289398190f,
+  0.609550595283508300f, 0.487851053476333620f, 0.611046791076660160f,
+  0.487512677907943730f, 0.612541973590850830f, 0.487169682979583740f,
+  0.614036023616790770f, 0.486822128295898440f,
+  0.615529060363769530f, 0.486469984054565430f, 0.617020964622497560f,
+  0.486113250255584720f, 0.618511795997619630f, 0.485751956701278690f,
+  0.620001494884490970f, 0.485386073589324950f,
+  0.621490061283111570f, 0.485015630722045900f, 0.622977554798126220f,
+  0.484640628099441530f, 0.624463796615600590f, 0.484261035919189450f,
+  0.625948905944824220f, 0.483876913785934450f,
+  0.627432823181152340f, 0.483488231897354130f, 0.628915548324584960f,
+  0.483094990253448490f, 0.630397081375122070f, 0.482697218656539920f,
+  0.631877362728118900f, 0.482294887304306030f,
+  0.633356392383575440f, 0.481888025999069210f, 0.634834170341491700f,
+  0.481476634740829470f, 0.636310696601867680f, 0.481060713529586790f,
+  0.637785911560058590f, 0.480640232563018800f,
+  0.639259815216064450f, 0.480215251445770260f, 0.640732467174530030f,
+  0.479785770177841190f, 0.642203748226165770f, 0.479351729154586790f,
+  0.643673717975616460f, 0.478913217782974240f,
+  0.645142316818237300f, 0.478470176458358760f, 0.646609604358673100f,
+  0.478022634983062740f, 0.648075461387634280f, 0.477570593357086180f,
+  0.649539887905120850f, 0.477114051580429080f,
+  0.651003003120422360f, 0.476653009653091430f, 0.652464628219604490f,
+  0.476187497377395630f, 0.653924822807312010f, 0.475717514753341670f,
+  0.655383586883544920f, 0.475243031978607180f,
+  0.656840860843658450f, 0.474764078855514530f, 0.658296704292297360f,
+  0.474280685186386110f, 0.659750998020172120f, 0.473792791366577150f,
+  0.661203861236572270f, 0.473300457000732420f,
+  0.662655174732208250f, 0.472803652286529540f, 0.664104938507080080f,
+  0.472302407026290890f, 0.665553152561187740f, 0.471796721220016480f,
+  0.666999816894531250f, 0.471286594867706300f,
+  0.668444931507110600f, 0.470772027969360350f, 0.669888436794281010f,
+  0.470253020524978640f, 0.671330332756042480f, 0.469729602336883540f,
+  0.672770678997039790f, 0.469201773405075070f,
+  0.674209356307983400f, 0.468669503927230830f, 0.675646364688873290f,
+  0.468132823705673220f, 0.677081763744354250f, 0.467591762542724610f,
+  0.678515493869781490f, 0.467046260833740230f,
+  0.679947495460510250f, 0.466496407985687260f, 0.681377887725830080f,
+  0.465942144393920900f, 0.682806491851806640f, 0.465383470058441160f,
+  0.684233427047729490f, 0.464820444583892820f,
+  0.685658574104309080f, 0.464253038167953490f, 0.687082052230834960f,
+  0.463681250810623170f, 0.688503682613372800f, 0.463105112314224240f,
+  0.689923584461212160f, 0.462524622678756710f,
+  0.691341698169708250f, 0.461939752101898190f, 0.692758023738861080f,
+  0.461350560188293460f, 0.694172501564025880f, 0.460757017135620120f,
+  0.695585191249847410f, 0.460159152746200560f,
+  0.696996033191680910f, 0.459556937217712400f, 0.698404967784881590f,
+  0.458950400352478030f, 0.699812114238739010f, 0.458339542150497440f,
+  0.701217353343963620f, 0.457724362611770630f,
+  0.702620685100555420f, 0.457104891538620000f, 0.704022109508514400f,
+  0.456481099128723140f, 0.705421566963195800f, 0.455853015184402470f,
+  0.706819176673889160f, 0.455220639705657960f,
+  0.708214759826660160f, 0.454584002494812010f, 0.709608435630798340f,
+  0.453943043947219850f, 0.711000144481658940f, 0.453297853469848630f,
+  0.712389826774597170f, 0.452648371458053590f,
+  0.713777542114257810f, 0.451994657516479490f, 0.715163230895996090f,
+  0.451336652040481570f, 0.716546893119812010f, 0.450674414634704590f,
+  0.717928528785705570f, 0.450007945299148560f,
+  0.719308137893676760f, 0.449337244033813480f, 0.720685660839080810f,
+  0.448662281036376950f, 0.722061097621917720f, 0.447983115911483760f,
+  0.723434448242187500f, 0.447299748659133910f,
+  0.724805653095245360f, 0.446612149477005000f, 0.726174771785736080f,
+  0.445920348167419430f, 0.727541804313659670f, 0.445224374532699580f,
+  0.728906631469726560f, 0.444524168968200680f,
+  0.730269372463226320f, 0.443819820880889890f, 0.731629908084869380f,
+  0.443111270666122440f, 0.732988238334655760f, 0.442398548126220700f,
+  0.734344422817230220f, 0.441681683063507080f,
+  0.735698342323303220f, 0.440960645675659180f, 0.737050116062164310f,
+  0.440235435962677000f, 0.738399624824523930f, 0.439506113529205320f,
+  0.739746868610382080f, 0.438772648572921750f,
+  0.741091907024383540f, 0.438035041093826290f, 0.742434620857238770f,
+  0.437293320894241330f, 0.743775069713592530f, 0.436547487974166870f,
+  0.745113253593444820f, 0.435797542333602910f,
+  0.746449112892150880f, 0.435043483972549440f, 0.747782647609710690f,
+  0.434285342693328860f, 0.749113857746124270f, 0.433523118495941160f,
+  0.750442683696746830f, 0.432756811380386350f,
+  0.751769185066223140f, 0.431986421346664430f, 0.753093302249908450f,
+  0.431211978197097780f, 0.754415094852447510f, 0.430433481931686400f,
+  0.755734443664550780f, 0.429650902748107910f,
+  0.757051348686218260f, 0.428864300251007080f, 0.758365929126739500f,
+  0.428073674440383910f, 0.759678006172180180f, 0.427278995513916020f,
+  0.760987639427185060f, 0.426480293273925780f,
+  0.762294828891754150f, 0.425677597522735600f, 0.763599574565887450f,
+  0.424870878458023070f, 0.764901816844940190f, 0.424060165882110600f,
+  0.766201555728912350f, 0.423245459794998170f,
+  0.767498791217803960f, 0.422426789999008180f, 0.768793523311614990f,
+  0.421604126691818240f, 0.770085752010345460f, 0.420777499675750730f,
+  0.771375417709350590f, 0.419946908950805660f,
+  0.772662520408630370f, 0.419112354516983030f, 0.773947000503540040f,
+  0.418273866176605220f, 0.775228977203369140f, 0.417431443929672240f,
+  0.776508331298828130f, 0.416585087776184080f,
+  0.777785122394561770f, 0.415734797716140750f, 0.779059290885925290f,
+  0.414880603551864620f, 0.780330777168273930f, 0.414022535085678100f,
+  0.781599700450897220f, 0.413160532712936400f,
+  0.782865881919860840f, 0.412294656038284300f, 0.784129500389099120f,
+  0.411424905061721800f, 0.785390377044677730f, 0.410551249980926510f,
+  0.786648571491241460f, 0.409673750400543210f,
+  0.787904083728790280f, 0.408792406320571900f, 0.789156913757324220f,
+  0.407907217741012570f, 0.790407001972198490f, 0.407018154859542850f,
+  0.791654348373413090f, 0.406125307083129880f,
+  0.792898952960968020f, 0.405228585004806520f, 0.794140756130218510f,
+  0.404328078031539920f, 0.795379877090454100f, 0.403423786163330080f,
+  0.796616137027740480f, 0.402515679597854610f,
+  0.797849655151367190f, 0.401603758335113530f, 0.799080371856689450f,
+  0.400688081979751590f, 0.800308227539062500f, 0.399768620729446410f,
+  0.801533281803131100f, 0.398845434188842770f,
+  0.802755534648895260f, 0.397918462753295900f, 0.803974866867065430f,
+  0.396987736225128170f, 0.805191397666931150f, 0.396053284406661990f,
+  0.806405067443847660f, 0.395115107297897340f,
+  0.807615816593170170f, 0.394173204898834230f, 0.808823645114898680f,
+  0.393227607011795040f, 0.810028612613677980f, 0.392278283834457400f,
+  0.811230659484863280f, 0.391325294971466060f,
+  0.812429726123809810f, 0.390368610620498660f, 0.813625931739807130f,
+  0.389408260583877560f, 0.814819097518920900f, 0.388444244861602780f,
+  0.816009342670440670f, 0.387476563453674320f,
+  0.817196667194366460f, 0.386505216360092160f, 0.818380951881408690f,
+  0.385530263185501100f, 0.819562196731567380f, 0.384551674127578740f,
+  0.820740520954132080f, 0.383569449186325070f,
+  0.821915745735168460f, 0.382583618164062500f, 0.823087990283966060f,
+  0.381594210863113400f, 0.824257194995880130f, 0.380601197481155400f,
+  0.825423359870910640f, 0.379604607820510860f,
+  0.826586425304412840f, 0.378604412078857420f, 0.827746450901031490f,
+  0.377600699663162230f, 0.828903317451477050f, 0.376593410968780520f,
+  0.830057144165039060f, 0.375582575798034670f,
+  0.831207871437072750f, 0.374568194150924680f, 0.832355499267578130f,
+  0.373550295829772950f, 0.833499968051910400f, 0.372528880834579470f,
+  0.834641277790069580f, 0.371503978967666630f,
+  0.835779488086700440f, 0.370475560426712040f, 0.836914479732513430f,
+  0.369443655014038090f, 0.838046371936798100f, 0.368408292531967160f,
+  0.839175045490264890f, 0.367369443178176880f,
+  0.840300500392913820f, 0.366327136754989620f, 0.841422796249389650f,
+  0.365281373262405400f, 0.842541813850402830f, 0.364232182502746580f,
+  0.843657672405242920f, 0.363179564476013180f,
+  0.844770252704620360f, 0.362123548984527590f, 0.845879614353179930f,
+  0.361064106225967410f, 0.846985757350921630f, 0.360001266002655030f,
+  0.848088562488555910f, 0.358935028314590450f,
+  0.849188148975372310f, 0.357865422964096070f, 0.850284397602081300f,
+  0.356792420148849490f, 0.851377367973327640f, 0.355716109275817870f,
+  0.852467060089111330f, 0.354636400938034060f,
+  0.853553414344787600f, 0.353553384542465210f, 0.854636430740356450f,
+  0.352467030286788940f, 0.855716109275817870f, 0.351377367973327640f,
+  0.856792449951171880f, 0.350284397602081300f,
+  0.857865393161773680f, 0.349188119173049930f, 0.858934998512268070f,
+  0.348088562488555910f, 0.860001266002655030f, 0.346985727548599240f,
+  0.861064076423645020f, 0.345879614353179930f,
+  0.862123548984527590f, 0.344770282506942750f, 0.863179564476013180f,
+  0.343657672405242920f, 0.864232182502746580f, 0.342541843652725220f,
+  0.865281403064727780f, 0.341422766447067260f,
+  0.866327106952667240f, 0.340300500392913820f, 0.867369413375854490f,
+  0.339175015687942500f, 0.868408262729644780f, 0.338046342134475710f,
+  0.869443655014038090f, 0.336914509534835820f,
+  0.870475590229034420f, 0.335779488086700440f, 0.871503949165344240f,
+  0.334641307592391970f, 0.872528910636901860f, 0.333499968051910400f,
+  0.873550295829772950f, 0.332355499267578130f,
+  0.874568223953247070f, 0.331207901239395140f, 0.875582575798034670f,
+  0.330057173967361450f, 0.876593410968780520f, 0.328903347253799440f,
+  0.877600669860839840f, 0.327746421098709110f,
+  0.878604412078857420f, 0.326586425304412840f, 0.879604578018188480f,
+  0.325423330068588260f, 0.880601167678833010f, 0.324257194995880130f,
+  0.881594181060791020f, 0.323088020086288450f,
+  0.882583618164062500f, 0.321915775537490840f, 0.883569478988647460f,
+  0.320740520954132080f, 0.884551644325256350f, 0.319562226533889770f,
+  0.885530233383178710f, 0.318380922079086300f,
+  0.886505246162414550f, 0.317196637392044070f, 0.887476563453674320f,
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+  -0.457724362611770630f, 0.699812114238739010f, -0.458339542150497440f,
+  0.698404967784881590f, -0.458950400352478030f,
+  0.696996033191680910f, -0.459556937217712400f, 0.695585191249847410f,
+  -0.460159152746200560f, 0.694172501564025880f, -0.460757017135620120f,
+  0.692758023738861080f, -0.461350560188293460f,
+  0.691341698169708250f, -0.461939752101898190f, 0.689923584461212160f,
+  -0.462524622678756710f, 0.688503682613372800f, -0.463105112314224240f,
+  0.687082052230834960f, -0.463681250810623170f,
+  0.685658574104309080f, -0.464253038167953490f, 0.684233427047729490f,
+  -0.464820444583892820f, 0.682806491851806640f, -0.465383470058441160f,
+  0.681377887725830080f, -0.465942144393920900f,
+  0.679947495460510250f, -0.466496407985687260f, 0.678515493869781490f,
+  -0.467046260833740230f, 0.677081763744354250f, -0.467591762542724610f,
+  0.675646364688873290f, -0.468132823705673220f,
+  0.674209356307983400f, -0.468669503927230830f, 0.672770678997039790f,
+  -0.469201773405075070f, 0.671330332756042480f, -0.469729602336883540f,
+  0.669888436794281010f, -0.470253020524978640f,
+  0.668444931507110600f, -0.470772027969360350f, 0.666999816894531250f,
+  -0.471286594867706300f, 0.665553152561187740f, -0.471796721220016480f,
+  0.664104938507080080f, -0.472302407026290890f,
+  0.662655174732208250f, -0.472803652286529540f, 0.661203861236572270f,
+  -0.473300457000732420f, 0.659750998020172120f, -0.473792791366577150f,
+  0.658296704292297360f, -0.474280685186386110f,
+  0.656840860843658450f, -0.474764078855514530f, 0.655383586883544920f,
+  -0.475243031978607180f, 0.653924822807312010f, -0.475717514753341670f,
+  0.652464628219604490f, -0.476187497377395630f,
+  0.651003003120422360f, -0.476653009653091430f, 0.649539887905120850f,
+  -0.477114051580429080f, 0.648075461387634280f, -0.477570593357086180f,
+  0.646609604358673100f, -0.478022634983062740f,
+  0.645142316818237300f, -0.478470176458358760f, 0.643673717975616460f,
+  -0.478913217782974240f, 0.642203748226165770f, -0.479351729154586790f,
+  0.640732467174530030f, -0.479785770177841190f,
+  0.639259815216064450f, -0.480215251445770260f, 0.637785911560058590f,
+  -0.480640232563018800f, 0.636310696601867680f, -0.481060713529586790f,
+  0.634834170341491700f, -0.481476634740829470f,
+  0.633356392383575440f, -0.481888025999069210f, 0.631877362728118900f,
+  -0.482294887304306030f, 0.630397081375122070f, -0.482697218656539920f,
+  0.628915548324584960f, -0.483094990253448490f,
+  0.627432823181152340f, -0.483488231897354130f, 0.625948905944824220f,
+  -0.483876913785934450f, 0.624463796615600590f, -0.484261035919189450f,
+  0.622977554798126220f, -0.484640628099441530f,
+  0.621490061283111570f, -0.485015630722045900f, 0.620001494884490970f,
+  -0.485386073589324950f, 0.618511795997619630f, -0.485751956701278690f,
+  0.617020964622497560f, -0.486113250255584720f,
+  0.615529060363769530f, -0.486469984054565430f, 0.614036023616790770f,
+  -0.486822128295898440f, 0.612541973590850830f, -0.487169682979583740f,
+  0.611046791076660160f, -0.487512677907943730f,
+  0.609550595283508300f, -0.487851053476333620f, 0.608053386211395260f,
+  -0.488184869289398190f, 0.606555163860321040f, -0.488514065742492680f,
+  0.605055928230285640f, -0.488838672637939450f,
+  0.603555679321289060f, -0.489158689975738530f, 0.602054476737976070f,
+  -0.489474087953567500f, 0.600552320480346680f, -0.489784896373748780f,
+  0.599049210548400880f, -0.490091055631637570f,
+  0.597545146942138670f, -0.490392625331878660f, 0.596040189266204830f,
+  -0.490689605474472050f, 0.594534337520599370f, -0.490981936454772950f,
+  0.593027591705322270f, -0.491269648075103760f,
+  0.591519951820373540f, -0.491552740335464480f, 0.590011477470397950f,
+  -0.491831213235855100f, 0.588502109050750730f, -0.492105036973953250f,
+  0.586991965770721440f, -0.492374241352081300f,
+  0.585480928421020510f, -0.492638826370239260f, 0.583969175815582280f,
+  -0.492898762226104740f, 0.582456588745117190f, -0.493154048919677730f,
+  0.580943167209625240f, -0.493404686450958250f,
+  0.579429090023040770f, -0.493650704622268680f, 0.577914178371429440f,
+  -0.493892073631286620f, 0.576398611068725590f, -0.494128793478012080f,
+  0.574882268905639650f, -0.494360834360122680f,
+  0.573365211486816410f, -0.494588255882263180f, 0.571847498416900630f,
+  -0.494810998439788820f, 0.570329129695892330f, -0.495029091835021970f,
+  0.568810045719146730f, -0.495242536067962650f,
+  0.567290365695953370f, -0.495451331138610840f, 0.565770030021667480f,
+  -0.495655417442321780f, 0.564249038696289060f, -0.495854884386062620f,
+  0.562727510929107670f, -0.496049642562866210f,
+  0.561205327510833740f, -0.496239781379699710f, 0.559682607650756840f,
+  -0.496425211429595950f, 0.558159291744232180f, -0.496605962514877320f,
+  0.556635499000549320f, -0.496782064437866210f,
+  0.555111110210418700f, -0.496953487396240230f, 0.553586184978485110f,
+  -0.497120231389999390f, 0.552060842514038090f, -0.497282296419143680f,
+  0.550534904003143310f, -0.497439652681350710f,
+  0.549008548259735110f, -0.497592359781265260f, 0.547481775283813480f,
+  -0.497740387916564940f, 0.545954465866088870f, -0.497883707284927370f,
+  0.544426798820495610f, -0.498022347688674930f,
+  0.542898654937744140f, -0.498156309127807620f, 0.541370153427124020f,
+  -0.498285561800003050f, 0.539841234683990480f, -0.498410135507583620f,
+  0.538311958312988280f, -0.498530030250549320f,
+  0.536782264709472660f, -0.498645216226577760f, 0.535252273082733150f,
+  -0.498755723237991330f, 0.533721983432769780f, -0.498861521482467650f,
+  0.532191336154937740f, -0.498962640762329100f,
+  0.530660390853881840f, -0.499059051275253300f, 0.529129147529602050f,
+  -0.499150782823562620f, 0.527597606182098390f, -0.499237775802612300f,
+  0.526065826416015630f, -0.499320119619369510f,
+  0.524533808231353760f, -0.499397724866867070f, 0.523001611232757570f,
+  -0.499470651149749760f, 0.521469116210937500f, -0.499538868665695190f,
+  0.519936442375183110f, -0.499602377414703370f,
+  0.518403589725494380f, -0.499661177396774290f, 0.516870558261871340f,
+  -0.499715298414230350f, 0.515337407588958740f, -0.499764710664749150f,
+  0.513804078102111820f, -0.499809414148330690f,
+  0.512270629405975340f, -0.499849408864974980f, 0.510737061500549320f,
+  -0.499884694814682010f, 0.509203374385833740f, -0.499915301799774170f,
+  0.507669627666473390f, -0.499941170215606690f,
+  0.506135761737823490f, -0.499962359666824340f, 0.504601895809173580f,
+  -0.499978810548782350f, 0.503067970275878910f, -0.499990582466125490f,
+  0.501533985137939450f, -0.499997645616531370f
+};
+
+
+
+/**   
+* @brief  Initialization function for the floating-point RFFT/RIFFT.  
+* @param[in,out] *S             points to an instance of the floating-point RFFT/RIFFT structure.  
+* @param[in,out] *S_CFFT        points to an instance of the floating-point CFFT/CIFFT structure.  
+* @param[in]     fftLenReal     length of the FFT.  
+* @param[in]     ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.  
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.  
+*   
+* \par Description:  
+* \par  
+* The parameter fftLenReal	Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.   
+* \par   
+* The parameter ifftFlagR controls whether a forward or inverse transform is computed.   
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.   
+* \par   
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.  
+* \par   
+* This function also initializes Twiddle factor table.    
+*/
+
+arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag)
+{
+
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialize the Real FFT length */
+  S->fftLenReal = (uint16_t) fftLenReal;
+
+  /*  Initialize the Complex FFT length */
+  S->fftLenBy2 = (uint16_t) fftLenReal / 2u;
+
+  /*  Initialize the Twiddle coefficientA pointer */
+  S->pTwiddleAReal = (float32_t *) realCoefA;
+
+  /*  Initialize the Twiddle coefficientB pointer */
+  S->pTwiddleBReal = (float32_t *) realCoefB;
+
+  /*  Initialize the Flag for selection of RFFT or RIFFT */
+  S->ifftFlagR = (uint8_t) ifftFlagR;
+
+  /*  Initialize the Flag for calculation Bit reversal or not */
+  S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+  /*  Initializations of structure parameters depending on the FFT length */
+  switch (S->fftLenReal)
+  {
+    /* Init table modifier value */
+  case 2048u:
+    S->twidCoefRModifier = 1u;
+    break;
+  case 512u:
+    S->twidCoefRModifier = 4u;
+    break;
+  case 128u:
+    S->twidCoefRModifier = 16u;
+    break;
+  default:
+    /*  Reporting argument error if rfftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  /* Init Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  if(S->ifftFlagR)
+  {
+    /* Initializes the CIFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 1u, 0u);
+  }
+  else
+  {
+    /* Initializes the CFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 0u, 0u);
+  }
+
+  /* return the status of RFFT Init function */
+  return (status);
+
+}
+
+  /**   
+   * @} end of RFFT_RIFFT group   
+   */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c
new file mode 100644
index 000000000..843a33bce
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c
@@ -0,0 +1,688 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_rfft_init_q15.c   
+*   
+* Description:	RFFT & RIFFT Q15 initialisation function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup RFFT_RIFFT   
+ * @{   
+ */
+
+
+
+/**   
+* \par   
+* Generation floating point real_CoefA array:   
+* \par   
+* n = 1024   
+* 
for (i = 0; i < n; i++)   
+*  {   
+*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));   
+*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+*  } 
   
+* \par   
+* Convert to fixed point Q15 format   
+*       round(pATable[i] * pow(2, 15))   
+*/
+
+
+static const q15_t realCoefAQ15[2048] = {
+
+  0x4000, 0xc000, 0x3fce, 0xc000, 0x3f9b, 0xc000, 0x3f69, 0xc001,
+  0x3f37, 0xc001, 0x3f05, 0xc002, 0x3ed2, 0xc003, 0x3ea0, 0xc004,
+  0x3e6e, 0xc005, 0x3e3c, 0xc006, 0x3e09, 0xc008, 0x3dd7, 0xc009,
+  0x3da5, 0xc00b, 0x3d73, 0xc00d, 0x3d40, 0xc00f, 0x3d0e, 0xc011,
+  0x3cdc, 0xc014, 0x3caa, 0xc016, 0x3c78, 0xc019, 0x3c45, 0xc01c,
+  0x3c13, 0xc01f, 0x3be1, 0xc022, 0x3baf, 0xc025, 0x3b7d, 0xc029,
+  0x3b4b, 0xc02c, 0x3b19, 0xc030, 0x3ae6, 0xc034, 0x3ab4, 0xc038,
+  0x3a82, 0xc03c, 0x3a50, 0xc041, 0x3a1e, 0xc045, 0x39ec, 0xc04a,
+  0x39ba, 0xc04f, 0x3988, 0xc054, 0x3956, 0xc059, 0x3924, 0xc05e,
+  0x38f2, 0xc064, 0x38c0, 0xc069, 0x388e, 0xc06f, 0x385c, 0xc075,
+  0x382a, 0xc07b, 0x37f9, 0xc081, 0x37c7, 0xc088, 0x3795, 0xc08e,
+  0x3763, 0xc095, 0x3731, 0xc09c, 0x36ff, 0xc0a3, 0x36ce, 0xc0aa,
+  0x369c, 0xc0b1, 0x366a, 0xc0b9, 0x3639, 0xc0c0, 0x3607, 0xc0c8,
+  0x35d5, 0xc0d0, 0x35a4, 0xc0d8, 0x3572, 0xc0e0, 0x3540, 0xc0e9,
+  0x350f, 0xc0f1, 0x34dd, 0xc0fa, 0x34ac, 0xc103, 0x347b, 0xc10c,
+  0x3449, 0xc115, 0x3418, 0xc11e, 0x33e6, 0xc128, 0x33b5, 0xc131,
+  0x3384, 0xc13b, 0x3352, 0xc145, 0x3321, 0xc14f, 0x32f0, 0xc159,
+  0x32bf, 0xc163, 0x328e, 0xc16e, 0x325c, 0xc178, 0x322b, 0xc183,
+  0x31fa, 0xc18e, 0x31c9, 0xc199, 0x3198, 0xc1a4, 0x3167, 0xc1b0,
+  0x3136, 0xc1bb, 0x3105, 0xc1c7, 0x30d5, 0xc1d3, 0x30a4, 0xc1df,
+  0x3073, 0xc1eb, 0x3042, 0xc1f7, 0x3012, 0xc204, 0x2fe1, 0xc210,
+  0x2fb0, 0xc21d, 0x2f80, 0xc22a, 0x2f4f, 0xc237, 0x2f1f, 0xc244,
+  0x2eee, 0xc251, 0x2ebe, 0xc25f, 0x2e8d, 0xc26d, 0x2e5d, 0xc27a,
+  0x2e2d, 0xc288, 0x2dfc, 0xc296, 0x2dcc, 0xc2a5, 0x2d9c, 0xc2b3,
+  0x2d6c, 0xc2c1, 0x2d3c, 0xc2d0, 0x2d0c, 0xc2df, 0x2cdc, 0xc2ee,
+  0x2cac, 0xc2fd, 0x2c7c, 0xc30c, 0x2c4c, 0xc31c, 0x2c1c, 0xc32b,
+  0x2bed, 0xc33b, 0x2bbd, 0xc34b, 0x2b8d, 0xc35b, 0x2b5e, 0xc36b,
+  0x2b2e, 0xc37b, 0x2aff, 0xc38c, 0x2acf, 0xc39c, 0x2aa0, 0xc3ad,
+  0x2a70, 0xc3be, 0x2a41, 0xc3cf, 0x2a12, 0xc3e0, 0x29e3, 0xc3f1,
+  0x29b4, 0xc403, 0x2984, 0xc414, 0x2955, 0xc426, 0x2926, 0xc438,
+  0x28f7, 0xc44a, 0x28c9, 0xc45c, 0x289a, 0xc46e, 0x286b, 0xc481,
+  0x283c, 0xc493, 0x280e, 0xc4a6, 0x27df, 0xc4b9, 0x27b1, 0xc4cc,
+  0x2782, 0xc4df, 0x2754, 0xc4f2, 0x2725, 0xc506, 0x26f7, 0xc51a,
+  0x26c9, 0xc52d, 0x269b, 0xc541, 0x266d, 0xc555, 0x263f, 0xc569,
+  0x2611, 0xc57e, 0x25e3, 0xc592, 0x25b5, 0xc5a7, 0x2587, 0xc5bb,
+  0x2559, 0xc5d0, 0x252c, 0xc5e5, 0x24fe, 0xc5fa, 0x24d0, 0xc610,
+  0x24a3, 0xc625, 0x2476, 0xc63b, 0x2448, 0xc650, 0x241b, 0xc666,
+  0x23ee, 0xc67c, 0x23c1, 0xc692, 0x2394, 0xc6a8, 0x2367, 0xc6bf,
+  0x233a, 0xc6d5, 0x230d, 0xc6ec, 0x22e0, 0xc703, 0x22b3, 0xc71a,
+  0x2287, 0xc731, 0x225a, 0xc748, 0x222d, 0xc75f, 0x2201, 0xc777,
+  0x21d5, 0xc78f, 0x21a8, 0xc7a6, 0x217c, 0xc7be, 0x2150, 0xc7d6,
+  0x2124, 0xc7ee, 0x20f8, 0xc807, 0x20cc, 0xc81f, 0x20a0, 0xc838,
+  0x2074, 0xc850, 0x2049, 0xc869, 0x201d, 0xc882, 0x1ff1, 0xc89b,
+  0x1fc6, 0xc8b5, 0x1f9b, 0xc8ce, 0x1f6f, 0xc8e8, 0x1f44, 0xc901,
+  0x1f19, 0xc91b, 0x1eee, 0xc935, 0x1ec3, 0xc94f, 0x1e98, 0xc969,
+  0x1e6d, 0xc983, 0x1e42, 0xc99e, 0x1e18, 0xc9b8, 0x1ded, 0xc9d3,
+  0x1dc3, 0xc9ee, 0x1d98, 0xca09, 0x1d6e, 0xca24, 0x1d44, 0xca3f,
+  0x1d19, 0xca5b, 0x1cef, 0xca76, 0x1cc5, 0xca92, 0x1c9b, 0xcaad,
+  0x1c72, 0xcac9, 0x1c48, 0xcae5, 0x1c1e, 0xcb01, 0x1bf5, 0xcb1e,
+  0x1bcb, 0xcb3a, 0x1ba2, 0xcb56, 0x1b78, 0xcb73, 0x1b4f, 0xcb90,
+  0x1b26, 0xcbad, 0x1afd, 0xcbca, 0x1ad4, 0xcbe7, 0x1aab, 0xcc04,
+  0x1a82, 0xcc21, 0x1a5a, 0xcc3f, 0x1a31, 0xcc5d, 0x1a08, 0xcc7a,
+  0x19e0, 0xcc98, 0x19b8, 0xccb6, 0x198f, 0xccd4, 0x1967, 0xccf3,
+  0x193f, 0xcd11, 0x1917, 0xcd30, 0x18ef, 0xcd4e, 0x18c8, 0xcd6d,
+  0x18a0, 0xcd8c, 0x1878, 0xcdab, 0x1851, 0xcdca, 0x182a, 0xcde9,
+  0x1802, 0xce08, 0x17db, 0xce28, 0x17b4, 0xce47, 0x178d, 0xce67,
+  0x1766, 0xce87, 0x173f, 0xcea7, 0x1719, 0xcec7, 0x16f2, 0xcee7,
+  0x16cb, 0xcf07, 0x16a5, 0xcf28, 0x167f, 0xcf48, 0x1659, 0xcf69,
+  0x1632, 0xcf8a, 0x160c, 0xcfab, 0x15e6, 0xcfcc, 0x15c1, 0xcfed,
+  0x159b, 0xd00e, 0x1575, 0xd030, 0x1550, 0xd051, 0x152a, 0xd073,
+  0x1505, 0xd094, 0x14e0, 0xd0b6, 0x14bb, 0xd0d8, 0x1496, 0xd0fa,
+  0x1471, 0xd11c, 0x144c, 0xd13e, 0x1428, 0xd161, 0x1403, 0xd183,
+  0x13df, 0xd1a6, 0x13ba, 0xd1c9, 0x1396, 0xd1eb, 0x1372, 0xd20e,
+  0x134e, 0xd231, 0x132a, 0xd255, 0x1306, 0xd278, 0x12e2, 0xd29b,
+  0x12bf, 0xd2bf, 0x129b, 0xd2e2, 0x1278, 0xd306, 0x1255, 0xd32a,
+  0x1231, 0xd34e, 0x120e, 0xd372, 0x11eb, 0xd396, 0x11c9, 0xd3ba,
+  0x11a6, 0xd3df, 0x1183, 0xd403, 0x1161, 0xd428, 0x113e, 0xd44c,
+  0x111c, 0xd471, 0x10fa, 0xd496, 0x10d8, 0xd4bb, 0x10b6, 0xd4e0,
+  0x1094, 0xd505, 0x1073, 0xd52a, 0x1051, 0xd550, 0x1030, 0xd575,
+  0x100e, 0xd59b, 0xfed, 0xd5c1, 0xfcc, 0xd5e6, 0xfab, 0xd60c,
+  0xf8a, 0xd632, 0xf69, 0xd659, 0xf48, 0xd67f, 0xf28, 0xd6a5,
+  0xf07, 0xd6cb, 0xee7, 0xd6f2, 0xec7, 0xd719, 0xea7, 0xd73f,
+  0xe87, 0xd766, 0xe67, 0xd78d, 0xe47, 0xd7b4, 0xe28, 0xd7db,
+  0xe08, 0xd802, 0xde9, 0xd82a, 0xdca, 0xd851, 0xdab, 0xd878,
+  0xd8c, 0xd8a0, 0xd6d, 0xd8c8, 0xd4e, 0xd8ef, 0xd30, 0xd917,
+  0xd11, 0xd93f, 0xcf3, 0xd967, 0xcd4, 0xd98f, 0xcb6, 0xd9b8,
+  0xc98, 0xd9e0, 0xc7a, 0xda08, 0xc5d, 0xda31, 0xc3f, 0xda5a,
+  0xc21, 0xda82, 0xc04, 0xdaab, 0xbe7, 0xdad4, 0xbca, 0xdafd,
+  0xbad, 0xdb26, 0xb90, 0xdb4f, 0xb73, 0xdb78, 0xb56, 0xdba2,
+  0xb3a, 0xdbcb, 0xb1e, 0xdbf5, 0xb01, 0xdc1e, 0xae5, 0xdc48,
+  0xac9, 0xdc72, 0xaad, 0xdc9b, 0xa92, 0xdcc5, 0xa76, 0xdcef,
+  0xa5b, 0xdd19, 0xa3f, 0xdd44, 0xa24, 0xdd6e, 0xa09, 0xdd98,
+  0x9ee, 0xddc3, 0x9d3, 0xdded, 0x9b8, 0xde18, 0x99e, 0xde42,
+  0x983, 0xde6d, 0x969, 0xde98, 0x94f, 0xdec3, 0x935, 0xdeee,
+  0x91b, 0xdf19, 0x901, 0xdf44, 0x8e8, 0xdf6f, 0x8ce, 0xdf9b,
+  0x8b5, 0xdfc6, 0x89b, 0xdff1, 0x882, 0xe01d, 0x869, 0xe049,
+  0x850, 0xe074, 0x838, 0xe0a0, 0x81f, 0xe0cc, 0x807, 0xe0f8,
+  0x7ee, 0xe124, 0x7d6, 0xe150, 0x7be, 0xe17c, 0x7a6, 0xe1a8,
+  0x78f, 0xe1d5, 0x777, 0xe201, 0x75f, 0xe22d, 0x748, 0xe25a,
+  0x731, 0xe287, 0x71a, 0xe2b3, 0x703, 0xe2e0, 0x6ec, 0xe30d,
+  0x6d5, 0xe33a, 0x6bf, 0xe367, 0x6a8, 0xe394, 0x692, 0xe3c1,
+  0x67c, 0xe3ee, 0x666, 0xe41b, 0x650, 0xe448, 0x63b, 0xe476,
+  0x625, 0xe4a3, 0x610, 0xe4d0, 0x5fa, 0xe4fe, 0x5e5, 0xe52c,
+  0x5d0, 0xe559, 0x5bb, 0xe587, 0x5a7, 0xe5b5, 0x592, 0xe5e3,
+  0x57e, 0xe611, 0x569, 0xe63f, 0x555, 0xe66d, 0x541, 0xe69b,
+  0x52d, 0xe6c9, 0x51a, 0xe6f7, 0x506, 0xe725, 0x4f2, 0xe754,
+  0x4df, 0xe782, 0x4cc, 0xe7b1, 0x4b9, 0xe7df, 0x4a6, 0xe80e,
+  0x493, 0xe83c, 0x481, 0xe86b, 0x46e, 0xe89a, 0x45c, 0xe8c9,
+  0x44a, 0xe8f7, 0x438, 0xe926, 0x426, 0xe955, 0x414, 0xe984,
+  0x403, 0xe9b4, 0x3f1, 0xe9e3, 0x3e0, 0xea12, 0x3cf, 0xea41,
+  0x3be, 0xea70, 0x3ad, 0xeaa0, 0x39c, 0xeacf, 0x38c, 0xeaff,
+  0x37b, 0xeb2e, 0x36b, 0xeb5e, 0x35b, 0xeb8d, 0x34b, 0xebbd,
+  0x33b, 0xebed, 0x32b, 0xec1c, 0x31c, 0xec4c, 0x30c, 0xec7c,
+  0x2fd, 0xecac, 0x2ee, 0xecdc, 0x2df, 0xed0c, 0x2d0, 0xed3c,
+  0x2c1, 0xed6c, 0x2b3, 0xed9c, 0x2a5, 0xedcc, 0x296, 0xedfc,
+  0x288, 0xee2d, 0x27a, 0xee5d, 0x26d, 0xee8d, 0x25f, 0xeebe,
+  0x251, 0xeeee, 0x244, 0xef1f, 0x237, 0xef4f, 0x22a, 0xef80,
+  0x21d, 0xefb0, 0x210, 0xefe1, 0x204, 0xf012, 0x1f7, 0xf042,
+  0x1eb, 0xf073, 0x1df, 0xf0a4, 0x1d3, 0xf0d5, 0x1c7, 0xf105,
+  0x1bb, 0xf136, 0x1b0, 0xf167, 0x1a4, 0xf198, 0x199, 0xf1c9,
+  0x18e, 0xf1fa, 0x183, 0xf22b, 0x178, 0xf25c, 0x16e, 0xf28e,
+  0x163, 0xf2bf, 0x159, 0xf2f0, 0x14f, 0xf321, 0x145, 0xf352,
+  0x13b, 0xf384, 0x131, 0xf3b5, 0x128, 0xf3e6, 0x11e, 0xf418,
+  0x115, 0xf449, 0x10c, 0xf47b, 0x103, 0xf4ac, 0xfa, 0xf4dd,
+  0xf1, 0xf50f, 0xe9, 0xf540, 0xe0, 0xf572, 0xd8, 0xf5a4,
+  0xd0, 0xf5d5, 0xc8, 0xf607, 0xc0, 0xf639, 0xb9, 0xf66a,
+  0xb1, 0xf69c, 0xaa, 0xf6ce, 0xa3, 0xf6ff, 0x9c, 0xf731,
+  0x95, 0xf763, 0x8e, 0xf795, 0x88, 0xf7c7, 0x81, 0xf7f9,
+  0x7b, 0xf82a, 0x75, 0xf85c, 0x6f, 0xf88e, 0x69, 0xf8c0,
+  0x64, 0xf8f2, 0x5e, 0xf924, 0x59, 0xf956, 0x54, 0xf988,
+  0x4f, 0xf9ba, 0x4a, 0xf9ec, 0x45, 0xfa1e, 0x41, 0xfa50,
+  0x3c, 0xfa82, 0x38, 0xfab4, 0x34, 0xfae6, 0x30, 0xfb19,
+  0x2c, 0xfb4b, 0x29, 0xfb7d, 0x25, 0xfbaf, 0x22, 0xfbe1,
+  0x1f, 0xfc13, 0x1c, 0xfc45, 0x19, 0xfc78, 0x16, 0xfcaa,
+  0x14, 0xfcdc, 0x11, 0xfd0e, 0xf, 0xfd40, 0xd, 0xfd73,
+  0xb, 0xfda5, 0x9, 0xfdd7, 0x8, 0xfe09, 0x6, 0xfe3c,
+  0x5, 0xfe6e, 0x4, 0xfea0, 0x3, 0xfed2, 0x2, 0xff05,
+  0x1, 0xff37, 0x1, 0xff69, 0x0, 0xff9b, 0x0, 0xffce,
+  0x0, 0x0, 0x0, 0x32, 0x0, 0x65, 0x1, 0x97,
+  0x1, 0xc9, 0x2, 0xfb, 0x3, 0x12e, 0x4, 0x160,
+  0x5, 0x192, 0x6, 0x1c4, 0x8, 0x1f7, 0x9, 0x229,
+  0xb, 0x25b, 0xd, 0x28d, 0xf, 0x2c0, 0x11, 0x2f2,
+  0x14, 0x324, 0x16, 0x356, 0x19, 0x388, 0x1c, 0x3bb,
+  0x1f, 0x3ed, 0x22, 0x41f, 0x25, 0x451, 0x29, 0x483,
+  0x2c, 0x4b5, 0x30, 0x4e7, 0x34, 0x51a, 0x38, 0x54c,
+  0x3c, 0x57e, 0x41, 0x5b0, 0x45, 0x5e2, 0x4a, 0x614,
+  0x4f, 0x646, 0x54, 0x678, 0x59, 0x6aa, 0x5e, 0x6dc,
+  0x64, 0x70e, 0x69, 0x740, 0x6f, 0x772, 0x75, 0x7a4,
+  0x7b, 0x7d6, 0x81, 0x807, 0x88, 0x839, 0x8e, 0x86b,
+  0x95, 0x89d, 0x9c, 0x8cf, 0xa3, 0x901, 0xaa, 0x932,
+  0xb1, 0x964, 0xb9, 0x996, 0xc0, 0x9c7, 0xc8, 0x9f9,
+  0xd0, 0xa2b, 0xd8, 0xa5c, 0xe0, 0xa8e, 0xe9, 0xac0,
+  0xf1, 0xaf1, 0xfa, 0xb23, 0x103, 0xb54, 0x10c, 0xb85,
+  0x115, 0xbb7, 0x11e, 0xbe8, 0x128, 0xc1a, 0x131, 0xc4b,
+  0x13b, 0xc7c, 0x145, 0xcae, 0x14f, 0xcdf, 0x159, 0xd10,
+  0x163, 0xd41, 0x16e, 0xd72, 0x178, 0xda4, 0x183, 0xdd5,
+  0x18e, 0xe06, 0x199, 0xe37, 0x1a4, 0xe68, 0x1b0, 0xe99,
+  0x1bb, 0xeca, 0x1c7, 0xefb, 0x1d3, 0xf2b, 0x1df, 0xf5c,
+  0x1eb, 0xf8d, 0x1f7, 0xfbe, 0x204, 0xfee, 0x210, 0x101f,
+  0x21d, 0x1050, 0x22a, 0x1080, 0x237, 0x10b1, 0x244, 0x10e1,
+  0x251, 0x1112, 0x25f, 0x1142, 0x26d, 0x1173, 0x27a, 0x11a3,
+  0x288, 0x11d3, 0x296, 0x1204, 0x2a5, 0x1234, 0x2b3, 0x1264,
+  0x2c1, 0x1294, 0x2d0, 0x12c4, 0x2df, 0x12f4, 0x2ee, 0x1324,
+  0x2fd, 0x1354, 0x30c, 0x1384, 0x31c, 0x13b4, 0x32b, 0x13e4,
+  0x33b, 0x1413, 0x34b, 0x1443, 0x35b, 0x1473, 0x36b, 0x14a2,
+  0x37b, 0x14d2, 0x38c, 0x1501, 0x39c, 0x1531, 0x3ad, 0x1560,
+  0x3be, 0x1590, 0x3cf, 0x15bf, 0x3e0, 0x15ee, 0x3f1, 0x161d,
+  0x403, 0x164c, 0x414, 0x167c, 0x426, 0x16ab, 0x438, 0x16da,
+  0x44a, 0x1709, 0x45c, 0x1737, 0x46e, 0x1766, 0x481, 0x1795,
+  0x493, 0x17c4, 0x4a6, 0x17f2, 0x4b9, 0x1821, 0x4cc, 0x184f,
+  0x4df, 0x187e, 0x4f2, 0x18ac, 0x506, 0x18db, 0x51a, 0x1909,
+  0x52d, 0x1937, 0x541, 0x1965, 0x555, 0x1993, 0x569, 0x19c1,
+  0x57e, 0x19ef, 0x592, 0x1a1d, 0x5a7, 0x1a4b, 0x5bb, 0x1a79,
+  0x5d0, 0x1aa7, 0x5e5, 0x1ad4, 0x5fa, 0x1b02, 0x610, 0x1b30,
+  0x625, 0x1b5d, 0x63b, 0x1b8a, 0x650, 0x1bb8, 0x666, 0x1be5,
+  0x67c, 0x1c12, 0x692, 0x1c3f, 0x6a8, 0x1c6c, 0x6bf, 0x1c99,
+  0x6d5, 0x1cc6, 0x6ec, 0x1cf3, 0x703, 0x1d20, 0x71a, 0x1d4d,
+  0x731, 0x1d79, 0x748, 0x1da6, 0x75f, 0x1dd3, 0x777, 0x1dff,
+  0x78f, 0x1e2b, 0x7a6, 0x1e58, 0x7be, 0x1e84, 0x7d6, 0x1eb0,
+  0x7ee, 0x1edc, 0x807, 0x1f08, 0x81f, 0x1f34, 0x838, 0x1f60,
+  0x850, 0x1f8c, 0x869, 0x1fb7, 0x882, 0x1fe3, 0x89b, 0x200f,
+  0x8b5, 0x203a, 0x8ce, 0x2065, 0x8e8, 0x2091, 0x901, 0x20bc,
+  0x91b, 0x20e7, 0x935, 0x2112, 0x94f, 0x213d, 0x969, 0x2168,
+  0x983, 0x2193, 0x99e, 0x21be, 0x9b8, 0x21e8, 0x9d3, 0x2213,
+  0x9ee, 0x223d, 0xa09, 0x2268, 0xa24, 0x2292, 0xa3f, 0x22bc,
+  0xa5b, 0x22e7, 0xa76, 0x2311, 0xa92, 0x233b, 0xaad, 0x2365,
+  0xac9, 0x238e, 0xae5, 0x23b8, 0xb01, 0x23e2, 0xb1e, 0x240b,
+  0xb3a, 0x2435, 0xb56, 0x245e, 0xb73, 0x2488, 0xb90, 0x24b1,
+  0xbad, 0x24da, 0xbca, 0x2503, 0xbe7, 0x252c, 0xc04, 0x2555,
+  0xc21, 0x257e, 0xc3f, 0x25a6, 0xc5d, 0x25cf, 0xc7a, 0x25f8,
+  0xc98, 0x2620, 0xcb6, 0x2648, 0xcd4, 0x2671, 0xcf3, 0x2699,
+  0xd11, 0x26c1, 0xd30, 0x26e9, 0xd4e, 0x2711, 0xd6d, 0x2738,
+  0xd8c, 0x2760, 0xdab, 0x2788, 0xdca, 0x27af, 0xde9, 0x27d6,
+  0xe08, 0x27fe, 0xe28, 0x2825, 0xe47, 0x284c, 0xe67, 0x2873,
+  0xe87, 0x289a, 0xea7, 0x28c1, 0xec7, 0x28e7, 0xee7, 0x290e,
+  0xf07, 0x2935, 0xf28, 0x295b, 0xf48, 0x2981, 0xf69, 0x29a7,
+  0xf8a, 0x29ce, 0xfab, 0x29f4, 0xfcc, 0x2a1a, 0xfed, 0x2a3f,
+  0x100e, 0x2a65, 0x1030, 0x2a8b, 0x1051, 0x2ab0, 0x1073, 0x2ad6,
+  0x1094, 0x2afb, 0x10b6, 0x2b20, 0x10d8, 0x2b45, 0x10fa, 0x2b6a,
+  0x111c, 0x2b8f, 0x113e, 0x2bb4, 0x1161, 0x2bd8, 0x1183, 0x2bfd,
+  0x11a6, 0x2c21, 0x11c9, 0x2c46, 0x11eb, 0x2c6a, 0x120e, 0x2c8e,
+  0x1231, 0x2cb2, 0x1255, 0x2cd6, 0x1278, 0x2cfa, 0x129b, 0x2d1e,
+  0x12bf, 0x2d41, 0x12e2, 0x2d65, 0x1306, 0x2d88, 0x132a, 0x2dab,
+  0x134e, 0x2dcf, 0x1372, 0x2df2, 0x1396, 0x2e15, 0x13ba, 0x2e37,
+  0x13df, 0x2e5a, 0x1403, 0x2e7d, 0x1428, 0x2e9f, 0x144c, 0x2ec2,
+  0x1471, 0x2ee4, 0x1496, 0x2f06, 0x14bb, 0x2f28, 0x14e0, 0x2f4a,
+  0x1505, 0x2f6c, 0x152a, 0x2f8d, 0x1550, 0x2faf, 0x1575, 0x2fd0,
+  0x159b, 0x2ff2, 0x15c1, 0x3013, 0x15e6, 0x3034, 0x160c, 0x3055,
+  0x1632, 0x3076, 0x1659, 0x3097, 0x167f, 0x30b8, 0x16a5, 0x30d8,
+  0x16cb, 0x30f9, 0x16f2, 0x3119, 0x1719, 0x3139, 0x173f, 0x3159,
+  0x1766, 0x3179, 0x178d, 0x3199, 0x17b4, 0x31b9, 0x17db, 0x31d8,
+  0x1802, 0x31f8, 0x182a, 0x3217, 0x1851, 0x3236, 0x1878, 0x3255,
+  0x18a0, 0x3274, 0x18c8, 0x3293, 0x18ef, 0x32b2, 0x1917, 0x32d0,
+  0x193f, 0x32ef, 0x1967, 0x330d, 0x198f, 0x332c, 0x19b8, 0x334a,
+  0x19e0, 0x3368, 0x1a08, 0x3386, 0x1a31, 0x33a3, 0x1a5a, 0x33c1,
+  0x1a82, 0x33df, 0x1aab, 0x33fc, 0x1ad4, 0x3419, 0x1afd, 0x3436,
+  0x1b26, 0x3453, 0x1b4f, 0x3470, 0x1b78, 0x348d, 0x1ba2, 0x34aa,
+  0x1bcb, 0x34c6, 0x1bf5, 0x34e2, 0x1c1e, 0x34ff, 0x1c48, 0x351b,
+  0x1c72, 0x3537, 0x1c9b, 0x3553, 0x1cc5, 0x356e, 0x1cef, 0x358a,
+  0x1d19, 0x35a5, 0x1d44, 0x35c1, 0x1d6e, 0x35dc, 0x1d98, 0x35f7,
+  0x1dc3, 0x3612, 0x1ded, 0x362d, 0x1e18, 0x3648, 0x1e42, 0x3662,
+  0x1e6d, 0x367d, 0x1e98, 0x3697, 0x1ec3, 0x36b1, 0x1eee, 0x36cb,
+  0x1f19, 0x36e5, 0x1f44, 0x36ff, 0x1f6f, 0x3718, 0x1f9b, 0x3732,
+  0x1fc6, 0x374b, 0x1ff1, 0x3765, 0x201d, 0x377e, 0x2049, 0x3797,
+  0x2074, 0x37b0, 0x20a0, 0x37c8, 0x20cc, 0x37e1, 0x20f8, 0x37f9,
+  0x2124, 0x3812, 0x2150, 0x382a, 0x217c, 0x3842, 0x21a8, 0x385a,
+  0x21d5, 0x3871, 0x2201, 0x3889, 0x222d, 0x38a1, 0x225a, 0x38b8,
+  0x2287, 0x38cf, 0x22b3, 0x38e6, 0x22e0, 0x38fd, 0x230d, 0x3914,
+  0x233a, 0x392b, 0x2367, 0x3941, 0x2394, 0x3958, 0x23c1, 0x396e,
+  0x23ee, 0x3984, 0x241b, 0x399a, 0x2448, 0x39b0, 0x2476, 0x39c5,
+  0x24a3, 0x39db, 0x24d0, 0x39f0, 0x24fe, 0x3a06, 0x252c, 0x3a1b,
+  0x2559, 0x3a30, 0x2587, 0x3a45, 0x25b5, 0x3a59, 0x25e3, 0x3a6e,
+  0x2611, 0x3a82, 0x263f, 0x3a97, 0x266d, 0x3aab, 0x269b, 0x3abf,
+  0x26c9, 0x3ad3, 0x26f7, 0x3ae6, 0x2725, 0x3afa, 0x2754, 0x3b0e,
+  0x2782, 0x3b21, 0x27b1, 0x3b34, 0x27df, 0x3b47, 0x280e, 0x3b5a,
+  0x283c, 0x3b6d, 0x286b, 0x3b7f, 0x289a, 0x3b92, 0x28c9, 0x3ba4,
+  0x28f7, 0x3bb6, 0x2926, 0x3bc8, 0x2955, 0x3bda, 0x2984, 0x3bec,
+  0x29b4, 0x3bfd, 0x29e3, 0x3c0f, 0x2a12, 0x3c20, 0x2a41, 0x3c31,
+  0x2a70, 0x3c42, 0x2aa0, 0x3c53, 0x2acf, 0x3c64, 0x2aff, 0x3c74,
+  0x2b2e, 0x3c85, 0x2b5e, 0x3c95, 0x2b8d, 0x3ca5, 0x2bbd, 0x3cb5,
+  0x2bed, 0x3cc5, 0x2c1c, 0x3cd5, 0x2c4c, 0x3ce4, 0x2c7c, 0x3cf4,
+  0x2cac, 0x3d03, 0x2cdc, 0x3d12, 0x2d0c, 0x3d21, 0x2d3c, 0x3d30,
+  0x2d6c, 0x3d3f, 0x2d9c, 0x3d4d, 0x2dcc, 0x3d5b, 0x2dfc, 0x3d6a,
+  0x2e2d, 0x3d78, 0x2e5d, 0x3d86, 0x2e8d, 0x3d93, 0x2ebe, 0x3da1,
+  0x2eee, 0x3daf, 0x2f1f, 0x3dbc, 0x2f4f, 0x3dc9, 0x2f80, 0x3dd6,
+  0x2fb0, 0x3de3, 0x2fe1, 0x3df0, 0x3012, 0x3dfc, 0x3042, 0x3e09,
+  0x3073, 0x3e15, 0x30a4, 0x3e21, 0x30d5, 0x3e2d, 0x3105, 0x3e39,
+  0x3136, 0x3e45, 0x3167, 0x3e50, 0x3198, 0x3e5c, 0x31c9, 0x3e67,
+  0x31fa, 0x3e72, 0x322b, 0x3e7d, 0x325c, 0x3e88, 0x328e, 0x3e92,
+  0x32bf, 0x3e9d, 0x32f0, 0x3ea7, 0x3321, 0x3eb1, 0x3352, 0x3ebb,
+  0x3384, 0x3ec5, 0x33b5, 0x3ecf, 0x33e6, 0x3ed8, 0x3418, 0x3ee2,
+  0x3449, 0x3eeb, 0x347b, 0x3ef4, 0x34ac, 0x3efd, 0x34dd, 0x3f06,
+  0x350f, 0x3f0f, 0x3540, 0x3f17, 0x3572, 0x3f20, 0x35a4, 0x3f28,
+  0x35d5, 0x3f30, 0x3607, 0x3f38, 0x3639, 0x3f40, 0x366a, 0x3f47,
+  0x369c, 0x3f4f, 0x36ce, 0x3f56, 0x36ff, 0x3f5d, 0x3731, 0x3f64,
+  0x3763, 0x3f6b, 0x3795, 0x3f72, 0x37c7, 0x3f78, 0x37f9, 0x3f7f,
+  0x382a, 0x3f85, 0x385c, 0x3f8b, 0x388e, 0x3f91, 0x38c0, 0x3f97,
+  0x38f2, 0x3f9c, 0x3924, 0x3fa2, 0x3956, 0x3fa7, 0x3988, 0x3fac,
+  0x39ba, 0x3fb1, 0x39ec, 0x3fb6, 0x3a1e, 0x3fbb, 0x3a50, 0x3fbf,
+  0x3a82, 0x3fc4, 0x3ab4, 0x3fc8, 0x3ae6, 0x3fcc, 0x3b19, 0x3fd0,
+  0x3b4b, 0x3fd4, 0x3b7d, 0x3fd7, 0x3baf, 0x3fdb, 0x3be1, 0x3fde,
+  0x3c13, 0x3fe1, 0x3c45, 0x3fe4, 0x3c78, 0x3fe7, 0x3caa, 0x3fea,
+  0x3cdc, 0x3fec, 0x3d0e, 0x3fef, 0x3d40, 0x3ff1, 0x3d73, 0x3ff3,
+  0x3da5, 0x3ff5, 0x3dd7, 0x3ff7, 0x3e09, 0x3ff8, 0x3e3c, 0x3ffa,
+  0x3e6e, 0x3ffb, 0x3ea0, 0x3ffc, 0x3ed2, 0x3ffd, 0x3f05, 0x3ffe,
+  0x3f37, 0x3fff, 0x3f69, 0x3fff, 0x3f9b, 0x4000, 0x3fce, 0x4000
+};
+
+/**   
+* \par  
+* Generation of real_CoefB array:   
+* \par   
+* n = 1024   
+* 
for (i = 0; i < n; i++)   
+*  {   
+*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));   
+*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+*  } 
  
+* \par   
+* Convert to fixed point Q15 format   
+*       round(pBTable[i] * pow(2, 15))   
+*   
+*/
+
+static const q15_t realCoefBQ15[2048] = {
+  0x4000, 0x4000, 0x4032, 0x4000, 0x4065, 0x4000, 0x4097, 0x3fff,
+  0x40c9, 0x3fff, 0x40fb, 0x3ffe, 0x412e, 0x3ffd, 0x4160, 0x3ffc,
+  0x4192, 0x3ffb, 0x41c4, 0x3ffa, 0x41f7, 0x3ff8, 0x4229, 0x3ff7,
+  0x425b, 0x3ff5, 0x428d, 0x3ff3, 0x42c0, 0x3ff1, 0x42f2, 0x3fef,
+  0x4324, 0x3fec, 0x4356, 0x3fea, 0x4388, 0x3fe7, 0x43bb, 0x3fe4,
+  0x43ed, 0x3fe1, 0x441f, 0x3fde, 0x4451, 0x3fdb, 0x4483, 0x3fd7,
+  0x44b5, 0x3fd4, 0x44e7, 0x3fd0, 0x451a, 0x3fcc, 0x454c, 0x3fc8,
+  0x457e, 0x3fc4, 0x45b0, 0x3fbf, 0x45e2, 0x3fbb, 0x4614, 0x3fb6,
+  0x4646, 0x3fb1, 0x4678, 0x3fac, 0x46aa, 0x3fa7, 0x46dc, 0x3fa2,
+  0x470e, 0x3f9c, 0x4740, 0x3f97, 0x4772, 0x3f91, 0x47a4, 0x3f8b,
+  0x47d6, 0x3f85, 0x4807, 0x3f7f, 0x4839, 0x3f78, 0x486b, 0x3f72,
+  0x489d, 0x3f6b, 0x48cf, 0x3f64, 0x4901, 0x3f5d, 0x4932, 0x3f56,
+  0x4964, 0x3f4f, 0x4996, 0x3f47, 0x49c7, 0x3f40, 0x49f9, 0x3f38,
+  0x4a2b, 0x3f30, 0x4a5c, 0x3f28, 0x4a8e, 0x3f20, 0x4ac0, 0x3f17,
+  0x4af1, 0x3f0f, 0x4b23, 0x3f06, 0x4b54, 0x3efd, 0x4b85, 0x3ef4,
+  0x4bb7, 0x3eeb, 0x4be8, 0x3ee2, 0x4c1a, 0x3ed8, 0x4c4b, 0x3ecf,
+  0x4c7c, 0x3ec5, 0x4cae, 0x3ebb, 0x4cdf, 0x3eb1, 0x4d10, 0x3ea7,
+  0x4d41, 0x3e9d, 0x4d72, 0x3e92, 0x4da4, 0x3e88, 0x4dd5, 0x3e7d,
+  0x4e06, 0x3e72, 0x4e37, 0x3e67, 0x4e68, 0x3e5c, 0x4e99, 0x3e50,
+  0x4eca, 0x3e45, 0x4efb, 0x3e39, 0x4f2b, 0x3e2d, 0x4f5c, 0x3e21,
+  0x4f8d, 0x3e15, 0x4fbe, 0x3e09, 0x4fee, 0x3dfc, 0x501f, 0x3df0,
+  0x5050, 0x3de3, 0x5080, 0x3dd6, 0x50b1, 0x3dc9, 0x50e1, 0x3dbc,
+  0x5112, 0x3daf, 0x5142, 0x3da1, 0x5173, 0x3d93, 0x51a3, 0x3d86,
+  0x51d3, 0x3d78, 0x5204, 0x3d6a, 0x5234, 0x3d5b, 0x5264, 0x3d4d,
+  0x5294, 0x3d3f, 0x52c4, 0x3d30, 0x52f4, 0x3d21, 0x5324, 0x3d12,
+  0x5354, 0x3d03, 0x5384, 0x3cf4, 0x53b4, 0x3ce4, 0x53e4, 0x3cd5,
+  0x5413, 0x3cc5, 0x5443, 0x3cb5, 0x5473, 0x3ca5, 0x54a2, 0x3c95,
+  0x54d2, 0x3c85, 0x5501, 0x3c74, 0x5531, 0x3c64, 0x5560, 0x3c53,
+  0x5590, 0x3c42, 0x55bf, 0x3c31, 0x55ee, 0x3c20, 0x561d, 0x3c0f,
+  0x564c, 0x3bfd, 0x567c, 0x3bec, 0x56ab, 0x3bda, 0x56da, 0x3bc8,
+  0x5709, 0x3bb6, 0x5737, 0x3ba4, 0x5766, 0x3b92, 0x5795, 0x3b7f,
+  0x57c4, 0x3b6d, 0x57f2, 0x3b5a, 0x5821, 0x3b47, 0x584f, 0x3b34,
+  0x587e, 0x3b21, 0x58ac, 0x3b0e, 0x58db, 0x3afa, 0x5909, 0x3ae6,
+  0x5937, 0x3ad3, 0x5965, 0x3abf, 0x5993, 0x3aab, 0x59c1, 0x3a97,
+  0x59ef, 0x3a82, 0x5a1d, 0x3a6e, 0x5a4b, 0x3a59, 0x5a79, 0x3a45,
+  0x5aa7, 0x3a30, 0x5ad4, 0x3a1b, 0x5b02, 0x3a06, 0x5b30, 0x39f0,
+  0x5b5d, 0x39db, 0x5b8a, 0x39c5, 0x5bb8, 0x39b0, 0x5be5, 0x399a,
+  0x5c12, 0x3984, 0x5c3f, 0x396e, 0x5c6c, 0x3958, 0x5c99, 0x3941,
+  0x5cc6, 0x392b, 0x5cf3, 0x3914, 0x5d20, 0x38fd, 0x5d4d, 0x38e6,
+  0x5d79, 0x38cf, 0x5da6, 0x38b8, 0x5dd3, 0x38a1, 0x5dff, 0x3889,
+  0x5e2b, 0x3871, 0x5e58, 0x385a, 0x5e84, 0x3842, 0x5eb0, 0x382a,
+  0x5edc, 0x3812, 0x5f08, 0x37f9, 0x5f34, 0x37e1, 0x5f60, 0x37c8,
+  0x5f8c, 0x37b0, 0x5fb7, 0x3797, 0x5fe3, 0x377e, 0x600f, 0x3765,
+  0x603a, 0x374b, 0x6065, 0x3732, 0x6091, 0x3718, 0x60bc, 0x36ff,
+  0x60e7, 0x36e5, 0x6112, 0x36cb, 0x613d, 0x36b1, 0x6168, 0x3697,
+  0x6193, 0x367d, 0x61be, 0x3662, 0x61e8, 0x3648, 0x6213, 0x362d,
+  0x623d, 0x3612, 0x6268, 0x35f7, 0x6292, 0x35dc, 0x62bc, 0x35c1,
+  0x62e7, 0x35a5, 0x6311, 0x358a, 0x633b, 0x356e, 0x6365, 0x3553,
+  0x638e, 0x3537, 0x63b8, 0x351b, 0x63e2, 0x34ff, 0x640b, 0x34e2,
+  0x6435, 0x34c6, 0x645e, 0x34aa, 0x6488, 0x348d, 0x64b1, 0x3470,
+  0x64da, 0x3453, 0x6503, 0x3436, 0x652c, 0x3419, 0x6555, 0x33fc,
+  0x657e, 0x33df, 0x65a6, 0x33c1, 0x65cf, 0x33a3, 0x65f8, 0x3386,
+  0x6620, 0x3368, 0x6648, 0x334a, 0x6671, 0x332c, 0x6699, 0x330d,
+  0x66c1, 0x32ef, 0x66e9, 0x32d0, 0x6711, 0x32b2, 0x6738, 0x3293,
+  0x6760, 0x3274, 0x6788, 0x3255, 0x67af, 0x3236, 0x67d6, 0x3217,
+  0x67fe, 0x31f8, 0x6825, 0x31d8, 0x684c, 0x31b9, 0x6873, 0x3199,
+  0x689a, 0x3179, 0x68c1, 0x3159, 0x68e7, 0x3139, 0x690e, 0x3119,
+  0x6935, 0x30f9, 0x695b, 0x30d8, 0x6981, 0x30b8, 0x69a7, 0x3097,
+  0x69ce, 0x3076, 0x69f4, 0x3055, 0x6a1a, 0x3034, 0x6a3f, 0x3013,
+  0x6a65, 0x2ff2, 0x6a8b, 0x2fd0, 0x6ab0, 0x2faf, 0x6ad6, 0x2f8d,
+  0x6afb, 0x2f6c, 0x6b20, 0x2f4a, 0x6b45, 0x2f28, 0x6b6a, 0x2f06,
+  0x6b8f, 0x2ee4, 0x6bb4, 0x2ec2, 0x6bd8, 0x2e9f, 0x6bfd, 0x2e7d,
+  0x6c21, 0x2e5a, 0x6c46, 0x2e37, 0x6c6a, 0x2e15, 0x6c8e, 0x2df2,
+  0x6cb2, 0x2dcf, 0x6cd6, 0x2dab, 0x6cfa, 0x2d88, 0x6d1e, 0x2d65,
+  0x6d41, 0x2d41, 0x6d65, 0x2d1e, 0x6d88, 0x2cfa, 0x6dab, 0x2cd6,
+  0x6dcf, 0x2cb2, 0x6df2, 0x2c8e, 0x6e15, 0x2c6a, 0x6e37, 0x2c46,
+  0x6e5a, 0x2c21, 0x6e7d, 0x2bfd, 0x6e9f, 0x2bd8, 0x6ec2, 0x2bb4,
+  0x6ee4, 0x2b8f, 0x6f06, 0x2b6a, 0x6f28, 0x2b45, 0x6f4a, 0x2b20,
+  0x6f6c, 0x2afb, 0x6f8d, 0x2ad6, 0x6faf, 0x2ab0, 0x6fd0, 0x2a8b,
+  0x6ff2, 0x2a65, 0x7013, 0x2a3f, 0x7034, 0x2a1a, 0x7055, 0x29f4,
+  0x7076, 0x29ce, 0x7097, 0x29a7, 0x70b8, 0x2981, 0x70d8, 0x295b,
+  0x70f9, 0x2935, 0x7119, 0x290e, 0x7139, 0x28e7, 0x7159, 0x28c1,
+  0x7179, 0x289a, 0x7199, 0x2873, 0x71b9, 0x284c, 0x71d8, 0x2825,
+  0x71f8, 0x27fe, 0x7217, 0x27d6, 0x7236, 0x27af, 0x7255, 0x2788,
+  0x7274, 0x2760, 0x7293, 0x2738, 0x72b2, 0x2711, 0x72d0, 0x26e9,
+  0x72ef, 0x26c1, 0x730d, 0x2699, 0x732c, 0x2671, 0x734a, 0x2648,
+  0x7368, 0x2620, 0x7386, 0x25f8, 0x73a3, 0x25cf, 0x73c1, 0x25a6,
+  0x73df, 0x257e, 0x73fc, 0x2555, 0x7419, 0x252c, 0x7436, 0x2503,
+  0x7453, 0x24da, 0x7470, 0x24b1, 0x748d, 0x2488, 0x74aa, 0x245e,
+  0x74c6, 0x2435, 0x74e2, 0x240b, 0x74ff, 0x23e2, 0x751b, 0x23b8,
+  0x7537, 0x238e, 0x7553, 0x2365, 0x756e, 0x233b, 0x758a, 0x2311,
+  0x75a5, 0x22e7, 0x75c1, 0x22bc, 0x75dc, 0x2292, 0x75f7, 0x2268,
+  0x7612, 0x223d, 0x762d, 0x2213, 0x7648, 0x21e8, 0x7662, 0x21be,
+  0x767d, 0x2193, 0x7697, 0x2168, 0x76b1, 0x213d, 0x76cb, 0x2112,
+  0x76e5, 0x20e7, 0x76ff, 0x20bc, 0x7718, 0x2091, 0x7732, 0x2065,
+  0x774b, 0x203a, 0x7765, 0x200f, 0x777e, 0x1fe3, 0x7797, 0x1fb7,
+  0x77b0, 0x1f8c, 0x77c8, 0x1f60, 0x77e1, 0x1f34, 0x77f9, 0x1f08,
+  0x7812, 0x1edc, 0x782a, 0x1eb0, 0x7842, 0x1e84, 0x785a, 0x1e58,
+  0x7871, 0x1e2b, 0x7889, 0x1dff, 0x78a1, 0x1dd3, 0x78b8, 0x1da6,
+  0x78cf, 0x1d79, 0x78e6, 0x1d4d, 0x78fd, 0x1d20, 0x7914, 0x1cf3,
+  0x792b, 0x1cc6, 0x7941, 0x1c99, 0x7958, 0x1c6c, 0x796e, 0x1c3f,
+  0x7984, 0x1c12, 0x799a, 0x1be5, 0x79b0, 0x1bb8, 0x79c5, 0x1b8a,
+  0x79db, 0x1b5d, 0x79f0, 0x1b30, 0x7a06, 0x1b02, 0x7a1b, 0x1ad4,
+  0x7a30, 0x1aa7, 0x7a45, 0x1a79, 0x7a59, 0x1a4b, 0x7a6e, 0x1a1d,
+  0x7a82, 0x19ef, 0x7a97, 0x19c1, 0x7aab, 0x1993, 0x7abf, 0x1965,
+  0x7ad3, 0x1937, 0x7ae6, 0x1909, 0x7afa, 0x18db, 0x7b0e, 0x18ac,
+  0x7b21, 0x187e, 0x7b34, 0x184f, 0x7b47, 0x1821, 0x7b5a, 0x17f2,
+  0x7b6d, 0x17c4, 0x7b7f, 0x1795, 0x7b92, 0x1766, 0x7ba4, 0x1737,
+  0x7bb6, 0x1709, 0x7bc8, 0x16da, 0x7bda, 0x16ab, 0x7bec, 0x167c,
+  0x7bfd, 0x164c, 0x7c0f, 0x161d, 0x7c20, 0x15ee, 0x7c31, 0x15bf,
+  0x7c42, 0x1590, 0x7c53, 0x1560, 0x7c64, 0x1531, 0x7c74, 0x1501,
+  0x7c85, 0x14d2, 0x7c95, 0x14a2, 0x7ca5, 0x1473, 0x7cb5, 0x1443,
+  0x7cc5, 0x1413, 0x7cd5, 0x13e4, 0x7ce4, 0x13b4, 0x7cf4, 0x1384,
+  0x7d03, 0x1354, 0x7d12, 0x1324, 0x7d21, 0x12f4, 0x7d30, 0x12c4,
+  0x7d3f, 0x1294, 0x7d4d, 0x1264, 0x7d5b, 0x1234, 0x7d6a, 0x1204,
+  0x7d78, 0x11d3, 0x7d86, 0x11a3, 0x7d93, 0x1173, 0x7da1, 0x1142,
+  0x7daf, 0x1112, 0x7dbc, 0x10e1, 0x7dc9, 0x10b1, 0x7dd6, 0x1080,
+  0x7de3, 0x1050, 0x7df0, 0x101f, 0x7dfc, 0xfee, 0x7e09, 0xfbe,
+  0x7e15, 0xf8d, 0x7e21, 0xf5c, 0x7e2d, 0xf2b, 0x7e39, 0xefb,
+  0x7e45, 0xeca, 0x7e50, 0xe99, 0x7e5c, 0xe68, 0x7e67, 0xe37,
+  0x7e72, 0xe06, 0x7e7d, 0xdd5, 0x7e88, 0xda4, 0x7e92, 0xd72,
+  0x7e9d, 0xd41, 0x7ea7, 0xd10, 0x7eb1, 0xcdf, 0x7ebb, 0xcae,
+  0x7ec5, 0xc7c, 0x7ecf, 0xc4b, 0x7ed8, 0xc1a, 0x7ee2, 0xbe8,
+  0x7eeb, 0xbb7, 0x7ef4, 0xb85, 0x7efd, 0xb54, 0x7f06, 0xb23,
+  0x7f0f, 0xaf1, 0x7f17, 0xac0, 0x7f20, 0xa8e, 0x7f28, 0xa5c,
+  0x7f30, 0xa2b, 0x7f38, 0x9f9, 0x7f40, 0x9c7, 0x7f47, 0x996,
+  0x7f4f, 0x964, 0x7f56, 0x932, 0x7f5d, 0x901, 0x7f64, 0x8cf,
+  0x7f6b, 0x89d, 0x7f72, 0x86b, 0x7f78, 0x839, 0x7f7f, 0x807,
+  0x7f85, 0x7d6, 0x7f8b, 0x7a4, 0x7f91, 0x772, 0x7f97, 0x740,
+  0x7f9c, 0x70e, 0x7fa2, 0x6dc, 0x7fa7, 0x6aa, 0x7fac, 0x678,
+  0x7fb1, 0x646, 0x7fb6, 0x614, 0x7fbb, 0x5e2, 0x7fbf, 0x5b0,
+  0x7fc4, 0x57e, 0x7fc8, 0x54c, 0x7fcc, 0x51a, 0x7fd0, 0x4e7,
+  0x7fd4, 0x4b5, 0x7fd7, 0x483, 0x7fdb, 0x451, 0x7fde, 0x41f,
+  0x7fe1, 0x3ed, 0x7fe4, 0x3bb, 0x7fe7, 0x388, 0x7fea, 0x356,
+  0x7fec, 0x324, 0x7fef, 0x2f2, 0x7ff1, 0x2c0, 0x7ff3, 0x28d,
+  0x7ff5, 0x25b, 0x7ff7, 0x229, 0x7ff8, 0x1f7, 0x7ffa, 0x1c4,
+  0x7ffb, 0x192, 0x7ffc, 0x160, 0x7ffd, 0x12e, 0x7ffe, 0xfb,
+  0x7fff, 0xc9, 0x7fff, 0x97, 0x7fff, 0x65, 0x7fff, 0x32,
+  0x7fff, 0x0, 0x7fff, 0xffce, 0x7fff, 0xff9b, 0x7fff, 0xff69,
+  0x7fff, 0xff37, 0x7ffe, 0xff05, 0x7ffd, 0xfed2, 0x7ffc, 0xfea0,
+  0x7ffb, 0xfe6e, 0x7ffa, 0xfe3c, 0x7ff8, 0xfe09, 0x7ff7, 0xfdd7,
+  0x7ff5, 0xfda5, 0x7ff3, 0xfd73, 0x7ff1, 0xfd40, 0x7fef, 0xfd0e,
+  0x7fec, 0xfcdc, 0x7fea, 0xfcaa, 0x7fe7, 0xfc78, 0x7fe4, 0xfc45,
+  0x7fe1, 0xfc13, 0x7fde, 0xfbe1, 0x7fdb, 0xfbaf, 0x7fd7, 0xfb7d,
+  0x7fd4, 0xfb4b, 0x7fd0, 0xfb19, 0x7fcc, 0xfae6, 0x7fc8, 0xfab4,
+  0x7fc4, 0xfa82, 0x7fbf, 0xfa50, 0x7fbb, 0xfa1e, 0x7fb6, 0xf9ec,
+  0x7fb1, 0xf9ba, 0x7fac, 0xf988, 0x7fa7, 0xf956, 0x7fa2, 0xf924,
+  0x7f9c, 0xf8f2, 0x7f97, 0xf8c0, 0x7f91, 0xf88e, 0x7f8b, 0xf85c,
+  0x7f85, 0xf82a, 0x7f7f, 0xf7f9, 0x7f78, 0xf7c7, 0x7f72, 0xf795,
+  0x7f6b, 0xf763, 0x7f64, 0xf731, 0x7f5d, 0xf6ff, 0x7f56, 0xf6ce,
+  0x7f4f, 0xf69c, 0x7f47, 0xf66a, 0x7f40, 0xf639, 0x7f38, 0xf607,
+  0x7f30, 0xf5d5, 0x7f28, 0xf5a4, 0x7f20, 0xf572, 0x7f17, 0xf540,
+  0x7f0f, 0xf50f, 0x7f06, 0xf4dd, 0x7efd, 0xf4ac, 0x7ef4, 0xf47b,
+  0x7eeb, 0xf449, 0x7ee2, 0xf418, 0x7ed8, 0xf3e6, 0x7ecf, 0xf3b5,
+  0x7ec5, 0xf384, 0x7ebb, 0xf352, 0x7eb1, 0xf321, 0x7ea7, 0xf2f0,
+  0x7e9d, 0xf2bf, 0x7e92, 0xf28e, 0x7e88, 0xf25c, 0x7e7d, 0xf22b,
+  0x7e72, 0xf1fa, 0x7e67, 0xf1c9, 0x7e5c, 0xf198, 0x7e50, 0xf167,
+  0x7e45, 0xf136, 0x7e39, 0xf105, 0x7e2d, 0xf0d5, 0x7e21, 0xf0a4,
+  0x7e15, 0xf073, 0x7e09, 0xf042, 0x7dfc, 0xf012, 0x7df0, 0xefe1,
+  0x7de3, 0xefb0, 0x7dd6, 0xef80, 0x7dc9, 0xef4f, 0x7dbc, 0xef1f,
+  0x7daf, 0xeeee, 0x7da1, 0xeebe, 0x7d93, 0xee8d, 0x7d86, 0xee5d,
+  0x7d78, 0xee2d, 0x7d6a, 0xedfc, 0x7d5b, 0xedcc, 0x7d4d, 0xed9c,
+  0x7d3f, 0xed6c, 0x7d30, 0xed3c, 0x7d21, 0xed0c, 0x7d12, 0xecdc,
+  0x7d03, 0xecac, 0x7cf4, 0xec7c, 0x7ce4, 0xec4c, 0x7cd5, 0xec1c,
+  0x7cc5, 0xebed, 0x7cb5, 0xebbd, 0x7ca5, 0xeb8d, 0x7c95, 0xeb5e,
+  0x7c85, 0xeb2e, 0x7c74, 0xeaff, 0x7c64, 0xeacf, 0x7c53, 0xeaa0,
+  0x7c42, 0xea70, 0x7c31, 0xea41, 0x7c20, 0xea12, 0x7c0f, 0xe9e3,
+  0x7bfd, 0xe9b4, 0x7bec, 0xe984, 0x7bda, 0xe955, 0x7bc8, 0xe926,
+  0x7bb6, 0xe8f7, 0x7ba4, 0xe8c9, 0x7b92, 0xe89a, 0x7b7f, 0xe86b,
+  0x7b6d, 0xe83c, 0x7b5a, 0xe80e, 0x7b47, 0xe7df, 0x7b34, 0xe7b1,
+  0x7b21, 0xe782, 0x7b0e, 0xe754, 0x7afa, 0xe725, 0x7ae6, 0xe6f7,
+  0x7ad3, 0xe6c9, 0x7abf, 0xe69b, 0x7aab, 0xe66d, 0x7a97, 0xe63f,
+  0x7a82, 0xe611, 0x7a6e, 0xe5e3, 0x7a59, 0xe5b5, 0x7a45, 0xe587,
+  0x7a30, 0xe559, 0x7a1b, 0xe52c, 0x7a06, 0xe4fe, 0x79f0, 0xe4d0,
+  0x79db, 0xe4a3, 0x79c5, 0xe476, 0x79b0, 0xe448, 0x799a, 0xe41b,
+  0x7984, 0xe3ee, 0x796e, 0xe3c1, 0x7958, 0xe394, 0x7941, 0xe367,
+  0x792b, 0xe33a, 0x7914, 0xe30d, 0x78fd, 0xe2e0, 0x78e6, 0xe2b3,
+  0x78cf, 0xe287, 0x78b8, 0xe25a, 0x78a1, 0xe22d, 0x7889, 0xe201,
+  0x7871, 0xe1d5, 0x785a, 0xe1a8, 0x7842, 0xe17c, 0x782a, 0xe150,
+  0x7812, 0xe124, 0x77f9, 0xe0f8, 0x77e1, 0xe0cc, 0x77c8, 0xe0a0,
+  0x77b0, 0xe074, 0x7797, 0xe049, 0x777e, 0xe01d, 0x7765, 0xdff1,
+  0x774b, 0xdfc6, 0x7732, 0xdf9b, 0x7718, 0xdf6f, 0x76ff, 0xdf44,
+  0x76e5, 0xdf19, 0x76cb, 0xdeee, 0x76b1, 0xdec3, 0x7697, 0xde98,
+  0x767d, 0xde6d, 0x7662, 0xde42, 0x7648, 0xde18, 0x762d, 0xdded,
+  0x7612, 0xddc3, 0x75f7, 0xdd98, 0x75dc, 0xdd6e, 0x75c1, 0xdd44,
+  0x75a5, 0xdd19, 0x758a, 0xdcef, 0x756e, 0xdcc5, 0x7553, 0xdc9b,
+  0x7537, 0xdc72, 0x751b, 0xdc48, 0x74ff, 0xdc1e, 0x74e2, 0xdbf5,
+  0x74c6, 0xdbcb, 0x74aa, 0xdba2, 0x748d, 0xdb78, 0x7470, 0xdb4f,
+  0x7453, 0xdb26, 0x7436, 0xdafd, 0x7419, 0xdad4, 0x73fc, 0xdaab,
+  0x73df, 0xda82, 0x73c1, 0xda5a, 0x73a3, 0xda31, 0x7386, 0xda08,
+  0x7368, 0xd9e0, 0x734a, 0xd9b8, 0x732c, 0xd98f, 0x730d, 0xd967,
+  0x72ef, 0xd93f, 0x72d0, 0xd917, 0x72b2, 0xd8ef, 0x7293, 0xd8c8,
+  0x7274, 0xd8a0, 0x7255, 0xd878, 0x7236, 0xd851, 0x7217, 0xd82a,
+  0x71f8, 0xd802, 0x71d8, 0xd7db, 0x71b9, 0xd7b4, 0x7199, 0xd78d,
+  0x7179, 0xd766, 0x7159, 0xd73f, 0x7139, 0xd719, 0x7119, 0xd6f2,
+  0x70f9, 0xd6cb, 0x70d8, 0xd6a5, 0x70b8, 0xd67f, 0x7097, 0xd659,
+  0x7076, 0xd632, 0x7055, 0xd60c, 0x7034, 0xd5e6, 0x7013, 0xd5c1,
+  0x6ff2, 0xd59b, 0x6fd0, 0xd575, 0x6faf, 0xd550, 0x6f8d, 0xd52a,
+  0x6f6c, 0xd505, 0x6f4a, 0xd4e0, 0x6f28, 0xd4bb, 0x6f06, 0xd496,
+  0x6ee4, 0xd471, 0x6ec2, 0xd44c, 0x6e9f, 0xd428, 0x6e7d, 0xd403,
+  0x6e5a, 0xd3df, 0x6e37, 0xd3ba, 0x6e15, 0xd396, 0x6df2, 0xd372,
+  0x6dcf, 0xd34e, 0x6dab, 0xd32a, 0x6d88, 0xd306, 0x6d65, 0xd2e2,
+  0x6d41, 0xd2bf, 0x6d1e, 0xd29b, 0x6cfa, 0xd278, 0x6cd6, 0xd255,
+  0x6cb2, 0xd231, 0x6c8e, 0xd20e, 0x6c6a, 0xd1eb, 0x6c46, 0xd1c9,
+  0x6c21, 0xd1a6, 0x6bfd, 0xd183, 0x6bd8, 0xd161, 0x6bb4, 0xd13e,
+  0x6b8f, 0xd11c, 0x6b6a, 0xd0fa, 0x6b45, 0xd0d8, 0x6b20, 0xd0b6,
+  0x6afb, 0xd094, 0x6ad6, 0xd073, 0x6ab0, 0xd051, 0x6a8b, 0xd030,
+  0x6a65, 0xd00e, 0x6a3f, 0xcfed, 0x6a1a, 0xcfcc, 0x69f4, 0xcfab,
+  0x69ce, 0xcf8a, 0x69a7, 0xcf69, 0x6981, 0xcf48, 0x695b, 0xcf28,
+  0x6935, 0xcf07, 0x690e, 0xcee7, 0x68e7, 0xcec7, 0x68c1, 0xcea7,
+  0x689a, 0xce87, 0x6873, 0xce67, 0x684c, 0xce47, 0x6825, 0xce28,
+  0x67fe, 0xce08, 0x67d6, 0xcde9, 0x67af, 0xcdca, 0x6788, 0xcdab,
+  0x6760, 0xcd8c, 0x6738, 0xcd6d, 0x6711, 0xcd4e, 0x66e9, 0xcd30,
+  0x66c1, 0xcd11, 0x6699, 0xccf3, 0x6671, 0xccd4, 0x6648, 0xccb6,
+  0x6620, 0xcc98, 0x65f8, 0xcc7a, 0x65cf, 0xcc5d, 0x65a6, 0xcc3f,
+  0x657e, 0xcc21, 0x6555, 0xcc04, 0x652c, 0xcbe7, 0x6503, 0xcbca,
+  0x64da, 0xcbad, 0x64b1, 0xcb90, 0x6488, 0xcb73, 0x645e, 0xcb56,
+  0x6435, 0xcb3a, 0x640b, 0xcb1e, 0x63e2, 0xcb01, 0x63b8, 0xcae5,
+  0x638e, 0xcac9, 0x6365, 0xcaad, 0x633b, 0xca92, 0x6311, 0xca76,
+  0x62e7, 0xca5b, 0x62bc, 0xca3f, 0x6292, 0xca24, 0x6268, 0xca09,
+  0x623d, 0xc9ee, 0x6213, 0xc9d3, 0x61e8, 0xc9b8, 0x61be, 0xc99e,
+  0x6193, 0xc983, 0x6168, 0xc969, 0x613d, 0xc94f, 0x6112, 0xc935,
+  0x60e7, 0xc91b, 0x60bc, 0xc901, 0x6091, 0xc8e8, 0x6065, 0xc8ce,
+  0x603a, 0xc8b5, 0x600f, 0xc89b, 0x5fe3, 0xc882, 0x5fb7, 0xc869,
+  0x5f8c, 0xc850, 0x5f60, 0xc838, 0x5f34, 0xc81f, 0x5f08, 0xc807,
+  0x5edc, 0xc7ee, 0x5eb0, 0xc7d6, 0x5e84, 0xc7be, 0x5e58, 0xc7a6,
+  0x5e2b, 0xc78f, 0x5dff, 0xc777, 0x5dd3, 0xc75f, 0x5da6, 0xc748,
+  0x5d79, 0xc731, 0x5d4d, 0xc71a, 0x5d20, 0xc703, 0x5cf3, 0xc6ec,
+  0x5cc6, 0xc6d5, 0x5c99, 0xc6bf, 0x5c6c, 0xc6a8, 0x5c3f, 0xc692,
+  0x5c12, 0xc67c, 0x5be5, 0xc666, 0x5bb8, 0xc650, 0x5b8a, 0xc63b,
+  0x5b5d, 0xc625, 0x5b30, 0xc610, 0x5b02, 0xc5fa, 0x5ad4, 0xc5e5,
+  0x5aa7, 0xc5d0, 0x5a79, 0xc5bb, 0x5a4b, 0xc5a7, 0x5a1d, 0xc592,
+  0x59ef, 0xc57e, 0x59c1, 0xc569, 0x5993, 0xc555, 0x5965, 0xc541,
+  0x5937, 0xc52d, 0x5909, 0xc51a, 0x58db, 0xc506, 0x58ac, 0xc4f2,
+  0x587e, 0xc4df, 0x584f, 0xc4cc, 0x5821, 0xc4b9, 0x57f2, 0xc4a6,
+  0x57c4, 0xc493, 0x5795, 0xc481, 0x5766, 0xc46e, 0x5737, 0xc45c,
+  0x5709, 0xc44a, 0x56da, 0xc438, 0x56ab, 0xc426, 0x567c, 0xc414,
+  0x564c, 0xc403, 0x561d, 0xc3f1, 0x55ee, 0xc3e0, 0x55bf, 0xc3cf,
+  0x5590, 0xc3be, 0x5560, 0xc3ad, 0x5531, 0xc39c, 0x5501, 0xc38c,
+  0x54d2, 0xc37b, 0x54a2, 0xc36b, 0x5473, 0xc35b, 0x5443, 0xc34b,
+  0x5413, 0xc33b, 0x53e4, 0xc32b, 0x53b4, 0xc31c, 0x5384, 0xc30c,
+  0x5354, 0xc2fd, 0x5324, 0xc2ee, 0x52f4, 0xc2df, 0x52c4, 0xc2d0,
+  0x5294, 0xc2c1, 0x5264, 0xc2b3, 0x5234, 0xc2a5, 0x5204, 0xc296,
+  0x51d3, 0xc288, 0x51a3, 0xc27a, 0x5173, 0xc26d, 0x5142, 0xc25f,
+  0x5112, 0xc251, 0x50e1, 0xc244, 0x50b1, 0xc237, 0x5080, 0xc22a,
+  0x5050, 0xc21d, 0x501f, 0xc210, 0x4fee, 0xc204, 0x4fbe, 0xc1f7,
+  0x4f8d, 0xc1eb, 0x4f5c, 0xc1df, 0x4f2b, 0xc1d3, 0x4efb, 0xc1c7,
+  0x4eca, 0xc1bb, 0x4e99, 0xc1b0, 0x4e68, 0xc1a4, 0x4e37, 0xc199,
+  0x4e06, 0xc18e, 0x4dd5, 0xc183, 0x4da4, 0xc178, 0x4d72, 0xc16e,
+  0x4d41, 0xc163, 0x4d10, 0xc159, 0x4cdf, 0xc14f, 0x4cae, 0xc145,
+  0x4c7c, 0xc13b, 0x4c4b, 0xc131, 0x4c1a, 0xc128, 0x4be8, 0xc11e,
+  0x4bb7, 0xc115, 0x4b85, 0xc10c, 0x4b54, 0xc103, 0x4b23, 0xc0fa,
+  0x4af1, 0xc0f1, 0x4ac0, 0xc0e9, 0x4a8e, 0xc0e0, 0x4a5c, 0xc0d8,
+  0x4a2b, 0xc0d0, 0x49f9, 0xc0c8, 0x49c7, 0xc0c0, 0x4996, 0xc0b9,
+  0x4964, 0xc0b1, 0x4932, 0xc0aa, 0x4901, 0xc0a3, 0x48cf, 0xc09c,
+  0x489d, 0xc095, 0x486b, 0xc08e, 0x4839, 0xc088, 0x4807, 0xc081,
+  0x47d6, 0xc07b, 0x47a4, 0xc075, 0x4772, 0xc06f, 0x4740, 0xc069,
+  0x470e, 0xc064, 0x46dc, 0xc05e, 0x46aa, 0xc059, 0x4678, 0xc054,
+  0x4646, 0xc04f, 0x4614, 0xc04a, 0x45e2, 0xc045, 0x45b0, 0xc041,
+  0x457e, 0xc03c, 0x454c, 0xc038, 0x451a, 0xc034, 0x44e7, 0xc030,
+  0x44b5, 0xc02c, 0x4483, 0xc029, 0x4451, 0xc025, 0x441f, 0xc022,
+  0x43ed, 0xc01f, 0x43bb, 0xc01c, 0x4388, 0xc019, 0x4356, 0xc016,
+  0x4324, 0xc014, 0x42f2, 0xc011, 0x42c0, 0xc00f, 0x428d, 0xc00d,
+  0x425b, 0xc00b, 0x4229, 0xc009, 0x41f7, 0xc008, 0x41c4, 0xc006,
+  0x4192, 0xc005, 0x4160, 0xc004, 0x412e, 0xc003, 0x40fb, 0xc002,
+  0x40c9, 0xc001, 0x4097, 0xc001, 0x4065, 0xc000, 0x4032, 0xc000
+};
+
+/**   
+* @brief  Initialization function for the Q15 RFFT/RIFFT.  
+* @param[in, out] *S             points to an instance of the Q15 RFFT/RIFFT structure.  
+* @param[in]      *S_CFFT        points to an instance of the Q15 CFFT/CIFFT structure.  
+* @param[in]      fftLenReal     length of the FFT.  
+* @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.  
+* @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.  
+*   
+* \par Description:  
+* \par  
+* The parameter fftLenReal	Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.   
+* \par   
+* The parameter ifftFlagR controls whether a forward or inverse transform is computed.   
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.   
+* \par   
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.  
+* \par   
+* This function also initializes Twiddle factor table.    
+*/
+
+arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag)
+{
+
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialize the Real FFT length */
+  S->fftLenReal = (uint16_t) fftLenReal;
+
+  /*  Initialize the Complex FFT length */
+  S->fftLenBy2 = (uint16_t) fftLenReal / 2u;
+
+  /*  Initialize the Twiddle coefficientA pointer */
+  S->pTwiddleAReal = (q15_t *) realCoefAQ15;
+
+  /*  Initialize the Twiddle coefficientB pointer */
+  S->pTwiddleBReal = (q15_t *) realCoefBQ15;
+
+  /*  Initialize the Flag for selection of RFFT or RIFFT */
+  S->ifftFlagR = (uint8_t) ifftFlagR;
+
+  /*  Initialize the Flag for calculation Bit reversal or not */
+  S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+  /*  Initialization of coef modifier depending on the FFT length */
+  switch (S->fftLenReal)
+  {
+  case 2048u:
+    S->twidCoefRModifier = 1u;
+    break;
+  case 512u:
+    S->twidCoefRModifier = 4u;
+    break;
+  case 128u:
+    S->twidCoefRModifier = 16u;
+    break;
+  default:
+    /*  Reporting argument error if rfftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  /* Init Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  if(S->ifftFlagR)
+  {
+    /* Initializes the CIFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_q15(S->pCfft, S->fftLenBy2, 1u, 1u);
+  }
+  else
+  {
+    /* Initializes the CFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_q15(S->pCfft, S->fftLenBy2, 0u, 1u);
+  }
+
+  /* return the status of RFFT Init function */
+  return (status);
+
+}
+
+  /**   
+   * @} end of RFFT_RIFFT group   
+   */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c
new file mode 100644
index 000000000..cabb994c2
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c
@@ -0,0 +1,681 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_rfft_init_q31.c   
+*   
+* Description:	RFFT & RIFFT Q31 initialisation function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup RFFT_RIFFT   
+ * @{   
+ */
+
+/**   
+* \par   
+* Generation floating point realCoefAQ31 array:   
+* \par   
+* n = 1024   
+* 
for (i = 0; i < n; i++)   
+* {   
+*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));   
+*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+* }
   
+* \par   
+* Convert to fixed point Q31 format   
+*     round(pATable[i] * pow(2, 31))   
+*/
+
+
+const q31_t realCoefAQ31[1024] = {
+  0x40000000, 0xc0000000, 0x3f9b783c, 0xc0004ef5,
+  0x3f36f170, 0xc0013bd3, 0x3ed26c94, 0xc002c697,
+  0x3e6deaa1, 0xc004ef3f, 0x3e096c8d, 0xc007b5c4,
+  0x3da4f351, 0xc00b1a20, 0x3d407fe6, 0xc00f1c4a,
+  0x3cdc1342, 0xc013bc39, 0x3c77ae5e, 0xc018f9e1,
+  0x3c135231, 0xc01ed535, 0x3baeffb3, 0xc0254e27,
+  0x3b4ab7db, 0xc02c64a6, 0x3ae67ba2, 0xc03418a2,
+  0x3a824bfd, 0xc03c6a07, 0x3a1e29e5, 0xc04558c0,
+  0x39ba1651, 0xc04ee4b8, 0x39561237, 0xc0590dd8,
+  0x38f21e8e, 0xc063d405, 0x388e3c4d, 0xc06f3726,
+  0x382a6c6a, 0xc07b371e, 0x37c6afdc, 0xc087d3d0,
+  0x37630799, 0xc0950d1d, 0x36ff7496, 0xc0a2e2e3,
+  0x369bf7c9, 0xc0b15502, 0x36389228, 0xc0c06355,
+  0x35d544a7, 0xc0d00db6, 0x3572103d, 0xc0e05401,
+  0x350ef5de, 0xc0f1360b, 0x34abf67e, 0xc102b3ac,
+  0x34491311, 0xc114ccb9, 0x33e64c8c, 0xc1278104,
+  0x3383a3e2, 0xc13ad060, 0x33211a07, 0xc14eba9d,
+  0x32beafed, 0xc1633f8a, 0x325c6688, 0xc1785ef4,
+  0x31fa3ecb, 0xc18e18a7, 0x319839a6, 0xc1a46c6e,
+  0x3136580d, 0xc1bb5a11, 0x30d49af1, 0xc1d2e158,
+  0x30730342, 0xc1eb0209, 0x301191f3, 0xc203bbe8,
+  0x2fb047f2, 0xc21d0eb8, 0x2f4f2630, 0xc236fa3b,
+  0x2eee2d9d, 0xc2517e31, 0x2e8d5f29, 0xc26c9a58,
+  0x2e2cbbc1, 0xc2884e6e, 0x2dcc4454, 0xc2a49a2e,
+  0x2d6bf9d1, 0xc2c17d52, 0x2d0bdd25, 0xc2def794,
+  0x2cabef3d, 0xc2fd08a9, 0x2c4c3106, 0xc31bb049,
+  0x2beca36c, 0xc33aee27, 0x2b8d475b, 0xc35ac1f7,
+  0x2b2e1dbe, 0xc37b2b6a, 0x2acf277f, 0xc39c2a2f,
+  0x2a70658a, 0xc3bdbdf6, 0x2a11d8c8, 0xc3dfe66c,
+  0x29b38223, 0xc402a33c, 0x29556282, 0xc425f410,
+  0x28f77acf, 0xc449d892, 0x2899cbf1, 0xc46e5069,
+  0x283c56cf, 0xc4935b3c, 0x27df1c50, 0xc4b8f8ad,
+  0x27821d59, 0xc4df2862, 0x27255ad1, 0xc505e9fb,
+  0x26c8d59c, 0xc52d3d18, 0x266c8e9f, 0xc555215a,
+  0x261086bc, 0xc57d965d, 0x25b4bed8, 0xc5a69bbe,
+  0x255937d5, 0xc5d03118, 0x24fdf294, 0xc5fa5603,
+  0x24a2eff6, 0xc6250a18, 0x244830dd, 0xc6504ced,
+  0x23edb628, 0xc67c1e18, 0x239380b6, 0xc6a87d2d,
+  0x23399167, 0xc6d569be, 0x22dfe917, 0xc702e35c,
+  0x228688a4, 0xc730e997, 0x222d70eb, 0xc75f7bfe,
+  0x21d4a2c8, 0xc78e9a1d, 0x217c1f15, 0xc7be4381,
+  0x2123e6ad, 0xc7ee77b3, 0x20cbfa6a, 0xc81f363d,
+  0x20745b24, 0xc8507ea7, 0x201d09b4, 0xc8825077,
+  0x1fc606f1, 0xc8b4ab32, 0x1f6f53b3, 0xc8e78e5b,
+  0x1f18f0ce, 0xc91af976, 0x1ec2df18, 0xc94eec03,
+  0x1e6d1f65, 0xc9836582, 0x1e17b28a, 0xc9b86572,
+  0x1dc29958, 0xc9edeb50, 0x1d6dd4a2, 0xca23f698,
+  0x1d196538, 0xca5a86c4, 0x1cc54bec, 0xca919b4e,
+  0x1c71898d, 0xcac933ae, 0x1c1e1ee9, 0xcb014f5b,
+  0x1bcb0cce, 0xcb39edca, 0x1b785409, 0xcb730e70,
+  0x1b25f566, 0xcbacb0bf, 0x1ad3f1b1, 0xcbe6d42b,
+  0x1a8249b4, 0xcc217822, 0x1a30fe38, 0xcc5c9c14,
+  0x19e01006, 0xcc983f70, 0x198f7fe6, 0xccd461a2,
+  0x193f4e9e, 0xcd110216, 0x18ef7cf4, 0xcd4e2037,
+  0x18a00bae, 0xcd8bbb6d, 0x1850fb8e, 0xcdc9d320,
+  0x18024d59, 0xce0866b8, 0x17b401d1, 0xce47759a,
+  0x176619b6, 0xce86ff2a, 0x171895c9, 0xcec702cb,
+  0x16cb76c9, 0xcf077fe1, 0x167ebd74, 0xcf4875ca,
+  0x16326a88, 0xcf89e3e8, 0x15e67ec1, 0xcfcbc999,
+  0x159afadb, 0xd00e2639, 0x154fdf8f, 0xd050f926,
+  0x15052d97, 0xd09441bb, 0x14bae5ab, 0xd0d7ff51,
+  0x14710883, 0xd11c3142, 0x142796d5, 0xd160d6e5,
+  0x13de9156, 0xd1a5ef90, 0x1395f8ba, 0xd1eb7a9a,
+  0x134dcdb4, 0xd2317756, 0x130610f7, 0xd277e518,
+  0x12bec333, 0xd2bec333, 0x1277e518, 0xd30610f7,
+  0x12317756, 0xd34dcdb4, 0x11eb7a9a, 0xd395f8ba,
+  0x11a5ef90, 0xd3de9156, 0x1160d6e5, 0xd42796d5,
+  0x111c3142, 0xd4710883, 0x10d7ff51, 0xd4bae5ab,
+  0x109441bb, 0xd5052d97, 0x1050f926, 0xd54fdf8f,
+  0x100e2639, 0xd59afadb, 0xfcbc999, 0xd5e67ec1,
+  0xf89e3e8, 0xd6326a88, 0xf4875ca, 0xd67ebd74,
+  0xf077fe1, 0xd6cb76c9, 0xec702cb, 0xd71895c9,
+  0xe86ff2a, 0xd76619b6, 0xe47759a, 0xd7b401d1,
+  0xe0866b8, 0xd8024d59, 0xdc9d320, 0xd850fb8e,
+  0xd8bbb6d, 0xd8a00bae, 0xd4e2037, 0xd8ef7cf4,
+  0xd110216, 0xd93f4e9e, 0xcd461a2, 0xd98f7fe6,
+  0xc983f70, 0xd9e01006, 0xc5c9c14, 0xda30fe38,
+  0xc217822, 0xda8249b4, 0xbe6d42b, 0xdad3f1b1,
+  0xbacb0bf, 0xdb25f566, 0xb730e70, 0xdb785409,
+  0xb39edca, 0xdbcb0cce, 0xb014f5b, 0xdc1e1ee9,
+  0xac933ae, 0xdc71898d, 0xa919b4e, 0xdcc54bec,
+  0xa5a86c4, 0xdd196538, 0xa23f698, 0xdd6dd4a2,
+  0x9edeb50, 0xddc29958, 0x9b86572, 0xde17b28a,
+  0x9836582, 0xde6d1f65, 0x94eec03, 0xdec2df18,
+  0x91af976, 0xdf18f0ce, 0x8e78e5b, 0xdf6f53b3,
+  0x8b4ab32, 0xdfc606f1, 0x8825077, 0xe01d09b4,
+  0x8507ea7, 0xe0745b24, 0x81f363d, 0xe0cbfa6a,
+  0x7ee77b3, 0xe123e6ad, 0x7be4381, 0xe17c1f15,
+  0x78e9a1d, 0xe1d4a2c8, 0x75f7bfe, 0xe22d70eb,
+  0x730e997, 0xe28688a4, 0x702e35c, 0xe2dfe917,
+  0x6d569be, 0xe3399167, 0x6a87d2d, 0xe39380b6,
+  0x67c1e18, 0xe3edb628, 0x6504ced, 0xe44830dd,
+  0x6250a18, 0xe4a2eff6, 0x5fa5603, 0xe4fdf294,
+  0x5d03118, 0xe55937d5, 0x5a69bbe, 0xe5b4bed8,
+  0x57d965d, 0xe61086bc, 0x555215a, 0xe66c8e9f,
+  0x52d3d18, 0xe6c8d59c, 0x505e9fb, 0xe7255ad1,
+  0x4df2862, 0xe7821d59, 0x4b8f8ad, 0xe7df1c50,
+  0x4935b3c, 0xe83c56cf, 0x46e5069, 0xe899cbf1,
+  0x449d892, 0xe8f77acf, 0x425f410, 0xe9556282,
+  0x402a33c, 0xe9b38223, 0x3dfe66c, 0xea11d8c8,
+  0x3bdbdf6, 0xea70658a, 0x39c2a2f, 0xeacf277f,
+  0x37b2b6a, 0xeb2e1dbe, 0x35ac1f7, 0xeb8d475b,
+  0x33aee27, 0xebeca36c, 0x31bb049, 0xec4c3106,
+  0x2fd08a9, 0xecabef3d, 0x2def794, 0xed0bdd25,
+  0x2c17d52, 0xed6bf9d1, 0x2a49a2e, 0xedcc4454,
+  0x2884e6e, 0xee2cbbc1, 0x26c9a58, 0xee8d5f29,
+  0x2517e31, 0xeeee2d9d, 0x236fa3b, 0xef4f2630,
+  0x21d0eb8, 0xefb047f2, 0x203bbe8, 0xf01191f3,
+  0x1eb0209, 0xf0730342, 0x1d2e158, 0xf0d49af1,
+  0x1bb5a11, 0xf136580d, 0x1a46c6e, 0xf19839a6,
+  0x18e18a7, 0xf1fa3ecb, 0x1785ef4, 0xf25c6688,
+  0x1633f8a, 0xf2beafed, 0x14eba9d, 0xf3211a07,
+  0x13ad060, 0xf383a3e2, 0x1278104, 0xf3e64c8c,
+  0x114ccb9, 0xf4491311, 0x102b3ac, 0xf4abf67e,
+  0xf1360b, 0xf50ef5de, 0xe05401, 0xf572103d,
+  0xd00db6, 0xf5d544a7, 0xc06355, 0xf6389228,
+  0xb15502, 0xf69bf7c9, 0xa2e2e3, 0xf6ff7496,
+  0x950d1d, 0xf7630799, 0x87d3d0, 0xf7c6afdc,
+  0x7b371e, 0xf82a6c6a, 0x6f3726, 0xf88e3c4d,
+  0x63d405, 0xf8f21e8e, 0x590dd8, 0xf9561237,
+  0x4ee4b8, 0xf9ba1651, 0x4558c0, 0xfa1e29e5,
+  0x3c6a07, 0xfa824bfd, 0x3418a2, 0xfae67ba2,
+  0x2c64a6, 0xfb4ab7db, 0x254e27, 0xfbaeffb3,
+  0x1ed535, 0xfc135231, 0x18f9e1, 0xfc77ae5e,
+  0x13bc39, 0xfcdc1342, 0xf1c4a, 0xfd407fe6,
+  0xb1a20, 0xfda4f351, 0x7b5c4, 0xfe096c8d,
+  0x4ef3f, 0xfe6deaa1, 0x2c697, 0xfed26c94,
+  0x13bd3, 0xff36f170, 0x4ef5, 0xff9b783c,
+  0x0, 0x0, 0x4ef5, 0x6487c4,
+  0x13bd3, 0xc90e90, 0x2c697, 0x12d936c,
+  0x4ef3f, 0x192155f, 0x7b5c4, 0x1f69373,
+  0xb1a20, 0x25b0caf, 0xf1c4a, 0x2bf801a,
+  0x13bc39, 0x323ecbe, 0x18f9e1, 0x38851a2,
+  0x1ed535, 0x3ecadcf, 0x254e27, 0x451004d,
+  0x2c64a6, 0x4b54825, 0x3418a2, 0x519845e,
+  0x3c6a07, 0x57db403, 0x4558c0, 0x5e1d61b,
+  0x4ee4b8, 0x645e9af, 0x590dd8, 0x6a9edc9,
+  0x63d405, 0x70de172, 0x6f3726, 0x771c3b3,
+  0x7b371e, 0x7d59396, 0x87d3d0, 0x8395024,
+  0x950d1d, 0x89cf867, 0xa2e2e3, 0x9008b6a,
+  0xb15502, 0x9640837, 0xc06355, 0x9c76dd8,
+  0xd00db6, 0xa2abb59, 0xe05401, 0xa8defc3,
+  0xf1360b, 0xaf10a22, 0x102b3ac, 0xb540982,
+  0x114ccb9, 0xbb6ecef, 0x1278104, 0xc19b374,
+  0x13ad060, 0xc7c5c1e, 0x14eba9d, 0xcdee5f9,
+  0x1633f8a, 0xd415013, 0x1785ef4, 0xda39978,
+  0x18e18a7, 0xe05c135, 0x1a46c6e, 0xe67c65a,
+  0x1bb5a11, 0xec9a7f3, 0x1d2e158, 0xf2b650f,
+  0x1eb0209, 0xf8cfcbe, 0x203bbe8, 0xfee6e0d,
+  0x21d0eb8, 0x104fb80e, 0x236fa3b, 0x10b0d9d0,
+  0x2517e31, 0x1111d263, 0x26c9a58, 0x1172a0d7,
+  0x2884e6e, 0x11d3443f, 0x2a49a2e, 0x1233bbac,
+  0x2c17d52, 0x1294062f, 0x2def794, 0x12f422db,
+  0x2fd08a9, 0x135410c3, 0x31bb049, 0x13b3cefa,
+  0x33aee27, 0x14135c94, 0x35ac1f7, 0x1472b8a5,
+  0x37b2b6a, 0x14d1e242, 0x39c2a2f, 0x1530d881,
+  0x3bdbdf6, 0x158f9a76, 0x3dfe66c, 0x15ee2738,
+  0x402a33c, 0x164c7ddd, 0x425f410, 0x16aa9d7e,
+  0x449d892, 0x17088531, 0x46e5069, 0x1766340f,
+  0x4935b3c, 0x17c3a931, 0x4b8f8ad, 0x1820e3b0,
+  0x4df2862, 0x187de2a7, 0x505e9fb, 0x18daa52f,
+  0x52d3d18, 0x19372a64, 0x555215a, 0x19937161,
+  0x57d965d, 0x19ef7944, 0x5a69bbe, 0x1a4b4128,
+  0x5d03118, 0x1aa6c82b, 0x5fa5603, 0x1b020d6c,
+  0x6250a18, 0x1b5d100a, 0x6504ced, 0x1bb7cf23,
+  0x67c1e18, 0x1c1249d8, 0x6a87d2d, 0x1c6c7f4a,
+  0x6d569be, 0x1cc66e99, 0x702e35c, 0x1d2016e9,
+  0x730e997, 0x1d79775c, 0x75f7bfe, 0x1dd28f15,
+  0x78e9a1d, 0x1e2b5d38, 0x7be4381, 0x1e83e0eb,
+  0x7ee77b3, 0x1edc1953, 0x81f363d, 0x1f340596,
+  0x8507ea7, 0x1f8ba4dc, 0x8825077, 0x1fe2f64c,
+  0x8b4ab32, 0x2039f90f, 0x8e78e5b, 0x2090ac4d,
+  0x91af976, 0x20e70f32, 0x94eec03, 0x213d20e8,
+  0x9836582, 0x2192e09b, 0x9b86572, 0x21e84d76,
+  0x9edeb50, 0x223d66a8, 0xa23f698, 0x22922b5e,
+  0xa5a86c4, 0x22e69ac8, 0xa919b4e, 0x233ab414,
+  0xac933ae, 0x238e7673, 0xb014f5b, 0x23e1e117,
+  0xb39edca, 0x2434f332, 0xb730e70, 0x2487abf7,
+  0xbacb0bf, 0x24da0a9a, 0xbe6d42b, 0x252c0e4f,
+  0xc217822, 0x257db64c, 0xc5c9c14, 0x25cf01c8,
+  0xc983f70, 0x261feffa, 0xcd461a2, 0x2670801a,
+  0xd110216, 0x26c0b162, 0xd4e2037, 0x2710830c,
+  0xd8bbb6d, 0x275ff452, 0xdc9d320, 0x27af0472,
+  0xe0866b8, 0x27fdb2a7, 0xe47759a, 0x284bfe2f,
+  0xe86ff2a, 0x2899e64a, 0xec702cb, 0x28e76a37,
+  0xf077fe1, 0x29348937, 0xf4875ca, 0x2981428c,
+  0xf89e3e8, 0x29cd9578, 0xfcbc999, 0x2a19813f,
+  0x100e2639, 0x2a650525, 0x1050f926, 0x2ab02071,
+  0x109441bb, 0x2afad269, 0x10d7ff51, 0x2b451a55,
+  0x111c3142, 0x2b8ef77d, 0x1160d6e5, 0x2bd8692b,
+  0x11a5ef90, 0x2c216eaa, 0x11eb7a9a, 0x2c6a0746,
+  0x12317756, 0x2cb2324c, 0x1277e518, 0x2cf9ef09,
+  0x12bec333, 0x2d413ccd, 0x130610f7, 0x2d881ae8,
+  0x134dcdb4, 0x2dce88aa, 0x1395f8ba, 0x2e148566,
+  0x13de9156, 0x2e5a1070, 0x142796d5, 0x2e9f291b,
+  0x14710883, 0x2ee3cebe, 0x14bae5ab, 0x2f2800af,
+  0x15052d97, 0x2f6bbe45, 0x154fdf8f, 0x2faf06da,
+  0x159afadb, 0x2ff1d9c7, 0x15e67ec1, 0x30343667,
+  0x16326a88, 0x30761c18, 0x167ebd74, 0x30b78a36,
+  0x16cb76c9, 0x30f8801f, 0x171895c9, 0x3138fd35,
+  0x176619b6, 0x317900d6, 0x17b401d1, 0x31b88a66,
+  0x18024d59, 0x31f79948, 0x1850fb8e, 0x32362ce0,
+  0x18a00bae, 0x32744493, 0x18ef7cf4, 0x32b1dfc9,
+  0x193f4e9e, 0x32eefdea, 0x198f7fe6, 0x332b9e5e,
+  0x19e01006, 0x3367c090, 0x1a30fe38, 0x33a363ec,
+  0x1a8249b4, 0x33de87de, 0x1ad3f1b1, 0x34192bd5,
+  0x1b25f566, 0x34534f41, 0x1b785409, 0x348cf190,
+  0x1bcb0cce, 0x34c61236, 0x1c1e1ee9, 0x34feb0a5,
+  0x1c71898d, 0x3536cc52, 0x1cc54bec, 0x356e64b2,
+  0x1d196538, 0x35a5793c, 0x1d6dd4a2, 0x35dc0968,
+  0x1dc29958, 0x361214b0, 0x1e17b28a, 0x36479a8e,
+  0x1e6d1f65, 0x367c9a7e, 0x1ec2df18, 0x36b113fd,
+  0x1f18f0ce, 0x36e5068a, 0x1f6f53b3, 0x371871a5,
+  0x1fc606f1, 0x374b54ce, 0x201d09b4, 0x377daf89,
+  0x20745b24, 0x37af8159, 0x20cbfa6a, 0x37e0c9c3,
+  0x2123e6ad, 0x3811884d, 0x217c1f15, 0x3841bc7f,
+  0x21d4a2c8, 0x387165e3, 0x222d70eb, 0x38a08402,
+  0x228688a4, 0x38cf1669, 0x22dfe917, 0x38fd1ca4,
+  0x23399167, 0x392a9642, 0x239380b6, 0x395782d3,
+  0x23edb628, 0x3983e1e8, 0x244830dd, 0x39afb313,
+  0x24a2eff6, 0x39daf5e8, 0x24fdf294, 0x3a05a9fd,
+  0x255937d5, 0x3a2fcee8, 0x25b4bed8, 0x3a596442,
+  0x261086bc, 0x3a8269a3, 0x266c8e9f, 0x3aaadea6,
+  0x26c8d59c, 0x3ad2c2e8, 0x27255ad1, 0x3afa1605,
+  0x27821d59, 0x3b20d79e, 0x27df1c50, 0x3b470753,
+  0x283c56cf, 0x3b6ca4c4, 0x2899cbf1, 0x3b91af97,
+  0x28f77acf, 0x3bb6276e, 0x29556282, 0x3bda0bf0,
+  0x29b38223, 0x3bfd5cc4, 0x2a11d8c8, 0x3c201994,
+  0x2a70658a, 0x3c42420a, 0x2acf277f, 0x3c63d5d1,
+  0x2b2e1dbe, 0x3c84d496, 0x2b8d475b, 0x3ca53e09,
+  0x2beca36c, 0x3cc511d9, 0x2c4c3106, 0x3ce44fb7,
+  0x2cabef3d, 0x3d02f757, 0x2d0bdd25, 0x3d21086c,
+  0x2d6bf9d1, 0x3d3e82ae, 0x2dcc4454, 0x3d5b65d2,
+  0x2e2cbbc1, 0x3d77b192, 0x2e8d5f29, 0x3d9365a8,
+  0x2eee2d9d, 0x3dae81cf, 0x2f4f2630, 0x3dc905c5,
+  0x2fb047f2, 0x3de2f148, 0x301191f3, 0x3dfc4418,
+  0x30730342, 0x3e14fdf7, 0x30d49af1, 0x3e2d1ea8,
+  0x3136580d, 0x3e44a5ef, 0x319839a6, 0x3e5b9392,
+  0x31fa3ecb, 0x3e71e759, 0x325c6688, 0x3e87a10c,
+  0x32beafed, 0x3e9cc076, 0x33211a07, 0x3eb14563,
+  0x3383a3e2, 0x3ec52fa0, 0x33e64c8c, 0x3ed87efc,
+  0x34491311, 0x3eeb3347, 0x34abf67e, 0x3efd4c54,
+  0x350ef5de, 0x3f0ec9f5, 0x3572103d, 0x3f1fabff,
+  0x35d544a7, 0x3f2ff24a, 0x36389228, 0x3f3f9cab,
+  0x369bf7c9, 0x3f4eaafe, 0x36ff7496, 0x3f5d1d1d,
+  0x37630799, 0x3f6af2e3, 0x37c6afdc, 0x3f782c30,
+  0x382a6c6a, 0x3f84c8e2, 0x388e3c4d, 0x3f90c8da,
+  0x38f21e8e, 0x3f9c2bfb, 0x39561237, 0x3fa6f228,
+  0x39ba1651, 0x3fb11b48, 0x3a1e29e5, 0x3fbaa740,
+  0x3a824bfd, 0x3fc395f9, 0x3ae67ba2, 0x3fcbe75e,
+  0x3b4ab7db, 0x3fd39b5a, 0x3baeffb3, 0x3fdab1d9,
+  0x3c135231, 0x3fe12acb, 0x3c77ae5e, 0x3fe7061f,
+  0x3cdc1342, 0x3fec43c7, 0x3d407fe6, 0x3ff0e3b6,
+  0x3da4f351, 0x3ff4e5e0, 0x3e096c8d, 0x3ff84a3c,
+  0x3e6deaa1, 0x3ffb10c1, 0x3ed26c94, 0x3ffd3969,
+  0x3f36f170, 0x3ffec42d, 0x3f9b783c, 0x3fffb10b
+};
+
+
+/**   
+* \par  
+* Generation of realCoefBQ31 array:   
+* \par   
+*  n = 512   
+* 
for (i = 0; i < n; i++)   
+* {   
+*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));   
+*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+* } 
   
+* \par   
+* Convert to fixed point Q31 format   
+*     round(pBTable[i] * pow(2, 31))   
+*   
+*/
+
+const q31_t realCoefBQ31[1024] = {
+  0x40000000, 0x40000000, 0x406487c4, 0x3fffb10b,
+  0x40c90e90, 0x3ffec42d, 0x412d936c, 0x3ffd3969,
+  0x4192155f, 0x3ffb10c1, 0x41f69373, 0x3ff84a3c,
+  0x425b0caf, 0x3ff4e5e0, 0x42bf801a, 0x3ff0e3b6,
+  0x4323ecbe, 0x3fec43c7, 0x438851a2, 0x3fe7061f,
+  0x43ecadcf, 0x3fe12acb, 0x4451004d, 0x3fdab1d9,
+  0x44b54825, 0x3fd39b5a, 0x4519845e, 0x3fcbe75e,
+  0x457db403, 0x3fc395f9, 0x45e1d61b, 0x3fbaa740,
+  0x4645e9af, 0x3fb11b48, 0x46a9edc9, 0x3fa6f228,
+  0x470de172, 0x3f9c2bfb, 0x4771c3b3, 0x3f90c8da,
+  0x47d59396, 0x3f84c8e2, 0x48395024, 0x3f782c30,
+  0x489cf867, 0x3f6af2e3, 0x49008b6a, 0x3f5d1d1d,
+  0x49640837, 0x3f4eaafe, 0x49c76dd8, 0x3f3f9cab,
+  0x4a2abb59, 0x3f2ff24a, 0x4a8defc3, 0x3f1fabff,
+  0x4af10a22, 0x3f0ec9f5, 0x4b540982, 0x3efd4c54,
+  0x4bb6ecef, 0x3eeb3347, 0x4c19b374, 0x3ed87efc,
+  0x4c7c5c1e, 0x3ec52fa0, 0x4cdee5f9, 0x3eb14563,
+  0x4d415013, 0x3e9cc076, 0x4da39978, 0x3e87a10c,
+  0x4e05c135, 0x3e71e759, 0x4e67c65a, 0x3e5b9392,
+  0x4ec9a7f3, 0x3e44a5ef, 0x4f2b650f, 0x3e2d1ea8,
+  0x4f8cfcbe, 0x3e14fdf7, 0x4fee6e0d, 0x3dfc4418,
+  0x504fb80e, 0x3de2f148, 0x50b0d9d0, 0x3dc905c5,
+  0x5111d263, 0x3dae81cf, 0x5172a0d7, 0x3d9365a8,
+  0x51d3443f, 0x3d77b192, 0x5233bbac, 0x3d5b65d2,
+  0x5294062f, 0x3d3e82ae, 0x52f422db, 0x3d21086c,
+  0x535410c3, 0x3d02f757, 0x53b3cefa, 0x3ce44fb7,
+  0x54135c94, 0x3cc511d9, 0x5472b8a5, 0x3ca53e09,
+  0x54d1e242, 0x3c84d496, 0x5530d881, 0x3c63d5d1,
+  0x558f9a76, 0x3c42420a, 0x55ee2738, 0x3c201994,
+  0x564c7ddd, 0x3bfd5cc4, 0x56aa9d7e, 0x3bda0bf0,
+  0x57088531, 0x3bb6276e, 0x5766340f, 0x3b91af97,
+  0x57c3a931, 0x3b6ca4c4, 0x5820e3b0, 0x3b470753,
+  0x587de2a7, 0x3b20d79e, 0x58daa52f, 0x3afa1605,
+  0x59372a64, 0x3ad2c2e8, 0x59937161, 0x3aaadea6,
+  0x59ef7944, 0x3a8269a3, 0x5a4b4128, 0x3a596442,
+  0x5aa6c82b, 0x3a2fcee8, 0x5b020d6c, 0x3a05a9fd,
+  0x5b5d100a, 0x39daf5e8, 0x5bb7cf23, 0x39afb313,
+  0x5c1249d8, 0x3983e1e8, 0x5c6c7f4a, 0x395782d3,
+  0x5cc66e99, 0x392a9642, 0x5d2016e9, 0x38fd1ca4,
+  0x5d79775c, 0x38cf1669, 0x5dd28f15, 0x38a08402,
+  0x5e2b5d38, 0x387165e3, 0x5e83e0eb, 0x3841bc7f,
+  0x5edc1953, 0x3811884d, 0x5f340596, 0x37e0c9c3,
+  0x5f8ba4dc, 0x37af8159, 0x5fe2f64c, 0x377daf89,
+  0x6039f90f, 0x374b54ce, 0x6090ac4d, 0x371871a5,
+  0x60e70f32, 0x36e5068a, 0x613d20e8, 0x36b113fd,
+  0x6192e09b, 0x367c9a7e, 0x61e84d76, 0x36479a8e,
+  0x623d66a8, 0x361214b0, 0x62922b5e, 0x35dc0968,
+  0x62e69ac8, 0x35a5793c, 0x633ab414, 0x356e64b2,
+  0x638e7673, 0x3536cc52, 0x63e1e117, 0x34feb0a5,
+  0x6434f332, 0x34c61236, 0x6487abf7, 0x348cf190,
+  0x64da0a9a, 0x34534f41, 0x652c0e4f, 0x34192bd5,
+  0x657db64c, 0x33de87de, 0x65cf01c8, 0x33a363ec,
+  0x661feffa, 0x3367c090, 0x6670801a, 0x332b9e5e,
+  0x66c0b162, 0x32eefdea, 0x6710830c, 0x32b1dfc9,
+  0x675ff452, 0x32744493, 0x67af0472, 0x32362ce0,
+  0x67fdb2a7, 0x31f79948, 0x684bfe2f, 0x31b88a66,
+  0x6899e64a, 0x317900d6, 0x68e76a37, 0x3138fd35,
+  0x69348937, 0x30f8801f, 0x6981428c, 0x30b78a36,
+  0x69cd9578, 0x30761c18, 0x6a19813f, 0x30343667,
+  0x6a650525, 0x2ff1d9c7, 0x6ab02071, 0x2faf06da,
+  0x6afad269, 0x2f6bbe45, 0x6b451a55, 0x2f2800af,
+  0x6b8ef77d, 0x2ee3cebe, 0x6bd8692b, 0x2e9f291b,
+  0x6c216eaa, 0x2e5a1070, 0x6c6a0746, 0x2e148566,
+  0x6cb2324c, 0x2dce88aa, 0x6cf9ef09, 0x2d881ae8,
+  0x6d413ccd, 0x2d413ccd, 0x6d881ae8, 0x2cf9ef09,
+  0x6dce88aa, 0x2cb2324c, 0x6e148566, 0x2c6a0746,
+  0x6e5a1070, 0x2c216eaa, 0x6e9f291b, 0x2bd8692b,
+  0x6ee3cebe, 0x2b8ef77d, 0x6f2800af, 0x2b451a55,
+  0x6f6bbe45, 0x2afad269, 0x6faf06da, 0x2ab02071,
+  0x6ff1d9c7, 0x2a650525, 0x70343667, 0x2a19813f,
+  0x70761c18, 0x29cd9578, 0x70b78a36, 0x2981428c,
+  0x70f8801f, 0x29348937, 0x7138fd35, 0x28e76a37,
+  0x717900d6, 0x2899e64a, 0x71b88a66, 0x284bfe2f,
+  0x71f79948, 0x27fdb2a7, 0x72362ce0, 0x27af0472,
+  0x72744493, 0x275ff452, 0x72b1dfc9, 0x2710830c,
+  0x72eefdea, 0x26c0b162, 0x732b9e5e, 0x2670801a,
+  0x7367c090, 0x261feffa, 0x73a363ec, 0x25cf01c8,
+  0x73de87de, 0x257db64c, 0x74192bd5, 0x252c0e4f,
+  0x74534f41, 0x24da0a9a, 0x748cf190, 0x2487abf7,
+  0x74c61236, 0x2434f332, 0x74feb0a5, 0x23e1e117,
+  0x7536cc52, 0x238e7673, 0x756e64b2, 0x233ab414,
+  0x75a5793c, 0x22e69ac8, 0x75dc0968, 0x22922b5e,
+  0x761214b0, 0x223d66a8, 0x76479a8e, 0x21e84d76,
+  0x767c9a7e, 0x2192e09b, 0x76b113fd, 0x213d20e8,
+  0x76e5068a, 0x20e70f32, 0x771871a5, 0x2090ac4d,
+  0x774b54ce, 0x2039f90f, 0x777daf89, 0x1fe2f64c,
+  0x77af8159, 0x1f8ba4dc, 0x77e0c9c3, 0x1f340596,
+  0x7811884d, 0x1edc1953, 0x7841bc7f, 0x1e83e0eb,
+  0x787165e3, 0x1e2b5d38, 0x78a08402, 0x1dd28f15,
+  0x78cf1669, 0x1d79775c, 0x78fd1ca4, 0x1d2016e9,
+  0x792a9642, 0x1cc66e99, 0x795782d3, 0x1c6c7f4a,
+  0x7983e1e8, 0x1c1249d8, 0x79afb313, 0x1bb7cf23,
+  0x79daf5e8, 0x1b5d100a, 0x7a05a9fd, 0x1b020d6c,
+  0x7a2fcee8, 0x1aa6c82b, 0x7a596442, 0x1a4b4128,
+  0x7a8269a3, 0x19ef7944, 0x7aaadea6, 0x19937161,
+  0x7ad2c2e8, 0x19372a64, 0x7afa1605, 0x18daa52f,
+  0x7b20d79e, 0x187de2a7, 0x7b470753, 0x1820e3b0,
+  0x7b6ca4c4, 0x17c3a931, 0x7b91af97, 0x1766340f,
+  0x7bb6276e, 0x17088531, 0x7bda0bf0, 0x16aa9d7e,
+  0x7bfd5cc4, 0x164c7ddd, 0x7c201994, 0x15ee2738,
+  0x7c42420a, 0x158f9a76, 0x7c63d5d1, 0x1530d881,
+  0x7c84d496, 0x14d1e242, 0x7ca53e09, 0x1472b8a5,
+  0x7cc511d9, 0x14135c94, 0x7ce44fb7, 0x13b3cefa,
+  0x7d02f757, 0x135410c3, 0x7d21086c, 0x12f422db,
+  0x7d3e82ae, 0x1294062f, 0x7d5b65d2, 0x1233bbac,
+  0x7d77b192, 0x11d3443f, 0x7d9365a8, 0x1172a0d7,
+  0x7dae81cf, 0x1111d263, 0x7dc905c5, 0x10b0d9d0,
+  0x7de2f148, 0x104fb80e, 0x7dfc4418, 0xfee6e0d,
+  0x7e14fdf7, 0xf8cfcbe, 0x7e2d1ea8, 0xf2b650f,
+  0x7e44a5ef, 0xec9a7f3, 0x7e5b9392, 0xe67c65a,
+  0x7e71e759, 0xe05c135, 0x7e87a10c, 0xda39978,
+  0x7e9cc076, 0xd415013, 0x7eb14563, 0xcdee5f9,
+  0x7ec52fa0, 0xc7c5c1e, 0x7ed87efc, 0xc19b374,
+  0x7eeb3347, 0xbb6ecef, 0x7efd4c54, 0xb540982,
+  0x7f0ec9f5, 0xaf10a22, 0x7f1fabff, 0xa8defc3,
+  0x7f2ff24a, 0xa2abb59, 0x7f3f9cab, 0x9c76dd8,
+  0x7f4eaafe, 0x9640837, 0x7f5d1d1d, 0x9008b6a,
+  0x7f6af2e3, 0x89cf867, 0x7f782c30, 0x8395024,
+  0x7f84c8e2, 0x7d59396, 0x7f90c8da, 0x771c3b3,
+  0x7f9c2bfb, 0x70de172, 0x7fa6f228, 0x6a9edc9,
+  0x7fb11b48, 0x645e9af, 0x7fbaa740, 0x5e1d61b,
+  0x7fc395f9, 0x57db403, 0x7fcbe75e, 0x519845e,
+  0x7fd39b5a, 0x4b54825, 0x7fdab1d9, 0x451004d,
+  0x7fe12acb, 0x3ecadcf, 0x7fe7061f, 0x38851a2,
+  0x7fec43c7, 0x323ecbe, 0x7ff0e3b6, 0x2bf801a,
+  0x7ff4e5e0, 0x25b0caf, 0x7ff84a3c, 0x1f69373,
+  0x7ffb10c1, 0x192155f, 0x7ffd3969, 0x12d936c,
+  0x7ffec42d, 0xc90e90, 0x7fffb10b, 0x6487c4,
+  0x7fffffff, 0x0, 0x7fffb10b, 0xff9b783c,
+  0x7ffec42d, 0xff36f170, 0x7ffd3969, 0xfed26c94,
+  0x7ffb10c1, 0xfe6deaa1, 0x7ff84a3c, 0xfe096c8d,
+  0x7ff4e5e0, 0xfda4f351, 0x7ff0e3b6, 0xfd407fe6,
+  0x7fec43c7, 0xfcdc1342, 0x7fe7061f, 0xfc77ae5e,
+  0x7fe12acb, 0xfc135231, 0x7fdab1d9, 0xfbaeffb3,
+  0x7fd39b5a, 0xfb4ab7db, 0x7fcbe75e, 0xfae67ba2,
+  0x7fc395f9, 0xfa824bfd, 0x7fbaa740, 0xfa1e29e5,
+  0x7fb11b48, 0xf9ba1651, 0x7fa6f228, 0xf9561237,
+  0x7f9c2bfb, 0xf8f21e8e, 0x7f90c8da, 0xf88e3c4d,
+  0x7f84c8e2, 0xf82a6c6a, 0x7f782c30, 0xf7c6afdc,
+  0x7f6af2e3, 0xf7630799, 0x7f5d1d1d, 0xf6ff7496,
+  0x7f4eaafe, 0xf69bf7c9, 0x7f3f9cab, 0xf6389228,
+  0x7f2ff24a, 0xf5d544a7, 0x7f1fabff, 0xf572103d,
+  0x7f0ec9f5, 0xf50ef5de, 0x7efd4c54, 0xf4abf67e,
+  0x7eeb3347, 0xf4491311, 0x7ed87efc, 0xf3e64c8c,
+  0x7ec52fa0, 0xf383a3e2, 0x7eb14563, 0xf3211a07,
+  0x7e9cc076, 0xf2beafed, 0x7e87a10c, 0xf25c6688,
+  0x7e71e759, 0xf1fa3ecb, 0x7e5b9392, 0xf19839a6,
+  0x7e44a5ef, 0xf136580d, 0x7e2d1ea8, 0xf0d49af1,
+  0x7e14fdf7, 0xf0730342, 0x7dfc4418, 0xf01191f3,
+  0x7de2f148, 0xefb047f2, 0x7dc905c5, 0xef4f2630,
+  0x7dae81cf, 0xeeee2d9d, 0x7d9365a8, 0xee8d5f29,
+  0x7d77b192, 0xee2cbbc1, 0x7d5b65d2, 0xedcc4454,
+  0x7d3e82ae, 0xed6bf9d1, 0x7d21086c, 0xed0bdd25,
+  0x7d02f757, 0xecabef3d, 0x7ce44fb7, 0xec4c3106,
+  0x7cc511d9, 0xebeca36c, 0x7ca53e09, 0xeb8d475b,
+  0x7c84d496, 0xeb2e1dbe, 0x7c63d5d1, 0xeacf277f,
+  0x7c42420a, 0xea70658a, 0x7c201994, 0xea11d8c8,
+  0x7bfd5cc4, 0xe9b38223, 0x7bda0bf0, 0xe9556282,
+  0x7bb6276e, 0xe8f77acf, 0x7b91af97, 0xe899cbf1,
+  0x7b6ca4c4, 0xe83c56cf, 0x7b470753, 0xe7df1c50,
+  0x7b20d79e, 0xe7821d59, 0x7afa1605, 0xe7255ad1,
+  0x7ad2c2e8, 0xe6c8d59c, 0x7aaadea6, 0xe66c8e9f,
+  0x7a8269a3, 0xe61086bc, 0x7a596442, 0xe5b4bed8,
+  0x7a2fcee8, 0xe55937d5, 0x7a05a9fd, 0xe4fdf294,
+  0x79daf5e8, 0xe4a2eff6, 0x79afb313, 0xe44830dd,
+  0x7983e1e8, 0xe3edb628, 0x795782d3, 0xe39380b6,
+  0x792a9642, 0xe3399167, 0x78fd1ca4, 0xe2dfe917,
+  0x78cf1669, 0xe28688a4, 0x78a08402, 0xe22d70eb,
+  0x787165e3, 0xe1d4a2c8, 0x7841bc7f, 0xe17c1f15,
+  0x7811884d, 0xe123e6ad, 0x77e0c9c3, 0xe0cbfa6a,
+  0x77af8159, 0xe0745b24, 0x777daf89, 0xe01d09b4,
+  0x774b54ce, 0xdfc606f1, 0x771871a5, 0xdf6f53b3,
+  0x76e5068a, 0xdf18f0ce, 0x76b113fd, 0xdec2df18,
+  0x767c9a7e, 0xde6d1f65, 0x76479a8e, 0xde17b28a,
+  0x761214b0, 0xddc29958, 0x75dc0968, 0xdd6dd4a2,
+  0x75a5793c, 0xdd196538, 0x756e64b2, 0xdcc54bec,
+  0x7536cc52, 0xdc71898d, 0x74feb0a5, 0xdc1e1ee9,
+  0x74c61236, 0xdbcb0cce, 0x748cf190, 0xdb785409,
+  0x74534f41, 0xdb25f566, 0x74192bd5, 0xdad3f1b1,
+  0x73de87de, 0xda8249b4, 0x73a363ec, 0xda30fe38,
+  0x7367c090, 0xd9e01006, 0x732b9e5e, 0xd98f7fe6,
+  0x72eefdea, 0xd93f4e9e, 0x72b1dfc9, 0xd8ef7cf4,
+  0x72744493, 0xd8a00bae, 0x72362ce0, 0xd850fb8e,
+  0x71f79948, 0xd8024d59, 0x71b88a66, 0xd7b401d1,
+  0x717900d6, 0xd76619b6, 0x7138fd35, 0xd71895c9,
+  0x70f8801f, 0xd6cb76c9, 0x70b78a36, 0xd67ebd74,
+  0x70761c18, 0xd6326a88, 0x70343667, 0xd5e67ec1,
+  0x6ff1d9c7, 0xd59afadb, 0x6faf06da, 0xd54fdf8f,
+  0x6f6bbe45, 0xd5052d97, 0x6f2800af, 0xd4bae5ab,
+  0x6ee3cebe, 0xd4710883, 0x6e9f291b, 0xd42796d5,
+  0x6e5a1070, 0xd3de9156, 0x6e148566, 0xd395f8ba,
+  0x6dce88aa, 0xd34dcdb4, 0x6d881ae8, 0xd30610f7,
+  0x6d413ccd, 0xd2bec333, 0x6cf9ef09, 0xd277e518,
+  0x6cb2324c, 0xd2317756, 0x6c6a0746, 0xd1eb7a9a,
+  0x6c216eaa, 0xd1a5ef90, 0x6bd8692b, 0xd160d6e5,
+  0x6b8ef77d, 0xd11c3142, 0x6b451a55, 0xd0d7ff51,
+  0x6afad269, 0xd09441bb, 0x6ab02071, 0xd050f926,
+  0x6a650525, 0xd00e2639, 0x6a19813f, 0xcfcbc999,
+  0x69cd9578, 0xcf89e3e8, 0x6981428c, 0xcf4875ca,
+  0x69348937, 0xcf077fe1, 0x68e76a37, 0xcec702cb,
+  0x6899e64a, 0xce86ff2a, 0x684bfe2f, 0xce47759a,
+  0x67fdb2a7, 0xce0866b8, 0x67af0472, 0xcdc9d320,
+  0x675ff452, 0xcd8bbb6d, 0x6710830c, 0xcd4e2037,
+  0x66c0b162, 0xcd110216, 0x6670801a, 0xccd461a2,
+  0x661feffa, 0xcc983f70, 0x65cf01c8, 0xcc5c9c14,
+  0x657db64c, 0xcc217822, 0x652c0e4f, 0xcbe6d42b,
+  0x64da0a9a, 0xcbacb0bf, 0x6487abf7, 0xcb730e70,
+  0x6434f332, 0xcb39edca, 0x63e1e117, 0xcb014f5b,
+  0x638e7673, 0xcac933ae, 0x633ab414, 0xca919b4e,
+  0x62e69ac8, 0xca5a86c4, 0x62922b5e, 0xca23f698,
+  0x623d66a8, 0xc9edeb50, 0x61e84d76, 0xc9b86572,
+  0x6192e09b, 0xc9836582, 0x613d20e8, 0xc94eec03,
+  0x60e70f32, 0xc91af976, 0x6090ac4d, 0xc8e78e5b,
+  0x6039f90f, 0xc8b4ab32, 0x5fe2f64c, 0xc8825077,
+  0x5f8ba4dc, 0xc8507ea7, 0x5f340596, 0xc81f363d,
+  0x5edc1953, 0xc7ee77b3, 0x5e83e0eb, 0xc7be4381,
+  0x5e2b5d38, 0xc78e9a1d, 0x5dd28f15, 0xc75f7bfe,
+  0x5d79775c, 0xc730e997, 0x5d2016e9, 0xc702e35c,
+  0x5cc66e99, 0xc6d569be, 0x5c6c7f4a, 0xc6a87d2d,
+  0x5c1249d8, 0xc67c1e18, 0x5bb7cf23, 0xc6504ced,
+  0x5b5d100a, 0xc6250a18, 0x5b020d6c, 0xc5fa5603,
+  0x5aa6c82b, 0xc5d03118, 0x5a4b4128, 0xc5a69bbe,
+  0x59ef7944, 0xc57d965d, 0x59937161, 0xc555215a,
+  0x59372a64, 0xc52d3d18, 0x58daa52f, 0xc505e9fb,
+  0x587de2a7, 0xc4df2862, 0x5820e3b0, 0xc4b8f8ad,
+  0x57c3a931, 0xc4935b3c, 0x5766340f, 0xc46e5069,
+  0x57088531, 0xc449d892, 0x56aa9d7e, 0xc425f410,
+  0x564c7ddd, 0xc402a33c, 0x55ee2738, 0xc3dfe66c,
+  0x558f9a76, 0xc3bdbdf6, 0x5530d881, 0xc39c2a2f,
+  0x54d1e242, 0xc37b2b6a, 0x5472b8a5, 0xc35ac1f7,
+  0x54135c94, 0xc33aee27, 0x53b3cefa, 0xc31bb049,
+  0x535410c3, 0xc2fd08a9, 0x52f422db, 0xc2def794,
+  0x5294062f, 0xc2c17d52, 0x5233bbac, 0xc2a49a2e,
+  0x51d3443f, 0xc2884e6e, 0x5172a0d7, 0xc26c9a58,
+  0x5111d263, 0xc2517e31, 0x50b0d9d0, 0xc236fa3b,
+  0x504fb80e, 0xc21d0eb8, 0x4fee6e0d, 0xc203bbe8,
+  0x4f8cfcbe, 0xc1eb0209, 0x4f2b650f, 0xc1d2e158,
+  0x4ec9a7f3, 0xc1bb5a11, 0x4e67c65a, 0xc1a46c6e,
+  0x4e05c135, 0xc18e18a7, 0x4da39978, 0xc1785ef4,
+  0x4d415013, 0xc1633f8a, 0x4cdee5f9, 0xc14eba9d,
+  0x4c7c5c1e, 0xc13ad060, 0x4c19b374, 0xc1278104,
+  0x4bb6ecef, 0xc114ccb9, 0x4b540982, 0xc102b3ac,
+  0x4af10a22, 0xc0f1360b, 0x4a8defc3, 0xc0e05401,
+  0x4a2abb59, 0xc0d00db6, 0x49c76dd8, 0xc0c06355,
+  0x49640837, 0xc0b15502, 0x49008b6a, 0xc0a2e2e3,
+  0x489cf867, 0xc0950d1d, 0x48395024, 0xc087d3d0,
+  0x47d59396, 0xc07b371e, 0x4771c3b3, 0xc06f3726,
+  0x470de172, 0xc063d405, 0x46a9edc9, 0xc0590dd8,
+  0x4645e9af, 0xc04ee4b8, 0x45e1d61b, 0xc04558c0,
+  0x457db403, 0xc03c6a07, 0x4519845e, 0xc03418a2,
+  0x44b54825, 0xc02c64a6, 0x4451004d, 0xc0254e27,
+  0x43ecadcf, 0xc01ed535, 0x438851a2, 0xc018f9e1,
+  0x4323ecbe, 0xc013bc39, 0x42bf801a, 0xc00f1c4a,
+  0x425b0caf, 0xc00b1a20, 0x41f69373, 0xc007b5c4,
+  0x4192155f, 0xc004ef3f, 0x412d936c, 0xc002c697,
+  0x40c90e90, 0xc0013bd3, 0x406487c4, 0xc0004ef5
+};
+
+/**   
+* @brief  Initialization function for the Q31 RFFT/RIFFT.  
+* @param[in, out] *S             points to an instance of the Q31 RFFT/RIFFT structure.  
+* @param[in, out] *S_CFFT        points to an instance of the Q31 CFFT/CIFFT structure.  
+* @param[in]      fftLenReal     length of the FFT.  
+* @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.  
+* @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.  
+*   
+* \par Description:  
+* \par  
+* The parameter fftLenReal	Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.   
+* \par   
+* The parameter ifftFlagR controls whether a forward or inverse transform is computed.   
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.   
+* \par   
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.  
+* \par   
+* This function also initializes Twiddle factor table.   
+*/
+
+arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialize the Real FFT length */
+  S->fftLenReal = (uint16_t) fftLenReal;
+
+  /*  Initialize the Complex FFT length */
+  S->fftLenBy2 = (uint16_t) fftLenReal / 2u;
+
+  /*  Initialize the Twiddle coefficientA pointer */
+  S->pTwiddleAReal = (q31_t *) realCoefAQ31;
+
+  /*  Initialize the Twiddle coefficientB pointer */
+  S->pTwiddleBReal = (q31_t *) realCoefBQ31;
+
+  /*  Initialize the Flag for selection of RFFT or RIFFT */
+  S->ifftFlagR = (uint8_t) ifftFlagR;
+
+  /*  Initialize the Flag for calculation Bit reversal or not */
+  S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+  /*  Initialization of coef modifier depending on the FFT length */
+  switch (S->fftLenReal)
+  {
+  case 512u:
+    S->twidCoefRModifier = 2u;
+    break;
+  case 128u:
+    S->twidCoefRModifier = 8u;
+    break;
+  default:
+    /*  Reporting argument error if rfftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  /* Init Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  if(S->ifftFlagR)
+  {
+    /* Initializes the CIFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_q31(S->pCfft, (uint16_t) S->fftLenBy2, 1u, 1u);
+  }
+  else
+  {
+    /* Initializes the CFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_q31(S->pCfft, (uint16_t) S->fftLenBy2, 0u, 1u);
+  }
+
+  /* return the status of RFFT Init function */
+  return (status);
+
+}
+
+  /**   
+   * @} end of RFFT_RIFFT group   
+   */
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c
new file mode 100644
index 000000000..dabde5993
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c
@@ -0,0 +1,457 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_rfft_q15.c   
+*   
+* Description:	RFFT & RIFFT Q15 process function   
+*   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------   
+*		Internal functions prototypes   
+--------------------------------------------------------------------*/
+
+void arm_split_rfft_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pATable,
+  q15_t * pBTable,
+  q15_t * pDst,
+  uint32_t modifier);
+
+void arm_split_rifft_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pATable,
+  q15_t * pBTable,
+  q15_t * pDst,
+  uint32_t modifier);
+
+/**   
+ * @addtogroup RFFT_RIFFT   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q15 RFFT/RIFFT.  
+ * @param[in]  *S    points to an instance of the Q15 RFFT/RIFFT structure.  
+ * @param[in]  *pSrc points to the input buffer.  
+ * @param[out] *pDst points to the output buffer.  
+ * @return none.  
+ *   
+ * \par Input an output formats:  
+ * \par   
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.   
+ * Hence the output format is different for different RFFT sizes.   
+ * The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:  
+ * \par   
+ * \image html RFFTQ15.gif "Input and Output Formats for Q15 RFFT"   
+ * \par   
+ * \image html RIFFTQ15.gif "Input and Output Formats for Q15 RIFFT"   
+ */
+
+void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst)
+{
+  const arm_cfft_radix4_instance_q15 *S_CFFT = S->pCfft;
+
+  /* Calculation of RIFFT of input */
+  if(S->ifftFlagR == 1u)
+  {
+    /*  Real IFFT core process */
+    arm_split_rifft_q15(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                        S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+
+    /* Complex readix-4 IFFT process */
+    arm_radix4_butterfly_inverse_q15(pDst, S_CFFT->fftLen,
+                                     S_CFFT->pTwiddle,
+                                     S_CFFT->twidCoefModifier);
+
+    /* Bit reversal process */
+    if(S->bitReverseFlagR == 1u)
+    {
+      arm_bitreversal_q15(pDst, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+  }
+  else
+  {
+    /* Calculation of RFFT of input */
+
+    /* Complex readix-4 FFT process */
+    arm_radix4_butterfly_q15(pSrc, S_CFFT->fftLen,
+                             S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
+
+    /* Bit reversal process */
+    if(S->bitReverseFlagR == 1u)
+    {
+      arm_bitreversal_q15(pSrc, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+
+    arm_split_rfft_q15(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                       S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+  }
+
+}
+
+  /**   
+   * @} end of RFFT_RIFFT group   
+   */
+
+/**   
+ * @brief  Core Real FFT process   
+ * @param  *pSrc 				points to the input buffer.  
+ * @param  fftLen  				length of FFT.  
+ * @param  *pATable 			points to the A twiddle Coef buffer.   
+ * @param  *pBTable 			points to the B twiddle Coef buffer.  
+ * @param  *pDst 				points to the output buffer.  
+ * @param  modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.   
+ * The function implements a Real FFT   
+ */
+
+void arm_split_rfft_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pATable,
+  q15_t * pBTable,
+  q15_t * pDst,
+  uint32_t modifier)
+{
+  uint32_t i;                                    /* Loop Counter */
+  q31_t outR, outI;                              /* Temporary variables for output */
+  q15_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
+  q15_t *pSrc1, *pSrc2;
+
+
+  pSrc[2u * fftLen] = pSrc[0];
+  pSrc[(2u * fftLen) + 1u] = pSrc[1];
+
+  pCoefA = &pATable[modifier * 2u];
+  pCoefB = &pBTable[modifier * 2u];
+
+  pSrc1 = &pSrc[2];
+  pSrc2 = &pSrc[(2u * fftLen) - 2u];
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  i = 1u;
+
+  while(i < fftLen)
+  {
+    /*   
+       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]   
+       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +   
+       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);   
+     */
+
+    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1] */
+    outR = __SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA));
+
+#else
+
+    /* -(pSrc[2 * i + 1] * pATable[2 * i + 1] - pSrc[2 * i] * pATable[2 * i]) */
+    outR = -(__SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA)));
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* pSrc[2 * n - 2 * i] * pBTable[2 * i] +   
+       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
+    outR = __SMLAD(*__SIMD32(pSrc2), *__SIMD32(pCoefB), outR) >> 15u;
+
+    /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    outI = __SMUSDX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));
+
+#else
+
+    outI = __SMUSDX(*__SIMD32(pCoefB), *__SIMD32(pSrc2)--);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] */
+    outI = __SMLADX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), outI);
+
+    /* write output */
+    pDst[2u * i] = (q15_t) outR;
+    pDst[(2u * i) + 1u] = outI >> 15u;
+
+    /* write complex conjugate output */
+    pDst[(4u * fftLen) - (2u * i)] = (q15_t) outR;
+    pDst[((4u * fftLen) - (2u * i)) + 1u] = -(outI >> 15u);
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (2u * modifier);
+    pCoefA = pCoefA + (2u * modifier);
+
+    i++;
+
+  }
+
+  pDst[2u * fftLen] = pSrc[0] - pSrc[1];
+  pDst[(2u * fftLen) + 1u] = 0;
+
+  pDst[0] = pSrc[0] + pSrc[1];
+  pDst[1] = 0;
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  i = 1u;
+
+  while(i < fftLen)
+  {
+    /*   
+       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]   
+       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +   
+       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);   
+     */
+
+    outR = *pSrc1 * *pCoefA;
+    outR = outR - (*(pSrc1 + 1) * *(pCoefA + 1));
+    outR = outR + (*pSrc2 * *pCoefB);
+    outR = (outR + (*(pSrc2 + 1) * *(pCoefB + 1))) >> 15;
+
+
+    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);  
+     */
+
+    outI = *pSrc2 * *(pCoefB + 1);
+    outI = outI - (*(pSrc2 + 1) * *pCoefB);
+    outI = outI + (*(pSrc1 + 1) * *pCoefA);
+    outI = outI + (*pSrc1 * *(pCoefA + 1));
+
+    /* update input pointers */
+    pSrc1 += 2u;
+    pSrc2 -= 2u;
+
+    /* write output */
+    pDst[2u * i] = (q15_t) outR;
+    pDst[(2u * i) + 1u] = outI >> 15u;
+
+    /* write complex conjugate output */
+    pDst[(4u * fftLen) - (2u * i)] = (q15_t) outR;
+    pDst[((4u * fftLen) - (2u * i)) + 1u] = -(outI >> 15u);
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (2u * modifier);
+    pCoefA = pCoefA + (2u * modifier);
+
+    i++;
+
+  }
+
+  pDst[2u * fftLen] = pSrc[0] - pSrc[1];
+  pDst[(2u * fftLen) + 1u] = 0;
+
+  pDst[0] = pSrc[0] + pSrc[1];
+  pDst[1] = 0;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+
+/**   
+ * @brief  Core Real IFFT process   
+ * @param[in]   *pSrc 				points to the input buffer.   
+ * @param[in]   fftLen  		    length of FFT.  
+ * @param[in]   *pATable 			points to the twiddle Coef A buffer.  
+ * @param[in]   *pBTable 			points to the twiddle Coef B buffer.   
+ * @param[out]  *pDst 				points to the output buffer.  
+ * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.   
+ * The function implements a Real IFFT   
+ */
+void arm_split_rifft_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pATable,
+  q15_t * pBTable,
+  q15_t * pDst,
+  uint32_t modifier)
+{
+  uint32_t i;                                    /* Loop Counter */
+  q31_t outR, outI;                              /* Temporary variables for output */
+  q15_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
+  q15_t *pSrc1, *pSrc2;
+  q15_t *pDst1 = &pDst[0];
+
+  pCoefA = &pATable[0];
+  pCoefB = &pBTable[0];
+
+  pSrc1 = &pSrc[0];
+  pSrc2 = &pSrc[2u * fftLen];
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  i = fftLen;
+
+  while(i > 0u)
+  {
+
+    /*   
+       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);   
+
+       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -   
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);   
+
+     */
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* pIn[2 * n - 2 * i] * pBTable[2 * i] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
+    outR = __SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB));
+
+#else
+
+    /* -(-pIn[2 * n - 2 * i] * pBTable[2 * i] + 
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1])) */
+    outR = -(__SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB)));
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i] */
+    outR = __SMLAD(*__SIMD32(pSrc1), *__SIMD32(pCoefA), outR) >> 15u;
+
+    /*   
+       -pIn[2 * n - 2 * i] * pBTable[2 * i + 1] +   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+    outI = __SMUADX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));
+
+    /* pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    outI = __SMLSDX(*__SIMD32(pCoefA), *__SIMD32(pSrc1)++, -outI);
+
+#else
+
+    outI = __SMLSDX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), -outI);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+    /* write output */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst1)++ = __PKHBT(outR, (outI >> 15u), 16);
+
+#else
+
+    *__SIMD32(pDst1)++ = __PKHBT((outI >> 15u), outR, 16);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (2u * modifier);
+    pCoefA = pCoefA + (2u * modifier);
+
+    i--;
+
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  i = fftLen;
+
+  while(i > 0u)
+  {
+
+    /*   
+       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);   
+     */
+
+    outR = *pSrc2 * *pCoefB;
+    outR = outR - (*(pSrc2 + 1) * *(pCoefB + 1));
+    outR = outR + (*pSrc1 * *pCoefA);
+    outR = (outR + (*(pSrc1 + 1) * *(pCoefA + 1))) >> 15;
+
+    /*  
+       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -  
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -  
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);  
+     */
+
+    outI = *(pSrc1 + 1) * *pCoefA;
+    outI = outI - (*pSrc1 * *(pCoefA + 1));
+    outI = outI - (*pSrc2 * *(pCoefB + 1));
+    outI = outI - (*(pSrc2 + 1) * *(pCoefB));
+
+    /* update input pointers */
+    pSrc1 += 2u;
+    pSrc2 -= 2u;
+
+    /* write output */
+    *pDst1++ = (q15_t) outR;
+    *pDst1++ = (q15_t) (outI >> 15);
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (2u * modifier);
+    pCoefA = pCoefA + (2u * modifier);
+
+    i--;
+
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
diff --git a/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c
new file mode 100644
index 000000000..76c92cdc7
--- /dev/null
+++ b/hardware/sam/system/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c
@@ -0,0 +1,326 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_rfft_q31.c   
+*   
+* Description:	RFFT & RIFFT Q31 process function   
+*   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------   
+*		Internal functions prototypes   
+--------------------------------------------------------------------*/
+
+void arm_split_rfft_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pATable,
+  q31_t * pBTable,
+  q31_t * pDst,
+  uint32_t modifier);
+
+void arm_split_rifft_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pATable,
+  q31_t * pBTable,
+  q31_t * pDst,
+  uint32_t modifier);
+
+/**   
+ * @addtogroup RFFT_RIFFT   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q31 RFFT/RIFFT.  
+ * @param[in]  *S    points to an instance of the Q31 RFFT/RIFFT structure.  
+ * @param[in]  *pSrc points to the input buffer.  
+ * @param[out] *pDst points to the output buffer.  
+ * @return none.  
+ *   
+ * \par Input an output formats:  
+ * \par   
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.  
+ * Hence the output format is different for different RFFT sizes.   
+ * The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:  
+ * \par   
+ * \image html RFFTQ31.gif "Input and Output Formats for Q31 RFFT"   
+ *   
+ * \par   
+ * \image html RIFFTQ31.gif "Input and Output Formats for Q31 RIFFT"   
+ */
+
+void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst)
+{
+  const arm_cfft_radix4_instance_q31 *S_CFFT = S->pCfft;
+
+  /* Calculation of RIFFT of input */
+  if(S->ifftFlagR == 1u)
+  {
+    /*  Real IFFT core process */
+    arm_split_rifft_q31(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                        S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+
+    /* Complex readix-4 IFFT process */
+    arm_radix4_butterfly_inverse_q31(pDst, S_CFFT->fftLen,
+                                     S_CFFT->pTwiddle,
+                                     S_CFFT->twidCoefModifier);
+    /* Bit reversal process */
+    if(S->bitReverseFlagR == 1u)
+    {
+      arm_bitreversal_q31(pDst, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+  }
+  else
+  {
+    /* Calculation of RFFT of input */
+
+    /* Complex readix-4 FFT process */
+    arm_radix4_butterfly_q31(pSrc, S_CFFT->fftLen,
+                             S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
+
+    /* Bit reversal process */
+    if(S->bitReverseFlagR == 1u)
+    {
+      arm_bitreversal_q31(pSrc, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+
+    /*  Real FFT core process */
+    arm_split_rfft_q31(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                       S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+  }
+
+}
+
+
+  /**   
+   * @} end of RFFT_RIFFT group   
+   */
+
+/**   
+ * @brief  Core Real FFT process   
+ * @param[in]   *pSrc 				points to the input buffer.   
+ * @param[in]   fftLen  			length of FFT.  
+ * @param[in]   *pATable 			points to the twiddle Coef A buffer.   
+ * @param[in]   *pBTable 			points to the twiddle Coef B buffer.   
+ * @param[out]  *pDst 				points to the output buffer.   
+ * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.   
+ */
+
+void arm_split_rfft_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pATable,
+  q31_t * pBTable,
+  q31_t * pDst,
+  uint32_t modifier)
+{
+  uint32_t i;                                    /* Loop Counter */
+  q31_t outR, outI;                              /* Temporary variables for output */
+  q31_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
+  q31_t CoefA1, CoefA2, CoefB1;                  /* Temporary variables for twiddle coefficients */
+  q31_t *pOut1 = &pDst[2], *pOut2 = &pDst[(4u * fftLen) - 1u];
+  q31_t *pIn1 = &pSrc[2], *pIn2 = &pSrc[(2u * fftLen) - 1u];
+
+  pSrc[2u * fftLen] = pSrc[0];
+  pSrc[(2u * fftLen) + 1u] = pSrc[1];
+
+  /* Init coefficient pointers */
+  pCoefA = &pATable[modifier * 2u];
+  pCoefB = &pBTable[modifier * 2u];
+
+  i = fftLen - 1u;
+
+  while(i > 0u)
+  {
+    /*   
+       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]   
+       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +   
+       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);   
+     */
+
+    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+    CoefA1 = *pCoefA++;
+    CoefA2 = *pCoefA;
+
+    /* outR = (pSrc[2 * i] * pATable[2 * i] */
+    outR = ((int32_t) (((q63_t) * pIn1 * CoefA1) >> 32));
+
+    /* outI = pIn[2 * i] * pATable[2 * i + 1] */
+    outI = ((int32_t) (((q63_t) * pIn1++ * CoefA2) >> 32));
+
+    /* - pSrc[2 * i + 1] * pATable[2 * i + 1] */
+    outR =
+      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn1 * (-CoefA2))) >> 32);
+
+    /* (pIn[2 * i + 1] * pATable[2 * i] */
+    outI =
+      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn1++ * (CoefA1))) >> 32);
+
+    /* pSrc[2 * n - 2 * i] * pBTable[2 * i]  */
+    outR =
+      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (-CoefA2))) >> 32);
+    CoefB1 = *pCoefB;
+
+    /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */
+    outI =
+      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn2-- * (-CoefB1))) >> 32);
+
+    /* pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */
+    outR =
+      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (CoefB1))) >> 32);
+
+    /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+    outI =
+      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn2-- * (-CoefA2))) >> 32);
+
+    /* write output */
+    *pOut1++ = (outR << 1u);
+    *pOut1++ = (outI << 1u);
+
+    /* write complex conjugate output */
+    *pOut2-- = -(outI << 1u);
+    *pOut2-- = (outR << 1u);
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (modifier * 2u);
+    pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+    i--;
+
+  }
+
+  pDst[2u * fftLen] = pSrc[0] - pSrc[1];
+  pDst[(2u * fftLen) + 1u] = 0;
+
+  pDst[0] = pSrc[0] + pSrc[1];
+  pDst[1] = 0;
+
+}
+
+
+/**   
+ * @brief  Core Real IFFT process   
+ * @param[in]   *pSrc 				points to the input buffer.  
+ * @param[in]   fftLen  			length of FFT.   
+ * @param[in]   *pATable 			points to the twiddle Coef A buffer.  
+ * @param[in]   *pBTable 			points to the twiddle Coef B buffer.   
+ * @param[out]  *pDst 				points to the output buffer.  
+ * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.   
+ */
+
+void arm_split_rifft_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pATable,
+  q31_t * pBTable,
+  q31_t * pDst,
+  uint32_t modifier)
+{
+  q31_t outR, outI;                              /* Temporary variables for output */
+  q31_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
+  q31_t CoefA1, CoefA2, CoefB1;                  /* Temporary variables for twiddle coefficients */
+  q31_t *pIn1 = &pSrc[0], *pIn2 = &pSrc[(2u * fftLen) + 1u];
+
+  pCoefA = &pATable[0];
+  pCoefB = &pBTable[0];
+
+  while(fftLen > 0u)
+  {
+    /*   
+       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);   
+
+       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -   
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);   
+
+     */
+    CoefA1 = *pCoefA++;
+    CoefA2 = *pCoefA;
+
+    /* outR = (pIn[2 * i] * pATable[2 * i] */
+    outR = ((int32_t) (((q63_t) * pIn1 * CoefA1) >> 32));
+
+    /* - pIn[2 * i] * pATable[2 * i + 1] */
+    outI = -((int32_t) (((q63_t) * pIn1++ * CoefA2) >> 32));
+
+    /* pIn[2 * i + 1] * pATable[2 * i + 1] */
+    outR =
+      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn1 * (CoefA2))) >> 32);
+
+    /* pIn[2 * i + 1] * pATable[2 * i] */
+    outI =
+      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn1++ * (CoefA1))) >> 32);
+
+    /* pIn[2 * n - 2 * i] * pBTable[2 * i] */
+    outR =
+      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (CoefA2))) >> 32);
+
+    CoefB1 = *pCoefB;
+
+    /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */
+    outI =
+      (q31_t) ((((q63_t) outI << 32) - ((q63_t) * pIn2-- * (CoefB1))) >> 32);
+
+    /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */
+    outR =
+      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (CoefB1))) >> 32);
+
+    /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+    outI =
+      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn2-- * (CoefA2))) >> 32);
+
+    /* write output */
+    *pDst++ = (outR << 1u);
+    *pDst++ = (outI << 1u);
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (modifier * 2u);
+    pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+    /* Decrement loop count */
+    fftLen--;
+
+  }
+
+
+}
diff --git a/hardware/sam/system/CMSIS/Documentation/CMSIS-SVD_Schema_1_0.xsd b/hardware/sam/system/CMSIS/Documentation/CMSIS-SVD_Schema_1_0.xsd
new file mode 100644
index 000000000..4f9aef635
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/CMSIS-SVD_Schema_1_0.xsd
@@ -0,0 +1,257 @@
+
+
+  
+  
+    
+      
+    
+  
+
+  
+    
+      
+    
+  
+
+  
+    
+      
+    
+  
+
+  
+    
+      
+    
+  
+
+  
+    
+      
+      
+      
+      
+      
+    
+  
+
+  
+    
+      
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    
+      
+      
+      
+      
+    
+  
+
+  
+    
+      
+      
+      
+    
+  
+
+  
+    
+      
+    
+  
+
+  
+    
+      
+      
+      
+        
+          
+            
+            
+          
+        
+      
+    
+  
+
+  
+    
+      
+      
+      
+        
+          
+            
+            
+            
+          
+        
+      
+    
+  
+
+  
+    
+      
+      
+    
+  
+
+  
+    
+      
+      
+      
+      
+    
+  
+
+  
+    
+      
+      
+    
+  
+
+  
+    
+      
+         
+     
+  
+
+  
+    
+      
+      
+      
+    
+  
+
+  
+    
+      
+        
+        
+        
+        
+        
+        
+        
+          
+            
+              
+                
+                  
+                    
+                    
+                    
+                    
+                    
+                    
+                    
+                    
+                    
+                    
+                    
+                    
+                      
+                        
+                          
+                            
+                              
+                                
+                                 
+                                
+                                
+                                
+                                
+                                
+                                
+                                
+                                
+                                
+                                  
+                                    
+                                      
+                                      
+                                        
+                                          
+                                          
+                                          
+                                            
+                                            
+                                            
+                                          
+                                          
+                                          
+                                          
+                                          
+                                          
+                                            
+                                              
+                                                
+                                                
+                                                
+                                                  
+                                                    
+                                                      
+                                                      
+                                                      
+                                                        
+                                                        
+                                                      
+                                                    
+                                                  
+                                                
+                                              
+                                              
+                                            
+                                          
+                                        
+                                        
+                                      
+                                    
+                                    
+                                  
+                                
+                              
+                              
+                            
+                          
+                        
+                      
+                    
+                  
+                  
+                
+              
+            
+          
+        
+        
+          
+            
+              
+              
+            
+          
+        
+      
+      
+    
+  
+
diff --git a/hardware/sam/system/CMSIS/Documentation/CMSIS_CM4_SIMD.htm b/hardware/sam/system/CMSIS/Documentation/CMSIS_CM4_SIMD.htm
new file mode 100644
index 000000000..243f377a8
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/CMSIS_CM4_SIMD.htm
@@ -0,0 +1,3809 @@
+
+
+  
+  CMSIS: Cortex-M4 SIMD Instructions
+  
+  
+
+
+
+
+
CMSIS Support for Cortex-M4 SIMD Instructions

+
+
This file describes the Cortex-M4 SIMD instructions supported by CMSIS.

+
Version: 1.00 - 25. November 2010

+
+
Information in this file, the accompany manuals, and software is

+                 Copyright © ARM Ltd.
All rights reserved.
+

+
+

+
+
Revision History

+
    
+	
  • Revision 0.01 - January 2010: Initial version
    • 
+	
  • Revision 0.02 - June 2010: added __QADD, __QSUB
    • 
+	
  • Revision 1.00 - November 2010: 
    • 
+

+
+

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Contents

+
+
    
+  
  1. About
    2. 
+  
  2. Cortex-M4 SIMD instruction support
    3. 
+  
  3. Examples
    4. 
+

+
+
+
+
 

+
About

+

+  CMSIS provides for the Cortex-M4 a set of functions supporting Cortex-M4 SIMD instructions.
+

+
+
 

+
Cortex-M4 SIMD instruction support

+
CMSIS supports the following functions for Cortex-M4 instructions:
+

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NameMnemonicDescription
__SADD8SADD8GE setting quad 8-bit signed addition
__QADD8QADD8Q setting quad 8-bit saturating addition
__SHADD8SHADD8Quad 8-bit signed addition with halved results
__UADD8UADD8GE setting quad 8-bit unsigned addition
__UQADD8UQADD8Quad 8-bit unsigned saturating addition
__UHADD8UHADD8Quad 8-bit unsigned addition with halved results
__SSUB8SSUB8GE setting quad 8-bit signed subtraction
__QSUB8QSUB8Q setting quad 8-bit saturating subtract
__SHSUB8SHSUB8Quad 8-bit signed subtraction with halved results
__USUB8USUB8GE setting quad 8-bit unsigned subtract
__UQSUB8UQSUB8Quad 8-bit unsigned saturating subtraction
__UHSUB8UHSUB8Quad 8-bit unsigned subtraction with halved results
__SADD16SADD16GE setting dual 16-bit signed addition
__QADD16QADD16Q setting dual 16-bit saturating addition
__SHADD16SHADD16Dual 16-bit signed addition with halved results
__UADD16UADD16GE setting dual 16-bit unsigned addition
__UQADD16UQADD16Dual 16-bit unsigned saturating addition
__UHADD16UHADD16Dual 16-bit unsigned addition with halved results
__SSUB16SSUB16GE setting dual 16-bit signed subtraction
__QSUB16QSUB16Q setting dual 16-bit saturating subtract
__SHSUB16SHSUB16Dual 16-bit signed subtraction with halved results
__USUB16USUB16GE setting dual 16-bit unsigned subtract
__UQSUB16UQSUB16Dual 16-bit unsigned saturating subtraction
__UHSUB16UHSUB16Dual 16-bit unsigned subtraction with halved results
__SASXSASXGE setting dual 16-bit addition and subtraction with exchange
__QASXQASXQ setting dual 16-bit add and subtract with exchange
__SHASXSHASXDual 16-bit signed addition and subtraction with halved results
__UASXUASXGE setting dual 16-bit unsigned addition and subtraction with exchange
__UQASXUQASXDual 16-bit unsigned saturating addition and subtraction with exchange
__UHASXUHASXDual 16-bit unsigned addition and subtraction with halved results and exchange
__SSAXSSAXGE setting dual 16-bit signed subtraction and addition with exchange
__QSAXQSAXQ setting dual 16-bit subtract and add with exchange
__SHSAXSHSAXDual 16-bit signed subtraction and addition with halved results
__USAXUSAXGE setting dual 16-bit unsigned subtract and add with exchange
__UQSAXUQSAXDual 16-bit unsigned saturating subtraction and addition with exchange
__UHSAXUHSAXDual 16-bit unsigned subtraction and addition with halved results and exchange
__USAD8USAD8Unsigned sum of quad 8-bit unsigned absolute difference
__USADA8USADA8Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate
__SSAT16SSAT16Q setting dual 16-bit saturate
__USAT16USAT16Q setting dual 16-bit unsigned saturate
__UXTB16UXTB16Dual extract 8-bits and zero-extend to 16-bits
__UXTAB16UXTAB16Extracted 16-bit to 32-bit unsigned addition
__SXTB16SXTB16Dual extract 8-bits and sign extend each to 16-bits
__SXTAB16SXTAB16Dual extracted 8-bit to 16-bit signed addition
__SMUADSMUADQ setting sum of dual 16-bit signed multiply
__SMUADXSMUADXQ setting sum of dual 16-bit signed multiply with exchange
__SMLADSMLADQ setting dual 16-bit signed multiply with single 32-bit accumulator
__SMLADXSMLADXQ setting pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator
__SMLALDSMLALDDual 16-bit signed multiply with single 64-bit accumulator
__SMLALDXSMLALDXDual 16-bit signed multiply with exchange with single 64-bit accumulator
__SMUSDSMUSDDual 16-bit signed multiply returning difference
__SMUSDXSMUSDXDual 16-bit signed multiply with exchange returning difference
__SMLSDSMLSDQ setting dual 16-bit signed multiply subtract with 32-bit accumulate
__SMLSDXSMLSDXQ setting dual 16-bit signed multiply with exchange subtract with 32-bit accumulate
__SMLSLDSMLSLDQ setting dual 16-bit signed multiply subtract with 64-bit accumulate
__SMLSLDXSMLSLDXQ setting dual 16-bit signed multiply with exchange subtract with 64-bit accumulate
__SELSELSelect bytes based on GE bits
__QADDQADDQ setting saturating add
__QSUBQSUB/td>
+      Q setting saturating subtract

+
+
+
+
+
Function __SADD8

+
+  
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Summary
+        
+uint32_t __SADD8(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform four 8-bit signed integer additions.

+          The GE bits in the APSR are set according to the results of the additions.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit summands.
    • 
+          
  • val2: second four 8-bit summands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the addition of the first bytes from each operand, in the first byte of the return value.
    • 
+            
  • the addition of the second bytes of each operand, in the second byte of the return value.
    • 
+            
  • the addition of the third bytes of each operand, in the third byte of the return value.
    • 
+            
  • the addition of the fourth bytes of each operand, in the fourth byte of the return value.
    • 
+          

+          
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
+             the results of the operation.

+             If res is the return value, then:
+          

+          
    
+            
  • if res[7:0] ≥ 0 then APSR.GE[0] = 1 else 0
    • 
+            
  • if res[15:8] ≥ 0 then APSR.GE[1] = 1 else 0
    • 
+            
  • if res[23:16] ≥ 0 then APSR.GE[2] = 1 else 0
    • 
+            
  • if res[31:24] ≥ 0 then APSR.GE[3] = 1 else 0
    • 
+         
      
+      
Operation
+        
+res[7:0]   = val1[7:0]   + val2[7:0]
+res[15:8]  = val1[15:8]  + val2[15:8]
+res[23:16] = val1[23:16] + val2[23:16]
+res[31:24] = val1[31:24] + val2[31:24]

+      

+
+
Function __QADD8

+
+  
+    
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Summary
+        
+uint32_t __QADD8(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform four 8-bit integer additions, saturating the results to 
+          the 8-bit signed integer range -27 ≤ x ≤ 27 - 1.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit summands.
    • 
+          
  • val2: second four 8-bit summands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the saturated addition of the first byte of each operand in the first byte of the return value.
    • 
+            
  • the saturated addition of the second byte of each operand in the second byte of the return value.
    • 
+            
  • the saturated addition of the third byte of each operand in the third byte of the return value.
    • 
+            
  • the saturated addition of the fourth byte of each operand in the fourth byte of the return value.
    • 
+          

+          
The returned results are saturated to the 16-bit signed integer range -27 ≤ x ≤ 27 - 1.
+          

+      
Operation
+        
+res[7:0]   = val1[7:0]   + val2[7:0]
+res[15:8]  = val1[15:8]  + val2[15:8]
+res[23:16] = val1[23:16] + val2[23:16]
+res[31:24] = val1[31:24] + val2[31:24]

+      

+
+
Function __SHADD8

+
+  
+    
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+
Summary
+        
+uint32_t __SHADD8(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform four signed 8-bit integer additions, halving the results.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit summands.
    • 
+          
  • val2: second four 8-bit summands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the halved addition of the first bytes from each operand, in the first byte of the return value.
    • 
+            
  • the halved addition of the second bytes from each operand, in the second byte of the return value.
    • 
+            
  • the halved addition fo the third bytes from each operand, in the third byte of the return value.
    • 
+            
  • the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.
    • 
+          

+      
Operation
+        
+res[7:0]   = (val1[7:0]   + val2[7:0])   >> 1
+res[15:8]  = (val1[15:8]  + val2[15:8])  >> 1
+res[23:16] = (val1[23:16] + val2[23:16]) >> 1
+res[31:24] = (val1[31:24] + val2[31:24]) >> 1

+      

+
+
Function __UADD8

+
+  
+    
+      
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Summary
+        
+uint32_t __UADD8(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform four unsigned 8-bit integer additions.

+          The GE bits in the APSR are set according to the results.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit summands for each addition.
    • 
+          
  • val2: second four 8-bit summands for each addition.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the addition of the first bytes in each operand, in the first byte of the return value.
    • 
+            
  • the addition of the second bytes in each operand, in the second byte of the return value.
    • 
+            
  • the addition of the third bytes in each operand, in the third byte of the return value.
    • 
+            
  • the addition of the fourth bytes in each operand, in the fourth byte of the return value.
    • 
+          

+          
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
+             the results of the operation.

+             If res is the return value, then:
+          

+          
    
+            
  • if res[7:0] ≥ 0x100 then APSR.GE[0] = 1 else 0
    • 
+            
  • if res[15:8] ≥ 0x100 then APSR.GE[1] = 1 else 0
    • 
+            
  • if res[23:16] ≥ 0x100 then APSR.GE[2] = 1 else 0
    • 
+            
  • if res[31:24] ≥ 0x100 then APSR.GE[3] = 1 else 0
    • 
+         
      
+      
Operation
+        
+res[7:0]   = val1[7:0]   + val2[7:0]
+res[15:8]  = val1[15:8]  + val2[15:8]
+res[23:16] = val1[23:16] + val2[23:16]
+res[31:24] = val1[31:24] + val2[31:24]

+      

+
+
Function __UQADD8

+
+  
+    
+      
+      
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+
Summary
+        
+uint32_t __UQADD8(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform four unsigned 8-bit integer additions, saturating the 
+          results to the 8-bit unsigned integer range 0 ≤ x ≤ 28 - 1.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit summands.
    • 
+          
  • val2: second four 8-bit summands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the addition of the first bytes in each operand, in the first byte of the return value.
    • 
+            
  • the addition of the second bytes in each operand, in the second byte of the return value.
    • 
+            
  • the addition of the third bytes in each operand, in the third byte of the return value.
    • 
+            
  • the addition of the fourth bytes in each operand, in the fourth byte of the return value.
    • 
+          

+          
The results are saturated to the 8-bit unsigned integer range 0 ≤ x ≤ 28 - 1.
+          

+      
Operation
+        
+res[7:0]   = val1[7:0]   + val2[7:0]
+res[15:8]  = val1[15:8]  + val2[15:8]
+res[23:16] = val1[23:16] + val2[23:16]
+res[31:24] = val1[31:24] + val2[31:24]

+      

+
+
Function __UHADD8

+
+  
+    
+      
+      
+    
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+      
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+      
+    
+  
+
Summary
+        
+uint32_t __UHADD8(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform four unsigned 8-bit integer additions, halving the results.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit summands.
    • 
+          
  • val2: second four 8-bit summands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the halved addition of the first bytes in each operand, in the first byte of the return value.
    • 
+            
  • the halved addition of the second bytes in each operand, in the second byte of the return value.
    • 
+            
  • the halved addition of the third bytes in each operand, in the third byte of the return value.
    • 
+            
  • the halved addition of the fourth bytes in each operand, in the fourth byte of the return value.
    • 
+          

+      
Operation
+        
+res[7:0]   = (val1[7:0]   + val2[7:0])   >> 1
+res[15:8]  = (val1[15:8]  + val2[15:8])  >> 1
+res[23:16] = (val1[23:16] + val2[23:16]) >> 1
+res[31:24] = (val1[31:24] + val2[31:24]) >> 1

+      

+
+
Function __SSUB8

+
+  
+    
+      
+      
+    
+
+    
+      
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+    
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+    
+  
+
Summary
+        
+uint32_t __SSUB8(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform four 8-bit signed integer subtractions.

+          The GE bits in the APSR are set according to the results.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit operands of each subtraction.
    • 
+          
  • val2: second four 8-bit operands of each subtraction.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the subtraction of the first byte in the second operand from the first byte in the 
+                first operand, in the first bytes of the return value.
    • 
+            
  • the subtraction of the second byte in the second operand from the second byte in 
+                the first operand, in the second byte of the return value.
    • 
+            
  • the subtraction of the third byte in the second operand from the third byte in the 
+                first operand, in the third byte of the return value.
    • 
+            
  • the subtraction of the fourth byte in the second operand from the fourth byte in 
+                the first operand, in the fourth byte of the return value.
    • 
+          

+          
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
+             the results of the operation. If res is the return value, then:
+          

+          
    
+            
  • if res[8:0] ≥ 0 then APSR.GE[0] = 1 else 0
    • 
+            
  • if res[15:8] ≥ 0 then APSR.GE[1] = 1 else 0
    • 
+            
  • if res[23:16] ≥ 0 then APSR.GE[2] = 1 else 0
    • 
+            
  • if res[31:24] ≥ 0 then APSR.GE[3] = 1 else 0
    • 
+         
      
+      
Operation
+        
+res[7:0]   = val1[7:0]   - val2[7:0]
+res[15:8]  = val1[15:8]  - val2[15:8]
+res[23:16] = val1[23:16] - val2[23:16]
+res[31:24] = val1[31:24] - val2[31:24]

+      

+
+
Function __QSUB8

+
+  
+    
+      
+      
+    
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+    
+      
+      
+    
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+    
+      
+      
+    
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+    
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+      
+      
+    
+  
+
Summary
+        
+uint32_t __QADD8(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform four 8-bit integer subtractions, saturating the results 
+          to the 8-bit signed integer range -27 ≤ x ≤ 27 - 1.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit operands.
    • 
+          
  • val2: second four 8-bit operands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the subtraction of the first byte in the second operand from the first byte in the 
+                first operand, in the first byte of the return value.
    • 
+            
  • the subtraction of the second byte in the second operand from the second byte in 
+                the first operand, in the second byte of the return value.
    • 
+            
  • the subtraction of the third byte in the second operand from the third byte in the 
+                first operand, in the third byte of the return value.
    • 
+            
  • the subtraction of the fourth byte in the second operand from the fourth byte in 
+                the first operand, in the fourth byte of the return value.
    • 
+          

+          
The returned results are saturated to the 8-bit signed integer range -27 ≤ x ≤ 27 - 1.
+          

+      
Operation
+        
+res[7:0]   = val1[7:0]   - val2[7:0]
+res[15:8]  = val1[15:8]  - val2[15:8]
+res[23:16] = val1[23:16] - val2[23:16]
+res[31:24] = val1[31:24] - val2[31:24]

+      

+
+
Function __SHSUB8

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SHSUB8(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform four signed 8-bit integer subtractions, halving the 
+          results.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit operands.
    • 
+          
  • val2: second four 8-bit operands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the halved subtraction of the first byte in the second operand from the first byte 
+                in the first operand, in the first byte of the return value.
    • 
+            
  • the halved subtraction of the second byte in the second operand from the second 
+                byte in the first operand, in the second byte of the return value.
    • 
+            
  • the halved subtraction of the third byte in the second operand from the third byte 
+                in the first operand, in the third byte of the return value.
    • 
+            
  • the halved subtraction of the fourth byte in the second operand from the fourth 
+                byte in the first operand, in the fourth byte of the return value.
    • 
+          

+      
Operation
+        
+res[7:0]   = (val1[7:0]   - val2[7:0])  >> 1
+res[15:8]  = (val1[15:8]  - val2[15:8]) >> 1
+res[23:16] = (val1[23:16] - val2[23:16] >> 1
+res[31:24] = (val1[31:24] - val2[31:24] >> 1

+      

+
+
Function __USUB8

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __USUB8(uint32_t val1, uint32_t val2);

+      
DescriptionThis function It enables you to perform four 8-bit unsigned integer subtractions.

+          The GE bits in the APSR are set according to the results.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit operands.
    • 
+          
  • val2: second four 8-bit operands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the subtraction of the first byte in the second operand from the first byte in the 
+                first operand, in the first byte of the return value.
    • 
+            
  • the subtraction of the second byte in the second operand from the second byte in 
+                the first operand, in the second byte of the return value.
    • 
+            
  • the subtraction of the third byte in the second operand from the third byte in the 
+                first operand, in the third byte of the return value.
    • 
+            
  • the subtraction of the fourth byte in the second operand from the fourth byte in 
+                the first operand, in the fourth byte of the return value.
    • 
+          

+          
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
+             the results of the operation.

+             If res is the return value, then:
+          

+          
    
+            
  • if res[7:0] ≥ 0 then APSR.GE[0] = 1 else 0
    • 
+            
  • if res[15:8] ≥ 0 then APSR.GE[1] = 1 else 0
    • 
+            
  • if res[23:16] ≥ 0 then APSR.GE[2] = 1 else 0
    • 
+            
  • if res[31:24] ≥ 0 then APSR.GE[3] = 1 else 0
    • 
+         
      
+      
Operation
+        
+res[7:0]   = val1[7:0]   - val2[7:0]
+res[15:8]  = val1[15:8]  - val2[15:8]
+res[23:16] = val1[23:16] - val2[23:16]
+res[31:24] = val1[31:24] - val2[31:24]

+      

+
+
Function __UQSUB8

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UQSUB8(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform four unsigned 8-bit integer subtractions, saturating 
+          the results to the 8-bit unsigned integer range 0 ≤ x ≤ 28 - 1.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit operands.
    • 
+          
  • val2: second four 8-bit operands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the subtraction of the first byte in the second operand from the first byte in the 
+                first operand, in the first byte of the return value.
    • 
+            
  • the subtraction of the second byte in the second operand from the second byte in 
+                the first operand, in the second byte of the return value.
    • 
+            
  • the subtraction of the third byte in the second operand from the third byte in the 
+                first operand, in the third byte of the return value.
    • 
+            
  • the subtraction of the fourth byte in the second operand from the fourth byte in 
+                the first operand, in the fourth byte of the return value.
    • 
+          

+          
The results are saturated to the 8-bit unsigned integer range 0 ≤ x ≤ 28 - 1.
+          

+      
Operation
+        
+res[7:0]   = val1[7:0]   - val2[7:0]
+res[15:8]  = val1[15:8]  - val2[15:8]
+res[23:16] = val1[23:16] - val2[23:16]
+res[31:24] = val1[31:24] - val2[31:24]

+      

+
+
Function __UHSUB8

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UHSUB8(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform four unsigned 8-bit integer subtractions, halving the 
+          results.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit operands.
    • 
+          
  • val2: second four 8-bit operands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the halved subtraction of the first byte in the second operand from the first byte 
+                in the first operand, in the first byte of the return value.
    • 
+            
  • the halved subtraction of the second byte in the second operand from the second 
+                byte in the first operand, in the second byte of the return value.
    • 
+            
  • the halved subtraction of the third byte in the second operand from the third byte 
+                in the first operand, in the third byte of the return value.
    • 
+            
  • the halved subtraction of the fourth byte in the second operand from the fourth 
+                byte in the first operand, in the fourth byte of the return value.
    • 
+          

+      
Operation
+        
+res[7:0]   = (val1[7:0]   - val2[7:0])   >> 1
+res[15:8]  = (val1[15:8]  - val2[15:8])  >> 1
+res[23:16] = (val1[23:16] - val2[23:16]) >> 1
+res[31:24] = (val1[31:24] - val2[31:24]) >> 1

+      

+
+
Function __SADD16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SADD16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two 16-bit signed integer additions.

+          The GE bits in the APSR are set according to the results of the additions.
+      
Parameter
+        
    
+          
  • val1: first two 16-bit summands.
    • 
+          
  • val2: second two 16-bit summands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the addition of the low halfwords in the low halfword of the return value.
    • 
+            
  • the addition of the high halfwords in the high halfword of the return value.
    • 
+          

+          
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on
+             the results of the operation.

+             If res is the return value, then:
+          

+          
    
+            
  • if res[15:0] ≥ 0 then APSR.GE[1:0] = 11 else 00
    • 
+            
  • if res[31:16] ≥ 0 then APSR.GE[3:2] = 11 else 00
    • 
+         
      
+      
Operation
+        
+res[15:0]  = val1[15:0]  + val2[15:0]
+res[31:16] = val1[31:16] + val2[31:16]

+      

+
+
Function __QADD16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __QADD16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two 16-bit integer arithmetic additions in parallel, 
+          saturating the results to the 16-bit signed integer range -215 ≤ x ≤ 215 - 1.
+      
Parameter
+        
    
+          
  • val1: first two 16-bit summands.
    • 
+          
  • val2: second two 16-bit summands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the saturated addition of the low halfwords in the low halfword of the return value.
    • 
+            
  • the saturated addition of the high halfwords in the high halfword of the return value.
    • 
+          

+          
The returned results are saturated to the 16-bit signed integer 
+             range -215 ≤ x ≤ 215 - 1
+          

+      
Operation
+        
+res[15:0]  = val1[15:0]  + val2[15:0]
+res[16:31] = val1[31:16] + val2[31:16]

+      

+
+
Function __SHADD16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SHADD16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two signed 16-bit integer additions, halving the 
+          results.
+      
Parameter
+        
    
+          
  • val1: first two 16-bit summands.
    • 
+          
  • val2: second two 16-bit summands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the halved addition of the low halfwords from each operand, in the low halfword 
+                of the return value.
    • 
+            
  • the halved addition of the high halfwords from each operand, in the high halfword 
+                of the return value.
    • 
+          

+      
Operation
+        
+res[15:0]  = (val1[15:0]  + val2[15:0])  >> 1
+res[31:16] = (val1[31:16] + val2[31:16]) >> 1

+      

+
+
Function __UADD16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UADD16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two 16-bit unsigned integer additions.

+          The GE bits in the APSR are set according to the results.
+      
Parameter
+        
    
+          
  • val1: first two 16-bit summands for each addition.
    • 
+          
  • val2: second two 16-bit summands for each addition.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the addition of the low halfwords in each operand, in the low halfword of the 
+                return value.
    • 
+            
  • the addition of the high halfwords in each operand, in the high halfword of the 
+                return value.
    • 
+          

+          
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
+             the results of the operation.

+             If res is the return value, then:
+          

+          
    
+            
  • if res[15:0] ≥ 0x10000 then APSR.GE[0] = 11 else 00
    • 
+            
  • if res[31:16] ≥ 0x10000 then APSR.GE[1] = 11 else 00
    • 
+         
      
+      
Operation
+        
+res[15:0]  = val1[15:0]  + val2[15:0]
+res[31:16] = val1[31:16] + val2[31:16]

+      

+
+
Function __UQADD16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UQADD16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two unsigned 16-bit integer additions, saturating the 
+          results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 - 1.
+      
Parameter
+        
    
+          
  • val1: first two 16-bit summands.
    • 
+          
  • val2: second two 16-bit summands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the addition of the low halfword in the first operand and the low halfword in the 
+                second operand, in the low halfword of the return value.
    • 
+            
  • the addition of the high halfword in the first operand and the high halfword in the 
+                second operand, in the high halfword of the return value.
    • 
+          

+          
The results are saturated to the 16-bit unsigned integer 
+             range 0 ≤ x ≤ 216 - 1.
+          

+      
Operation
+        
+res[15:0]  = val1[15:0]  + val2[15:0]
+res[31:16] = val1[31:16] + val2[31:16]

+      

+
+
Function __UHADD16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UHADD16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two unsigned 16-bit integer additions, halving the 
+          results.
+      
Parameter
+        
    
+          
  • val1: first two 16-bit summands.
    • 
+          
  • val2: second two 16-bit summands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the halved addition of the low halfwords in each operand, in the low halfword of 
+                the return value.
    • 
+            
  • the halved addition of the high halfwords in each operand, in the high halfword 
+                of the return value.
    • 
+          

+      
Operation
+        
+res[15:0]  = (val1[15:0]  + val2[15:0])  >> 1
+res[31:16] = (val1[31:16] + val2[31:16]) >> 1

+      

+
+
Function __SSUB16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SSUB16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two 16-bit signed integer subtractions.

+          The GE bits in the APSR are set according to the results.
+      
Parameter
+        
    
+          
  • val1: first two 16-bit operands of each subtraction.
    • 
+          
  • val2: second two 16-bit operands of each subtraction.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the subtraction of the low halfword in the second operand from the low halfword 
+                in the first operand, in the low halfword of the return value.
    • 
+            
  • the subtraction of the high halfword in the second operand from the high halfword 
+                in the first operand, in the high halfword of the return value.
    • 
+          

+          
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
+             the results of the operation.

+             If res is the return value, then:
+          

+          
    
+            
  • if res[15:0] ≥ 0 then APSR.GE[1:0] = 11 else 00
    • 
+            
  • if res[31:16] ≥ 0 then APSR.GE[3:2] = 11 else 00
    • 
+         
      
+      
Operation
+        
+res[15:0]  = val1[15:0]  - val2[15:0]
+res[31:16] = val1[31:16] - val2[31:16]

+      

+
+
Function __QSUB16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __QSUB16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two 16-bit integer subtractions, saturating the 
+          results to the 16-bit signed integer range -215 ≤ x ≤ 215 - 1.
+      
Parameter
+        
    
+          
  • val1: first two 16-bit operands.
    • 
+          
  • val2: second two 16-bit operands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the saturated subtraction of the low halfword in the second operand from the low 
+                halfword in the first operand, in the low halfword of the returned result.
    • 
+            
  • the saturated subtraction of the high halfword in the second operand from the high 
+                halfword in the first operand, in the high halfword of the returned result.
    • 
+          

+          
The returned results are saturated to the 16-bit signed integer 
+             range -215 ≤ x ≤ 215 - 1.
+          

+      
Operation
+        
+res[15:0]  = val1[15:0]  - val2[15:0]
+res[31:16] = val1[31:16] - val2[31:16]

+      

+
+
Function __SHSUB16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SHSUB16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two signed 16-bit integer subtractions, halving the 
+          results.
+      
Parameter
+        
    
+          
  • val1: first two 16-bit operands.
    • 
+          
  • val2: second two 16-bit operands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the halved subtraction of the low halfword in the second operand from the low 
+                halfword in the first operand, in the low halfword of the return value.
    • 
+            
  • the halved subtraction of the high halfword in the second operand from the high 
+                halfword in the first operand, in the high halfword of the return value.
    • 
+          

+      
Operation
+        
+res[15:0]  = (val1[15:0]  - val2[15:0])  >> 1
+res[31:16] = (val1[31:16] - val2[31:16]) >> 1

+      

+
+
Function __USUB16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __USUB16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two 16-bit unsigned integer subtractions.

+          The GE bits in the APSR are set according to the results.
+      
Parameter
+        
    
+          
  • val1: first two 16-bit operands.
    • 
+          
  • val2: second two 16-bit operands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the subtraction of the low halfword in the second operand from the low halfword 
+                in the first operand, in the low halfword of the return value.
    • 
+            
  • the subtraction of the high halfword in the second operand from the high halfword 
+                in the first operand, in the high halfword of the return value.
    • 
+          

+          
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on
+             the results of the operation.

+             If res is the return value, then:
+          

+          
    
+            
  • if res[15:0] ≥ 0 then APSR.GE[1:0] = 11 else 00
    • 
+            
  • if res[31:16] ≥ 0 then APSR.GE[3:2] = 11 else 00
    • 
+         
      
+      
Operation
+        
+res[15:0]  = val1[15:0]  - val2[15:0]
+res[31:16] = val1[31:16] - val2[31:16]

+      

+
+
Function __UQSUB16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UQSUB16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two unsigned 16-bit integer subtractions, saturating 
+          the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 - 1.
+      
Parameter
+        
    
+          
  • val1: first two 16-bit operands for each subtraction.
    • 
+          
  • val2: second two 16-bit operands for each subtraction.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the subtraction of the low halfword in the second operand from the low halfword 
+                in the first operand, in the low halfword of the return value.
    • 
+            
  • the subtraction of the high halfword in the second operand from the high halfword 
+                in the first operand, in the high halfword of the return value.
    • 
+          

+          
The results are saturated to the 16-bit unsigned integer range 0 ≤ x ≤ 216 - 1.
+          

+      
Operation
+        
+res[15:0]  = val1[15:0]  - val2[15:0]
+res[31:16] = val1[31:16] - val2[31:16]

+      

+
+
Function __UHSUB16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UHSUB16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two unsigned 16-bit integer subtractions, halving 
+          the results.
+      
Parameter
+        
    
+          
  • val1: first two 16-bit operands.
    • 
+          
  • val2: second two 16-bit operands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the halved subtraction of the low halfword in the second operand from the low 
+                halfword in the first operand, in the low halfword of the return value.
    • 
+            
  • the halved subtraction of the high halfword in the second operand from the high 
+                halfword in the first operand, in the high halfword of the return value.
    • 
+          

+      
Operation
+        
+res[15:0]  = (val1[15:0]  - val2[15:0])  >> 1
+res[31:16] = (val1[31:16] - val2[31:16]) >> 1

+      

+
+
Function __SASX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SASX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function inserts an SASX instruction into the instruction stream generated by the 
+          compiler. It enables you to exchange the halfwords of the second operand, add the high 
+          halfwords and subtract the low halfwords.

+          The GE bits in the APRS are set according to the results.
+      
Parameter
+        
    
+          
  • val1: first operand for the subtraction in the low halfword, and the
+              first operand for the addition in the high halfword.
    • 
+          
  • val2: second operand for the subtraction in the high halfword, and the 
+              second operand for the addition in the low halfword.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the subtraction of the high halfword in the second operand from the low halfword 
+                in the first operand, in the low halfword of the return value.
    • 
+            
  • the addition of the high halfword in the first operand and the low halfword in the 
+                second operand, in the high halfword of the return value.
    • 
+          

+          
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on
+             the results of the operation.

+             If res is the return value, then:
+          

+          
    
+            
  • if res[15:0] ≥ 0 then APSR.GE[1:0] = 11 else 00
    • 
+            
  • if res[31:16] ≥ 0 then APSR.GE[3:2] = 11 else 00
    • 
+         
      
+      
Operation
+        
+res[15:0]  = val1[15:0] - val2[31:16]
+res[31:16] = val1[31:16] + val2[15:0]

+      

+
+
Function __QASX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __QASX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to exchange the halfwords of the one operand, then add the high
+          halfwords and subtract the low halfwords, saturating the results to the 16-bit signed 
+          integer range -215 ≤ x ≤ 215 - 1.
+      
Parameter
+        
    
+          
  • val1: first operand for the subtraction in the low halfword, and the 
+                       first operand for the addition in the high halfword.
    • 
+          
  • val2: second operand for the subtraction in the high halfword, and the
+                       second operand for the addition in the low halfword.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the saturated subtraction of the high halfword in the second operand from the low 
+                halfword in the first operand, in the low halfword of the return value.
    • 
+            
  • the saturated addition of the high halfword in the first operand and the low 
+                halfword in the second operand, in the high halfword of the return value.
    • 
+          

+          
The returned results are saturated to the 16-bit signed integer 
+             range -215 ≤ x ≤ 215 - 1.
+          

+      
Operation
+        
+res[15:0]  = val1[15:0]  - val2[31:16]
+res[31:16] = val1[31:16] + val2[15:0]

+      

+
+
Function __SHASX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SHASX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to exchange the two halfwords of one operand, perform one 
+          signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands.
    • 
+          
  • val2: second 16-bit operands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the halved subtraction of the high halfword in the second operand from the low 
+                halfword in the first operand, in the low halfword of the return value.
    • 
+            
  • the halved subtraction of the low halfword in the second operand from the high 
+                halfword in the first operand, in the high halfword of the return value.
    • 
+          

+      
Operation
+        
+res[15:0]  = (val1[15:0]  - val2[31:16]) >> 1
+res[31:16] = (val1[31:16] - val2[15:0])  >> 1

+      

+
+
Function __UASX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UASX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to exchange the two halfwords of the second operand, add the 
+          high halfwords and subtract the low halfwords.

+          The GE bits in the APSR are set according to the results.
+      
Parameter
+        
    
+          
  • val1: first operand for the subtraction in the low halfword, and the
+              first operand for the addition in the high halfword.
    • 
+          
  • val2: second operand for the subtraction in the high halfword and the
+              second operand for the addition in the low halfword.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the subtraction of the high halfword in the second operand from the low halfword 
+                in the first operand, in the low halfword of the return value.
    • 
+            
  • the addition of the high halfword in the first operand and the low halfword in the 
+                second operand, in the high halfword of the return value.
    • 
+          

+          
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
+             the results of the operation.

+             If res is the return value, then:
+          

+          
    
+            
  • if res[15:0] ≥ 0 then APSR.GE[1:0] = 11 else 00
    • 
+            
  • if res[31:16] ≥ 0x10000 then APSR.GE[3:2] = 11 else 00
    • 
+         
      
+      
Operation
+        
+res[15:0]  = val1[15:0]  - val2[31:16]
+res[31:16] = val1[31:16] + val2[15:0]

+      

+
+
Function __UQASX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UQASX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to exchange the halfwords of the second operand and perform 
+          one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturating the 
+          results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 - 1.
+      
Parameter
+        
    
+          
  • val1: first two 16-bit operands.
    • 
+          
  • val2: second two 16-bit operands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the subtraction of the high halfword in the second operand from the low halfword 
+                in the first operand, in the low halfword of the return value.
    • 
+            
  • the subtraction of the low halfword in the second operand from the high halfword 
+                in the first operand, in the high halfword of the return value.
    • 
+          

+          
The results are saturated to the 16-bit unsigned integer  
+             range 0 ≤ x ≤ 216 - 1.
+          

+      
Operation
+        
+res[15:0]  = val1[15:0]  - val2[31:16]
+res[31:16] = val1[31:16] + val2[15:0]

+      

+
+
Function __UHASX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UHASX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to exchange the halfwords of the second operand, add the high 
+          halfwords and subtract the low halfwords, halving the results.
+      
Parameter
+        
    
+          
  • val1: first operand for the subtraction in the low halfword, and the
+           first operand for the addition in the high halfword.
    • 
+          
  • val2: second operand for the subtraction in the high halfword, and the 
+           second operand for the addition in the low halfword.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the halved subtraction of the high halfword in the second operand from the low 
+                halfword in the first operand.
    • 
+            
  • the halved addition of the high halfword in the first operand and the low halfword 
+                in the second operand.
    • 
+          

+      
Operation
+        
+res[15:0]  = (val1[15:0]  - val2[31:16]) >> 1
+res[31:16] = (val1[31:16] + val2[15:0])  >> 1

+      

+
+
Function __SSAX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SSAX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to exchange the two halfwords of one operand and perform one 
+          16-bit integer subtraction and one 16-bit addition.

+          The GE bits in the APSR are set according to the results.
+      
Parameter
+        
    
+          
  • val1: first operand for the addition in the low halfword, and the first 
+              operand for the subtraction in the high halfword.
    • 
+          
  • val2: second operand for the addition in the high halfword, and the
+              second operand for the subtraction in the low halfword.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the addition of the low halfword in the first operand and the high halfword in the 
+                second operand, in the low halfword of the return value.
    • 
+            
  • the subtraction of the low halfword in the second operand from the high halfword 
+                in the first operand, in the high halfword of the return value.
    • 
+          

+          
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
+             the results of the operation.

+             If res is the return value, then:
+          

+          
    
+            
  • if res[15:0] ≥ 0 then APSR.GE[1:0] = 11 else 00
    • 
+            
  • if res[31:16] ≥ 0 then APSR.GE[3:2] = 11 else 00
    • 
+         
      
+      
Operation
+        
+res[15:0]  = val1[15:0]  + val2[31:16]
+res[31:16] = val1[31:16] - val2[15:0]

+      

+
+
Function __QSAX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __QSAX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to exchange the halfwords of one operand, then subtract the 
+          high halfwords and add the low halfwords, saturating the results to the 16-bit signed 
+          integer range -215 ≤ x ≤ 215 - 1.
+      
Parameter
+        
    
+          
  • val1: first operand for the addition in the low halfword, and the first
+           operand for the subtraction in the high halfword.
    • 
+          
  • val2: second operand for the addition in the high halfword, and the 
+           second operand for the subtraction in the low halfword.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the saturated addition of the low halfword of the first operand and the high 
+                halfword of the second operand, in the low halfword of the return value.
    • 
+            
  • the saturated subtraction of the low halfword of the second operand from the high 
+                halfword of the first operand, in the high halfword of the return value.
    • 
+          

+          
The returned results are saturated to the 16-bit signed integer 
+             range -215 ≤ x ≤ 215 - 1.
+          

+      
Operation
+        
+res[15:0]  = val1[15:0]  + val2[31:16]
+res[31:16] = val1[31:16] - val2[15:0]

+      

+
+
Function __SHSAX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SHSAX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to exchange the two halfwords of one operand, perform one 
+          signed 16-bit integer subtraction and one signed 16-bit addition, and halve the results.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands.
    • 
+          
  • val2: second 16-bit operands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the halved addition of the low halfword in the first operand and the high halfword 
+                in the second operand, in the low halfword of the return value.
    • 
+            
  • the halved subtraction of the low halfword in the second operand from the high 
+                halfword in the first operand, in the high halfword of the return value.
    • 
+          

+      
Operation
+        
+res[15:0]  = (val1[15:0]  + val2[31:16]) >> 1
+res[31:16] = (val1[31:16] - val2[15:0])  >> 1

+      

+
+
Function __USAX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __USAX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to exchange the halfwords of the second operand, subtract the 
+          high halfwords and add the low halfwords.

+          The GE bits in the APSR are set according to the results.
+      
Parameter
+        
    
+          
  • val1: first operand for the addition in the low halfword, and the first
+              operand for the subtraction in the high halfword.
    • 
+          
  • val2: second operand for the addition in the high halfword, and the
+              second operand for the subtraction in the low halfword.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the addition of the low halfword in the first operand and the high halfword in the 
+                second operand, in the low halfword of the return value.
    • 
+            
  • the subtraction of the low halfword in the second operand from the high halfword 
+                in the first operand, in the high halfword of the return value.
    • 
+          

+          
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
+             the results of the operation.

+             If res is the return value, then:
+          

+          
    
+            
  • if res[15:0] ≥ 0x10000 then APSR.GE[1:0] = 11 else 00
    • 
+            
  • if res[31:16] ≥ 0 then APSR.GE[3:2] = 11 else 00
    • 
+         
      
+      
Operation
+        
+res[15:0]  = val1[15:0]  + val2[31:16]
+res[31:16] = val1[31:16] - val2[15:0]

+      

+
+
Function __UQSAX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UQSAX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to exchange the halfwords of the second operand and perform 
+          one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating the 
+          results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 - 1.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operand for the addition in the low halfword, and the
+              first 16-bit operand for the subtraction in the high halfword.
    • 
+          
  • val2: second 16-bit halfword for the addition in the high halfword,
+              and the second 16-bit halfword for the subtraction in the low halfword.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the addition of the low halfword in the first operand and the high halfword in the 
+                second operand, in the low halfword of the return value.
    • 
+            
  • the subtraction of the low halfword in the second operand from the high halfword 
+                in the first operand, in the high halfword of the return value.
    • 
+          

+          
The results are saturated to the 16-bit unsigned integer 
+             range 0 ≤ x ≤ 216 - 1.
+          

+      
Operation
+        
+res[15:0]  = val1[15:0]  + val2[31:16]
+res[31:16] = val1[31:16] - val2[15:0]

+      

+
+
Function __UHSAX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UHSAX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to exchange the halfwords of the second operand, subtract the 
+          high halfwords and add the low halfwords, halving the results.
+      
Parameter
+        
    
+          
  • val1: first operand for the addition in the low halfword, and the first
+              operand for the subtraction in the high halfword.
    • 
+          
  • val2: second operand for the addition in the high halfword, and the
+              second operand for the subtraction in the low halfword.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the halved addition of the high halfword in the second operand and the low 
+                halfword in the first operand, in the low halfword of the return value.
    • 
+            
  • the halved subtraction of the low halfword in the second operand from the high 
+                halfword in the first operand, in the high halfword of the return value.
    • 
+          

+      
Operation
+        
+res[15:0]  = (val1[15:0]  + val2[31:16]) >> 1
+res[31:16] = (val1[31:16] - val2[15:0])  >> 1

+      

+
+
Function __USAD8

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __USAD8(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform four unsigned 8-bit subtractions, and add the 
+          absolute values of the differences together, returning the result as a single unsigned 
+          integer.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit operands for the subtractions.
    • 
+          
  • val2: second four 8-bit operands for the subtractions.
    • 
+        

+      
Return Value
+         
The function returns the sum of the absolute differences of:

+         
    
+            
  • the subtraction of the first byte in the second operand from the first byte in the 
+                first operand.
    • 
+            
  • the subtraction of the second byte in the second operand from the second byte in 
+                the first operand.
    • 
+            
  • the subtraction of the third byte in the second operand from the third byte in the 
+                first operand.
    • 
+            
  • the subtraction of the fourth byte in the second operand from the fourth byte in 
+                the first operand.
    • 
+          

+          
The sum is returned as a single unsigned integer.

+      
Operation
+        
+absdiff1  = val1[7:0]   - val2[7:0]
+absdiff2  = val1[15:8]  - val2[15:8]
+absdiff3  = val1[23:16] - val2[23:16]
+absdiff4  = val1[31:24] - val2[31:24]
+res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4

+      

+
+
Function __USADA8

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __USADA8(uint32_t val1, uint32_t val2, uint32_t val3);

+      
DescriptionThis function enables you to perform four unsigned 8-bit subtractions, and add the 
+          absolute values of the differences to a 32-bit accumulate operand.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit operands for the subtractions.
    • 
+          
  • val2: second four 8-bit operands for the subtractions.
    • 
+          
  • val3: accumulation value.
    • 
+        

+      
Return Value
+         
The function returns the sum of the absolute differences of the following 
+            bytes, added to the accumulation value:

+         
    
+            
  • the subtraction of the first byte in the second operand from the first byte in the 
+                first operand.
    • 
+            
  • the subtraction of the second byte in the second operand from the second byte in 
+                the first operand.
    • 
+            
  • the subtraction of the third byte in the second operand from the third byte in the 
+                first operand.
    • 
+            
  • the subtraction of the fourth byte in the second operand from the fourth byte in 
+                the first operand.
    • 
+          

+      
Operation
+        
+absdiff1  = val1[7:0]   - val2[7:0]
+absdiff2  = val1[15:8]  - val2[15:8]
+absdiff3  = val1[23:16] - val2[23:16]
+absdiff4  = val1[31:24] - val2[31:24]
+sum       = absdiff1 + absdiff2 + absdiff3 + absdiff4
+res[31:0] = sum[31:0] + val3[31:0]

+      

+
+
Function __SSAT16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SSAT16(uint32_t val1, const uint32_t val2);

+      
DescriptionThis function enables you to saturate two signed 16-bit values to a selected signed range.

+          The Q bit is set if either operation saturates.
+      
Parameter
+        
    
+          
  • val1: two signed 16-bit values to be saturated.
    • 
+          
  • val2: bit position for saturation, an integral constant expression in the
+              range 1 to 16.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the signed saturation of the low halfword in val1, saturated to the bit position 
+                specified in val2 and returned in the low halfword of the return value.
    • 
+            
  • the signed saturation of the high halfword in val1, saturated to the bit position 
+                specified in val2 and returned in the high halfword of the return value.
    • 
+          

+      
Operation
+        
+Saturate halfwords in val1 to the signed range specified by the bit position in val2

+      

+
+
Function __USAT16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __USAT16(uint32_t val1, const uint32_t val2);

+      
DescriptionThis function enables you to saturate two signed 16-bit values to a selected unsigned 
+         range.

+         The Q bit is set if either operation saturates.
+      
Parameter
+        
    
+          
  • val1: two 16-bit values that are to be saturated.
    • 
+          
  • val2: bit position for saturation, and must be an integral constant 
+           expression in the range 0 to 15.
    • 
+        

+      
Return Value
+         
The function returns the saturation of the two signed 16-bit values, as non-negative values.

+         
    
+            
  • the saturation of the low halfword in val1, saturated to the bit position 
+                specified in val2 and returned in the low halfword of the return value.
    • 
+            
  • the saturation of the high halfword in val1, saturated to the bit position 
+                specified in val2 and returned in the high halfword of the return value.
    • 
+          

+      
Operation
+        
+Saturate halfwords in val1 to the unsigned range specified by the bit position in val2

+      

+
+
Function __UXTB16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UXTB16(uint32_t val);

+      
DescriptionThis function enables you to extract two 8-bit values from an operand and zero-extend 
+          them to 16 bits each.
+      
Parameter
+        
    
+          
  • val1: two 8-bit values in val[7:0] and val[23:16] to be sign-extended.
    • 
+        

+      
Return Value
+         
The function returns the 8-bit values zero-extended to 16-bit values.

+         
    
+            
  • zero-extended value of val[7:0] in the low halfword of the return value.
    • 
+            
  • zero-extended value of val[23:16] in the high halfword of the return value.
    • 
+          

+      
Operation
+        
+res[15:0]  = ZeroExtended(val[7:0]  )
+res[31:16] = ZeroExtended(val[23:16])

+      

+
+
Function __UXTAB16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UXTAB16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to extract two 8-bit values from one operand, zero-extend them 
+          to 16 bits each, and add the results to two 16-bit values from another operand.
+      
Parameter
+        
    
+          
  • val1: value added to the zero-extended to 16-bit values.
    • 
+          
  • val2: two 8-bit values to be extracted and zero-extended.
    • 
+        

+      
Return Value
+         
The function returns the 8-bit values in val2, zero-extended to 16-bit values 
+            and added to val1.

+      
Operation
+        
+res[15:0]  = ZeroExt(val2[7:0]   to 16 bits) + val1[15:0]
+res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16]

+      

+
+
Function __SXTB16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SXTB16(uint32_t val);

+      
DescriptionThis function enables you to extract two 8-bit values from an operand and sign-extend 
+          them to 16 bits each.
+      
Parameter
+        
    
+          
  • val1: two 8-bit values in val[7:0] and val[23:16] to be sign-extended.
    • 
+        

+      
Return Value
+         
The function returns the 8-bit values sign-extended to 16-bit values.

+         
    
+            
  • sign-extended value of val[7:0] in the low halfword of the return value.
    • 
+            
  • sign-extended value of val[23:16] in the high halfword of the return value.
    • 
+          

+      
Operation
+        
+res[15:0]  = SignExtended(val[7:0]
+res[31:16] = SignExtended(val[23:16]

+      

+
+
Function __SXTAB16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SXTAB16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to extract two 8-bit values from the second operand (at bit 
+          positions [7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the 
+          first operand.
+      
Parameter
+        
    
+          
  • val1: values added to the zero-extended to 16-bit values.
    • 
+          
  • val2: two 8-bit values to be extracted and zero-extended.
    • 
+        

+      
Return Value
+         
The function returns the addition of val1 and val2, where the 8-bit values in 
+            val2[7:0] and val2[23:16] have been extracted and sign-extended prior to the addition.

+      
Operation
+        
+res[15:0]  = val1[15:0]  + SignExtended(val2[7:0])
+res[31:16] = val1[31:16] + SignExtended(val2[23:16])

+      

+
+
Function __SMUAD

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SMUAD(uint32_t val1, uint32_t val2);

+      
DescriptionThis function It enables you to perform two 16-bit signed multiplications, adding the 
+          products together.

+          The Q bit is set if the addition overflows.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands for each multiplication.
    • 
+          
  • val2: second 16-bit operands for each multiplication.
    • 
+        

+      
Return Value
+         
The function returns the sum of the products of the two 16-bit signed multiplications.

+      
Operation
+        
+p1 = val1[15:0]  * val2[15:0]
+p2 = val1[31:16] * val2[31:16]
+res[31:0] = p1 + p2

+      

+
+
Function __SMUADX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SMUADX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two 16-bit signed multiplications with exchanged
+          halfwords of the second operand, adding the products together.

+          The Q bit is set if the addition overflows.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands for each multiplication.
    • 
+          
  • val2: second 16-bit operands for each multiplication.
    • 
+        

+      
Return Value
+         
The function returns the sum of the products of the two 16-bit signed multiplications with exchanged
+            halfwords of the second operand.

+      
Operation
+        
+p1 = val1[15:0]  * val2[31:16]
+p2 = val1[31:16] * val2[15:0]
+res[31:0] = p1 + p2

+      

+
+
Function __SMLAD

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SMLAD(uint32_t val1, uint32_t val2, uint32_t val3);

+      
DescriptionThis function enables you to perform two signed 16-bit multiplications, adding both 
+          results to a 32-bit accumulate operand.

+          The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands for each multiplication.
    • 
+          
  • val2: second 16-bit operands for each multiplication.
    • 
+          
  • val2: accumulate value.
    • 
+        

+      
Return Value
+         
The function returns the product of each multiplication added to the accumulate 
+            value, as a 32-bit integer.

+      
Operation
+        
+p1 = val1[15:0]  * val2[15:0]
+p2 = val1[31:16] * val2[31:16]
+res[31:0] = p1 + p2 + val3[31:0]

+      

+
+
Function __SMLADX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SMLADX(uint32_t val1, uint32_t val2, uint32_t val3);

+      
DescriptionThis function enables you to perform two signed 16-bit multiplications with exchanged
+          halfwords of the second operand, adding both results to a 32-bit accumulate operand.

+          The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands for each multiplication.
    • 
+          
  • val2: second 16-bit operands for each multiplication.
    • 
+          
  • val2: accumulate value.
    • 
+        

+      
Return Value
+         
The function returns the product of each multiplication with exchanged
+            halfwords of the second operand added to the accumulate value, as a 32-bit integer.

+      
Operation
+        
+p1 = val1[15:0]  * val2[31:16]
+p2 = val1[31:16] * val2[15:0]
+res[31:0] = p1 + p2 + val3[31:0]

+      

+
+
Function __SMLALD

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint64_t __SMLALD(uint32_t val1, uint32_t val2, uint64_t val3);

+      
DescriptionThis function enables you to perform two signed 16-bit multiplications, adding both 
+          results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit 
+          addition. This overflow is not detected if it occurs. Instead, the result wraps around 
+          modulo264.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands for each multiplication.
    • 
+          
  • val2: second 16-bit operands for each multiplication.
    • 
+          
  • val2: accumulate value.
    • 
+        

+      
Return Value
+         
The function returns the product of each multiplication added to the accumulate value.

+      
Operation
+        
+p1 = val1[15:0]  * val2[15:0]
+p2 = val1[31:16] * val2[31:16]
+sum = p1 + p2 + val3[63:32][31:0]
+res[63:32] = sum[63:32]
+res[31:0]  = sum[31:0]

+      

+
+
Function __SMLALDX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+unsigned long long __SMLALDX(uint32_t val1, uint32_t val2, unsigned long long val3);

+      
DescriptionThis function enables you to exchange the halfwords of the second operand, and perform 
+          two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. 
+          Overflow is only possible as a result of the 64-bit addition. This overflow is not detected 
+          if it occurs. Instead, the result wraps around modulo264.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands for each multiplication.
    • 
+          
  • val2: second 16-bit operands for each multiplication.
    • 
+          
  • val2: accumulate value.
    • 
+        

+      
Return Value
+         
The function returns the product of each multiplication added to the accumulate value.

+      
Operation
+        
+p1 = val1[15:0]  * val2[31:16]
+p2 = val1[31:16] * val2[15:0]
+sum = p1 + p2 + val3[63:32][31:0]
+res[63:32] = sum[63:32]
+res[31:0] = sum[31:0]

+      

+
+
Function __SMUSD

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SMUSD(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two 16-bit signed multiplications, taking the 
+          difference of the products by subtracting the high halfword product from the low 
+          halfword product.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands for each multiplication.
    • 
+          
  • val2: second 16-bit operands for each multiplication.
    • 
+        

+      
Return Value
+         
The function returns the difference of the products of the two 16-bit signed multiplications.

+      
Operation
+        
+p1 = val1[15:0]  * val2[15:0]
+p2 = val1[31:16] * val2[31:16]
+res[31:0] = p1 - p2

+      

+
+
Function __SMUSDX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SMUSDX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two 16-bit signed multiplications, subtracting one 
+          of the products from the other. The halfwords of the second operand are exchanged 
+          before performing the arithmetic. This produces top * bottom and bottom * top 
+          multiplication.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands for each multiplication.
    • 
+          
  • val2: second 16-bit operands for each multiplication.
    • 
+        

+      
Return Value
+         
The function returns the difference of the products of the two 16-bit signed multiplications.

+      
Operation
+        
+p1 = val1[15:0]  * val2[31:16]
+p2 = val1[31:16] * val2[15:0]
+res[31:0] = p1 - p2

+      

+
+
Function __SMLSD

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SMLSD(uint32_t val1, uint32_t val2, uint32_t val3);

+      
DescriptionThis function enables you to perform two 16-bit signed multiplications, take the 
+          difference of the products, subtracting the high halfword product from the low halfword 
+          product, and add the difference to a 32-bit accumulate operand.

+          The Q bit is set if the accumulation overflows. Overflow cannot occur during the multiplications or the 
+          subtraction.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands for each multiplication.
    • 
+          
  • val2: second 16-bit operands for each multiplication.
    • 
+          
  • val3: accumulate value.
    • 
+        

+      
Return Value
+         
The function returns the difference of the product of each multiplication, added 
+            to the accumulate value.

+      
Operation
+        
+p1 = val1[15:0]  * val2[15:0]
+p2 = val1[31:16] * val2[31:16]
+res[31:0] = p1 - p2 + val3[31:0]

+      

+
+
Function __SMLSDX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SMLSDX(uint32_t val1, uint32_t val2, uint32_t val3);

+      
DescriptionThis function enables you to exchange the halfwords in the second operand, then perform 
+          two 16-bit signed multiplications. The difference of the products is added to a 32-bit 
+          accumulate operand.

+          The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications or the subtraction.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands for each multiplication.
    • 
+          
  • val2: second 16-bit operands for each multiplication.
    • 
+          
  • val3: accumulate value.
    • 
+        

+      
Return Value
+         
The function returns the difference of the product of each multiplication, added 
+            to the accumulate value.

+      
Operation
+        
+p1 = val1[15:0]  * val2[31:16]
+p2 = val1[31:16] * val2[15:0]
+res[31:0] = p1 - p2 + val3[31:0]

+      

+
+
Function __SMLSLD

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint64_t __SMLSLD(uint32_t val1, uint32_t val2, uint64_t val3);

+      
DescriptionThis function It enables you to perform two 16-bit signed multiplications, take the 
+          difference of the products, subtracting the high halfword product from the low halfword 
+          product, and add the difference to a 64-bit accumulate operand. Overflow cannot occur 
+          during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit 
+          addition, and this overflow is not detected. Instead, the result wraps round to  
+          modulo264.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands for each multiplication.
    • 
+          
  • val2: second 16-bit operands for each multiplication.
    • 
+          
  • val3: accumulate value.
    • 
+        

+      
Return Value
+         
The function returns the difference of the product of each multiplication, 
+            added to the accumulate value.

+      
Operation
+        
+p1 = val1[15:0]  * val2[15:0]
+p2 = val1[31:16] * val2[31:16]
+res[63:0] = p1 - p2 + val3[63:0]

+      

+
+
Function __SMLSLDX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+unsigned long long __SMLSLDX(uint32_t val1, uint32_t val2, unsigned long long val3);

+      
DescriptionThis function enables you to exchange the halfwords of the second operand, perform two 
+          16-bit multiplications, adding the difference of the products to a 64-bit accumulate 
+          operand. Overflow cannot occur during the multiplications or the subtraction. Overflow 
+          can occur as a result of the 64-bit addition, and this overflow is not detected. Instead, 
+          the result wraps round to modulo264.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands for each multiplication.
    • 
+          
  • val2: second 16-bit operands for each multiplication.
    • 
+          
  • val3: accumulate value.
    • 
+        

+      
Return Value
+         
The function returns the difference of the product of each multiplication, 
+            added to the accumulate value.

+      
Operation
+        
+p1 = val1[15:0]  * val2[31:16]
+p2 = val1[31:16] * val2[15:0]
+res[63:0] = p1 - p2 + val3[63:0]

+      

+
+
+
Function __SEL

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+  
+
Summary
+        
+uint32_t __SEL(uint32_t val1, uint32_t val2);

+      
DescriptionThis function inserts a SEL instruction into the instruction stream generated by the 
+          compiler. It enables you to select bytes from the input parameters, whereby the bytes 
+          that are selected depend upon the results of previous SIMD instruction function. The 
+          results of previous SIMD instruction function are represented by the Greater than or 
+          Equal flags in the Application Program Status Register (APSR).
+          The __SEL function works equally well on both halfword and byte operand function 
+          results. This is because halfword operand operations set two (duplicate) GE bits per 
+          value.
+      
Parameter
+        
    
+          
  • val1: four selectable 8-bit values.
    • 
+          
  • val2: four selectable 8-bit values.
    • 
+        

+      
Return Value
+         
The function selects bytes from the input parameters and returns them in the 
+            return value, res, according to the following criteria:

+         
    
+            
  • if APSR.GE[0] == 1 then res[7:0] = val1[7:0] else res[7:0] = val2[7:0]
    • 
+            
  • if APSR.GE[1] == 1 then res[15:8] = val1[15:8] else res[15:8] = val2[15:8]
    • 
+            
  • if APSR.GE[2] == 1 then res[23:16] = val1[23:16] else res[23:16] = val2[23:16]
    • 
+            
  • if APSR.GE[3] == 1 then res[31;24] = val1[31:24] else res = val2[31:24]
    • 
+          

+      

+
+
Function __QADD

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+  
+
Summary
+        
+uint32_t __QADD(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to obtain the saturating add of two integers.

+         The Q bit is set if the operation saturates.
+      
Parameter
+        
    
+          
  • val1: first summand of the saturating add operation.
    • 
+          
  • val2: second summand of the saturating add operation.
    • 
+        

+      
Return Value
+         
The function returns the saturating addition of val1 and val2.

+      
Operation
+        
+res[31:0] = SAT(val1 + SAT(val2 * 2))

+      

+
+
Function __QSUB

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+  
+
Summary
+        
+uint32_t __QSUB(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to obtain the saturating subtraction of two integers.

+         The Q bit is set if the operation saturates.
+      
Parameter
+        
    
+          
  • val1: minuend of the saturating subtraction operation.
    • 
+          
  • val2: subtrahend of the saturating subtraction operation.
    • 
+        

+      
Return Value
+         
The function returns the saturating subtraction of val1 and val2.

+      
Operation
+        
+res[31:0] = SAT(val1 - SAT(val2 * 2))

+      

+
+
+
+
 

+
Examples

+
Following are some coding examples using the SIMD functions:
+

+
+
+  
+    
+      
+      
+    
+ 
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+  
+
NameDescription
AdditionAdd two values using SIMD function
SubtractionSubtract two values using SIMD function
MultiplicationPerforming a multiplication using SIMD function

+
+
+
Addition

+
+  
+    
+      
+      
+    
+  
+
Example
+        
+uint32_t add_halfwords(uint32_t val1, uint32_t val2)
+{
+   uint32_t res;
+   res = __SADD16(val1, val2);
+   return res;
+}

+      

+
+
Subtraction

+
+  
+    
+      
+      
+    
+  
+
Example
+        
+uint32_t sub_halfwords(uint32_t val1, uint32_t val2)
+{
+  uint32_t res;
+  res = __SSUB16(val1, val2);
+  return res;
+}

+      

+
+
Multiplication

+
+  
+    
+      
+      
+    
+  
+
Example
+        
+uint32_t dual_mul_add_products(uint32_t val1, uint32_t val2)
+{
+  uint32_t res;
+  res = __SMUAD(val1, val2);
+  return res;
+}

+      

+
+
+
+
\ No newline at end of file
diff --git a/hardware/sam/system/CMSIS/Documentation/CMSIS_Core.htm b/hardware/sam/system/CMSIS/Documentation/CMSIS_Core.htm
new file mode 100644
index 000000000..d52ea1e08
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/CMSIS_Core.htm
@@ -0,0 +1,1470 @@
+
+
+  
+  CMSIS: Cortex Microcontroller Software Interface Standard
+  
+  
+
+
Cortex Microcontroller Software Interface Standard

+
+
This file describes the Cortex Microcontroller Software Interface Standard (CMSIS).

+
Version: 2.10 - July 2011

+
+
Information in this file, the accompany manuals, and software is

+                 Copyright © ARM Ltd.
All rights reserved.
+

+
+

+
+
Revision History

+
    
+	
  • Version 1.00: initial release. 
    • 
+	
  • Version 1.01: added __LDREXx, __STREXx, and __CLREX.
    • 
+	
  • Version 1.02: added Cortex-M0. 
    • 
+	
  • Version 1.10: second review. 
    • 
+	
  • Version 1.20: third review. 
    • 
+	
  • Version 1.30 PRE-RELEASE: reworked Startup Concept, additional Debug Functionality.
    • 
+	
  • Version 1.30 2nd PRE-RELEASE: changed folder structure, added doxyGen comments, added Bit definitions.
    • 
+	
  • Version 1.30: updated Device Support Packages.
    • 
+	
  • Version 2.00: added Cortex-M4 support.
    • 
+	
  • Version 2.01: internal review.
    • 
+	
  • Version 2.02: updated Device Specific Defines
    • 
+	
  • Version 2.10: reworked core include files
    • 
+

+
+

+
+
Contents

+
+
    
+  
  1. About
    2. 
+  
  2. Coding Rules and Conventions
    3. 
+  
  3. CMSIS Files
    4. 
+  
  4. Core Peripheral Access Layer
    5. 
+  
  5. CMSIS Example
    6. 
+  
  6. CMSIS MISRA-C:2004 Compliance Exceptions
    7. 
+

+
+
About

+
+

+  The Cortex Microcontroller Software Interface Standard (CMSIS) answers the challenges
+  that are faced when software components are deployed to physical microcontroller devices based on a
+  Cortex-M0 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M 
+  processor cores (the term Cortex-M is used to indicate that). The CMSIS is defined in close co-operation
+  with various silicon and software vendors and provides a common approach to interface to peripherals, 
+  real-time operating systems, and middleware components.
+

+
+
ARM provides as part of the CMSIS the following software layers that are
+available for various compiler implementations:

+
    
+  
  • Core Peripheral Access Layer: contains name definitions, 
+    address definitions and helper functions to
+    access core registers and peripherals. It defines also a device
+    independent interface for RTOS Kernels that includes debug channel
+    definitions.
    • 
+

+
+
These software layers are expanded by Silicon partners with:

+
    
+  
  • Device Peripheral Access Layer: provides definitions
+    for all device peripherals
    • 
+  
  • Access Functions for Peripherals (optional): provides
+    additional helper functions for peripherals
    • 
+

+
+
CMSIS defines for a Cortex-M Microcontroller System:

+
    
+  
  • A common way to access peripheral registers
+    and a common way to define exception vectors.
    • 
+  
  • The register names of the Core
+    Peripherals and the names of the Core
+    Exception Vectors.
    • 
+  
  • An device independent interface for RTOS Kernels including a debug
+    channel.
    • 
+

+
+

+  By using CMSIS compliant software components, the user can easier re-use template code. 
+  CMSIS is intended to enable the combination of software components from multiple middleware vendors.
+

+
+
Coding Rules and Conventions

+
+

+  The following section describes the coding rules and conventions used in the CMSIS 
+  implementation. It contains also information about data types and version number information.
+

+
+
Essentials

+
    
+  
  • The CMSIS C code conforms to MISRA 2004 rules. In case of MISRA violations, 
+      there are disable and enable sequences for PC-LINT inserted.
    • 
+  
  • ANSI standard data types defined in the ANSI C header file
+    <stdint.h> are used.
    • 
+  
  • #define constants that include expressions must be enclosed by
+    parenthesis.
    • 
+  
  • Variables and parameters have a complete data type.
    • 
+  
  • All functions in the Core Peripheral Access Layer are
+    re-entrant.
    • 
+  
  • The Core Peripheral Access Layer has no blocking code
+    (which means that wait/query loops are done at other software layers).
    • 
+  
  • For each exception/interrupt there is definition for:
+  
      
+    
    • an exception/interrupt handler with the postfix _Handler 
+	(for exceptions) or _IRQHandler (for interrupts).
      • 
+    
    • a default exception/interrupt handler (weak definition) that contains an endless loop.
      • 
+    
    • a #define of the interrupt number with the postfix _IRQn.
      • 
+  
    • 
+

+
+
Recommendations

+
+
The CMSIS recommends the following conventions for identifiers.

+
    
+  
  • CAPITAL names to identify Core Registers, Peripheral Registers, and CPU Instructions.
    • 
+  
  • CamelCase names to identify peripherals access functions and interrupts.
    • 
+  
  • PERIPHERAL_ prefix to identify functions that belong to specify peripherals.
    • 
+  
  • Doxygen comments for all functions are included as described under Function Comments below.
    • 
+

+
+Comments
+
+
    
+  
  • Comments use the ANSI C90 style (/* comment */) or C++ style 
+  (// comment). It is assumed that the programming tools support today 
+	consistently the C++ comment style.
    • 
+  
  • Function Comments provide for each function the following information:
+  
      
+    
    • one-line brief function overview.
      • 
+    
    • detailed parameter explanation.
      • 
+    
    • detailed information about return values.
      • 
+    
    • detailed description of the actual function.
      • 
+  
    
+  
    Doxygen Example:
    
+  
    +/** 
+ * @brief  Enable Interrupt in NVIC Interrupt Controller
+ * @param  IRQn  interrupt number that specifies the interrupt
+ * @return none.
+ * Enable the specified interrupt in the NVIC Interrupt Controller.
+ * Other settings of the interrupt such as priority are not affected.
+ */
    
+  
    • 
+

+
+
Data Types and IO Type Qualifiers

+
+

+  The Cortex-M HAL uses the standard types from the standard ANSI C header file
+  <stdint.h>. IO Type Qualifiers are used to specify the access
+  to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of 
+  debug information of peripheral registers.
+

+
+
+  
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+  
+
IO Type Qualifier#defineDescription
__Ivolatile constRead access only
__OvolatileWrite access only
__IOvolatileRead and write access

+
+
CMSIS Version Number

+

+  File core_cm4.h contains the version number of the CMSIS with the following define:
+

+
+
+#define __CM4_CMSIS_VERSION_MAIN  (0x02)      /* [31:16] main version       */
+#define __CM4_CMSIS_VERSION_SUB   (0x10)      /* [15:0]  sub version        */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB)

+
+

+  File core_cm3.h contains the version number of the CMSIS with the following define:
+

+
+
+#define __CM3_CMSIS_VERSION_MAIN  (0x02)      /* [31:16] main version       */
+#define __CM3_CMSIS_VERSION_SUB   (0x10)      /* [15:0]  sub version        */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB)

+
+

+  File core_cm0.h contains the version number of the CMSIS with the following define:
+

+
+
+#define __CM0_CMSIS_VERSION_MAIN  (0x02)      /* [31:16] main version       */
+#define __CM0_CMSIS_VERSION_SUB   (0x10)      /* [15:0]  sub version        */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB)

+
+
+
CMSIS Cortex Core

+

+  File core_cm4.h contains the type of the CMSIS Cortex-M with the following define:
+

+
+
+#define __CORTEX_M                (0x04)

+
+

+  File core_cm3.h contains the type of the CMSIS Cortex-M with the following define:
+

+
+
+#define __CORTEX_M                (0x03)

+
+

+  File core_cm0.h contains the type of the CMSIS Cortex-M with the following define:
+

+
+
+#define __CORTEX_M                (0x00)

+
+
+
CMSIS Files

+

+  This section describes the Files provided in context with the CMSIS to access the Cortex-M
+  hardware and peripherals.
+

+
+
+  
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+  
+
FileProviderDescription
device.hDevice specific (provided by silicon partner)Defines the peripherals for the actual device. The file may use 
+        several other include files to define the peripherals of the actual device.
core_cm0.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the core peripherals for the Cortex-M0 CPU and core peripherals.
core_cm3.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the core peripherals for the Cortex-M3 CPU and core peripherals.
core_cm4.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the core peripherals for the Cortex-M4 CPU and core peripherals.
core_cm4_simd.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the Cortex-M4 Core SIMD functions.
core_cmFunc.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the Cortex-M Core Register access functions.
core_cmInstr.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the Cortex-M Core instructions.
startup_deviceARM (adapted by compiler partner / silicon partner)Provides the Cortex-M startup code and the complete (device specific) Interrupt Vector Table
system_deviceARM (adapted by silicon partner)Provides a device specific configuration file for the device. It configures the device initializes 
+        typically the oscillator (PLL) that is part of the microcontroller device

+
+
device.h

+
+

+  The file device.h is provided by the silicon vendor and is the 
+  central include file that the application programmer is using in 
+  the C source code. This file contains:
+

+
    
+  
  • 
+	
    Interrupt Number Definition: provides interrupt numbers 
+	(IRQn) for all core and device specific exceptions and interrupts.
    
+	
    • 
+	
  • 
+	
    Configuration for core_cm0.h / core_cm3.h / core_cm4.h: reflects the 
+	actual configuration of the Cortex-M processor that is part of the actual 
+	device. As such the file core_cm0.h / core_cm3.h / core_cm4.h is included that 
+	implements access to processor registers and core peripherals. 
    
+	
    • 
+	
  • 
+	
    Device Peripheral Access Layer: provides definitions
+    for all device peripherals. It contains all data structures and the address 
+	mapping for the device specific peripherals. 
    
+	
    • 
+  
  • Access Functions for Peripherals (optional): provides
+    additional helper functions for peripherals that are useful for programming 
+	of these peripherals. Access Functions may be provided as inline functions 
+	or can be extern references to a device specific library provided by the 
+	silicon vendor.
    • 
+

+
+
+
Interrupt Number Definition

+
+
To access the device specific interrupts the device.h file defines IRQn 
+numbers for the complete device using a enum typedef as shown below:

+
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions/Interrupt Numbers ************************************************/
+  NonMaskableInt_IRQn             = -14,      /*!< 2 Non Maskable Interrupt                              */
+  HardFault_IRQn                  = -13,      /*!< 3 Cortex-M3 Hard Fault Interrupt                      */
+  MemoryManagement_IRQn           = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt               */
+  BusFault_IRQn                   = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                       */
+  UsageFault_IRQn                 = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                     */
+  SVCall_IRQn                     = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                        */
+  DebugMonitor_IRQn               = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt                  */
+  PendSV_IRQn                     = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                        */
+  SysTick_IRQn                    = -1,       /*!< 15 Cortex-M3 System Tick Interrupt                    */
+/******  STM32 specific Interrupt Numbers ****************************************************************/
+  WWDG_STM_IRQn                   = 0,        /*!< Window WatchDog Interrupt                             */
+  PVD_STM_IRQn                    = 1,        /*!< PVD through EXTI Line detection Interrupt             */
+  :
+  :
+  } IRQn_Type;

+
+
+
Device Specific Defines

+

+  The following device implementation specific defines are set in the device header file and are 
+  used for the Cortex-M core configuration options. Some configuration options are reflected 
+  in the CMSIS layer using the #define settings described below.
+

+

+  Several features in core_cm#.h are configured by the following defines 
+  that must be defined before #include <core_cm#.h>
+  preprocessor command.
+

+
+
+  
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+  
+
#defineCoreValueDescription
__CM0_REVM00x0000Core revision number ([15:8] revision number, [7:0] patch number)
__CM3_REVM30x0101 | 0x0200Core revision number ([15:8] revision number, [7:0] patch number)
__CM4_REVM40x0000Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITSM0, M3, M42 .. 8Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENTM0, M3, M40 | 1Defines if a MPU is present or not
__FPU_PRESENTM40 | 1Defines if a FPU is present or not
__Vendor_SysTickConfigM0, M3, M40 | 1When this define is setup to 1, the SysTickConfig function 
+		in core_cm3.h is excluded. In this case the device.h 
+		file must contain a vendor specific implementation of this function.

+
+
+
Device Peripheral Access Layer

+

+  Each peripheral uses a prefix which consists of <device abbreviation>_ 
+  and <peripheral name>_ to identify peripheral registers that access this 
+  specific peripheral. The intention of this is to avoid name collisions caused
+  due to short names. If more than one peripheral of the same type exists, 
+  identifiers have a postfix (digit or letter). For example:
+

+
    
+	
  • <device abbreviation>_UART_Type: defines the generic register layout for all UART channels in a device.
+      
    +typedef struct
+{
+  union {
+  __I  uint8_t  RBR;                     /*!< Offset: 0x000 (R/ )  Receiver Buffer Register    */
+  __O  uint8_t  THR;                     /*!< Offset: 0x000 ( /W)  Transmit Holding Register   */
+  __IO uint8_t  DLL;                     /*!< Offset: 0x000 (R/W)  Divisor Latch LSB           */
+       uint32_t RESERVED0;
+  };
+  union {
+  __IO uint8_t  DLM;                     /*!< Offset: 0x004 (R/W)  Divisor Latch MSB           */
+  __IO uint32_t IER;                     /*!< Offset: 0x004 (R/W)  Interrupt Enable Register   */
+  };
+  union {
+  __I  uint32_t IIR;                     /*!< Offset: 0x008 (R/ )  Interrupt ID Register       */
+  __O  uint8_t  FCR;                     /*!< Offset: 0x008 ( /W)  FIFO Control Register       */
+  };
+  __IO uint8_t  LCR;                     /*!< Offset: 0x00C (R/W)  Line Control Register       */
+       uint8_t  RESERVED1[7];
+  __I  uint8_t  LSR;                     /*!< Offset: 0x014 (R/ )  Line Status Register        */
+       uint8_t  RESERVED2[7];
+  __IO uint8_t  SCR;                     /*!< Offset: 0x01C (R/W)  Scratch Pad Register        */
+       uint8_t  RESERVED3[3];
+  __IO uint32_t ACR;                     /*!< Offset: 0x020 (R/W)  Autobaud Control Register   */
+  __IO uint8_t  ICR;                     /*!< Offset: 0x024 (R/W)  IrDA Control Register       */
+       uint8_t  RESERVED4[3];
+  __IO uint8_t  FDR;                     /*!< Offset: 0x028 (R/W)  Fractional Divider Register */
+       uint8_t  RESERVED5[7];
+  __IO uint8_t  TER;                     /*!< Offset: 0x030 (R/W)  Transmit Enable Register    */
+       uint8_t  RESERVED6[39];
+  __I  uint8_t  FIFOLVL;                 /*!< Offset: 0x058 (R/ )  FIFO Level Register         */
+} LPC_UART_TypeDef;
    
+  
    • 
+	
  • <device abbreviation>_UART1: is a pointer to a register structure that refers to a specific UART. 
+      For example UART1->THR is the transmit holding register of UART1.
+      
    +#define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )
+#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )
    
+  
    • 
+

+
+
Minimal Requiements

+

+  To access the peripheral registers and related function in a device the files device.h 
+  and core_cm0.h / core_cm3.h defines as a minimum:
+

+
    
+  
  • The Register Layout Typedef for each peripheral that defines all register names.
+      Names that start with RESERVE are used to introduce space into the structure to adjust the addresses of
+      the peripheral registers. For example:
+      
    +typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
    
+  
    • 
+
+  
  • 
+    Base Address for each peripheral (in case of multiple peripherals 
+    that use the same register layout typedef multiple base addresses are defined). For example:
+    
    +#define SysTick_BASE (SCS_BASE + 0x0010)            /* SysTick Base Address */
    
+  
    • 
+
+  
  • 
+    Access Definition for each peripheral (in case of multiple peripherals that use 
+    the same register layout typedef multiple access definitions exist, i.e. LPC_UART0, 
+    LPC_UART2). For Example:
+    
    +#define SysTick ((SysTick_Type *) SysTick_BASE)     /* SysTick access definition */
    
+  
    • 
+

+
+

+  These definitions allow to access the peripheral registers from user code with simple assignments like:
+

+
SysTick->CTRL = 0;

+
+
Optional Features

+
In addition the  device.h file may define:

+
    
+	
  • 
+    #define constants that simplify access to the peripheral registers. 
+	  These constant define bit-positions or other specific patterns are that required for the 
+    programming of the peripheral registers. The identifiers used start with 
+    <device abbreviation>_ and <peripheral name>_. 
+    It is recommended to use CAPITAL letters for such #define constants.
+  
    • 
+	
  • 
+    Functions that perform more complex functions with the peripheral (i.e. status query before 
+    a sending register is accessed). Again these function start with 
+    <device abbreviation>_ and <peripheral name>_. 
+  
    • 
+

+
+
core_cm0.h

+

+  File core_cm0.h describes the data structures for the Cortex-M0 core peripherals and does 
+  the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers 
+  and core peripherals with efficient functions (defined as static inline).
+

+
This file implement the Core Peripheral Access Layer for a Cortex-M0.

+
The define  __CMSIS_GENERIC allows to use core_cm0.h in generic 
+   library projects that are device independent. Only core relevant types and defines are used.

+
+
core_cm3.h

+

+  File core_cm3.h describes the data structures for the Cortex-M3 core peripherals and does 
+  the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers 
+  and core peripherals with efficient functions (defined as static inline).
+

+
This file implement the Core Peripheral Access Layer for a Cortex-M3.

+
The define  __CMSIS_GENERIC allows to use core_cm3.h in generic 
+   library projects that are device independent. Only core relevant types and defines are used.

+
+
core_cm4.h, core_cm4_simd.h

+

+  File core_cm4.h describes the data structures for the Cortex-M4 core peripherals and does 
+  the address mapping of this structures. It also provides basic access to the Cortex-M4 core registers 
+  and core peripherals with efficient functions (defined as static inline).
+

+

+  File core_cm4_simd.h defines Cortex-M4 SIMD instructions.
+

+
Together these files implement the Core Peripheral Access Layer for a Cortex-M4.

+
The define  __CMSIS_GENERIC allows to use core_cm4.h in generic 
+   library projects that are device independent. Only core relevant types and defines are used.

+
+
core_cmFunc.h and core_cmInstr.h

+

+  File core_cmFunc.h defines the Cortex-M Core Register access functions (defined as static inline).
+

+

+  File core_cmInstr.h defines the Cortex-M Core instructions (defined as static inline).
+

+
These files are part of the Core Peripheral Access Layer for a Cortex-M.

+
+
startup_device

+

+  A template file for startup_device is provided by ARM for each supported
+  compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific 
+  interrupt handlers. Each interrupt handler is defined as weak function 
+  to an dummy handler. Therefore the interrupt handler can be directly used in application software 
+  without any requirements to adapt the startup_device file.
+

+

+  The following exception names are fixed and define the start of the vector table for a Cortex-M0:
+

+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler

+
+

+  The following exception names are fixed and define the start of the vector table for a Cortex-M3:
+

+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler

+
+

+  In the following examples for device specific interrupts are shown:
+

+
+; External Interrupts
+                DCD     WWDG_IRQHandler           ; Window Watchdog
+                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler         ; Tamper

+
+

+  Device specific interrupts must have a dummy function that can be overwritten in user code. 
+  Below is an example for this dummy function.
+

+
+Default_Handler PROC
+                EXPORT WWDG_IRQHandler   [WEAK]
+                EXPORT PVD_IRQHandler    [WEAK]
+                EXPORT TAMPER_IRQHandler [WEAK]
+                :
+                :
+                WWDG_IRQHandler
+                PVD_IRQHandler
+                TAMPER_IRQHandler
+                :
+                :
+                B .
+                ENDP

+                
+

+  The user application may simply define an interrupt handler function by using the handler name
+  as shown below.
+

+
+void WWDG_IRQHandler(void)
+{
+  :
+  :
+}

+
+
+
system_device.c

+

+  A template file for system_device.c is provided by ARM but adapted by 
+  the silicon vendor to match their actual device. As a minimum requirement 
+  this file must provide a device specific system configuration function and a global variable 
+  that contains the system frequency. It configures the device and initializes typically the 
+  oscillator (PLL) that is part of the microcontroller device.
+

+

+  The file system_device.c must provide
+  as a minimum requirement the SystemInit function as shown below.
+

+
+
+  
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+  
+
Function DefinitionDescription
void SystemInit (void)Setup the microcontroller system. Typically this function configures the 
+                     oscillator (PLL) that is part of the microcontroller device. For systems 
+                     with variable clock speed it also updates the variable SystemCoreClock.

+                     SystemInit is called from startup_device file.
void SystemCoreClockUpdate (void)Updates the variable SystemCoreClock and must be called whenever the 
+                     core clock is changed during program execution. SystemCoreClockUpdate()
+                     evaluates the clock register settings and calculates the current core clock.
+

+
+

+  Also part of the file system_device.c 
+  is the variable SystemCoreClock which contains the current CPU clock speed shown below.
+

+
+
+  
+    
+      
+      
+    
+    
+      
+      
+    
+  
+
Variable DefinitionDescription
uint32_t SystemCoreClockContains the system core clock (which is the system clock	frequency supplied 
+                     to the SysTick timer and the processor core clock). This variable can be 
+                     used by the user application to setup the SysTick timer or configure other 
+                     parameters. It may also be used by debugger to query the frequency of the 
+                     debug timer or configure the trace clock speed.

+                     SystemCoreClock is initialized with a correct predefined value.


+		                 The compiler must be configured to avoid the removal of this variable in 
+		                 case that the application program is not using it. It is important for 
+		                 debug systems that the variable is physically present in memory so that 
+		                 it can be examined to configure the debugger.

+
+
Note

+
    
+  
  • The above definitions are the minimum requirements for the file 
+	system_device.c. This 
+	file may export more functions or variables that provide a more flexible 
+	configuration of the microcontroller system.
    
+  
    • 
+

+
+
+
Core Peripheral Access Layer

+
+
Cortex-M Core Register Access

+

+  The following functions are defined in core_cm0.h / core_cm3.h
+  and provide access to Cortex-M core registers.
+

+
+
+  
+    
+      
+      
+      
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+
Function DefinitionCoreCore RegisterDescription
void __enable_irq (void)M0, M3, M4PRIMASK = 0Global Interrupt enable (using the instruction CPSIE	i)
void __disable_irq (void)M0, M3, M4PRIMASK = 1Global Interrupt disable (using the instruction CPSID i)
uint32_t __get_CONTROL (void)M0, M3, M4return CONTROLReturn Control Register Value (using the instruction MRS)
void __set_CONTROL (uint32_t value)M0, M3, M4CONTROL = valueSet CONTROL register value (using the instruction MSR)
uint32_t __get_IPSR (void)M0, M3, M4return IPSRReturn IPSR Register Value (using the instruction MRS)
uint32_t __get_APSR (void)M0, M3, M4return APSRReturn APSR Register Value (using the instruction MRS)
uint32_t __get_xPSR (void)M0, M3, M4return xPSRReturn xPSR Register Value (using the instruction MRS)
uint32_t __get_PSP (void)M0, M3, M4return PSPReturn Process Stack Pointer (using the instruction MRS)
void __set_PSP (uint32_t TopOfProcStack)>M0, M3, M4PSP = TopOfProcStackSet Process Stack Pointer value (using the instruction MSR)
uint32_t __get_MSP (void)M0, M3, M4return MSPReturn Main Stack Pointer (using the instruction MRS)
void __set_MSP (uint32_t TopOfMainStack)M0, M3, M4MSP = TopOfMainStackSet Main Stack Pointer (using the instruction MSR)
uint32_t __get_PRIMASK (void)M0, M3, M4return PRIMASKReturn Priority Mask Register (using the instruction MRS)
void __set_PRIMASK (uint32_t value)M0, M3, M4PRIMASK = valueAssign value to Priority Mask Register (using the instruction MSR)
void __enable_fault_irq (void)M3, M4FAULTMASK = 0Global Fault exception and Interrupt enable (using the instruction CPSIE f)
void __disable_fault_irq (void)M3, M4FAULTMASK = 1Global Fault exception and Interrupt disable (using the instruction CPSID f)
uint32_t __get_BASEPRI (void)M3, M4return BASEPRIReturn Base Priority (using the instruction MRS)
void __set_BASEPRI (uint32_t value)M3, M4BASEPRI = valueSet Base Priority (using the instruction MSR)
uint32_t __get_FAULTMASK (void)M3, M4return FAULTMASKReturn Fault Mask Register (using the instruction MRS)
void __set_FAULTMASK (uint32_t value)M3, M4FAULTMASK = valueAssign value to Fault Mask Register (using the instruction MSR)
uint32_t __get_FPSCR (void)M4return FPSCRReturn Floating Point Status / Control Register
void __set_FPSCR (uint32_t value)M4FPSCR = valueAssign value to Floating Point Status / Control Register

+
+
Cortex-M Instruction Access

+

+  The following functions are defined in core_cm0.h / core_cm3.hand
+  generate specific Cortex-M instructions. The functions are implemented in the file 
+  core_cm0.c / core_cm3.c.
+

+
+
+  
+    
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+  
+
NameCoreGenerated CPU InstructionDescription
void __NOP (void)M0, M3, M4NOPNo Operation
void __WFI (void)M0, M3, M4WFIWait for Interrupt
void __WFE (void)M0, M3, M4WFEWait for Event
void __SEV (void)M0, M3, M4SEVSet Event
void __ISB (void)M0, M3, M4ISBInstruction Synchronization Barrier
void __DSB (void)M0, M3, M4DSBData Synchronization Barrier
void __DMB (void)M0, M3, M4DMBData Memory Barrier
uint32_t __REV (uint32_t value)M0, M3, M4REVReverse byte order in integer value.
uint32_t __REV16 (uint16_t value)M0, M3, M4REV16Reverse byte order in unsigned short value. 
sint32_t __REVSH (sint16_t value)M0, M3, M4REVSHReverse byte order in signed short value with sign extension to integer.
uint32_t __RBIT (uint32_t value)M3, M4RBITReverse bit order of value
uint8_t __LDREXB (uint8_t *addr)M3, M4LDREXBLoad exclusive byte
uint16_t __LDREXH (uint16_t *addr)M3, M4LDREXHLoad exclusive half-word
uint32_t __LDREXW (uint32_t *addr)M3, M4LDREXWLoad exclusive word
uint8_t __STREXB (uint8_t value, uint8_t *addr)M3, M4STREXBStore exclusive byte
uint16_t __STREXH (uint16_t value, uint16_t *addr)M3, M4STREXHStore exclusive half-word
uint32_t __STREXW (uint32_t value, uint32_t *addr)M3, M4STREXWStore exclusive word
void  __CLREX (void)M3, M4CLREXRemove the exclusive lock created by __LDREXB, __LDREXH, or __LDREXW
void  __SSAT (void)M3, M4SSATsaturate a signed value
void  __USAT (void)M3, M4USATsaturate an unsigned value

+
+
+
NVIC Access Functions

+

+  The CMSIS provides access to the NVIC via the register interface structure and several helper
+  functions that simplify the setup of the NVIC. The CMSIS HAL uses IRQ numbers (IRQn) to 
+  identify the interrupts. The first device interrupt has the IRQn value 0. Therefore negative 
+  IRQn values are used for processor core exceptions.
+

+

+  For the IRQn values of core exceptions the file device.h provides 
+  the following enum names.
+

+
+
+  
+    
+      
+      
+      
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+    
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+  
+
Core Exception enum ValueCoreIRQnDescription
NonMaskableInt_IRQnM0, M3, M4-14Cortex-M Non Maskable Interrupt
HardFault_IRQnM0, M3, M4-13Cortex-M Hard Fault Interrupt
MemoryManagement_IRQnM3, M4-12Cortex-M Memory Management Interrupt
BusFault_IRQnM3, M4-11Cortex-M Bus Fault Interrupt
UsageFault_IRQnM3, M4-10Cortex-M Usage Fault Interrupt
SVCall_IRQnM0, M3, M4-5Cortex-M SV Call Interrupt 
DebugMonitor_IRQnM3, M4-4Cortex-M Debug Monitor Interrupt
PendSV_IRQnM0, M3, M4-2Cortex-M Pend SV Interrupt
SysTick_IRQnM0, M3, M4-1Cortex-M System Tick Interrupt

+
+
The following functions simplify the setup of the NVIC.
+The functions are defined as static inline.

+
+
+  
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+    
+  
+
NameCoreParameterDescription
void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)M3, M4Priority Grouping ValueSet the Priority Grouping (Groups . Subgroups)
uint32_t NVIC_GetPriorityGrouping (void)M3, M4(void)Get the Priority Grouping (Groups . Subgroups)
void NVIC_EnableIRQ (IRQn_Type IRQn)M0, M3, M4IRQ NumberEnable IRQn
void NVIC_DisableIRQ (IRQn_Type IRQn)M0, M3, M4IRQ NumberDisable IRQn
uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)M0, M3, M4IRQ NumberReturn 1 if IRQn is pending else 0
void NVIC_SetPendingIRQ (IRQn_Type IRQn)M0, M3, M4IRQ NumberSet IRQn Pending
void NVIC_ClearPendingIRQ (IRQn_Type IRQn)M0, M3, M4IRQ NumberClear IRQn Pending Status
uint32_t NVIC_GetActive (IRQn_Type IRQn)M3, M4IRQ NumberReturn 1 if IRQn is active else 0
void NVIC_SetPriority (

+	    IRQn_Type IRQn,

+	    uint32_t priority)		M0, M3, M4IRQ Number, PrioritySet Priority for IRQn

+                     (not threadsafe for Cortex-M0)
uint32_t NVIC_GetPriority (IRQn_Type IRQn)M0, M3, M4IRQ NumberGet Priority for IRQn
uint32_t NVIC_EncodePriority (

+	    uint32_t PriorityGroup,

+	    uint32_t PreemptPriority,

+	    uint32_t SubPriority)		M3, M4IRQ Number,

+	  Priority Group,

+	  Preemptive Priority,

+	  Sub Priority		Encode priority for given group, preemptive and sub priority
void NVIC_DecodePriority (

+	    uint32_t Priority,
 
+	    uint32_t PriorityGroup,
 
+	    uint32_t* pPreemptPriority,
 
+	    uint32_t* pSubPriority)		M3, M4

+	  Priority,

+	  Priority Group,

+	  pointer to Preempt. Priority,

+	  pointer to Sub Priority		Decode given priority to group, preemptive and sub priority
void NVIC_SystemReset (void)M0, M3, M4(void)Resets the System

+
Note

+
    
+  
  • The processor exceptions have negative enum values. Device specific interrupts 
+         have positive enum values and start with 0. The values are defined in
+         device.h file.
+      
    
+  
    • 
+  
  • The values for PreemptPriority and SubPriority
+         used in functions NVIC_EncodePriority and NVIC_DecodePriority
+         depend on the available __NVIC_PRIO_BITS implemented in the NVIC.
+      
    
+  
    • 
+

+
+
+
SysTick Configuration Function

+
+
The following function is used to configure the SysTick timer and start the 
+SysTick interrupt.

+
+
+  
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+  
+
NameParameterDescription
uint32_t SysTickConfig (uint32_t ticks)ticks is SysTick counter reload valueSetup the SysTick timer and enable the SysTick interrupt. After this 
+        call the SysTick timer creates interrupts with the specified time interval.


+        Return: 0 when successful, 1 on failure.

+      

+
+
+
Cortex-M3 / Cortex-M4 ITM Debug Access

+
+
The Cortex-M3 / Cortex-M4 incorporates the Instrumented Trace Macrocell (ITM) that 
+provides together with the Serial Viewer Output trace capabilities for the 
+microcontroller system. The ITM has 32 communication channels; two ITM 
+communication channels are used by CMSIS to output the following information:

+
    
+  
  • ITM Channel 0: implements the ITM_SendChar function 
+      which can be used for printf-style output via the debug interface.
    • 
+  
  • ITM Channel 31: is reserved for the RTOS kernel and can be used for 
+      kernel awareness debugging.
    • 
+

+
Note

+
    
+  
  • The ITM channel 31 is selected for the RTOS kernel since some kernels 
+      may use the Privileged level for program execution. ITM 
+      channels have 4 groups with 8 channels each, whereby each group can be 
+      configured for access rights in the Unprivileged level. The ITM channel 0 
+      may be therefore enabled for the user task whereas ITM channel 31 may be 
+      accessible only in Privileged level from the RTOS kernel itself.
    
+  
    • 
+

+
+
The prototype of the ITM_SendChar routine is shown in the 
+table below.

+
+
+  
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+  
+
NameParameterDescription
void uint32_t ITM_SendChar(uint32_t chr)character to outputThe function outputs a character via the ITM channel 0. The 
+                     function returns when no debugger is connected that has booked the 
+                     output. It is blocking when a debugger is connected, but the 
+                     previous character send is not transmitted.


+                     Return: the input character 'chr'.
+      

+
+

+  Example for the usage of the ITM Channel 31 for RTOS Kernels:
+

+
+  // check if debugger connected and ITM channel enabled for tracing
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
+  (ITM->TCR & ITM_TCR_ITMENA) &&
+  (ITM->TER & (1UL << 31))) {
+    // transmit trace data
+    while (ITM->PORT31_U32 == 0);
+    ITM->PORT[31].u8 = task_id;      // id of next task
+    while (ITM->PORT[31].u32 == 0);
+    ITM->PORT[31].u32 = task_status; // status information
+  }

+
+
+
Cortex-M3 additional Debug Access

+
+
CMSIS provides additional debug functions to enlarge the Cortex-M3 Debug Access.
+Data can be transmitted via a certain global buffer variable towards the target system.

+
+
The buffer variable and the prototypes of the additional functions are shown in the 
+table below.

+
+
+  
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
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+    
+  
+
NameParameterDescription
extern volatile int ITM_RxBuffer Buffer to transmit data towards debug system. 


+                     Value 0x5AA55AA5 indicates that buffer is empty.
int ITM_ReceiveChar (void)noneThe nonblocking functions returns the character stored in 
+                     ITM_RxBuffer. 


+                     Return: -1 indicates that no character was received.
int ITM_CheckChar (void)noneThe function checks if a character is available in ITM_RxBuffer. 


+                     Return: 1 indicates that a character is available, 0 indicates that
+                     no character is available.

+
+
+
CMSIS Example

+

+  The following section shows a typical example for using the CMSIS layer in user applications.
+  The example is based on a STM32F10x Device.
+

+
+#include "stm32f10x.h"
+
+volatile uint32_t msTicks;                       /* timeTicks counter */
+
+void SysTick_Handler(void) {
+  msTicks++;                                     /* increment timeTicks counter */
+}
+
+__INLINE static void Delay (uint32_t dlyTicks) {
+  uint32_t curTicks = msTicks;
+
+  while ((msTicks - curTicks) < dlyTicks);
+}
+
+__INLINE static void LED_Config(void) {
+  ;                                              /* Configure the LEDs */
+}
+
+__INLINE static void LED_On (uint32_t led) {
+  ;                                              /* Turn On  LED */
+}
+
+__INLINE static void LED_Off (uint32_t led) {
+  ;                                              /* Turn Off LED */
+}
+
+int main (void) {
+  if (SysTick_Config (SystemCoreClock / 1000)) { /* Setup SysTick for 1 msec interrupts */
+    ;                                            /* Handle Error */
+    while (1);
+  }
+  
+  LED_Config();                                  /* configure the LEDs */                            
+ 
+  while(1) {
+    LED_On (0x100);                              /* Turn  on the LED   */
+    Delay (100);                                 /* delay  100 Msec    */
+    LED_Off (0x100);                             /* Turn off the LED   */
+    Delay (100);                                 /* delay  100 Msec    */
+  }
+}

+
+
+
CMSIS MISRA-C:2004 Compliance Exceptions

+

+  CMSIS violates following MISRA-C2004 Rules:
+

+
    
+   
  • Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
    
+       Function definitions in header files are used to allow 'inlining'.
    •  
+
+   
  • Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    
+       Unions are used for effective representation of core registers.
    • 
+   
+   
  • Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
    
+       Function-like macros are used to allow more efficient code.
    •  
+

+
+
  

+
+
\ No newline at end of file
diff --git a/hardware/sam/system/CMSIS/Documentation/CMSIS_DebugSupport.htm b/hardware/sam/system/CMSIS/Documentation/CMSIS_DebugSupport.htm
new file mode 100644
index 000000000..9ed077d61
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/CMSIS_DebugSupport.htm
@@ -0,0 +1,240 @@
+
+
+
+CMSIS Debug Support
+
+
+
+
+
+
+
+
+
CMSIS Debug Support

+
This file describes the CMSIS Debug support available with CMSIS (starting V1.30).

+
Version: 1.02 - 25. July 2011

+
+
Information in this file, the accompany manuals, and software is

+                 Copyright © ARM Ltd.
All rights reserved.
+

+
+

+
+
Revision History

+
    
+	
  • Version 1.00: Initial Release. 
    • 
+	
  • Version 1.01: Internal Review. 
    • 
+	
  • Version 1.02: Removed product specific information. 
    • 
+

+
+

+
+
Contents

+
+
    
+  
  1. About
    2. 
+  
  2. Cortex-M3 / Cortex-M4 ITM Debug Access
    3. 
+  
  3. Debug IN / OUT functions
    4. 
+  
  4. ITM Debug Support in Debugger
    5. 
+

+
+
 

+
About

+

+  CMSIS provides for Cortex-M3 / Cortex-M4 processor based microcontrollers debug support via the Instrumented Trace Macrocell (ITM).
+  This document describes the available CMSIS Debug functions and the used methods.
+

+
+
 

+
Cortex-M3 / Cortex-M4 ITM Debug Access

+

+  The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with 
+  the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has 
+  32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM 
+  communication channels are used by CMSIS to output the following information:
+

+
    
+	
  • ITM Channel 0: used for printf-style output via the debug interface.
    • 
+	
  • ITM Channel 31: is reserved for RTOS kernel awareness debugging.
    • 
+

+
+
 

+
Debug IN / OUT functions

+
CMSIS provides following debug functions:

+
    
+	
  • ITM_SendChar (uses ITM channel 0)
    • 
+	
  • ITM_ReceiveChar (uses global variable)
    • 
+	
  • ITM_CheckChar (uses global variable)
    • 
+

+
+
ITM_SendChar

+

+  ITM_SendChar is used to transmit a character over ITM channel 0 from 
+  the microcontroller system to the debug system. 

+  Only a 8 bit value is transmitted.
+

+
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  /* check if debugger connected and ITM channel enabled for tracing */
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA)  &&
+      (ITM->TCR & ITM_TCR_ITMENA)                  &&
+      (ITM->TER & (1UL << 0))  ) 
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t)ch;
+  }  
+  return (ch);
+}

+
+
ITM_ReceiveChar

+

+  ITM communication channel is only capable for OUT direction. For IN direction
+  a global variable is used. A simple mechanism detects if a character is received.
+  The project to test need to be build with debug information.
+

+
+

+  The global variable ITM_RxBuffer is used to transmit a 8 bit value from debug system
+  to microcontroller system. ITM_RxBuffer is 32 bit wide to 
+	ensure a proper handshake.
+

+
+extern volatile int32_t ITM_RxBuffer;                    /* variable to receive characters                             */
+

+

+  A dedicated bit pattern is used to determine if ITM_RxBuffer is empty
+  or contains a valid value.
+

+
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
+

+

+  ITM_ReceiveChar is used to receive a 8 bit value from the debug system. The function is nonblocking.
+  It returns the received character or '-1' if no character was available.
+

+
+static __INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                               /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+  
+  return (ch); 
+}
+

+
+
ITM_CheckChar

+

+  ITM_CheckChar is used to check if a character is received.
+

+
+static __INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}

+
+
+
 

+
ITM Debug Support in a Debugger

+

+  The Debugger shall offer a dedicated console window for printf style debug input and output using the CMSIS defined ITM methods described above.
+

+
Direction: Microcontroller -> Debugger:

+
    
+  
  • 
+    at the beginning of a debug session the debugger shall enable ITM trace on channel 0 and continuously snoop for channel 0 data on the ITM trace
+    stream it receives from the Microcontroller's CoreSight ITM unit
+  
    • 
+  
  • 
+    data received via the ITM communication channel 0 is interpreted as charater and gets redirected into the dedicated Console Window
+  
    • 
+

+
+
Direction: Debugger -> Microcontroller:

+
    
+  
  • 
+    at the beginning of a debug session the debugger shall seek for the presence of the global variable named ITM_RxBuffer in the debug
+    information of the application being loaded
+  
    • 
+  
  • 
+    strings entered into the Console Window are written by the debugger as a stream of char values via the variable ITM_RxBuffer.
+  
    • 
+  
  • 
+    the debugger writes the next character into the ITM_RxBuffer only once the value has been read and the ITM_RXBUFFER_EMPTY value being set.
+    (refer to: ITM_ReceiveChar()).
+

+
+
+
+
\ No newline at end of file
diff --git a/hardware/sam/system/CMSIS/Documentation/CMSIS_History.htm b/hardware/sam/system/CMSIS/Documentation/CMSIS_History.htm
new file mode 100644
index 000000000..9b44a3fb4
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/CMSIS_History.htm
@@ -0,0 +1,472 @@
+
+
+
+CMSIS Version History
+
+
+
+
+
+
+
+
+
CMSIS Version History

+
This document describes the changes between the different CMSIS versions.

+
Version: 2.10 - July 2011

+
+
Information in this file, the accompany manuals, and software is

+                 Copyright © ARM Ltd.
All rights reserved.
+

+
+

+
+
+
Contents

+
+
    
+  
  1. Used Toolchains
    2. 
+  
  2. Changes to version V2.00
    3. 
+  
  3. Changes to version V1.30
    4. 
+  
  4. Changes to version V1.20
    5. 
+  
  5. Open Points
    6. 
+  
  6. Limitations
    7. 
+

+
+
+
Used Toolchains

+

+  Following toolchains have been used for test / verification:.
+

+  
    
+    
  • ARM: MDK-ARM Version 4.21
    • 
+    
  • GNU: Sourcery G++ Lite Edition for ARM 2010.09-51
    • 
+    
  • IAR: IAR Embedded Workbench Kickstart Edition V6.10
    • 
+  

+
+
+
Changes to version V2.00

+
+
Added CMSIS DSP Software Library support for Cortex-M0 based MCUs

+

+  The CMSIS DSP Software Library provides now also libraries and examples for Cortex-M0.
+

+

+  For more information refer to CMSIS DSP Library documentation.
+

+
+
Added big endian support for DSP library

+

+  The CMSIS DSP Software Library provides now also pre-build libraries 
+	and projects for big endian devices.
+

+

+  For more information refer to CMSIS DSP Library documentation.
+

+
+
+
Simplified folder structure for CMSIS include files

+

+  All CMSIS core include files as well as the DSP-Library header files are located in 
+	a single folder ./CMSIS/Include.
+

+
+
Changed folder structure for Device Support packages

+

+  Device Support packages are expected to be in folder ./Device located at the
+  same level as ./CMSIS.
+

+
The new Device folder contains the following subfolders:

+  
    
+     
  • Device
    • 
+       
      
+         
    • <Vendor> 
+           
        
+             
      • <Device> | <Device Series>
+               
          
+                  
        • Include
          
+                      <device>.h
          
+                      system_<device>.h
          
+                  
          • 
+                  
        • Source
+                    
            
+                       
          • Templates
            
+                           system_<device>.c
            
+                          
              
+                             
            • <Toolchain>
              
+                                 startup_<device>.s
              
+                             
              • 
+                             
            • <Toolchain>
              • 
+                                
            • ...
              • 
+                          
            
+                       
            • 
+                    
          
+                  
          • 
+               
        
+             
      • <Device> | <Device Series>
        • 
+             
      • ...
        • 
+           
      
+         
      • 
+         
    • <Vendor>
      • 
+         
    • ...
      • 
+       
    
+     
+  

+
Template files are application specific files and are required to be copied to the project prior to use!

+
+
Removed CMSIS core source files

+

+  The CMSIS core source files core_cm0.c, core_cm3.c, core_cm4.c 
+  containing helper functions for older ARM compiler versions got removed.
+

+

+  For the ARM Compiler Toolchain version V4.0.677 or later is 
+	required!

+
+
+
Changes to version V1.30

+
+
Added CMSIS DSP Software Library

+

+  The CMSIS DSP Software Library is a suite of common signal processing functions targeted 
+  to Cortex-M processor based microcontrollers. Even though the code has been specifically 
+  optimized towards using the extended DSP instruction set of the Cortex-M4 processor, 
+  the library can be compiled for any Cortex-M processor.
+

+

+  For more information see CMSIS DSP Library documentation.
+

+
+
Added CMSIS System View Description

+

+  The CMSIS System View Description answers the challenges of accurate, detailed and 
+  timely device aware peripheral debugging support for Cortex Microcontroller based 
+  devices by the software development tools vendor community.
+

+

+  Silicon vendors shall create and maintain a formalized description of the debug view 
+  for all the peripherals contained in their Cortex Microcontroller based devices.
+  Tool vendors use such descriptions to establish device specific debug support in 
+  their debugging tools.
+

+

+  A standardized System View Description shall provide a common approach to 
+  capturing peripheral debug related information in a machine readable files.
+

+

+  For more information see CMSIS System View Description.
+

+
+
Added Cortex-M4 Core Support

+

+  Additional folder CM4, containing the Cortex-M4 core support files, has been added.
+

+  
    
+    
  • CM0
    • 
+    
  • CM3
    • 
+    
  • CM4
+       
      
+         
    • CoreSupport
      • 
+         
    • DeviceSupport
      • 
+       
    
+    
    • 
+  

+
+
New naming for Core Support Files

+

+  The new Core Support Files are:
+

+
    
+  
  • core_cm#.h  (# = 0, 3, 4)
    • 
+  
  • core_cmFunc.h  (Cortex-M Core Register access functions)
    • 
+  
  • core_cmInstr.h  (Cortex-M Core instructions)
    • 
+  
  • core_cm4_simd.h (Cortex-M4 SIMD instructions)
    • 
+

+
+
Changes to version V1.20

+
+
Removed CMSIS Middelware packages

+

+  CMSIS Middleware is removed and no longer focus of CMSIS.
+

+
+
SystemFrequency renamed to SystemCoreClock

+

+  The variable name SystemCoreClock is more precise than SystemFrequency
+  because the variable holds the clock value at which the core is running.
+

+
+
Changed startup concept

+

+  The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit 
+  from main) has the weakness that it does not work for controllers which need a already 
+  configuerd clock system to configure the external memory controller.
+

+
+
Changed startup concept

+
    
+  
  • 
+    SystemInit() is called from startup file before premain.
+  
    • 
+  
  • 
+    SystemInit() configures the clock system and also configures
+    an existing external memory controller.
+  
    • 
+  
  • 
+    SystemInit() must not use global variables.
+  
    • 
+  
  • 
+    SystemCoreClock is initialized with a correct predefined value.
+  
    • 
+  
  • 
+    Additional function void SystemCoreClockUpdate (void) is provided.
    
+   SystemCoreClockUpdate() updates the variable SystemCoreClock
+   and must be called whenever the core clock is changed.
    
+   SystemCoreClockUpdate() evaluates the clock register settings and calculates
+   the current core clock.
+  
    • 
+

+      
+
+
Advanced Debug Functions

+

+  ITM communication channel is only capable for OUT direction. To allow also communication for
+  IN direction a simple concept is provided.
+

+
    
+  
  • 
+    Global variable volatile int ITM_RxBuffer used for IN data.
+  
    • 
+  
  • 
+    Function int ITM_CheckChar (void) checks if a new character is available.
+  
    • 
+  
  • 
+    Function int ITM_ReceiveChar (void) retrieves the new character.
+  
    • 
+

+
+

+  For detailed explanation see file CMSIS debug support.htm. 
+

+
+
+
Core Register Bit Definitions

+

+  Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the
+  defines correspond with the Cortex-M Technical Reference Manual.  
+

+

+  e.g. SysTick structure with bit definitions
+

+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */

+
+
DoxyGen Tags

+

+  DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation
+  using DoxyGen.
+

+
+
Folder Structure

+

+  The folder structure is changed to differentiate the single support packages.
+

+
+  
    
+    
  • CM0
    • 
+    
  • CM3
+       
      
+         
    • CoreSupport
      • 
+         
    • DeviceSupport
      • 
+           
        
+             
      • Vendor 
+               
          
+                 
        • Device
+                   
            
+                      
          • Startup
+                        
              
+                          
            • Toolchain
              • 
+                          
            • Toolchain
              • 
+                          
            • ...
              • 
+                        
            
+                      
            • 
+                   
          
+                 
          • 
+                 
        • Device
          • 
+                 
        • ...
          • 
+               
        
+             
        • 
+             
      • Vendor
        • 
+             
      • ...
        • 
+           
      
+         
+         
    • Example (optional)
+           
        
+             
      • Toolchain 
+               
          
+                 
        • Device
          • 
+                 
        • Device
          • 
+                 
        • ...
          • 
+               
        
+             
        • 
+             
      • Toolchain
        • 
+             
      • ...
        • 
+           
      
+         
      • 
+       
    
+    
    • 
+     
+    
  • Documentation
    • 
+  

+
+
Open Points

+

+  Following points need to be clarified and solved:
+

+
    
+  
  • 
+    
    
+      Equivalent C and Assembler startup files.
+    
    
+    
    
+      Is there a need for having C startup files although assembler startup files are
+      very efficient and do not need to be changed?
+    
    
+  
    • 
+  
  • 
+    
    
+      Placing of HEAP in external RAM.
+    
    
+    
    
+      It must be possible to place HEAP in external RAM if the device supports an 
+      external memory controller.
+    
    
+  
    • 
+  
  • 
+    
    
+      Placing of STACK /HEAP.
+    
    
+    
    
+      STACK should always be placed at the end of internal RAM.
+    
    
+    
    
+      If HEAP is placed in internal RAM than it should be placed after RW ZI section.
+    
    
+  
    • 
+

+
+
+
Limitations

+

+  The following limitations are not covered with the current CMSIS version:
+

+
    
+ 
  • 
+  No C startup files are available. 
+ 
    • 
+

+
diff --git a/hardware/sam/system/CMSIS/Documentation/CMSIS_Logo_Final.jpg b/hardware/sam/system/CMSIS/Documentation/CMSIS_Logo_Final.jpg
new file mode 100644
index 000000000..e04560175
Binary files /dev/null and b/hardware/sam/system/CMSIS/Documentation/CMSIS_Logo_Final.jpg differ
diff --git a/hardware/sam/system/CMSIS/Documentation/CMSIS_System_View_Description.htm b/hardware/sam/system/CMSIS/Documentation/CMSIS_System_View_Description.htm
new file mode 100644
index 000000000..d47878efd
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/CMSIS_System_View_Description.htm
@@ -0,0 +1,1157 @@
+
+
+  
+  CMSIS - SVD: Cortex Microcontroller Software Interface Standard - System View Description
+  
+  
+	
+
+
+
+
Cortex Microcontroller Software Interface Standard

+System View Description

+
+
This file describes the Cortex Microcontroller Software 
+Interface Standard - System View Description (CMSIS - SVD) concept and syntax.

+
Version: 1.02 - 27. July 2011

+
+
Information in this file, the accompany manuals, and software is

+                 Copyright © ARM Ltd.
All rights reserved.
+

+
+

+
+
Revision History

+
    
+	
  • Version 0.91: initial proposal.
    • 
+	
  • Version 0.92: revised proposal considering forum feedback (e.g. consider 
+	IP-XACT constructs and naming scheme)
    • 
+	
  • Version 1.0: new elements: peripheral version, vendor specific 
+	extension section, interrupt mapping information, global peripheral disable 
+	condition, naming of register arrays, enhanced naming schemes, etc.
    • 
+	
  • Version 1.0: SVD versioning and updated schema file
    • 
+	
  • Version 1.01: Error corrections in the example code. "include" has been removed. Restricted to one device per file.
    • 
+	
  • Version 1.02: Adding the use case of device header file generation.
    • 
+

+
+
 

+
+

+
+
Contents

+
+
    
+  
  1. About
    2. 
+  
  2. Motivation
    3. 
+  
  3. Requirements
    4. 
+  
  4. Format
    5. 
+  
  5. Example
    6. 
+  
  6. Questions & Answers
    7. 
+

+
+
About

+
+

+  The Cortex Microcontroller Software Interface Standard - System View 
+	Description (CMSIS - SVD) answers the challenges
+  of accurate, detailed and timely device aware peripheral debugging support for Cortex 
+	Microcontroller based devices by the software development 
+	tools vendor community.
+

+

+  Silicon vendors shall create and maintain a formalized description of the 
+	debug view for all the peripherals contained in their Cortex 
+	Microcontroller based devices. Tool vendors use such descriptions to 
+	establish device specific debug support in their debugging tools with minimal turn around times and 
+	manageable effort. Device support across many development tools  is 
+	essential for silicon provider in order to promote new devices and device 
+	variants entering the market. Device aware debug views provide fast and 
+	convenient access to all registers and fields as well as a detailed 
+	description. This enables software developer to 
+	develop and debug code most efficiently and adopt new devices early and 
+	quickly.

+

+  A standardized System View Description shall provide a common approach to 
+	capturing peripheral debug related information in a machine readable files. 
+	The scope of the contained information is agreed to match the level usually 
+	provided by silicon vendors in their device reference manuals, however in a 
+	formalized XML based format. There 
+	are other description languages already available. IP-XACT from the SPIRIT 
+	consortium is a prominent example. IP-XACT covers the register description 
+	sufficiently, however it comprises many other aspects of the devices like 
+	ports, bus-protocols, modeling, tool flows, etc. making a direct use of 
+	IP-XACT too complex. The design of the SVD language is 
+	taking some guidance from IP-XACT thus allowing straight forward conversion 
+	from IP-XACT to CMSIS-SVD where IP-XACT device information is already 
+	available.

+

+  In a second step the CMSIS-SVD description shall be used for automatically 
+	generating CMSIS compliant a device header file. This enables the 
+	information in the header file to be consistent with what the debugger will 
+	display and CMSIS compliant by construction. The header file generation will 
+	require some additional pieces of information and therefore a future version 
+	of the description will need to include some extensions for this purpose.

+

+  Device aware debugging support is only one aspect of device 
+	support essential to software development environments, however it is one of 
+	the most time consuming and error prone ones.

+
Motivation

+

+
+The software developer of microcontroller devices is faced with a growing number 
+of devices with an ever increasing number of peripheral blocks providing a wide 
+range of distinct and complex functionality. The development of drivers for 
+these peripherals is in the critical path of every project. Modern debuggers are supporting the software developer in getting the 
+software to run according to the requirements. A debugger providing peripheral awareness improves the 
+ability to access and interpret complex configuration and status information of 
+peripherals. Even though this is only one aspect of device support within microcontroller 
+development environments it is essential for the successful and timely adoption 
+of development tools and the device by the market.

+
Today software development environments address device aware 
+debugging in various ways. They either use documents or proprietary file formats 
+as input for providing peripheral views in the debuggers. 
+Extracting peripheral information from written documentation is a very time 
+consuming, tedious and error prone task. Having a file containing peripheral specific information to generate peripheral views 
+is going to make device support more affordable, reliable and timely. 
+The challenge for the tool providers is the support of many 
+different and incompatible file formats from a growing number of silicon vendors. 
+For silicon vendors it is time consuming and costly to engage with many tool 
+provider in order to achieve device support in a wide range of development 
+environments.

+
Standardizing on a System View Description aims to ease this challenge 
+by agreeing on a formal XML-based file format. In conjunction with supporting web server infrastructure silicon partner 
+shall upload and maintain such descriptions in a tool vendor agnostic device 
+database, hosted e.g. by the web server infrastructure 
+
+cmsis.arm.com . Access control to sensitive information is managed on a per user 
+basis. This allows silicon vendors to upload information for devices that have 
+not been made public.  

+
Such an approach provides benefits for silicon and tool vendors as well as 
+software developers of Cortex-M based microcontroller devices

+
    
+  
  • timely and accurate device support provided by a whole range of tool providers 
    • 
+	
  • tool providers become more efficient in supporting a multitude of devices 
+	and device variants
    • 
+	
  • less interaction required between silicon vendors and the  
+	tool providers
    • 
+	
  • silicon provider has control over and maintains the System View 
+	Description during the life cycle of the device
    • 
+	
  • high quality device support in terms of completeness and correctness of 
+	device aware debugging
    • 
+	
  • improved productivity and user experience for the software developer
    • 
+

+
Requirements

+
The debug description shall capture the information about all 
+the peripherals contained in a specific device. This section describes which 
+items of information are deemed relevant for a debugger. Silicon vendors are expected to 
+provide the System View Description for their devices, matching the information 
+contained in device reference manuals. The System View Description shall be suitable for straight forward 
+generation from existing databases like IP-XACT descriptions or SIDSC. The size 
+of device description is a concern and therefore redundancy in the description 
+shall be avoided. The size of SVD files affects the efficiency of 
+distribution as well as the loading time by the development tools. Last but not least manual editing of SVD files shall be possible for 
+the purpose of customization by SW developers.

+
Required content of the description

+
From a programmer's perspective a peripheral can be seen as a set of registers 
+with unique names being mapped to fixed addresses allocated 
+within a defined range of an address space.

+
From a debugger's point of view read accesses to a physical register need to be 
+executed in order to display its current value. The debugger executes a write 
+access to a register when a user edits its value. For this purpose the debugger 
+needs to know about the following additional attributes: 

+
    
+				
  • minimal addressable unit = smallest series of bits 
+				identified by a unique address (e.g. byte-addressable memory) 
    • 
+				
  • register size = number of bits forming a register (ARM Cortex-M usually 
+				32 bits)
    • 
+				
  • access permission = read and write, read only, 
+				write only
    • 
+				
  • access side effects = accesses by the debugger must 
+				be avoided if it has side effects. Some side effects may be 
+				reversed by the debugger to compensate for the side effect
    • 
+

+
In many cases peripheral registers are partitioned into chunks of bits of 
+distinct functionality. In this document these chunks are referred to as 
+field. Each 
+register that consists of fields shall  be described by a list 
+of uniquely named fields (Note: field names are not required to be 
+unique across registers). In order for a debugger to extract the 
+value of a field from the corresponding register the following attributes are required:

+
    
+				
  • most significant bit = highest bit position of the 
+				bit-field in the corresponding register
    • 
+				
  • least significant bit = lowest bit position of the 
+				bit-field within the corresponding register
    • 
+				
  • access permission = read and write, read only, 
+				write only
    • 
+

+
An enumerated value maps a number to a specific descriptive string 
+representing the semantics of the value of a field. The debugger displays the 
+descriptive string rather than the number to simplify the access to the 
+information thus 
+avoiding the necessity of a look-up in the device reference manual. Each item of 
+an enumerated value has the following attributes:

+
    
+				
  • value = value of the bit-field that corresponds to 
+				the string attribute
    • 
+				
  • name = short string that describes the semantics of a 
+				field when the corresponding value is set
    • 
+				
  • description = detailed description of the semantics 
+				of the field when the corresponding value is set
    • 
+

+
The hierarchical structure of the description looks like this:

+
Device =

+
    
+	
  • 
+		
     Peripherals
    
+		
      
+						
    • 
+						
      Peripheral
      
+						
        
+										
      • 
+										
        Registers
        
+										
          
+														
        • 
+														
          
+														Register
          
+														
            
+																		
          • 
+																		
            
+																		Fields
            
+																		
              
+																						
            • 
+																						
              Field
              
+																						
                
+																										
              • 
+																										
                Enumerated Values
                
+																										
                  
+																														
                • 
+																														
                  Enumerated Value
                  
+																														
                  • 
+																										
                
+																										
                • 
+																						
              
+																						
              • 
+																		
            
+																		
            • 
+														
          
+														
          • 
+										
        
+										
        • 
+						
      
+						
      • 
+		
    
+	
    • 
+

+
+
One file can only contain a description for a single device or device family 
+sharing the identical description. Devices consists of a one or more peripherals. 
+Each peripheral contains 
+one or more registers, where each register may consist of one or more fields. 
+The values of a field maybe represented through descriptive strings and detailed 
+descriptions, the enumerated values.

+
In many cases there are multiple 
+instances of the same peripheral in a device (e.g. Timer0, Timer1, etc.). For 
+this reason the description has the concept of deriving a peripheral from a peripheral 
+that has already been described. The attribute derivedFrom specifies 
+such a relationship. 
+Similarly registers or fields can be reused within the device description. The 
+grouping of  peripherals providing 
+similar functionality (e.g. Simple Timer, Complex Timer) is controlled via the element groupName. 
+All peripherals associated with the same group name are collectively listed under this group 
+in the order they have been specified in the file. 
+Collecting  
+similar or related peripherals into peripheral groups helps structuring the list 
+of peripherals e.g. in a drop down menu (tool dependent). Devices with a large 
+set of peripherals will benefit from this additional level of structure.

+
Each of the items (i.e. Device, Peripheral, Register and 
+Field) owns an description element containing verbose information about 
+the respective element. The description field plays 
+an important part in improving the software development productivity. Instead of 
+searching through the reference manual the detailed explanation from the manual 
+could become immediately accessible from within the development environment.

+
Details about the exact display format and layout of the peripheral view are 
+considered beyond the scope of the description. It is up to the tool vendor to 
+visualize the contained information appropriately. The  
+silicon vendor provides details about the device's peripherals that is commonly available. 

+
System View Description files need to be validated for:

+
    
+				
  1. syntactical correctness using XML-Schema checking utilities
    2. 
+				
  2. consistency  of the provided information (e.g. multiple registers mapped to the same address, 
+				all registers located within the specified address ranges of a 
+				peripheral, all fields are within the range of the register 
+				size, etc.) by a utility developed by ARM (SVDConv.exe)
    3. 
+				
  3.  semantical correctness of the System View Description 
+				against the silicon specification executed by the silicon vendor
    4. 
+

+
The SVD description format was extended by numerous elements during the 
+review period targeting version 1.0 and new extensions are expected for future 
+versions of this format. A new section named "vendorExtensions" has been added 
+to the end of the top level to allow silicon vendors and tool partners to 
+innovate and expand the description in order to overcome limitations of the 
+current specification until these can be incorporated into new versions of 
+CMSIS-SVD. 

+

+
+
 Format

+
+

+  The following section describes the SVD file format in detail. Each subsection 
+	defines a single hierarchy level of the description and lists all mandatory 
+	and optional language elements for that specific level including type 
+	information for each element. Each element is discussed in more detail and a 
+	brief snippet is provided as an example. The sequence of elements shown 
+	below is binding. Optional elements are highlighted in green, blue elements 
+	are mandatory unless they have been already specified globally on a higher 
+	level.

+

+  An XML-schema file is provided alongside this document for syntactical 
+	checking of descriptions being developed.

+
<device schemaVersion="xs:decimal" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">

+
   <name>xs:Name</name>

+   <version>xs:string</version>

+   <description>xs:string</description>

+   <addressUnitBits>scaledNonNegativeInteger</addressUnitBits>

+   <width>scaledNonNegativeInteger </width>

+

+   <size>scaledNonNegativeInteger</size>

+   <access>accessType</access>

+   <resetValue>scaledNonNegativeInteger</resetValue>

+   <resetMask>scaledNonNegativeInteger</resetMask>

+
   <peripherals>

+      ...

+   </peripherals>

+   <vendorExtensions>

+      ...

+    </vendorExtensions>

+
</device>

+
The device provides the outermost frame of the description. All other 
+elements like peripherals, registers and fields are described inside of this scope. A device contains one or more peripherals.
+The optional elements size, access, resetValue and resetMask are used as default values throughout the 
+device description unless they get overruled on a lower level of the description 
+(e.g. peripheral or register).

+
Mandatory items:

+
name = the unique name string is used to identify the device. 
+All devices of a silicon vendor are required to have a unique name. In case an 
+SVD description covers a family or series of devices, the name of the series or 
+family is placed here. The device names of the members of the series or family 
+are listed in <memberDevices>

+
description = string describing main features of a device 
+(e.g. CPU, clock frequency, peripheral overview, etc.)

+
version = the string is defining the version of the 
+description for this device. Silicon vendors will maintain the description 
+throughout the lifecycle of the device and need to ensure that all updated and 
+released copies have a unique version string indicating the order in which. Note: this must not be used for 
+detailing the version of the device.

+
 

+
addressUnitBits = defines the number of data bits for each address 
+increment. The value for Cortex-M based devices is  8 (byte-addressable).

+
width = defines the number of bits for the maximum single 
+transfer size allowed by the bus interface hence the maximum size of a single 
+register that can be defined for the address space. This information is relevant 
+for debuggers when determining the size of debug transfers. The expected value 
+for Cortex-M based devices is 32.

+
peripherals = next level of description (see next section 
+for details)

+
Optional Items:

+
size = defines the default bit-width of registers contained 
+in the device. This element can be overruled by re-specifying the size element on a lower level of the 
+description.

+
access = defines the default access permissions for all 
+registers in the device. The allowed tokens are:

+  - read-only: read access is permitted. Write operations have an undefined 
+result.

+  - write-only: write access is permitted. Read operations have an 
+undefined result. 

+  -read-write: both read and write accesses are permitted. Writes affect 
+the state of the register and reads return a value related to the register

+  -writeOnce: only the first write after reset has an effect on the 
+register. Read operations deliver undefined results

+  -read-writeOnce: Read operations deliver a result related to the register 
+content. Only the first write access to this register after a reset will have an 
+effect on the register content.

+
resetValue = defines the default value of all registers 
+after a reset. There are scenarios where SW developers need to know, what the 
+reset value of a register or field is. Even though listed as optional on this 
+level of the description, silicon vendors should ensure that this information is 
+provided for all registers. 

+
resetMask = defines those bit positions set to one to be 
+taken from resetValue element. All other elements are undefined. If a register 
+does not have a defined reset value the resetMask needs to be set to 0.

+
vendorExtensions = the content and format of this section of 
+the description is unspecified. Silicon vendors may choose to provide additional 
+information. The assumption is that by default this section is completely 
+ignored by the debugger. It is up to the silicon vendor to specify the content 
+of this section and share the specification with the tool vendors. The new 
+elements shall be considered for a future version of the description format.

+
Example:

+
<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd" >
+  <name>CMSIS_Cortex-M3</name>
+  <version>0.1</version>
+  <description>ARM Cortex-M3 based Microcontroller demonstration device</description>
+  <addressUnitBits>8</addressUnitBits>
+  <width>32</width>
+  <size>32</size>
+  <access>read-write</access>
+  <resetValue>0</resetValue>
+  <resetMask>0xffffffff</resetMask>

+
  <peripherals>
+    ...
+  </peripherals>
+</device>

+
The device description above is at version 0.1 and uniquely identifies the 
+device by the name "CMSIS_Cortex-M3". The peripherals are memory mapped in a 
+byte-addressable address space with a bus width of 32 bits. The default size of 
+the registers contained in the peripherals is set to 32 bits. Unless redefined 
+for specific peripherals, registers or fields all registers are read-write 
+accessible. A reset value of 0 valid for all 32 bits as specified by the reset 
+mask is set for all registers unless overruled at a lower level of the description.

+

+
<peripherals>

+
   <peripheral>

+     ...

+   </peripheral>

+
     ...

+
   <peripheral>

+     ...

+   </peripheral>

+
</peripherals>

+
This construct sets the frame for all peripherals and peripheral groups contained in a device. This 
+creates a container element which ease-up processing with languages like Java.

+

+
<peripheral derivedFrom="xs:Name">

+
   <name>xs:Name</name>

+   <version>xs:string</name>

+   <description>xs:string </description>

+   <groupName>xs:string</groupName>

+   <prependToName>xs:string</prependToName>

+   <appendToName>xs:string</appendToName>

+   <disableCondition>xs:string</disableCondition>

+   <baseAddress>scaledNonNegativeInteger</baseAddress>

+   <size>scaledNonNegativeInteger</size>

+   <access>accessType</access>

+   <resetValue>scaledNonNegativeInteger</resetValue>

+   <resetMask>scaledNonNegativeInteger</resetMask>

+
   <addressBlock>

+      <offset>scaledNonNegativeInteger</offset>

+      <size>scaledNonNegativeInteger</size>

+      <usage>usageType</usage>

+   </addressBlock>

+   ...

+  <addressBlock>

+      <offset>scaledNonNegativeInteger</offset>

+      <size>scaledNonNegativeInteger</size>

+      <usage>usageType</usage>

+   </addressBlock>

+   <interrupt>

+      <name>xs:string</name>

+      <value>scaledNonNegativeInteger</value>

+   </interrupt>

+   <registers>

+   ...

+   </registers>

+
</peripheral>

+
A peripheral encloses the description of one or more registers belonging to 
+this named peripheral. The address range allocated in the address space for this 
+peripheral is defined through one or more address ranges. An address range is 
+specified relative to the base address of the peripheral. This information 
+allows to display a memory map overview for all peripherals. Please note that 
+such a memory map does not contain any information for memories and unoccupied 
+address ranges.

+
Mandatory items:

+
name = name string used to identify the peripheral. Peripheral 
+names are required to be unique within the scope of a device.

+
baseAddress = lowest address reserved or used by the peripheral

+
description = string providing an overview of the purpose 
+and functionality of the peripheral

+
addressBlock = a peripheral may occupy one or more disparate 
+blocks in the address space. An addressBlock is a complex element consisting of 
+the mandatory elements:

+    offset: specifying the start address of an address block. It 
+is calculated from the sum of baseAddress and offset

+    size: specifying the number of addressUnitBits being covered 
+by this address block. The end address of an address block is the sum of start 
+address and the size - 1.

+    usage: the usage element is of usageType specifying 
+if the addresses within the specified address block is used for 
+registers or buffer or is reserved. 
+

+Note: registers must not be allocated 
+to an address within a reserved or buffer address range.

+
registers = next lower level of description (see next section 
+for details)

+
Optional items:

+
derivedFrom = this attribute specifies the name of a peripheral 
+that has already been described for this device. The description of that device 
+will be copied. It is mandatory to overwrite the name as well as the 
+addressOffset. All other specified information will overwrite the respective 
+elements in the copy.

+
version = the string specifies the version of this 
+peripheral description.

+
disableCondition = C language compliant logical expression 
+resulting in a true or false result. If "true" the refresh of the display 
+for this peripheral is disabled 
+and related accesses by the debugger are suppressed. Only constants and references to other registers 
+contained in the description are allowed:  
+<peripheral>-><register>-><field> (e.g.: (System->ClockControl->apbEnable == 0)). 
+Only the following operators are allowed [&&,||, ==, !=, >>, <<, &, |]. Warning! 
+This feature must only be use in case accesses from the debugger to registers of 
+un-clocked peripherals result in severe debugging failures. SVD is intended to 
+be fully static information and not include any run-time computation or 
+functions such capabilities may be added by the tools but is considered beyond 
+the scope of this description language.

+
prependToName = all register names of this peripheral have 
+their names prepended with the string specified

+
appendToName = all register names of this peripheral have 
+their names appended with the string specified

+
size = defines the default bit-width of registers contained 
+in the device. This element can be overruled by re-specifying the size element on a lower level of the 
+description.

+
access = defines the default access permissions for all 
+registers in the peripheral. The value can be reset on a lower level of the 
+description. The allowed tokens are:

+  - read-only: read access is permitted. Write operations have an undefined 
+result.

+  - write-only: write access is permitted. Read operations have an 
+undefined result. 

+  -read-write: both read and write accesses are permitted. Writes affect 
+the state of the register and reads return a value related to the register

+  -writeOnce: only the first write after reset has an effect on the 
+register. Read operations deliver undefined results

+  -read-writeOnce: Read operations deliver a result related to the register 
+content. Only the first write access to this register after a reset will have an 
+effect on the register content.

+
resetValue = defines the default value of all registers 
+after a reset but can be set for individual registers and fields on a lower 
+level of the description.

+
resetMask = defines those bit positions set to one to be 
+taken from resetValue element. All other elements are undefined. This is the 
+default value for the whole peripheral but can be readjusted on lower levels. If 
+a register does not have a defined reset value the resetMask needs to be set to 
+0.

+
interrupt = is a complex type that consists of the name of 
+the interrupt and the associated enumeration value. A peripheral can also have 
+multiple associated interrupts. This entry is mainly intended for information 
+only purposes in order to display the interrupts and respective interrupt 
+numbers associated with a peripheral.

+
Example:

+
... 
+    <peripheral>
+       <name>Timer0</name>
+       <version>1.0.32</version>
+       <description>Timer 0 is a simple 16 bit timer counting down ... </description>
+       <baseAddress>0x40000000</baseAddress>
+       <addressBlock>
+         <offset>0x0</offset>
+         <size>0x400</size>
+         <usage>registers</usage>
+       </addressBlock>
+       <interrupt><name>TIM0_INT</name><value>34</value></interrupt>
+       <registers>
+         ...
+       </registers>
+    </peripheral>
+    <peripheral derivedFrom="Timer0">
+      <name>Timer1</name>
+      <baseAddress>0x40000400</baseAddress>
+    </peripheral>
+
+...

+

+
<registers> ... </registers>

+
This construct sets the frame for all registers contained in a peripheral. 
+This creates container elements which ease-up processing with languages like Java.

+

+
<register derivedFrom=xs:Name>

+
   <dim>scaledNonNegativeInteger</dim>

+   <dimIncrement>scaledNonNegativeInteger</dimIncrement>

+   <dimIndex>xs:string</dimIndex>

+   <name>xs:Name</name>

+   <displayName>xs:string</displayName>

+   <description>xs:string</description>

+   <alternateGroup>xs:Name</alternateGroup>

+   <addressOffset>scaledNonNegativeInteger 
+</addressOffset>

+    <size>scaledNonNegativeInteger</size>

+   <access>accessType</access>

+   <resetValue>scaledNonNegativeInteger</resetValue>

+   <resetMask>scaledNonNegativeInteger</resetMask>

+
+   <modifiedWriteValues>writeValueType</modifiedWriteValues>

+   <writeConstraint>writeConstraintType</writeConstraint>

+   <readAction>readActionType </readAction>

+   <fields>

+      ...

+   </fields> 

+
</register>

+
The definition of registers is the central part of the description. A 
+register may use its complete size for a single purpose and therefore not 
+consist of fields. Otherwise the description 
+of fields is mandatory.

+
Mandatory items:

+

+
name = name string used to identify the register. Register 
+names are required to be unique within the scope of a peripheral.

+
description = string describing the details of the register.

+
addressOffset = value defining the address of the register relative to 
+the baseAddress defined by the peripheral the register belongs to.

+

+
The following elements can be omitted if the corresponding value has been set 
+on a higher level of the description and matches the value required for this register:

+
size =value defining the bit-width of the register

+
access = predefined tokens: read-only, write-only, read-write, 
+writeOnce, read-writeOnce strings defining the allowed 
+accesses for this register.

+
resetValue = element defining the value of the register 
+immediately after a reset.

+
resetMask= element specifying those bits of the resetValue that 
+are defined (bit positions containing a 0 bit are ignored, bit 
+positions containing a 1 bit are taken from the corresponding bit position of 
+the resetValue). If a register does not have a defined reset value the resetMask 
+needs to be set to 0.

+
Optional items:

+
dim = if this field is specified the value defines the 
+number of elements in an array of registers.

+
dimIncrement = if dim is specified this element becomes 
+mandatory and specifies the address increment in between 
+two neighboring registers of the register array in the address map.

+
dimIndex = this element specifies the substrings within the 
+register array names that will replace the %s within the register name. By 
+default the index is a decimal value starting with 0 for the first register. 
+Examples:

+   <dim>6</dim> <dimIncrement>4</dimIncrement> <dimIndex>A,B,C,D,E,Z</dimIndex> 
+<name>GPIO_%s_CTRL</name> ...

+   => GPIO_A_CTRL, GPIO_B_CTRL, GPIO_C_CTRL, GPIO_D_CTRL, GPIO_E_CTRL, 
+GPIO_Z_CTRL

+   <dim>4</dim> <dimIncrement>4</dimIncrement> <dimIndex>3-6</dimIndex> 
+<name>IRQ%s</name> ... 

+   => IRQ3, IRQ4, IRQ5, IRQ6                  

+
displayName = when used, this is the string being used by a 
+graphical frontend to visualize the register otherwise the name element is used. 
+Note: the display name may contain special characters and white spaces. It also 
+uses "%s" as the place holder for the dimIndex substring.

+
alternateGroup = when used, this element specifies a name of 
+a group that all alternate register with the same name a associated with. At the 
+same time it indicates that there is a register description allocating the same 
+absolute address in the address space. 

+
modifiedWriteValues = element to describe the manipulation of 
+data written to a register. If not specified the value written to the field is the 
+value stored in the field. The other options are bitwise operations: 

+  oneToClear: write data bits of one shall clear (set to zero) the 
+corresponding bit in the register

+  oneToSet: write data bits of one shall set (set to one) the 
+corresponding bit in the register

+  oneToToggle: write data bits of one shall toggle (invert) the 
+corresponding bit in the register

+  zeroToClear: write data bits of zero shall clear (set to zero) 
+the corresponding bit in the register

+  zeroToSet: write data bits of zero shall set (set to one) the 
+corresponding bit in the register

+  zeroToToggle: write data bits of zero shall toggle (invert) the 
+corresponding bit in the register

+  clear: after a write operation all bits in the field are cleared (set to 
+zero)

+  set: after a write operation all bits in the field are set (set to one)

+  modify: after a write operation all bit in the field may be modified 
+(default)

+
writeConstraint: has a set of options:

+  writeAsRead = if true only the last read value can be written

+  useEnumeratedValues = if true only those values listed in the 
+enumeratedValues list are considered valid write values

+  minimum = specifies the smallest number to be written to the 
+register

+  maximum = specifies the largest number to be written to the 
+register

+
readAction: if set it specifies the side effect following 
+read operations. If not set the register is not modified following a read 
+operations. The defined side effects are:

+  clear: indicates that the register is cleared (set to zero) 
+following a read operation

+  set: indicates that the register is set (set to ones) following a 
+read operation

+  modify: indicates that the register is modified in some way 
+after a read operation

+  modifyExternal: indicates that one or more dependent resources 
+other than the current register 
+are immediately affected by a read (it is recommended that the register 
+description specifies these dependencies). Debuggers are not expected to read 
+this register location unless explicitly instructed by user.

+
fields = next lower level of description (see next section 
+for details).

+
Optional attribute:

+
derivedFrom = specifies the name of the register to be 
+replicated. Elements being specified underneath will override the values specified 
+from the register being derived from. Note that it is mandatory to overwrite at 
+least name and addressOffset.

+
Example:

+
... 
+       <register>
+         <name>TimerCtrl0</name>
+         <description>Timer Control Register</description>
+         <addressOffset>0x0</addressOffset>
+         <access>read-write</access>
+         <resetValue>0x00008001</resetValue>
+         <resetMask>0x0000ffff</resetMask>
+         <size>32<size>
+         <fields>
+           ...
+         </fields>
+       </register>
+       <register derivedFrom="TimerCtrl0">
+         <name>TimerCtrl1</name>
+         <addressOffset>0x4<addressOffset>
+       </register>
+...

+

+
<fields> ... </fields>

+
This construct sets the frame for all fields contained in a register. 
+This creates container elements which ease-up processing with languages like Java.

+

+
 <field derivedFrom="xs:Name">

+
   <name>xs:Name</name>

+   <description>xs:string</description>

+   
+<bitOffset>scaledNonNegativeInteger</bitOffset>
+<bitWidth>scaledNonNegativeInteger</bitWidth>

+   or

+   <lsb>scaledNonNegativeInteger</lsb> <msb>scaledNonNegativeInteger</msb>

+   or

+   <bitRange>pattern</bitRange>

+   <access>accessType</access>

+   <modifiedWriteValues>writeValueType</modifiedWriteValues>

+   <writeConstraint>writeConstraintType</writeConstraint>

+   <readAction>readActionType </readAction>

+   <enumeratedValues>

+      ...

+   </enumeratedValues>

+
</field>

+
A bit-field has a name that is unique for the register it belongs to. The 
+position and size within the register is either described by the combination of 
+the least significant bit's position (lsb) and the most significant bit's 
+position (msb) or the lsb and the size, specifying the bit-width of the 
+field.  A field may define an enumeratedValue in order to make the display 
+more intuitive to read. 

+
Mandatory items:

+
name = name string used to identify the field. Field names 
+are required to be unique within the scope of a register.

+

+
description = string describing the details of the register.

+

+
There are 3 ways to describe a field to be used mutually exclusive:

+a) specifying bitOffset and bitWidth (IP-XACT like)

+b) specifying lsb and msb of the field.

+c) specifying a bit range in the format "[<msb>:<lsb>]"

+
bitOffset = value defining the position of the least significant bit 
+of the field within the register it belongs to.

+bitWidth = value defining the bit-width of the bitfield within the 
+register it belongs to.

+

+

+lsb = value defining the bit position of the least significant 
+bit within the register it belongs to.

+msb = value defining the bit position of the most significant 
+bit within the register it belongs to. 
+

+
bitRange = a string in the format: [<msb>:<lsb>]

+

+
Optional items:

+
derivedFrom = the field is cloned 
+from a previously defined field with a unique name.

+
access = predefined strings defining the allowed 
+accesses for this register: read-only, write-only, read-write, writeOnce, 
+read-writeOnce. Can be omitted if it matches the access permission set for the parent register.

+
enumeratedValues = next lower level of description (see next section 
+for details)

+
modifiedWriteValues = element to describe the manipulation of 
+data written to a field. If not specified the value written to the field is the 
+value stored in the field. The other options are bitwise operations: 

+  oneToClear: write data bit of one shall clear (set to zero) the 
+corresponding bit in the field

+  oneToSet: write data bit of one shall set (set to one) the corresponding 
+bit in the field

+  oneToToggle: write data bit of one shall toggle (invert) the 
+corresponding bit in the field

+  zeroToClear: write data bit of zero shall clear (set to zero) the 
+corresponding bit in the field

+  zeroToSet: write data bit of zero shall set (set to one) the 
+corresponding bit in the field

+  zeroToToggle: write data bit of zero shall toggle (invert) the 
+corresponding bit in the field

+  clear: after a write operation all bits in the field are cleared (set to 
+zero)

+  set: after a write operation all bits in the field are set (set to one)

+  modify: after a write operation all bit in the field may be modified 
+(default)

+
writeConstraint: has a set of options:

+  writeAsRead = if true only the last read value can be written

+  useEnumeratedValues = if true only those values listed in the 
+enumeratedValues list are considered valid write values

+  minimum = specifies the smallest number to be written to the field

+  maximum = specifies the largest number to be written to the field

+
readAction: if set it specifies the side effect following 
+read operations. If not set the field is not modified following a read 
+operations. The defined side effects are:

+  clear: indicates that the field is cleared (set to zero) 
+following a read operation

+  set: indicates that the field is set (set to ones) following a 
+read operation

+  modify: indicates that the field is modified in some way after a 
+read operation 
+

+  modifyExternal: indicates that one or more dependent resources 
+other than this field are immediately affected by a read (it is recommended that 
+the field description specifies these dependencies). Debuggers are not expected 
+to read the field unless explicitly instructed by user.

+
Example:

+
...
+         <field>
+           <name>TimerCtrl0_IntSel</name>
+           <description>Select interrupt line that is triggered by timer overflow.</description>
+	   <bitOffset>1</bitOffset>
+           <bitWidth>3</bitWidth>
+           <access>read-write</access>
+	   <resetValue>0x0</resetValue>
+           <modifiedWriteValues>oneToSet</modifiedWriteValues>
+           <writeConstraint>
+              <range>
+                <minimum>0</minimum>
+                <maximum>5</maximum>
+              </range>
+           </writeConstraint>
+           <readAction>clear</readAction>
+ 
+           <enumeratedValues>
+              ...
+           </enumeratedValues>
+         </field>
+...

+

+
<enumeratedValues 
+derivedFrom="xs:Name">

+
   <name>xs:Name</name>

+   <usage>usageType</usage>

+   <enumeratedValue>

+      ...

+   </enumeratedValue>

+
      ... 

+
   <enumeratedValue>

+      ...

+   </enumeratedValue>

+
</enumeratedValues>

+
An enumerated value provides one or more enumeration items (enumeratedValue), defining a map 
+between all possible values of the bit-field it belongs to and the corresponding 
+human readable semantics of that value.

+
Mandatory items:

+enumeratedValue = next lower level of description (see next section 
+for details)

+
Optional items:

+derivedFrom = the enumeratedValues can be copied or derived 
+from a previously defined enumeratedValue that has been given a unique name.

+name = name string to identify an enumeratedValue. Named 
+enumeratedValues need to be unique in the scope of a device in order to be reusable 
+throughout the description of a device.

+usage = possible values are read, write or
+read-write. This allows to specify two different enumerated values 
+depending whether it is to be used for a read or a write access. If not specified the enueratedValues are valid for read and write.

+
Example:

+
...
+           <enumeratedValues>
+              <name>TimerIntSelect</name>
+              <usage>read-write</usage>
+              <enumeratedValue>
+                <name>disabled</name>
+                <description>disabled bit</description>
+                <value>0</value>
+              </enumeratedValue>
+              ...
+              <enumeratedValue>
+                <name>reserved</name>
+	        <description>reserved values. Do not use</description>
+                <isDefault>true</isDefault>
+              </enumeratedValue>
+           </enumeratedValues>
+...

+

+
<enumeratedValue>

+
   <name>xs:name</name>

+   <description>xs:string</description>

+   <value>scaledNonNegativeInteger</value>

+  
+or

+   <isDefault>xs:boolean</isDefault>

+

+
</enumeratedValue>

+
An enumeratedValue defines a map between a value and the string reading the 
+corresponding human readable semantics for that value in a brief and a detailed 
+version

+
Mandatory items:

+
name= brief string verbally describing the semantics of the value 
+defined for this enumeratedValue. E.g. used for display in visualization of a bit-field 
+instead of the value.

+

+value = defines the constant of the bit-field that the name 
+corresponds to.

+
isDefault = defines the name and description for all other 
+values that are not explicitly listed

+
Optional item:

+
description = extended string verbally describing the semantics 
+of the value defined for this enumeratedValue in full detail.

+
Example:

+
...
+         <enumeratedValue>
+            <name>disabled</name>
+            <description>Timer does not generate interrupts</description>
+            <value>0</value>
+         </enumeratedValue>
+         ...
+         <enumeratedValue>
+            <name>enabled</name>
+            <description>Timer does not generate interrupts</description>
+            <isDefault>true</isDefault>
+         </enumeratedValue>
+
+...

+

+
Names

+
Names shall comply with ANSI C variable naming restrictions.

+
Constants

+
Number constants shall be entered in hexadecimal, decimal or binary format.

+
    
+				
  • hexadecimal is indicated by a leading "0x"
    • 
+				
  • binary format is indicated by a leading  "#"
    • 
+				
  • all other formats are interpreted as decimal numbers
    • 
+				
  • the value tag in enumeratedValue accepts do not care bits 
+				represented by "x"
    • 
+

+
Comments 

+
Comments have the standard XML format "<!--" starts a comment
+	"-->" terminates a comment

+
Example

+
+<?xml version="1.0" encoding="utf-8"?>
+ 
+<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd" >
+  <name>Cortex_M3_Sample</name>
+  <version>0.1</version>
+  <description>ARM Cortex-M3 based Microcontroller dummy device</description>
+  <!-- Bus Interface Properties -->
+  <!-- Cortex-M3 is byte addressable -->
+  <addressUnitBits>8</addressUnitBits>
+  <!-- the maximum data bit width accessible within a single transfer is 32bits -->
+  <width>32</width>
+
+  <!-- Register Default Properties -->
+  <!-- the size of the registers is set to a bit width of 32. This can be overruled for individual peripherals and/or registers -->
+  <size>32</size>
+  <!-- the access to all registers is set to be readable and writeable. This can be overruled for individual peripherals and/or registers -->
+  <access>read-write</access>
+  <!-- for demonstration purposes the resetValue for all registers of the device is set to be 0. This can be overruled within the description -->
+  <resetValue>0</resetValue>
+  <!-- the resetMask = 0 specifies that by default no register of this device has a defined reset value -->
+  <resetMask>0</resetMask>
+
+  <peripherals>
+    <peripheral>
+      <name>Timer0</name>
+      <description>A simple 16 bit timer counting down ... </description>
+      <groupName>Timer</groupName>
+      <baseAddress>0x40000000</baseAddress>
+      <!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x8</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <addressBlock>
+        <offset>0x8</offset>
+        <size>0x3f8</size>
+        <usage>reserved</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TIM0_IRQn</name>
+        <value>34</value>
+      </interrupt>
+      <registers>
+        <register> 
+          <name>TimerCtrl0</name>
+          <!-- the display name is an unrestricted string. -->
+          <displayName>Timer Ctrl 0</displayName>
+          <description>Timer Control Register</description>
+          <addressOffset>0x0</addressOffset>
+          <!-- size=32, access=read-write, resetValue=0x0, resetMask=0xffffffff, volatile=false -->
+          <fields>
+            <field>
+              <name>TimerCtrl0_En</name>
+              <description>Enable Bit activates the timer.</description>
+              <!-- Spirit like bit range description: [0:0] -->
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <!-- Writing 1 enables, writing 0 has no effect -->
+	      <modifiedWriteValues>oneToSet</modifiedWriteValues>
+              <!-- The write constraint is defined to be that only the values provided by the enumeratedValues below are allowed -->
+              <writeConstraint>
+                <useEnumeratedValues>true</useEnumeratedValues>
+              </writeConstraint>
+              <!-- there is no side effect on reads, therefore <readAction> is not set -->
+              <!-- oneBitEnable named enumeration that can be reused in other parts of the description -->
+              <enumeratedValues>
+                <name>oneBitEnable</name>
+                <!-- the same enumerated Values are used for read and write. This default is assumed when this tag is missing -->
+                <usage>read-write</usage>
+                <enumeratedValue>
+                  <name>enabled</name>
+                  <description>Timer is enabled and active</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>disabled</name>
+                  <description>Timer is disabled and inactive</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TimerCtrl0_Dis</name>
+              <description>Disable Bit deactivates the timer.</description>
+              <!-- Spirit like bit range description: [1:1] -->
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <!-- Writing 1 sets, writing 0 has no effect -->
+	      <modifiedWriteValues>oneToSet</modifiedWriteValues>
+              <!-- The write constraint is defined to be that only the values provided by the enumeratedValues below are allowed -->
+              <writeConstraint>
+                <useEnumeratedValues>true</useEnumeratedValues>
+              </writeConstraint>
+              <!-- there is no side effect on reads, therefore <readAction> is not set -->
+              <!-- oneBitEnable named enumeration that can be reused in other parts of the description -->
+              <enumeratedValues derivedFrom="oneBitEnable"></enumeratedValues>
+            </field>
+            <field>
+              <name>TimerCtrl0_Int</name>
+              <description>Select interrupt line that is triggered by timer overflow.</description>
+              <!-- the position of the bit field is described in the bitRange style. -->
+              <bitRange>[4:2]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>disabled</name>
+                  <description>Timer does not generate interrupts</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>int 0</name>
+                  <description>Timer does generate interrupts on interrupt line 0</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>int 1</name>
+                  <description>Timer does generate interrupts on interrupt line 1</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>int 2</name>
+                  <description>Timer does generate interrupts on interrupt line 2</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>int 3</name>
+                  <description>Timer does generate interrupts on interrupt line 3</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>int 4</name>
+                  <description>Timer does generate interrupts on interrupt line 4</description>
+                  <value>5</value>
+                </enumeratedValue>
+                <!-- this is the default element. All the valid value not listed above (6,7) have the following name and description -->
+                <enumeratedValue>
+                  <name>reserved</name>
+                  <description>Timer is configured incorrectly and the functionality is considered unpredictable</description>
+                  <isDefault>true</isDefault>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TimerCounter0</name>
+          <description>Timer0 16 Bit Counter Register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>16</size>
+        </register>
+        <!-- a copy of the counter register TimerCounter0 with the name="TimerCounter1" and the addressOffset="0x8" -->
+        <register derivedFrom="TimerCounter0">
+          <name>TimerCounter1</name>
+          <addressOffset>0x6</addressOffset>
+        </register>
+        <!-- ... this is a restricted demo example and a real timer peripheral would have more register to be complete -->
+      </registers>
+    </peripheral>
+    <!-- a copy of Timer0 with the name="Timer1 and the baseAddress="0x40000400" -->
+    <peripheral derivedFrom="Timer0">
+      <name>Timer1</name>
+      <baseAddress>0x40000400</baseAddress>
+      <interrupt>
+        <name>TIM1_IRQn</name>
+        <value>35</value>
+      </interrupt>
+    </peripheral>
+  </peripherals>
+</device>

+
+
Questions & Answers

+
Is there any relation between the System View Description and the CMSIS 
+standard?

+
Initiallly there was no immediate link but both initiatives had a common goal: 
+Create a sound software development eco-system for Cortex-M based 
+Microcontroller, giving the customers the free choice of devices and software 
+development environments and all resources required for a successful product 
+development in a single location. Meanwhile we have started to generate 
+CMSIS compliant device header files from the same CMSIS-SVD description. We will 
+introduce a small number of additional description tags in the next version of 
+the specification. The benefit is the synchronization between symbols used in 
+the application and the symbols displayed by the debugger.  

+
Why does the format not provide constructs like macros and 
+conditional statements?

+
It is assumed that the description is generated from other sources and 
+therefore such concepts would only complicate the language unnecessarily. It is 
+recommended to use a standard C pre-processor to generate the debug description 
+format from a redundancy optimized description.

+
Do we need to consider endianess in the description?

+
This should be specified on a device configuration level and is not specific 
+to the visualization of peripheral details in a System View. Endianess becomes 
+relevant when using bit fields in the CMSIS compliant device header file.

+
Is the System View Description limited to Cortex-M based devices ?

+
+
+
There may have been assumptions made about the structure of the device due to 
+it being developed around a Cortex-M processor. E.g. that all peripherals are 
+assumed to be memory mapped and to reside in a single address space. It is quite 
+likely that the description format may also serve other architectures 
+sufficiently. There is no intent to limit the format to Cortex-M 
+processor based devices. 

+
+
+
\ No newline at end of file
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@@ -0,0 +1,3 @@
+
+NOTE - Open the index.html file inside the html directory to access CMSIS DSP Library documentation
+
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+CMSIS DSP Software Library: Data Structures
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Data Structures
  

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+Here are the data structures with brief descriptions:
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arm_bilinear_interp_instance_f32Instance structure for the floating-point bilinear interpolation function 
arm_bilinear_interp_instance_q15Instance structure for the Q15 bilinear interpolation function 
arm_bilinear_interp_instance_q31Instance structure for the Q31 bilinear interpolation function 
arm_bilinear_interp_instance_q7Instance structure for the Q15 bilinear interpolation function 
arm_biquad_cas_df1_32x64_ins_q31Instance structure for the high precision Q31 Biquad cascade filter 
arm_biquad_cascade_df2T_instance_f32Instance structure for the floating-point transposed direct form II Biquad cascade filter 
arm_biquad_casd_df1_inst_f32Instance structure for the floating-point Biquad cascade filter 
arm_biquad_casd_df1_inst_q15Instance structure for the Q15 Biquad cascade filter 
arm_biquad_casd_df1_inst_q31Instance structure for the Q31 Biquad cascade filter 
arm_cfft_radix4_instance_f32Instance structure for the floating-point CFFT/CIFFT function 
arm_cfft_radix4_instance_q15Instance structure for the Q15 CFFT/CIFFT function 
arm_cfft_radix4_instance_q31Instance structure for the Q31 CFFT/CIFFT function 
arm_dct4_instance_f32Instance structure for the floating-point DCT4/IDCT4 function 
arm_dct4_instance_q15Instance structure for the Q15 DCT4/IDCT4 function 
arm_dct4_instance_q31Instance structure for the Q31 DCT4/IDCT4 function 
arm_fir_decimate_instance_f32Instance structure for the floating-point FIR decimator 
arm_fir_decimate_instance_q15Instance structure for the Q15 FIR decimator 
arm_fir_decimate_instance_q31Instance structure for the Q31 FIR decimator 
arm_fir_instance_f32Instance structure for the floating-point FIR filter 
arm_fir_instance_q15Instance structure for the Q15 FIR filter 
arm_fir_instance_q31Instance structure for the Q31 FIR filter 
arm_fir_instance_q7Instance structure for the Q7 FIR filter 
arm_fir_interpolate_instance_f32Instance structure for the floating-point FIR interpolator 
arm_fir_interpolate_instance_q15Instance structure for the Q15 FIR interpolator 
arm_fir_interpolate_instance_q31Instance structure for the Q31 FIR interpolator 
arm_fir_lattice_instance_f32Instance structure for the floating-point FIR lattice filter 
arm_fir_lattice_instance_q15Instance structure for the Q15 FIR lattice filter 
arm_fir_lattice_instance_q31Instance structure for the Q31 FIR lattice filter 
arm_fir_sparse_instance_f32Instance structure for the floating-point sparse FIR filter 
arm_fir_sparse_instance_q15Instance structure for the Q15 sparse FIR filter 
arm_fir_sparse_instance_q31Instance structure for the Q31 sparse FIR filter 
arm_fir_sparse_instance_q7Instance structure for the Q7 sparse FIR filter 
arm_iir_lattice_instance_f32Instance structure for the floating-point IIR lattice filter 
arm_iir_lattice_instance_q15Instance structure for the Q15 IIR lattice filter 
arm_iir_lattice_instance_q31Instance structure for the Q31 IIR lattice filter 
arm_linear_interp_instance_f32Instance structure for the floating-point Linear Interpolate function 
arm_lms_instance_f32Instance structure for the floating-point LMS filter 
arm_lms_instance_q15Instance structure for the Q15 LMS filter 
arm_lms_instance_q31Instance structure for the Q31 LMS filter 
arm_lms_norm_instance_f32Instance structure for the floating-point normalized LMS filter 
arm_lms_norm_instance_q15Instance structure for the Q15 normalized LMS filter 
arm_lms_norm_instance_q31Instance structure for the Q31 normalized LMS filter 
arm_matrix_instance_f32Instance structure for the floating-point matrix structure 
arm_matrix_instance_q15Instance structure for the Q15 matrix structure 
arm_matrix_instance_q31Instance structure for the Q31 matrix structure 
arm_pid_instance_f32Instance structure for the floating-point PID Control 
arm_pid_instance_q15Instance structure for the Q15 PID Control 
arm_pid_instance_q31Instance structure for the Q31 PID Control 
arm_rfft_instance_f32Instance structure for the floating-point RFFT/RIFFT function 
arm_rfft_instance_q15Instance structure for the Q15 RFFT/RIFFT function 
arm_rfft_instance_q31Instance structure for the Q31 RFFT/RIFFT function 

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+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__abs__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__abs__f32_8c.html
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+CMSIS DSP Software Library: arm_abs_f32.c File Reference
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+  

+Functions  

+  

+
arm_abs_f32.c File Reference
  

+

+

+#include "arm_math.h"

+#include <math.h>

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_abs_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)

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Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__abs__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__abs__f32_8c_source.html
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+CMSIS DSP Software Library: arm_abs_f32.c Source File
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Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__abs__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__abs__q15_8c.html
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+CMSIS DSP Software Library: arm_abs_q15.c File Reference
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+  

+Functions  

+  

+
arm_abs_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_abs_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

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Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__abs__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__abs__q15_8c_source.html
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+CMSIS DSP Software Library: arm_abs_q15.c Source File
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Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__abs__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__abs__q31_8c.html
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+CMSIS DSP Software Library: arm_abs_q31.c File Reference
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+Functions  

+  

+
arm_abs_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
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+
+

+Functions
void arm_abs_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

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Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__abs__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__abs__q31_8c_source.html
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+CMSIS DSP Software Library: arm_abs_q31.c Source File
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Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__abs__q7_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__abs__q7_8c.html
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+CMSIS DSP Software Library: arm_abs_q7.c File Reference
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+Functions  

+  

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arm_abs_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

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+

+Functions
void arm_abs_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)

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Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__abs__q7_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__abs__q7_8c_source.html
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+
+
+CMSIS DSP Software Library: arm_abs_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__add__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__add__f32_8c.html
new file mode 100644
index 000000000..bdc39ac7b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__add__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_add_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_add_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_add_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__add__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__add__f32_8c_source.html
new file mode 100644
index 000000000..a6de21656
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__add__f32_8c_source.html
@@ -0,0 +1,161 @@
+
+
+
+
+CMSIS DSP Software Library: arm_add_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__add__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__add__q15_8c.html
new file mode 100644
index 000000000..a8ec01567
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__add__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_add_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_add_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_add_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__add__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__add__q15_8c_source.html
new file mode 100644
index 000000000..040323fdd
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__add__q15_8c_source.html
@@ -0,0 +1,174 @@
+
+
+
+
+CMSIS DSP Software Library: arm_add_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__add__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__add__q31_8c.html
new file mode 100644
index 000000000..c190d565f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__add__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_add_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_add_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_add_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__add__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__add__q31_8c_source.html
new file mode 100644
index 000000000..588759670
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__add__q31_8c_source.html
@@ -0,0 +1,175 @@
+
+
+
+
+CMSIS DSP Software Library: arm_add_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__add__q7_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__add__q7_8c.html
new file mode 100644
index 000000000..9b2192ec9
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__add__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_add_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_add_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_add_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__add__q7_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__add__q7_8c_source.html
new file mode 100644
index 000000000..820838885
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__add__q7_8c_source.html
@@ -0,0 +1,173 @@
+
+
+
+
+CMSIS DSP Software Library: arm_add_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__32x64__init__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__32x64__init__q31_8c.html
new file mode 100644
index 000000000..275b77a56
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__32x64__init__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_32x64_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_32x64_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_biquad_cas_df1_32x64_init_q31 (arm_biquad_cas_df1_32x64_ins_q31 *S, uint8_t numStages, q31_t *pCoeffs, q63_t *pState, uint8_t postShift)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__32x64__init__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__32x64__init__q31_8c_source.html
new file mode 100644
index 000000000..b36c37c8a
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__32x64__init__q31_8c_source.html
@@ -0,0 +1,130 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_32x64_init_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__32x64__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__32x64__q31_8c.html
new file mode 100644
index 000000000..ec4e914db
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__32x64__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_32x64_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_32x64_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_biquad_cas_df1_32x64_q31 (const arm_biquad_cas_df1_32x64_ins_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__32x64__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__32x64__q31_8c_source.html
new file mode 100644
index 000000000..93966d095
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__32x64__q31_8c_source.html
@@ -0,0 +1,405 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_32x64_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__f32_8c.html
new file mode 100644
index 000000000..03352c51b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_biquad_cascade_df1_f32 (const arm_biquad_casd_df1_inst_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__f32_8c_source.html
new file mode 100644
index 000000000..58e5b9404
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__f32_8c_source.html
@@ -0,0 +1,356 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__fast__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__fast__q15_8c.html
new file mode 100644
index 000000000..add09a6d0
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__fast__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_fast_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_fast_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_biquad_cascade_df1_fast_q15 (const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__fast__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__fast__q15_8c_source.html
new file mode 100644
index 000000000..e211ac2da
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__fast__q15_8c_source.html
@@ -0,0 +1,322 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_fast_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__fast__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__fast__q31_8c.html
new file mode 100644
index 000000000..727376977
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__fast__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_fast_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_fast_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_biquad_cascade_df1_fast_q31 (const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__fast__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__fast__q31_8c_source.html
new file mode 100644
index 000000000..098077007
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__fast__q31_8c_source.html
@@ -0,0 +1,308 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_fast_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__f32_8c.html
new file mode 100644
index 000000000..98e998287
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_biquad_cascade_df1_init_f32 (arm_biquad_casd_df1_inst_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__f32_8c_source.html
new file mode 100644
index 000000000..8e3ad0997
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__f32_8c_source.html
@@ -0,0 +1,129 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_init_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__q15_8c.html
new file mode 100644
index 000000000..5ed36d7cd
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_biquad_cascade_df1_init_q15 (arm_biquad_casd_df1_inst_q15 *S, uint8_t numStages, q15_t *pCoeffs, q15_t *pState, int8_t postShift)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__q15_8c_source.html
new file mode 100644
index 000000000..1ea314682
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@@ -0,0 +1,133 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_init_q15.c Source File
+
+
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+
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+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__q31_8c.html
new file mode 100644
index 000000000..fe634c141
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_biquad_cascade_df1_init_q31 (arm_biquad_casd_df1_inst_q31 *S, uint8_t numStages, q31_t *pCoeffs, q31_t *pState, int8_t postShift)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__q31_8c_source.html
new file mode 100644
index 000000000..f3ba98c79
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__q31_8c_source.html
@@ -0,0 +1,134 @@
+
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+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_init_q31.c Source File
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__q15_8c.html
new file mode 100644
index 000000000..8b0727fde
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@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_biquad_cascade_df1_q15 (const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__q15_8c_source.html
new file mode 100644
index 000000000..32712f815
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__q15_8c_source.html
@@ -0,0 +1,419 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_q15.c Source File
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__q31_8c.html
new file mode 100644
index 000000000..4d5b4ca57
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_biquad_cascade_df1_q31 (const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__q31_8c_source.html
new file mode 100644
index 000000000..cfe7ce2c6
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__q31_8c_source.html
@@ -0,0 +1,402 @@
+
+
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+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_q31.c Source File
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+
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+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df2_t__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df2_t__f32_8c.html
new file mode 100644
index 000000000..7996a6ffe
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+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df2T_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_biquad_cascade_df2T_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_biquad_cascade_df2T_f32 (const arm_biquad_cascade_df2T_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)

+

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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df2_t__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df2_t__f32_8c_source.html
new file mode 100644
index 000000000..f885fef37
--- /dev/null
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@@ -0,0 +1,322 @@
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+CMSIS DSP Software Library: arm_biquad_cascade_df2T_f32.c Source File
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+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df2_t__init__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df2_t__init__f32_8c.html
new file mode 100644
index 000000000..1cbe28848
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df2_t__init__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df2T_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_biquad_cascade_df2T_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_biquad_cascade_df2T_init_f32 (arm_biquad_cascade_df2T_instance_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState)

+

+
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+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df2_t__init__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df2_t__init__f32_8c_source.html
new file mode 100644
index 000000000..776720d0e
--- /dev/null
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@@ -0,0 +1,127 @@
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+
+CMSIS DSP Software Library: arm_biquad_cascade_df2T_init_f32.c Source File
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+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__f32_8c.html
new file mode 100644
index 000000000..a8197e48e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__f32_8c.html
@@ -0,0 +1,244 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cfft_radix4_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cfft_radix4_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+

+Functions
void arm_cfft_radix4_f32 (const arm_cfft_radix4_instance_f32 *S, float32_t *pSrc)
void arm_radix4_butterfly_f32 (float32_t *pSrc, uint16_t fftLen, float32_t *pCoef, uint16_t twidCoefModifier)
void arm_radix4_butterfly_inverse_f32 (float32_t *pSrc, uint16_t fftLen, float32_t *pCoef, uint16_t twidCoefModifier, float32_t onebyfftLen)
void arm_bitreversal_f32 (float32_t *pSrc, uint16_t fftSize, uint16_t bitRevFactor, uint16_t *pBitRevTab)

+
Function Documentation

+
+

+

+      
+        
+          
+          
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+          
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+        
+      
void arm_radix4_butterfly_f32 (float32_t *  pSrc, 
uint16_t  fftLen, 
float32_t *  pCoef, 
uint16_t  twidCoefModifier 
)

+

+

+
+
Core function for the floating-point CFFT butterfly process. 

+
end of CFFT_CIFFT group 

+
+
Definition at line 223 of file arm_cfft_radix4_f32.c.

+
+

+

+
+

+

+      
+        
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void arm_radix4_butterfly_inverse_f32 (float32_t *  pSrc, 
uint16_t  fftLen, 
float32_t *  pCoef, 
uint16_t  twidCoefModifier, 
float32_t  onebyfftLen 
)

+

+

+
+
Core function for the floating-point CIFFT butterfly process. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of floating-point data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
[in]onebyfftLenvalue of 1/fftLen. 

+  

+

+
Returns:
none. 

+
+
Definition at line 660 of file arm_cfft_radix4_f32.c.

+
+

+

+
+

+

+      
+        
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+          
+          
+        
+      
void arm_bitreversal_f32 (float32_t *  pSrc, 
uint16_t  fftSize, 
uint16_t  bitRevFactor, 
uint16_t *  pBitRevTab 
)

+

+

+
+
In-place bit reversal function. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of floating-point data type. 
[in]fftSizelength of the FFT. 
[in]bitRevFactorbit reversal modifier that supports different size FFTs with the same bit reversal table. 
[in]*pBitRevTabpoints to the bit reversal table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 1177 of file arm_cfft_radix4_f32.c.

+
+

+

+

+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__f32_8c_source.html
new file mode 100644
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+CMSIS DSP Software Library: arm_cfft_radix4_f32.c Source File
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Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__f32_8c.html
new file mode 100644
index 000000000..403d16e5b
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+
+
+
+CMSIS DSP Software Library: arm_cfft_radix4_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_cfft_radix4_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+#include "arm_common_tables.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+

+Functions
arm_status arm_cfft_radix4_init_f32 (arm_cfft_radix4_instance_f32 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)

+Variables
static const float32_t twiddleCoef [2048]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__f32_8c_source.html
new file mode 100644
index 000000000..d3cdea7ae
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+
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+
+CMSIS DSP Software Library: arm_cfft_radix4_init_f32.c Source File
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__q15_8c.html
new file mode 100644
index 000000000..c19dc6ab7
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__q15_8c.html
@@ -0,0 +1,88 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cfft_radix4_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_cfft_radix4_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+#include "arm_common_tables.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+

+Functions
arm_status arm_cfft_radix4_init_q15 (arm_cfft_radix4_instance_q15 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)

+Variables
static const q15_t twiddleCoefQ15 [2048]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__q15_8c_source.html
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@@ -0,0 +1,435 @@
+
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+CMSIS DSP Software Library: arm_cfft_radix4_init_q15.c Source File
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+
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+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__q31_8c.html
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@@ -0,0 +1,88 @@
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+
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+CMSIS DSP Software Library: arm_cfft_radix4_init_q31.c File Reference
+
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+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_cfft_radix4_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+#include "arm_common_tables.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+

+Functions
arm_status arm_cfft_radix4_init_q31 (arm_cfft_radix4_instance_q31 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)

+Variables
static const q31_t twiddleCoefQ31 [2048]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__q31_8c_source.html
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index 000000000..38da528d7
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@@ -0,0 +1,690 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cfft_radix4_init_q31.c Source File
+
+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__q15_8c.html
new file mode 100644
index 000000000..7b1f4e633
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+
+
+
+
+CMSIS DSP Software Library: arm_cfft_radix4_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cfft_radix4_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+

+Functions
void arm_cfft_radix4_q15 (const arm_cfft_radix4_instance_q15 *S, q15_t *pSrc)
void arm_radix4_butterfly_q15 (q15_t *pSrc16, uint32_t fftLen, q15_t *pCoef16, uint32_t twidCoefModifier)
void arm_radix4_butterfly_inverse_q15 (q15_t *pSrc16, uint32_t fftLen, q15_t *pCoef16, uint32_t twidCoefModifier)
void arm_bitreversal_q15 (q15_t *pSrc16, uint32_t fftLen, uint16_t bitRevFactor, uint16_t *pBitRevTab)

+
Function Documentation

+
+

+

+      
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void arm_radix4_butterfly_q15 (q15_t *  pSrc16, 
uint32_t  fftLen, 
q15_t *  pCoef16, 
uint32_t  twidCoefModifier 
)

+

+

+
+
Core function for the Q15 CFFT butterfly process. 

+
end of CFFT_CIFFT group 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrc16points to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoef16points to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 138 of file arm_cfft_radix4_q15.c.

+
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void arm_radix4_butterfly_inverse_q15 (q15_t *  pSrc16, 
uint32_t  fftLen, 
q15_t *  pCoef16, 
uint32_t  twidCoefModifier 
)

+

+

+
+
Core function for the Q15 CIFFT butterfly process. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrc16points to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoef16points to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 1053 of file arm_cfft_radix4_q15.c.

+
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+      
void arm_bitreversal_q15 (q15_t *  pSrc, 
uint32_t  fftLen, 
uint16_t  bitRevFactor, 
uint16_t *  pBitRevTab 
)

+

+

+
+
In-place bit reversal function. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]bitRevFactorbit reversal modifier that supports different size FFTs with the same bit reversal table 
[in]*pBitRevTabpoints to bit reversal table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 1906 of file arm_cfft_radix4_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__q15_8c_source.html
new file mode 100644
index 000000000..9fbe3c676
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+
+
+
+
+CMSIS DSP Software Library: arm_cfft_radix4_q15.c Source File
+
+
+
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+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__q31_8c.html
new file mode 100644
index 000000000..5afb7e4e1
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__q31_8c.html
@@ -0,0 +1,247 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cfft_radix4_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cfft_radix4_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+

+Functions
void arm_cfft_radix4_q31 (const arm_cfft_radix4_instance_q31 *S, q31_t *pSrc)
void arm_radix4_butterfly_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pCoef, uint32_t twidCoefModifier)
void arm_radix4_butterfly_inverse_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pCoef, uint32_t twidCoefModifier)
void arm_bitreversal_q31 (q31_t *pSrc, uint32_t fftLen, uint16_t bitRevFactor, uint16_t *pBitRevTable)

+
Function Documentation

+
+

+

+      
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+      
void arm_radix4_butterfly_q31 (q31_t *  pSrc, 
uint32_t  fftLen, 
q31_t *  pCoef, 
uint32_t  twidCoefModifier 
)

+

+

+
+
Core function for the Q31 CFFT butterfly process. 

+
end of CFFT_CIFFT group 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 139 of file arm_cfft_radix4_q31.c.

+
+

+

+
+

+

+      
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+        
+      
void arm_radix4_butterfly_inverse_q31 (q31_t *  pSrc, 
uint32_t  fftLen, 
q31_t *  pCoef, 
uint32_t  twidCoefModifier 
)

+

+

+
+
Core function for the Q31 CIFFT butterfly process. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 517 of file arm_cfft_radix4_q31.c.

+
+

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+
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+      
void arm_bitreversal_q31 (q31_t *  pSrc, 
uint32_t  fftLen, 
uint16_t  bitRevFactor, 
uint16_t *  pBitRevTab 
)

+

+

+
+
In-place bit reversal function. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]bitRevFactorbit reversal modifier that supports different size FFTs with the same bit reversal table 
[in]*pBitRevTabpoints to bit reversal table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 848 of file arm_cfft_radix4_q31.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__q31_8c_source.html
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index 000000000..5d01552b8
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+CMSIS DSP Software Library: arm_cfft_radix4_q31.c Source File
+
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Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__class__marks__example__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__class__marks__example__f32_8c.html
new file mode 100644
index 000000000..764cd25fc
--- /dev/null
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+
+
+
+
+CMSIS DSP Software Library: arm_class_marks_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Defines |
+Functions |
+Variables  

+  

+
arm_class_marks_example_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define USE_STATIC_INIT
#define TEST_LENGTH_SAMPLES   (20*4)
#define NUMSTUDENTS   20
#define NUMSUBJECTS   4

+Functions
int32_t main ()

+Variables
const float32_t testMarks_f32 [TEST_LENGTH_SAMPLES]
const float32_t testUnity_f32 [4]
static float32_t testOutput [TEST_LENGTH_SAMPLES]
uint32_t numStudents = 20
uint32_t numSubjects = 4
float32_t max_marks
float32_t min_marks
float32_t mean
float32_t std
float32_t var
uint32_t student_num

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define USE_STATIC_INIT

+

+

+
+
Definition at line 69 of file arm_class_marks_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define TEST_LENGTH_SAMPLES   (20*4)

+

+

+
Examples: 
arm_class_marks_example_f32.c, arm_fft_bin_example_f32.c, arm_fir_example_f32.c, arm_linear_interp_example_f32.c, and arm_signal_converge_example_f32.c.

+

+
Definition at line 75 of file arm_class_marks_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define NUMSTUDENTS   20

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 123 of file arm_class_marks_example_f32.c.

+
+

+

+
+

+

+      
+        
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+        
+      
#define NUMSUBJECTS   4

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 124 of file arm_class_marks_example_f32.c.

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void  )

+

+

+
Examples: 
arm_class_marks_example_f32.c, arm_convolution_example_f32.c, arm_dotproduct_example_f32.c, arm_fft_bin_example_f32.c, arm_fir_example_f32.c, arm_graphic_equalizer_example_q31.c, arm_linear_interp_example_f32.c, arm_matrix_example_f32.c, arm_signal_converge_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 139 of file arm_class_marks_example_f32.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float32_t testMarks_f32[TEST_LENGTH_SAMPLES]

+

+

+Initial value:
  
+{    
+    42.000000,  37.000000,  81.000000,  28.000000,   
+    83.000000,  72.000000,  36.000000,  38.000000,   
+    32.000000,  51.000000,  63.000000,  64.000000,   
+    97.000000,  82.000000,  95.000000,  90.000000,   
+    66.000000,  51.000000,  54.000000,  42.000000,   
+    67.000000,  56.000000,  45.000000,  57.000000,   
+    67.000000,  69.000000,  35.000000,  52.000000,   
+    29.000000,  81.000000,  58.000000,  47.000000,   
+    38.000000,  76.000000,  100.000000, 29.000000,   
+    33.000000,  47.000000,  29.000000,  50.000000,   
+    34.000000,  41.000000,  61.000000,  46.000000,   
+    52.000000,  50.000000,  48.000000,  36.000000,   
+    47.000000,  55.000000,  44.000000,  40.000000,   
+    100.000000, 94.000000,  84.000000,  37.000000,   
+    32.000000,  71.000000,  47.000000,  77.000000,   
+    31.000000,  50.000000,  49.000000,  35.000000,   
+    63.000000,  67.000000,  40.000000,  31.000000,   
+    29.000000,  68.000000,  61.000000,  38.000000,   
+    31.000000,  28.000000,  28.000000,  76.000000,   
+    55.000000,  33.000000,  29.000000,  39.000000 
+}
+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 80 of file arm_class_marks_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t testUnity_f32[4]

+

+

+Initial value:
  
+{    
+    1.000,  1.000,  1.000,  1.000 
+}
+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 108 of file arm_class_marks_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testOutput[TEST_LENGTH_SAMPLES] [static]

+

+

+
Examples: 
arm_class_marks_example_f32.c, arm_dotproduct_example_f32.c, arm_fft_bin_example_f32.c, arm_fir_example_f32.c, arm_graphic_equalizer_example_q31.c, arm_linear_interp_example_f32.c, and arm_sin_cos_example_f32.c.

+

+
Definition at line 117 of file arm_class_marks_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t numStudents = 20

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 130 of file arm_class_marks_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t numSubjects = 4

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 131 of file arm_class_marks_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t max_marks

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 132 of file arm_class_marks_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t min_marks

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 132 of file arm_class_marks_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t mean

+

+

+
Examples: 
arm_class_marks_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 132 of file arm_class_marks_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t std

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 132 of file arm_class_marks_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t var

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 132 of file arm_class_marks_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t student_num

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 133 of file arm_class_marks_example_f32.c.

+
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+

+

+
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+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__class__marks__example__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__class__marks__example__f32_8c_source.html
new file mode 100644
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@@ -0,0 +1,226 @@
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+CMSIS DSP Software Library: arm_class_marks_example_f32.c Source File
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+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__f32_8c.html
new file mode 100644
index 000000000..9eb1ffa33
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_conj_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_conj_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_conj_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__f32_8c_source.html
new file mode 100644
index 000000000..84868b12f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__f32_8c_source.html
@@ -0,0 +1,171 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_conj_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__q15_8c.html
new file mode 100644
index 000000000..d266b0628
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_conj_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_conj_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_conj_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__q15_8c_source.html
new file mode 100644
index 000000000..96d9a69ef
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__q15_8c_source.html
@@ -0,0 +1,171 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_conj_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__q31_8c.html
new file mode 100644
index 000000000..463c91929
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_conj_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_conj_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_conj_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__q31_8c_source.html
new file mode 100644
index 000000000..1eb0d09c8
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__q31_8c_source.html
@@ -0,0 +1,179 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_conj_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__f32_8c.html
new file mode 100644
index 000000000..2823695cc
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_dot_prod_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_dot_prod_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_dot_prod_f32 (float32_t *pSrcA, float32_t *pSrcB, uint32_t numSamples, float32_t *realResult, float32_t *imagResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__f32_8c_source.html
new file mode 100644
index 000000000..c0394dd1d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__f32_8c_source.html
@@ -0,0 +1,182 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_dot_prod_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__q15_8c.html
new file mode 100644
index 000000000..b90697cc7
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_dot_prod_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_dot_prod_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_dot_prod_q15 (q15_t *pSrcA, q15_t *pSrcB, uint32_t numSamples, q31_t *realResult, q31_t *imagResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__q15_8c_source.html
new file mode 100644
index 000000000..6a3cb4ace
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__q15_8c_source.html
@@ -0,0 +1,184 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_dot_prod_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__q31_8c.html
new file mode 100644
index 000000000..2195b74ec
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_dot_prod_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_dot_prod_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_dot_prod_q31 (q31_t *pSrcA, q31_t *pSrcB, uint32_t numSamples, q63_t *realResult, q63_t *imagResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__q31_8c_source.html
new file mode 100644
index 000000000..e292ea3bc
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__q31_8c_source.html
@@ -0,0 +1,184 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_dot_prod_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__f32_8c.html
new file mode 100644
index 000000000..e1bd36b8b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mag_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_mag_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_mag_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__f32_8c_source.html
new file mode 100644
index 000000000..7f1716cee
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__f32_8c_source.html
@@ -0,0 +1,183 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mag_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__q15_8c.html
new file mode 100644
index 000000000..cf8cc0eb4
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mag_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_mag_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_mag_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__q15_8c_source.html
new file mode 100644
index 000000000..7d8d5905c
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__q15_8c_source.html
@@ -0,0 +1,201 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mag_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__q31_8c.html
new file mode 100644
index 000000000..e99318c68
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mag_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_mag_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_mag_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__q31_8c_source.html
new file mode 100644
index 000000000..f45c0f6db
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__q31_8c_source.html
@@ -0,0 +1,199 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mag_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__f32_8c.html
new file mode 100644
index 000000000..e6ed8a820
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mag_squared_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_mag_squared_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_mag_squared_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__f32_8c_source.html
new file mode 100644
index 000000000..c26a7bdec
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__f32_8c_source.html
@@ -0,0 +1,183 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mag_squared_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__q15_8c.html
new file mode 100644
index 000000000..3d70290d7
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mag_squared_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_mag_squared_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_mag_squared_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__q15_8c_source.html
new file mode 100644
index 000000000..145e46745
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__q15_8c_source.html
@@ -0,0 +1,197 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mag_squared_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__q31_8c.html
new file mode 100644
index 000000000..ae9e291c1
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mag_squared_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_mag_squared_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_mag_squared_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__q31_8c_source.html
new file mode 100644
index 000000000..a308689f1
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__q31_8c_source.html
@@ -0,0 +1,197 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mag_squared_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__f32_8c.html
new file mode 100644
index 000000000..7caccac01
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mult_cmplx_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_mult_cmplx_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_mult_cmplx_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__f32_8c_source.html
new file mode 100644
index 000000000..a2878c7c2
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__f32_8c_source.html
@@ -0,0 +1,209 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mult_cmplx_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__q15_8c.html
new file mode 100644
index 000000000..d6b4626b2
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mult_cmplx_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_mult_cmplx_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_mult_cmplx_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__q15_8c_source.html
new file mode 100644
index 000000000..be68eadfd
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__q15_8c_source.html
@@ -0,0 +1,230 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mult_cmplx_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__q31_8c.html
new file mode 100644
index 000000000..95dd398a7
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mult_cmplx_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_mult_cmplx_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_mult_cmplx_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__q31_8c_source.html
new file mode 100644
index 000000000..a7b3b3222
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__q31_8c_source.html
@@ -0,0 +1,255 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mult_cmplx_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__f32_8c.html
new file mode 100644
index 000000000..18f40cc34
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mult_real_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_mult_real_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_mult_real_f32 (float32_t *pSrcCmplx, float32_t *pSrcReal, float32_t *pCmplxDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__f32_8c_source.html
new file mode 100644
index 000000000..1237712c8
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__f32_8c_source.html
@@ -0,0 +1,185 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mult_real_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__q15_8c.html
new file mode 100644
index 000000000..e9db6d309
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mult_real_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_mult_real_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_mult_real_q15 (q15_t *pSrcCmplx, q15_t *pSrcReal, q15_t *pCmplxDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__q15_8c_source.html
new file mode 100644
index 000000000..76bbf4e8b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__q15_8c_source.html
@@ -0,0 +1,197 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mult_real_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__q31_8c.html
new file mode 100644
index 000000000..e57b4cada
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mult_real_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_mult_real_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_mult_real_q31 (q31_t *pSrcCmplx, q31_t *pSrcReal, q31_t *pCmplxDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__q31_8c_source.html
new file mode 100644
index 000000000..be1079d9a
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__q31_8c_source.html
@@ -0,0 +1,197 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mult_real_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__common__tables_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__common__tables_8c.html
new file mode 100644
index 000000000..2a6fff0c6
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__common__tables_8c.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_common_tables.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Variables  

+  

+
arm_common_tables.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+

+Variables
const uint16_t armBitRevTable [256]
const q15_t armRecipTableQ15 [64]
const q31_t armRecipTableQ31 [64]

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const q15_t armRecipTableQ15[64]

+

+

+Initial value:
 {
+  0x7F03, 0x7D13, 0x7B31, 0x795E, 0x7798, 0x75E0,
+  0x7434, 0x7294, 0x70FF, 0x6F76, 0x6DF6, 0x6C82,
+  0x6B16, 0x69B5, 0x685C, 0x670C, 0x65C4, 0x6484,
+  0x634C, 0x621C, 0x60F3, 0x5FD0, 0x5EB5, 0x5DA0,
+  0x5C91, 0x5B88, 0x5A85, 0x5988, 0x5890, 0x579E,
+  0x56B0, 0x55C8, 0x54E4, 0x5405, 0x532B, 0x5255,
+  0x5183, 0x50B6, 0x4FEC, 0x4F26, 0x4E64, 0x4DA6,
+  0x4CEC, 0x4C34, 0x4B81, 0x4AD0, 0x4A23, 0x4978,
+  0x48D1, 0x482D, 0x478C, 0x46ED, 0x4651, 0x45B8,
+  0x4521, 0x448D, 0x43FC, 0x436C, 0x42DF, 0x4255,
+  0x41CC, 0x4146, 0x40C2, 0x4040
+}
+
end of CFFT_CIFFT group 

+
+
Definition at line 115 of file arm_common_tables.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t armRecipTableQ31[64]

+

+

+Initial value:
 {
+  0x7F03F03F, 0x7D137420, 0x7B31E739, 0x795E9F94, 0x7798FD29, 0x75E06928,
+  0x7434554D, 0x72943B4B, 0x70FF9C40, 0x6F760031, 0x6DF6F593, 0x6C8210E3,
+  0x6B16EC3A, 0x69B526F6, 0x685C655F, 0x670C505D, 0x65C4952D, 0x6484E519,
+  0x634CF53E, 0x621C7E4F, 0x60F33C61, 0x5FD0EEB3, 0x5EB55785, 0x5DA03BEB,
+  0x5C9163A1, 0x5B8898E6, 0x5A85A85A, 0x598860DF, 0x58909373, 0x579E1318,
+  0x56B0B4B8, 0x55C84F0B, 0x54E4BA80, 0x5405D124, 0x532B6E8F, 0x52556FD0,
+  0x5183B35A, 0x50B618F3, 0x4FEC81A2, 0x4F26CFA2, 0x4E64E64E, 0x4DA6AA1D,
+  0x4CEC008B, 0x4C34D010, 0x4B810016, 0x4AD078EF, 0x4A2323C4, 0x4978EA96,
+  0x48D1B827, 0x482D77FE, 0x478C1657, 0x46ED801D, 0x4651A2E5, 0x45B86CE2,
+  0x4521CCE1, 0x448DB244, 0x43FC0CFA, 0x436CCD78, 0x42DFE4B4, 0x42554426,
+  0x41CCDDB6, 0x4146A3C6, 0x40C28923, 0x40408102
+}
+

+
Definition at line 132 of file arm_common_tables.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__common__tables_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__common__tables_8c_source.html
new file mode 100644
index 000000000..15c8529fe
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__common__tables_8c_source.html
@@ -0,0 +1,181 @@
+
+
+
+
+CMSIS DSP Software Library: arm_common_tables.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__f32_8c.html
new file mode 100644
index 000000000..4c7cf3e86
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_conv_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_conv_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__f32_8c_source.html
new file mode 100644
index 000000000..61c2d8ff8
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__f32_8c_source.html
@@ -0,0 +1,626 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__fast__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__fast__q15_8c.html
new file mode 100644
index 000000000..d39f7d653
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__fast__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_fast_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_conv_fast_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_conv_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__fast__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__fast__q15_8c_source.html
new file mode 100644
index 000000000..13b027477
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__fast__q15_8c_source.html
@@ -0,0 +1,713 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_fast_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__fast__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__fast__q31_8c.html
new file mode 100644
index 000000000..a9a80e496
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__fast__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_fast_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_conv_fast_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_conv_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__fast__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__fast__q31_8c_source.html
new file mode 100644
index 000000000..a4525b294
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__fast__q31_8c_source.html
@@ -0,0 +1,601 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_fast_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__f32_8c.html
new file mode 100644
index 000000000..d9c433fca
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_partial_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_conv_partial_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_conv_partial_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst, uint32_t firstIndex, uint32_t numPoints)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__f32_8c_source.html
new file mode 100644
index 000000000..d043ca91f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__f32_8c_source.html
@@ -0,0 +1,673 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_partial_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__fast__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__fast__q15_8c.html
new file mode 100644
index 000000000..ff4703fd3
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__fast__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_partial_fast_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_conv_partial_fast_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_conv_partial_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__fast__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__fast__q15_8c_source.html
new file mode 100644
index 000000000..449cde144
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__fast__q15_8c_source.html
@@ -0,0 +1,751 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_partial_fast_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__fast__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__fast__q31_8c.html
new file mode 100644
index 000000000..885d423f7
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__fast__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_partial_fast_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_conv_partial_fast_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_conv_partial_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__fast__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__fast__q31_8c_source.html
new file mode 100644
index 000000000..f0a8d4e71
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__fast__q31_8c_source.html
@@ -0,0 +1,639 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_partial_fast_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q15_8c.html
new file mode 100644
index 000000000..9ad51bcbd
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_partial_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_conv_partial_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_conv_partial_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q15_8c_source.html
new file mode 100644
index 000000000..31a90ec83
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q15_8c_source.html
@@ -0,0 +1,811 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_partial_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q31_8c.html
new file mode 100644
index 000000000..1440909d4
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_partial_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_conv_partial_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_conv_partial_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q31_8c_source.html
new file mode 100644
index 000000000..859950124
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q31_8c_source.html
@@ -0,0 +1,663 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_partial_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q7_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q7_8c.html
new file mode 100644
index 000000000..b6da19035
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_partial_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_conv_partial_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_conv_partial_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, uint32_t firstIndex, uint32_t numPoints)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q7_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q7_8c_source.html
new file mode 100644
index 000000000..988b71d8b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q7_8c_source.html
@@ -0,0 +1,771 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_partial_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__q15_8c.html
new file mode 100644
index 000000000..3d7eee6f0
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_conv_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_conv_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__q15_8c_source.html
new file mode 100644
index 000000000..9d80dedcf
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__q15_8c_source.html
@@ -0,0 +1,765 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__q31_8c.html
new file mode 100644
index 000000000..2fa09eecb
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_conv_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_conv_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__q31_8c_source.html
new file mode 100644
index 000000000..e583f7442
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__q31_8c_source.html
@@ -0,0 +1,618 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__q7_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__q7_8c.html
new file mode 100644
index 000000000..386465884
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_conv_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_conv_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__q7_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__q7_8c_source.html
new file mode 100644
index 000000000..a13412f29
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__conv__q7_8c_source.html
@@ -0,0 +1,721 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__convolution__example__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__convolution__example__f32_8c.html
new file mode 100644
index 000000000..dff62b015
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__convolution__example__f32_8c.html
@@ -0,0 +1,386 @@
+
+
+
+
+CMSIS DSP Software Library: arm_convolution_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Defines |
+Functions |
+Variables  

+  

+
arm_convolution_example_f32.c File Reference
  

+

+

+#include "arm_math.h"

+#include "math_helper.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define MAX_BLOCKSIZE   128
#define DELTA   (0.000001f)
#define SNR_THRESHOLD   90

+Functions
int32_t main (void)

+Variables
float32_t Ak [MAX_BLOCKSIZE]
float32_t Bk [MAX_BLOCKSIZE]
float32_t AxB [MAX_BLOCKSIZE *2]
float32_t testInputA_f32 [64]
float32_t testInputB_f32 [64]
const float testRefOutput_f32 [126]
uint32_t srcALen = 64
uint32_t srcBLen = 64
uint32_t outLen
float32_t snr

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define MAX_BLOCKSIZE   128

+

+

+
Examples: 
arm_convolution_example_f32.c, arm_dotproduct_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 95 of file arm_convolution_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define DELTA   (0.000001f)

+

+

+
Examples: 
arm_dotproduct_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 96 of file arm_convolution_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define SNR_THRESHOLD   90

+

+

+
Examples: 
arm_convolution_example_f32.c, and arm_matrix_example_f32.c.

+

+
Definition at line 97 of file arm_convolution_example_f32.c.

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void  )

+

+

+
+
Definition at line 175 of file arm_convolution_example_f32.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t Ak[MAX_BLOCKSIZE]

+

+

+
Examples: 
arm_convolution_example_f32.c.

+

+
Definition at line 102 of file arm_convolution_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t Bk[MAX_BLOCKSIZE]

+

+

+
Examples: 
arm_convolution_example_f32.c.

+

+
Definition at line 103 of file arm_convolution_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t AxB[MAX_BLOCKSIZE *2]

+

+

+
Examples: 
arm_convolution_example_f32.c.

+

+
Definition at line 104 of file arm_convolution_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testInputA_f32[64]

+

+

+Initial value:
  
+{  
+-0.808920,  1.357369,   1.180861,   -0.504544,  1.762637,   -0.703285,   
+1.696966,   0.620571,   -0.151093,  -0.100235,  -0.872382,  -0.403579,   
+-0.860749,  -0.382648,  -1.052338,  0.128113,   -0.646269,  1.093377,    
+-2.209198,  0.471706,   0.408901,   1.266242,   0.598252,   1.176827,    
+-0.203421,  0.213596,   -0.851964,  -0.466958,  0.021841,   -0.698938,   
+-0.604107,  0.461778,   -0.318219,  0.942520,   0.577585,   0.417619,    
+0.614665,   0.563679,   -1.295073,  -0.764437,  0.952194,   -0.859222,   
+-0.618554,  -2.268542,  -1.210592,  1.655853,   -2.627219,  -0.994249,   
+-1.374704,  0.343799,   0.025619,   1.227481,   -0.708031,  0.069355,    
+-1.845228,  -1.570886,  1.010668,   -1.802084,  1.630088,   1.286090,    
+-0.161050,  -0.940794,  0.367961,   0.291907 
+         
+}
+
Examples: 
arm_convolution_example_f32.c.

+

+
Definition at line 110 of file arm_convolution_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testInputB_f32[64]

+

+

+Initial value:
  
+{  
+0.933724,   0.046881,   1.316470,   0.438345,   0.332682,   2.094885,    
+0.512081,   0.035546,   0.050894,   -2.320371,  0.168711,   -1.830493,   
+-0.444834,  -1.003242,  -0.531494,  -1.365600,  -0.155420,  -0.757692,   
+-0.431880,  -0.380021,  0.096243,   -0.695835,  0.558850,   -1.648962,   
+0.020369,   -0.363630,  0.887146,   0.845503,   -0.252864,  -0.330397,   
+1.269131,   -1.109295,  -1.027876,  0.135940,   0.116721,   -0.293399,   
+-1.349799,  0.166078,   -0.802201,  0.369367,   -0.964568,  -2.266011,   
+0.465178,   0.651222,   -0.325426,  0.320245,   -0.784178,  -0.579456,   
+0.093374,   0.604778,   -0.048225,  0.376297,   -0.394412,  0.578182,    
+-1.218141,  -1.387326,  0.692462,   -0.631297,  0.153137,   -0.638952,   
+0.635474,   -0.970468,  1.334057,   -0.111370 
+}
+
Examples: 
arm_convolution_example_f32.c.

+

+
Definition at line 126 of file arm_convolution_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float testRefOutput_f32[126]

+

+

+Initial value:
   
+{  
+-0.818943,  1.229484,   -0.533664,  1.016604,   0.341875,   -1.963656,   
+5.171476,   3.478033,   7.616361,   6.648384,   0.479069,   1.792012,    
+-1.295591,  -7.447818,  0.315830,   -10.657445, -2.483469,  -6.524236,   
+-7.380591,  -3.739005,  -8.388957,  0.184147,   -1.554888,  3.786508,    
+-1.684421,  5.400610,   -1.578126,  7.403361,   8.315999,   2.080267,    
+11.077776,  2.749673,   7.138962,   2.748762,   0.660363,   0.981552,    
+1.442275,   0.552721,   -2.576892,  4.703989,   0.989156,   8.759344,    
+-0.564825,  -3.994680,  0.954710,   -5.014144,  6.592329,   1.599488,    
+-13.979146, -0.391891,  -4.453369,  -2.311242,  -2.948764,  1.761415,    
+-0.138322,  10.433007,  -2.309103,  4.297153,   8.535523,   3.209462,    
+8.695819,   5.569919,   2.514304,   5.582029,   2.060199,   0.642280,    
+7.024616,   1.686615,   -6.481756,  1.343084,   -3.526451,  1.099073,    
+-2.965764,  -0.173723,  -4.111484,  6.528384,   -6.965658,  1.726291,    
+1.535172,   11.023435,  2.338401,   -4.690188,  1.298210,   3.943885,    
+8.407885,   5.168365,   0.684131,   1.559181,   1.859998,   2.852417,    
+8.574070,   -6.369078,  6.023458,   11.837963,  -6.027632,  4.469678,    
+-6.799093,  -2.674048,  6.250367,   -6.809971,  -3.459360,  9.112410,    
+-2.711621,  -1.336678,  1.564249,   -1.564297,  -1.296760,  8.904013,    
+-3.230109,  6.878013,   -7.819823,  3.369909,   -1.657410,  -2.007358,   
+-4.112825,  1.370685,   -3.420525,  -6.276605,  3.244873,   -3.352638,   
+1.545372,   0.902211,   0.197489,   -1.408732,  0.523390,   0.348440 
+}
+
Examples: 
arm_convolution_example_f32.c, arm_graphic_equalizer_example_q31.c, and arm_sin_cos_example_f32.c.

+

+
Definition at line 141 of file arm_convolution_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t srcALen = 64

+

+

+
Examples: 
arm_convolution_example_f32.c.

+

+
Definition at line 170 of file arm_convolution_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t srcBLen = 64

+

+

+
Examples: 
arm_convolution_example_f32.c.

+

+
Definition at line 171 of file arm_convolution_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t outLen

+

+

+
Examples: 
arm_convolution_example_f32.c.

+

+
Definition at line 172 of file arm_convolution_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t snr

+

+

+
Examples: 
arm_convolution_example_f32.c, arm_fir_example_f32.c, arm_graphic_equalizer_example_q31.c, and arm_matrix_example_f32.c.

+

+
Definition at line 173 of file arm_convolution_example_f32.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__convolution__example__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__convolution__example__f32_8c_source.html
new file mode 100644
index 000000000..5fc7237fe
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__convolution__example__f32_8c_source.html
@@ -0,0 +1,237 @@
+
+
+
+
+CMSIS DSP Software Library: arm_convolution_example_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__copy__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__copy__f32_8c.html
new file mode 100644
index 000000000..ba5c552e3
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__copy__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_copy_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_copy_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_copy_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__copy__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__copy__f32_8c_source.html
new file mode 100644
index 000000000..7533e382d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__copy__f32_8c_source.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_copy_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__copy__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__copy__q15_8c.html
new file mode 100644
index 000000000..229bcaeea
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__copy__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_copy_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_copy_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_copy_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__copy__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__copy__q15_8c_source.html
new file mode 100644
index 000000000..fa1ed3a98
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__copy__q15_8c_source.html
@@ -0,0 +1,183 @@
+
+
+
+
+CMSIS DSP Software Library: arm_copy_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__copy__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__copy__q31_8c.html
new file mode 100644
index 000000000..b487ad6d2
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__copy__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_copy_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_copy_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_copy_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__copy__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__copy__q31_8c_source.html
new file mode 100644
index 000000000..4ee3b5b62
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__copy__q31_8c_source.html
@@ -0,0 +1,161 @@
+
+
+
+
+CMSIS DSP Software Library: arm_copy_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__copy__q7_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__copy__q7_8c.html
new file mode 100644
index 000000000..a655ee2a4
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__copy__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_copy_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_copy_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_copy_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__copy__q7_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__copy__q7_8c_source.html
new file mode 100644
index 000000000..8c52643a2
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__copy__q7_8c_source.html
@@ -0,0 +1,159 @@
+
+
+
+
+CMSIS DSP Software Library: arm_copy_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__f32_8c.html
new file mode 100644
index 000000000..88a960ddd
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_correlate_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_correlate_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_correlate_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__f32_8c_source.html
new file mode 100644
index 000000000..557b9b0fd
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__f32_8c_source.html
@@ -0,0 +1,729 @@
+
+
+
+
+CMSIS DSP Software Library: arm_correlate_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__fast__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__fast__q15_8c.html
new file mode 100644
index 000000000..7d3f2d981
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__fast__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_correlate_fast_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_correlate_fast_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_correlate_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__fast__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__fast__q15_8c_source.html
new file mode 100644
index 000000000..345b342ec
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__fast__q15_8c_source.html
@@ -0,0 +1,658 @@
+
+
+
+
+CMSIS DSP Software Library: arm_correlate_fast_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__fast__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__fast__q31_8c.html
new file mode 100644
index 000000000..23d3b06e7
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__fast__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_correlate_fast_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_correlate_fast_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_correlate_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__fast__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__fast__q31_8c_source.html
new file mode 100644
index 000000000..39b1af449
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__fast__q31_8c_source.html
@@ -0,0 +1,631 @@
+
+
+
+
+CMSIS DSP Software Library: arm_correlate_fast_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q15_8c.html
new file mode 100644
index 000000000..4a5a8702b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_correlate_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_correlate_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_correlate_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q15_8c_source.html
new file mode 100644
index 000000000..1982577e7
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q15_8c_source.html
@@ -0,0 +1,752 @@
+
+
+
+
+CMSIS DSP Software Library: arm_correlate_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q31_8c.html
new file mode 100644
index 000000000..0f0122866
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_correlate_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_correlate_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_correlate_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q31_8c_source.html
new file mode 100644
index 000000000..d00827c14
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q31_8c_source.html
@@ -0,0 +1,718 @@
+
+
+
+
+CMSIS DSP Software Library: arm_correlate_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q7_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q7_8c.html
new file mode 100644
index 000000000..7055386cd
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_correlate_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_correlate_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_correlate_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q7_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q7_8c_source.html
new file mode 100644
index 000000000..b86b03714
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q7_8c_source.html
@@ -0,0 +1,821 @@
+
+
+
+
+CMSIS DSP Software Library: arm_correlate_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cos__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cos__f32_8c.html
new file mode 100644
index 000000000..137febfe8
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cos__f32_8c.html
@@ -0,0 +1,87 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cos_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_cos_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+

+Functions
float32_t arm_cos_f32 (float32_t x)

+Variables
static const float32_t cosTable [259]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cos__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cos__f32_8c_source.html
new file mode 100644
index 000000000..4acf4da26
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cos__f32_8c_source.html
@@ -0,0 +1,263 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cos_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cos__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cos__q15_8c.html
new file mode 100644
index 000000000..564549ddb
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cos__q15_8c.html
@@ -0,0 +1,87 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cos_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_cos_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+

+Functions
q15_t arm_cos_q15 (q15_t x)

+Variables
static const q15_t cosTableQ15 [259]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cos__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cos__q15_8c_source.html
new file mode 100644
index 000000000..21086560b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cos__q15_8c_source.html
@@ -0,0 +1,223 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cos_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cos__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cos__q31_8c.html
new file mode 100644
index 000000000..0448801c4
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cos__q31_8c.html
@@ -0,0 +1,87 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cos_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_cos_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+

+Functions
q31_t arm_cos_q31 (q31_t x)

+Variables
static const q31_t cosTableQ31 [259]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cos__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cos__q31_8c_source.html
new file mode 100644
index 000000000..28a582334
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__cos__q31_8c_source.html
@@ -0,0 +1,259 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cos_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__f32_8c.html
new file mode 100644
index 000000000..ba9322e88
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_dct4_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_dct4_f32 (const arm_dct4_instance_f32 *S, float32_t *pState, float32_t *pInlineBuffer)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__f32_8c_source.html
new file mode 100644
index 000000000..96213b0c5
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__f32_8c_source.html
@@ -0,0 +1,426 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__f32_8c.html
new file mode 100644
index 000000000..21724161b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__f32_8c.html
@@ -0,0 +1,92 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_dct4_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+

+Functions
arm_status arm_dct4_init_f32 (arm_dct4_instance_f32 *S, arm_rfft_instance_f32 *S_RFFT, arm_cfft_radix4_instance_f32 *S_CFFT, uint16_t N, uint16_t Nby2, float32_t normalize)

+Variables
static const float32_t Weights_128 [256]
static const float32_t Weights_512 [1024]
static const float32_t Weights_2048 [4096]
static const float32_t cos_factors_128 [128]
static const float32_t cos_factors_512 [512]
static const float32_t cos_factors_2048 [2048]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__f32_8c_source.html
new file mode 100644
index 000000000..480fd6114
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__f32_8c_source.html
@@ -0,0 +1,4223 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_init_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__q15_8c.html
new file mode 100644
index 000000000..325fa1d2f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__q15_8c.html
@@ -0,0 +1,92 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_dct4_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+

+Functions
arm_status arm_dct4_init_q15 (arm_dct4_instance_q15 *S, arm_rfft_instance_q15 *S_RFFT, arm_cfft_radix4_instance_q15 *S_CFFT, uint16_t N, uint16_t Nby2, q15_t normalize)

+Variables
static const q15_t WeightsQ15_128 [256]
static const q15_t WeightsQ15_512 [1024]
static const q15_t WeightsQ15_2048 [4096]
static const q15_t cos_factorsQ15_128 [128]
static const q15_t cos_factorsQ15_512 [512]
static const q15_t cos_factorsQ15_2048 [2048]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__q15_8c_source.html
new file mode 100644
index 000000000..2dd02feee
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__q15_8c_source.html
@@ -0,0 +1,1199 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_init_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__q31_8c.html
new file mode 100644
index 000000000..cdd7741b2
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__q31_8c.html
@@ -0,0 +1,92 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_dct4_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+

+Functions
arm_status arm_dct4_init_q31 (arm_dct4_instance_q31 *S, arm_rfft_instance_q31 *S_RFFT, arm_cfft_radix4_instance_q31 *S_CFFT, uint16_t N, uint16_t Nby2, q31_t normalize)

+Variables
static const q31_t WeightsQ31_128 [256]
static const q31_t WeightsQ31_512 [1024]
static const q31_t WeightsQ31_2048 [4096]
static const q31_t cos_factorsQ31_128 [128]
static const q31_t cos_factorsQ31_512 [512]
static const q31_t cos_factorsQ31_2048 [2048]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__q31_8c_source.html
new file mode 100644
index 000000000..0ee51b3ec
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__q31_8c_source.html
@@ -0,0 +1,2207 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_init_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__q15_8c.html
new file mode 100644
index 000000000..04607282f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_dct4_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_dct4_q15 (const arm_dct4_instance_q15 *S, q15_t *pState, q15_t *pInlineBuffer)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__q15_8c_source.html
new file mode 100644
index 000000000..58c55a94f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__q15_8c_source.html
@@ -0,0 +1,433 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__q31_8c.html
new file mode 100644
index 000000000..1f037ce3e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_dct4_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_dct4_q31 (const arm_dct4_instance_q31 *S, q31_t *pState, q31_t *pInlineBuffer)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__q31_8c_source.html
new file mode 100644
index 000000000..5ec02833e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dct4__q31_8c_source.html
@@ -0,0 +1,433 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__f32_8c.html
new file mode 100644
index 000000000..3089dca9f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dot_prod_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_dot_prod_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_dot_prod_f32 (float32_t *pSrcA, float32_t *pSrcB, uint32_t blockSize, float32_t *result)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__f32_8c_source.html
new file mode 100644
index 000000000..514a12ac3
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__f32_8c_source.html
@@ -0,0 +1,165 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dot_prod_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q15_8c.html
new file mode 100644
index 000000000..abf98621b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dot_prod_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_dot_prod_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_dot_prod_q15 (q15_t *pSrcA, q15_t *pSrcB, uint32_t blockSize, q63_t *result)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q15_8c_source.html
new file mode 100644
index 000000000..f1667c6e2
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q15_8c_source.html
@@ -0,0 +1,176 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dot_prod_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q31_8c.html
new file mode 100644
index 000000000..f50681beb
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dot_prod_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_dot_prod_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_dot_prod_q31 (q31_t *pSrcA, q31_t *pSrcB, uint32_t blockSize, q63_t *result)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q31_8c_source.html
new file mode 100644
index 000000000..0dcf860e8
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q31_8c_source.html
@@ -0,0 +1,167 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dot_prod_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q7_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q7_8c.html
new file mode 100644
index 000000000..c12b4bcb2
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dot_prod_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_dot_prod_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_dot_prod_q7 (q7_t *pSrcA, q7_t *pSrcB, uint32_t blockSize, q31_t *result)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q7_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q7_8c_source.html
new file mode 100644
index 000000000..8103c5eb5
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q7_8c_source.html
@@ -0,0 +1,207 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dot_prod_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dotproduct__example__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dotproduct__example__f32_8c.html
new file mode 100644
index 000000000..891dbbdef
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dotproduct__example__f32_8c.html
@@ -0,0 +1,273 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dotproduct_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Defines |
+Functions |
+Variables  

+  

+
arm_dotproduct_example_f32.c File Reference
  

+

+

+#include <math.h>

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define MAX_BLOCKSIZE   32
#define DELTA   (0.000001f)

+Functions
int32_t main (void)

+Variables
float32_t srcA_buf_f32 [MAX_BLOCKSIZE]
float32_t srcB_buf_f32 [MAX_BLOCKSIZE]
float32_t refDotProdOut = 5.9273644806352142
float32_t multOutput [MAX_BLOCKSIZE]
float32_t testOutput
arm_status status

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define MAX_BLOCKSIZE   32

+

+

+
+
Definition at line 76 of file arm_dotproduct_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define DELTA   (0.000001f)

+

+

+
+
Definition at line 77 of file arm_dotproduct_example_f32.c.

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void  )

+

+

+
+
Definition at line 130 of file arm_dotproduct_example_f32.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t srcA_buf_f32[MAX_BLOCKSIZE]

+

+

+Initial value:
   
+{   
+-0.4325648115282207,    -1.6655843782380970,    0.1253323064748307,  
+ 0.2876764203585489,    -1.1464713506814637,    1.1909154656429988,  
+ 1.1891642016521031,    -0.0376332765933176,    0.3272923614086541,  
+ 0.1746391428209245,    -0.1867085776814394,    0.7257905482933027,  
+-0.5883165430141887,     2.1831858181971011,   -0.1363958830865957,  
+ 0.1139313135208096,     1.0667682113591888,    0.0592814605236053,  
+-0.0956484054836690,    -0.8323494636500225,    0.2944108163926404,  
+-1.3361818579378040,     0.7143245518189522,    1.6235620644462707,  
+-0.6917757017022868,     0.8579966728282626,    1.2540014216025324,  
+-1.5937295764474768,    -1.4409644319010200,    0.5711476236581780,  
+-0.3998855777153632,     0.6899973754643451 
+}
+
Examples: 
arm_dotproduct_example_f32.c.

+

+
Definition at line 86 of file arm_dotproduct_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t srcB_buf_f32[MAX_BLOCKSIZE]

+

+

+Initial value:
   
+{   
+ 1.7491401329284098,    0.1325982188803279,  0.3252281811989881,     
+-0.7938091410349637,    0.3149236145048914, -0.5272704888029532,     
+ 0.9322666565031119,    1.1646643544607362, -2.0456694357357357,     
+-0.6443728590041911,    1.7410657940825480,  0.4867684246821860,     
+ 1.0488288293660140,    1.4885752747099299,  1.2705014969484090,     
+-1.8561241921210170,    2.1343209047321410,  1.4358467535865909,     
+-0.9173023332875400,   -1.1060770780029008,  0.8105708062681296,     
+ 0.6985430696369063,   -0.4015827425012831,  1.2687512030669628,     
+-0.7836083053674872,    0.2132664971465569,  0.7878984786088954,     
+ 0.8966819356782295,   -0.1869172943544062,  1.0131816724341454,     
+ 0.2484350696132857,    0.0596083377937976 
+}
+
Examples: 
arm_dotproduct_example_f32.c.

+

+
Definition at line 104 of file arm_dotproduct_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t refDotProdOut = 5.9273644806352142

+

+

+
Examples: 
arm_dotproduct_example_f32.c.

+

+
Definition at line 120 of file arm_dotproduct_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t multOutput[MAX_BLOCKSIZE]

+

+

+
Examples: 
arm_dotproduct_example_f32.c.

+

+
Definition at line 125 of file arm_dotproduct_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testOutput

+

+

+
+
Definition at line 126 of file arm_dotproduct_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_status status

+

+

+
Examples: 
arm_convolution_example_f32.c, arm_dotproduct_example_f32.c, arm_fft_bin_example_f32.c, arm_fir_example_f32.c, arm_graphic_equalizer_example_q31.c, arm_linear_interp_example_f32.c, arm_matrix_example_f32.c, arm_signal_converge_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 128 of file arm_dotproduct_example_f32.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dotproduct__example__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dotproduct__example__f32_8c_source.html
new file mode 100644
index 000000000..e7fa374c5
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__dotproduct__example__f32_8c_source.html
@@ -0,0 +1,187 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dotproduct_example_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fft__bin__example__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fft__bin__example__f32_8c.html
new file mode 100644
index 000000000..bc308320f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fft__bin__example__f32_8c.html
@@ -0,0 +1,243 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fft_bin_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Defines |
+Functions |
+Variables  

+  

+
arm_fft_bin_example_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define TEST_LENGTH_SAMPLES   2048

+Functions
int32_t main (void)

+Variables
float32_t testInput_f32_10khz [TEST_LENGTH_SAMPLES]
static float32_t testOutput [TEST_LENGTH_SAMPLES/2]
uint32_t fftSize = 1024
uint32_t ifftFlag = 0
uint32_t doBitReverse = 1
uint32_t refIndex = 213
uint32_t testIndex = 0

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define TEST_LENGTH_SAMPLES   2048

+

+

+
+
Definition at line 84 of file arm_fft_bin_example_f32.c.

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void  )

+

+

+
+
Definition at line 106 of file arm_fft_bin_example_f32.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t testInput_f32_10khz[TEST_LENGTH_SAMPLES]

+

+

+
Examples: 
arm_fft_bin_example_f32.c.

+

+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testOutput[TEST_LENGTH_SAMPLES/2] [static]

+

+

+
+
Definition at line 90 of file arm_fft_bin_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t fftSize = 1024

+

+

+
Examples: 
arm_fft_bin_example_f32.c.

+

+
Definition at line 95 of file arm_fft_bin_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t ifftFlag = 0

+

+

+
Examples: 
arm_fft_bin_example_f32.c.

+

+
Definition at line 96 of file arm_fft_bin_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t doBitReverse = 1

+

+

+
Examples: 
arm_fft_bin_example_f32.c.

+

+
Definition at line 97 of file arm_fft_bin_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t refIndex = 213

+

+

+
Examples: 
arm_fft_bin_example_f32.c.

+

+
Definition at line 100 of file arm_fft_bin_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t testIndex = 0

+

+

+
Examples: 
arm_fft_bin_example_f32.c.

+

+
Definition at line 100 of file arm_fft_bin_example_f32.c.

+
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+

+

+
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+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fft__bin__example__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fft__bin__example__f32_8c_source.html
new file mode 100644
index 000000000..5c913693c
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fft__bin__example__f32_8c_source.html
@@ -0,0 +1,163 @@
+
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+
+
+CMSIS DSP Software Library: arm_fft_bin_example_f32.c Source File
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fill__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fill__f32_8c.html
new file mode 100644
index 000000000..6f1d99a93
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fill__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fill_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fill_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fill_f32 (float32_t value, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fill__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fill__f32_8c_source.html
new file mode 100644
index 000000000..8180689d3
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fill__f32_8c_source.html
@@ -0,0 +1,161 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fill_f32.c Source File
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+
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+
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+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fill__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fill__q15_8c.html
new file mode 100644
index 000000000..ecadb61fc
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fill__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fill_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fill_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fill_q15 (q15_t value, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fill__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fill__q15_8c_source.html
new file mode 100644
index 000000000..104ed935a
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fill__q15_8c_source.html
@@ -0,0 +1,164 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fill_q15.c Source File
+
+
+
+
+
+
+
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+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fill__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fill__q31_8c.html
new file mode 100644
index 000000000..c8e95662c
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fill__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fill_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fill_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fill_q31 (q31_t value, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fill__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fill__q31_8c_source.html
new file mode 100644
index 000000000..ff91f12b3
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fill__q31_8c_source.html
@@ -0,0 +1,161 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fill_q31.c Source File
+
+
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+
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+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fill__q7_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fill__q7_8c.html
new file mode 100644
index 000000000..c46009559
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fill__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fill_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fill_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fill_q7 (q7_t value, q7_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fill__q7_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fill__q7_8c_source.html
new file mode 100644
index 000000000..3d9697df0
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fill__q7_8c_source.html
@@ -0,0 +1,162 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fill_q7.c Source File
+
+
+
+
+
+
+
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+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__f32_8c.html
new file mode 100644
index 000000000..2191d977f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_decimate_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_decimate_f32 (const arm_fir_decimate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__f32_8c_source.html
new file mode 100644
index 000000000..08e606564
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__f32_8c_source.html
@@ -0,0 +1,344 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__fast__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__fast__q15_8c.html
new file mode 100644
index 000000000..e138f1877
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__fast__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_fast_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_decimate_fast_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_decimate_fast_q15 (const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__fast__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__fast__q15_8c_source.html
new file mode 100644
index 000000000..bd5019168
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__fast__q15_8c_source.html
@@ -0,0 +1,238 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_fast_q15.c Source File
+
+
+
+
+
+
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+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__fast__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__fast__q31_8c.html
new file mode 100644
index 000000000..04834a183
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__fast__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_fast_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_decimate_fast_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_decimate_fast_q31 (arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__fast__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__fast__q31_8c_source.html
new file mode 100644
index 000000000..6b965a2eb
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__fast__q31_8c_source.html
@@ -0,0 +1,257 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_fast_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__f32_8c.html
new file mode 100644
index 000000000..648ce3bed
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_decimate_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_fir_decimate_init_f32 (arm_fir_decimate_instance_f32 *S, uint16_t numTaps, uint8_t M, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__f32_8c_source.html
new file mode 100644
index 000000000..d3f76dae6
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__f32_8c_source.html
@@ -0,0 +1,147 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_init_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__q15_8c.html
new file mode 100644
index 000000000..c00d58e65
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_decimate_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_fir_decimate_init_q15 (arm_fir_decimate_instance_q15 *S, uint16_t numTaps, uint8_t M, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__q15_8c_source.html
new file mode 100644
index 000000000..efe874022
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__q15_8c_source.html
@@ -0,0 +1,148 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_init_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__q31_8c.html
new file mode 100644
index 000000000..7aa5afe07
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_decimate_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_fir_decimate_init_q31 (arm_fir_decimate_instance_q31 *S, uint16_t numTaps, uint8_t M, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__q31_8c_source.html
new file mode 100644
index 000000000..2df1f14fe
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__q31_8c_source.html
@@ -0,0 +1,147 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_init_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__q15_8c.html
new file mode 100644
index 000000000..cd67a34ad
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_decimate_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_decimate_q15 (const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__q15_8c_source.html
new file mode 100644
index 000000000..00aeb5067
--- /dev/null
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@@ -0,0 +1,325 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__q31_8c.html
new file mode 100644
index 000000000..6ecbaaa86
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_decimate_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_decimate_q31 (const arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__q31_8c_source.html
new file mode 100644
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--- /dev/null
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@@ -0,0 +1,344 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_q31.c Source File
+
+
+
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+
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+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__example__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__example__f32_8c.html
new file mode 100644
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--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__example__f32_8c.html
@@ -0,0 +1,314 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Defines |
+Functions |
+Variables  

+  

+
arm_fir_example_f32.c File Reference
  

+

+

+#include "arm_math.h"

+#include "math_helper.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define TEST_LENGTH_SAMPLES   320
#define SNR_THRESHOLD_F32   140.0f
#define BLOCK_SIZE   32
#define NUM_TAPS   29

+Functions
int32_t main (void)

+Variables
float32_t testInput_f32_1kHz_15kHz [TEST_LENGTH_SAMPLES]
float32_t refOutput [TEST_LENGTH_SAMPLES]
static float32_t testOutput [TEST_LENGTH_SAMPLES]
static float32_t firStateF32 [BLOCK_SIZE+NUM_TAPS-1]
const float32_t firCoeffs32 [NUM_TAPS]
uint32_t blockSize = BLOCK_SIZE
uint32_t numBlocks = TEST_LENGTH_SAMPLES/BLOCK_SIZE
float32_t snr

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define TEST_LENGTH_SAMPLES   320

+

+

+
+
Definition at line 116 of file arm_fir_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define SNR_THRESHOLD_F32   140.0f

+

+

+
Examples: 
arm_fir_example_f32.c, and arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 117 of file arm_fir_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define BLOCK_SIZE   32

+

+

+
Examples: 
arm_fir_example_f32.c.

+

+
Definition at line 118 of file arm_fir_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define NUM_TAPS   29

+

+

+
Examples: 
arm_fir_example_f32.c.

+

+
Definition at line 119 of file arm_fir_example_f32.c.

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void  )

+

+

+
+
Definition at line 166 of file arm_fir_example_f32.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t testInput_f32_1kHz_15kHz[TEST_LENGTH_SAMPLES]

+

+

+
Examples: 
arm_fir_example_f32.c.

+

+

+

+
+

+

+      
+        
+          
+        
+      
float32_t refOutput[TEST_LENGTH_SAMPLES]

+

+

+
Examples: 
arm_fir_example_f32.c.

+

+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testOutput[TEST_LENGTH_SAMPLES] [static]

+

+

+
+
Definition at line 133 of file arm_fir_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t firStateF32[BLOCK_SIZE+NUM_TAPS-1] [static]

+

+

+
+
Definition at line 139 of file arm_fir_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t firCoeffs32[NUM_TAPS]

+

+

+Initial value:
 { 
+-0.0018225230f, -0.0015879294f, +0.0000000000f, +0.0036977508f, +0.0080754303f, +0.0085302217f, -0.0000000000f, -0.0173976984f, 
+-0.0341458607f, -0.0333591565f, +0.0000000000f, +0.0676308395f, +0.1522061835f, +0.2229246956f, +0.2504960933f, +0.2229246956f, 
++0.1522061835f, +0.0676308395f, +0.0000000000f, -0.0333591565f, -0.0341458607f, -0.0173976984f, -0.0000000000f, +0.0085302217f, 
++0.0080754303f, +0.0036977508f, +0.0000000000f, -0.0015879294f, -0.0018225230f 
+}
+
Examples: 
arm_fir_example_f32.c.

+

+
Definition at line 146 of file arm_fir_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t blockSize = BLOCK_SIZE

+

+

+
Examples: 
arm_fir_example_f32.c, arm_signal_converge_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 157 of file arm_fir_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t numBlocks = TEST_LENGTH_SAMPLES/BLOCK_SIZE

+

+

+
Examples: 
arm_fir_example_f32.c.

+

+
Definition at line 158 of file arm_fir_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t snr

+

+

+
+
Definition at line 160 of file arm_fir_example_f32.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__example__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__example__f32_8c_source.html
new file mode 100644
index 000000000..fe4d3aacf
--- /dev/null
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@@ -0,0 +1,208 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_example_f32.c Source File
+
+
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+
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+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__f32_8c.html
new file mode 100644
index 000000000..a3da1e9a0
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_f32 (const arm_fir_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__f32_8c_source.html
new file mode 100644
index 000000000..e817d7c53
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__f32_8c_source.html
@@ -0,0 +1,416 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_f32.c Source File
+
+
+
+
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+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__fast__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__fast__q15_8c.html
new file mode 100644
index 000000000..8ba6f405d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__fast__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_fast_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_fast_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_fast_q15 (const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__fast__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__fast__q15_8c_source.html
new file mode 100644
index 000000000..93947ef70
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__fast__q15_8c_source.html
@@ -0,0 +1,320 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_fast_q15.c Source File
+
+
+
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+
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+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__fast__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__fast__q31_8c.html
new file mode 100644
index 000000000..60079ce25
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__fast__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_fast_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_fast_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_fast_q31 (const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__fast__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__fast__q31_8c_source.html
new file mode 100644
index 000000000..cb4ececa9
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__fast__q31_8c_source.html
@@ -0,0 +1,342 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_fast_q31.c Source File
+
+
+
+
+
+
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+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__f32_8c.html
new file mode 100644
index 000000000..ea1fb6171
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_init_f32 (arm_fir_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__f32_8c_source.html
new file mode 100644
index 000000000..923683c0e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__f32_8c_source.html
@@ -0,0 +1,131 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_init_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q15_8c.html
new file mode 100644
index 000000000..e072bfeb2
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_fir_init_q15 (arm_fir_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q15_8c_source.html
new file mode 100644
index 000000000..1eed9131f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q15_8c_source.html
@@ -0,0 +1,172 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_init_q15.c Source File
+
+
+
+
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+
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+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q31_8c.html
new file mode 100644
index 000000000..cbd399b7f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_init_q31 (arm_fir_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q31_8c_source.html
new file mode 100644
index 000000000..8f9f0258e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q31_8c_source.html
@@ -0,0 +1,131 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_init_q31.c Source File
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q7_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q7_8c.html
new file mode 100644
index 000000000..1f1549f77
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_init_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_init_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_init_q7 (arm_fir_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q7_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q7_8c_source.html
new file mode 100644
index 000000000..f9735f00e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q7_8c_source.html
@@ -0,0 +1,132 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_init_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__f32_8c.html
new file mode 100644
index 000000000..b572895df
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_interpolate_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_interpolate_f32 (const arm_fir_interpolate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__f32_8c_source.html
new file mode 100644
index 000000000..562656f64
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__f32_8c_source.html
@@ -0,0 +1,369 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__f32_8c.html
new file mode 100644
index 000000000..e728cda15
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_interpolate_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_fir_interpolate_init_f32 (arm_fir_interpolate_instance_f32 *S, uint8_t L, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__f32_8c_source.html
new file mode 100644
index 000000000..da0b1022a
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__f32_8c_source.html
@@ -0,0 +1,150 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_init_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__q15_8c.html
new file mode 100644
index 000000000..8770df289
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_interpolate_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_fir_interpolate_init_q15 (arm_fir_interpolate_instance_q15 *S, uint8_t L, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__q15_8c_source.html
new file mode 100644
index 000000000..9c48e936e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__q15_8c_source.html
@@ -0,0 +1,149 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_init_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__q31_8c.html
new file mode 100644
index 000000000..9a0a55f02
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_interpolate_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_fir_interpolate_init_q31 (arm_fir_interpolate_instance_q31 *S, uint8_t L, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__q31_8c_source.html
new file mode 100644
index 000000000..7d7407d1a
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__q31_8c_source.html
@@ -0,0 +1,149 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_init_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__q15_8c.html
new file mode 100644
index 000000000..48d14c673
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_interpolate_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_interpolate_q15 (const arm_fir_interpolate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__q15_8c_source.html
new file mode 100644
index 000000000..526d1aa0e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__q15_8c_source.html
@@ -0,0 +1,392 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__q31_8c.html
new file mode 100644
index 000000000..40bd2e7c4
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_interpolate_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_interpolate_q31 (const arm_fir_interpolate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__q31_8c_source.html
new file mode 100644
index 000000000..2649b86f8
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__q31_8c_source.html
@@ -0,0 +1,382 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__f32_8c.html
new file mode 100644
index 000000000..23fbdc79e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_lattice_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_lattice_f32 (const arm_fir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__f32_8c_source.html
new file mode 100644
index 000000000..d49d77141
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__f32_8c_source.html
@@ -0,0 +1,480 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__f32_8c.html
new file mode 100644
index 000000000..630fb1011
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_lattice_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_lattice_init_f32 (arm_fir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pCoeffs, float32_t *pState)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__f32_8c_source.html
new file mode 100644
index 000000000..efc2413ab
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__f32_8c_source.html
@@ -0,0 +1,127 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_init_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__q15_8c.html
new file mode 100644
index 000000000..3819d4584
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_lattice_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_lattice_init_q15 (arm_fir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pCoeffs, q15_t *pState)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__q15_8c_source.html
new file mode 100644
index 000000000..807445000
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__q15_8c_source.html
@@ -0,0 +1,127 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_init_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__q31_8c.html
new file mode 100644
index 000000000..3caba1a99
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_lattice_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_lattice_init_q31 (arm_fir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pCoeffs, q31_t *pState)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__q31_8c_source.html
new file mode 100644
index 000000000..2406c9436
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__q31_8c_source.html
@@ -0,0 +1,127 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_init_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__q15_8c.html
new file mode 100644
index 000000000..ba6230ffd
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_lattice_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_lattice_q15 (const arm_fir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__q15_8c_source.html
new file mode 100644
index 000000000..3f58e8c78
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__q15_8c_source.html
@@ -0,0 +1,579 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__q31_8c.html
new file mode 100644
index 000000000..cd8ecfbdb
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_lattice_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_lattice_q31 (const arm_fir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__q31_8c_source.html
new file mode 100644
index 000000000..c67c9f8e7
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__q31_8c_source.html
@@ -0,0 +1,487 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__q15_8c.html
new file mode 100644
index 000000000..584d68923
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_q15 (const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__q15_8c_source.html
new file mode 100644
index 000000000..a72742ce4
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__q15_8c_source.html
@@ -0,0 +1,408 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__q31_8c.html
new file mode 100644
index 000000000..3cdf06aa5
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_q31 (const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__q31_8c_source.html
new file mode 100644
index 000000000..180d2cdaa
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__q31_8c_source.html
@@ -0,0 +1,424 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__q7_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__q7_8c.html
new file mode 100644
index 000000000..3eb3d09d8
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_q7 (const arm_fir_instance_q7 *S, q7_t *pSrc, q7_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__q7_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__q7_8c_source.html
new file mode 100644
index 000000000..a53eeb3f5
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__q7_8c_source.html
@@ -0,0 +1,429 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__f32_8c.html
new file mode 100644
index 000000000..15470fc35
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_sparse_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_sparse_f32 (arm_fir_sparse_instance_f32 *S, float32_t *pSrc, float32_t *pDst, float32_t *pScratchIn, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__f32_8c_source.html
new file mode 100644
index 000000000..d718ec19e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__f32_8c_source.html
@@ -0,0 +1,353 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__f32_8c.html
new file mode 100644
index 000000000..d51dbc8f2
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_sparse_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_sparse_init_f32 (arm_fir_sparse_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__f32_8c_source.html
new file mode 100644
index 000000000..71362e37c
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__f32_8c_source.html
@@ -0,0 +1,139 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_init_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q15_8c.html
new file mode 100644
index 000000000..037f0f558
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_sparse_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_sparse_init_q15 (arm_fir_sparse_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q15_8c_source.html
new file mode 100644
index 000000000..fc1d6873e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q15_8c_source.html
@@ -0,0 +1,139 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_init_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q31_8c.html
new file mode 100644
index 000000000..21f6344e7
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_sparse_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_sparse_init_q31 (arm_fir_sparse_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q31_8c_source.html
new file mode 100644
index 000000000..b943d7f2f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q31_8c_source.html
@@ -0,0 +1,139 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_init_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q7_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q7_8c.html
new file mode 100644
index 000000000..58985ec53
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_init_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_sparse_init_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_sparse_init_q7 (arm_fir_sparse_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q7_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q7_8c_source.html
new file mode 100644
index 000000000..4a75391d6
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q7_8c_source.html
@@ -0,0 +1,139 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_init_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q15_8c.html
new file mode 100644
index 000000000..0105940ce
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_sparse_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_sparse_q15 (arm_fir_sparse_instance_q15 *S, q15_t *pSrc, q15_t *pDst, q15_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q15_8c_source.html
new file mode 100644
index 000000000..88a9a3c59
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q15_8c_source.html
@@ -0,0 +1,447 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q31_8c.html
new file mode 100644
index 000000000..a804e8407
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_sparse_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_sparse_q31 (arm_fir_sparse_instance_q31 *S, q31_t *pSrc, q31_t *pDst, q31_t *pScratchIn, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q31_8c_source.html
new file mode 100644
index 000000000..73c759049
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q31_8c_source.html
@@ -0,0 +1,414 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q7_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q7_8c.html
new file mode 100644
index 000000000..e972a6985
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_sparse_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_sparse_q7 (arm_fir_sparse_instance_q7 *S, q7_t *pSrc, q7_t *pDst, q7_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q7_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q7_8c_source.html
new file mode 100644
index 000000000..1ea85908c
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q7_8c_source.html
@@ -0,0 +1,435 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q15_8c.html
new file mode 100644
index 000000000..e111bf66e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_float_to_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_float_to_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_float_to_q15 (float32_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q15_8c_source.html
new file mode 100644
index 000000000..33fe5504b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q15_8c_source.html
@@ -0,0 +1,230 @@
+
+
+
+
+CMSIS DSP Software Library: arm_float_to_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q31_8c.html
new file mode 100644
index 000000000..3f66fd8cc
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_float_to_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_float_to_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_float_to_q31 (float32_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q31_8c_source.html
new file mode 100644
index 000000000..5fb55c3de
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q31_8c_source.html
@@ -0,0 +1,233 @@
+
+
+
+
+CMSIS DSP Software Library: arm_float_to_q31.c Source File
+
+
+
+
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+
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+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q7_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q7_8c.html
new file mode 100644
index 000000000..7ef7c9886
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_float_to_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_float_to_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_float_to_q7 (float32_t *pSrc, q7_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q7_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q7_8c_source.html
new file mode 100644
index 000000000..844731d5f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q7_8c_source.html
@@ -0,0 +1,230 @@
+
+
+
+
+CMSIS DSP Software Library: arm_float_to_q7.c Source File
+
+
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+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__graphic__equalizer__example__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__graphic__equalizer__example__q31_8c.html
new file mode 100644
index 000000000..7fb393a1d
--- /dev/null
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+
+
+
+
+CMSIS DSP Software Library: arm_graphic_equalizer_example_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Defines |
+Functions |
+Variables  

+  

+
arm_graphic_equalizer_example_q31.c File Reference
  

+

+

+#include "arm_math.h"

+#include "math_helper.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+

+Defines
#define TESTLENGTH   320
#define BLOCKSIZE   32
#define NUMBLOCKS   (TESTLENGTH/BLOCKSIZE)
#define NUMSTAGES   2
#define SNR_THRESHOLD_F32   98

+Functions
int32_t main (void)

+Variables
float32_t testInput_f32 [TESTLENGTH]
static float32_t testOutput [TESTLENGTH]
float32_t testRefOutput_f32 [TESTLENGTH]
static q63_t biquadStateBand1Q31 [4 *2]
static q63_t biquadStateBand2Q31 [4 *2]
static q31_t biquadStateBand3Q31 [4 *2]
static q31_t biquadStateBand4Q31 [4 *2]
static q31_t biquadStateBand5Q31 [4 *2]
q31_t inputQ31 [BLOCKSIZE]
q31_t outputQ31 [BLOCKSIZE]
const q31_t coeffTable [950]
int gainDB [5] = {0, -3, 6, 4, -6}
float32_t snr

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define TESTLENGTH   320

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 117 of file arm_graphic_equalizer_example_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define BLOCKSIZE   32

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c, and arm_signal_converge_example_f32.c.

+

+
Definition at line 120 of file arm_graphic_equalizer_example_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define NUMBLOCKS   (TESTLENGTH/BLOCKSIZE)

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 123 of file arm_graphic_equalizer_example_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define NUMSTAGES   2

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 126 of file arm_graphic_equalizer_example_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define SNR_THRESHOLD_F32   98

+

+

+
+
Definition at line 128 of file arm_graphic_equalizer_example_q31.c.

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void  )

+

+

+
+
Definition at line 285 of file arm_graphic_equalizer_example_q31.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t testInput_f32[TESTLENGTH]

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c, arm_signal_converge_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 83 of file arm_sin_cos_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testOutput[TESTLENGTH] [static]

+

+

+
+
Definition at line 135 of file arm_graphic_equalizer_example_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testRefOutput_f32[TESTLENGTH]

+

+

+
+
Definition at line 141 of file arm_convolution_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q63_t biquadStateBand1Q31[4 *2] [static]

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 143 of file arm_graphic_equalizer_example_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q63_t biquadStateBand2Q31[4 *2] [static]

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 144 of file arm_graphic_equalizer_example_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t biquadStateBand3Q31[4 *2] [static]

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 145 of file arm_graphic_equalizer_example_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t biquadStateBand4Q31[4 *2] [static]

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 146 of file arm_graphic_equalizer_example_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t biquadStateBand5Q31[4 *2] [static]

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 147 of file arm_graphic_equalizer_example_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t inputQ31[BLOCKSIZE]

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 153 of file arm_graphic_equalizer_example_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t outputQ31[BLOCKSIZE]

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 154 of file arm_graphic_equalizer_example_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t coeffTable[950]

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 167 of file arm_graphic_equalizer_example_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
int gainDB[5] = {0, -3, 6, 4, -6}

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 276 of file arm_graphic_equalizer_example_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t snr

+

+

+
+
Definition at line 278 of file arm_graphic_equalizer_example_q31.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__graphic__equalizer__example__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__graphic__equalizer__example__q31_8c_source.html
new file mode 100644
index 000000000..c131db8d9
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__graphic__equalizer__example__q31_8c_source.html
@@ -0,0 +1,377 @@
+
+
+
+
+CMSIS DSP Software Library: arm_graphic_equalizer_example_q31.c Source File
+
+
+
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+
+
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+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__f32_8c.html
new file mode 100644
index 000000000..53bf9ebf2
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_iir_lattice_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_iir_lattice_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_iir_lattice_f32 (const arm_iir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__f32_8c_source.html
new file mode 100644
index 000000000..829588e47
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__f32_8c_source.html
@@ -0,0 +1,387 @@
+
+
+
+
+CMSIS DSP Software Library: arm_iir_lattice_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__f32_8c.html
new file mode 100644
index 000000000..0e1ff1094
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_iir_lattice_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_iir_lattice_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_iir_lattice_init_f32 (arm_iir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pkCoeffs, float32_t *pvCoeffs, float32_t *pState, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__f32_8c_source.html
new file mode 100644
index 000000000..606ef4f0d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__f32_8c_source.html
@@ -0,0 +1,133 @@
+
+
+
+
+CMSIS DSP Software Library: arm_iir_lattice_init_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__q15_8c.html
new file mode 100644
index 000000000..29f5ab521
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_iir_lattice_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_iir_lattice_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_iir_lattice_init_q15 (arm_iir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pkCoeffs, q15_t *pvCoeffs, q15_t *pState, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__q15_8c_source.html
new file mode 100644
index 000000000..1fcbc32ef
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__q15_8c_source.html
@@ -0,0 +1,133 @@
+
+
+
+
+CMSIS DSP Software Library: arm_iir_lattice_init_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__q31_8c.html
new file mode 100644
index 000000000..659c893c9
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_iir_lattice_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_iir_lattice_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_iir_lattice_init_q31 (arm_iir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pkCoeffs, q31_t *pvCoeffs, q31_t *pState, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__q31_8c_source.html
new file mode 100644
index 000000000..88562443f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__q31_8c_source.html
@@ -0,0 +1,133 @@
+
+
+
+
+CMSIS DSP Software Library: arm_iir_lattice_init_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__q15_8c.html
new file mode 100644
index 000000000..8c1d940ff
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_iir_lattice_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_iir_lattice_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_iir_lattice_q15 (const arm_iir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__q15_8c_source.html
new file mode 100644
index 000000000..a3c70e0fb
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__q15_8c_source.html
@@ -0,0 +1,445 @@
+
+
+
+
+CMSIS DSP Software Library: arm_iir_lattice_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__q31_8c.html
new file mode 100644
index 000000000..2fc40f912
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_iir_lattice_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_iir_lattice_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_iir_lattice_q31 (const arm_iir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__q31_8c_source.html
new file mode 100644
index 000000000..11fcf393d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__q31_8c_source.html
@@ -0,0 +1,385 @@
+
+
+
+
+CMSIS DSP Software Library: arm_iir_lattice_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__linear__interp__example__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__linear__interp__example__f32_8c.html
new file mode 100644
index 000000000..ce0395860
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__linear__interp__example__f32_8c.html
@@ -0,0 +1,287 @@
+
+
+
+
+CMSIS DSP Software Library: arm_linear_interp_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Defines |
+Functions |
+Variables  

+  

+
arm_linear_interp_example_f32.c File Reference
  

+

+

+#include "arm_math.h"

+#include "math_helper.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define SNR_THRESHOLD   90
#define TEST_LENGTH_SAMPLES   10
#define XSPACING   (0.00005f)

+Functions
int32_t main (void)

+Variables
float32_t testInputSin_f32 [TEST_LENGTH_SAMPLES]
float32_t testRefSinOutput32_f32 [TEST_LENGTH_SAMPLES]
float32_t testOutput [TEST_LENGTH_SAMPLES]
float32_t testLinIntOutput [TEST_LENGTH_SAMPLES]
float32_t arm_linear_interep_table [188495]
float32_t snr1
float32_t snr2

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define SNR_THRESHOLD   90

+

+

+
+
Definition at line 73 of file arm_linear_interp_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define TEST_LENGTH_SAMPLES   10

+

+

+
+
Definition at line 74 of file arm_linear_interp_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define XSPACING   (0.00005f)

+

+

+
Examples: 
arm_linear_interp_example_f32.c.

+

+
Definition at line 75 of file arm_linear_interp_example_f32.c.

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void  )

+

+

+
+
Definition at line 123 of file arm_linear_interp_example_f32.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t testInputSin_f32[TEST_LENGTH_SAMPLES]

+

+

+Initial value:
  
+{
+    -0.649716504673081170,  -2.501723745497831200,  0.188250329003310100,   0.432092748487532540,   -1.722010988459680800,  1.788766476323060600,   1.786136060975809500,   -0.056525543169408797,  
+    0.491596272728153760,   0.262309671126153390   
+}
+
Examples: 
arm_linear_interp_example_f32.c.

+

+
Definition at line 83 of file arm_linear_interp_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testRefSinOutput32_f32[TEST_LENGTH_SAMPLES]

+

+

+Initial value:
   
+{
+    -0.604960695383043530,  -0.597090287967934840,  0.187140422442966500,   0.418772124875992690,   -0.988588831792106880,  0.976338412038794010,   0.976903856413481100,   -0.056495446835214236,  
+    0.472033731854734240,   0.259311907228582830
+}
+
Examples: 
arm_linear_interp_example_f32.c.

+

+
Definition at line 93 of file arm_linear_interp_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testOutput[TEST_LENGTH_SAMPLES]

+

+

+
+
Definition at line 102 of file arm_linear_interp_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testLinIntOutput[TEST_LENGTH_SAMPLES]

+

+

+
Examples: 
arm_linear_interp_example_f32.c.

+

+
Definition at line 107 of file arm_linear_interp_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_linear_interep_table[188495]

+

+

+
Examples: 
arm_linear_interp_example_f32.c.

+

+

+

+
+

+

+      
+        
+          
+        
+      
float32_t snr1

+

+

+
Examples: 
arm_linear_interp_example_f32.c.

+

+
Definition at line 117 of file arm_linear_interp_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t snr2

+

+

+
Examples: 
arm_linear_interp_example_f32.c.

+

+
Definition at line 118 of file arm_linear_interp_example_f32.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__linear__interp__example__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__linear__interp__example__f32_8c_source.html
new file mode 100644
index 000000000..3fe9dee55
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__linear__interp__example__f32_8c_source.html
@@ -0,0 +1,207 @@
+
+
+
+
+CMSIS DSP Software Library: arm_linear_interp_example_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__f32_8c.html
new file mode 100644
index 000000000..f76d8032d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_lms_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_lms_f32 (const arm_lms_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__f32_8c_source.html
new file mode 100644
index 000000000..1787962b6
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__f32_8c_source.html
@@ -0,0 +1,366 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__f32_8c.html
new file mode 100644
index 000000000..95d892874
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_lms_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_lms_init_f32 (arm_lms_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__f32_8c_source.html
new file mode 100644
index 000000000..7be3e8b57
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__f32_8c_source.html
@@ -0,0 +1,131 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_init_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__q15_8c.html
new file mode 100644
index 000000000..6b2b59386
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_lms_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_lms_init_q15 (arm_lms_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint32_t postShift)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__q15_8c_source.html
new file mode 100644
index 000000000..d7485e933
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__q15_8c_source.html
@@ -0,0 +1,136 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_init_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__q31_8c.html
new file mode 100644
index 000000000..65e5481b2
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_lms_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_lms_init_q31 (arm_lms_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint32_t postShift)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__q31_8c_source.html
new file mode 100644
index 000000000..3f31d6739
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__q31_8c_source.html
@@ -0,0 +1,136 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_init_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__f32_8c.html
new file mode 100644
index 000000000..09bae676d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_lms_norm_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_lms_norm_f32 (arm_lms_norm_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__f32_8c_source.html
new file mode 100644
index 000000000..1b609babd
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__f32_8c_source.html
@@ -0,0 +1,398 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__f32_8c.html
new file mode 100644
index 000000000..34ace1466
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_lms_norm_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_lms_norm_init_f32 (arm_lms_norm_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__f32_8c_source.html
new file mode 100644
index 000000000..813bda8fa
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__f32_8c_source.html
@@ -0,0 +1,138 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_init_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__q15_8c.html
new file mode 100644
index 000000000..37afc9259
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__q15_8c.html
@@ -0,0 +1,84 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_lms_norm_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+#include "arm_common_tables.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_lms_norm_init_q15 (arm_lms_norm_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint8_t postShift)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__q15_8c_source.html
new file mode 100644
index 000000000..f98cc7f5d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__q15_8c_source.html
@@ -0,0 +1,146 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_init_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__q31_8c.html
new file mode 100644
index 000000000..5f523b912
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__q31_8c.html
@@ -0,0 +1,84 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_lms_norm_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+#include "arm_common_tables.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_lms_norm_init_q31 (arm_lms_norm_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint8_t postShift)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__q31_8c_source.html
new file mode 100644
index 000000000..b257f2227
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__q31_8c_source.html
@@ -0,0 +1,146 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_init_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__q15_8c.html
new file mode 100644
index 000000000..12852f9a7
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_lms_norm_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_lms_norm_q15 (arm_lms_norm_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__q15_8c_source.html
new file mode 100644
index 000000000..efe324a32
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__q15_8c_source.html
@@ -0,0 +1,420 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__q31_8c.html
new file mode 100644
index 000000000..dc1d25b97
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_lms_norm_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_lms_norm_q31 (arm_lms_norm_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__q31_8c_source.html
new file mode 100644
index 000000000..e857f90ff
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__q31_8c_source.html
@@ -0,0 +1,437 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__q15_8c.html
new file mode 100644
index 000000000..a867659cc
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_lms_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_lms_q15 (const arm_lms_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__q15_8c_source.html
new file mode 100644
index 000000000..4270b3ebf
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__q15_8c_source.html
@@ -0,0 +1,369 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__q31_8c.html
new file mode 100644
index 000000000..9239af4b8
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_lms_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_lms_q31 (const arm_lms_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__q31_8c_source.html
new file mode 100644
index 000000000..7fe78dfe5
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__lms__q31_8c_source.html
@@ -0,0 +1,382 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__f32_8c.html
new file mode 100644
index 000000000..2b2851816
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_add_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_add_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_add_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__f32_8c_source.html
new file mode 100644
index 000000000..75cb27398
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__f32_8c_source.html
@@ -0,0 +1,194 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_add_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__q15_8c.html
new file mode 100644
index 000000000..4d694ff72
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_add_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_add_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_add_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__q15_8c_source.html
new file mode 100644
index 000000000..7c7e5d204
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__q15_8c_source.html
@@ -0,0 +1,205 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_add_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__q31_8c.html
new file mode 100644
index 000000000..14c8e851d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_add_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_add_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_add_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__q31_8c_source.html
new file mode 100644
index 000000000..6b603d142
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__q31_8c_source.html
@@ -0,0 +1,204 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_add_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__f32_8c.html
new file mode 100644
index 000000000..90f259051
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_mat_init_f32 (arm_matrix_instance_f32 *S, uint16_t nRows, uint16_t nColumns, float32_t *pData)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__f32_8c_source.html
new file mode 100644
index 000000000..55986e419
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__f32_8c_source.html
@@ -0,0 +1,126 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_init_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__q15_8c.html
new file mode 100644
index 000000000..c0736772f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_mat_init_q15 (arm_matrix_instance_q15 *S, uint16_t nRows, uint16_t nColumns, q15_t *pData)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__q15_8c_source.html
new file mode 100644
index 000000000..c2f5ec3e5
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__q15_8c_source.html
@@ -0,0 +1,127 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_init_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__q31_8c.html
new file mode 100644
index 000000000..a822f8517
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_mat_init_q31 (arm_matrix_instance_q31 *S, uint16_t nRows, uint16_t nColumns, q31_t *pData)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__q31_8c_source.html
new file mode 100644
index 000000000..78c8a2c2d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__q31_8c_source.html
@@ -0,0 +1,126 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_init_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__inverse__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__inverse__f32_8c.html
new file mode 100644
index 000000000..8e211dcc4
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__inverse__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_inverse_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_inverse_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_inverse_f32 (const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__inverse__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__inverse__f32_8c_source.html
new file mode 100644
index 000000000..46a5d7e24
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__inverse__f32_8c_source.html
@@ -0,0 +1,693 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_inverse_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__f32_8c.html
new file mode 100644
index 000000000..55e68df18
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_mult_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_mult_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_mult_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__f32_8c_source.html
new file mode 100644
index 000000000..3fc42a58d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__f32_8c_source.html
@@ -0,0 +1,305 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_mult_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__fast__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__fast__q15_8c.html
new file mode 100644
index 000000000..9bbd1d2cf
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__fast__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_mult_fast_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_mult_fast_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_mult_fast_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__fast__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__fast__q15_8c_source.html
new file mode 100644
index 000000000..3d98de76c
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__fast__q15_8c_source.html
@@ -0,0 +1,312 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_mult_fast_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__fast__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__fast__q31_8c.html
new file mode 100644
index 000000000..841d4c5d0
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__fast__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_mult_fast_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_mult_fast_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_mult_fast_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__fast__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__fast__q31_8c_source.html
new file mode 100644
index 000000000..35c2be447
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__fast__q31_8c_source.html
@@ -0,0 +1,232 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_mult_fast_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__q15_8c.html
new file mode 100644
index 000000000..a7c43c145
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_mult_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_mult_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_mult_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__q15_8c_source.html
new file mode 100644
index 000000000..908c17a83
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__q15_8c_source.html
@@ -0,0 +1,412 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_mult_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__q31_8c.html
new file mode 100644
index 000000000..340601ccf
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_mult_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_mult_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_mult_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__q31_8c_source.html
new file mode 100644
index 000000000..364177e40
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__q31_8c_source.html
@@ -0,0 +1,313 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_mult_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__f32_8c.html
new file mode 100644
index 000000000..af76a9409
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_scale_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_scale_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_scale_f32 (const arm_matrix_instance_f32 *pSrc, float32_t scale, arm_matrix_instance_f32 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__f32_8c_source.html
new file mode 100644
index 000000000..83d5a64c2
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__f32_8c_source.html
@@ -0,0 +1,189 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_scale_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__q15_8c.html
new file mode 100644
index 000000000..f0165bc2f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_scale_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_scale_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_scale_q15 (const arm_matrix_instance_q15 *pSrc, q15_t scaleFract, int32_t shift, arm_matrix_instance_q15 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__q15_8c_source.html
new file mode 100644
index 000000000..da0e424ba
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__q15_8c_source.html
@@ -0,0 +1,195 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_scale_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__q31_8c.html
new file mode 100644
index 000000000..fa9a500cc
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_scale_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_scale_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_scale_q31 (const arm_matrix_instance_q31 *pSrc, q31_t scaleFract, int32_t shift, arm_matrix_instance_q31 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__q31_8c_source.html
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+CMSIS DSP Software Library: arm_mat_scale_q31.c Source File
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+

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+
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+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__f32_8c.html
new file mode 100644
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+
+
+
+
+CMSIS DSP Software Library: arm_mat_sub_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_sub_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_sub_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)

+

+
+
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+

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+

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+
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+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__f32_8c_source.html
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+CMSIS DSP Software Library: arm_mat_sub_f32.c Source File
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+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__q15_8c.html
new file mode 100644
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--- /dev/null
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+
+
+CMSIS DSP Software Library: arm_mat_sub_q15.c File Reference
+
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+
+
+
+

+  

+Functions  

+  

+
arm_mat_sub_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_sub_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__q15_8c_source.html
new file mode 100644
index 000000000..21ef30fb2
--- /dev/null
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+CMSIS DSP Software Library: arm_mat_sub_q15.c Source File
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+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__q31_8c.html
new file mode 100644
index 000000000..c9aee4faf
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__q31_8c.html
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+
+
+
+
+CMSIS DSP Software Library: arm_mat_sub_q31.c File Reference
+
+
+
+
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+
+
+
+

+  

+Functions  

+  

+
arm_mat_sub_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_sub_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__q31_8c_source.html
new file mode 100644
index 000000000..2511fb20c
--- /dev/null
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+CMSIS DSP Software Library: arm_mat_sub_q31.c Source File
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Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__f32_8c.html
new file mode 100644
index 000000000..97bda00cf
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__f32_8c.html
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+
+
+
+
+CMSIS DSP Software Library: arm_mat_trans_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_trans_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_trans_f32 (const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__f32_8c_source.html
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+CMSIS DSP Software Library: arm_mat_trans_f32.c Source File
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Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__q15_8c.html
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+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__q15_8c.html
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+
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+
+CMSIS DSP Software Library: arm_mat_trans_q15.c File Reference
+
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+
+
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+
+
+
+

+  

+Functions  

+  

+
arm_mat_trans_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_trans_q15 (const arm_matrix_instance_q15 *pSrc, arm_matrix_instance_q15 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__q15_8c_source.html
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+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__q15_8c_source.html
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+CMSIS DSP Software Library: arm_mat_trans_q15.c Source File
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+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__q31_8c.html
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--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__q31_8c.html
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+
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+CMSIS DSP Software Library: arm_mat_trans_q31.c File Reference
+
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+
+

+  

+Functions  

+  

+
arm_mat_trans_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_trans_q31 (const arm_matrix_instance_q31 *pSrc, arm_matrix_instance_q31 *pDst)

+

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+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__q31_8c_source.html
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+CMSIS DSP Software Library: arm_mat_trans_q31.c Source File
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Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__math_8h.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__math_8h.html
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+
+
+CMSIS DSP Software Library: arm_math.h File Reference
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+
+

+  

+Data Structures |
+Defines |
+Typedefs |
+Enumerations |
+Functions  

+  

+
arm_math.h File Reference
  

+

+

+#include "ARMCM4.h"

+#include "string.h"

+#include "math.h"

+
+
Go to the source code of this file.

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+Data Structures
struct  arm_fir_instance_q7
 Instance structure for the Q7 FIR filter.  More...
struct  arm_fir_instance_q15
 Instance structure for the Q15 FIR filter.  More...
struct  arm_fir_instance_q31
 Instance structure for the Q31 FIR filter.  More...
struct  arm_fir_instance_f32
 Instance structure for the floating-point FIR filter.  More...
struct  arm_biquad_casd_df1_inst_q15
 Instance structure for the Q15 Biquad cascade filter.  More...
struct  arm_biquad_casd_df1_inst_q31
 Instance structure for the Q31 Biquad cascade filter.  More...
struct  arm_biquad_casd_df1_inst_f32
 Instance structure for the floating-point Biquad cascade filter.  More...
struct  arm_matrix_instance_f32
 Instance structure for the floating-point matrix structure.  More...
struct  arm_matrix_instance_q15
 Instance structure for the Q15 matrix structure.  More...
struct  arm_matrix_instance_q31
 Instance structure for the Q31 matrix structure.  More...
struct  arm_pid_instance_q15
 Instance structure for the Q15 PID Control.  More...
struct  arm_pid_instance_q31
 Instance structure for the Q31 PID Control.  More...
struct  arm_pid_instance_f32
 Instance structure for the floating-point PID Control.  More...
struct  arm_linear_interp_instance_f32
 Instance structure for the floating-point Linear Interpolate function.  More...
struct  arm_bilinear_interp_instance_f32
 Instance structure for the floating-point bilinear interpolation function.  More...
struct  arm_bilinear_interp_instance_q31
 Instance structure for the Q31 bilinear interpolation function.  More...
struct  arm_bilinear_interp_instance_q15
 Instance structure for the Q15 bilinear interpolation function.  More...
struct  arm_bilinear_interp_instance_q7
 Instance structure for the Q15 bilinear interpolation function.  More...
struct  arm_cfft_radix4_instance_q15
 Instance structure for the Q15 CFFT/CIFFT function.  More...
struct  arm_cfft_radix4_instance_q31
 Instance structure for the Q31 CFFT/CIFFT function.  More...
struct  arm_cfft_radix4_instance_f32
 Instance structure for the floating-point CFFT/CIFFT function.  More...
struct  arm_rfft_instance_q15
 Instance structure for the Q15 RFFT/RIFFT function.  More...
struct  arm_rfft_instance_q31
 Instance structure for the Q31 RFFT/RIFFT function.  More...
struct  arm_rfft_instance_f32
 Instance structure for the floating-point RFFT/RIFFT function.  More...
struct  arm_dct4_instance_f32
 Instance structure for the floating-point DCT4/IDCT4 function.  More...
struct  arm_dct4_instance_q31
 Instance structure for the Q31 DCT4/IDCT4 function.  More...
struct  arm_dct4_instance_q15
 Instance structure for the Q15 DCT4/IDCT4 function.  More...
struct  arm_fir_decimate_instance_q15
 Instance structure for the Q15 FIR decimator.  More...
struct  arm_fir_decimate_instance_q31
 Instance structure for the Q31 FIR decimator.  More...
struct  arm_fir_decimate_instance_f32
 Instance structure for the floating-point FIR decimator.  More...
struct  arm_fir_interpolate_instance_q15
 Instance structure for the Q15 FIR interpolator.  More...
struct  arm_fir_interpolate_instance_q31
 Instance structure for the Q31 FIR interpolator.  More...
struct  arm_fir_interpolate_instance_f32
 Instance structure for the floating-point FIR interpolator.  More...
struct  arm_biquad_cas_df1_32x64_ins_q31
 Instance structure for the high precision Q31 Biquad cascade filter.  More...
struct  arm_biquad_cascade_df2T_instance_f32
 Instance structure for the floating-point transposed direct form II Biquad cascade filter.  More...
struct  arm_fir_lattice_instance_q15
 Instance structure for the Q15 FIR lattice filter.  More...
struct  arm_fir_lattice_instance_q31
 Instance structure for the Q31 FIR lattice filter.  More...
struct  arm_fir_lattice_instance_f32
 Instance structure for the floating-point FIR lattice filter.  More...
struct  arm_iir_lattice_instance_q15
 Instance structure for the Q15 IIR lattice filter.  More...
struct  arm_iir_lattice_instance_q31
 Instance structure for the Q31 IIR lattice filter.  More...
struct  arm_iir_lattice_instance_f32
 Instance structure for the floating-point IIR lattice filter.  More...
struct  arm_lms_instance_f32
 Instance structure for the floating-point LMS filter.  More...
struct  arm_lms_instance_q15
 Instance structure for the Q15 LMS filter.  More...
struct  arm_lms_instance_q31
 Instance structure for the Q31 LMS filter.  More...
struct  arm_lms_norm_instance_f32
 Instance structure for the floating-point normalized LMS filter.  More...
struct  arm_lms_norm_instance_q31
 Instance structure for the Q31 normalized LMS filter.  More...
struct  arm_lms_norm_instance_q15
 Instance structure for the Q15 normalized LMS filter.  More...
struct  arm_fir_sparse_instance_f32
 Instance structure for the floating-point sparse FIR filter.  More...
struct  arm_fir_sparse_instance_q31
 Instance structure for the Q31 sparse FIR filter.  More...
struct  arm_fir_sparse_instance_q15
 Instance structure for the Q15 sparse FIR filter.  More...
struct  arm_fir_sparse_instance_q7
 Instance structure for the Q7 sparse FIR filter.  More...

+Defines
#define __CMSIS_GENERIC
#define DELTA_Q31   (0x100)
#define DELTA_Q15   0x5
#define INDEX_MASK   0x0000003F
#define PI   3.14159265358979f
#define TABLE_SIZE   256
#define TABLE_SPACING_Q31   0x800000
#define TABLE_SPACING_Q15   0x80
#define INPUT_SPACING   0xB60B61
#define __SIMD32(addr)   (*(int32_t **) & (addr))
#define __PACKq7(v0, v1, v2, v3)

+Typedefs
typedef int8_t q7_t
typedef int16_t q15_t
typedef int32_t q31_t
typedef int64_t q63_t
typedef float float32_t
typedef double float64_t

+Enumerations
enum  arm_status { 

+  ARM_MATH_SUCCESS =  0, 
+ARM_MATH_ARGUMENT_ERROR =  -1, 
+ARM_MATH_LENGTH_ERROR =  -2, 
+ARM_MATH_SIZE_MISMATCH =  -3, 
+

+  ARM_MATH_NANINF =  -4, 
+ARM_MATH_SINGULAR =  -5, 
+ARM_MATH_TEST_FAILURE =  -6
+

+ }

+Functions
static __INLINE q31_t clip_q63_to_q31 (q63_t x)
static __INLINE q15_t clip_q63_to_q15 (q63_t x)
static __INLINE q7_t clip_q31_to_q7 (q31_t x)
static __INLINE q15_t clip_q31_to_q15 (q31_t x)
static __INLINE q63_t mult32x64 (q63_t x, q31_t y)
static __INLINE uint32_t arm_recip_q31 (q31_t in, q31_t *dst, q31_t *pRecipTable)
static __INLINE uint32_t arm_recip_q15 (q15_t in, q15_t *dst, q15_t *pRecipTable)
void arm_fir_q7 (const arm_fir_instance_q7 *S, q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
void arm_fir_init_q7 (arm_fir_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, uint32_t blockSize)
void arm_fir_q15 (const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_fir_fast_q15 (const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
arm_status arm_fir_init_q15 (arm_fir_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
void arm_fir_q31 (const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_fir_fast_q31 (const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_fir_init_q31 (arm_fir_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
void arm_fir_f32 (const arm_fir_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_fir_init_f32 (arm_fir_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
void arm_biquad_cascade_df1_q15 (const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_biquad_cascade_df1_init_q15 (arm_biquad_casd_df1_inst_q15 *S, uint8_t numStages, q15_t *pCoeffs, q15_t *pState, int8_t postShift)
void arm_biquad_cascade_df1_fast_q15 (const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_biquad_cascade_df1_q31 (const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_biquad_cascade_df1_fast_q31 (const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_biquad_cascade_df1_init_q31 (arm_biquad_casd_df1_inst_q31 *S, uint8_t numStages, q31_t *pCoeffs, q31_t *pState, int8_t postShift)
void arm_biquad_cascade_df1_f32 (const arm_biquad_casd_df1_inst_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_biquad_cascade_df1_init_f32 (arm_biquad_casd_df1_inst_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState)
arm_status arm_mat_add_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
arm_status arm_mat_add_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst)
arm_status arm_mat_add_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
arm_status arm_mat_trans_f32 (const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst)
arm_status arm_mat_trans_q15 (const arm_matrix_instance_q15 *pSrc, arm_matrix_instance_q15 *pDst)
arm_status arm_mat_trans_q31 (const arm_matrix_instance_q31 *pSrc, arm_matrix_instance_q31 *pDst)
arm_status arm_mat_mult_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
arm_status arm_mat_mult_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState)
arm_status arm_mat_mult_fast_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState)
arm_status arm_mat_mult_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
arm_status arm_mat_mult_fast_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
arm_status arm_mat_sub_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
arm_status arm_mat_sub_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst)
arm_status arm_mat_sub_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
arm_status arm_mat_scale_f32 (const arm_matrix_instance_f32 *pSrc, float32_t scale, arm_matrix_instance_f32 *pDst)
arm_status arm_mat_scale_q15 (const arm_matrix_instance_q15 *pSrc, q15_t scaleFract, int32_t shift, arm_matrix_instance_q15 *pDst)
arm_status arm_mat_scale_q31 (const arm_matrix_instance_q31 *pSrc, q31_t scaleFract, int32_t shift, arm_matrix_instance_q31 *pDst)
void arm_mat_init_q31 (arm_matrix_instance_q31 *S, uint16_t nRows, uint16_t nColumns, q31_t *pData)
void arm_mat_init_q15 (arm_matrix_instance_q15 *S, uint16_t nRows, uint16_t nColumns, q15_t *pData)
void arm_mat_init_f32 (arm_matrix_instance_f32 *S, uint16_t nRows, uint16_t nColumns, float32_t *pData)
void arm_pid_init_f32 (arm_pid_instance_f32 *S, int32_t resetStateFlag)
void arm_pid_reset_f32 (arm_pid_instance_f32 *S)
void arm_pid_init_q31 (arm_pid_instance_q31 *S, int32_t resetStateFlag)
void arm_pid_reset_q31 (arm_pid_instance_q31 *S)
void arm_pid_init_q15 (arm_pid_instance_q15 *S, int32_t resetStateFlag)
void arm_pid_reset_q15 (arm_pid_instance_q15 *S)
void arm_mult_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)
void arm_mult_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
void arm_mult_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
void arm_mult_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
void arm_cfft_radix4_q15 (const arm_cfft_radix4_instance_q15 *S, q15_t *pSrc)
arm_status arm_cfft_radix4_init_q15 (arm_cfft_radix4_instance_q15 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
void arm_cfft_radix4_q31 (const arm_cfft_radix4_instance_q31 *S, q31_t *pSrc)
arm_status arm_cfft_radix4_init_q31 (arm_cfft_radix4_instance_q31 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
void arm_cfft_radix4_f32 (const arm_cfft_radix4_instance_f32 *S, float32_t *pSrc)
arm_status arm_cfft_radix4_init_f32 (arm_cfft_radix4_instance_f32 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
void arm_radix4_butterfly_f32 (float32_t *pSrc, uint16_t fftLen, float32_t *pCoef, uint16_t twidCoefModifier)
void arm_radix4_butterfly_inverse_f32 (float32_t *pSrc, uint16_t fftLen, float32_t *pCoef, uint16_t twidCoefModifier, float32_t onebyfftLen)
void arm_bitreversal_f32 (float32_t *pSrc, uint16_t fftSize, uint16_t bitRevFactor, uint16_t *pBitRevTab)
void arm_radix4_butterfly_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pCoef, uint32_t twidCoefModifier)
void arm_radix4_butterfly_inverse_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pCoef, uint32_t twidCoefModifier)
void arm_bitreversal_q31 (q31_t *pSrc, uint32_t fftLen, uint16_t bitRevFactor, uint16_t *pBitRevTab)
void arm_radix4_butterfly_q15 (q15_t *pSrc16, uint32_t fftLen, q15_t *pCoef16, uint32_t twidCoefModifier)
void arm_radix4_butterfly_inverse_q15 (q15_t *pSrc16, uint32_t fftLen, q15_t *pCoef16, uint32_t twidCoefModifier)
void arm_bitreversal_q15 (q15_t *pSrc, uint32_t fftLen, uint16_t bitRevFactor, uint16_t *pBitRevTab)
void arm_rfft_q15 (const arm_rfft_instance_q15 *S, q15_t *pSrc, q15_t *pDst)
arm_status arm_rfft_init_q15 (arm_rfft_instance_q15 *S, arm_cfft_radix4_instance_q15 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
void arm_rfft_q31 (const arm_rfft_instance_q31 *S, q31_t *pSrc, q31_t *pDst)
arm_status arm_rfft_init_q31 (arm_rfft_instance_q31 *S, arm_cfft_radix4_instance_q31 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
arm_status arm_rfft_init_f32 (arm_rfft_instance_f32 *S, arm_cfft_radix4_instance_f32 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
void arm_rfft_f32 (const arm_rfft_instance_f32 *S, float32_t *pSrc, float32_t *pDst)
arm_status arm_dct4_init_f32 (arm_dct4_instance_f32 *S, arm_rfft_instance_f32 *S_RFFT, arm_cfft_radix4_instance_f32 *S_CFFT, uint16_t N, uint16_t Nby2, float32_t normalize)
void arm_dct4_f32 (const arm_dct4_instance_f32 *S, float32_t *pState, float32_t *pInlineBuffer)
arm_status arm_dct4_init_q31 (arm_dct4_instance_q31 *S, arm_rfft_instance_q31 *S_RFFT, arm_cfft_radix4_instance_q31 *S_CFFT, uint16_t N, uint16_t Nby2, q31_t normalize)
void arm_dct4_q31 (const arm_dct4_instance_q31 *S, q31_t *pState, q31_t *pInlineBuffer)
arm_status arm_dct4_init_q15 (arm_dct4_instance_q15 *S, arm_rfft_instance_q15 *S_RFFT, arm_cfft_radix4_instance_q15 *S_CFFT, uint16_t N, uint16_t Nby2, q15_t normalize)
void arm_dct4_q15 (const arm_dct4_instance_q15 *S, q15_t *pState, q15_t *pInlineBuffer)
void arm_add_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
void arm_add_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)
void arm_add_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
void arm_add_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
void arm_sub_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
void arm_sub_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)
void arm_sub_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
void arm_sub_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
void arm_scale_f32 (float32_t *pSrc, float32_t scale, float32_t *pDst, uint32_t blockSize)
void arm_scale_q7 (q7_t *pSrc, q7_t scaleFract, int8_t shift, q7_t *pDst, uint32_t blockSize)
void arm_scale_q15 (q15_t *pSrc, q15_t scaleFract, int8_t shift, q15_t *pDst, uint32_t blockSize)
void arm_scale_q31 (q31_t *pSrc, q31_t scaleFract, int8_t shift, q31_t *pDst, uint32_t blockSize)
void arm_abs_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
void arm_abs_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_abs_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_abs_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_dot_prod_f32 (float32_t *pSrcA, float32_t *pSrcB, uint32_t blockSize, float32_t *result)
void arm_dot_prod_q7 (q7_t *pSrcA, q7_t *pSrcB, uint32_t blockSize, q31_t *result)
void arm_dot_prod_q15 (q15_t *pSrcA, q15_t *pSrcB, uint32_t blockSize, q63_t *result)
void arm_dot_prod_q31 (q31_t *pSrcA, q31_t *pSrcB, uint32_t blockSize, q63_t *result)
void arm_shift_q7 (q7_t *pSrc, int8_t shiftBits, q7_t *pDst, uint32_t blockSize)
void arm_shift_q15 (q15_t *pSrc, int8_t shiftBits, q15_t *pDst, uint32_t blockSize)
void arm_shift_q31 (q31_t *pSrc, int8_t shiftBits, q31_t *pDst, uint32_t blockSize)
void arm_offset_f32 (float32_t *pSrc, float32_t offset, float32_t *pDst, uint32_t blockSize)
void arm_offset_q7 (q7_t *pSrc, q7_t offset, q7_t *pDst, uint32_t blockSize)
void arm_offset_q15 (q15_t *pSrc, q15_t offset, q15_t *pDst, uint32_t blockSize)
void arm_offset_q31 (q31_t *pSrc, q31_t offset, q31_t *pDst, uint32_t blockSize)
void arm_negate_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_negate_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
void arm_negate_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_negate_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_copy_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_copy_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
void arm_copy_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_copy_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_fill_f32 (float32_t value, float32_t *pDst, uint32_t blockSize)
void arm_fill_q7 (q7_t value, q7_t *pDst, uint32_t blockSize)
void arm_fill_q15 (q15_t value, q15_t *pDst, uint32_t blockSize)
void arm_fill_q31 (q31_t value, q31_t *pDst, uint32_t blockSize)
void arm_conv_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst)
void arm_conv_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
void arm_conv_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
void arm_conv_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
void arm_conv_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
void arm_conv_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst)
arm_status arm_conv_partial_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst, uint32_t firstIndex, uint32_t numPoints)
arm_status arm_conv_partial_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints)
arm_status arm_conv_partial_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints)
arm_status arm_conv_partial_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints)
arm_status arm_conv_partial_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints)
arm_status arm_conv_partial_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, uint32_t firstIndex, uint32_t numPoints)
void arm_fir_decimate_f32 (const arm_fir_decimate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
arm_status arm_fir_decimate_init_f32 (arm_fir_decimate_instance_f32 *S, uint16_t numTaps, uint8_t M, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
void arm_fir_decimate_q15 (const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_fir_decimate_fast_q15 (const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
arm_status arm_fir_decimate_init_q15 (arm_fir_decimate_instance_q15 *S, uint16_t numTaps, uint8_t M, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
void arm_fir_decimate_q31 (const arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_fir_decimate_fast_q31 (arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
arm_status arm_fir_decimate_init_q31 (arm_fir_decimate_instance_q31 *S, uint16_t numTaps, uint8_t M, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
void arm_fir_interpolate_q15 (const arm_fir_interpolate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
arm_status arm_fir_interpolate_init_q15 (arm_fir_interpolate_instance_q15 *S, uint8_t L, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
void arm_fir_interpolate_q31 (const arm_fir_interpolate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
arm_status arm_fir_interpolate_init_q31 (arm_fir_interpolate_instance_q31 *S, uint8_t L, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
void arm_fir_interpolate_f32 (const arm_fir_interpolate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
arm_status arm_fir_interpolate_init_f32 (arm_fir_interpolate_instance_f32 *S, uint8_t L, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
void arm_biquad_cas_df1_32x64_q31 (const arm_biquad_cas_df1_32x64_ins_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_biquad_cas_df1_32x64_init_q31 (arm_biquad_cas_df1_32x64_ins_q31 *S, uint8_t numStages, q31_t *pCoeffs, q63_t *pState, uint8_t postShift)
void arm_biquad_cascade_df2T_f32 (const arm_biquad_cascade_df2T_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_biquad_cascade_df2T_init_f32 (arm_biquad_cascade_df2T_instance_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState)
void arm_fir_lattice_init_q15 (arm_fir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pCoeffs, q15_t *pState)
void arm_fir_lattice_q15 (const arm_fir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_fir_lattice_init_q31 (arm_fir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pCoeffs, q31_t *pState)
void arm_fir_lattice_q31 (const arm_fir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_fir_lattice_init_f32 (arm_fir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pCoeffs, float32_t *pState)
void arm_fir_lattice_f32 (const arm_fir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_iir_lattice_f32 (const arm_iir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_iir_lattice_init_f32 (arm_iir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pkCoeffs, float32_t *pvCoeffs, float32_t *pState, uint32_t blockSize)
void arm_iir_lattice_q31 (const arm_iir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_iir_lattice_init_q31 (arm_iir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pkCoeffs, q31_t *pvCoeffs, q31_t *pState, uint32_t blockSize)
void arm_iir_lattice_q15 (const arm_iir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_iir_lattice_init_q15 (arm_iir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pkCoeffs, q15_t *pvCoeffs, q15_t *pState, uint32_t blockSize)
void arm_lms_f32 (const arm_lms_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize)
void arm_lms_init_f32 (arm_lms_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize)
void arm_lms_init_q15 (arm_lms_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint32_t postShift)
void arm_lms_q15 (const arm_lms_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize)
void arm_lms_q31 (const arm_lms_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize)
void arm_lms_init_q31 (arm_lms_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint32_t postShift)
void arm_lms_norm_f32 (arm_lms_norm_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize)
void arm_lms_norm_init_f32 (arm_lms_norm_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize)
void arm_lms_norm_q31 (arm_lms_norm_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize)
void arm_lms_norm_init_q31 (arm_lms_norm_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint8_t postShift)
void arm_lms_norm_q15 (arm_lms_norm_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize)
void arm_lms_norm_init_q15 (arm_lms_norm_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint8_t postShift)
void arm_correlate_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst)
void arm_correlate_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
void arm_correlate_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
void arm_correlate_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
void arm_correlate_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
void arm_correlate_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst)
void arm_fir_sparse_f32 (arm_fir_sparse_instance_f32 *S, float32_t *pSrc, float32_t *pDst, float32_t *pScratchIn, uint32_t blockSize)
void arm_fir_sparse_init_f32 (arm_fir_sparse_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
void arm_fir_sparse_q31 (arm_fir_sparse_instance_q31 *S, q31_t *pSrc, q31_t *pDst, q31_t *pScratchIn, uint32_t blockSize)
void arm_fir_sparse_init_q31 (arm_fir_sparse_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
void arm_fir_sparse_q15 (arm_fir_sparse_instance_q15 *S, q15_t *pSrc, q15_t *pDst, q15_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize)
void arm_fir_sparse_init_q15 (arm_fir_sparse_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
void arm_fir_sparse_q7 (arm_fir_sparse_instance_q7 *S, q7_t *pSrc, q7_t *pDst, q7_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize)
void arm_fir_sparse_init_q7 (arm_fir_sparse_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
void arm_sin_cos_f32 (float32_t theta, float32_t *pSinVal, float32_t *pCcosVal)
void arm_sin_cos_q31 (q31_t theta, q31_t *pSinVal, q31_t *pCosVal)
void arm_cmplx_conj_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
void arm_cmplx_conj_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
void arm_cmplx_conj_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)
void arm_cmplx_mag_squared_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
void arm_cmplx_mag_squared_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
void arm_cmplx_mag_squared_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)
static __INLINE float32_t arm_pid_f32 (arm_pid_instance_f32 *S, float32_t in)
static __INLINE q31_t arm_pid_q31 (arm_pid_instance_q31 *S, q31_t in)
static __INLINE q15_t arm_pid_q15 (arm_pid_instance_q15 *S, q15_t in)
arm_status arm_mat_inverse_f32 (const arm_matrix_instance_f32 *src, arm_matrix_instance_f32 *dst)
static __INLINE void arm_clarke_f32 (float32_t Ia, float32_t Ib, float32_t *pIalpha, float32_t *pIbeta)
static __INLINE void arm_clarke_q31 (q31_t Ia, q31_t Ib, q31_t *pIalpha, q31_t *pIbeta)
void arm_q7_to_q31 (q7_t *pSrc, q31_t *pDst, uint32_t blockSize)
static __INLINE void arm_inv_clarke_f32 (float32_t Ialpha, float32_t Ibeta, float32_t *pIa, float32_t *pIb)
static __INLINE void arm_inv_clarke_q31 (q31_t Ialpha, q31_t Ibeta, q31_t *pIa, q31_t *pIb)
void arm_q7_to_q15 (q7_t *pSrc, q15_t *pDst, uint32_t blockSize)
static __INLINE void arm_park_f32 (float32_t Ialpha, float32_t Ibeta, float32_t *pId, float32_t *pIq, float32_t sinVal, float32_t cosVal)
static __INLINE void arm_park_q31 (q31_t Ialpha, q31_t Ibeta, q31_t *pId, q31_t *pIq, q31_t sinVal, q31_t cosVal)
void arm_q7_to_float (q7_t *pSrc, float32_t *pDst, uint32_t blockSize)
static __INLINE void arm_inv_park_f32 (float32_t Id, float32_t Iq, float32_t *pIalpha, float32_t *pIbeta, float32_t sinVal, float32_t cosVal)
static __INLINE void arm_inv_park_q31 (q31_t Id, q31_t Iq, q31_t *pIalpha, q31_t *pIbeta, q31_t sinVal, q31_t cosVal)
void arm_q31_to_float (q31_t *pSrc, float32_t *pDst, uint32_t blockSize)
static __INLINE float32_t arm_linear_interp_f32 (arm_linear_interp_instance_f32 *S, float32_t x)
static __INLINE q31_t arm_linear_interp_q31 (q31_t *pYData, q31_t x, uint32_t nValues)
static __INLINE q15_t arm_linear_interp_q15 (q15_t *pYData, q31_t x, uint32_t nValues)
static __INLINE q7_t arm_linear_interp_q7 (q7_t *pYData, q31_t x, uint32_t nValues)
float32_t arm_sin_f32 (float32_t x)
q31_t arm_sin_q31 (q31_t x)
q15_t arm_sin_q15 (q15_t x)
float32_t arm_cos_f32 (float32_t x)
q31_t arm_cos_q31 (q31_t x)
q15_t arm_cos_q15 (q15_t x)
static __INLINE arm_status arm_sqrt_f32 (float32_t in, float32_t *pOut)
arm_status arm_sqrt_q31 (q31_t in, q31_t *pOut)
arm_status arm_sqrt_q15 (q15_t in, q15_t *pOut)
static __INLINE void arm_circularWrite_f32 (int32_t *circBuffer, int32_t L, uint16_t *writeOffset, int32_t bufferInc, const int32_t *src, int32_t srcInc, uint32_t blockSize)
static __INLINE void arm_circularRead_f32 (int32_t *circBuffer, int32_t L, int32_t *readOffset, int32_t bufferInc, int32_t *dst, int32_t *dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize)
static __INLINE void arm_circularWrite_q15 (q15_t *circBuffer, int32_t L, uint16_t *writeOffset, int32_t bufferInc, const q15_t *src, int32_t srcInc, uint32_t blockSize)
static __INLINE void arm_circularRead_q15 (q15_t *circBuffer, int32_t L, int32_t *readOffset, int32_t bufferInc, q15_t *dst, q15_t *dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize)
static __INLINE void arm_circularWrite_q7 (q7_t *circBuffer, int32_t L, uint16_t *writeOffset, int32_t bufferInc, const q7_t *src, int32_t srcInc, uint32_t blockSize)
static __INLINE void arm_circularRead_q7 (q7_t *circBuffer, int32_t L, int32_t *readOffset, int32_t bufferInc, q7_t *dst, q7_t *dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize)
void arm_power_q31 (q31_t *pSrc, uint32_t blockSize, q63_t *pResult)
void arm_power_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
void arm_power_q15 (q15_t *pSrc, uint32_t blockSize, q63_t *pResult)
void arm_power_q7 (q7_t *pSrc, uint32_t blockSize, q31_t *pResult)
void arm_mean_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult)
void arm_mean_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)
void arm_mean_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
void arm_mean_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
void arm_var_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
void arm_var_q31 (q31_t *pSrc, uint32_t blockSize, q63_t *pResult)
void arm_var_q15 (q15_t *pSrc, uint32_t blockSize, q31_t *pResult)
void arm_rms_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
void arm_rms_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
void arm_rms_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)
void arm_std_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
void arm_std_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
void arm_std_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)
void arm_cmplx_mag_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
void arm_cmplx_mag_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
void arm_cmplx_mag_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)
void arm_cmplx_dot_prod_q15 (q15_t *pSrcA, q15_t *pSrcB, uint32_t numSamples, q31_t *realResult, q31_t *imagResult)
void arm_cmplx_dot_prod_q31 (q31_t *pSrcA, q31_t *pSrcB, uint32_t numSamples, q63_t *realResult, q63_t *imagResult)
void arm_cmplx_dot_prod_f32 (float32_t *pSrcA, float32_t *pSrcB, uint32_t numSamples, float32_t *realResult, float32_t *imagResult)
void arm_cmplx_mult_real_q15 (q15_t *pSrcCmplx, q15_t *pSrcReal, q15_t *pCmplxDst, uint32_t numSamples)
void arm_cmplx_mult_real_q31 (q31_t *pSrcCmplx, q31_t *pSrcReal, q31_t *pCmplxDst, uint32_t numSamples)
void arm_cmplx_mult_real_f32 (float32_t *pSrcCmplx, float32_t *pSrcReal, float32_t *pCmplxDst, uint32_t numSamples)
void arm_min_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *result, uint32_t *index)
void arm_min_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex)
void arm_min_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex)
void arm_min_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex)
void arm_max_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex)
void arm_max_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex)
void arm_max_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex)
void arm_max_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex)
void arm_cmplx_mult_cmplx_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t numSamples)
void arm_cmplx_mult_cmplx_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t numSamples)
void arm_cmplx_mult_cmplx_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t numSamples)
void arm_float_to_q31 (float32_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_float_to_q15 (float32_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_float_to_q7 (float32_t *pSrc, q7_t *pDst, uint32_t blockSize)
void arm_q31_to_q15 (q31_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_q31_to_q7 (q31_t *pSrc, q7_t *pDst, uint32_t blockSize)
void arm_q15_to_float (q15_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_q15_to_q31 (q15_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_q15_to_q7 (q15_t *pSrc, q7_t *pDst, uint32_t blockSize)
static __INLINE float32_t arm_bilinear_interp_f32 (const arm_bilinear_interp_instance_f32 *S, float32_t X, float32_t Y)
static __INLINE q31_t arm_bilinear_interp_q31 (arm_bilinear_interp_instance_q31 *S, q31_t X, q31_t Y)
static __INLINE q15_t arm_bilinear_interp_q15 (arm_bilinear_interp_instance_q15 *S, q31_t X, q31_t Y)
static __INLINE q7_t arm_bilinear_interp_q7 (arm_bilinear_interp_instance_q7 *S, q31_t X, q31_t Y)

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Define Documentation

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#define __CMSIS_GENERIC

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Definition at line 254 of file arm_math.h.

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#define DELTA_Q31   (0x100)

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Macros required for reciprocal calculation in Normalized LMS. 

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Definition at line 280 of file arm_math.h.

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#define DELTA_Q15   0x5

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Definition at line 281 of file arm_math.h.

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#define INDEX_MASK   0x0000003F

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Definition at line 282 of file arm_math.h.

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#define PI   3.14159265358979f

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Definition at line 283 of file arm_math.h.

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#define TABLE_SIZE   256

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Macros required for SINE and COSINE Fast math approximations. 

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Definition at line 289 of file arm_math.h.

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#define TABLE_SPACING_Q31   0x800000

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Definition at line 290 of file arm_math.h.

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#define TABLE_SPACING_Q15   0x80

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Definition at line 291 of file arm_math.h.

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#define INPUT_SPACING   0xB60B61

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Macros required for SINE and COSINE Controller functions. 

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Definition at line 298 of file arm_math.h.

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#define __SIMD32( addr )   (*(int32_t **) & (addr))

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definition to read/write two 16 bit values. 

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Definition at line 349 of file arm_math.h.

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#define __PACKq7( v0, 
 v1, 
 v2, 
 v3 
)

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+Value:
( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |   \
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
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definition to pack four 8 bit values. 

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Definition at line 366 of file arm_math.h.

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Typedef Documentation

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typedef int8_t q7_t

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8-bit fractional data type in 1.7 format. 

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Definition at line 319 of file arm_math.h.

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typedef int16_t q15_t

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16-bit fractional data type in 1.15 format. 

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Definition at line 324 of file arm_math.h.

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typedef int32_t q31_t

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32-bit fractional data type in 1.31 format. 

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Definition at line 329 of file arm_math.h.

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typedef int64_t q63_t

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64-bit fractional data type in 1.63 format. 

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Definition at line 334 of file arm_math.h.

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typedef float float32_t

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32-bit floating-point type definition. 

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Definition at line 339 of file arm_math.h.

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typedef double float64_t

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64-bit floating-point type definition. 

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Definition at line 344 of file arm_math.h.

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Enumeration Type Documentation

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enum arm_status

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Error status returned by some functions in the library. 

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Enumerator: 

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ARM_MATH_SUCCESS 
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No error 

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ARM_MATH_ARGUMENT_ERROR 
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One or more arguments are incorrect 

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ARM_MATH_LENGTH_ERROR 
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Length of data buffer is incorrect 

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ARM_MATH_SIZE_MISMATCH 
+
Size of matrices is not compatible with the operation. 

+
ARM_MATH_NANINF 
+
Not-a-number (NaN) or infinity is generated 

+
ARM_MATH_SINGULAR 
+
Generated by matrix inversion if the input matrix is singular and cannot be inverted. 

+
ARM_MATH_TEST_FAILURE 
+
Test Failed 

+

+

+

+
+
Definition at line 305 of file arm_math.h.

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
static __INLINE q31_t clip_q63_to_q31 (q63_t  x ) [static]

+

+

+
+
Clips Q63 to Q31 values. 

+
+
Definition at line 383 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
static __INLINE q15_t clip_q63_to_q15 (q63_t  x ) [static]

+

+

+
+
Clips Q63 to Q15 values. 

+
+
Definition at line 393 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
static __INLINE q7_t clip_q31_to_q7 (q31_t  x ) [static]

+

+

+
+
Clips Q31 to Q7 values. 

+
+
Definition at line 403 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
static __INLINE q15_t clip_q31_to_q15 (q31_t  x ) [static]

+

+

+
+
Clips Q31 to Q15 values. 

+
+
Definition at line 413 of file arm_math.h.

+
+

+

+
+

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+        
+      
static __INLINE q63_t mult32x64 (q63_t  x, 
q31_t  y 
) [static]

+

+

+
+
Multiplies 32 X 64 and returns 32 bit result in 2.30 format. 

+
+
Definition at line 424 of file arm_math.h.

+
+

+

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+        
+      
static __INLINE uint32_t arm_recip_q31 (q31_t  in, 
q31_t *  dst, 
q31_t *  pRecipTable 
) [static]

+

+

+
+
Function to Calculates 1/in(reciprocal) value of Q31 Data type. 

+
+
Definition at line 463 of file arm_math.h.

+
+

+

+
+

+

+      
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+      
static __INLINE uint32_t arm_recip_q15 (q15_t  in, 
q15_t *  dst, 
q15_t *  pRecipTable 
) [static]

+

+

+
+
Function to Calculates 1/in(reciprocal) value of Q15 Data type. 

+
+
Definition at line 514 of file arm_math.h.

+
+

+

+
+

+

+      
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+      
void arm_radix4_butterfly_f32 (float32_t *  pSrc, 
uint16_t  fftLen, 
float32_t *  pCoef, 
uint16_t  twidCoefModifier 
)

+

+

+
+
Core function for the floating-point CFFT butterfly process. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of floating-point data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to the twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none.

+
end of CFFT_CIFFT group 

+
+
Definition at line 223 of file arm_cfft_radix4_f32.c.

+
+

+

+
+

+

+      
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+      
void arm_radix4_butterfly_inverse_f32 (float32_t *  pSrc, 
uint16_t  fftLen, 
float32_t *  pCoef, 
uint16_t  twidCoefModifier, 
float32_t  onebyfftLen 
)

+

+

+
+
Core function for the floating-point CIFFT butterfly process. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of floating-point data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
[in]onebyfftLenvalue of 1/fftLen. 

+  

+

+
Returns:
none. 

+
+
Definition at line 660 of file arm_cfft_radix4_f32.c.

+
+

+

+
+

+

+      
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+        
+      
void arm_bitreversal_f32 (float32_t *  pSrc, 
uint16_t  fftSize, 
uint16_t  bitRevFactor, 
uint16_t *  pBitRevTab 
)

+

+

+
+
In-place bit reversal function. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of floating-point data type. 
[in]fftSizelength of the FFT. 
[in]bitRevFactorbit reversal modifier that supports different size FFTs with the same bit reversal table. 
[in]*pBitRevTabpoints to the bit reversal table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 1177 of file arm_cfft_radix4_f32.c.

+
+

+

+
+

+

+      
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+        
+      
void arm_radix4_butterfly_q31 (q31_t *  pSrc, 
uint32_t  fftLen, 
q31_t *  pCoef, 
uint32_t  twidCoefModifier 
)

+

+

+
+
Core function for the Q31 CFFT butterfly process. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none.

+
end of CFFT_CIFFT group 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 139 of file arm_cfft_radix4_q31.c.

+
+

+

+
+

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+        
+      
void arm_radix4_butterfly_inverse_q31 (q31_t *  pSrc, 
uint32_t  fftLen, 
q31_t *  pCoef, 
uint32_t  twidCoefModifier 
)

+

+

+
+
Core function for the Q31 CIFFT butterfly process. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 517 of file arm_cfft_radix4_q31.c.

+
+

+

+
+

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+        
+      
void arm_bitreversal_q31 (q31_t *  pSrc, 
uint32_t  fftLen, 
uint16_t  bitRevFactor, 
uint16_t *  pBitRevTab 
)

+

+

+
+
In-place bit reversal function. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]bitRevFactorbit reversal modifier that supports different size FFTs with the same bit reversal table 
[in]*pBitRevTabpoints to bit reversal table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 848 of file arm_cfft_radix4_q31.c.

+
+

+

+
+

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+        
+      
void arm_radix4_butterfly_q15 (q15_t *  pSrc16, 
uint32_t  fftLen, 
q15_t *  pCoef16, 
uint32_t  twidCoefModifier 
)

+

+

+
+
Core function for the Q15 CFFT butterfly process. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrc16points to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoef16points to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none.

+
end of CFFT_CIFFT group 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrc16points to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoef16points to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 138 of file arm_cfft_radix4_q15.c.

+
+

+

+
+

+

+      
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+        
+      
void arm_radix4_butterfly_inverse_q15 (q15_t *  pSrc16, 
uint32_t  fftLen, 
q15_t *  pCoef16, 
uint32_t  twidCoefModifier 
)

+

+

+
+
Core function for the Q15 CIFFT butterfly process. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrc16points to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoef16points to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 1053 of file arm_cfft_radix4_q15.c.

+
+

+

+
+

+

+      
+        
+          
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+          
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+          
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+        
+          
+          
+          
+        
+      
void arm_bitreversal_q15 (q15_t *  pSrc, 
uint32_t  fftLen, 
uint16_t  bitRevFactor, 
uint16_t *  pBitRevTab 
)

+

+

+
+
In-place bit reversal function. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]bitRevFactorbit reversal modifier that supports different size FFTs with the same bit reversal table 
[in]*pBitRevTabpoints to bit reversal table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 1906 of file arm_cfft_radix4_q15.c.

+
+

+

+
+

+

+      
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+        
+      
static __INLINE void arm_circularWrite_f32 (int32_t *  circBuffer, 
int32_t  L, 
uint16_t *  writeOffset, 
int32_t  bufferInc, 
const int32_t *  src, 
int32_t  srcInc, 
uint32_t  blockSize 
) [static]

+

+

+
+
floating-point Circular write function. 

+
end of SQRT group 

+
+
Definition at line 5751 of file arm_math.h.

+
+

+

+
+

+

+      
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+        
+        
+          
+          
+          
+        
+      
static __INLINE void arm_circularRead_f32 (int32_t *  circBuffer, 
int32_t  L, 
int32_t *  readOffset, 
int32_t  bufferInc, 
int32_t *  dst, 
int32_t *  dst_base, 
int32_t  dst_length, 
int32_t  dstInc, 
uint32_t  blockSize 
) [static]

+

+

+
+
floating-point Circular Read function. 

+
+
Definition at line 5796 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+          
+          
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+        
+        
+          
+          
+          
+        
+      
static __INLINE void arm_circularWrite_q15 (q15_t *  circBuffer, 
int32_t  L, 
uint16_t *  writeOffset, 
int32_t  bufferInc, 
const q15_t *  src, 
int32_t  srcInc, 
uint32_t  blockSize 
) [static]

+

+

+
+
Q15 Circular write function. 

+
+
Definition at line 5851 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
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+        
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+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
static __INLINE void arm_circularRead_q15 (q15_t *  circBuffer, 
int32_t  L, 
int32_t *  readOffset, 
int32_t  bufferInc, 
q15_t *  dst, 
q15_t *  dst_base, 
int32_t  dst_length, 
int32_t  dstInc, 
uint32_t  blockSize 
) [static]

+

+

+
+
Q15 Circular Read function. 

+
+
Definition at line 5896 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
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+        
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+          
+        
+        
+          
+          
+          
+        
+      
static __INLINE void arm_circularWrite_q7 (q7_t *  circBuffer, 
int32_t  L, 
uint16_t *  writeOffset, 
int32_t  bufferInc, 
const q7_t *  src, 
int32_t  srcInc, 
uint32_t  blockSize 
) [static]

+

+

+
+
Q7 Circular write function. 

+
+
Definition at line 5953 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
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+        
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+        
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+          
+          
+          
+          
+        
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+          
+          
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+        
+        
+          
+          
+          
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+        
+        
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+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
static __INLINE void arm_circularRead_q7 (q7_t *  circBuffer, 
int32_t  L, 
int32_t *  readOffset, 
int32_t  bufferInc, 
q7_t *  dst, 
q7_t *  dst_base, 
int32_t  dst_length, 
int32_t  dstInc, 
uint32_t  blockSize 
) [static]

+

+

+
+
Q7 Circular Read function. 

+
+
Definition at line 5998 of file arm_math.h.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__math_8h_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__math_8h_source.html
new file mode 100644
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--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__math_8h_source.html
@@ -0,0 +1,3817 @@
+
+
+
+
+CMSIS DSP Software Library: arm_math.h Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__matrix__example__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__matrix__example__f32_8c.html
new file mode 100644
index 000000000..397df9f14
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__matrix__example__f32_8c.html
@@ -0,0 +1,275 @@
+
+
+
+
+CMSIS DSP Software Library: arm_matrix_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Defines |
+Functions |
+Variables  

+  

+
arm_matrix_example_f32.c File Reference
  

+

+

+#include "arm_math.h"

+#include "math_helper.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define SNR_THRESHOLD   90

+Functions
int32_t main (void)

+Variables
const float32_t B_f32 [4]
const float32_t A_f32 [16]
float32_t AT_f32 [16]
float32_t ATMA_f32 [16]
float32_t ATMAI_f32 [16]
float32_t X_f32 [4]
const float32_t xRef_f32 [4] = {73.0, 8.0, 21.25, 2.875}
float32_t snr

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define SNR_THRESHOLD   90

+

+

+
+
Definition at line 80 of file arm_matrix_example_f32.c.

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void  )

+

+

+
+
Definition at line 130 of file arm_matrix_example_f32.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float32_t B_f32[4]

+

+

+Initial value:
  
+{    
+    782.0, 7577.0, 470.0, 4505.0 
+}
+
Examples: 
arm_matrix_example_f32.c.

+

+
Definition at line 87 of file arm_matrix_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t A_f32[16]

+

+

+Initial value:
  
+{ 
+        
+    1.0,        32.0,       4.0,        128.0,  
+    1.0,        32.0,       64.0,       2048.0, 
+    1.0,        16.0,       4.0,        64.0, 
+    1.0,        16.0,       64.0,       1024.0, 
+}
+
Examples: 
arm_matrix_example_f32.c.

+

+
Definition at line 96 of file arm_matrix_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t AT_f32[16]

+

+

+
Examples: 
arm_matrix_example_f32.c.

+

+
Definition at line 110 of file arm_matrix_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t ATMA_f32[16]

+

+

+
Examples: 
arm_matrix_example_f32.c.

+

+
Definition at line 112 of file arm_matrix_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t ATMAI_f32[16]

+

+

+
Examples: 
arm_matrix_example_f32.c.

+

+
Definition at line 114 of file arm_matrix_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t X_f32[4]

+

+

+
Examples: 
arm_matrix_example_f32.c.

+

+
Definition at line 116 of file arm_matrix_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t xRef_f32[4] = {73.0, 8.0, 21.25, 2.875}

+

+

+
Examples: 
arm_matrix_example_f32.c.

+

+
Definition at line 121 of file arm_matrix_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t snr

+

+

+
+
Definition at line 123 of file arm_matrix_example_f32.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__matrix__example__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__matrix__example__f32_8c_source.html
new file mode 100644
index 000000000..56288e945
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__matrix__example__f32_8c_source.html
@@ -0,0 +1,236 @@
+
+
+
+
+CMSIS DSP Software Library: arm_matrix_example_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__max__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__max__f32_8c.html
new file mode 100644
index 000000000..cebc886bb
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__max__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_max_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_max_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_max_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__max__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__max__f32_8c_source.html
new file mode 100644
index 000000000..d6c3f7ef9
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__max__f32_8c_source.html
@@ -0,0 +1,170 @@
+
+
+
+
+CMSIS DSP Software Library: arm_max_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__max__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__max__q15_8c.html
new file mode 100644
index 000000000..5c404dd43
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__max__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_max_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_max_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_max_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__max__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__max__q15_8c_source.html
new file mode 100644
index 000000000..ab3f7c2ed
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__max__q15_8c_source.html
@@ -0,0 +1,170 @@
+
+
+
+
+CMSIS DSP Software Library: arm_max_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__max__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__max__q31_8c.html
new file mode 100644
index 000000000..cb5bf9c69
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__max__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_max_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_max_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_max_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__max__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__max__q31_8c_source.html
new file mode 100644
index 000000000..f673f6905
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__max__q31_8c_source.html
@@ -0,0 +1,172 @@
+
+
+
+
+CMSIS DSP Software Library: arm_max_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__max__q7_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__max__q7_8c.html
new file mode 100644
index 000000000..0795a1a25
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__max__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_max_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_max_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_max_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__max__q7_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__max__q7_8c_source.html
new file mode 100644
index 000000000..accd44897
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__max__q7_8c_source.html
@@ -0,0 +1,257 @@
+
+
+
+
+CMSIS DSP Software Library: arm_max_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mean__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mean__f32_8c.html
new file mode 100644
index 000000000..8893326b1
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mean__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mean_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mean_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_mean_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mean__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mean__f32_8c_source.html
new file mode 100644
index 000000000..886fcdca2
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mean__f32_8c_source.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mean_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mean__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mean__q15_8c.html
new file mode 100644
index 000000000..8af8eb7ba
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mean__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mean_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mean_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_mean_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mean__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mean__q15_8c_source.html
new file mode 100644
index 000000000..18d8b56e6
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mean__q15_8c_source.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mean_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mean__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mean__q31_8c.html
new file mode 100644
index 000000000..e72b7618e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mean__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mean_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mean_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_mean_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mean__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mean__q31_8c_source.html
new file mode 100644
index 000000000..5fb51c398
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mean__q31_8c_source.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mean_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mean__q7_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mean__q7_8c.html
new file mode 100644
index 000000000..4a58692ff
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mean__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mean_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mean_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_mean_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mean__q7_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mean__q7_8c_source.html
new file mode 100644
index 000000000..e28148b05
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mean__q7_8c_source.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mean_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__min__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__min__f32_8c.html
new file mode 100644
index 000000000..806e098ba
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__min__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_min_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_min_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_min_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__min__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__min__f32_8c_source.html
new file mode 100644
index 000000000..bf395b326
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__min__f32_8c_source.html
@@ -0,0 +1,175 @@
+
+
+
+
+CMSIS DSP Software Library: arm_min_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__min__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__min__q15_8c.html
new file mode 100644
index 000000000..52a2c72ba
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__min__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_min_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_min_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_min_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__min__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__min__q15_8c_source.html
new file mode 100644
index 000000000..30600e1ce
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__min__q15_8c_source.html
@@ -0,0 +1,176 @@
+
+
+
+
+CMSIS DSP Software Library: arm_min_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__min__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__min__q31_8c.html
new file mode 100644
index 000000000..97d75fa67
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__min__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_min_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_min_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_min_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__min__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__min__q31_8c_source.html
new file mode 100644
index 000000000..8e268d04c
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__min__q31_8c_source.html
@@ -0,0 +1,174 @@
+
+
+
+
+CMSIS DSP Software Library: arm_min_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__min__q7_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__min__q7_8c.html
new file mode 100644
index 000000000..c16961930
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__min__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_min_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_min_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_min_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__min__q7_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__min__q7_8c_source.html
new file mode 100644
index 000000000..e7802851d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__min__q7_8c_source.html
@@ -0,0 +1,254 @@
+
+
+
+
+CMSIS DSP Software Library: arm_min_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mult__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mult__f32_8c.html
new file mode 100644
index 000000000..0601319eb
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mult__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mult_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mult_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_mult_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mult__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mult__f32_8c_source.html
new file mode 100644
index 000000000..e89956bd4
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mult__f32_8c_source.html
@@ -0,0 +1,166 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mult_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mult__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mult__q15_8c.html
new file mode 100644
index 000000000..9c2068d44
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mult__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mult_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mult_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_mult_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mult__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mult__q15_8c_source.html
new file mode 100644
index 000000000..549addebd
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mult__q15_8c_source.html
@@ -0,0 +1,165 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mult_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mult__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mult__q31_8c.html
new file mode 100644
index 000000000..154851dcc
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mult__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mult_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mult_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_mult_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mult__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mult__q31_8c_source.html
new file mode 100644
index 000000000..c235c1d17
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mult__q31_8c_source.html
@@ -0,0 +1,168 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mult_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mult__q7_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mult__q7_8c.html
new file mode 100644
index 000000000..e0df57d95
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mult__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mult_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mult_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_mult_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mult__q7_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mult__q7_8c_source.html
new file mode 100644
index 000000000..a7a67901b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__mult__q7_8c_source.html
@@ -0,0 +1,172 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mult_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__negate__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__negate__f32_8c.html
new file mode 100644
index 000000000..08dbd5f35
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__negate__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_negate_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_negate_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_negate_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__negate__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__negate__f32_8c_source.html
new file mode 100644
index 000000000..2980f57be
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__negate__f32_8c_source.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_negate_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__negate__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__negate__q15_8c.html
new file mode 100644
index 000000000..28dc3d644
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__negate__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_negate_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_negate_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_negate_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__negate__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__negate__q15_8c_source.html
new file mode 100644
index 000000000..cfda4c81b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__negate__q15_8c_source.html
@@ -0,0 +1,188 @@
+
+
+
+
+CMSIS DSP Software Library: arm_negate_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__negate__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__negate__q31_8c.html
new file mode 100644
index 000000000..fa798f017
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__negate__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_negate_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_negate_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_negate_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__negate__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__negate__q31_8c_source.html
new file mode 100644
index 000000000..fd34eb2dc
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__negate__q31_8c_source.html
@@ -0,0 +1,167 @@
+
+
+
+
+CMSIS DSP Software Library: arm_negate_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__negate__q7_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__negate__q7_8c.html
new file mode 100644
index 000000000..43adc0e98
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__negate__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_negate_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_negate_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_negate_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__negate__q7_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__negate__q7_8c_source.html
new file mode 100644
index 000000000..6aff496a9
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__negate__q7_8c_source.html
@@ -0,0 +1,170 @@
+
+
+
+
+CMSIS DSP Software Library: arm_negate_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__offset__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__offset__f32_8c.html
new file mode 100644
index 000000000..8c6ca5f21
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__offset__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_offset_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_offset_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_offset_f32 (float32_t *pSrc, float32_t offset, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__offset__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__offset__f32_8c_source.html
new file mode 100644
index 000000000..b53a1b2f5
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__offset__f32_8c_source.html
@@ -0,0 +1,161 @@
+
+
+
+
+CMSIS DSP Software Library: arm_offset_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__offset__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__offset__q15_8c.html
new file mode 100644
index 000000000..f773a85a0
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__offset__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_offset_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_offset_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_offset_q15 (q15_t *pSrc, q15_t offset, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__offset__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__offset__q15_8c_source.html
new file mode 100644
index 000000000..5b96cf87b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__offset__q15_8c_source.html
@@ -0,0 +1,175 @@
+
+
+
+
+CMSIS DSP Software Library: arm_offset_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__offset__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__offset__q31_8c.html
new file mode 100644
index 000000000..ac3b46415
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__offset__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_offset_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_offset_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_offset_q31 (q31_t *pSrc, q31_t offset, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__offset__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__offset__q31_8c_source.html
new file mode 100644
index 000000000..6739240f2
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__offset__q31_8c_source.html
@@ -0,0 +1,173 @@
+
+
+
+
+CMSIS DSP Software Library: arm_offset_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__offset__q7_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__offset__q7_8c.html
new file mode 100644
index 000000000..4c3e36e56
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__offset__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_offset_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_offset_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_offset_q7 (q7_t *pSrc, q7_t offset, q7_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__offset__q7_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__offset__q7_8c_source.html
new file mode 100644
index 000000000..d8bd330eb
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__offset__q7_8c_source.html
@@ -0,0 +1,174 @@
+
+
+
+
+CMSIS DSP Software Library: arm_offset_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__f32_8c.html
new file mode 100644
index 000000000..9923ee89b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_pid_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_pid_init_f32 (arm_pid_instance_f32 *S, int32_t resetStateFlag)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__f32_8c_source.html
new file mode 100644
index 000000000..3ba46253f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__f32_8c_source.html
@@ -0,0 +1,128 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_init_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__q15_8c.html
new file mode 100644
index 000000000..911792ef2
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_pid_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_pid_init_q15 (arm_pid_instance_q15 *S, int32_t resetStateFlag)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__q15_8c_source.html
new file mode 100644
index 000000000..ddd14a47e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__q15_8c_source.html
@@ -0,0 +1,163 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_init_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__q31_8c.html
new file mode 100644
index 000000000..91105d2ad
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_pid_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_pid_init_q31 (arm_pid_instance_q31 *S, int32_t resetStateFlag)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__q31_8c_source.html
new file mode 100644
index 000000000..abd1ce76a
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__q31_8c_source.html
@@ -0,0 +1,148 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_init_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__f32_8c.html
new file mode 100644
index 000000000..99c811298
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_reset_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_pid_reset_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_pid_reset_f32 (arm_pid_instance_f32 *S)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__f32_8c_source.html
new file mode 100644
index 000000000..f499a1365
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__f32_8c_source.html
@@ -0,0 +1,112 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_reset_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__q15_8c.html
new file mode 100644
index 000000000..20d303922
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_reset_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_pid_reset_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_pid_reset_q15 (arm_pid_instance_q15 *S)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__q15_8c_source.html
new file mode 100644
index 000000000..333448d45
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__q15_8c_source.html
@@ -0,0 +1,111 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_reset_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__q31_8c.html
new file mode 100644
index 000000000..399b1afdb
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_reset_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_pid_reset_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_pid_reset_q31 (arm_pid_instance_q31 *S)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__q31_8c_source.html
new file mode 100644
index 000000000..944673608
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__q31_8c_source.html
@@ -0,0 +1,112 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_reset_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__power__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__power__f32_8c.html
new file mode 100644
index 000000000..59073bbd4
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__power__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_power_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_power_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_power_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__power__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__power__f32_8c_source.html
new file mode 100644
index 000000000..2e36246e1
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__power__f32_8c_source.html
@@ -0,0 +1,172 @@
+
+
+
+
+CMSIS DSP Software Library: arm_power_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__power__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__power__q15_8c.html
new file mode 100644
index 000000000..14628a15f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__power__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_power_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_power_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_power_q15 (q15_t *pSrc, uint32_t blockSize, q63_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__power__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__power__q15_8c_source.html
new file mode 100644
index 000000000..89bc7515a
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__power__q15_8c_source.html
@@ -0,0 +1,181 @@
+
+
+
+
+CMSIS DSP Software Library: arm_power_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__power__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__power__q31_8c.html
new file mode 100644
index 000000000..9e8f09453
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__power__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_power_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_power_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_power_q31 (q31_t *pSrc, uint32_t blockSize, q63_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__power__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__power__q31_8c_source.html
new file mode 100644
index 000000000..1bf163856
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__power__q31_8c_source.html
@@ -0,0 +1,171 @@
+
+
+
+
+CMSIS DSP Software Library: arm_power_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__power__q7_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__power__q7_8c.html
new file mode 100644
index 000000000..e402b5ed2
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__power__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_power_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_power_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_power_q7 (q7_t *pSrc, uint32_t blockSize, q31_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__power__q7_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__power__q7_8c_source.html
new file mode 100644
index 000000000..62f6e0742
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__power__q7_8c_source.html
@@ -0,0 +1,177 @@
+
+
+
+
+CMSIS DSP Software Library: arm_power_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__float_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__float_8c.html
new file mode 100644
index 000000000..f0630f83e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__float_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q15_to_float.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_q15_to_float.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_q15_to_float (q15_t *pSrc, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__float_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__float_8c_source.html
new file mode 100644
index 000000000..861b56be2
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__float_8c_source.html
@@ -0,0 +1,159 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q15_to_float.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__q31_8c.html
new file mode 100644
index 000000000..d629350cf
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q15_to_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_q15_to_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_q15_to_q31 (q15_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__q31_8c_source.html
new file mode 100644
index 000000000..cc51fface
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__q31_8c_source.html
@@ -0,0 +1,159 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q15_to_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__q7_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__q7_8c.html
new file mode 100644
index 000000000..eeff234ba
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q15_to_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_q15_to_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_q15_to_q7 (q15_t *pSrc, q7_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__q7_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__q7_8c_source.html
new file mode 100644
index 000000000..3d32865b6
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__q7_8c_source.html
@@ -0,0 +1,159 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q15_to_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__float_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__float_8c.html
new file mode 100644
index 000000000..83104ea81
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__float_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q31_to_float.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_q31_to_float.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_q31_to_float (q31_t *pSrc, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__float_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__float_8c_source.html
new file mode 100644
index 000000000..4377b564f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__float_8c_source.html
@@ -0,0 +1,159 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q31_to_float.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__q15_8c.html
new file mode 100644
index 000000000..15d1d1821
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q31_to_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_q31_to_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_q31_to_q15 (q31_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__q15_8c_source.html
new file mode 100644
index 000000000..7c717aa9f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__q15_8c_source.html
@@ -0,0 +1,159 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q31_to_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__q7_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__q7_8c.html
new file mode 100644
index 000000000..6bc04e71f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q31_to_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_q31_to_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_q31_to_q7 (q31_t *pSrc, q7_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__q7_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__q7_8c_source.html
new file mode 100644
index 000000000..123304a98
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__q7_8c_source.html
@@ -0,0 +1,159 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q31_to_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__float_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__float_8c.html
new file mode 100644
index 000000000..cdecd2284
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__float_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q7_to_float.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_q7_to_float.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_q7_to_float (q7_t *pSrc, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__float_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__float_8c_source.html
new file mode 100644
index 000000000..c1a91ebbc
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__float_8c_source.html
@@ -0,0 +1,159 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q7_to_float.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__q15_8c.html
new file mode 100644
index 000000000..751852790
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q7_to_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_q7_to_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_q7_to_q15 (q7_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__q15_8c_source.html
new file mode 100644
index 000000000..6cad6a62d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__q15_8c_source.html
@@ -0,0 +1,159 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q7_to_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__q31_8c.html
new file mode 100644
index 000000000..39c1986e8
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q7_to_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_q7_to_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_q7_to_q31 (q7_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__q31_8c_source.html
new file mode 100644
index 000000000..991a96e35
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__q31_8c_source.html
@@ -0,0 +1,159 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q7_to_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__f32_8c.html
new file mode 100644
index 000000000..75be7ae2c
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__f32_8c.html
@@ -0,0 +1,221 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_rfft_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+

+Functions
void arm_split_rfft_f32 (float32_t *pSrc, uint32_t fftLen, float32_t *pATable, float32_t *pBTable, float32_t *pDst, uint32_t modifier)
void arm_split_rifft_f32 (float32_t *pSrc, uint32_t fftLen, float32_t *pATable, float32_t *pBTable, float32_t *pDst, uint32_t modifier)
void arm_rfft_f32 (const arm_rfft_instance_f32 *S, float32_t *pSrc, float32_t *pDst)

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_split_rfft_f32 (float32_t *  pSrc, 
uint32_t  fftLen, 
float32_t *  pATable, 
float32_t *  pBTable, 
float32_t *  pDst, 
uint32_t  modifier 
)

+

+

+
+
Core Real FFT process. 

+
end of RFFT_RIFFT group 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer. 
[in]fftLenlength of FFT. 
[in]*pATablepoints to the twiddle Coef A buffer. 
[in]*pBTablepoints to the twiddle Coef B buffer. 
[out]*pDstpoints to the output buffer. 
[in]modifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 218 of file arm_rfft_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_split_rifft_f32 (float32_t *  pSrc, 
uint32_t  fftLen, 
float32_t *  pATable, 
float32_t *  pBTable, 
float32_t *  pDst, 
uint32_t  modifier 
)

+

+

+
+
Core Real IFFT process. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer. 
[in]fftLenlength of FFT. 
[in]*pATablepoints to the twiddle Coef A buffer. 
[in]*pBTablepoints to the twiddle Coef B buffer. 
[out]*pDstpoints to the output buffer. 
[in]modifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 316 of file arm_rfft_f32.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__f32_8c_source.html
new file mode 100644
index 000000000..ffd922b02
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@@ -0,0 +1,334 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__f32_8c.html
new file mode 100644
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--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__f32_8c.html
@@ -0,0 +1,88 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_rfft_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+

+Functions
arm_status arm_rfft_init_f32 (arm_rfft_instance_f32 *S, arm_cfft_radix4_instance_f32 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)

+Variables
static const float32_t realCoefA [2048]
static const float32_t realCoefB [2048]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__f32_8c_source.html
new file mode 100644
index 000000000..ebb0ad6ee
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__f32_8c_source.html
@@ -0,0 +1,1720 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_init_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__q15_8c.html
new file mode 100644
index 000000000..bbdf7e7f0
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__q15_8c.html
@@ -0,0 +1,88 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_rfft_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+

+Functions
arm_status arm_rfft_init_q15 (arm_rfft_instance_q15 *S, arm_cfft_radix4_instance_q15 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)

+Variables
static const q15_t realCoefAQ15 [2048]
static const q15_t realCoefBQ15 [2048]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__q15_8c_source.html
new file mode 100644
index 000000000..db98a1f11
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__q15_8c_source.html
@@ -0,0 +1,693 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_init_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__q31_8c.html
new file mode 100644
index 000000000..2d6216db1
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__q31_8c.html
@@ -0,0 +1,88 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_rfft_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+

+Functions
arm_status arm_rfft_init_q31 (arm_rfft_instance_q31 *S, arm_cfft_radix4_instance_q31 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)

+Variables
const q31_t realCoefAQ31 [1024]
const q31_t realCoefBQ31 [1024]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__q31_8c_source.html
new file mode 100644
index 000000000..4191d96b0
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__q31_8c_source.html
@@ -0,0 +1,688 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_init_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__q15_8c.html
new file mode 100644
index 000000000..9b4d72765
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__q15_8c.html
@@ -0,0 +1,221 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_rfft_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+

+Functions
void arm_split_rfft_q15 (q15_t *pSrc, uint32_t fftLen, q15_t *pATable, q15_t *pBTable, q15_t *pDst, uint32_t modifier)
void arm_split_rifft_q15 (q15_t *pSrc, uint32_t fftLen, q15_t *pATable, q15_t *pBTable, q15_t *pDst, uint32_t modifier)
void arm_rfft_q15 (const arm_rfft_instance_q15 *S, q15_t *pSrc, q15_t *pDst)

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+        
+        
+          
+          
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+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_split_rfft_q15 (q15_t *  pSrc, 
uint32_t  fftLen, 
q15_t *  pATable, 
q15_t *  pBTable, 
q15_t *  pDst, 
uint32_t  modifier 
)

+

+

+
+
Core Real FFT process. 

+
end of RFFT_RIFFT group 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
*pSrcpoints to the input buffer. 
fftLenlength of FFT. 
*pATablepoints to the A twiddle Coef buffer. 
*pBTablepoints to the B twiddle Coef buffer. 
*pDstpoints to the output buffer. 
modifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. The function implements a Real FFT 

+
+
Definition at line 143 of file arm_rfft_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
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+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_split_rifft_q15 (q15_t *  pSrc, 
uint32_t  fftLen, 
q15_t *  pATable, 
q15_t *  pBTable, 
q15_t *  pDst, 
uint32_t  modifier 
)

+

+

+
+
Core Real IFFT process. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer. 
[in]fftLenlength of FFT. 
[in]*pATablepoints to the twiddle Coef A buffer. 
[in]*pBTablepoints to the twiddle Coef B buffer. 
[out]*pDstpoints to the output buffer. 
[in]modifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. The function implements a Real IFFT 

+
+
Definition at line 312 of file arm_rfft_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__q15_8c_source.html
new file mode 100644
index 000000000..02fd37aed
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__q15_8c_source.html
@@ -0,0 +1,480 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__q31_8c.html
new file mode 100644
index 000000000..7fb5a637c
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__q31_8c.html
@@ -0,0 +1,221 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_rfft_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+

+Functions
void arm_split_rfft_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pATable, q31_t *pBTable, q31_t *pDst, uint32_t modifier)
void arm_split_rifft_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pATable, q31_t *pBTable, q31_t *pDst, uint32_t modifier)
void arm_rfft_q31 (const arm_rfft_instance_q31 *S, q31_t *pSrc, q31_t *pDst)

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_split_rfft_q31 (q31_t *  pSrc, 
uint32_t  fftLen, 
q31_t *  pATable, 
q31_t *  pBTable, 
q31_t *  pDst, 
uint32_t  modifier 
)

+

+

+
+
Core Real FFT process. 

+
end of RFFT_RIFFT group 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer. 
[in]fftLenlength of FFT. 
[in]*pATablepoints to the twiddle Coef A buffer. 
[in]*pBTablepoints to the twiddle Coef B buffer. 
[out]*pDstpoints to the output buffer. 
[in]modifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 143 of file arm_rfft_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_split_rifft_q31 (q31_t *  pSrc, 
uint32_t  fftLen, 
q31_t *  pATable, 
q31_t *  pBTable, 
q31_t *  pDst, 
uint32_t  modifier 
)

+

+

+
+
Core Real IFFT process. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer. 
[in]fftLenlength of FFT. 
[in]*pATablepoints to the twiddle Coef A buffer. 
[in]*pBTablepoints to the twiddle Coef B buffer. 
[out]*pDstpoints to the output buffer. 
[in]modifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 249 of file arm_rfft_q31.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rfft__q31_8c_source.html
new file mode 100644
index 000000000..a80f27dde
--- /dev/null
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@@ -0,0 +1,349 @@
+
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+
+CMSIS DSP Software Library: arm_rfft_q31.c Source File
+
+
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+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rms__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rms__f32_8c.html
new file mode 100644
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--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rms__f32_8c.html
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+
+
+
+
+CMSIS DSP Software Library: arm_rms_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_rms_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_rms_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rms__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rms__f32_8c_source.html
new file mode 100644
index 000000000..ba6472623
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rms__f32_8c_source.html
@@ -0,0 +1,167 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rms_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rms__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rms__q15_8c.html
new file mode 100644
index 000000000..21db5111d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rms__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rms_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_rms_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_rms_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rms__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rms__q15_8c_source.html
new file mode 100644
index 000000000..ca4320247
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rms__q15_8c_source.html
@@ -0,0 +1,193 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rms_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rms__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rms__q31_8c.html
new file mode 100644
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--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rms__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rms_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_rms_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_rms_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rms__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rms__q31_8c_source.html
new file mode 100644
index 000000000..466bc8de6
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__rms__q31_8c_source.html
@@ -0,0 +1,183 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rms_q31.c Source File
+
+
+
+
+
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+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__scale__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__scale__f32_8c.html
new file mode 100644
index 000000000..81fdf6650
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__scale__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_scale_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_scale_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_scale_f32 (float32_t *pSrc, float32_t scale, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__scale__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__scale__f32_8c_source.html
new file mode 100644
index 000000000..0b690fcf5
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__scale__f32_8c_source.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_scale_f32.c Source File
+
+
+
+
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+
+
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+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__scale__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__scale__q15_8c.html
new file mode 100644
index 000000000..82e730a0d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__scale__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_scale_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_scale_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_scale_q15 (q15_t *pSrc, q15_t scaleFract, int8_t shift, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__scale__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__scale__q15_8c_source.html
new file mode 100644
index 000000000..87057c1ac
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__scale__q15_8c_source.html
@@ -0,0 +1,207 @@
+
+
+
+
+CMSIS DSP Software Library: arm_scale_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__scale__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__scale__q31_8c.html
new file mode 100644
index 000000000..0d981fe1d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__scale__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_scale_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_scale_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_scale_q31 (q31_t *pSrc, q31_t scaleFract, int8_t shift, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__scale__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__scale__q31_8c_source.html
new file mode 100644
index 000000000..ee8e195b5
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__scale__q31_8c_source.html
@@ -0,0 +1,163 @@
+
+
+
+
+CMSIS DSP Software Library: arm_scale_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__scale__q7_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__scale__q7_8c.html
new file mode 100644
index 000000000..3a83c8078
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__scale__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_scale_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_scale_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_scale_q7 (q7_t *pSrc, q7_t scaleFract, int8_t shift, q7_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__scale__q7_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__scale__q7_8c_source.html
new file mode 100644
index 000000000..cfcb293fa
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__scale__q7_8c_source.html
@@ -0,0 +1,187 @@
+
+
+
+
+CMSIS DSP Software Library: arm_scale_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__shift__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__shift__q15_8c.html
new file mode 100644
index 000000000..0d8998705
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__shift__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_shift_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_shift_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_shift_q15 (q15_t *pSrc, int8_t shiftBits, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__shift__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__shift__q15_8c_source.html
new file mode 100644
index 000000000..276dd7ac9
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__shift__q15_8c_source.html
@@ -0,0 +1,286 @@
+
+
+
+
+CMSIS DSP Software Library: arm_shift_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__shift__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__shift__q31_8c.html
new file mode 100644
index 000000000..741ee906b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__shift__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_shift_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_shift_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_shift_q31 (q31_t *pSrc, int8_t shiftBits, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__shift__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__shift__q31_8c_source.html
new file mode 100644
index 000000000..0367f45ff
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__shift__q31_8c_source.html
@@ -0,0 +1,173 @@
+
+
+
+
+CMSIS DSP Software Library: arm_shift_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__shift__q7_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__shift__q7_8c.html
new file mode 100644
index 000000000..8d864b910
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__shift__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_shift_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_shift_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_shift_q7 (q7_t *pSrc, int8_t shiftBits, q7_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__shift__q7_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__shift__q7_8c_source.html
new file mode 100644
index 000000000..343e4a415
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__shift__q7_8c_source.html
@@ -0,0 +1,248 @@
+
+
+
+
+CMSIS DSP Software Library: arm_shift_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__signal__converge__example__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__signal__converge__example__f32_8c.html
new file mode 100644
index 000000000..e7ec791dd
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__signal__converge__example__f32_8c.html
@@ -0,0 +1,511 @@
+
+
+
+
+CMSIS DSP Software Library: arm_signal_converge_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Defines |
+Functions |
+Variables  

+  

+
arm_signal_converge_example_f32.c File Reference
  

+

+

+#include "arm_math.h"

+#include "math_helper.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define TEST_LENGTH_SAMPLES   1536
#define NUMTAPS   32
#define BLOCKSIZE   32
#define DELTA_ERROR   0.000001f
#define DELTA_COEFF   0.0001f
#define MU   0.5f
#define NUMFRAMES   (TEST_LENGTH_SAMPLES / BLOCKSIZE)

+Functions
arm_status test_signal_converge_example (void)
arm_status test_signal_converge (float32_t *err_signal, uint32_t blockSize)
void getinput (float32_t *input, uint32_t fr_cnt, uint32_t blockSize)
int32_t main (void)

+Variables
float32_t firStateF32 [NUMTAPS+BLOCKSIZE]
arm_fir_instance_f32 LPF_instance
float32_t lmsStateF32 [NUMTAPS+BLOCKSIZE]
float32_t errOutput [TEST_LENGTH_SAMPLES]
arm_lms_norm_instance_f32 lmsNorm_instance
float32_t testInput_f32 [TEST_LENGTH_SAMPLES]
float32_t lmsNormCoeff_f32 [32]
const float32_t FIRCoeff_f32 [32]
float32_t wire1 [BLOCKSIZE]
float32_t wire2 [BLOCKSIZE]
float32_t wire3 [BLOCKSIZE]
float32_t err_signal [BLOCKSIZE]

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define TEST_LENGTH_SAMPLES   1536

+

+

+
+
Definition at line 100 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define NUMTAPS   32

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Definition at line 101 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define BLOCKSIZE   32

+

+

+
+
Definition at line 102 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define DELTA_ERROR   0.000001f

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Definition at line 103 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define DELTA_COEFF   0.0001f

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Definition at line 104 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define MU   0.5f

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Definition at line 105 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define NUMFRAMES   (TEST_LENGTH_SAMPLES / BLOCKSIZE)

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Definition at line 107 of file arm_signal_converge_example_f32.c.

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
arm_status test_signal_converge_example (void  )

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status test_signal_converge (float32_t *  err_signal, 
uint32_t  blockSize 
)

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void getinput (float32_t *  input, 
uint32_t  fr_cnt, 
uint32_t  blockSize 
)

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void  )

+

+

+
+
Definition at line 163 of file arm_signal_converge_example_f32.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t firStateF32[NUMTAPS+BLOCKSIZE]

+

+

+
Examples: 
arm_fir_example_f32.c, and arm_signal_converge_example_f32.c.

+

+
Definition at line 113 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_fir_instance_f32 LPF_instance

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Definition at line 114 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t lmsStateF32[NUMTAPS+BLOCKSIZE]

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Definition at line 120 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t errOutput[TEST_LENGTH_SAMPLES]

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Definition at line 121 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_lms_norm_instance_f32 lmsNorm_instance

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Definition at line 122 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testInput_f32[TEST_LENGTH_SAMPLES]

+

+

+
+
Definition at line 83 of file arm_sin_cos_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t lmsNormCoeff_f32[32]

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t FIRCoeff_f32[32]

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+

+

+
+

+

+      
+        
+          
+        
+      
float32_t wire1[BLOCKSIZE]

+

+

+
Examples: 
arm_signal_converge_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 154 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t wire2[BLOCKSIZE]

+

+

+
Examples: 
arm_signal_converge_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 155 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t wire3[BLOCKSIZE]

+

+

+
Examples: 
arm_signal_converge_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 156 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t err_signal[BLOCKSIZE]

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Definition at line 157 of file arm_signal_converge_example_f32.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__signal__converge__example__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__signal__converge__example__f32_8c_source.html
new file mode 100644
index 000000000..8a552925d
--- /dev/null
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@@ -0,0 +1,246 @@
+
+
+
+
+CMSIS DSP Software Library: arm_signal_converge_example_f32.c Source File
+
+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__example__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__example__f32_8c.html
new file mode 100644
index 000000000..02c93c0d7
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__example__f32_8c.html
@@ -0,0 +1,301 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sin_cos_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Defines |
+Functions |
+Variables  

+  

+
arm_sin_cos_example_f32.c File Reference
  

+

+

+#include <math.h>

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define MAX_BLOCKSIZE   32
#define DELTA   (0.000001f)

+Functions
int32_t main (void)

+Variables
const float32_t testInput_f32 [MAX_BLOCKSIZE]
const float32_t testRefOutput_f32 = 1.000000000
uint32_t blockSize = 32
float32_t testOutput
float32_t cosOutput
float32_t sinOutput
float32_t cosSquareOutput
float32_t sinSquareOutput
arm_status status

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define MAX_BLOCKSIZE   32

+

+

+
+
Definition at line 74 of file arm_sin_cos_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define DELTA   (0.000001f)

+

+

+
+
Definition at line 75 of file arm_sin_cos_example_f32.c.

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void  )

+

+

+
+
Definition at line 111 of file arm_sin_cos_example_f32.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float32_t testInput_f32[MAX_BLOCKSIZE]

+

+

+Initial value:
  
+{    
+    -1.244916875853235400,  -4.793533929171324800,  0.360705030233248850,   0.827929644170887320,   -3.299532218312426900,  3.427441903227623800,   3.422401784294607700,   -0.108308165334010680,   
+    0.941943896490312180,   0.502609575000365850,   -0.537345278736373500,  2.088817392965764500,   -1.693168684143455700,  6.283185307179590700,   -0.392545884746175080,  0.327893095115825040,    
+    3.070147440456292300,   0.170611405884662230,   -0.275275082396073010,  -2.395492805446796300,  0.847311163536506600,   -3.845517018083148800,  2.055818378415868300,   4.672594161978930800,    
+    -1.990923030266425800,  2.469305197656249500,   3.609002606064021000,   -4.586736582331667500,  -4.147080139136136300,  1.643756718868359500,   -1.150866392366494800,  1.985805026477433800 
+ 
+ 
+}
+

+
Definition at line 83 of file arm_sin_cos_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t testRefOutput_f32 = 1.000000000

+

+

+
+
Definition at line 93 of file arm_sin_cos_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t blockSize = 32

+

+

+
+
Definition at line 98 of file arm_sin_cos_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testOutput

+

+

+
+
Definition at line 99 of file arm_sin_cos_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t cosOutput

+

+

+
Examples: 
arm_sin_cos_example_f32.c.

+

+
Definition at line 100 of file arm_sin_cos_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t sinOutput

+

+

+
Examples: 
arm_sin_cos_example_f32.c.

+

+
Definition at line 101 of file arm_sin_cos_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t cosSquareOutput

+

+

+
Examples: 
arm_sin_cos_example_f32.c.

+

+
Definition at line 102 of file arm_sin_cos_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t sinSquareOutput

+

+

+
Examples: 
arm_sin_cos_example_f32.c.

+

+
Definition at line 103 of file arm_sin_cos_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_status status

+

+

+
+
Definition at line 109 of file arm_sin_cos_example_f32.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__example__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__example__f32_8c_source.html
new file mode 100644
index 000000000..75e7e6e2d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__example__f32_8c_source.html
@@ -0,0 +1,172 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sin_cos_example_f32.c Source File
+
+
+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__f32_8c.html
new file mode 100644
index 000000000..fa0eb7212
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__f32_8c.html
@@ -0,0 +1,88 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sin_cos_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_sin_cos_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+

+Functions
void arm_sin_cos_f32 (float32_t theta, float32_t *pSinVal, float32_t *pCosVal)

+Variables
static const float32_t cosTable [360]
static const float32_t sinTable [360]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__f32_8c_source.html
new file mode 100644
index 000000000..1100a56ba
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__f32_8c_source.html
@@ -0,0 +1,420 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sin_cos_f32.c Source File
+
+
+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__q31_8c.html
new file mode 100644
index 000000000..9843fc011
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__q31_8c.html
@@ -0,0 +1,88 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sin_cos_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_sin_cos_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+

+Functions
void arm_sin_cos_q31 (q31_t theta, q31_t *pSinVal, q31_t *pCosVal)

+Variables
static const int32_t sinTableQ31 [360]
static const int32_t cosTableQ31 [360]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__q31_8c_source.html
new file mode 100644
index 000000000..43f81351a
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__q31_8c_source.html
@@ -0,0 +1,340 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sin_cos_q31.c Source File
+
+
+
+
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+
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+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__f32_8c.html
new file mode 100644
index 000000000..b6ec0dbd4
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__f32_8c.html
@@ -0,0 +1,87 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sin_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_sin_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+

+Functions
float32_t arm_sin_f32 (float32_t x)

+Variables
static const float32_t sinTable [259]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__f32_8c_source.html
new file mode 100644
index 000000000..0d93ef7f1
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__f32_8c_source.html
@@ -0,0 +1,265 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sin_f32.c Source File
+
+
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+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__q15_8c.html
new file mode 100644
index 000000000..283a8e581
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__q15_8c.html
@@ -0,0 +1,87 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sin_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_sin_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+

+Functions
q15_t arm_sin_q15 (q15_t x)

+Variables
static const q15_t sinTableQ15 [259]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__q15_8c_source.html
new file mode 100644
index 000000000..9ac80e073
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__q15_8c_source.html
@@ -0,0 +1,225 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sin_q15.c Source File
+
+
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+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__q31_8c.html
new file mode 100644
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--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__q31_8c.html
@@ -0,0 +1,87 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sin_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_sin_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+

+Functions
q31_t arm_sin_q31 (q31_t x)

+Variables
static const q31_t sinTableQ31 [259]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__q31_8c_source.html
new file mode 100644
index 000000000..c33376ab8
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sin__q31_8c_source.html
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+
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+
+CMSIS DSP Software Library: arm_sin_q31.c Source File
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+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sqrt__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sqrt__q15_8c.html
new file mode 100644
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--- /dev/null
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+
+
+
+
+CMSIS DSP Software Library: arm_sqrt_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_sqrt_q15.c File Reference
  

+

+

+#include "arm_math.h"

+#include "arm_common_tables.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_sqrt_q15 (q15_t in, q15_t *pOut)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sqrt__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sqrt__q15_8c_source.html
new file mode 100644
index 000000000..f126b141e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sqrt__q15_8c_source.html
@@ -0,0 +1,231 @@
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+CMSIS DSP Software Library: arm_sqrt_q15.c Source File
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+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sqrt__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sqrt__q31_8c.html
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--- /dev/null
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+
+
+
+
+CMSIS DSP Software Library: arm_sqrt_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_sqrt_q31.c File Reference
  

+

+

+#include "arm_math.h"

+#include "arm_common_tables.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_sqrt_q31 (q31_t in, q31_t *pOut)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sqrt__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sqrt__q31_8c_source.html
new file mode 100644
index 000000000..0ab402062
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sqrt__q31_8c_source.html
@@ -0,0 +1,252 @@
+
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+
+
+CMSIS DSP Software Library: arm_sqrt_q31.c Source File
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+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__std__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__std__f32_8c.html
new file mode 100644
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--- /dev/null
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+
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+
+
+CMSIS DSP Software Library: arm_std_f32.c File Reference
+
+
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+
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+
+
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+
+

+  

+Functions  

+  

+
arm_std_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_std_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__std__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__std__f32_8c_source.html
new file mode 100644
index 000000000..ed803ccfb
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__std__f32_8c_source.html
@@ -0,0 +1,255 @@
+
+
+
+
+CMSIS DSP Software Library: arm_std_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__std__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__std__q15_8c.html
new file mode 100644
index 000000000..96695992a
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__std__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_std_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_std_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_std_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__std__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__std__q15_8c_source.html
new file mode 100644
index 000000000..c6a6e5442
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__std__q15_8c_source.html
@@ -0,0 +1,269 @@
+
+
+
+
+CMSIS DSP Software Library: arm_std_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__std__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__std__q31_8c.html
new file mode 100644
index 000000000..b988fbb29
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__std__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_std_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_std_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_std_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__std__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__std__q31_8c_source.html
new file mode 100644
index 000000000..d8b7665f4
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__std__q31_8c_source.html
@@ -0,0 +1,255 @@
+
+
+
+
+CMSIS DSP Software Library: arm_std_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sub__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sub__f32_8c.html
new file mode 100644
index 000000000..ddd54ddd5
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sub__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sub_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_sub_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_sub_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sub__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sub__f32_8c_source.html
new file mode 100644
index 000000000..eaa168348
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sub__f32_8c_source.html
@@ -0,0 +1,161 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sub_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sub__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sub__q15_8c.html
new file mode 100644
index 000000000..a21d71163
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sub__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sub_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_sub_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_sub_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sub__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sub__q15_8c_source.html
new file mode 100644
index 000000000..a86898595
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sub__q15_8c_source.html
@@ -0,0 +1,171 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sub_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sub__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sub__q31_8c.html
new file mode 100644
index 000000000..5eb6a74dc
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sub__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sub_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_sub_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_sub_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sub__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sub__q31_8c_source.html
new file mode 100644
index 000000000..942eaf97d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sub__q31_8c_source.html
@@ -0,0 +1,172 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sub_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sub__q7_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sub__q7_8c.html
new file mode 100644
index 000000000..65b05025b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sub__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sub_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_sub_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_sub_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sub__q7_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sub__q7_8c_source.html
new file mode 100644
index 000000000..5ea204404
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__sub__q7_8c_source.html
@@ -0,0 +1,170 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sub_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__var__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__var__f32_8c.html
new file mode 100644
index 000000000..083bb9343
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__var__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_var_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_var_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_var_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__var__f32_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__var__f32_8c_source.html
new file mode 100644
index 000000000..08728629d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__var__f32_8c_source.html
@@ -0,0 +1,252 @@
+
+
+
+
+CMSIS DSP Software Library: arm_var_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__var__q15_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__var__q15_8c.html
new file mode 100644
index 000000000..82ffd6a4a
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__var__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_var_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_var_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_var_q15 (q15_t *pSrc, uint32_t blockSize, q31_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__var__q15_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__var__q15_8c_source.html
new file mode 100644
index 000000000..b31c09667
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__var__q15_8c_source.html
@@ -0,0 +1,252 @@
+
+
+
+
+CMSIS DSP Software Library: arm_var_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__var__q31_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__var__q31_8c.html
new file mode 100644
index 000000000..1dd506ba7
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__var__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_var_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_var_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_var_q31 (q31_t *pSrc, uint32_t blockSize, q63_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__var__q31_8c_source.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__var__q31_8c_source.html
new file mode 100644
index 000000000..de68b857c
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__var__q31_8c_source.html
@@ -0,0 +1,252 @@
+
+
+
+
+CMSIS DSP Software Library: arm_var_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__variance__example__f32_8c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__variance__example__f32_8c.html
new file mode 100644
index 000000000..beead8f9f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm__variance__example__f32_8c.html
@@ -0,0 +1,253 @@
+
+
+
+
+CMSIS DSP Software Library: arm_variance_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Defines |
+Functions |
+Variables  

+  

+
arm_variance_example_f32.c File Reference
  

+

+

+#include <math.h>

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define MAX_BLOCKSIZE   32
#define DELTA   (0.000001f)

+Functions
int32_t main (void)

+Variables
float32_t wire1 [MAX_BLOCKSIZE]
float32_t wire2 [MAX_BLOCKSIZE]
float32_t wire3 [MAX_BLOCKSIZE]
float32_t testInput_f32 [32]
uint32_t blockSize = 32
float32_t refVarianceOut = 0.903941793931839

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define MAX_BLOCKSIZE   32

+

+

+
+
Definition at line 83 of file arm_variance_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define DELTA   (0.000001f)

+

+

+
+
Definition at line 84 of file arm_variance_example_f32.c.

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void  )

+

+

+
+
Definition at line 122 of file arm_variance_example_f32.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t wire1[MAX_BLOCKSIZE]

+

+

+
+
Definition at line 90 of file arm_variance_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t wire2[MAX_BLOCKSIZE]

+

+

+
+
Definition at line 91 of file arm_variance_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t wire3[MAX_BLOCKSIZE]

+

+

+
+
Definition at line 92 of file arm_variance_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testInput_f32[32]

+

+

+Initial value:
 
+{ 
+-0.432564811528221,     -1.665584378238097,     0.125332306474831,      0.287676420358549,  
+-1.146471350681464,     1.190915465642999,      1.189164201652103,      -0.037633276593318,     
+0.327292361408654,      0.174639142820925,      -0.186708577681439,     0.725790548293303,  
+-0.588316543014189,     2.183185818197101,      -0.136395883086596,     0.113931313520810,  
+1.066768211359189,      0.059281460523605,      -0.095648405483669,     -0.832349463650022,     
+0.294410816392640,      -1.336181857937804,     0.714324551818952,      1.623562064446271,  
+-0.691775701702287,     0.857996672828263,      1.254001421602532,      -1.593729576447477,     
+-1.440964431901020,     0.571147623658178,      -0.399885577715363,     0.689997375464345
+  
+}
+

+
Definition at line 99 of file arm_variance_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t blockSize = 32

+

+

+
+
Definition at line 115 of file arm_variance_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t refVarianceOut = 0.903941793931839

+

+

+
Examples: 
arm_variance_example_f32.c.

+

+
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+CMSIS DSP Software Library: arm_variance_example_f32.c Source File
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+CMSIS DSP Software Library: arm_class_marks_example_f32.c
+
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+

+  

+
arm_class_marks_example_f32.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision:    V1.0.3 
+*  
+* Project:      CMSIS DSP Library  
+* Title:        arm_class_marks_example_f32.c         
+*  
+* Description:  Example code to calculate Minimum, Maximum 
+*               Mean, std and variance of marks obtained in a class 
+* 
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+*  
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+#include "arm_math.h" 
+ 
+#define USE_STATIC_INIT 
+ 
+ /* ---------------------------------------------------------------------- 
+** Global defines  
+** ------------------------------------------------------------------- */ 
+ 
+#define TEST_LENGTH_SAMPLES     (20*4) 
+ 
+/* ---------------------------------------------------------------------- 
+** List of Marks scored by 20 students for 4 subjects 
+** ------------------------------------------------------------------- */  
+const float32_t testMarks_f32[TEST_LENGTH_SAMPLES] =  
+{    
+    42.000000,  37.000000,  81.000000,  28.000000,   
+    83.000000,  72.000000,  36.000000,  38.000000,   
+    32.000000,  51.000000,  63.000000,  64.000000,   
+    97.000000,  82.000000,  95.000000,  90.000000,   
+    66.000000,  51.000000,  54.000000,  42.000000,   
+    67.000000,  56.000000,  45.000000,  57.000000,   
+    67.000000,  69.000000,  35.000000,  52.000000,   
+    29.000000,  81.000000,  58.000000,  47.000000,   
+    38.000000,  76.000000,  100.000000, 29.000000,   
+    33.000000,  47.000000,  29.000000,  50.000000,   
+    34.000000,  41.000000,  61.000000,  46.000000,   
+    52.000000,  50.000000,  48.000000,  36.000000,   
+    47.000000,  55.000000,  44.000000,  40.000000,   
+    100.000000, 94.000000,  84.000000,  37.000000,   
+    32.000000,  71.000000,  47.000000,  77.000000,   
+    31.000000,  50.000000,  49.000000,  35.000000,   
+    63.000000,  67.000000,  40.000000,  31.000000,   
+    29.000000,  68.000000,  61.000000,  38.000000,   
+    31.000000,  28.000000,  28.000000,  76.000000,   
+    55.000000,  33.000000,  29.000000,  39.000000 
+};  
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Number of subjects X 1  
+* ------------------------------------------------------------------- */  
+const float32_t testUnity_f32[4] =  
+{    
+    1.000,  1.000,  1.000,  1.000 
+}; 
+ 
+ 
+/* ---------------------------------------------------------------------- 
+** f32 Output buffer 
+** ------------------------------------------------------------------- */  
+static float32_t testOutput[TEST_LENGTH_SAMPLES]; 
+ 
+ 
+/* ------------------------------------------------------------------ 
+* Global defines  
+*------------------------------------------------------------------- */ 
+#define     NUMSTUDENTS  20 
+#define     NUMSUBJECTS  4 
+ 
+/* ------------------------------------------------------------------ 
+* Global variables  
+*------------------------------------------------------------------- */ 
+ 
+uint32_t    numStudents = 20; 
+uint32_t    numSubjects = 4;  
+float32_t   max_marks, min_marks, mean, std, var; 
+uint32_t    student_num;    
+ 
+/* ---------------------------------------------------------------------------------- 
+* Main f32 test function.  It returns maximum marks secured and student number 
+* ------------------------------------------------------------------------------- */ 
+ 
+int32_t main() 
+{ 
+ 
+#ifndef  USE_STATIC_INIT 
+ 
+    arm_matrix_instance_f32 srcA; 
+    arm_matrix_instance_f32 srcB; 
+    arm_matrix_instance_f32 dstC;  
+ 
+    /* Input and output matrices initializations */  
+    arm_mat_init_f32(&srcA, numStudents, numSubjects, (float32_t *)testMarks_f32);  
+    arm_mat_init_f32(&srcB, numSubjects, 1, (float32_t *)testUnity_f32);  
+    arm_mat_init_f32(&dstC, numStudents, 1, testOutput);  
+ 
+#else 
+ 
+    /* Static Initializations of Input and output matrix sizes and array */ 
+    arm_matrix_instance_f32 srcA = {NUMSTUDENTS, NUMSUBJECTS, (float32_t *)testMarks_f32}; 
+    arm_matrix_instance_f32 srcB = {NUMSUBJECTS, 1, (float32_t *)testUnity_f32}; 
+    arm_matrix_instance_f32 dstC = {NUMSTUDENTS, 1, testOutput}; 
+ 
+#endif 
+ 
+     
+    /* ---------------------------------------------------------------------- 
+    *Call the Matrix multiplication process function   
+    * ------------------------------------------------------------------- */ 
+    arm_mat_mult_f32(&srcA, &srcB, &dstC); 
+     
+    /* ---------------------------------------------------------------------- 
+    ** Call the Max function to calculate max marks among numStudents 
+    ** ------------------------------------------------------------------- */ 
+    arm_max_f32(testOutput, numStudents, &max_marks, &student_num);  
+ 
+    /* ---------------------------------------------------------------------- 
+    ** Call the Min function to calculate min marks among numStudents 
+    ** ------------------------------------------------------------------- */ 
+    arm_min_f32(testOutput, numStudents, &min_marks, &student_num);  
+ 
+    /* ---------------------------------------------------------------------- 
+    ** Call the Mean function to calculate mean 
+    ** ------------------------------------------------------------------- */ 
+    arm_mean_f32(testOutput, numStudents, &mean); 
+ 
+    /* ---------------------------------------------------------------------- 
+    ** Call the std function to calculate standard deviation 
+    ** ------------------------------------------------------------------- */ 
+    arm_std_f32(testOutput, numStudents, &std); 
+ 
+    /* ---------------------------------------------------------------------- 
+    ** Call the var function to calculate variance 
+    ** ------------------------------------------------------------------- */ 
+    arm_var_f32(testOutput, numStudents, &var); 
+ 
+} 
+ 
+ 
+
 

+
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm_convolution_example_f32_8c-example.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm_convolution_example_f32_8c-example.html
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+
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+
+CMSIS DSP Software Library: arm_convolution_example_f32.c
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+  

+
arm_convolution_example_f32.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision:    V1.0.3 
+*  
+* Project:      CMSIS DSP Library  
+* Title:        arm_convolution_example_f32.c         
+*  
+* Description:  Example code demonstrating Convolution of two input signals using fft. 
+* 
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+#include "arm_math.h" 
+#include "math_helper.h"                 
+ 
+/* ---------------------------------------------------------------------- 
+* Defines each of the tests performed 
+* ------------------------------------------------------------------- */ 
+#define MAX_BLOCKSIZE   128 
+#define DELTA           (0.000001f) 
+#define SNR_THRESHOLD   90 
+ 
+/* ---------------------------------------------------------------------- 
+* Declare I/O buffers  
+* ------------------------------------------------------------------- */ 
+float32_t Ak[MAX_BLOCKSIZE];        /* Input A */ 
+float32_t Bk[MAX_BLOCKSIZE];        /* Input B */ 
+float32_t AxB[MAX_BLOCKSIZE * 2];   /* Output */ 
+ 
+/* ---------------------------------------------------------------------- 
+* Test input data for Floating point Convolution example for 32-blockSize 
+* Generated by the MATLAB randn() function 
+* ------------------------------------------------------------------- */ 
+float32_t testInputA_f32[64] =  
+{  
+-0.808920,  1.357369,   1.180861,   -0.504544,  1.762637,   -0.703285,   
+1.696966,   0.620571,   -0.151093,  -0.100235,  -0.872382,  -0.403579,   
+-0.860749,  -0.382648,  -1.052338,  0.128113,   -0.646269,  1.093377,    
+-2.209198,  0.471706,   0.408901,   1.266242,   0.598252,   1.176827,    
+-0.203421,  0.213596,   -0.851964,  -0.466958,  0.021841,   -0.698938,   
+-0.604107,  0.461778,   -0.318219,  0.942520,   0.577585,   0.417619,    
+0.614665,   0.563679,   -1.295073,  -0.764437,  0.952194,   -0.859222,   
+-0.618554,  -2.268542,  -1.210592,  1.655853,   -2.627219,  -0.994249,   
+-1.374704,  0.343799,   0.025619,   1.227481,   -0.708031,  0.069355,    
+-1.845228,  -1.570886,  1.010668,   -1.802084,  1.630088,   1.286090,    
+-0.161050,  -0.940794,  0.367961,   0.291907 
+         
+};  
+  
+float32_t testInputB_f32[64] =  
+{  
+0.933724,   0.046881,   1.316470,   0.438345,   0.332682,   2.094885,    
+0.512081,   0.035546,   0.050894,   -2.320371,  0.168711,   -1.830493,   
+-0.444834,  -1.003242,  -0.531494,  -1.365600,  -0.155420,  -0.757692,   
+-0.431880,  -0.380021,  0.096243,   -0.695835,  0.558850,   -1.648962,   
+0.020369,   -0.363630,  0.887146,   0.845503,   -0.252864,  -0.330397,   
+1.269131,   -1.109295,  -1.027876,  0.135940,   0.116721,   -0.293399,   
+-1.349799,  0.166078,   -0.802201,  0.369367,   -0.964568,  -2.266011,   
+0.465178,   0.651222,   -0.325426,  0.320245,   -0.784178,  -0.579456,   
+0.093374,   0.604778,   -0.048225,  0.376297,   -0.394412,  0.578182,    
+-1.218141,  -1.387326,  0.692462,   -0.631297,  0.153137,   -0.638952,   
+0.635474,   -0.970468,  1.334057,   -0.111370 
+};  
+  
+const float testRefOutput_f32[126] =   
+{  
+-0.818943,  1.229484,   -0.533664,  1.016604,   0.341875,   -1.963656,   
+5.171476,   3.478033,   7.616361,   6.648384,   0.479069,   1.792012,    
+-1.295591,  -7.447818,  0.315830,   -10.657445, -2.483469,  -6.524236,   
+-7.380591,  -3.739005,  -8.388957,  0.184147,   -1.554888,  3.786508,    
+-1.684421,  5.400610,   -1.578126,  7.403361,   8.315999,   2.080267,    
+11.077776,  2.749673,   7.138962,   2.748762,   0.660363,   0.981552,    
+1.442275,   0.552721,   -2.576892,  4.703989,   0.989156,   8.759344,    
+-0.564825,  -3.994680,  0.954710,   -5.014144,  6.592329,   1.599488,    
+-13.979146, -0.391891,  -4.453369,  -2.311242,  -2.948764,  1.761415,    
+-0.138322,  10.433007,  -2.309103,  4.297153,   8.535523,   3.209462,    
+8.695819,   5.569919,   2.514304,   5.582029,   2.060199,   0.642280,    
+7.024616,   1.686615,   -6.481756,  1.343084,   -3.526451,  1.099073,    
+-2.965764,  -0.173723,  -4.111484,  6.528384,   -6.965658,  1.726291,    
+1.535172,   11.023435,  2.338401,   -4.690188,  1.298210,   3.943885,    
+8.407885,   5.168365,   0.684131,   1.559181,   1.859998,   2.852417,    
+8.574070,   -6.369078,  6.023458,   11.837963,  -6.027632,  4.469678,    
+-6.799093,  -2.674048,  6.250367,   -6.809971,  -3.459360,  9.112410,    
+-2.711621,  -1.336678,  1.564249,   -1.564297,  -1.296760,  8.904013,    
+-3.230109,  6.878013,   -7.819823,  3.369909,   -1.657410,  -2.007358,   
+-4.112825,  1.370685,   -3.420525,  -6.276605,  3.244873,   -3.352638,   
+1.545372,   0.902211,   0.197489,   -1.408732,  0.523390,   0.348440 
+}; 
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Declare Global variables  
+* ------------------------------------------------------------------- */ 
+uint32_t srcALen = 64;   /* Length of Input A */ 
+uint32_t srcBLen = 64;   /* Length of Input B */ 
+uint32_t outLen;         /* Length of convolution output */ 
+float32_t snr;           /* output SNR */ 
+ 
+int32_t main(void) 
+{ 
+    arm_status status;     /* Status of the example */ 
+    arm_cfft_radix4_instance_f32 cfft_instance; /* CFFT Structure instance */ 
+ 
+    /* CFFT Structure instance pointer */ 
+    arm_cfft_radix4_instance_f32 *cfft_instance_ptr =  
+            (arm_cfft_radix4_instance_f32*) &cfft_instance; 
+ 
+    /* output length of convolution */ 
+    outLen = srcALen + srcBLen - 1; 
+ 
+    /* Initialise the fft input buffers with all zeros */ 
+    arm_fill_f32(0.0,  Ak, MAX_BLOCKSIZE); 
+    arm_fill_f32(0.0,  Bk, MAX_BLOCKSIZE); 
+ 
+    /* Copy the input values to the fft input buffers */ 
+    arm_copy_f32(testInputA_f32,  Ak, MAX_BLOCKSIZE/2); 
+    arm_copy_f32(testInputB_f32,  Bk, MAX_BLOCKSIZE/2); 
+     
+    /* Initialize the CFFT function to compute 64 point fft */  
+    status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 0, 1); 
+ 
+    /* Transform input a[n] from time domain to frequency domain A[k] */ 
+    arm_cfft_radix4_f32(cfft_instance_ptr, Ak); 
+    /* Transform input b[n] from time domain to frequency domain B[k] */ 
+    arm_cfft_radix4_f32(cfft_instance_ptr, Bk); 
+     
+    /* Complex Multiplication of the two input buffers in frequency domain */ 
+    arm_cmplx_mult_cmplx_f32(Ak, Bk, AxB, MAX_BLOCKSIZE/2);  
+ 
+    /* Initialize the CIFFT function to compute 64 point ifft */  
+    status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 1, 1); 
+ 
+    /* Transform the multiplication output from frequency domain to time domain, 
+       that gives the convolved output  */ 
+    arm_cfft_radix4_f32(cfft_instance_ptr, AxB); 
+ 
+    /* SNR Calculation */ 
+    snr = arm_snr_f32((float32_t *)testRefOutput_f32, AxB, srcALen + srcBLen - 1); 
+     
+    /* Compare the SNR with threshold to test whether the  
+       computed output is matched with the reference output values. */ 
+    if( snr > SNR_THRESHOLD) 
+    { 
+        status = ARM_MATH_SUCCESS; 
+    } 
+         
+    if( status != ARM_MATH_SUCCESS) 
+    { 
+      while(1); 
+    } 
+} 
+                                  
+
 

+
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+
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+

+
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+
+
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+
+doxygen 1.7.2 

+
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm_dotproduct_example_f32_8c-example.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm_dotproduct_example_f32_8c-example.html
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+
+
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+CMSIS DSP Software Library: arm_dotproduct_example_f32.c
+
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+

+  

+
arm_dotproduct_example_f32.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision:    V1.0.3 
+*  
+* Project:      CMSIS DSP Library  
+* Title:        arm_dotproduct_example_f32.c          
+*  
+* Description:  Example code computing dot product of two vectors. 
+* 
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+#include <math.h>     
+#include "arm_math.h" 
+ 
+/* ---------------------------------------------------------------------- 
+* Defines each of the tests performed 
+* ------------------------------------------------------------------- */ 
+#define MAX_BLOCKSIZE   32 
+#define DELTA           (0.000001f) 
+ 
+/* ---------------------------------------------------------------------- 
+* Test input data for Floating point Dot Product example for 32-blockSize 
+* Generated by the MATLAB randn() function 
+* ------------------------------------------------------------------- */  
+/* ----------------------------------------------------------------------  
+** Test input data of srcA for blockSize 32   
+** ------------------------------------------------------------------- */  
+float32_t srcA_buf_f32[MAX_BLOCKSIZE] =   
+{   
+-0.4325648115282207,    -1.6655843782380970,    0.1253323064748307,  
+ 0.2876764203585489,    -1.1464713506814637,    1.1909154656429988,  
+ 1.1891642016521031,    -0.0376332765933176,    0.3272923614086541,  
+ 0.1746391428209245,    -0.1867085776814394,    0.7257905482933027,  
+-0.5883165430141887,     2.1831858181971011,   -0.1363958830865957,  
+ 0.1139313135208096,     1.0667682113591888,    0.0592814605236053,  
+-0.0956484054836690,    -0.8323494636500225,    0.2944108163926404,  
+-1.3361818579378040,     0.7143245518189522,    1.6235620644462707,  
+-0.6917757017022868,     0.8579966728282626,    1.2540014216025324,  
+-1.5937295764474768,    -1.4409644319010200,    0.5711476236581780,  
+-0.3998855777153632,     0.6899973754643451 
+};   
+  
+/* ----------------------------------------------------------------------  
+** Test input data of srcB for blockSize 32   
+** ------------------------------------------------------------------- */   
+float32_t srcB_buf_f32[MAX_BLOCKSIZE] =   
+{   
+ 1.7491401329284098,    0.1325982188803279,  0.3252281811989881,     
+-0.7938091410349637,    0.3149236145048914, -0.5272704888029532,     
+ 0.9322666565031119,    1.1646643544607362, -2.0456694357357357,     
+-0.6443728590041911,    1.7410657940825480,  0.4867684246821860,     
+ 1.0488288293660140,    1.4885752747099299,  1.2705014969484090,     
+-1.8561241921210170,    2.1343209047321410,  1.4358467535865909,     
+-0.9173023332875400,   -1.1060770780029008,  0.8105708062681296,     
+ 0.6985430696369063,   -0.4015827425012831,  1.2687512030669628,     
+-0.7836083053674872,    0.2132664971465569,  0.7878984786088954,     
+ 0.8966819356782295,   -0.1869172943544062,  1.0131816724341454,     
+ 0.2484350696132857,    0.0596083377937976 
+};   
+ 
+/* Reference dot product output */ 
+float32_t  refDotProdOut = 5.9273644806352142;   
+ 
+/* ---------------------------------------------------------------------- 
+* Declare Global variables  
+* ------------------------------------------------------------------- */ 
+float32_t multOutput[MAX_BLOCKSIZE];  /* Intermediate output */ 
+float32_t testOutput;  /* Final ouput */ 
+ 
+arm_status status;   /* Status of the example */ 
+
+int32_t main(void) 
+{ 
+    uint32_t i;          /* Loop counter */ 
+    float32_t diff;      /* Difference between reference and test outputs */ 
+ 
+    /* Multiplication of two input buffers */ 
+    arm_mult_f32(srcA_buf_f32, srcB_buf_f32, multOutput, MAX_BLOCKSIZE); 
+     
+    /* Accumulate the multiplication output values to  
+       get the dot product of the two inputs */ 
+    for(i=0; i< MAX_BLOCKSIZE; i++) 
+    {          
+        arm_add_f32(&testOutput, &multOutput[i], &testOutput, 1);    
+    } 
+ 
+    /* absolute value of difference between ref and test */ 
+    diff = fabsf(refDotProdOut - testOutput); 
+     
+    /* Comparison of dot product value with reference */ 
+    if(diff > DELTA) 
+    { 
+        status = ARM_MATH_TEST_FAILURE; 
+    } 
+         
+    if( status == ARM_MATH_TEST_FAILURE) 
+    { 
+      while(1); 
+    } 
+} 
+ 
+
 

+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm_fft_bin_example_f32_8c-example.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm_fft_bin_example_f32_8c-example.html
new file mode 100644
index 000000000..9441daeb8
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm_fft_bin_example_f32_8c-example.html
@@ -0,0 +1,158 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fft_bin_example_f32.c
+
+
+
+
+
+
+
+
+
+

+  

+
arm_fft_bin_example_f32.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision:    V1.0.3  
+*  
+* Project:      CMSIS DSP Library  
+* Title:        arm_fft_bin_example_f32.c         
+*  
+* Description:  Example code demonstrating calculation of Max energy bin of  
+*               frequency domain of input signal. 
+* 
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+#include "arm_math.h" 
+ 
+#define TEST_LENGTH_SAMPLES 2048 
+ 
+/* ------------------------------------------------------------------- 
+* External Input and Output buffer Declarations for FFT Bin Example 
+* ------------------------------------------------------------------- */ 
+extern float32_t testInput_f32_10khz[TEST_LENGTH_SAMPLES]; 
+static float32_t testOutput[TEST_LENGTH_SAMPLES/2]; 
+ 
+/* ------------------------------------------------------------------ 
+* Global variables for FFT Bin Example 
+* ------------------------------------------------------------------- */ 
+uint32_t fftSize = 1024; 
+uint32_t ifftFlag = 0; 
+uint32_t doBitReverse = 1; 
+ 
+/* Reference index at which max energy of bin ocuurs */ 
+uint32_t refIndex = 213, testIndex = 0; 
+ 
+/* ---------------------------------------------------------------------- 
+* Max magnitude FFT Bin test 
+* ------------------------------------------------------------------- */ 
+ 
+int32_t main(void) 
+{ 
+   
+    arm_status status; 
+    arm_cfft_radix4_instance_f32 S; 
+    float32_t maxValue; 
+     
+    status = ARM_MATH_SUCCESS; 
+     
+    /* Initialize the CFFT/CIFFT module */  
+    status = arm_cfft_radix4_init_f32(&S, fftSize,  
+                                    ifftFlag, doBitReverse); 
+     
+    /* Process the data through the CFFT/CIFFT module */ 
+    arm_cfft_radix4_f32(&S, testInput_f32_10khz); 
+     
+     
+    /* Process the data through the Complex Magnitude Module for  
+    calculating the magnitude at each bin */ 
+    arm_cmplx_mag_f32(testInput_f32_10khz, testOutput,  
+                    fftSize);  
+     
+    /* Calculates maxValue and returns corresponding BIN value */ 
+    arm_max_f32(testOutput, fftSize, &maxValue, &testIndex); 
+     
+    if(testIndex !=  refIndex) 
+    { 
+        status = ARM_MATH_TEST_FAILURE; 
+    } 
+     
+    /* ---------------------------------------------------------------------- 
+    ** Loop here if the signals fail the PASS check. 
+    ** This denotes a test failure 
+    ** ------------------------------------------------------------------- */ 
+     
+    if( status != ARM_MATH_SUCCESS) 
+    { 
+        while(1); 
+    } 
+} 
+ 
+
 

+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm_fir_example_f32_8c-example.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm_fir_example_f32_8c-example.html
new file mode 100644
index 000000000..77c118aab
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm_fir_example_f32_8c-example.html
@@ -0,0 +1,203 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_example_f32.c
+
+
+
+
+
+
+
+
+
+

+  

+
arm_fir_example_f32.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+ * Copyright (C) 2010 ARM Limited. All rights reserved.   
+ *  
+ * $Date:           29. November 2010  
+ * $Revision:       V1.0.3  
+ *  
+ * Project:         CMSIS DSP Library  
+ * Title:           arm_fir_example_f32.c         
+ *  
+ * Description: Example code demonstrating how an FIR filter can be used
+ *               as a low pass filter.
+ * 
+ * Target Processor: Cortex-M4/Cortex-M3  
+ *
+ *
+ * Version 1.0.3 2010/11/29 
+ *    Re-organized the CMSIS folders and updated documentation. 
+ * 
+ * Version 1.0.1 2010/10/05 KK 
+ *    Production release and review comments incorporated.  
+ *
+ * Version 1.0.0 2010/09/20 KK
+ *    Production release and review comments incorporated.
+ * ------------------------------------------------------------------- */ 
+ 
+/* ---------------------------------------------------------------------- 
+** Include Files  
+** ------------------------------------------------------------------- */ 
+
+#include "arm_math.h" 
+#include "math_helper.h" 
+ 
+/* ---------------------------------------------------------------------- 
+** Macro Defines  
+** ------------------------------------------------------------------- */ 
+
+#define TEST_LENGTH_SAMPLES 320 
+#define SNR_THRESHOLD_F32   140.0f 
+#define BLOCK_SIZE          32 
+#define NUM_TAPS            29 
+ 
+/* ------------------------------------------------------------------- 
+ * The input signal and reference output (computed with MATLAB)
+ * are defined externally in arm_fir_lpf_data.c.
+ * ------------------------------------------------------------------- */ 
+
+extern float32_t testInput_f32_1kHz_15kHz[TEST_LENGTH_SAMPLES]; 
+extern float32_t refOutput[TEST_LENGTH_SAMPLES]; 
+ 
+/* ------------------------------------------------------------------- 
+ * Declare Test output buffer 
+ * ------------------------------------------------------------------- */ 
+
+static float32_t testOutput[TEST_LENGTH_SAMPLES]; 
+ 
+/* ------------------------------------------------------------------- 
+ * Declare State buffer of size (numTaps + blockSize - 1) 
+ * ------------------------------------------------------------------- */ 
+
+static float32_t firStateF32[BLOCK_SIZE + NUM_TAPS - 1]; 
+ 
+/* ---------------------------------------------------------------------- 
+** FIR Coefficients buffer generated using fir1() MATLAB function. 
+** fir1(28, 6/24)
+** ------------------------------------------------------------------- */ 
+ 
+const float32_t firCoeffs32[NUM_TAPS] = { 
+-0.0018225230f, -0.0015879294f, +0.0000000000f, +0.0036977508f, +0.0080754303f, +0.0085302217f, -0.0000000000f, -0.0173976984f, 
+-0.0341458607f, -0.0333591565f, +0.0000000000f, +0.0676308395f, +0.1522061835f, +0.2229246956f, +0.2504960933f, +0.2229246956f, 
++0.1522061835f, +0.0676308395f, +0.0000000000f, -0.0333591565f, -0.0341458607f, -0.0173976984f, -0.0000000000f, +0.0085302217f, 
++0.0080754303f, +0.0036977508f, +0.0000000000f, -0.0015879294f, -0.0018225230f 
+}; 
+ 
+/* ------------------------------------------------------------------ 
+ * Global variables for FIR LPF Example 
+ * ------------------------------------------------------------------- */ 
+
+uint32_t blockSize = BLOCK_SIZE; 
+uint32_t numBlocks = TEST_LENGTH_SAMPLES/BLOCK_SIZE; 
+ 
+float32_t  snr; 
+ 
+/* ---------------------------------------------------------------------- 
+ * FIR LPF Example 
+ * ------------------------------------------------------------------- */ 
+ 
+int32_t main(void) 
+{ 
+  uint32_t i; 
+  arm_fir_instance_f32 S; 
+  arm_status status; 
+  float32_t  *inputF32, *outputF32; 
+ 
+  /* Initialize input and output buffer pointers */ 
+  inputF32 = &testInput_f32_1kHz_15kHz[0];   
+  outputF32 = &testOutput[0]; 
+
+  /* Call FIR init function to initialize the instance structure. */
+  arm_fir_init_f32(&S, NUM_TAPS, (float32_t *)&firCoeffs32[0], &firStateF32[0], blockSize); 
+ 
+  /* ---------------------------------------------------------------------- 
+  ** Call the FIR process function for every blockSize samples  
+  ** ------------------------------------------------------------------- */ 
+
+  for(i=0; i < numBlocks; i++)  
+    {    
+      arm_fir_f32(&S, inputF32 + (i * blockSize), outputF32 + (i * blockSize), blockSize);  
+    } 
+ 
+  /* ---------------------------------------------------------------------- 
+  ** Compare the generated output against the reference output computed
+  ** in MATLAB.
+  ** ------------------------------------------------------------------- */ 
+
+  snr = arm_snr_f32(&refOutput[0], &testOutput[0], TEST_LENGTH_SAMPLES); 
+ 
+  if (snr < SNR_THRESHOLD_F32) 
+    { 
+      status = ARM_MATH_TEST_FAILURE; 
+    } 
+  else
+    {
+      status = ARM_MATH_SUCCESS; 
+    }
+     
+  /* ---------------------------------------------------------------------- 
+  ** Loop here if the signal does not match the reference output.
+  ** ------------------------------------------------------------------- */ 
+     
+  if( status != ARM_MATH_SUCCESS) 
+    { 
+      while(1); 
+    } 
+} 
+ 
+
 

+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm_graphic_equalizer_example_q31_8c-example.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm_graphic_equalizer_example_q31_8c-example.html
new file mode 100644
index 000000000..1789bb576
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm_graphic_equalizer_example_q31_8c-example.html
@@ -0,0 +1,372 @@
+
+
+
+
+CMSIS DSP Software Library: arm_graphic_equalizer_example_q31.c
+
+
+
+
+
+
+
+
+
+

+  

+
arm_graphic_equalizer_example_q31.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:         29. November 2010  
+* $Revision:      V1.0.3 
+*  
+* Project:    CMSIS DSP Library  
+* Title:          arm_graphic_equalizer_example_q31.c         
+*  
+* Description:  Example showing an audio graphic equalizer constructed
+*              out of Biquad filters.
+* 
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+#include "arm_math.h" 
+#include "math_helper.h"
+
+/* Length of the overall data in the test */ 
+#define TESTLENGTH 320
+
+/* Block size for the underlying processing */
+#define BLOCKSIZE 32
+
+/* Total number of blocks to run */
+#define NUMBLOCKS (TESTLENGTH/BLOCKSIZE)
+
+/* Number of 2nd order Biquad stages per filter */
+#define NUMSTAGES 2
+
+#define SNR_THRESHOLD_F32  98
+ 
+/* ------------------------------------------------------------------- 
+ * External Declarations for Input and Output buffers 
+ * ------------------------------------------------------------------- */
+ 
+extern float32_t testInput_f32[TESTLENGTH]; 
+static float32_t testOutput[TESTLENGTH]; 
+
+extern float32_t testRefOutput_f32[TESTLENGTH];
+
+/* ----------------------------------------------------------------------  
+** Q31 state buffers for Band1, Band2, Band3, Band4, Band5  
+** ------------------------------------------------------------------- */  
+   
+static q63_t biquadStateBand1Q31[4 * 2];   
+static q63_t biquadStateBand2Q31[4 * 2];   
+static q31_t biquadStateBand3Q31[4 * 2];   
+static q31_t biquadStateBand4Q31[4 * 2];   
+static q31_t biquadStateBand5Q31[4 * 2];   
+ 
+/* ----------------------------------------------------------------------  
+** Q31 input and output buffers  
+** ------------------------------------------------------------------- */  
+
+q31_t inputQ31[BLOCKSIZE];   
+q31_t outputQ31[BLOCKSIZE];  
+ 
+/* ----------------------------------------------------------------------
+** Entire coefficient table.  There are 10 coefficients per 4th order Biquad
+** cascade filter.  The first 10 coefficients correspond to the -9 dB gain
+** setting of band 1; the next 10 coefficient correspond to the -8 dB gain
+** setting of band 1; and so on.  There are 10*19=190 coefficients in total
+** for band 1 (gains = -9, -8, -7, ..., 9).  After this come the 190 coefficients
+** for band 2.
+**
+** The coefficients are in Q29 format and require a postShift of 2.
+** ------------------------------------------------------------------- */
+
+const q31_t coeffTable[950] = {
+
+    /* Band 1, -9 dB gain */
+    535576962, -1071153923, 535576962, 1073741824, -536870912, 535576962, -1063501998, 527979313, 1060865294, -524146981, 
+    /* Band 1, -8 dB gain */
+    535723226, -1071446451, 535723226, 1073741824, -536870912, 535723226, -1063568947, 527903217, 1061230578, -524503778, 
+    535868593, -1071737186, 535868593, 1073741824, -536870912, 535868593, -1063627467, 527819780, 1061585502, -524850686, 
+    536013181, -1072026363, 536013181, 1073741824, -536870912, 536013181, -1063677598, 527728935, 1061930361, -525187972, 
+    536157109, -1072314217, 536157109, 1073741824, -536870912, 536157109, -1063719372, 527630607, 1062265438, -525515897, 
+    536300492, -1072600983, 536300492, 1073741824, -536870912, 536300492, -1063752815, 527524720, 1062591011, -525834716, 
+    536443447, -1072886894, 536443447, 1073741824, -536870912, 536443447, -1063777945, 527411186, 1062907350, -526144676, 
+    536586091, -1073172183, 536586091, 1073741824, -536870912, 536586091, -1063794775, 527289917, 1063214717, -526446017, 
+    536728541, -1073457082, 536728541, 1073741824, -536870912, 536728541, -1063803308, 527160815, 1063513366, -526738975, 
+    536870912, -1073741824, 536870912, 1073741824, -536870912, 536870912, -1063803543, 527023777, 1063803543, -527023777, 
+    537013321, -1074026642, 537013321, 1073741824, -536870912, 537013321, -1063795470, 526878696, 1064085490, -527300648, 
+    537155884, -1074311768, 537155884, 1073741824, -536870912, 537155884, -1063779073, 526725455, 1064359439, -527569803, 
+    537298718, -1074597435, 537298718, 1073741824, -536870912, 537298718, -1063754328, 526563934, 1064625617, -527831454, 
+    537441939, -1074883878, 537441939, 1073741824, -536870912, 537441939, -1063721205, 526394005, 1064884245, -528085806, 
+    537585666, -1075171331, 537585666, 1073741824, -536870912, 537585666, -1063679666, 526215534, 1065135536, -528333059, 
+    537730015, -1075460030, 537730015, 1073741824, -536870912, 537730015, -1063629666, 526028380, 1065379699, -528573409, 
+    537875106, -1075750212, 537875106, 1073741824, -536870912, 537875106, -1063571152, 525832396, 1065616936, -528807045, 
+    538021057, -1076042114, 538021057, 1073741824, -536870912, 538021057, -1063504065, 525627429, 1065847444, -529034151, 
+    538167989, -1076335977, 538167989, 1073741824, -536870912, 538167989, -1063428338, 525413317, 1066071412, -529254907, 
+    
+    /* Band 2, -9 dB gain */
+    531784976, -1055497692, 523873415, 1066213307, -529420241, 531784976, -1040357886, 509828014, 1028908252, -494627367,
+    /* Band 2, -8 dB gain */ 
+    532357636, -1056601982, 524400080, 1066115844, -529326645, 532357636, -1040623406, 509562600, 1030462237, -496062122, 
+    532927392, -1057707729, 524931110, 1066024274, -529239070, 532927392, -1040848253, 509262081, 1031969246, -497457090, 
+    533494678, -1058816094, 525467240, 1065939047, -529157961, 533494678, -1041032161, 508925950, 1033429976, -498812573, 
+    534059929, -1059928204, 526009170, 1065860582, -529083734, 534059929, -1041174868, 508553717, 1034845124, -500128887, 
+    534623580, -1061045148, 526557561, 1065789260, -529016764, 534623580, -1041276126, 508144920, 1036215393, -501406373, 
+    535186068, -1062167969, 527113032, 1065725420, -528957385, 535186068, -1041335703, 507699125, 1037541500, -502645399, 
+    535747827, -1063297666, 527676151, 1065669351, -528905879, 535747827, -1041353386, 507215934, 1038824183, -503846368, 
+    536309295, -1064435183, 528247436, 1065621289, -528862476, 536309295, -1041328990, 506694984, 1040064203, -505009724, 
+    536870912, -1065581413, 528827349, 1065581413, -528827349, 536870912, -1041262354, 506135953, 1041262354, -506135953, 
+    537433117, -1066737194, 529416295, 1065549847, -528800610, 537433117, -1041153346, 505538564, 1042419457, -507225588, 
+    537996352, -1067903307, 530014622, 1065526651, -528782316, 537996352, -1041001864, 504902578, 1043536370, -508279208, 
+    538561061, -1069080480, 530622620, 1065511830, -528772462, 538561061, -1040807833, 504227800, 1044613981, -509297437, 
+    539127690, -1070269387, 531240527, 1065505333, -528770987, 539127690, -1040571205, 503514074, 1045653211, -510280946, 
+    539696690, -1071470656, 531868525, 1065507054, -528777778, 539696690, -1040291951, 502761277, 1046655011, -511230450, 
+    540268512, -1072684867, 532506750, 1065516837, -528792672, 540268512, -1039970063, 501969320, 1047620358, -512146700, 
+    540843613, -1073912567, 533155297, 1065534483, -528815459, 540843613, -1039605542, 501138139, 1048550251, -513030484, 
+    541422451, -1075154268, 533814224, 1065559750, -528845892, 541422451, -1039198394, 500267687, 1049445708, -513882621, 
+    542005489, -1076410460, 534483561, 1065592362, -528883686, 542005489, -1038748624, 499357932, 1050307760, -514703956, 
+    518903861, -1001986830, 486725277, 1037235801, -502367695, 518903861, -945834422, 446371043, 902366163, -400700571, 
+    520899989, -1005630916, 488289126, 1036926846, -502147311, 520899989, -946490935, 445581846, 907921945, -404936158, 
+    522893209, -1009290002, 489869792, 1036650484, -501961419, 522893209, -947006359, 444685310, 913306106, -409075225, 
+    524884763, -1012968199, 491470256, 1036407567, -501810737, 524884763, -947377809, 443679533, 918521018, -413116221, 
+    526875910, -1016669649, 493093518, 1036198712, -501695739, 526875910, -947602324, 442562672, 923569247, -417057897, 
+    528867927, -1020398503, 494742575, 1036024293, -501616651, 528867927, -947676875, 441332970, 928453558, -420899319, 
+    530862111, -1024158905, 496420407, 1035884447, -501573457, 530862111, -947598385, 439988777, 933176909, -424639872, 
+    532859778, -1027954970, 498129955, 1035779077, -501565907, 532859778, -947363742, 438528571, 937742446, -428279254, 
+    534862260, -1031790763, 499874098, 1035707863, -501593525, 534862260, -946969823, 436950987, 942153486, -431817474, 
+    536870912, -1035670279, 501655630, 1035670279, -501655630, 536870912, -946413508, 435254839, 946413508, -435254839, 
+    538887107, -1039597419, 503477238, 1035665609, -501751354, 538887107, -945691703, 433439146, 950526127, -438591937, 
+    540912240, -1043575967, 505341475, 1035692963, -501879659, 540912240, -944801359, 431503152, 954495080, -441829621, 
+    542947726, -1047609569, 507250741, 1035751307, -502039364, 542947726, -943739490, 429446349, 958324201, -444968987, 
+    544995000, -1051701717, 509207261, 1035839473, -502229165, 544995000, -942503190, 427268492, 962017400, -448011351, 
+    547055523, -1055855728, 511213065, 1035956193, -502447657, 547055523, -941089647, 424969617, 965578640, -450958226, 
+    549130774, -1060074734, 513269973, 1036100110, -502693359, 549130774, -939496155, 422550049, 969011913, -453811298, 
+    551222259, -1064361672, 515379585, 1036269804, -502964731, 551222259, -937720119, 420010407, 972321228, -456572401, 
+    553331507, -1068719280, 517543273, 1036463810, -503260192, 553331507, -935759057, 417351601, 975510582, -459243495, 
+    555460072, -1073150100, 519762181, 1036680633, -503578144, 555460072, -933610600, 414574832, 978583948, -461826644, 
+    494084017, -851422604, 404056273, 930151631, -423619864, 494084017, -673714108, 339502486, 561843007, -265801750, 
+    498713542, -859177141, 406587077, 929211656, -423786402, 498713542, -673274906, 338185129, 573719128, -272222942, 
+    503369016, -867012190, 409148384, 928362985, -424054784, 503369016, -672533059, 336693984, 585290277, -278599028, 
+    508052536, -874935599, 411746438, 927604291, -424422151, 508052536, -671478538, 335026905, 596558312, -284920289, 
+    512766286, -882955583, 414387826, 926933782, -424885216, 512766286, -670100998, 333182045, 607525792, -291177811, 
+    517512534, -891080712, 417079474, 926349262, -425440318, 517512534, -668389789, 331157902, 618195914, -297363485, 
+    522293635, -899319903, 419828635, 925848177, -426083491, 522293635, -666333963, 328953368, 628572440, -303470012, 
+    527112032, -907682405, 422642886, 925427679, -426810526, 527112032, -663922286, 326567785, 638659631, -309490882, 
+    531970251, -916177781, 425530105, 925084675, -427617023, 531970251, -661143261, 324000998, 648462180, -315420352, 
+    536870912, -924815881, 428498454, 924815881, -428498454, 536870912, -657985147, 321253420, 657985147, -321253420, 
+    541816719, -933606817, 431556352, 924617870, -429450209, 541816719, -654435997, 318326093, 667233900, -326985786, 
+    546810467, -942560921, 434712438, 924487114, -430467639, 546810467, -650483688, 315220754, 676214053, -332613816, 
+    551855042, -951688708, 437975532, 924420027, -431546101, 551855042, -646115970, 311939896, 684931422, -338134495, 
+    556953421, -961000826, 441354588, 924413001, -432680993, 556953421, -641320513, 308486839, 693391970, -343545389, 
+    562108672, -970508005, 444858642, 924462435, -433867780, 562108672, -636084967, 304865786, 701601770, -348844597, 
+    567323959, -980220994, 448496743, 924564764, -435102022, 567323959, -630397020, 301081886, 709566963, -354030710, 
+    572602539, -990150500, 452277894, 924716482, -436379394, 572602539, -624244471, 297141281, 717293726, -359102767, 
+    577947763, -1000307125, 456210977, 924914158, -437695705, 577947763, -617615296, 293051155, 724788245, -364060214, 
+    583363084, -1010701292, 460304674, 925154455, -439046908, 583363084, -610497723, 288819761, 732056685, -368902865, 
+    387379495, -506912469, 196933274, 840112184, -347208270, 387379495, 506912469, 196933274, -840112184, -347208270, 
+    401658082, -532275898, 207149427, 833765363, -343175316, 401658082, 532275898, 207149427, -833765363, -343175316, 
+    416472483, -558722695, 217902617, 827270154, -339107319, 416472483, 558722695, 217902617, -827270154, -339107319, 
+    431841949, -586290861, 229212798, 820624988, -335007540, 431841949, 586290861, 229212798, -820624988, -335007540, 
+    447786335, -615019650, 241100489, 813828443, -330879528, 447786335, 615019650, 241100489, -813828443, -330879528, 
+    464326111, -644949597, 253586805, 806879270, -326727141, 464326111, 644949597, 253586805, -806879270, -326727141, 
+    481482377, -676122557, 266693475, 799776409, -322554559, 481482377, 676122557, 266693475, -799776409, -322554559, 
+    499276882, -708581728, 280442865, 792519013, -318366296, 499276882, 708581728, 280442865, -792519013, -318366296, 
+    517732032, -742371685, 294857996, 785106465, -314167221, 517732032, 742371685, 294857996, -785106465, -314167221, 
+    536870912, -777538408, 309962566, 777538408, -309962566, 536870912, 777538408, 309962566, -777538408, -309962566, 
+    556717294, -814129313, 325780968, 769814766, -305757943, 556717294, 814129313, 325780968, -769814766, -305757943, 
+    577295658, -852193284, 342338310, 761935777, -301559360, 577295658, 852193284, 342338310, -761935777, -301559360, 
+    598631206, -891780698, 359660433, 753902014, -297373230, 598631206, 891780698, 359660433, -753902014, -297373230, 
+    620749877, -932943463, 377773927, 745714425, -293206383, 620749877, 932943463, 377773927, -745714425, -293206383, 
+    643678365, -975735041, 396706151, 737374355, -289066077, 643678365, 975735041, 396706151, -737374355, -289066077, 
+    667444134, -1020210487, 416485252, 728883588, -284960004, 667444134, 1020210487, 416485252, -728883588, -284960004, 
+    692075438, -1066426476, 437140179, 720244375, -280896294, 692075438, 1066426476, 437140179, -720244375, -280896294, 
+    717601336, -1114441339, 458700704, 711459472, -276883515, 717601336, 1114441339, 458700704, -711459472, -276883515, 
+    744051710, -1164315096, 481197437, 702532174, -272930673, 744051710, 1164315096, 481197437, -702532174, -272930673 
+
+};
+
+/* ----------------------------------------------------------------------
+** Desired gains, in dB, per band
+** ------------------------------------------------------------------- */
+
+int gainDB[5] = {0, -3, 6, 4, -6};
+
+float32_t snr;
+
+
+/* ---------------------------------------------------------------------- 
+ * Graphic equalizer Example 
+ * ------------------------------------------------------------------- */ 
+ 
+int32_t main(void) 
+{ 
+  float32_t  *inputF32, *outputF32;  
+  arm_biquad_cas_df1_32x64_ins_q31 S1; 
+  arm_biquad_cas_df1_32x64_ins_q31 S2; 
+  arm_biquad_casd_df1_inst_q31 S3; 
+  arm_biquad_casd_df1_inst_q31 S4; 
+  arm_biquad_casd_df1_inst_q31 S5; 
+  int i;
+  int32_t status;
+     
+  inputF32 = &testInput_f32[0];  
+  outputF32 = &testOutput[0]; 
+     
+  /* Initialize the state and coefficient buffers for all Biquad sections */
+
+  arm_biquad_cas_df1_32x64_init_q31(&S1, NUMSTAGES, 
+                    (q31_t *) &coeffTable[190*0 + 10*(gainDB[0] + 9)],
+                    &biquadStateBand1Q31[0], 2);
+
+  arm_biquad_cas_df1_32x64_init_q31(&S2, NUMSTAGES, 
+                    (q31_t *) &coeffTable[190*1 + 10*(gainDB[1] + 9)],
+                    &biquadStateBand2Q31[0], 2);
+     
+  arm_biquad_cascade_df1_init_q31(&S3, NUMSTAGES, 
+                  (q31_t *) &coeffTable[190*2 + 10*(gainDB[2] + 9)],
+                  &biquadStateBand3Q31[0], 2);
+
+  arm_biquad_cascade_df1_init_q31(&S4, NUMSTAGES, 
+                  (q31_t *) &coeffTable[190*3 + 10*(gainDB[3] + 9)],
+                  &biquadStateBand4Q31[0], 2); 
+     
+  arm_biquad_cascade_df1_init_q31(&S5, NUMSTAGES, 
+                  (q31_t *) &coeffTable[190*4 + 10*(gainDB[4] + 9)],
+                  &biquadStateBand5Q31[0], 2); 
+     
+ 
+  /* Call the process functions and needs to change filter coefficients  
+     for varying the gain of each band */ 
+ 
+  for(i=0; i < NUMBLOCKS; i++) 
+    {    
+
+      /* ---------------------------------------------------------------------- 
+      ** Convert block of input data from float to Q31 
+      ** ------------------------------------------------------------------- */ 
+
+      arm_float_to_q31(inputF32 + (i*BLOCKSIZE), inputQ31, BLOCKSIZE);     
+         
+      /* ----------------------------------------------------------------------
+      ** Scale down by 1/8.  This provides additional headroom so that the
+      ** graphic EQ can apply gain.
+      ** ------------------------------------------------------------------- */
+
+      arm_scale_q31(inputQ31, 0x7FFFFFFF, -3, inputQ31, BLOCKSIZE);
+
+      /* ----------------------------------------------------------------------
+      ** Call the Q31 Biquad Cascade DF1 32x64 process function for band1, band2
+      ** ------------------------------------------------------------------- */
+
+      arm_biquad_cas_df1_32x64_q31(&S1, inputQ31, outputQ31, BLOCKSIZE); 
+      arm_biquad_cas_df1_32x64_q31(&S2, outputQ31, outputQ31, BLOCKSIZE); 
+
+      /* ---------------------------------------------------------------------- 
+      ** Call the Q31 Biquad Cascade DF1 process function for band3, band4, band5
+      ** ------------------------------------------------------------------- */        
+
+      arm_biquad_cascade_df1_q31(&S3, outputQ31, outputQ31, BLOCKSIZE); 
+      arm_biquad_cascade_df1_q31(&S4, outputQ31, outputQ31, BLOCKSIZE);  
+      arm_biquad_cascade_df1_q31(&S5, outputQ31, outputQ31, BLOCKSIZE); 
+ 
+      /* ---------------------------------------------------------------------- 
+      ** Convert Q31 result back to float 
+      ** ------------------------------------------------------------------- */ 
+
+      arm_q31_to_float(outputQ31, outputF32 + (i * BLOCKSIZE), BLOCKSIZE);
+
+      /* ---------------------------------------------------------------------- 
+      ** Scale back up
+      ** ------------------------------------------------------------------- */ 
+
+      arm_scale_f32(outputF32 + (i * BLOCKSIZE), 8.0f, outputF32 + (i * BLOCKSIZE), BLOCKSIZE);
+    }; 
+
+    snr = arm_snr_f32(testRefOutput_f32, testOutput, TESTLENGTH);
+
+    if (snr < SNR_THRESHOLD_F32) 
+    { 
+        status = ARM_MATH_TEST_FAILURE; 
+    } 
+    else
+    {
+        status = ARM_MATH_SUCCESS; 
+    }
+         
+  /* ---------------------------------------------------------------------- 
+  ** Loop here if the signal does not match the reference output.
+  ** ------------------------------------------------------------------- */ 
+     
+  if( status != ARM_MATH_SUCCESS) 
+    { 
+      while(1); 
+    } 
+
+
+} 
+ 
+
 

+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm_linear_interp_example_f32_8c-example.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm_linear_interp_example_f32_8c-example.html
new file mode 100644
index 000000000..544a5e7a6
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm_linear_interp_example_f32_8c-example.html
@@ -0,0 +1,202 @@
+
+
+
+
+CMSIS DSP Software Library: arm_linear_interp_example_f32.c
+
+
+
+
+
+
+
+
+
+

+  

+
arm_linear_interp_example_f32.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision:    V1.0.3 
+*  
+* Project:      CMSIS DSP Library  
+* Title:        arm_linear_interp_example_f32.c       
+*  
+* Description:  Example code demonstrating usage of sin function  
+*               and uses linear interpolation to get higher precision 
+*                
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+#include "arm_math.h" 
+#include "math_helper.h" 
+ 
+#define SNR_THRESHOLD           90 
+#define TEST_LENGTH_SAMPLES     10 
+#define XSPACING                (0.00005f)
+ 
+/* ---------------------------------------------------------------------- 
+* Test input data for F32 SIN function 
+* Generated by the MATLAB rand() function 
+* randn('state', 0)
+* xi = (((1/4.18318581819710)* randn(blockSize, 1) * 2* pi));
+* --------------------------------------------------------------------*/ 
+float32_t testInputSin_f32[TEST_LENGTH_SAMPLES] =  
+{
+    -0.649716504673081170,  -2.501723745497831200,  0.188250329003310100,   0.432092748487532540,   -1.722010988459680800,  1.788766476323060600,   1.786136060975809500,   -0.056525543169408797,  
+    0.491596272728153760,   0.262309671126153390   
+};  
+ 
+/*------------------------------------------------------------------------------ 
+*  Reference out of SIN F32 function for Block Size = 10  
+*  Calculated from sin(testInputSin_f32) 
+*------------------------------------------------------------------------------*/ 
+float32_t testRefSinOutput32_f32[TEST_LENGTH_SAMPLES] =   
+{
+    -0.604960695383043530,  -0.597090287967934840,  0.187140422442966500,   0.418772124875992690,   -0.988588831792106880,  0.976338412038794010,   0.976903856413481100,   -0.056495446835214236,  
+    0.472033731854734240,   0.259311907228582830
+}; 
+ 
+/*------------------------------------------------------------------------------ 
+*  Method 1: Test out Buffer Calculated from Cubic Interpolation 
+*------------------------------------------------------------------------------*/ 
+float32_t testOutput[TEST_LENGTH_SAMPLES]; 
+ 
+/*------------------------------------------------------------------------------ 
+*  Method 2: Test out buffer Calculated from Linear Interpolation 
+*------------------------------------------------------------------------------*/ 
+float32_t testLinIntOutput[TEST_LENGTH_SAMPLES]; 
+
+/*------------------------------------------------------------------------------ 
+*  External table used for linear interpolation 
+*------------------------------------------------------------------------------*/ 
+extern float32_t arm_linear_interep_table[188495];
+ 
+/* ---------------------------------------------------------------------- 
+* Global Variables for caluclating SNR's for Method1 & Method 2 
+* ------------------------------------------------------------------- */ 
+float32_t snr1; 
+float32_t snr2; 
+ 
+/* ---------------------------------------------------------------------------- 
+* Calculation of Sine values from Cubic Interpolation and Linear interpolation 
+* ---------------------------------------------------------------------------- */ 
+int32_t main(void) 
+{ 
+    uint32_t i; 
+    arm_status status; 
+            
+    arm_linear_interp_instance_f32 S = {188495, -3.141592653589793238, XSPACING, &arm_linear_interep_table[0]}; 
+
+    /*------------------------------------------------------------------------------ 
+    *  Method 1: Test out Calculated from Cubic Interpolation 
+    *------------------------------------------------------------------------------*/ 
+    for(i=0; i< TEST_LENGTH_SAMPLES; i++) 
+    { 
+        testOutput[i] = arm_sin_f32(testInputSin_f32[i]); 
+    } 
+     
+    /*------------------------------------------------------------------------------ 
+    *  Method 2: Test out Calculated from Cubic Interpolation and Linear interpolation 
+    *------------------------------------------------------------------------------*/
+    
+    for(i=0; i< TEST_LENGTH_SAMPLES; i++) 
+    { 
+        testLinIntOutput[i] = arm_linear_interp_f32(&S, testInputSin_f32[i]);
+    }
+ 
+    /*------------------------------------------------------------------------------ 
+    *                   SNR calculation for method 1 
+    *------------------------------------------------------------------------------*/   
+    snr1 = arm_snr_f32(testRefSinOutput32_f32, testOutput, 2); 
+ 
+    /*------------------------------------------------------------------------------ 
+    *                   SNR calculation for method 2 
+    *------------------------------------------------------------------------------*/   
+    snr2 = arm_snr_f32(testRefSinOutput32_f32, testLinIntOutput, 2); 
+     
+    /*------------------------------------------------------------------------------ 
+    *                   Initialise status depending on SNR calculations 
+    *------------------------------------------------------------------------------*/  
+    if( snr2 > snr1) 
+    { 
+        status = ARM_MATH_SUCCESS; 
+    } 
+    else 
+    { 
+        status = ARM_MATH_TEST_FAILURE; 
+    } 
+     
+    /* ---------------------------------------------------------------------- 
+    ** Loop here if the signals fail the PASS check. 
+    ** This denotes a test failure 
+    ** ------------------------------------------------------------------- */ 
+    if( status != ARM_MATH_SUCCESS) 
+    { 
+        while(1); 
+    } 
+} 
+ 
+
 

+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm_matrix_example_f32_8c-example.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm_matrix_example_f32_8c-example.html
new file mode 100644
index 000000000..428e48625
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm_matrix_example_f32_8c-example.html
@@ -0,0 +1,231 @@
+
+
+
+
+CMSIS DSP Software Library: arm_matrix_example_f32.c
+
+
+
+
+
+
+
+
+
+

+  

+
arm_matrix_example_f32.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision:    V1.0.3
+*  
+* Project:      CMSIS DSP Library  
+* Title:        arm_matrix_example_f32.c          
+*  
+* Description:  Example code demonstrating least square fit to data  
+*               using matrix functions  
+*                
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+#include "arm_math.h" 
+#include "math_helper.h" 
+ 
+#define SNR_THRESHOLD   90 
+ 
+/* -------------------------------------------------------------------------------- 
+* Test input data(Cycles) taken from FIR Q15 module for differant cases of blockSize  
+* and tapSize 
+* --------------------------------------------------------------------------------- */ 
+ 
+const float32_t B_f32[4] =  
+{    
+    782.0, 7577.0, 470.0, 4505.0 
+}; 
+ 
+/* -------------------------------------------------------------------------------- 
+* Formula to fit is  C1 + C2 * numTaps + C3 * blockSize + C4 * numTaps * blockSize 
+* -------------------------------------------------------------------------------- */ 
+ 
+const float32_t A_f32[16] =  
+{ 
+    /* Const,   numTaps,    blockSize,  numTaps*blockSize */    
+    1.0,        32.0,       4.0,        128.0,  
+    1.0,        32.0,       64.0,       2048.0, 
+    1.0,        16.0,       4.0,        64.0, 
+    1.0,        16.0,       64.0,       1024.0, 
+};  
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Temporary buffers  for storing intermediate values 
+* ------------------------------------------------------------------- */ 
+/* Transpose of A Buffer */ 
+float32_t AT_f32[16]; 
+/* (Transpose of A * A) Buffer */ 
+float32_t ATMA_f32[16]; 
+/* Inverse(Transpose of A * A)  Buffer */ 
+float32_t ATMAI_f32[16]; 
+/* Test Output Buffer */ 
+float32_t X_f32[4]; 
+ 
+/* ---------------------------------------------------------------------- 
+* Reference ouput buffer C1, C2, C3 and C4 taken from MATLAB  
+* ------------------------------------------------------------------- */ 
+const float32_t xRef_f32[4] = {73.0, 8.0, 21.25, 2.875}; 
+ 
+float32_t snr; 
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Max magnitude FFT Bin test 
+* ------------------------------------------------------------------- */ 
+ 
+int32_t main(void) 
+{ 
+ 
+    arm_matrix_instance_f32 A;      /* Matrix A Instance */ 
+    arm_matrix_instance_f32 AT;     /* Matrix AT(A transpose) instance */ 
+    arm_matrix_instance_f32 ATMA;   /* Matrix ATMA( AT multiply with A) instance */ 
+    arm_matrix_instance_f32 ATMAI;  /* Matrix ATMAI(Inverse of ATMA) instance */ 
+    arm_matrix_instance_f32 B;      /* Matrix B instance */ 
+    arm_matrix_instance_f32 X;      /* Matrix X(Unknown Matrix) instance */ 
+ 
+    uint32_t srcRows, srcColumns;   /* Temporary variables */
+    arm_status status; 
+ 
+    /* Initialise A Matrix Instance with numRows, numCols and data array(A_f32) */ 
+    srcRows = 4; 
+    srcColumns = 4; 
+    arm_mat_init_f32(&A, srcRows, srcColumns, (float32_t *)A_f32); 
+ 
+    /* Initialise Matrix Instance AT with numRows, numCols and data array(AT_f32) */ 
+    srcRows = 4; 
+    srcColumns = 4; 
+    arm_mat_init_f32(&AT, srcRows, srcColumns, AT_f32); 
+ 
+    /* calculation of A transpose */ 
+    status = arm_mat_trans_f32(&A, &AT); 
+     
+ 
+    /* Initialise ATMA Matrix Instance with numRows, numCols and data array(ATMA_f32) */ 
+    srcRows = 4; 
+    srcColumns = 4; 
+    arm_mat_init_f32(&ATMA, srcRows, srcColumns, ATMA_f32); 
+ 
+    /* calculation of AT Multiply with A */ 
+    status = arm_mat_mult_f32(&AT, &A, &ATMA); 
+ 
+    /* Initialise ATMAI Matrix Instance with numRows, numCols and data array(ATMAI_f32) */ 
+    srcRows = 4; 
+    srcColumns = 4; 
+    arm_mat_init_f32(&ATMAI, srcRows, srcColumns, ATMAI_f32); 
+ 
+    /* calculation of Inverse((Transpose(A) * A) */ 
+    status = arm_mat_inverse_f32(&ATMA, &ATMAI); 
+ 
+    /* calculation of (Inverse((Transpose(A) * A)) *  Transpose(A)) */ 
+    status = arm_mat_mult_f32(&ATMAI, &AT, &ATMA); 
+ 
+    /* Initialise B Matrix Instance with numRows, numCols and data array(B_f32) */ 
+    srcRows = 4; 
+    srcColumns = 1; 
+    arm_mat_init_f32(&B, srcRows, srcColumns, (float32_t *)B_f32);  
+ 
+    /* Initialise X Matrix Instance with numRows, numCols and data array(X_f32) */ 
+    srcRows = 4; 
+    srcColumns = 1; 
+    arm_mat_init_f32(&X, srcRows, srcColumns, X_f32); 
+ 
+    /* calculation ((Inverse((Transpose(A) * A)) *  Transpose(A)) * B) */ 
+    status = arm_mat_mult_f32(&ATMA, &B, &X); 
+     
+    /* Comparison of reference with test output */     
+    snr = arm_snr_f32((float32_t *)xRef_f32, X_f32, 4); 
+ 
+    /*------------------------------------------------------------------------------ 
+    *                   Initialise status depending on SNR calculations 
+    *------------------------------------------------------------------------------*/  
+    if( snr > SNR_THRESHOLD) 
+    { 
+        status = ARM_MATH_SUCCESS; 
+    } 
+    else 
+    { 
+        status = ARM_MATH_TEST_FAILURE; 
+    } 
+ 
+     
+    /* ---------------------------------------------------------------------- 
+    ** Loop here if the signals fail the PASS check. 
+    ** This denotes a test failure 
+    ** ------------------------------------------------------------------- */    
+    if( status != ARM_MATH_SUCCESS) 
+    { 
+      while(1); 
+    } 
+} 
+ 
+
 

+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm_signal_converge_example_f32_8c-example.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm_signal_converge_example_f32_8c-example.html
new file mode 100644
index 000000000..5898465db
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm_signal_converge_example_f32_8c-example.html
@@ -0,0 +1,241 @@
+
+
+
+
+CMSIS DSP Software Library: arm_signal_converge_example_f32.c
+
+
+
+
+
+
+
+
+
+

+  

+
arm_signal_converge_example_f32.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision:    V1.0.3
+*  
+* Project:      CMSIS DSP Library  
+* Title:        arm_signal_converge_example_f32.c         
+*  
+* Description:  Example code demonstrating convergence of an adaptive 
+*               filter. 
+* 
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+#include "arm_math.h" 
+#include "math_helper.h" 
+ 
+/* ---------------------------------------------------------------------- 
+** Global defines for the simulation 
+* ------------------------------------------------------------------- */ 
+ 
+#define TEST_LENGTH_SAMPLES 1536 
+#define NUMTAPS             32 
+#define BLOCKSIZE           32 
+#define DELTA_ERROR         0.000001f 
+#define DELTA_COEFF         0.0001f 
+#define MU                  0.5f 
+ 
+#define NUMFRAMES (TEST_LENGTH_SAMPLES / BLOCKSIZE) 
+ 
+/* ---------------------------------------------------------------------- 
+* Declare FIR state buffers and structure  
+* ------------------------------------------------------------------- */ 
+  
+float32_t firStateF32[NUMTAPS + BLOCKSIZE];  
+arm_fir_instance_f32 LPF_instance; 
+ 
+/* ---------------------------------------------------------------------- 
+* Declare LMSNorm state buffers and structure  
+* ------------------------------------------------------------------- */ 
+  
+float32_t lmsStateF32[NUMTAPS + BLOCKSIZE];  
+float32_t errOutput[TEST_LENGTH_SAMPLES]; 
+arm_lms_norm_instance_f32 lmsNorm_instance; 
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Function Declarations for Signal Convergence Example  
+* ------------------------------------------------------------------- */ 
+ 
+arm_status test_signal_converge_example( void ); 
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Internal functions 
+* ------------------------------------------------------------------- */ 
+arm_status test_signal_converge(float32_t* err_signal, 
+                                 uint32_t blockSize); 
+ 
+void getinput(float32_t* input, 
+         uint32_t fr_cnt,  
+         uint32_t blockSize);  
+ 
+/* ---------------------------------------------------------------------- 
+* External Declarations for FIR F32 module Test 
+* ------------------------------------------------------------------- */ 
+extern float32_t testInput_f32[TEST_LENGTH_SAMPLES]; 
+extern float32_t lmsNormCoeff_f32[32]; 
+extern const float32_t FIRCoeff_f32[32]; 
+extern arm_lms_norm_instance_f32 lmsNorm_instance; 
+ 
+/* ---------------------------------------------------------------------- 
+* Declare I/O buffers  
+* ------------------------------------------------------------------- */ 
+ 
+float32_t wire1[BLOCKSIZE]; 
+float32_t wire2[BLOCKSIZE]; 
+float32_t wire3[BLOCKSIZE]; 
+float32_t err_signal[BLOCKSIZE]; 
+ 
+/* ---------------------------------------------------------------------- 
+* Signal converge test 
+* ------------------------------------------------------------------- */ 
+ 
+int32_t main(void) 
+{ 
+  uint32_t i; 
+  arm_status status; 
+  uint32_t index; 
+  float32_t minValue; 
+ 
+  /* Initialize the LMSNorm data structure */ 
+  arm_lms_norm_init_f32(&lmsNorm_instance, NUMTAPS, lmsNormCoeff_f32, lmsStateF32, MU, BLOCKSIZE); 
+ 
+  /* Initialize the FIR data structure */ 
+  arm_fir_init_f32(&LPF_instance, NUMTAPS, (float32_t *)FIRCoeff_f32, firStateF32, BLOCKSIZE); 
+ 
+  /* ---------------------------------------------------------------------- 
+  * Loop over the frames of data and execute each of the processing 
+  * functions in the system. 
+  * ------------------------------------------------------------------- */ 
+ 
+  for(i=0; i < NUMFRAMES; i++)  
+    { 
+      /* Read the input data - uniformly distributed random noise - into wire1 */  
+      arm_copy_f32(testInput_f32 + (i * BLOCKSIZE), wire1, BLOCKSIZE); 
+ 
+      /* Execute the FIR processing function.  Input wire1 and output wire2 */  
+      arm_fir_f32(&LPF_instance, wire1, wire2, BLOCKSIZE); 
+       
+      /* Execute the LMS Norm processing function*/  
+ 
+      arm_lms_norm_f32(&lmsNorm_instance, /* LMSNorm instance */ 
+               wire1,                     /* Input signal */  
+               wire2,                     /* Reference Signal */ 
+               wire3,                     /* Converged Signal */ 
+               err_signal,                /* Error Signal, this will become small as the signal converges */ 
+               BLOCKSIZE);                /* BlockSize */ 
+ 
+      /* apply overall gain */  
+      arm_scale_f32(wire3, 5, wire3, BLOCKSIZE);     /* in-place buffer */  
+    } 
+ 
+  status = ARM_MATH_SUCCESS; 
+ 
+  /* ------------------------------------------------------------------------------- 
+  * Test whether the error signal has reached towards 0. 
+  * ----------------------------------------------------------------------------- */ 
+ 
+  arm_abs_f32(err_signal, err_signal, BLOCKSIZE); 
+  arm_min_f32(err_signal, BLOCKSIZE, &minValue, &index); 
+ 
+  if (minValue > DELTA_ERROR) 
+  { 
+      status = ARM_MATH_TEST_FAILURE; 
+  } 
+ 
+  /* ---------------------------------------------------------------------- 
+  * Test whether the filter coefficients have converged. 
+  * ------------------------------------------------------------------- */ 
+ 
+  arm_sub_f32((float32_t *)FIRCoeff_f32, lmsNormCoeff_f32, lmsNormCoeff_f32, NUMTAPS); 
+ 
+  arm_abs_f32(lmsNormCoeff_f32, lmsNormCoeff_f32, NUMTAPS); 
+  arm_min_f32(lmsNormCoeff_f32, NUMTAPS, &minValue, &index); 
+ 
+  if (minValue > DELTA_COEFF) 
+  { 
+      status = ARM_MATH_TEST_FAILURE; 
+  } 
+ 
+  /* ---------------------------------------------------------------------- 
+  * Loop here if the signals did not pass the convergence check. 
+  * This denotes a test failure 
+  * ------------------------------------------------------------------- */ 
+ 
+  if( status != ARM_MATH_SUCCESS) 
+  { 
+      while(1); 
+  } 
+} 
+ 
+
 

+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm_sin_cos_example_f32_8c-example.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm_sin_cos_example_f32_8c-example.html
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@@ -0,0 +1,167 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sin_cos_example_f32.c
+
+
+
+
+
+
+
+
+
+

+  

+
arm_sin_cos_example_f32.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision:    V1.0.3
+*  
+* Project:      CMSIS DSP Library  
+* Title:        arm_sin_cos_example_f32.c         
+*  
+* Description:  Example code demonstrating sin and cos calculation of input signal. 
+* 
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+#include <math.h>     
+#include "arm_math.h" 
+ 
+/* ---------------------------------------------------------------------- 
+* Defines each of the tests performed 
+* ------------------------------------------------------------------- */ 
+#define MAX_BLOCKSIZE   32 
+#define DELTA           (0.000001f) 
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Test input data for Floating point sin_cos example for 32-blockSize 
+* Generated by the MATLAB randn() function 
+* ------------------------------------------------------------------- */ 
+ 
+const float32_t testInput_f32[MAX_BLOCKSIZE] =  
+{    
+    -1.244916875853235400,  -4.793533929171324800,  0.360705030233248850,   0.827929644170887320,   -3.299532218312426900,  3.427441903227623800,   3.422401784294607700,   -0.108308165334010680,   
+    0.941943896490312180,   0.502609575000365850,   -0.537345278736373500,  2.088817392965764500,   -1.693168684143455700,  6.283185307179590700,   -0.392545884746175080,  0.327893095115825040,    
+    3.070147440456292300,   0.170611405884662230,   -0.275275082396073010,  -2.395492805446796300,  0.847311163536506600,   -3.845517018083148800,  2.055818378415868300,   4.672594161978930800,    
+    -1.990923030266425800,  2.469305197656249500,   3.609002606064021000,   -4.586736582331667500,  -4.147080139136136300,  1.643756718868359500,   -1.150866392366494800,  1.985805026477433800 
+ 
+ 
+};  
+ 
+const float32_t testRefOutput_f32 = 1.000000000; 
+ 
+/* ---------------------------------------------------------------------- 
+* Declare Global variables  
+* ------------------------------------------------------------------- */ 
+uint32_t blockSize = 32; 
+float32_t  testOutput;  
+float32_t  cosOutput;  
+float32_t  sinOutput;  
+float32_t  cosSquareOutput;  
+float32_t  sinSquareOutput; 
+ 
+/* ---------------------------------------------------------------------- 
+* Max magnitude FFT Bin test 
+* ------------------------------------------------------------------- */ 
+
+arm_status status; 
+ 
+int32_t main(void) 
+{ 
+    float32_t diff; 
+    uint32_t i; 
+ 
+    for(i=0; i< blockSize; i++) 
+    { 
+        cosOutput = arm_cos_f32(testInput_f32[i]); 
+        sinOutput = arm_sin_f32(testInput_f32[i]); 
+ 
+        arm_mult_f32(&cosOutput, &cosOutput, &cosSquareOutput, 1); 
+        arm_mult_f32(&sinOutput, &sinOutput, &sinSquareOutput, 1); 
+ 
+        arm_add_f32(&cosSquareOutput, &sinSquareOutput, &testOutput, 1);
+ 
+        /* absolute value of difference between ref and test */ 
+        diff = fabsf(testRefOutput_f32 - testOutput); 
+     
+        /* Comparison of sin_cos value with reference */ 
+        if(diff > DELTA) 
+        { 
+           status = ARM_MATH_TEST_FAILURE; 
+        } 
+         
+        if( status == ARM_MATH_TEST_FAILURE) 
+        { 
+           while(1); 
+        } 
+ 
+    } 
+} 
+ 
+
 

+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm_variance_example_f32_8c-example.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/arm_variance_example_f32_8c-example.html
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@@ -0,0 +1,201 @@
+
+
+
+
+CMSIS DSP Software Library: arm_variance_example_f32.c
+
+
+
+
+
+
+
+
+
+

+  

+
arm_variance_example_f32.c
  

+

+

+
/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.     
+*    
+* $Date:        29. November 2010  
+* $Revision:    V1.0.3
+*     
+* Project:      CMSIS DSP Library  
+* Title:        arm_variance_example_f32.c       
+* 
+* Description:  Example code demonstrating variance calculation of input sequence.
+*     
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */
+
+#include <math.h>    
+#include "arm_math.h"
+
+/* ----------------------------------------------------------------------
+* Defines each of the tests performed
+* ------------------------------------------------------------------- */
+#define MAX_BLOCKSIZE   32
+#define DELTA           (0.000001f)
+
+
+/* ----------------------------------------------------------------------
+* Declare I/O buffers 
+* ------------------------------------------------------------------- */
+float32_t wire1[MAX_BLOCKSIZE];
+float32_t wire2[MAX_BLOCKSIZE];
+float32_t wire3[MAX_BLOCKSIZE];
+
+/* ----------------------------------------------------------------------
+* Test input data for Floating point Variance example for 32-blockSize
+* Generated by the MATLAB randn() function
+* ------------------------------------------------------------------- */
+
+float32_t testInput_f32[32] = 
+{ 
+-0.432564811528221,     -1.665584378238097,     0.125332306474831,      0.287676420358549,  
+-1.146471350681464,     1.190915465642999,      1.189164201652103,      -0.037633276593318,     
+0.327292361408654,      0.174639142820925,      -0.186708577681439,     0.725790548293303,  
+-0.588316543014189,     2.183185818197101,      -0.136395883086596,     0.113931313520810,  
+1.066768211359189,      0.059281460523605,      -0.095648405483669,     -0.832349463650022,     
+0.294410816392640,      -1.336181857937804,     0.714324551818952,      1.623562064446271,  
+-0.691775701702287,     0.857996672828263,      1.254001421602532,      -1.593729576447477,     
+-1.440964431901020,     0.571147623658178,      -0.399885577715363,     0.689997375464345
+  
+};
+
+/* ----------------------------------------------------------------------
+* Declare Global variables 
+* ------------------------------------------------------------------- */
+uint32_t blockSize = 32;
+float32_t  refVarianceOut = 0.903941793931839; 
+
+/* ----------------------------------------------------------------------
+* Variance calculation test
+* ------------------------------------------------------------------- */
+
+int32_t main(void)
+{
+    arm_status status;
+    float32_t mean, oneByBlockSize;
+    float32_t variance;
+    float32_t diff;
+    
+    status = ARM_MATH_SUCCESS;
+    
+    /* Calculation of mean value of input */
+    
+    /* x' = 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1) */
+    
+    /* Fill wire1 buffer with 1.0 value */
+    arm_fill_f32(1.0,  wire1, blockSize);
+    
+    /* Calculate the dot product of wire1 and wire2 */
+    /* (x(0)* 1 + x(1) * 1 + ...+ x(n-1) * 1) */
+    arm_dot_prod_f32(testInput_f32, wire1, blockSize, &mean);
+    
+    /* Calculation of 1/blockSize */
+    oneByBlockSize = 1.0 / (blockSize);
+    
+    /* 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1)  */
+    arm_mult_f32(&mean, &oneByBlockSize, &mean, 1);
+    
+    
+    /* Calculation of variance value of input */
+    
+    /* (1/blockSize) * (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */
+    
+    /* Fill wire2 with mean value x' */
+    arm_fill_f32(mean,  wire2, blockSize);
+    
+    /* wire3 contains (x-x') */     
+    arm_sub_f32(testInput_f32, wire2, wire3, blockSize);
+    
+    /* wire2 contains (x-x') */             
+    arm_copy_f32(wire3, wire2, blockSize);
+    
+    /* (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */
+    arm_dot_prod_f32(wire2, wire3, blockSize, &variance); 
+
+    /* Calculation of 1/blockSize */
+    oneByBlockSize = 1.0 / (blockSize - 1);
+
+    /* Calculation of variance */       
+    arm_mult_f32(&variance, &oneByBlockSize, &variance, 1);
+    
+    /* absolute value of difference between ref and test */
+    diff = fabsf(refVarianceOut - variance);
+    
+    /* Comparison of variance value with reference */
+    if(diff > DELTA)
+    {
+        status = ARM_MATH_TEST_FAILURE;
+    }
+        
+    if( status != ARM_MATH_SUCCESS)
+    {
+      while(1);
+    }
+}
+
+
 

+
+
+
+
+
+

+
+

+
+
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+
+doxygen 1.7.2 

+
+
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+
+
+
+
+CMSIS DSP Software Library: Alphabetical List
+
+
+
+
+
+
+
+
+
+

+  

+
Data Structure Index
  

+

+

+
A

+
+
  A  

+		arm_cfft_radix4_instance_q15   arm_fir_instance_q7   arm_fir_sparse_instance_q7   arm_lms_norm_instance_q31   
arm_bilinear_interp_instance_f32   arm_cfft_radix4_instance_q31   arm_fir_interpolate_instance_f32   arm_iir_lattice_instance_f32   arm_matrix_instance_f32   
arm_bilinear_interp_instance_q15   arm_dct4_instance_f32   arm_fir_interpolate_instance_q15   arm_iir_lattice_instance_q15   arm_matrix_instance_q15   
arm_bilinear_interp_instance_q31   arm_dct4_instance_q15   arm_fir_interpolate_instance_q31   arm_iir_lattice_instance_q31   arm_matrix_instance_q31   
arm_bilinear_interp_instance_q7   arm_dct4_instance_q31   arm_fir_lattice_instance_f32   arm_linear_interp_instance_f32   arm_pid_instance_f32   
arm_biquad_cas_df1_32x64_ins_q31   arm_fir_decimate_instance_f32   arm_fir_lattice_instance_q15   arm_lms_instance_f32   arm_pid_instance_q15   
arm_biquad_cascade_df2T_instance_f32   arm_fir_decimate_instance_q15   arm_fir_lattice_instance_q31   arm_lms_instance_q15   arm_pid_instance_q31   
arm_biquad_casd_df1_inst_f32   arm_fir_decimate_instance_q31   arm_fir_sparse_instance_f32   arm_lms_instance_q31   arm_rfft_instance_f32   
arm_biquad_casd_df1_inst_q15   arm_fir_instance_f32   arm_fir_sparse_instance_q15   arm_lms_norm_instance_f32   arm_rfft_instance_q15   
arm_biquad_casd_df1_inst_q31   arm_fir_instance_q15   arm_fir_sparse_instance_q31   arm_lms_norm_instance_q15   arm_rfft_instance_q31   
arm_cfft_radix4_instance_f32   arm_fir_instance_q31   
A

+

+
+
+
+
+

+
+

+
+
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+
+
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/doxygen.png b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/doxygen.png
new file mode 100644
index 000000000..635ed52fc
Binary files /dev/null and b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/doxygen.png differ
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/examples.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/examples.html
new file mode 100644
index 000000000..0acc93611
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/examples.html
@@ -0,0 +1,91 @@
+
+
+
+
+CMSIS DSP Software Library: Examples
+
+
+
+
+
+
+
+
+
+

+  

+
Examples
  

+

+

+Here is a list of all examples:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/files.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/files.html
new file mode 100644
index 000000000..8797c45d9
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/files.html
@@ -0,0 +1,327 @@
+
+
+
+
+CMSIS DSP Software Library: File Index
+
+
+
+
+
+
+
+
+
+

+  

+
File List
  

+

+

+Here is a list of all files with brief descriptions:
+  
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arm_abs_f32.c [code]
arm_abs_q15.c [code]
arm_abs_q31.c [code]
arm_abs_q7.c [code]
arm_add_f32.c [code]
arm_add_q15.c [code]
arm_add_q31.c [code]
arm_add_q7.c [code]
arm_biquad_cascade_df1_32x64_init_q31.c [code]
arm_biquad_cascade_df1_32x64_q31.c [code]
arm_biquad_cascade_df1_f32.c [code]
arm_biquad_cascade_df1_fast_q15.c [code]
arm_biquad_cascade_df1_fast_q31.c [code]
arm_biquad_cascade_df1_init_f32.c [code]
arm_biquad_cascade_df1_init_q15.c [code]
arm_biquad_cascade_df1_init_q31.c [code]
arm_biquad_cascade_df1_q15.c [code]
arm_biquad_cascade_df1_q31.c [code]
arm_biquad_cascade_df2T_f32.c [code]
arm_biquad_cascade_df2T_init_f32.c [code]
arm_cfft_radix4_f32.c [code]
arm_cfft_radix4_init_f32.c [code]
arm_cfft_radix4_init_q15.c [code]
arm_cfft_radix4_init_q31.c [code]
arm_cfft_radix4_q15.c [code]
arm_cfft_radix4_q31.c [code]
arm_class_marks_example_f32.c [code]
arm_cmplx_conj_f32.c [code]
arm_cmplx_conj_q15.c [code]
arm_cmplx_conj_q31.c [code]
arm_cmplx_dot_prod_f32.c [code]
arm_cmplx_dot_prod_q15.c [code]
arm_cmplx_dot_prod_q31.c [code]
arm_cmplx_mag_f32.c [code]
arm_cmplx_mag_q15.c [code]
arm_cmplx_mag_q31.c [code]
arm_cmplx_mag_squared_f32.c [code]
arm_cmplx_mag_squared_q15.c [code]
arm_cmplx_mag_squared_q31.c [code]
arm_cmplx_mult_cmplx_f32.c [code]
arm_cmplx_mult_cmplx_q15.c [code]
arm_cmplx_mult_cmplx_q31.c [code]
arm_cmplx_mult_real_f32.c [code]
arm_cmplx_mult_real_q15.c [code]
arm_cmplx_mult_real_q31.c [code]
arm_common_tables.c [code]
arm_conv_f32.c [code]
arm_conv_fast_q15.c [code]
arm_conv_fast_q31.c [code]
arm_conv_partial_f32.c [code]
arm_conv_partial_fast_q15.c [code]
arm_conv_partial_fast_q31.c [code]
arm_conv_partial_q15.c [code]
arm_conv_partial_q31.c [code]
arm_conv_partial_q7.c [code]
arm_conv_q15.c [code]
arm_conv_q31.c [code]
arm_conv_q7.c [code]
arm_convolution_example_f32.c [code]
arm_copy_f32.c [code]
arm_copy_q15.c [code]
arm_copy_q31.c [code]
arm_copy_q7.c [code]
arm_correlate_f32.c [code]
arm_correlate_fast_q15.c [code]
arm_correlate_fast_q31.c [code]
arm_correlate_q15.c [code]
arm_correlate_q31.c [code]
arm_correlate_q7.c [code]
arm_cos_f32.c [code]
arm_cos_q15.c [code]
arm_cos_q31.c [code]
arm_dct4_f32.c [code]
arm_dct4_init_f32.c [code]
arm_dct4_init_q15.c [code]
arm_dct4_init_q31.c [code]
arm_dct4_q15.c [code]
arm_dct4_q31.c [code]
arm_dot_prod_f32.c [code]
arm_dot_prod_q15.c [code]
arm_dot_prod_q31.c [code]
arm_dot_prod_q7.c [code]
arm_dotproduct_example_f32.c [code]
arm_fft_bin_example_f32.c [code]
arm_fill_f32.c [code]
arm_fill_q15.c [code]
arm_fill_q31.c [code]
arm_fill_q7.c [code]
arm_fir_decimate_f32.c [code]
arm_fir_decimate_fast_q15.c [code]
arm_fir_decimate_fast_q31.c [code]
arm_fir_decimate_init_f32.c [code]
arm_fir_decimate_init_q15.c [code]
arm_fir_decimate_init_q31.c [code]
arm_fir_decimate_q15.c [code]
arm_fir_decimate_q31.c [code]
arm_fir_example_f32.c [code]
arm_fir_f32.c [code]
arm_fir_fast_q15.c [code]
arm_fir_fast_q31.c [code]
arm_fir_init_f32.c [code]
arm_fir_init_q15.c [code]
arm_fir_init_q31.c [code]
arm_fir_init_q7.c [code]
arm_fir_interpolate_f32.c [code]
arm_fir_interpolate_init_f32.c [code]
arm_fir_interpolate_init_q15.c [code]
arm_fir_interpolate_init_q31.c [code]
arm_fir_interpolate_q15.c [code]
arm_fir_interpolate_q31.c [code]
arm_fir_lattice_f32.c [code]
arm_fir_lattice_init_f32.c [code]
arm_fir_lattice_init_q15.c [code]
arm_fir_lattice_init_q31.c [code]
arm_fir_lattice_q15.c [code]
arm_fir_lattice_q31.c [code]
arm_fir_q15.c [code]
arm_fir_q31.c [code]
arm_fir_q7.c [code]
arm_fir_sparse_f32.c [code]
arm_fir_sparse_init_f32.c [code]
arm_fir_sparse_init_q15.c [code]
arm_fir_sparse_init_q31.c [code]
arm_fir_sparse_init_q7.c [code]
arm_fir_sparse_q15.c [code]
arm_fir_sparse_q31.c [code]
arm_fir_sparse_q7.c [code]
arm_float_to_q15.c [code]
arm_float_to_q31.c [code]
arm_float_to_q7.c [code]
arm_graphic_equalizer_example_q31.c [code]
arm_iir_lattice_f32.c [code]
arm_iir_lattice_init_f32.c [code]
arm_iir_lattice_init_q15.c [code]
arm_iir_lattice_init_q31.c [code]
arm_iir_lattice_q15.c [code]
arm_iir_lattice_q31.c [code]
arm_linear_interp_example_f32.c [code]
arm_lms_f32.c [code]
arm_lms_init_f32.c [code]
arm_lms_init_q15.c [code]
arm_lms_init_q31.c [code]
arm_lms_norm_f32.c [code]
arm_lms_norm_init_f32.c [code]
arm_lms_norm_init_q15.c [code]
arm_lms_norm_init_q31.c [code]
arm_lms_norm_q15.c [code]
arm_lms_norm_q31.c [code]
arm_lms_q15.c [code]
arm_lms_q31.c [code]
arm_mat_add_f32.c [code]
arm_mat_add_q15.c [code]
arm_mat_add_q31.c [code]
arm_mat_init_f32.c [code]
arm_mat_init_q15.c [code]
arm_mat_init_q31.c [code]
arm_mat_inverse_f32.c [code]
arm_mat_mult_f32.c [code]
arm_mat_mult_fast_q15.c [code]
arm_mat_mult_fast_q31.c [code]
arm_mat_mult_q15.c [code]
arm_mat_mult_q31.c [code]
arm_mat_scale_f32.c [code]
arm_mat_scale_q15.c [code]
arm_mat_scale_q31.c [code]
arm_mat_sub_f32.c [code]
arm_mat_sub_q15.c [code]
arm_mat_sub_q31.c [code]
arm_mat_trans_f32.c [code]
arm_mat_trans_q15.c [code]
arm_mat_trans_q31.c [code]
arm_math.h [code]
arm_matrix_example_f32.c [code]
arm_max_f32.c [code]
arm_max_q15.c [code]
arm_max_q31.c [code]
arm_max_q7.c [code]
arm_mean_f32.c [code]
arm_mean_q15.c [code]
arm_mean_q31.c [code]
arm_mean_q7.c [code]
arm_min_f32.c [code]
arm_min_q15.c [code]
arm_min_q31.c [code]
arm_min_q7.c [code]
arm_mult_f32.c [code]
arm_mult_q15.c [code]
arm_mult_q31.c [code]
arm_mult_q7.c [code]
arm_negate_f32.c [code]
arm_negate_q15.c [code]
arm_negate_q31.c [code]
arm_negate_q7.c [code]
arm_offset_f32.c [code]
arm_offset_q15.c [code]
arm_offset_q31.c [code]
arm_offset_q7.c [code]
arm_pid_init_f32.c [code]
arm_pid_init_q15.c [code]
arm_pid_init_q31.c [code]
arm_pid_reset_f32.c [code]
arm_pid_reset_q15.c [code]
arm_pid_reset_q31.c [code]
arm_power_f32.c [code]
arm_power_q15.c [code]
arm_power_q31.c [code]
arm_power_q7.c [code]
arm_q15_to_float.c [code]
arm_q15_to_q31.c [code]
arm_q15_to_q7.c [code]
arm_q31_to_float.c [code]
arm_q31_to_q15.c [code]
arm_q31_to_q7.c [code]
arm_q7_to_float.c [code]
arm_q7_to_q15.c [code]
arm_q7_to_q31.c [code]
arm_rfft_f32.c [code]
arm_rfft_init_f32.c [code]
arm_rfft_init_q15.c [code]
arm_rfft_init_q31.c [code]
arm_rfft_q15.c [code]
arm_rfft_q31.c [code]
arm_rms_f32.c [code]
arm_rms_q15.c [code]
arm_rms_q31.c [code]
arm_scale_f32.c [code]
arm_scale_q15.c [code]
arm_scale_q31.c [code]
arm_scale_q7.c [code]
arm_shift_q15.c [code]
arm_shift_q31.c [code]
arm_shift_q7.c [code]
arm_signal_converge_example_f32.c [code]
arm_sin_cos_example_f32.c [code]
arm_sin_cos_f32.c [code]
arm_sin_cos_q31.c [code]
arm_sin_f32.c [code]
arm_sin_q15.c [code]
arm_sin_q31.c [code]
arm_sqrt_q15.c [code]
arm_sqrt_q31.c [code]
arm_std_f32.c [code]
arm_std_q15.c [code]
arm_std_q31.c [code]
arm_sub_f32.c [code]
arm_sub_q15.c [code]
arm_sub_q31.c [code]
arm_sub_q7.c [code]
arm_var_f32.c [code]
arm_var_q15.c [code]
arm_var_q31.c [code]
arm_variance_example_f32.c [code]

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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions.html
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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all struct and union fields with links to the structures/unions they belong to:
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_0x62.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_0x62.html
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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all struct and union fields with links to the structures/unions they belong to:
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_0x65.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_0x65.html
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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all struct and union fields with links to the structures/unions they belong to:
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_0x66.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_0x66.html
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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all struct and union fields with links to the structures/unions they belong to:
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+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_0x69.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_0x69.html
new file mode 100644
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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all struct and union fields with links to the structures/unions they belong to:
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+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_0x6b.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_0x6b.html
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+CMSIS DSP Software Library: Data Fields
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+
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+Here is a list of all struct and union fields with links to the structures/unions they belong to:
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+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_0x6c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_0x6c.html
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+CMSIS DSP Software Library: Data Fields
+
+
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+Here is a list of all struct and union fields with links to the structures/unions they belong to:
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+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all struct and union fields with links to the structures/unions they belong to:
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- m -

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+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_0x6e.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_0x6e.html
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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all struct and union fields with links to the structures/unions they belong to:
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_0x6f.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_0x6f.html
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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all struct and union fields with links to the structures/unions they belong to:
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_0x70.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_0x70.html
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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all struct and union fields with links to the structures/unions they belong to:
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+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_0x72.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_0x72.html
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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all struct and union fields with links to the structures/unions they belong to:
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_0x73.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_0x73.html
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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all struct and union fields with links to the structures/unions they belong to:
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_0x74.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_0x74.html
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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all struct and union fields with links to the structures/unions they belong to:
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_0x78.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_0x78.html
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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all struct and union fields with links to the structures/unions they belong to:
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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+doxygen 1.7.2 

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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x62.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x62.html
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+CMSIS DSP Software Library: Data Fields - Variables
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+doxygen 1.7.2 

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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x65.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x65.html
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x6d.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x6d.html
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x6e.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x6e.html
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x6f.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x6f.html
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+CMSIS DSP Software Library: Data Fields - Variables
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- x -

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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals.html
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+CMSIS DSP Software Library: Data Fields
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- _ -

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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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+CMSIS DSP Software Library: Data Fields
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+
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- a -

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+
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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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+CMSIS DSP Software Library: Data Fields
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+
+
- b -

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+
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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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+CMSIS DSP Software Library: Data Fields
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+
+
- c -

+

+
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+

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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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+CMSIS DSP Software Library: Data Fields
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+
+
- d -

+

+
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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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+CMSIS DSP Software Library: Data Fields
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+
+
- e -

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+

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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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+CMSIS DSP Software Library: Data Fields
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+
+
- f -

+

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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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+CMSIS DSP Software Library: Data Fields
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+
+
- g -

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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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+CMSIS DSP Software Library: Data Fields
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+
+
- i -

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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
+
+
- l -

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+
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+
+
+

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+

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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x6d.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x6d.html
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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
+
+
- m -

+

+
+
+
+
+

+
+

+
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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x6e.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x6e.html
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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
+
+
- n -

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x6f.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x6f.html
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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
+
+
- o -

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
+
+
- p -

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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+CMSIS DSP Software Library: Data Fields
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+

+Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
+
+
- q -

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x72.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x72.html
new file mode 100644
index 000000000..74974972d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x72.html
@@ -0,0 +1,140 @@
+
+
+
+
+CMSIS DSP Software Library: Data Fields
+
+
+
+
+
+
+
+
+
+

+Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
+
+
- r -

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x73.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x73.html
new file mode 100644
index 000000000..3ef80eaab
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x73.html
@@ -0,0 +1,170 @@
+
+
+
+
+CMSIS DSP Software Library: Data Fields
+
+
+
+
+
+
+
+
+
+

+Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
+
+
- s -

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x74.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x74.html
new file mode 100644
index 000000000..c5eda4bfb
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x74.html
@@ -0,0 +1,194 @@
+
+
+
+
+CMSIS DSP Software Library: Data Fields
+
+
+
+
+
+
+
+
+
+

+Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
+
+
- t -

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x75.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x75.html
new file mode 100644
index 000000000..76f4e4212
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x75.html
@@ -0,0 +1,113 @@
+
+
+
+
+CMSIS DSP Software Library: Data Fields
+
+
+
+
+
+
+
+
+
+

+Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
+
+
- u -

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x76.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x76.html
new file mode 100644
index 000000000..555974e04
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x76.html
@@ -0,0 +1,113 @@
+
+
+
+
+CMSIS DSP Software Library: Data Fields
+
+
+
+
+
+
+
+
+
+

+Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
+
+
- v -

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x77.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x77.html
new file mode 100644
index 000000000..cc75df034
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x77.html
@@ -0,0 +1,149 @@
+
+
+
+
+CMSIS DSP Software Library: Data Fields
+
+
+
+
+
+
+
+
+
+

+Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
+
+
- w -

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x78.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x78.html
new file mode 100644
index 000000000..cb6f7da2c
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_0x78.html
@@ -0,0 +1,119 @@
+
+
+
+
+CMSIS DSP Software Library: Data Fields
+
+
+
+
+
+
+
+
+
+

+Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
+
+
- x -

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_defs.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_defs.html
new file mode 100644
index 000000000..b4733ba03
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_defs.html
@@ -0,0 +1,246 @@
+
+
+
+
+CMSIS DSP Software Library: Data Fields
+
+
+
+
+
+
+
+
+
+

+ 
+
+
- _ -

+
+
+
- b -

+
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- d -

+
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- i -

+
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- x -

+

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+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_enum.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_enum.html
new file mode 100644
index 000000000..b0e9d6dfa
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_enum.html
@@ -0,0 +1,85 @@
+
+
+
+
+CMSIS DSP Software Library: Data Fields
+
+
+
+
+
+
+
+
+
+

+ 
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_eval.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_eval.html
new file mode 100644
index 000000000..b27676d51
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_eval.html
@@ -0,0 +1,103 @@
+
+
+
+
+CMSIS DSP Software Library: Data Fields
+
+
+
+
+
+
+
+
+
+

+ 
+

+
+
+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_func.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_func.html
new file mode 100644
index 000000000..654b085f9
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_func.html
@@ -0,0 +1,1185 @@
+
+
+
+
+CMSIS DSP Software Library: Data Fields
+
+
+
+
+
+
+
+
+
+

+ 
+
+
- a -

+

+
+
+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_func_0x63.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_func_0x63.html
new file mode 100644
index 000000000..39cf528f2
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_func_0x63.html
@@ -0,0 +1,105 @@
+
+
+
+
+CMSIS DSP Software Library: Data Fields
+
+
+
+
+
+
+
+
+
+

+ 
+
+
- c -

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_func_0x67.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_func_0x67.html
new file mode 100644
index 000000000..31e908dea
--- /dev/null
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@@ -0,0 +1,96 @@
+
+
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+CMSIS DSP Software Library: Data Fields
+
+
+
+
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+

+ 
+
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- g -

+

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+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_func_0x6d.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_func_0x6d.html
new file mode 100644
index 000000000..144d0730f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_func_0x6d.html
@@ -0,0 +1,109 @@
+
+
+
+
+CMSIS DSP Software Library: Data Fields
+
+
+
+
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+

+ 
+
+
- m -

+

+
+
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+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_func_0x74.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_func_0x74.html
new file mode 100644
index 000000000..c1f4c5e32
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_func_0x74.html
@@ -0,0 +1,99 @@
+
+
+
+
+CMSIS DSP Software Library: Data Fields
+
+
+
+
+
+
+
+
+
+

+ 
+
+
- t -

+

+
+
+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_type.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_type.html
new file mode 100644
index 000000000..fed241ab5
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_type.html
@@ -0,0 +1,100 @@
+
+
+
+
+CMSIS DSP Software Library: Data Fields
+
+
+
+
+
+
+
+
+
+

+ 
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_vars.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_vars.html
new file mode 100644
index 000000000..4f8335dc9
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/globals_vars.html
@@ -0,0 +1,535 @@
+
+
+
+
+CMSIS DSP Software Library: Data Fields
+
+
+
+
+
+
+
+
+
+

+ 
+
+
- a -

+
+
+
- b -

+
+
+
- c -

+
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+
- d -

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- n -

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- o -

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+

+
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+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___basic_abs.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___basic_abs.html
new file mode 100644
index 000000000..f23be47b2
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___basic_abs.html
@@ -0,0 +1,277 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Absolute Value
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Absolute Value

+
+[Basic Math Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_abs_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_abs_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_abs_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_abs_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)

+
Detailed Description

+
Computes the absolute value of a vector on an element-by-element basis.

+
   
+     pDst[n] = abs(pSrcA[n]),   0 <= n < blockSize.   
+ 
The operation can be done in-place by setting the input and output pointers to the same buffer. There are separate functions for floating-point, Q7, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_abs_f32 (float32_t *  pSrc, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Floating-point vector absolute value. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer 
[out]*pDstpoints to the output buffer 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Definition at line 66 of file arm_abs_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_abs_q31 (q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Q31 vector absolute value. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer 
[out]*pDstpoints to the output buffer 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. 

+
+
Definition at line 58 of file arm_abs_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_abs_q15 (q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Q15 vector absolute value. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer 
[out]*pDstpoints to the output buffer 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. 

+
+
Definition at line 57 of file arm_abs_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_abs_q7 (q7_t *  pSrc, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Q7 vector absolute value. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer 
[out]*pDstpoints to the output buffer 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. 

+
+
Definition at line 57 of file arm_abs_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___basic_add.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___basic_add.html
new file mode 100644
index 000000000..9d5f8d102
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___basic_add.html
@@ -0,0 +1,305 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Addition
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Addition

+
+[Basic Math Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_add_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
void arm_add_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
void arm_add_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
void arm_add_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)

+
Detailed Description

+
Element-by-element addition of two vectors.

+
   
+     pDst[n] = pSrcA[n] + pSrcB[n],   0 <= n < blockSize.   
+ 
There are separate functions for floating-point, Q7, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_add_f32 (float32_t *  pSrcA, 
float32_t *  pSrcB, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Floating-point vector addition. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_dotproduct_example_f32.c, and arm_sin_cos_example_f32.c.

+

+
Definition at line 65 of file arm_add_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
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+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_add_q31 (q31_t *  pSrcA, 
q31_t *  pSrcB, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Q31 vector addition. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated. 

+
+
Definition at line 59 of file arm_add_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
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+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_add_q15 (q15_t *  pSrcA, 
q15_t *  pSrcB, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Q15 vector addition. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 

+
+
Definition at line 58 of file arm_add_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+          
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+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_add_q7 (q7_t *  pSrcA, 
q7_t *  pSrcB, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Q7 vector addition. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. 

+
+
Definition at line 58 of file arm_add_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___basic_mult.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___basic_mult.html
new file mode 100644
index 000000000..f51ae33c1
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___basic_mult.html
@@ -0,0 +1,305 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Multiplication
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Multiplication

+
+[Basic Math Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_mult_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
void arm_mult_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
void arm_mult_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
void arm_mult_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)

+
Detailed Description

+
Element-by-element multiplication of two vectors.

+
   
+     pDst[n] = pSrcA[n] * pSrcB[n],   0 <= n < blockSize.   
+ 
There are separate functions for floating-point, Q7, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_mult_f32 (float32_t *  pSrcA, 
float32_t *  pSrcB, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Floating-point vector multiplication. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_dotproduct_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 68 of file arm_mult_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_mult_q31 (q31_t *  pSrcA, 
q31_t *  pSrcB, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Q31 vector multiplication. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated. 

+
+
Definition at line 61 of file arm_mult_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_mult_q15 (q15_t *  pSrcA, 
q15_t *  pSrcB, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Q15 vector multiplication. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 

+
+
Definition at line 62 of file arm_mult_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
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+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_mult_q7 (q7_t *  pSrcA, 
q7_t *  pSrcB, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Q7 vector multiplication. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. 

+
+
Definition at line 64 of file arm_mult_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___basic_sub.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___basic_sub.html
new file mode 100644
index 000000000..34d69aa7a
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___basic_sub.html
@@ -0,0 +1,305 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Subtraction
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Subtraction

+
+[Basic Math Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_sub_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
void arm_sub_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
void arm_sub_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
void arm_sub_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)

+
Detailed Description

+
Element-by-element subtraction of two vectors.

+
   
+     pDst[n] = pSrcA[n] - pSrcB[n],   0 <= n < blockSize.   
+ 
There are separate functions for floating-point, Q7, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_sub_f32 (float32_t *  pSrcA, 
float32_t *  pSrcB, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Floating-point vector subtraction. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_signal_converge_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 66 of file arm_sub_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_sub_q31 (q31_t *  pSrcA, 
q31_t *  pSrcB, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Q31 vector subtraction. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. 

+
+
Definition at line 58 of file arm_sub_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_sub_q15 (q15_t *  pSrcA, 
q15_t *  pSrcB, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Q15 vector subtraction. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 

+
+
Definition at line 58 of file arm_sub_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_sub_q7 (q7_t *  pSrcA, 
q7_t *  pSrcB, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Q7 vector subtraction. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. 

+
+
Definition at line 58 of file arm_sub_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___bilinear_interpolate.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___bilinear_interpolate.html
new file mode 100644
index 000000000..110dac1ce
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___bilinear_interpolate.html
@@ -0,0 +1,288 @@
+
+
+
+
+CMSIS DSP Software Library: Bilinear Interpolation
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Bilinear Interpolation

+
+[Interpolation Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
static __INLINE float32_t arm_bilinear_interp_f32 (const arm_bilinear_interp_instance_f32 *S, float32_t X, float32_t Y)
static __INLINE q31_t arm_bilinear_interp_q31 (arm_bilinear_interp_instance_q31 *S, q31_t X, q31_t Y)
static __INLINE q15_t arm_bilinear_interp_q15 (arm_bilinear_interp_instance_q15 *S, q31_t X, q31_t Y)
static __INLINE q7_t arm_bilinear_interp_q7 (arm_bilinear_interp_instance_q7 *S, q31_t X, q31_t Y)

+
Detailed Description

+
Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. The underlying function f(x, y) is sampled on a regular grid and the interpolation process determines values between the grid points. Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. Bilinear interpolation is often used in image processing to rescale images. The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.

+
Algorithm 

+
The instance structure used by the bilinear interpolation functions describes a two dimensional data table. For floating-point, the instance structure is defined as: 
+   typedef struct
+   {
+     uint16_t numRows;
+     uint16_t numCols;
+     float32_t *pData;
+ } arm_bilinear_interp_instance_f32;
+ 

+
where numRows specifies the number of rows in the table; numCols specifies the number of columns in the table; and pData points to an array of size numRows*numCols values. The data table pTable is organized in row order and the supplied data values fall on integer indexes. That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.

+
Let (x, y) specify the desired interpolation point. Then define: 
+     XF = floor(x)
+     YF = floor(y)
+ 
 

+
The interpolated output point is computed as: 
+  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ 
 Note that the coordinates (x, y) contain integer and fractional components. The integer components specify which portion of the table to use while the fractional components control the interpolation processor.

+
if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
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+        
+        
+          
+          
+          
+        
+      
static __INLINE float32_t arm_bilinear_interp_f32 (const arm_bilinear_interp_instance_f32 *  S, 
float32_t  X, 
float32_t  Y 
) [static]

+

+

+
+
Floating-point bilinear interpolation. 

+
Parameters:

+  
+    
+    
+    
+  
[in,out]*Spoints to an instance of the interpolation structure. 
[in]Xinterpolation coordinate. 
[in]Yinterpolation coordinate. 

+  

+

+
Returns:
out interpolated value. 

+
+
Definition at line 6739 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
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+          
+        
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+          
+          
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+        
+        
+          
+          
+          
+        
+      
static __INLINE q31_t arm_bilinear_interp_q31 (arm_bilinear_interp_instance_q31 *  S, 
q31_t  X, 
q31_t  Y 
) [static]

+

+

+
+
Q31 bilinear interpolation. 

+
Parameters:

+  
+    
+    
+    
+  
[in,out]*Spoints to an instance of the interpolation structure. 
[in]Xinterpolation coordinate in 12.20 format. 
[in]Yinterpolation coordinate in 12.20 format. 

+  

+

+
Returns:
out interpolated value. 

+
+
Definition at line 6806 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
static __INLINE q15_t arm_bilinear_interp_q15 (arm_bilinear_interp_instance_q15 *  S, 
q31_t  X, 
q31_t  Y 
) [static]

+

+

+
+
Q15 bilinear interpolation. 

+
Parameters:

+  
+    
+    
+    
+  
[in,out]*Spoints to an instance of the interpolation structure. 
[in]Xinterpolation coordinate in 12.20 format. 
[in]Yinterpolation coordinate in 12.20 format. 

+  

+

+
Returns:
out interpolated value. 

+
+
Definition at line 6882 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
static __INLINE q7_t arm_bilinear_interp_q7 (arm_bilinear_interp_instance_q7 *  S, 
q31_t  X, 
q31_t  Y 
) [static]

+

+

+
+
Q7 bilinear interpolation. 

+
Parameters:

+  
+    
+    
+    
+  
[in,out]*Spoints to an instance of the interpolation structure. 
[in]Xinterpolation coordinate in 12.20 format. 
[in]Yinterpolation coordinate in 12.20 format. 

+  

+

+
Returns:
out interpolated value. 

+
+
Definition at line 6962 of file arm_math.h.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___biquad_cascade_d_f1.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___biquad_cascade_d_f1.html
new file mode 100644
index 000000000..30166fa76
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___biquad_cascade_d_f1.html
@@ -0,0 +1,605 @@
+
+
+
+
+CMSIS DSP Software Library: Biquad Cascade IIR Filters Using Direct Form I Structure
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Biquad Cascade IIR Filters Using Direct Form I Structure

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_biquad_cascade_df1_init_f32 (arm_biquad_casd_df1_inst_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState)
void arm_biquad_cascade_df1_f32 (const arm_biquad_casd_df1_inst_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_biquad_cascade_df1_init_q31 (arm_biquad_casd_df1_inst_q31 *S, uint8_t numStages, q31_t *pCoeffs, q31_t *pState, int8_t postShift)
void arm_biquad_cascade_df1_q31 (const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_biquad_cascade_df1_fast_q31 (const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_biquad_cascade_df1_init_q15 (arm_biquad_casd_df1_inst_q15 *S, uint8_t numStages, q15_t *pCoeffs, q15_t *pState, int8_t postShift)
void arm_biquad_cascade_df1_q15 (const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_biquad_cascade_df1_fast_q15 (const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+
Detailed Description

+
This set of functions implements arbitrary order recursive (IIR) filters. The filters are implemented as a cascade of second order Biquad sections. The functions support Q15, Q31 and floating-point data types. Fast version of Q15 and Q31 also supported on CortexM4 and Cortex-M3.

+
The functions operate on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc points to the array of input data and pDst points to the array of output data. Both arrays contain blockSize values.

+
Algorithm 
Each Biquad stage implements a second order filter using the difference equation: 
   
+     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+ 
 A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage. 

+Biquad.gif
+
Single Biquad filter stage

+ Coefficients b0, b1 and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients. Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. Pay careful attention to the sign of the feedback coefficients. Some design tools use the difference equation 
   
+     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]   
+ 
 In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.

+
Higher order filters are realized as a cascade of second order sections. numStages refers to the number of second order stages used. For example, an 8th order filter would be realized with numStages=4 second order stages. 

+BiquadCascade.gif
+
8th order filter using a cascade of Biquad stages

+ A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).

+
The pState points to state variables array. Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. The state variables are arranged in the pState array as: 
   
+     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ 

+
The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. The state array has a total length of 4*numStages values. The state variables are updated after each block of data is processed, the coefficients are untouched.

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. There are separate instance structure declarations for each of the 3 supported data types.

+
Init Functions 
There is also an associated initialization function for each data type. The initialization function performs following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros before static initialization. The code below statically initializes each of the 3 different data type filter instance structures 
   
+     arm_biquad_casd_df1_inst_f32 S1 = {numStages, pState, pCoeffs};   
+     arm_biquad_casd_df1_inst_q15 S2 = {numStages, pState, pCoeffs, postShift};   
+     arm_biquad_casd_df1_inst_q31 S3 = {numStages, pState, pCoeffs, postShift};   
+ 
 where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer; pCoeffs is the address of the coefficient buffer; postShift shift to be applied.

+
Fixed-Point Behavior 
Care must be taken when using the Q15 and Q31 versions of the Biquad Cascade filter functions. Following issues must be considered:
    
+
  • Scaling of coefficients
    • 
+
  • Filter gain
    • 
+
  • Overflow and saturation
    • 
+

+

+
Scaling of coefficients:  Filter coefficients are represented as fractional values and coefficients are restricted to lie in the range [-1 +1). The fixed-point functions have an additional scaling parameter postShift which allow the filter coefficients to exceed the range [+1 -1). At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. 

+BiquadPostshift.gif
+
Fixed-point Biquad with shift by postShift bits after accumulator

+ This essentially scales the filter coefficients by 2^postShift. For example, to realize the coefficients 
   
+    {1.5, -0.8, 1.2, 1.6, -0.9}   
+ 
 set the pCoeffs array to: 
   
+    {0.75, -0.4, 0.6, 0.8, -0.45}   
+ 
 and set postShift=1

+
Filter gain:  The frequency response of a Biquad filter is a function of its coefficients. It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies. This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter. To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.

+
Overflow and saturation:  For Q15 and Q31 versions, it is described separately as part of the function specific documentation below. 

+
Function Documentation

+
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void arm_biquad_cascade_df1_init_f32 (arm_biquad_casd_df1_inst_f32 *  S, 
uint8_t  numStages, 
float32_t *  pCoeffs, 
float32_t *  pState 
)

+

+

+
+
Initialization function for the floating-point Biquad cascade filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point Biquad cascade structure. 
[in]numStagesnumber of 2nd order stages in the filter. 
[in]*pCoeffspoints to the filter coefficients array. 
[in]*pStatepoints to the state array. 

+  

+

+
Returns:
none

+
Coefficient and State Ordering:

+
The coefficients are stored in the array pCoeffs in the following order: 
   
+     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}   
+ 

+
where b1x and a1x are the coefficients for the first stage, b2x and a2x are the coefficients for the second stage, and so on. The pCoeffs array contains a total of 5*numStages values.

+
The pState is a pointer to state array. Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. The state variables are arranged in the pState array as: 
   
+     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ 
 The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. The state array has a total length of 4*numStages values. The state variables are updated after each block of data is processed; the coefficients are untouched. 

+
+
Definition at line 83 of file arm_biquad_cascade_df1_init_f32.c.

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void arm_biquad_cascade_df1_f32 (const arm_biquad_casd_df1_inst_f32 *  S, 
float32_t *  pSrc, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the floating-point Biquad cascade filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point Biquad cascade structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none. 

+
+
Definition at line 171 of file arm_biquad_cascade_df1_f32.c.

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void arm_biquad_cascade_df1_init_q31 (arm_biquad_casd_df1_inst_q31 *  S, 
uint8_t  numStages, 
q31_t *  pCoeffs, 
q31_t *  pState, 
int8_t  postShift 
)

+

+

+
+
Initialization function for the Q31 Biquad cascade filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 Biquad cascade structure. 
[in]numStagesnumber of 2nd order stages in the filter. 
[in]*pCoeffspoints to the filter coefficients buffer. 
[in]*pStatepoints to the state buffer. 
[in]postShiftShift to be applied after the accumulator. Varies according to the coefficients format 

+  

+

+
Returns:
none

+
Coefficient and State Ordering:

+
The coefficients are stored in the array pCoeffs in the following order: 
   
+     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}   
+ 
 where b1x and a1x are the coefficients for the first stage, b2x and a2x are the coefficients for the second stage, and so on. The pCoeffs array contains a total of 5*numStages values.

+
The pState points to state variables array. Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. The state variables are arranged in the pState array as: 
   
+     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ 
 The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. The state array has a total length of 4*numStages values. The state variables are updated after each block of data is processed; the coefficients are untouched. 

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 81 of file arm_biquad_cascade_df1_init_q31.c.

+
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void arm_biquad_cascade_df1_q31 (const arm_biquad_casd_df1_inst_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q31 Biquad cascade filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 Biquad cascade structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25). After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to 1.31 format by discarding the low 32 bits.

+
Refer to the function arm_biquad_cascade_df1_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4. 

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 69 of file arm_biquad_cascade_df1_q31.c.

+
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void arm_biquad_cascade_df1_fast_q31 (const arm_biquad_casd_df1_inst_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 Biquad cascade structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
This function is optimized for speed at the expense of fixed-point precision and overflow protection. The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. These intermediate results are added to a 2.30 accumulator. Finally, the accumulator is saturated and converted to a 1.31 result. The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). Use the intialization function arm_biquad_cascade_df1_init_q31() to initialize filter structure.

+
Refer to the function arm_biquad_cascade_df1_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. Both the slow and the fast versions use the same instance structure. Use the function arm_biquad_cascade_df1_init_q31() to initialize the filter structure. 

+
+
Definition at line 70 of file arm_biquad_cascade_df1_fast_q31.c.

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void arm_biquad_cascade_df1_init_q15 (arm_biquad_casd_df1_inst_q15 *  S, 
uint8_t  numStages, 
q15_t *  pCoeffs, 
q15_t *  pState, 
int8_t  postShift 
)

+

+

+
+
Initialization function for the Q15 Biquad cascade filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 Biquad cascade structure. 
[in]numStagesnumber of 2nd order stages in the filter. 
[in]*pCoeffspoints to the filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]postShiftShift to be applied to the accumulator result. Varies according to the coefficients format 

+  

+

+
Returns:
none

+
Coefficient and State Ordering:

+
The coefficients are stored in the array pCoeffs in the following order: 
   
+     {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...}   
+ 
 where b1x and a1x are the coefficients for the first stage, b2x and a2x are the coefficients for the second stage, and so on. The pCoeffs array contains a total of 6*numStages values. The zero coefficient between b1 and b2 facilities use of 16-bit SIMD instructions on the Cortex-M4.

+
The state variables are stored in the array pState. Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. The state variables are arranged in the pState array as: 
   
+     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ 
 The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. The state array has a total length of 4*numStages values. The state variables are updated after each block of data is processed; the coefficients are untouched. 

+
+
Definition at line 81 of file arm_biquad_cascade_df1_init_q15.c.

+
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void arm_biquad_cascade_df1_q15 (const arm_biquad_casd_df1_inst_q15 *  S, 
q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q15 Biquad cascade filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 Biquad cascade structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the location where the output result is written. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. The accumulator is then shifted by postShift bits to truncate the result to 1.15 format by discarding the low 16 bits. Finally, the result is saturated to 1.15 format.

+
Refer to the function arm_biquad_cascade_df1_fast_q15() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4. 

+
+
Definition at line 70 of file arm_biquad_cascade_df1_q15.c.

+
+

+

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void arm_biquad_cascade_df1_fast_q15 (const arm_biquad_casd_df1_inst_q15 *  S, 
q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 Biquad cascade structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
This fast version uses a 32-bit accumulator with 2.30 format. The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around and distorts the result. In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). The 2.30 accumulator is then shifted by postShift bits and the result truncated to 1.15 format by discarding the low 16 bits.

+
Refer to the function arm_biquad_cascade_df1_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure. Use the function arm_biquad_cascade_df1_init_q15() to initialize the filter structure. 

+
+
Definition at line 69 of file arm_biquad_cascade_df1_fast_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
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+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___biquad_cascade_d_f1__32x64.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___biquad_cascade_d_f1__32x64.html
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+
+
+
+
+CMSIS DSP Software Library: High Precision Q31 Biquad Cascade Filter
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
High Precision Q31 Biquad Cascade Filter

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+

+Functions
void arm_biquad_cas_df1_32x64_init_q31 (arm_biquad_cas_df1_32x64_ins_q31 *S, uint8_t numStages, q31_t *pCoeffs, q63_t *pState, uint8_t postShift)
void arm_biquad_cas_df1_32x64_q31 (const arm_biquad_cas_df1_32x64_ins_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+
Detailed Description

+
This function implements a high precision Biquad cascade filter which operates on Q31 data values. The filter coefficients are in 1.31 format and the state variables are in 1.63 format. The double precision state variables reduce quantization noise in the filter and provide a cleaner output. These filters are particularly useful when implementing filters in which the singularities are close to the unit circle. This is common for low pass or high pass filters with very low cutoff frequencies.

+
The function operates on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc and pDst points to input and output arrays containing blockSize Q31 values.

+
Algorithm 
Each Biquad stage implements a second order filter using the difference equation: 
   
+     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+ 
 A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage. 

+Biquad.gif
+
Single Biquad filter stage

+ Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients. Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. Pay careful attention to the sign of the feedback coefficients. Some design tools use the difference equation 
   
+     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]   
+ 
 In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.

+
Higher order filters are realized as a cascade of second order sections. numStages refers to the number of second order stages used. For example, an 8th order filter would be realized with numStages=4 second order stages. 

+BiquadCascade.gif
+
8th order filter using a cascade of Biquad stages

+ A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).

+
The pState points to state variables array . Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2] and each state variable in 1.63 format to improve precision. The state variables are arranged in the array as: 
   
+     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ 

+
The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. The state array has a total length of 4*numStages values of data in 1.63 format. The state variables are updated after each block of data is processed; the coefficients are untouched.

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.

+
Init Function 
There is also an associated initialization function which performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer. 
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros before static initialization. For example, to statically initialize the filter instance structure use 
   
+     arm_biquad_cas_df1_32x64_ins_q31 S1 = {numStages, pState, pCoeffs, postShift};   
+ 
 where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer; pCoeffs is the address of the coefficient buffer; postShift shift to be applied which is described in detail below. 

+
Fixed-Point Behavior 
Care must be taken while using Biquad Cascade 32x64 filter function. Following issues must be considered:
    
+
  • Scaling of coefficients
    • 
+
  • Filter gain
    • 
+
  • Overflow and saturation
    • 
+

+

+
Filter coefficients are represented as fractional values and restricted to lie in the range [-1 +1). The processing function has an additional scaling parameter postShift which allows the filter coefficients to exceed the range [+1 -1). At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. 

+BiquadPostshift.gif
+
Fixed-point Biquad with shift by postShift bits after accumulator

+ This essentially scales the filter coefficients by 2^postShift. For example, to realize the coefficients 
   
+    {1.5, -0.8, 1.2, 1.6, -0.9}   
+ 
 set the Coefficient array to: 
   
+    {0.75, -0.4, 0.6, 0.8, -0.45}   
+ 
 and set postShift=1

+
The second thing to keep in mind is the gain through the filter. The frequency response of a Biquad filter is a function of its coefficients. It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies. This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter. To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.

+
The third item to consider is the overflow and saturation behavior of the fixed-point Q31 version. This is described in the function specific documentation below. 

+
Function Documentation

+
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void arm_biquad_cas_df1_32x64_init_q31 (arm_biquad_cas_df1_32x64_ins_q31 *  S, 
uint8_t  numStages, 
q31_t *  pCoeffs, 
q63_t *  pState, 
uint8_t  postShift 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the high precision Q31 Biquad cascade filter structure. 
[in]numStagesnumber of 2nd order stages in the filter. 
[in]*pCoeffspoints to the filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]postShiftShift to be applied after the accumulator. Varies according to the coefficients format. 

+  

+

+
Returns:
none

+
Coefficient and State Ordering:

+
The coefficients are stored in the array pCoeffs in the following order: 
   
+     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}   
+ 
 where b1x and a1x are the coefficients for the first stage, b2x and a2x are the coefficients for the second stage, and so on. The pCoeffs array contains a total of 5*numStages values.

+
The pState points to state variables array and size of each state variable is 1.63 format. Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. The state variables are arranged in the state array as: 
   
+     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ 
 The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. The state array has a total length of 4*numStages values. The state variables are updated after each block of data is processed; the coefficients are untouched. 

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 77 of file arm_biquad_cascade_df1_32x64_init_q31.c.

+
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void arm_biquad_cas_df1_32x64_q31 (const arm_biquad_cas_df1_32x64_ins_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the high precision Q31 Biquad cascade filter. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25). After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to 1.31 format by discarding the low 32 bits.

+
Two related functions are provided in the CMSIS DSP library. arm_biquad_cascade_df1_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q63 accumulator. arm_biquad_cascade_df1_fast_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q31 accumulator. 

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 176 of file arm_biquad_cascade_df1_32x64_q31.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___biquad_cascade_d_f2_t.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___biquad_cascade_d_f2_t.html
new file mode 100644
index 000000000..f95285ba9
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@@ -0,0 +1,221 @@
+
+
+
+
+CMSIS DSP Software Library: Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+

+Functions
void arm_biquad_cascade_df2T_init_f32 (arm_biquad_cascade_df2T_instance_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState)
void arm_biquad_cascade_df2T_f32 (const arm_biquad_cascade_df2T_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)

+
Detailed Description

+
This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure. The filters are implemented as a cascade of second order Biquad sections. These functions provide a slight memory savings as compared to the direct form I Biquad filter functions. Only floating-point data is supported.

+
This function operate on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc points to the array of input data and pDst points to the array of output data. Both arrays contain blockSize values.

+
Algorithm 
Each Biquad stage implements a second order filter using the difference equation: 
   
+    y[n] = b0 * x[n] + d1   
+    d1 = b1 * x[n] + a1 * y[n] + d2   
+    d2 = b2 * x[n] + a2 * y[n]   
+ 
 where d1 and d2 represent the two state values.

+
A Biquad filter using a transposed Direct Form II structure is shown below. 

+BiquadDF2Transposed.gif
+
Single transposed Direct Form II Biquad

+ Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients. Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. Pay careful attention to the sign of the feedback coefficients. Some design tools flip the sign of the feedback coefficients: 
   
+    y[n] = b0 * x[n] + d1;   
+    d1 = b1 * x[n] - a1 * y[n] + d2;   
+    d2 = b2 * x[n] - a2 * y[n];   
+ 
 In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.

+
Higher order filters are realized as a cascade of second order sections. numStages refers to the number of second order stages used. For example, an 8th order filter would be realized with numStages=4 second order stages. A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).

+
pState points to the state variable array. Each Biquad stage has 2 state variables d1 and d2. The state variables are arranged in the pState array as: 
   
+     {d11, d12, d21, d22, ...}   
+ 
 where d1x refers to the state variables for the first Biquad and d2x refers to the state variables for the second Biquad. The state array has a total length of 2*numStages values. The state variables are updated after each block of data is processed; the coefficients are untouched.

+
The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II. The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types. That is why the Direct Form I structure supports Q15 and Q31 data types. The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2. Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad. The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.

+
Init Functions 
There is also an associated initialization function. The initialization function performs following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros before static initialization. For example, to statically initialize the instance structure use 
   
+     arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};   
+ 
 where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer. pCoeffs is the address of the coefficient buffer; 

+
Function Documentation

+
+

+

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void arm_biquad_cascade_df2T_init_f32 (arm_biquad_cascade_df2T_instance_f32 *  S, 
uint8_t  numStages, 
float32_t *  pCoeffs, 
float32_t *  pState 
)

+

+

+
+
Initialization function for the floating-point transposed direct form II Biquad cascade filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the filter data structure. 
[in]numStagesnumber of 2nd order stages in the filter. 
[in]*pCoeffspoints to the filter coefficients. 
[in]*pStatepoints to the state buffer. 

+  

+

+
Returns:
none

+
Coefficient and State Ordering: 

+
The coefficients are stored in the array pCoeffs in the following order: 
   
+     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}   
+ 

+
where b1x and a1x are the coefficients for the first stage, b2x and a2x are the coefficients for the second stage, and so on. The pCoeffs array contains a total of 5*numStages values.

+
The pState is a pointer to state array. Each Biquad stage has 2 state variables d1, and d2. The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. The state array has a total length of 2*numStages values. The state variables are updated after each block of data is processed; the coefficients are untouched. 

+
+
Definition at line 73 of file arm_biquad_cascade_df2T_init_f32.c.

+
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void arm_biquad_cascade_df2T_f32 (const arm_biquad_cascade_df2T_instance_f32 *  S, 
float32_t *  pSrc, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the floating-point transposed direct form II Biquad cascade filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the filter data structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
+
Definition at line 143 of file arm_biquad_cascade_df2T_f32.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___c_f_f_t___c_i_f_f_t.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___c_f_f_t___c_i_f_f_t.html
new file mode 100644
index 000000000..eb144c9f7
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+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___c_f_f_t___c_i_f_f_t.html
@@ -0,0 +1,570 @@
+
+
+
+
+CMSIS DSP Software Library: Complex FFT Functions
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
Complex FFT Functions

+
+[Transform Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Functions
arm_status arm_cfft_radix4_init_f32 (arm_cfft_radix4_instance_f32 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
void arm_cfft_radix4_f32 (const arm_cfft_radix4_instance_f32 *S, float32_t *pSrc)
arm_status arm_cfft_radix4_init_q31 (arm_cfft_radix4_instance_q31 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
void arm_cfft_radix4_q31 (const arm_cfft_radix4_instance_q31 *S, q31_t *pSrc)
arm_status arm_cfft_radix4_init_q15 (arm_cfft_radix4_instance_q15 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
void arm_cfft_radix4_q15 (const arm_cfft_radix4_instance_q15 *S, q15_t *pSrc)

+Variables
static const float32_t twiddleCoef [2048]
static const q31_t twiddleCoefQ31 [2048]
static const q15_t twiddleCoefQ15 [2048]
const uint16_t armBitRevTable [256]

+
Detailed Description

+
Complex Fast Fourier Transform(CFFT) and Complex Inverse Fast Fourier Transform(CIFFT) is an efficient algorithm to compute Discrete Fourier Transform(DFT) and Inverse Discrete Fourier Transform(IDFT). Computational complexity of CFFT reduces drastically when compared to DFT. 

+
This set of functions implements CFFT/CIFFT for Q15, Q31, and floating-point data types. The functions operates on in-place buffer which uses same buffer for input and output. Complex input is stored in input buffer in an interleaved fashion.

+
The functions operate on blocks of input and output data and each call to the function processes 2*fftLen samples through the transform. pSrc points to In-place arrays containing 2*fftLen values. 

+
The pSrc points to the array of in-place buffer of size 2*fftLen and inputs and outputs are stored in an interleaved fashion as shown below. 
 {real[0], imag[0], real[1], imag[1],..} 

+
Lengths supported by the transform: 

+
Internally, the function utilize a radix-4 decimation in frequency(DIF) algorithm and the size of the FFT supported are of the lengths [16, 64, 256, 1024].

+
Algorithm: 

+
Complex Fast Fourier Transform: 

+
Input real and imaginary data: 
   
+ x(n) = xa + j * ya   
+ x(n+N/4 ) = xb + j * yb   
+ x(n+N/2 ) = xc + j * yc   
+ x(n+3N 4) = xd + j * yd   
+ 
 where N is length of FFT 

+
Output real and imaginary data: 
   
+ X(4r) = xa'+ j * ya'   
+ X(4r+1) = xb'+ j * yb'   
+ X(4r+2) = xc'+ j * yc'   
+ X(4r+3) = xd'+ j * yd'   
+ 
 

+
Twiddle factors for radix-4 FFT: 
   
+ Wn = co1 + j * (- si1)   
+ W2n = co2 + j * (- si2)   
+ W3n = co3 + j * (- si3)   
+ 

+

+CFFT.gif
+
Radix-4 Decimation-in Frequency Complex Fast Fourier Transform

+

+
Output from Radix-4 CFFT Results in Digit reversal order. Interchange middle two branches of every butterfly results in Bit reversed output. 

+
 Butterfly CFFT equations: 
   
+ xa' = xa + xb + xc + xd   
+ ya' = ya + yb + yc + yd   
+ xc' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)   
+ yc' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)   
+ xb' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)   
+ yb' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)   
+ xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)   
+ yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)   
+ 

+
Complex Inverse Fast Fourier Transform: 

+
CIFFT uses same twiddle factor table as CFFT with modifications in the design equation as shown below.

+
 Modified Butterfly CIFFT equations: 
   
+ xa' = xa + xb + xc + xd   
+ ya' = ya + yb + yc + yd   
+ xc' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)   
+ yc' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)   
+ xb' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)   
+ yb' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)   
+ xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)   
+ yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)   
+ 

+
Instance Structure 
A separate instance structure must be defined for each Instance but the twiddle factors and bit reversal tables can be reused. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Initializes twiddle factor table and bit reversal table pointers 
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Manually initialize the instance structure as follows: 
   
+arm_cfft_radix4_instance_f32 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor, onebyfftLen};   
+arm_cfft_radix4_instance_q31 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};   
+arm_cfft_radix4_instance_q15 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};   
+ 
 

+
where fftLen length of CFFT/CIFFT; ifftFlag Flag for selection of CFFT or CIFFT(Set ifftFlag to calculate CIFFT otherwise calculates CFFT); bitReverseFlag Flag for selection of output order(Set bitReverseFlag to output in normal order otherwise output in bit reversed order); pTwiddlepoints to array of twiddle coefficients; pBitRevTable points to the array of bit reversal table. twidCoefModifier modifier for twiddle factor table which supports all FFT lengths with same table; pBitRevTable modifier for bit reversal table which supports all FFT lengths with same table. onebyfftLen value of 1/fftLen to calculate CIFFT;

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the CFFT/CIFFT function. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

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arm_status arm_cfft_radix4_init_f32 (arm_cfft_radix4_instance_f32 *  S, 
uint16_t  fftLen, 
uint8_t  ifftFlag, 
uint8_t  bitReverseFlag 
)

+

+

+
+
Initialization function for the floating-point CFFT/CIFFT. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point CFFT/CIFFT structure. 
[in]fftLenlength of the FFT. 
[in]ifftFlagflag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.

+
Description: 

+
The parameter ifftFlag controls whether a forward or inverse transform is computed. Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated 

+
The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 

+
The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. 

+
This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. 

+
Examples: 
arm_convolution_example_f32.c, and arm_fft_bin_example_f32.c.

+

+
Definition at line 1118 of file arm_cfft_radix4_init_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cfft_radix4_f32 (const arm_cfft_radix4_instance_f32 *  S, 
float32_t *  pSrc 
)

+

+

+
+
Processing function for the floating-point CFFT/CIFFT. 

+
Parameters:

+  
+    
+    
+  
[in]*Spoints to an instance of the floating-point CFFT/CIFFT structure. 
[in,out]*pSrcpoints to the complex data buffer of size 2*fftLen. Processing occurs in-place. 

+  

+

+
Returns:
none. 

+
Examples: 
arm_convolution_example_f32.c, and arm_fft_bin_example_f32.c.

+

+
Definition at line 177 of file arm_cfft_radix4_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
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+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_cfft_radix4_init_q31 (arm_cfft_radix4_instance_q31 *  S, 
uint16_t  fftLen, 
uint8_t  ifftFlag, 
uint8_t  bitReverseFlag 
)

+

+

+
+
Initialization function for the Q31 CFFT/CIFFT. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 CFFT/CIFFT structure. 
[in]fftLenlength of the FFT. 
[in]ifftFlagflag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.

+
Description: 

+
The parameter ifftFlag controls whether a forward or inverse transform is computed. Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated 

+
The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 

+
The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. 

+
This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. 

+
+
Definition at line 608 of file arm_cfft_radix4_init_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cfft_radix4_q31 (const arm_cfft_radix4_instance_q31 *  S, 
q31_t *  pSrc 
)

+

+

+
+
Processing function for the Q31 CFFT/CIFFT. 

+
Parameters:

+  
+    
+    
+  
[in]*Spoints to an instance of the Q31 CFFT/CIFFT structure. 
[in,out]*pSrcpoints to the complex data buffer of size 2*fftLen. Processing occurs in-place. 

+  

+

+
Returns:
none.

+
Input and output formats: 

+
Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. Hence the output format is different for different FFT sizes. The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT: 

+

+CFFTQ31.gif
+
Input and Output Formats for Q31 CFFT

+ 

+CIFFTQ31.gif
+
Input and Output Formats for Q31 CIFFT

+ 

+
+
Definition at line 66 of file arm_cfft_radix4_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
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+          
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+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_cfft_radix4_init_q15 (arm_cfft_radix4_instance_q15 *  S, 
uint16_t  fftLen, 
uint8_t  ifftFlag, 
uint8_t  bitReverseFlag 
)

+

+

+
+
Initialization function for the Q15 CFFT/CIFFT. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 CFFT/CIFFT structure. 
[in]fftLenlength of the FFT. 
[in]ifftFlagflag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.

+
Description: 

+
The parameter ifftFlag controls whether a forward or inverse transform is computed. Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated 

+
The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 

+
The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. 

+
This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. 

+
+
Definition at line 353 of file arm_cfft_radix4_init_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cfft_radix4_q15 (const arm_cfft_radix4_instance_q15 *  S, 
q15_t *  pSrc 
)

+

+

+
+
Processing function for the Q15 CFFT/CIFFT. 

+
Parameters:

+  
+    
+    
+  
[in]*Spoints to an instance of the Q15 CFFT/CIFFT structure. 
[in,out]*pSrcpoints to the complex data buffer. Processing occurs in-place. 

+  

+

+
Returns:
none.

+
Input and output formats: 

+
Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. Hence the output format is different for different FFT sizes. The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT: 

+

+CFFTQ15.gif
+
Input and Output Formats for Q15 CFFT

+ 

+CIFFTQ15.gif
+
Input and Output Formats for Q15 CIFFT

+ 

+
+
Definition at line 66 of file arm_cfft_radix4_q15.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float32_t twiddleCoef[2048] [static]

+

+

+
Example code for Floating-point Twiddle factors Generation: 

+
for(i = 0; i< N; i++)   
+ {   
+	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);   
+	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);   
+ } 
 

+
where N = 1024 and PI = 3.14159265358979 

+
Cos and Sin values are in interleaved fashion 

+
+
Definition at line 70 of file arm_cfft_radix4_init_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t twiddleCoefQ31[2048] [static]

+

+

+
Example code for Q31 Twiddle factors Generation:: 

+
for(i = 0; i< N; i++)   
+ {   
+    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);   
+    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);   
+ } 
 

+
where N = 1024 and PI = 3.14159265358979 

+
Cos and Sin values are interleaved fashion 

+
Convert Floating point to Q31(Fixed point 1.31): round(twiddleCoefQ31(i) * pow(2, 31)) 

+
+
Definition at line 71 of file arm_cfft_radix4_init_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t twiddleCoefQ15[2048] [static]

+

+

+
Example code for Q15 Twiddle factors Generation:: 

+
for(i = 0; i< N; i++)   
+ {   
+	twiddleCoefQ15[2*i]= cos(i * 2*PI/(float)N);   
+	twiddleCoefQ15[2*i+1]= sin(i * 2*PI/(float)N);   
+ } 
 

+
where N = 1024 and PI = 3.14159265358979 

+
Cos and Sin values are interleaved fashion 

+
Convert Floating point to Q15(Fixed point 1.15): round(twiddleCoefQ15(i) * pow(2, 15)) 

+
+
Definition at line 72 of file arm_cfft_radix4_init_q15.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const uint16_t armBitRevTable[256]

+

+

+
Pseudo code for Generation of Bit reversal Table is 

+
for(l=1;l <= N/4;l++)   
+ {   
+   for(i=0;i<logN2;i++)   
+   {    
+     a[i]=l&(1<<i);   
+   }   
+   for(j=0; j<logN2; j++)   
+   {   
+     if (a[j]!=0)   
+     y[l]+=(1<<((logN2-1)-j));   
+   }   
+   y[l] = y[l] >> 1;   
+  } 
 

+
where N = 1024 logN2 = 10 

+
N is the maximum FFT Size supported 

+
+
Definition at line 68 of file arm_common_tables.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___class_marks.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___class_marks.html
new file mode 100644
index 000000000..f9cc050a7
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___class_marks.html
@@ -0,0 +1,98 @@
+
+
+
+
+CMSIS DSP Software Library: Class Marks Example
+
+
+
+
+
+
+
+
+
+

+  

+
Class Marks Example

+
+[Examples]
+
  

+

+

+
+

+
Description: 

+
Demonstrates the use the Maximum, Minimum, Mean, Standard Deviation, Variance and Matrix functions to calculate statistical values of marks obtained in a class.

+
Note:
This example also demonstrates the usage of static initialization.

+
Variables Description:

+
    
+
  • testMarks_f32 points to the marks scored by 20 students in 4 subjects 
    • 
+
  • max_marks Maximum of all marks 
    • 
+
  • min_marks Minimum of all marks 
    • 
+
  • mean Mean of all marks 
    • 
+
  • var Variance of the marks 
    • 
+
  • std Standard deviation of the marks 
    • 
+
  • numStudents Total number of students in the class
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_class_marks_example_f32.c 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___cmplx_by_cmplx_mult.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___cmplx_by_cmplx_mult.html
new file mode 100644
index 000000000..6b7fb8918
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___cmplx_by_cmplx_mult.html
@@ -0,0 +1,253 @@
+
+
+
+
+CMSIS DSP Software Library: Complex-by-Complex Multiplication
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Complex-by-Complex Multiplication

+
+[Complex Math Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_cmplx_mult_cmplx_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t numSamples)
void arm_cmplx_mult_cmplx_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t numSamples)
void arm_cmplx_mult_cmplx_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t numSamples)

+
Detailed Description

+
Multiplies a complex vector by another complex vector and generates a complex result. The data in the complex arrays is stored in an interleaved fashion (real, imag, real, imag, ...). The parameter numSamples represents the number of complex samples processed. The complex arrays have a total of 2*numSamples real values.

+
The underlying algorithm is used:

+
   
+ for(n=0; n<numSamples; n++) {   
+     pDst[(2*n)+0] = pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1];   
+     pDst[(2*n)+1] = pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0];   
+ }   
+ 
There are separate functions for floating-point, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
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+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_mult_cmplx_f32 (float32_t *  pSrcA, 
float32_t *  pSrcB, 
float32_t *  pDst, 
uint32_t  numSamples 
)

+

+

+
+
Floating-point complex-by-complex multiplication. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]numSamplesnumber of complex samples in each vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_convolution_example_f32.c.

+

+
Definition at line 73 of file arm_cmplx_mult_cmplx_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_mult_cmplx_q31 (q31_t *  pSrcA, 
q31_t *  pSrcB, 
q31_t *  pDst, 
uint32_t  numSamples 
)

+

+

+
+
Q31 complex-by-complex multiplication. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]numSamplesnumber of complex samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format. Input down scaling is not required. 

+
+
Definition at line 56 of file arm_cmplx_mult_cmplx_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_mult_cmplx_q15 (q15_t *  pSrcA, 
q15_t *  pSrcB, 
q15_t *  pDst, 
uint32_t  numSamples 
)

+

+

+
+
Q15 complex-by-complex multiplication. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]numSamplesnumber of complex samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format. 

+
+
Definition at line 54 of file arm_cmplx_mult_cmplx_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___cmplx_by_real_mult.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___cmplx_by_real_mult.html
new file mode 100644
index 000000000..c2c76f684
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___cmplx_by_real_mult.html
@@ -0,0 +1,252 @@
+
+
+
+
+CMSIS DSP Software Library: Complex-by-Real Multiplication
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Complex-by-Real Multiplication

+
+[Complex Math Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_cmplx_mult_real_f32 (float32_t *pSrcCmplx, float32_t *pSrcReal, float32_t *pCmplxDst, uint32_t numSamples)
void arm_cmplx_mult_real_q31 (q31_t *pSrcCmplx, q31_t *pSrcReal, q31_t *pCmplxDst, uint32_t numSamples)
void arm_cmplx_mult_real_q15 (q15_t *pSrcCmplx, q15_t *pSrcReal, q15_t *pCmplxDst, uint32_t numSamples)

+
Detailed Description

+
Multiplies a complex vector by a real vector and generates a complex result. The data in the complex arrays is stored in an interleaved fashion (real, imag, real, imag, ...). The parameter numSamples represents the number of complex samples processed. The complex arrays have a total of 2*numSamples real values while the real array has a total of numSamples real values.

+
The underlying algorithm is used:

+
   
+ for(n=0; n<numSamples; n++) {   
+     pCmplxDst[(2*n)+0] = pSrcCmplx[(2*n)+0] * pSrcReal[n];   
+     pCmplxDst[(2*n)+1] = pSrcCmplx[(2*n)+1] * pSrcReal[n];   
+ }   
+ 
There are separate functions for floating-point, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_mult_real_f32 (float32_t *  pSrcCmplx, 
float32_t *  pSrcReal, 
float32_t *  pCmplxDst, 
uint32_t  numSamples 
)

+

+

+
+
Floating-point complex-by-real multiplication. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcCmplxpoints to the complex input vector 
[in]*pSrcRealpoints to the real input vector 
[out]*pCmplxDstpoints to the complex output vector 
[in]numSamplesnumber of samples in each vector 

+  

+

+
Returns:
none. 

+
+
Definition at line 74 of file arm_cmplx_mult_real_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_mult_real_q31 (q31_t *  pSrcCmplx, 
q31_t *  pSrcReal, 
q31_t *  pCmplxDst, 
uint32_t  numSamples 
)

+

+

+
+
Q31 complex-by-real multiplication. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcCmplxpoints to the complex input vector 
[in]*pSrcRealpoints to the real input vector 
[out]*pCmplxDstpoints to the complex output vector 
[in]numSamplesnumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated. 

+
+
Definition at line 56 of file arm_cmplx_mult_real_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_mult_real_q15 (q15_t *  pSrcCmplx, 
q15_t *  pSrcReal, 
q15_t *  pCmplxDst, 
uint32_t  numSamples 
)

+

+

+
+
Q15 complex-by-real multiplication. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcCmplxpoints to the complex input vector 
[in]*pSrcRealpoints to the real input vector 
[out]*pCmplxDstpoints to the complex output vector 
[in]numSamplesnumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 

+
+
Definition at line 56 of file arm_cmplx_mult_real_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___conv.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___conv.html
new file mode 100644
index 000000000..3a1f922ba
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___conv.html
@@ -0,0 +1,475 @@
+
+
+
+
+CMSIS DSP Software Library: Convolution
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Convolution

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_conv_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst)
void arm_conv_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
void arm_conv_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
void arm_conv_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
void arm_conv_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
void arm_conv_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst)

+
Detailed Description

+
Convolution is a mathematical operation that operates on two finite length vectors to generate a finite length output vector. Convolution is similar to correlation and is frequently used in filtering and data analysis. The CMSIS DSP library contains functions for convolving Q7, Q15, Q31, and floating-point data types. The library also provides fast versions of the Q15 and Q31 functions on Cortex-M4 and Cortex-M3.

+
Algorithm 
Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively. Then the convolution

+
   
+                   c[n] = a[n] * b[n]   
+ 
is defined as 

+ConvolutionEquation.gif
+

+ 

+
Note that c[n] is of length srcALen + srcBLen - 1 and is defined over the interval n=0, 1, 2, ..., srcALen + srcBLen - 2. pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen. The output result is written to pDst and the calling function must allocate srcALen+srcBLen-1 words for the result.

+
Conceptually, when two signals a[n] and b[n] are convolved, the signal b[n] slides over a[n]. For each offset n, the overlapping portions of a[n] and b[n] are multiplied and summed together.

+
Note that convolution is a commutative operation:

+
   
+                   a[n] * b[n] = b[n] * a[n].   
+ 
This means that switching the A and B arguments to the convolution functions has no effect.

+
Fixed-Point Behavior

+
Convolution requires summing up a large number of intermediate products. As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation. Refer to the function specific documentation below for further details of the particular algorithm used. 

+
Function Documentation

+
+

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void arm_conv_f32 (float32_t *  pSrcA, 
uint32_t  srcALen, 
float32_t *  pSrcB, 
uint32_t  srcBLen, 
float32_t *  pDst 
)

+

+

+
+
Convolution of floating-point sequences. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 

+  

+

+
Returns:
none. 

+
+
Definition at line 103 of file arm_conv_f32.c.

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void arm_conv_q31 (q31_t *  pSrcA, 
uint32_t  srcALen, 
q31_t *  pSrcB, 
uint32_t  srcBLen, 
q31_t *  pDst 
)

+

+

+
+
Convolution of Q31 sequences. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, as maximum of min(srcALen, srcBLen) number of additions are carried internally. The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.

+
See arm_conv_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4. 

+
+
Definition at line 71 of file arm_conv_q31.c.

+
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void arm_conv_fast_q31 (q31_t *  pSrcA, 
uint32_t  srcALen, 
q31_t *  pSrcB, 
uint32_t  srcBLen, 
q31_t *  pDst 
)

+

+

+
+
Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
This function is optimized for speed at the expense of fixed-point precision and overflow protection. The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 format. Finally, the accumulator is saturated and converted to a 1.31 result.

+
The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result. In order to avoid overflows completely the input signals must be scaled down. Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, as maximum of min(srcALen, srcBLen) number of additions are carried internally.

+
See arm_conv_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. 

+
+
Definition at line 68 of file arm_conv_fast_q31.c.

+
+

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void arm_conv_q15 (q15_t *  pSrcA, 
uint32_t  srcALen, 
q15_t *  pSrcB, 
uint32_t  srcBLen, 
q15_t *  pDst 
)

+

+

+
+
Convolution of Q15 sequences. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 64-bit internal accumulator. Both inputs are in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. This approach provides 33 guard bits and there is no risk of overflow. The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.

+
Refer to arm_conv_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4. 

+
+
Definition at line 68 of file arm_conv_q15.c.

+
+

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void arm_conv_fast_q15 (q15_t *  pSrcA, 
uint32_t  srcALen, 
q15_t *  pSrcB, 
uint32_t  srcBLen, 
q15_t *  pDst 
)

+

+

+
+
Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
This fast version uses a 32-bit accumulator with 2.30 format. The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, as maximum of min(srcALen, srcBLen) number of additions are carried internally. The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.

+
See arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. 

+
+
Definition at line 66 of file arm_conv_fast_q15.c.

+
+

+

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+      
void arm_conv_q7 (q7_t *  pSrcA, 
uint32_t  srcALen, 
q7_t *  pSrcB, 
uint32_t  srcBLen, 
q7_t *  pDst 
)

+

+

+
+
Convolution of Q7 sequences. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 32-bit internal accumulator. Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format. 

+
+
Definition at line 65 of file arm_conv_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___convolution_example.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___convolution_example.html
new file mode 100644
index 000000000..5e00fd1c0
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___convolution_example.html
@@ -0,0 +1,105 @@
+
+
+
+
+CMSIS DSP Software Library: Convolution Example
+
+
+
+
+
+
+
+
+
+

+  

+
Convolution Example

+
+[Examples]
+
  

+

+

+
+

+
Description: 

+
Demonstrates the convolution theorem with the use of the Complex FFT, Complex-by-Complex Multiplication, and Support Functions.

+
Algorithm:

+
The convolution theorem states that convolution in the time domain corresponds to multiplication in the frequency domain. Therefore, the Fourier transform of the convoution of two signals is equal to the product of their individual Fourier transforms. The Fourier transform of a signal can be evaluated efficiently using the Fast Fourier Transform (FFT). 

+
Two input signals, a[n] and b[n], with lengths n1 and n2 respectively, are zero padded so that their lengths become N, which is greater than or equal to (n1+n2-1) and is a power of 4 as FFT implementation is radix-4. The convolution of a[n] and b[n] is obtained by taking the FFT of the input signals, multiplying the Fourier transforms of the two signals, and taking the inverse FFT of the multiplied result. 

+
This is denoted by the following equations: 
 A[k] = FFT(a[n],N)
+ B[k] = FFT(b[n],N)
+ conv(a[n], b[n]) = IFFT(A[k] * B[k], N)
 where A[k] and B[k] are the N-point FFTs of the signals a[n] and b[n] respectively. The length of the convolved signal is (n1+n2-1).

+
Block Diagram:

+

+Convolution.gif
+

+

+
Variables Description:

+
    
+
  • testInputA_f32 points to the first input sequence 
    • 
+
  • srcALen length of the first input sequence 
    • 
+
  • testInputB_f32 points to the second input sequence 
    • 
+
  • srcBLen length of the second input sequence 
    • 
+
  • outLen length of convolution output sequence, (srcALen + srcBLen - 1) 
    • 
+
  • AxB points to the output array where the product of individual FFTs of inputs is stored.
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_convolution_example_f32.c 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___corr.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___corr.html
new file mode 100644
index 000000000..017f5b4e0
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@@ -0,0 +1,474 @@
+
+
+
+
+CMSIS DSP Software Library: Correlation
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Correlation

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_correlate_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst)
void arm_correlate_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
void arm_correlate_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
void arm_correlate_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
void arm_correlate_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
void arm_correlate_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst)

+
Detailed Description

+
Correlation is a mathematical operation that is similar to convolution. As with convolution, correlation uses two signals to produce a third signal. The underlying algorithms in correlation and convolution are identical except that one of the inputs is flipped in convolution. Correlation is commonly used to measure the similarity between two signals. It has applications in pattern recognition, cryptanalysis, and searching. The CMSIS library provides correlation functions for Q7, Q15, Q31 and floating-point data types. Fast versions of the Q15 and Q31 functions are also provided.

+
Algorithm 
Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively. The convolution of the two signals is denoted by 
   
+                   c[n] = a[n] * b[n]   
+ 
 In correlation, one of the signals is flipped in time 
   
+                   c[n] = a[n] * b[-n]   
+ 

+
and this is mathematically defined as 

+CorrelateEquation.gif
+

+ 

+
The pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen. The result c[n] is of length 2 * max(srcALen, srcBLen) - 1 and is defined over the interval n=0, 1, 2, ..., (2 * max(srcALen, srcBLen) - 2). The output result is written to pDst and the calling function must allocate 2 * max(srcALen, srcBLen) - 1 words for the result.

+
Note 

+
The pDst should be initialized to all zeros before being used.

+
Fixed-Point Behavior 

+
Correlation requires summing up a large number of intermediate products. As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation. Refer to the function specific documentation below for further details of the particular algorithm used. 

+
Function Documentation

+
+

+

+      
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void arm_correlate_f32 (float32_t *  pSrcA, 
uint32_t  srcALen, 
float32_t *  pSrcB, 
uint32_t  srcBLen, 
float32_t *  pDst 
)

+

+

+
+
Correlation of floating-point sequences. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 

+  

+

+
Returns:
none. 

+
+
Definition at line 95 of file arm_correlate_f32.c.

+
+

+

+
+

+

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void arm_correlate_q31 (q31_t *  pSrcA, 
uint32_t  srcALen, 
q31_t *  pSrcB, 
uint32_t  srcBLen, 
q31_t *  pDst 
)

+

+

+
+
Correlation of Q31 sequences. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a maximum of min(srcALen, srcBLen) number of additions is carried internally. The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.

+
See arm_correlate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4. 

+
+
Definition at line 71 of file arm_correlate_q31.c.

+
+

+

+
+

+

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+      
void arm_correlate_fast_q31 (q31_t *  pSrcA, 
uint32_t  srcALen, 
q31_t *  pSrcB, 
uint32_t  srcBLen, 
q31_t *  pDst 
)

+

+

+
+
Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
This function is optimized for speed at the expense of fixed-point precision and overflow protection. The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 format. Finally, the accumulator is saturated and converted to a 1.31 result.

+
The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result. In order to avoid overflows completely the input signals must be scaled down. The input signals should be scaled down to avoid intermediate overflows. Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a maximum of min(srcALen, srcBLen) number of additions is carried internally.

+
See arm_correlate_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. 

+
+
Definition at line 70 of file arm_correlate_fast_q31.c.

+
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void arm_correlate_q15 (q15_t *  pSrcA, 
uint32_t  srcALen, 
q15_t *  pSrcB, 
uint32_t  srcBLen, 
q15_t *  pDst 
)

+

+

+
+
Correlation of Q15 sequences. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 64-bit internal accumulator. Both inputs are in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. This approach provides 33 guard bits and there is no risk of overflow. The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.

+
Refer to arm_correlate_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4. 

+
+
Definition at line 68 of file arm_correlate_q15.c.

+
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void arm_correlate_fast_q15 (q15_t *  pSrcA, 
uint32_t  srcALen, 
q15_t *  pSrcB, 
uint32_t  srcBLen, 
q15_t *  pDst 
)

+

+

+
+
Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
This fast version uses a 32-bit accumulator with 2.30 format. The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a maximum of min(srcALen, srcBLen) number of additions is carried internally. The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.

+
See arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. 

+
+
Definition at line 66 of file arm_correlate_fast_q15.c.

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void arm_correlate_q7 (q7_t *  pSrcA, 
uint32_t  srcALen, 
q7_t *  pSrcB, 
uint32_t  srcBLen, 
q7_t *  pDst 
)

+

+

+
+
Correlation of Q7 sequences. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 32-bit internal accumulator. Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format. 

+
+
Definition at line 65 of file arm_correlate_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___d_c_t4___i_d_c_t4.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___d_c_t4___i_d_c_t4.html
new file mode 100644
index 000000000..8a777ed0d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___d_c_t4___i_d_c_t4.html
@@ -0,0 +1,839 @@
+
+
+
+
+CMSIS DSP Software Library: DCT Type IV Functions
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
DCT Type IV Functions

+
+[Transform Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+

+Functions
arm_status arm_dct4_init_f32 (arm_dct4_instance_f32 *S, arm_rfft_instance_f32 *S_RFFT, arm_cfft_radix4_instance_f32 *S_CFFT, uint16_t N, uint16_t Nby2, float32_t normalize)
void arm_dct4_f32 (const arm_dct4_instance_f32 *S, float32_t *pState, float32_t *pInlineBuffer)
arm_status arm_dct4_init_q31 (arm_dct4_instance_q31 *S, arm_rfft_instance_q31 *S_RFFT, arm_cfft_radix4_instance_q31 *S_CFFT, uint16_t N, uint16_t Nby2, q31_t normalize)
void arm_dct4_q31 (const arm_dct4_instance_q31 *S, q31_t *pState, q31_t *pInlineBuffer)
arm_status arm_dct4_init_q15 (arm_dct4_instance_q15 *S, arm_rfft_instance_q15 *S_RFFT, arm_cfft_radix4_instance_q15 *S_CFFT, uint16_t N, uint16_t Nby2, q15_t normalize)
void arm_dct4_q15 (const arm_dct4_instance_q15 *S, q15_t *pState, q15_t *pInlineBuffer)

+Variables
static const float32_t Weights_128 [256]
static const float32_t Weights_512 [1024]
static const float32_t Weights_2048 [4096]
static const float32_t cos_factors_128 [128]
static const float32_t cos_factors_512 [512]
static const float32_t cos_factors_2048 [2048]
static const q31_t WeightsQ31_128 [256]
static const q31_t WeightsQ31_512 [1024]
static const q31_t WeightsQ31_2048 [4096]
static const q31_t cos_factorsQ31_128 [128]
static const q31_t cos_factorsQ31_512 [512]
static const q31_t cos_factorsQ31_2048 [2048]
static const q15_t WeightsQ15_128 [256]
static const q15_t WeightsQ15_512 [1024]
static const q15_t WeightsQ15_2048 [4096]
static const q15_t cos_factorsQ15_128 [128]
static const q15_t cos_factorsQ15_512 [512]
static const q15_t cos_factorsQ15_2048 [2048]

+
Detailed Description

+
Representation of signals by minimum number of values is important for storage and transmission. The possibility of large discontinuity between the beginning and end of a period of a signal in DFT can be avoided by extending the signal so that it is even-symmetric. Discrete Cosine Transform (DCT) is constructed such that its energy is heavily concentrated in the lower part of the spectrum and is very widely used in signal and image coding applications. The family of DCTs (DCT type- 1,2,3,4) is the outcome of different combinations of homogeneous boundary conditions. DCT has an excellent energy-packing capability, hence has many applications and in data compression in particular.

+
DCT is essentially the Discrete Fourier Transform(DFT) of an even-extended real signal. Reordering of the input data makes the computation of DCT just a problem of computing the DFT of a real signal with a few additional operations. This approach provides regular, simple, and very efficient DCT algorithms for practical hardware and software implementations.

+
DCT type-II can be implemented using Fast fourier transform (FFT) internally, as the transform is applied on real values, Real FFT can be used. DCT4 is implemented using DCT2 as their implementations are similar except with some added pre-processing and post-processing. DCT2 implementation can be described in the following steps:

+
    
+
  • Re-ordering input
    • 
+
  • Calculating Real FFT
    • 
+
  • Multiplication of weights and Real FFT output and getting real part from the product.
    • 
+

+
This process is explained by the block diagram below: 

+

+DCT4.gif
+
Discrete Cosine Transform - type-IV

+
Algorithm: 
The N-point type-IV DCT is defined as a real, linear transformation by the formula: 

+DCT4Equation.gif
+

+ where k = 0,1,2,.....N-1 

+
Its inverse is defined as follows: 

+IDCT4Equation.gif
+

+ where n = 0,1,2,.....N-1 

+
The DCT4 matrices become involutory (i.e. they are self-inverse) by multiplying with an overall scale factor of sqrt(2/N). The symmetry of the transform matrix indicates that the fast algorithms for the forward and inverse transform computation are identical. Note that the implementation of Inverse DCT4 and DCT4 is same, hence same process function can be used for both.

+
Lengths supported by the transform: 
As DCT4 internally uses Real FFT, it supports all the lengths supported by arm_rfft_f32(). The library provides separate functions for Q15, Q31, and floating-point data types. 

+
Instance Structure 
The instances for Real FFT and FFT, cosine values table and twiddle factor table are stored in an instance data structure. A separate instance structure must be defined for each transform. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Initializes Real FFT as its process function is used internally in DCT4, by calling arm_rfft_init_f32(). 
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Manually initialize the instance structure as follows: 
   
+arm_dct4_instance_f32 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};   
+arm_dct4_instance_q31 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};  
+arm_dct4_instance_q15 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};  
+ 
 where N is the length of the DCT4; Nby2 is half of the length of the DCT4; normalize is normalizing factor used and is equal to sqrt(2/N); pTwiddle points to the twiddle factor table; pCosFactor points to the cosFactor table; pRfft points to the real FFT instance; pCfft points to the complex FFT instance; The CFFT and RFFT structures also needs to be initialized, refer to arm_cfft_radix4_f32() and arm_rfft_f32() respectively for details regarding static initialization.

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the DCT4 transform functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

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arm_status arm_dct4_init_f32 (arm_dct4_instance_f32 *  S, 
arm_rfft_instance_f32 *  S_RFFT, 
arm_cfft_radix4_instance_f32 *  S_CFFT, 
uint16_t  N, 
uint16_t  Nby2, 
float32_t  normalize 
)

+

+

+
+
Initialization function for the floating-point DCT4/IDCT4. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of floating-point DCT4/IDCT4 structure. 
[in]*S_RFFTpoints to an instance of floating-point RFFT/RIFFT structure. 
[in]*S_CFFTpoints to an instance of floating-point CFFT/CIFFT structure. 
[in]Nlength of the DCT4. 
[in]Nby2half of the length of the DCT4. 
[in]normalizenormalizing factor. 

+  

+

+
Returns:
arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. 

+
Normalizing factor: 
The normalizing factor is sqrt(2/N), which depends on the size of transform N. Floating-point normalizing factors are mentioned in the table below for different DCT sizes: 

+dct4NormalizingF32Table.gif
+

+ 

+
+
Definition at line 4142 of file arm_dct4_init_f32.c.

+
+

+

+
+

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+      
void arm_dct4_f32 (const arm_dct4_instance_f32 *  S, 
float32_t *  pState, 
float32_t *  pInlineBuffer 
)

+

+

+
+
Processing function for the floating-point DCT4/IDCT4. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point DCT4/IDCT4 structure. 
[in]*pStatepoints to state buffer. 
[in,out]*pInlineBufferpoints to the in-place input and output buffer. 

+  

+

+
Returns:
none. 

+
+
Definition at line 126 of file arm_dct4_f32.c.

+
+

+

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arm_status arm_dct4_init_q31 (arm_dct4_instance_q31 *  S, 
arm_rfft_instance_q31 *  S_RFFT, 
arm_cfft_radix4_instance_q31 *  S_CFFT, 
uint16_t  N, 
uint16_t  Nby2, 
q31_t  normalize 
)

+

+

+
+
Initialization function for the Q31 DCT4/IDCT4. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of Q31 DCT4/IDCT4 structure. 
[in]*S_RFFTpoints to an instance of Q31 RFFT/RIFFT structure 
[in]*S_CFFTpoints to an instance of Q31 CFFT/CIFFT structure 
[in]Nlength of the DCT4. 
[in]Nby2half of the length of the DCT4. 
[in]normalizenormalizing factor. 

+  

+

+
Returns:
arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. 

+
Normalizing factor: 
The normalizing factor is sqrt(2/N), which depends on the size of transform N. Normalizing factors in 1.31 format are mentioned in the table below for different DCT sizes: 

+dct4NormalizingQ31Table.gif
+

+ 

+
+
Definition at line 2133 of file arm_dct4_init_q31.c.

+
+

+

+
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+      
void arm_dct4_q31 (const arm_dct4_instance_q31 *  S, 
q31_t *  pState, 
q31_t *  pInlineBuffer 
)

+

+

+
+
Processing function for the Q31 DCT4/IDCT4. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 DCT4 structure. 
[in]*pStatepoints to state buffer. 
[in,out]*pInlineBufferpoints to the in-place input and output buffer. 

+  

+

+
Returns:
none. 

+
Input an output formats: 
Input samples need to be downscaled by 1 bit to avoid saturations in the Q31 DCT process, as the conversion from DCT2 to DCT4 involves one subtraction. Internally inputs are downscaled in the RFFT process function to avoid overflows. Number of bits downscaled, depends on the size of the transform. The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:

+

+dct4FormatsQ31Table.gif
+

+ 
+
Definition at line 53 of file arm_dct4_q31.c.

+
+

+

+
+

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+      
arm_status arm_dct4_init_q15 (arm_dct4_instance_q15 *  S, 
arm_rfft_instance_q15 *  S_RFFT, 
arm_cfft_radix4_instance_q15 *  S_CFFT, 
uint16_t  N, 
uint16_t  Nby2, 
q15_t  normalize 
)

+

+

+
+
Initialization function for the Q15 DCT4/IDCT4. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of Q15 DCT4/IDCT4 structure. 
[in]*S_RFFTpoints to an instance of Q15 RFFT/RIFFT structure. 
[in]*S_CFFTpoints to an instance of Q15 CFFT/CIFFT structure. 
[in]Nlength of the DCT4. 
[in]Nby2half of the length of the DCT4. 
[in]normalizenormalizing factor. 

+  

+

+
Returns:
arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. 

+
Normalizing factor: 
The normalizing factor is sqrt(2/N), which depends on the size of transform N. Normalizing factors in 1.15 format are mentioned in the table below for different DCT sizes: 

+dct4NormalizingQ15Table.gif
+

+ 

+
+
Definition at line 1125 of file arm_dct4_init_q15.c.

+
+

+

+
+

+

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void arm_dct4_q15 (const arm_dct4_instance_q15 *  S, 
q15_t *  pState, 
q15_t *  pInlineBuffer 
)

+

+

+
+
Processing function for the Q15 DCT4/IDCT4. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 DCT4 structure. 
[in]*pStatepoints to state buffer. 
[in,out]*pInlineBufferpoints to the in-place input and output buffer. 

+  

+

+
Returns:
none.

+
Input an output formats: 
Internally inputs are downscaled in the RFFT process function to avoid overflows. Number of bits downscaled, depends on the size of the transform. The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:

+

+dct4FormatsQ15Table.gif
+

+ 
+
Definition at line 52 of file arm_dct4_q15.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float32_t Weights_128[256] [static]

+

+

+
Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
 

+
C command to generate the table 
   
+ for(i = 0; i< N; i++)   
+ {   
+    weights[2*i]= cos(i*c);   
+    weights[(2*i)+1]= -sin(i * c);   
+ } 
 

+
Where N is the Number of weights to be calculated and c is pi/(2*N) 

+
In the tables below the real and imaginary values are placed alternatively, hence the array length is 2*N. 

+
+
Definition at line 64 of file arm_dct4_init_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t Weights_512[1024] [static]

+

+

+
+
Definition at line 195 of file arm_dct4_init_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t Weights_2048[4096] [static]

+

+

+
+
Definition at line 710 of file arm_dct4_init_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t cos_factors_128[128] [static]

+

+

+
cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
 

+
C command to generate the table 

+
 for(i = 0; i< N; i++)   
+ {   
+    cos_factors[i]= 2 * cos((2*i+1)*c/2);   
+ } 
 

+
where N is the number of factors to generate and c is pi/(2*N) 

+
+
Definition at line 2774 of file arm_dct4_init_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t cos_factors_512[512] [static]

+

+

+
+
Definition at line 2841 of file arm_dct4_init_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t cos_factors_2048[2048] [static]

+

+

+
+
Definition at line 3100 of file arm_dct4_init_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t WeightsQ31_128[256] [static]

+

+

+
Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
 

+
C command to generate the table 
   
+ for(i = 0; i< N; i++)   
+ {   
+   weights[2*i]= cos(i*c);   
+   weights[(2*i)+1]= -sin(i * c);   
+ } 
 

+
where N is the Number of weights to be calculated and c is pi/(2*N) 

+
Convert the output to q31 format by multiplying with 2^31 and saturated if required. 

+
In the tables below the real and imaginary values are placed alternatively, hence the array length is 2*N. 

+
+
Definition at line 66 of file arm_dct4_init_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t WeightsQ31_512[1024] [static]

+

+

+
+
Definition at line 133 of file arm_dct4_init_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t WeightsQ31_2048[4096] [static]

+

+

+
+
Definition at line 392 of file arm_dct4_init_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t cos_factorsQ31_128[128] [static]

+

+

+
cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
 

+
C command to generate the table 
   
+ for(i = 0; i< N; i++)   
+ {   
+   cos_factors[i]= 2 * cos((2*i+1)*c/2);   
+ } 
 

+
where N is the number of factors to generate and c is pi/(2*N) 

+
Then converted to q31 format by multiplying with 2^31 and saturated if required. 

+
+
Definition at line 1436 of file arm_dct4_init_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t cos_factorsQ31_512[512] [static]

+

+

+
+
Definition at line 1471 of file arm_dct4_init_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t cos_factorsQ31_2048[2048] [static]

+

+

+
+
Definition at line 1602 of file arm_dct4_init_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t WeightsQ15_128[256] [static]

+

+

+
Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
 

+
C command to generate the table 
   
+ for(i = 0; i< N; i++)   
+ {   
+   weights[2*i]= cos(i*c);   
+   weights[(2*i)+1]= -sin(i * c);   
+ } 
 

+
where N is the Number of weights to be calculated and c is pi/(2*N) 

+
Converted the output to q15 format by multiplying with 2^31 and saturated if required. 

+
In the tables below the real and imaginary values are placed alternatively, hence the array length is 2*N. 

+
+
Definition at line 66 of file arm_dct4_init_q15.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t WeightsQ15_512[1024] [static]

+

+

+
+
Definition at line 101 of file arm_dct4_init_q15.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t WeightsQ15_2048[4096] [static]

+

+

+
+
Definition at line 232 of file arm_dct4_init_q15.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t cos_factorsQ15_128[128] [static]

+

+

+Initial value:
 {
+  0x7fff, 0x7ffa, 0x7ff0, 0x7fe1, 0x7fce, 0x7fb5, 0x7f97, 0x7f75,
+  0x7f4d, 0x7f21, 0x7ef0, 0x7eba, 0x7e7f, 0x7e3f, 0x7dfa, 0x7db0,
+  0x7d62, 0x7d0f, 0x7cb7, 0x7c5a, 0x7bf8, 0x7b92, 0x7b26, 0x7ab6,
+  0x7a42, 0x79c8, 0x794a, 0x78c7, 0x7840, 0x77b4, 0x7723, 0x768e,
+  0x75f4, 0x7555, 0x74b2, 0x740b, 0x735f, 0x72af, 0x71fa, 0x7141,
+  0x7083, 0x6fc1, 0x6efb, 0x6e30, 0x6d62, 0x6c8f, 0x6bb8, 0x6adc,
+  0x69fd, 0x6919, 0x6832, 0x6746, 0x6657, 0x6563, 0x646c, 0x6371,
+  0x6271, 0x616f, 0x6068, 0x5f5e, 0x5e50, 0x5d3e, 0x5c29, 0x5b10,
+  0x59f3, 0x58d4, 0x57b0, 0x568a, 0x5560, 0x5433, 0x5302, 0x51ce,
+  0x5097, 0x4f5e, 0x4e21, 0x4ce1, 0x4b9e, 0x4a58, 0x490f, 0x47c3,
+  0x4675, 0x4524, 0x43d0, 0x427a, 0x4121, 0x3fc5, 0x3e68, 0x3d07,
+  0x3ba5, 0x3a40, 0x38d8, 0x376f, 0x3604, 0x3496, 0x3326, 0x31b5,
+  0x3041, 0x2ecc, 0x2d55, 0x2bdc, 0x2a61, 0x28e5, 0x2767, 0x25e8,
+  0x2467, 0x22e5, 0x2161, 0x1fdc, 0x1e56, 0x1ccf, 0x1b47, 0x19bd,
+  0x1833, 0x16a8, 0x151b, 0x138e, 0x1201, 0x1072, 0xee3, 0xd53,
+  0xbc3, 0xa33, 0x8a2, 0x710, 0x57f, 0x3ed, 0x25b, 0xc9
+}
+
cosFactor tables are generated using the formula : 
 cos_factors[n] = 2 * cos((2n+1)*pi/(4*N)) 
 

+
C command to generate the table 
   
+ for(i = 0; i< N; i++)   
+ {   
+   cos_factors[i]= 2 * cos((2*i+1)*c/2);   
+ } 
 

+
where N is the number of factors to generate and c is pi/(2*N) 

+
Then converted to q15 format by multiplying with 2^31 and saturated if required. 

+
+
Definition at line 764 of file arm_dct4_init_q15.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t cos_factorsQ15_512[512] [static]

+

+

+
+
Definition at line 783 of file arm_dct4_init_q15.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t cos_factorsQ15_2048[2048] [static]

+

+

+
+
Definition at line 850 of file arm_dct4_init_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___dotproduct_example.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___dotproduct_example.html
new file mode 100644
index 000000000..3c4a96a63
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___dotproduct_example.html
@@ -0,0 +1,96 @@
+
+
+
+
+CMSIS DSP Software Library: Dot Product Example
+
+
+
+
+
+
+
+
+
+

+  

+
Dot Product Example

+
+[Examples]
+
  

+

+

+
+

+
Description: 

+
Demonstrates the use of the Multiply and Add functions to perform the dot product. The dot product of two vectors is obtained by multiplying corresponding elements and summing the products.

+
Algorithm:

+
The two input vectors A and B with length n, are multiplied element-by-element and then added to obtain dot product. 

+
This is denoted by the following equation: 
  dotProduct = A[0] * B[0] + A[1] * B[1] + ... + A[n-1] * B[n-1]

+
Block Diagram:

+

+dotProduct.gif
+

+

+
Variables Description:

+
    
+
  • srcA_buf_f32 points to first input vector 
    • 
+
  • srcB_buf_f32 points to second input vector 
    • 
+
  • testOutput stores dot product of the two input vectors.
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_dotproduct_example_f32.c 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___f_i_r.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___f_i_r.html
new file mode 100644
index 000000000..72c41d658
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___f_i_r.html
@@ -0,0 +1,721 @@
+
+
+
+
+CMSIS DSP Software Library: Finite Impulse Response (FIR) Filters
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Finite Impulse Response (FIR) Filters

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_fir_init_f32 (arm_fir_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
void arm_fir_f32 (const arm_fir_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_fir_init_q31 (arm_fir_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
void arm_fir_q31 (const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_fir_fast_q31 (const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
arm_status arm_fir_init_q15 (arm_fir_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
void arm_fir_q15 (const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_fir_fast_q15 (const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_fir_init_q7 (arm_fir_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, uint32_t blockSize)
void arm_fir_q7 (const arm_fir_instance_q7 *S, q7_t *pSrc, q7_t *pDst, uint32_t blockSize)

+
Detailed Description

+
This set of functions implements Finite Impulse Response (FIR) filters for Q7, Q15, Q31, and floating-point data types. Fast versions of Q15 and Q31 are also provided on Cortex-M4 and Cortex-M3. The functions operate on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc and pDst points to input and output arrays containing blockSize values.

+
Algorithm: 
The FIR filter algorithm is based upon a sequence of multiply-accumulate (MAC) operations. Each filter coefficient b[n] is multiplied by a state variable which equals a previous input sample x[n]. 
   
+    y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]   
+ 
 

+

+FIR.gif
+
Finite Impulse Response filter

+ 

+
pCoeffs points to a coefficient array of size numTaps. Coefficients are stored in time reversed order. 

+
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 

+
pState points to a state array of size numTaps + blockSize - 1. Samples in the state buffer are stored in the following order. 

+
   
+    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}   
+ 
 

+
Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1. The increased state buffer length allows circular addressing, which is traditionally used in the FIR filters, to be avoided and yields a significant speed improvement. The state variables are updated after each block of data is processed; the coefficients are untouched. 

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. There are separate instance structure declarations for each of the 4 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros before static initialization. The code below statically initializes each of the 4 different data type filter instance structures 
   
+arm_fir_instance_f32 S = {numTaps, pState, pCoeffs};   
+arm_fir_instance_q31 S = {numTaps, pState, pCoeffs};   
+arm_fir_instance_q15 S = {numTaps, pState, pCoeffs};   
+arm_fir_instance_q7 S =  {numTaps, pState, pCoeffs};   
+ 

+
where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer; pCoeffs is the address of the coefficient buffer.

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the FIR filter functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
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+          
+        
+        
+          
+          
+          
+        
+      
void arm_fir_init_f32 (arm_fir_instance_f32 *  S, 
uint16_t  numTaps, 
float32_t *  pCoeffs, 
float32_t *  pState, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the floating-point FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point FIR filter structure. 
[in]numTapsNumber of filter coefficients in the filter. 
[in]*pCoeffspoints to the filter coefficients buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of samples that are processed per call. 

+  

+

+
Returns:
none.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 

+
pState points to the array of state variables. pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_f32(). 

+
Examples: 
arm_fir_example_f32.c, and arm_signal_converge_example_f32.c.

+

+
Definition at line 68 of file arm_fir_init_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_fir_f32 (const arm_fir_instance_f32 *  S, 
float32_t *  pSrc, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the floating-point FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point FIR filter structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none. 

+
Examples: 
arm_fir_example_f32.c, and arm_signal_converge_example_f32.c.

+

+
Definition at line 128 of file arm_fir_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
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+          
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+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_fir_init_q31 (arm_fir_instance_q31 *  S, 
uint16_t  numTaps, 
q31_t *  pCoeffs, 
q31_t *  pState, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the Q31 FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 FIR filter structure. 
[in]numTapsNumber of filter coefficients in the filter. 
[in]*pCoeffspoints to the filter coefficients buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of samples that are processed per call. 

+  

+

+
Returns:
none.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 

+
pState points to the array of state variables. pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q31(). 

+
+
Definition at line 68 of file arm_fir_init_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_fir_q31 (const arm_fir_instance_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q31 FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 FIR filter structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. After all multiply-accumulates are performed, the 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.

+
Refer to the function arm_fir_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4. 

+
+
Definition at line 67 of file arm_fir_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
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+          
+          
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+          
+        
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+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_fir_fast_q31 (const arm_fir_instance_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
This function is optimized for speed at the expense of fixed-point precision and overflow protection. The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. These intermediate results are added to a 2.30 accumulator. Finally, the accumulator is saturated and converted to a 1.31 result. The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.

+
Refer to the function arm_fir_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. Both the slow and the fast versions use the same instance structure. Use the function arm_fir_init_q31() to initialize the filter structure. 

+
+
Definition at line 66 of file arm_fir_fast_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
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+          
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+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_fir_init_q15 (arm_fir_instance_q15 *  S, 
uint16_t  numTaps, 
q15_t *  pCoeffs, 
q15_t *  pState, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the Q15 FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 FIR filter structure. 
[in]numTapsNumber of filter coefficients in the filter. Must be even and greater than or equal to 4. 
[in]*pCoeffspoints to the filter coefficients buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizeis number of samples processed per call. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if numTaps is not greater than or equal to 4 and even.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 Note that numTaps must be even and greater than or equal to 4. To implement an odd length filter simply increase numTaps by 1 and set the last coefficient to zero. For example, to implement a filter with numTaps=3 and coefficients 
   
+     {0.3, -0.8, 0.3}   
+ 
 set numTaps=4 and use the coefficients: 
   
+     {0.3, -0.8, 0.3, 0}.   
+ 
 Similarly, to implement a two point filter 
   
+     {0.3, -0.3}   
+ 
 set numTaps=4 and use the coefficients: 
   
+     {0.3, -0.3, 0, 0}.   
+ 
 

+
pState points to the array of state variables. pState is of length numTaps+blockSize-1, where blockSize is the number of input samples processed by each call to arm_fir_q15(). 

+
+
Definition at line 85 of file arm_fir_init_q15.c.

+
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void arm_fir_q15 (const arm_fir_instance_q15 *  S, 
q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q15 FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 FIR structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format.

+
Refer to the function arm_fir_fast_q15() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4. 

+
+
Definition at line 68 of file arm_fir_q15.c.

+
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void arm_fir_fast_q15 (const arm_fir_instance_q15 *  S, 
q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 FIR filter structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
This fast version uses a 32-bit accumulator with 2.30 format. The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around and distorts the result. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.

+
Refer to the function arm_fir_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure. Use the function arm_fir_init_q15() to initialize the filter structure. 

+
+
Definition at line 65 of file arm_fir_fast_q15.c.

+
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void arm_fir_init_q7 (arm_fir_instance_q7 *  S, 
uint16_t  numTaps, 
q7_t *  pCoeffs, 
q7_t *  pState, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the Q7 FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q7 FIR filter structure. 
[in]numTapsNumber of filter coefficients in the filter. 
[in]*pCoeffspoints to the filter coefficients buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of samples that are processed per call. 

+  

+

+
Returns:
none

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 

+
pState points to the array of state variables. pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q7(). 

+
+
Definition at line 65 of file arm_fir_init_q7.c.

+
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void arm_fir_q7 (const arm_fir_instance_q7 *  S, 
q7_t *  pSrc, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q7 FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q7 FIR filter structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 32-bit internal accumulator. Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result. The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. The accumulator is converted to 18.7 format by discarding the low 7 bits. Finally, the result is truncated to 1.7 format. 

+
+
Definition at line 64 of file arm_fir_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
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+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___f_i_r___interpolate.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___f_i_r___interpolate.html
new file mode 100644
index 000000000..cb4ae7802
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___f_i_r___interpolate.html
@@ -0,0 +1,497 @@
+
+
+
+
+CMSIS DSP Software Library: Finite Impulse Response (FIR) Interpolator
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Finite Impulse Response (FIR) Interpolator

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+

+Functions
arm_status arm_fir_interpolate_init_f32 (arm_fir_interpolate_instance_f32 *S, uint8_t L, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
void arm_fir_interpolate_f32 (const arm_fir_interpolate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
arm_status arm_fir_interpolate_init_q31 (arm_fir_interpolate_instance_q31 *S, uint8_t L, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
void arm_fir_interpolate_q31 (const arm_fir_interpolate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
arm_status arm_fir_interpolate_init_q15 (arm_fir_interpolate_instance_q15 *S, uint8_t L, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
void arm_fir_interpolate_q15 (const arm_fir_interpolate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+
Detailed Description

+
These functions combine an upsampler (zero stuffer) and an FIR filter. They are used in multirate systems for increasing the sample rate of a signal without introducing high frequency images. Conceptually, the functions are equivalent to the block diagram below: 

+

+FIRInterpolator.gif
+
Components included in the FIR Interpolator functions

+
 After upsampling by a factor of L, the signal should be filtered by a lowpass filter with a normalized cutoff frequency of 1/L in order to eliminate high frequency copies of the spectrum. The user of the function is responsible for providing the filter coefficients.

+
The FIR interpolator functions provided in the CMSIS DSP Library combine the upsampler and FIR filter in an efficient manner. The upsampler inserts L-1 zeros between each sample. Instead of multiplying by these zero values, the FIR filter is designed to skip them. This leads to an efficient implementation without any wasted effort. The functions operate on blocks of input and output data. pSrc points to an array of blockSize input values and pDst points to an array of blockSize*L output values.

+
The library provides separate functions for Q15, Q31, and floating-point data types.

+
Algorithm: 
The functions use a polyphase filter structure: 
   
+    y[n] = b[0] * x[n] + b[L]   * x[n-1] + ... + b[L*(phaseLength-1)] * x[n-phaseLength+1]   
+    y[n+1] = b[1] * x[n] + b[L+1] * x[n-1] + ... + b[L*(phaseLength-1)+1] * x[n-phaseLength+1]   
+    ...   
+    y[n+(L-1)] = b[L-1] * x[n] + b[2*L-1] * x[n-1] + ....+ b[L*(phaseLength-1)+(L-1)] * x[n-phaseLength+1]   
+ 
 This approach is more efficient than straightforward upsample-then-filter algorithms. With this method the computation is reduced by a factor of 1/L when compared to using a standard FIR filter. 

+
pCoeffs points to a coefficient array of size numTaps. numTaps must be a multiple of the interpolation factor L and this is checked by the initialization functions. Internally, the function divides the FIR filter's impulse response into shorter filters of length phaseLength=numTaps/L. Coefficients are stored in time reversed order. 

+
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 

+
pState points to a state array of size blockSize + phaseLength - 1. Samples in the state buffer are stored in the order: 

+
   
+    {x[n-phaseLength+1], x[n-phaseLength], x[n-phaseLength-1], x[n-phaseLength-2]....x[0], x[1], ..., x[blockSize-1]}   
+ 
 The state variables are updated after each block of data is processed, the coefficients are untouched.

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable array should be allocated separately. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+
  • Checks to make sure that the length of the filter is a multiple of the interpolation factor.
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. The code below statically initializes each of the 3 different data type filter instance structures 
   
+ arm_fir_interpolate_instance_f32 S = {L, phaseLength, pCoeffs, pState};   
+ arm_fir_interpolate_instance_q31 S = {L, phaseLength, pCoeffs, pState};   
+ arm_fir_interpolate_instance_q15 S = {L, phaseLength, pCoeffs, pState};   
+ 
 where L is the interpolation factor; phaseLength=numTaps/L is the length of each of the shorter FIR filters used internally, pCoeffs is the address of the coefficient buffer; pState is the address of the state buffer. Be sure to set the values in the state buffer to zeros when doing static initialization.

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the FIR interpolate filter functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
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arm_status arm_fir_interpolate_init_f32 (arm_fir_interpolate_instance_f32 *  S, 
uint8_t  L, 
uint16_t  numTaps, 
float32_t *  pCoeffs, 
float32_t *  pState, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the floating-point FIR interpolator. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point FIR interpolator structure. 
[in]Lupsample factor. 
[in]numTapsnumber of filter coefficients in the filter. 
[in]*pCoeffspoints to the filter coefficient buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if the filter length numTaps is not a multiple of the interpolation factor L.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}   
+ 
 The length of the filter numTaps must be a multiple of the interpolation factor L. 

+
pState points to the array of state variables. pState is of length (numTaps/L)+blockSize-1 words where blockSize is the number of input samples processed by each call to arm_fir_interpolate_f32(). 

+
+
Definition at line 68 of file arm_fir_interpolate_init_f32.c.

+
+

+

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void arm_fir_interpolate_f32 (const arm_fir_interpolate_instance_f32 *  S, 
float32_t *  pSrc, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the floating-point FIR interpolator. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point FIR interpolator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none. 

+
+
Definition at line 135 of file arm_fir_interpolate_f32.c.

+
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arm_status arm_fir_interpolate_init_q31 (arm_fir_interpolate_instance_q31 *  S, 
uint8_t  L, 
uint16_t  numTaps, 
q31_t *  pCoeffs, 
q31_t *  pState, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the Q31 FIR interpolator. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 FIR interpolator structure. 
[in]Lupsample factor. 
[in]numTapsnumber of filter coefficients in the filter. 
[in]*pCoeffspoints to the filter coefficient buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if the filter length numTaps is not a multiple of the interpolation factor L.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}   
+ 
 The length of the filter numTaps must be a multiple of the interpolation factor L. 

+
pState points to the array of state variables. pState is of length (numTaps/L)+blockSize-1 words where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q31(). 

+
+
Definition at line 69 of file arm_fir_interpolate_init_q31.c.

+
+

+

+
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void arm_fir_interpolate_q31 (const arm_fir_interpolate_instance_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q31 FIR interpolator. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 FIR interpolator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by 1/(numTaps/L). since numTaps/L additions occur per output sample. After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. 

+
+
Definition at line 63 of file arm_fir_interpolate_q31.c.

+
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arm_status arm_fir_interpolate_init_q15 (arm_fir_interpolate_instance_q15 *  S, 
uint8_t  L, 
uint16_t  numTaps, 
q15_t *  pCoeffs, 
q15_t *  pState, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the Q15 FIR interpolator. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 FIR interpolator structure. 
[in]Lupsample factor. 
[in]numTapsnumber of filter coefficients in the filter. 
[in]*pCoeffspoints to the filter coefficient buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if the filter length numTaps is not a multiple of the interpolation factor L.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}   
+ 
 The length of the filter numTaps must be a multiple of the interpolation factor L. 

+
pState points to the array of state variables. pState is of length (numTaps/L)+blockSize-1 words where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q15(). 

+
+
Definition at line 68 of file arm_fir_interpolate_init_q15.c.

+
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void arm_fir_interpolate_q15 (const arm_fir_interpolate_instance_q15 *  S, 
q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q15 FIR interpolator. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 FIR interpolator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format. 

+
+
Definition at line 62 of file arm_fir_interpolate_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___f_i_r___lattice.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___f_i_r___lattice.html
new file mode 100644
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+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___f_i_r___lattice.html
@@ -0,0 +1,433 @@
+
+
+
+
+CMSIS DSP Software Library: Finite Impulse Response (FIR) Lattice Filters
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Finite Impulse Response (FIR) Lattice Filters

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_fir_lattice_init_f32 (arm_fir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pCoeffs, float32_t *pState)
void arm_fir_lattice_f32 (const arm_fir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_fir_lattice_init_q31 (arm_fir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pCoeffs, q31_t *pState)
void arm_fir_lattice_q31 (const arm_fir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_fir_lattice_init_q15 (arm_fir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pCoeffs, q15_t *pState)
void arm_fir_lattice_q15 (const arm_fir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+
Detailed Description

+
This set of functions implements Finite Impulse Response (FIR) lattice filters for Q15, Q31 and floating-point data types. Lattice filters are used in a variety of adaptive filter applications. The filter structure is feedforward and the net impulse response is finite length. The functions operate on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc and pDst point to input and output arrays containing blockSize values.

+
Algorithm: 

+FIRLattice.gif
+
Finite Impulse Response Lattice filter

+ The following difference equation is implemented: 
   
+    f0[n] = g0[n] = x[n]   
+    fm[n] = fm-1[n] + km * gm-1[n-1] for m = 1, 2, ...M   
+    gm[n] = km * fm-1[n] + gm-1[n-1] for m = 1, 2, ...M   
+    y[n] = fM[n]   
+ 
 

+
pCoeffs points to tha array of reflection coefficients of size numStages. Reflection Coefficients are stored in the following order. 

+
   
+    {k1, k2, ..., kM}   
+ 
 where M is number of stages 

+
pState points to a state array of size numStages. The state variables (g values) hold previous inputs and are stored in the following order. 
   
+    {g0[n], g1[n], g2[n] ...gM-1[n]}   
+ 
 The state variables are updated after each block of data is processed; the coefficients are untouched. 

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros and then manually initialize the instance structure as follows: 
   
+arm_fir_lattice_instance_f32 S = {numStages, pState, pCoeffs};   
+arm_fir_lattice_instance_q31 S = {numStages, pState, pCoeffs};   
+arm_fir_lattice_instance_q15 S = {numStages, pState, pCoeffs};   
+ 
 

+
where numStages is the number of stages in the filter; pState is the address of the state buffer; pCoeffs is the address of the coefficient buffer. 

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the FIR Lattice filter functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

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void arm_fir_lattice_init_f32 (arm_fir_lattice_instance_f32 *  S, 
uint16_t  numStages, 
float32_t *  pCoeffs, 
float32_t *  pState 
)

+

+

+
+
Initialization function for the floating-point FIR lattice filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point FIR lattice structure. 
[in]numStagesnumber of filter stages. 
[in]*pCoeffspoints to the coefficient buffer. The array is of length numStages. 
[in]*pStatepoints to the state buffer. The array is of length numStages. 

+  

+

+
Returns:
none. 

+
+
Definition at line 53 of file arm_fir_lattice_init_f32.c.

+
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void arm_fir_lattice_f32 (const arm_fir_lattice_instance_f32 *  S, 
float32_t *  pSrc, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the floating-point FIR lattice filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point FIR lattice structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
+
Definition at line 121 of file arm_fir_lattice_f32.c.

+
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void arm_fir_lattice_init_q31 (arm_fir_lattice_instance_q31 *  S, 
uint16_t  numStages, 
q31_t *  pCoeffs, 
q31_t *  pState 
)

+

+

+
+
Initialization function for the Q31 FIR lattice filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 FIR lattice structure. 
[in]numStagesnumber of filter stages. 
[in]*pCoeffspoints to the coefficient buffer. The array is of length numStages. 
[in]*pStatepoints to the state buffer. The array is of length numStages. 

+  

+

+
Returns:
none. 

+
+
Definition at line 53 of file arm_fir_lattice_init_q31.c.

+
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+

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void arm_fir_lattice_q31 (const arm_fir_lattice_instance_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q31 FIR lattice filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 FIR lattice structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: In order to avoid overflows the input signal must be scaled down by 2*log2(numStages) bits. 

+
+
Definition at line 58 of file arm_fir_lattice_q31.c.

+
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void arm_fir_lattice_init_q15 (arm_fir_lattice_instance_q15 *  S, 
uint16_t  numStages, 
q15_t *  pCoeffs, 
q15_t *  pState 
)

+

+

+
+
Initialization function for the Q15 FIR lattice filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 FIR lattice structure. 
[in]numStagesnumber of filter stages. 
[in]*pCoeffspoints to the coefficient buffer. The array is of length numStages. 
[in]*pStatepoints to the state buffer. The array is of length numStages. 

+  

+

+
Returns:
none. 

+
+
Definition at line 53 of file arm_fir_lattice_init_q15.c.

+
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void arm_fir_lattice_q15 (const arm_fir_lattice_instance_q15 *  S, 
q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q15 FIR lattice filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 FIR lattice structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
+
Definition at line 54 of file arm_fir_lattice_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___f_i_r___sparse.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___f_i_r___sparse.html
new file mode 100644
index 000000000..ec3ef549f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___f_i_r___sparse.html
@@ -0,0 +1,674 @@
+
+
+
+
+CMSIS DSP Software Library: Finite Impulse Response (FIR) Sparse Filters
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Finite Impulse Response (FIR) Sparse Filters

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_fir_sparse_init_f32 (arm_fir_sparse_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
void arm_fir_sparse_f32 (arm_fir_sparse_instance_f32 *S, float32_t *pSrc, float32_t *pDst, float32_t *pScratchIn, uint32_t blockSize)
void arm_fir_sparse_init_q31 (arm_fir_sparse_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
void arm_fir_sparse_q31 (arm_fir_sparse_instance_q31 *S, q31_t *pSrc, q31_t *pDst, q31_t *pScratchIn, uint32_t blockSize)
void arm_fir_sparse_init_q15 (arm_fir_sparse_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
void arm_fir_sparse_q15 (arm_fir_sparse_instance_q15 *S, q15_t *pSrc, q15_t *pDst, q15_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize)
void arm_fir_sparse_init_q7 (arm_fir_sparse_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
void arm_fir_sparse_q7 (arm_fir_sparse_instance_q7 *S, q7_t *pSrc, q7_t *pDst, q7_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize)

+
Detailed Description

+
This group of functions implements sparse FIR filters. Sparse FIR filters are equivalent to standard FIR filters except that most of the coefficients are equal to zero. Sparse filters are used for simulating reflections in communications and audio applications.

+
There are separate functions for Q7, Q15, Q31, and floating-point data types. The functions operate on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc and pDst points to input and output arrays respectively containing blockSize values.

+
Algorithm: 
The sparse filter instant structure contains an array of tap indices pTapDelay which specifies the locations of the non-zero coefficients. This is in addition to the coefficient array b. The implementation essentially skips the multiplications by zero and leads to an efficient realization. 
  
+     y[n] = b[0] * x[n-pTapDelay[0]] + b[1] * x[n-pTapDelay[1]] + b[2] * x[n-pTapDelay[2]] + ...+ b[numTaps-1] * x[n-pTapDelay[numTaps-1]]   
+ 
 

+

+FIRSparse.gif
+
Sparse FIR filter. b[n] represents the filter coefficients

+ 

+
pCoeffs points to a coefficient array of size numTaps; pTapDelay points to an array of nonzero indices and is also of size numTaps; pState points to a state array of size maxDelay + blockSize, where maxDelay is the largest offset value that is ever used in the pTapDelay array. Some of the processing functions also require temporary working buffers.

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient and offset arrays may be shared among several instances while state variable arrays cannot be shared. There are separate instance structure declarations for each of the 4 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros before static initialization. The code below statically initializes each of the 4 different data type filter instance structures 
   
+arm_fir_sparse_instance_f32 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};   
+arm_fir_sparse_instance_q31 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};   
+arm_fir_sparse_instance_q15 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};   
+arm_fir_sparse_instance_q7 S =  {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};   
+ 
 

+

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the sparse FIR filter functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

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void arm_fir_sparse_init_f32 (arm_fir_sparse_instance_f32 *  S, 
uint16_t  numTaps, 
float32_t *  pCoeffs, 
float32_t *  pState, 
int32_t *  pTapDelay, 
uint16_t  maxDelay, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the floating-point sparse FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point sparse FIR structure. 
[in]numTapsnumber of nonzero coefficients in the filter. 
[in]*pCoeffspoints to the array of filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]*pTapDelaypoints to the array of offset times. 
[in]maxDelaymaximum offset time supported. 
[in]blockSizenumber of samples that will be processed per block. 

+  

+

+
Returns:
none

+
Description: 

+
pCoeffs holds the filter coefficients and has length numTaps. pState holds the filter's state variables and must be of length maxDelay + blockSize, where maxDelay is the maximum number of delay line values. blockSize is the number of samples processed by the arm_fir_sparse_f32() function. 

+
+
Definition at line 65 of file arm_fir_sparse_init_f32.c.

+
+

+

+
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void arm_fir_sparse_f32 (arm_fir_sparse_instance_f32 *  S, 
float32_t *  pSrc, 
float32_t *  pDst, 
float32_t *  pScratchIn, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the floating-point sparse FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point sparse FIR structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]*pScratchInpoints to a temporary buffer of size blockSize. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none. 

+
+
Definition at line 113 of file arm_fir_sparse_f32.c.

+
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void arm_fir_sparse_init_q31 (arm_fir_sparse_instance_q31 *  S, 
uint16_t  numTaps, 
q31_t *  pCoeffs, 
q31_t *  pState, 
int32_t *  pTapDelay, 
uint16_t  maxDelay, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the Q31 sparse FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 sparse FIR structure. 
[in]numTapsnumber of nonzero coefficients in the filter. 
[in]*pCoeffspoints to the array of filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]*pTapDelaypoints to the array of offset times. 
[in]maxDelaymaximum offset time supported. 
[in]blockSizenumber of samples that will be processed per block. 

+  

+

+
Returns:
none

+
Description: 

+
pCoeffs holds the filter coefficients and has length numTaps. pState holds the filter's state variables and must be of length maxDelay + blockSize, where maxDelay is the maximum number of delay line values. blockSize is the number of words processed by arm_fir_sparse_q31() function. 

+
+
Definition at line 64 of file arm_fir_sparse_init_q31.c.

+
+

+

+
+

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void arm_fir_sparse_q31 (arm_fir_sparse_instance_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pDst, 
q31_t *  pScratchIn, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q31 sparse FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 sparse FIR structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]*pScratchInpoints to a temporary buffer of size blockSize. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 32-bit accumulator. The 1.31 x 1.31 multiplications are truncated to 2.30 format. This leads to loss of precision on the intermediate multiplications and provides only a single guard bit. If the accumulator result overflows, it wraps around rather than saturate. In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits. 

+
+
Definition at line 58 of file arm_fir_sparse_q31.c.

+
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+        
+      
void arm_fir_sparse_init_q15 (arm_fir_sparse_instance_q15 *  S, 
uint16_t  numTaps, 
q15_t *  pCoeffs, 
q15_t *  pState, 
int32_t *  pTapDelay, 
uint16_t  maxDelay, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the Q15 sparse FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 sparse FIR structure. 
[in]numTapsnumber of nonzero coefficients in the filter. 
[in]*pCoeffspoints to the array of filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]*pTapDelaypoints to the array of offset times. 
[in]maxDelaymaximum offset time supported. 
[in]blockSizenumber of samples that will be processed per block. 

+  

+

+
Returns:
none

+
Description: 

+
pCoeffs holds the filter coefficients and has length numTaps. pState holds the filter's state variables and must be of length maxDelay + blockSize, where maxDelay is the maximum number of delay line values. blockSize is the number of words processed by arm_fir_sparse_q15() function. 

+
+
Definition at line 65 of file arm_fir_sparse_init_q15.c.

+
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+

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void arm_fir_sparse_q15 (arm_fir_sparse_instance_q15 *  S, 
q15_t *  pSrc, 
q15_t *  pDst, 
q15_t *  pScratchIn, 
q31_t *  pScratchOut, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q15 sparse FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 sparse FIR structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]*pScratchInpoints to a temporary buffer of size blockSize. 
[in]*pScratchOutpoints to a temporary buffer of size blockSize. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 32-bit accumulator. The 1.15 x 1.15 multiplications yield a 2.30 result and these are added to a 2.30 accumulator. Thus the full precision of the multiplications is maintained but there is only a single guard bit in the accumulator. If the accumulator result overflows it will wrap around rather than saturate. After all multiply-accumulates are performed, the 2.30 accumulator is truncated to 2.15 format and then saturated to 1.15 format. In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits. 

+
+
Definition at line 60 of file arm_fir_sparse_q15.c.

+
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void arm_fir_sparse_init_q7 (arm_fir_sparse_instance_q7 *  S, 
uint16_t  numTaps, 
q7_t *  pCoeffs, 
q7_t *  pState, 
int32_t *  pTapDelay, 
uint16_t  maxDelay, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the Q7 sparse FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q7 sparse FIR structure. 
[in]numTapsnumber of nonzero coefficients in the filter. 
[in]*pCoeffspoints to the array of filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]*pTapDelaypoints to the array of offset times. 
[in]maxDelaymaximum offset time supported. 
[in]blockSizenumber of samples that will be processed per block. 

+  

+

+
Returns:
none

+
Description: 

+
pCoeffs holds the filter coefficients and has length numTaps. pState holds the filter's state variables and must be of length maxDelay + blockSize, where maxDelay is the maximum number of delay line values. blockSize is the number of samples processed by the arm_fir_sparse_q7() function. 

+
+
Definition at line 65 of file arm_fir_sparse_init_q7.c.

+
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void arm_fir_sparse_q7 (arm_fir_sparse_instance_q7 *  S, 
q7_t *  pSrc, 
q7_t *  pDst, 
q7_t *  pScratchIn, 
q31_t *  pScratchOut, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q7 sparse FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q7 sparse FIR structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]*pScratchInpoints to a temporary buffer of size blockSize. 
[in]*pScratchOutpoints to a temporary buffer of size blockSize. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 32-bit internal accumulator. Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result. The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. The accumulator is then converted to 18.7 format by discarding the low 7 bits. Finally, the result is truncated to 1.7 format. 

+
+
Definition at line 65 of file arm_fir_sparse_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___f_i_r__decimate.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___f_i_r__decimate.html
new file mode 100644
index 000000000..99def24a0
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___f_i_r__decimate.html
@@ -0,0 +1,610 @@
+
+
+
+
+CMSIS DSP Software Library: Finite Impulse Response (FIR) Decimator
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Finite Impulse Response (FIR) Decimator

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+
+
+

+Functions
arm_status arm_fir_decimate_init_f32 (arm_fir_decimate_instance_f32 *S, uint16_t numTaps, uint8_t M, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
void arm_fir_decimate_f32 (const arm_fir_decimate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
arm_status arm_fir_decimate_init_q31 (arm_fir_decimate_instance_q31 *S, uint16_t numTaps, uint8_t M, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
void arm_fir_decimate_q31 (const arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_fir_decimate_fast_q31 (arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
arm_status arm_fir_decimate_init_q15 (arm_fir_decimate_instance_q15 *S, uint16_t numTaps, uint8_t M, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
void arm_fir_decimate_q15 (const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_fir_decimate_fast_q15 (const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+
Detailed Description

+
These functions combine an FIR filter together with a decimator. They are used in multirate systems for reducing the sample rate of a signal without introducing aliasing distortion. Conceptually, the functions are equivalent to the block diagram below: 

+

+FIRDecimator.gif
+
Components included in the FIR Decimator functions

+
 When decimating by a factor of M, the signal should be prefiltered by a lowpass filter with a normalized cutoff frequency of 1/M in order to prevent aliasing distortion. The user of the function is responsible for providing the filter coefficients.

+
The FIR decimator functions provided in the CMSIS DSP Library combine the FIR filter and the decimator in an efficient manner. Instead of calculating all of the FIR filter outputs and discarding M-1 out of every M, only the samples output by the decimator are computed. The functions operate on blocks of input and output data. pSrc points to an array of blockSize input values and pDst points to an array of blockSize/M output values. In order to have an integer number of output samples blockSize must always be a multiple of the decimation factor M.

+
The library provides separate functions for Q15, Q31 and floating-point data types.

+
Algorithm: 
The FIR portion of the algorithm uses the standard form filter: 
   
+    y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]   
+ 
 where, b[n] are the filter coefficients. 

+
The pCoeffs points to a coefficient array of size numTaps. Coefficients are stored in time reversed order. 

+
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 

+
pState points to a state array of size numTaps + blockSize - 1. Samples in the state buffer are stored in the order: 

+
   
+    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}   
+ 
 The state variables are updated after each block of data is processed, the coefficients are untouched.

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable array should be allocated separately. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+
  • Checks to make sure that the size of the input is a multiple of the decimation factor.
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. The code below statically initializes each of the 3 different data type filter instance structures 
   
+arm_fir_decimate_instance_f32 S = {M, numTaps, pCoeffs, pState};   
+arm_fir_decimate_instance_q31 S = {M, numTaps, pCoeffs, pState};   
+arm_fir_decimate_instance_q15 S = {M, numTaps, pCoeffs, pState};   
+ 
 where M is the decimation factor; numTaps is the number of filter coefficients in the filter; pCoeffs is the address of the coefficient buffer; pState is the address of the state buffer. Be sure to set the values in the state buffer to zeros when doing static initialization.

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the FIR decimate filter functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

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arm_status arm_fir_decimate_init_f32 (arm_fir_decimate_instance_f32 *  S, 
uint16_t  numTaps, 
uint8_t  M, 
float32_t *  pCoeffs, 
float32_t *  pState, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the floating-point FIR decimator. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point FIR decimator structure. 
[in]numTapsnumber of coefficients in the filter. 
[in]Mdecimation factor. 
[in]*pCoeffspoints to the filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if blockSize is not a multiple of M.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 

+
pState points to the array of state variables. pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_f32(). M is the decimation factor. 

+
+
Definition at line 67 of file arm_fir_decimate_init_f32.c.

+
+

+

+
+

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void arm_fir_decimate_f32 (const arm_fir_decimate_instance_f32 *  S, 
float32_t *  pSrc, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the floating-point FIR decimator. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point FIR decimator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none. 

+
+
Definition at line 132 of file arm_fir_decimate_f32.c.

+
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+

+
+

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arm_status arm_fir_decimate_init_q31 (arm_fir_decimate_instance_q31 *  S, 
uint16_t  numTaps, 
uint8_t  M, 
q31_t *  pCoeffs, 
q31_t *  pState, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the Q31 FIR decimator. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 FIR decimator structure. 
[in]numTapsnumber of coefficients in the filter. 
[in]Mdecimation factor. 
[in]*pCoeffspoints to the filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if blockSize is not a multiple of M.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 

+
pState points to the array of state variables. pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_q31(). M is the decimation factor. 

+
+
Definition at line 67 of file arm_fir_decimate_init_q31.c.

+
+

+

+
+

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void arm_fir_decimate_q31 (const arm_fir_decimate_instance_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q31 FIR decimator. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 FIR decimator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2). After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.

+
Refer to the function arm_fir_decimate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4. 

+
+
Definition at line 64 of file arm_fir_decimate_q31.c.

+
+

+

+
+

+

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+      
void arm_fir_decimate_fast_q31 (arm_fir_decimate_instance_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 FIR decimator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none

+
Scaling and Overflow Behavior:

+
This function is optimized for speed at the expense of fixed-point precision and overflow protection. The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. These intermediate results are added to a 2.30 accumulator. Finally, the accumulator is saturated and converted to a 1.31 result. The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).

+
Refer to the function arm_fir_decimate_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. Both the slow and the fast versions use the same instance structure. Use the function arm_fir_decimate_init_q31() to initialize the filter structure. 

+
+
Definition at line 65 of file arm_fir_decimate_fast_q31.c.

+
+

+

+
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arm_status arm_fir_decimate_init_q15 (arm_fir_decimate_instance_q15 *  S, 
uint16_t  numTaps, 
uint8_t  M, 
q15_t *  pCoeffs, 
q15_t *  pState, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the Q15 FIR decimator. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 FIR decimator structure. 
[in]numTapsnumber of coefficients in the filter. 
[in]Mdecimation factor. 
[in]*pCoeffspoints to the filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if blockSize is not a multiple of M.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 

+
pState points to the array of state variables. pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples to the call arm_fir_decimate_q15(). M is the decimation factor. 

+
+
Definition at line 68 of file arm_fir_decimate_init_q15.c.

+
+

+

+
+

+

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void arm_fir_decimate_q15 (const arm_fir_decimate_instance_q15 *  S, 
q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q15 FIR decimator. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 FIR decimator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the location where the output result is written. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format.

+
Refer to the function arm_fir_decimate_fast_q15() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4. 

+
+
Definition at line 65 of file arm_fir_decimate_q15.c.

+
+

+

+
+

+

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void arm_fir_decimate_fast_q15 (const arm_fir_decimate_instance_q15 *  S, 
q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 FIR decimator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none

+
Scaling and Overflow Behavior: 

+
This fast version uses a 32-bit accumulator with 2.30 format. The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around and distorts the result. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (log2 is read as log to the base 2). The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.

+
Refer to the function arm_fir_decimate_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure. Use the function arm_fir_decimate_init_q15() to initialize the filter structure. 

+
+
Definition at line 63 of file arm_fir_decimate_fast_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___f_i_r_l_p_f.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___f_i_r_l_p_f.html
new file mode 100644
index 000000000..8d3f3217a
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___f_i_r_l_p_f.html
@@ -0,0 +1,121 @@
+
+
+
+
+CMSIS DSP Software Library: FIR Lowpass Filter Example
+
+
+
+
+
+
+
+
+
+

+  

+
FIR Lowpass Filter Example

+
+[Examples]
+
  

+

+

+
+

+
Description: 

+
Removes high frequency signal components from the input using an FIR lowpass filter. The example demonstrates how to configure an FIR filter and then pass data through it in a block-by-block fashion. 

+FIRLPF_signalflow.gif
+

+

+
Algorithm:

+
The input signal is a sum of two sine waves: 1 kHz and 15 kHz. This is processed by an FIR lowpass filter with cutoff frequency 6 kHz. The lowpass filter eliminates the 15 kHz signal leaving only the 1 kHz sine wave at the output. 

+
The lowpass filter was designed using MATLAB with a sample rate of 48 kHz and a length of 29 points. The MATLAB code to generate the filter coefficients is shown below: 
+     h = fir1(28, 6/24);
+ 
 The first argument is the "order" of the filter and is always one less than the desired length. The second argument is the normalized cutoff frequency. This is in the range 0 (DC) to 1.0 (Nyquist). A 6 kHz cutoff with a Nyquist frequency of 24 kHz lies at a normalized frequency of 6/24 = 0.25. The CMSIS FIR filter function requires the coefficients to be in time reversed order. 
+     fliplr(h)
+ 
 The resulting filter coefficients and are shown below. Note that the filter is symmetric (a property of linear phase FIR filters) and the point of symmetry is sample 14. Thus the filter will have a delay of 14 samples for all frequencies. 

+

+FIRLPF_coeffs.gif
+

+ 

+
The frequency response of the filter is shown next. The passband gain of the filter is 1.0 and it reaches 0.5 at the cutoff frequency 6 kHz. 

+

+FIRLPF_response.gif
+

+ 

+
The input signal is shown below. The left hand side shows the signal in the time domain while the right hand side is a frequency domain representation. The two sine wave components can be clearly seen. 

+

+FIRLPF_input.gif
+

+ 

+
The output of the filter is shown below. The 15 kHz component has been eliminated. 

+

+FIRLPF_output.gif
+

+

+
Variables Description:

+
    
+
  • testInput_f32_1kHz_15kHz points to the input data 
    • 
+
  • refOutput points to the reference output data 
    • 
+
  • testOutput points to the test output data 
    • 
+
  • firStateF32 points to state buffer 
    • 
+
  • firCoeffs32 points to coefficient buffer 
    • 
+
  • blockSize number of samples processed at a time 
    • 
+
  • numBlocks number of frames
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_fir_example_f32.c 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___fill.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___fill.html
new file mode 100644
index 000000000..cf67b44f7
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___fill.html
@@ -0,0 +1,271 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Fill
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Fill

+
+[Support Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_fill_f32 (float32_t value, float32_t *pDst, uint32_t blockSize)
void arm_fill_q31 (q31_t value, q31_t *pDst, uint32_t blockSize)
void arm_fill_q15 (q15_t value, q15_t *pDst, uint32_t blockSize)
void arm_fill_q7 (q7_t value, q7_t *pDst, uint32_t blockSize)

+
Detailed Description

+
Fills the destination vector with a constant value.

+
   
+ 	pDst[n] = value;   0 <= n < blockSize.   
+ 
There are separate functions for floating point, Q31, Q15, and Q7 data types. 

+
Function Documentation

+
+

+

+      
+        
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+          
+          
+        
+      
void arm_fill_f32 (float32_t  value, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Fills a constant value into a floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]valueinput value to be filled 
[out]*pDstpoints to output vector 
[in]blockSizelength of the output vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_convolution_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 66 of file arm_fill_f32.c.

+
+

+

+
+

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+      
void arm_fill_q31 (q31_t  value, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Fills a constant value into a Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]valueinput value to be filled 
[out]*pDstpoints to output vector 
[in]blockSizelength of the output vector 

+  

+

+
Returns:
none. 

+
+
Definition at line 53 of file arm_fill_q31.c.

+
+

+

+
+

+

+      
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+      
void arm_fill_q15 (q15_t  value, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Fills a constant value into a Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]valueinput value to be filled 
[out]*pDstpoints to output vector 
[in]blockSizelength of the output vector 

+  

+

+
Returns:
none. 

+
+
Definition at line 53 of file arm_fill_q15.c.

+
+

+

+
+

+

+      
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+          
+          
+        
+      
void arm_fill_q7 (q7_t  value, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Fills a constant value into a Q7 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]valueinput value to be filled 
[out]*pDstpoints to output vector 
[in]blockSizelength of the output vector 

+  

+

+
Returns:
none. 

+
+
Definition at line 53 of file arm_fill_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___frequency_bin.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___frequency_bin.html
new file mode 100644
index 000000000..63e11d8e4
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___frequency_bin.html
@@ -0,0 +1,108 @@
+
+
+
+
+CMSIS DSP Software Library: Frequency Bin Example
+
+
+
+
+
+
+
+
+
+

+  

+
Frequency Bin Example

+
+[Examples]
+
  

+

+

+
+

+
Description

+
Demonstrates the calculation of the maximum energy bin in the frequency domain of the input signal with the use of Complex FFT, Complex Magnitude, and Maximum functions.

+
Algorithm:

+
The input test signal contains a 10 kHz signal with uniformly distributed white noise. Calculating the FFT of the input signal will give us the maximum energy of the bin corresponding to the input frequency of 10 kHz.

+
Block Diagram:

+FFTBin.gif
+
Block Diagram

+ 

+
The figure below shows the time domain signal of 10 kHz signal with uniformly distributed white noise, and the next figure shows the input in the frequency domain. The bin with maximum energy corresponds to 10 kHz signal. 

+

+FFTBinInput.gif
+
Input signal in Time domain

+ 

+FFTBinOutput.gif
+
Input signal in Frequency domain

+ 

+
Variables Description:

+
    
+
  • testInput_f32_10khz points to the input data 
    • 
+
  • testOutput points to the output data 
    • 
+
  • fftSize length of FFT 
    • 
+
  • ifftFlag flag for the selection of CFFT/CIFFT 
    • 
+
  • doBitReverse Flag for selection of normal order or bit reversed order 
    • 
+
  • refIndex reference index value at which maximum energy of bin ocuurs 
    • 
+
  • testIndex calculated index value at which maximum energy of bin ocuurs
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_fft_bin_example_f32.c 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___g_e_q5_band.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___g_e_q5_band.html
new file mode 100644
index 000000000..e515aa945
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___g_e_q5_band.html
@@ -0,0 +1,130 @@
+
+
+
+
+CMSIS DSP Software Library: Graphic Audio Equalizer Example
+
+
+
+
+
+
+
+
+
+

+  

+
Graphic Audio Equalizer Example

+
+[Examples]
+
  

+

+

+
+

+
Description: 

+
This example demonstrates how a 5-band graphic equalizer can be constructed using the Biquad cascade functions. A graphic equalizer is used in audio applications to vary the tonal quality of the audio.

+
Block Diagram:

+
The design is based on a cascade of 5 filter sections. 

+GEQ_signalflow.gif
+

+ Each filter section is 4th order and consists of a cascade of two Biquads. Each filter has a nominal gain of 0 dB (1.0 in linear units) and boosts or cuts signals within a specific frequency range. The edge frequencies between the 5 bands are 100, 500, 2000, and 6000 Hz. Each band has an adjustable boost or cut in the range of +/- 9 dB. For example, the band that extends from 500 to 2000 Hz has the response shown below: 

+

+GEQ_bandresponse.gif
+

+ 

+
With 1 dB steps, each filter has a total of 19 different settings. The filter coefficients for all possible 19 settings were precomputed in MATLAB and stored in a table. With 5 different tables, there are a total of 5 x 19 = 95 different 4th order filters. All 95 responses are shown below: 

+

+GEQ_allbandresponse.gif
+

+ 

+
Each 4th order filter has 10 coefficents for a grand total of 950 different filter coefficients that must be tabulated. The input and output data is in Q31 format. For better noise performance, the two low frequency bands are implemented using the high precision 32x64-bit Biquad filters. The remaining 3 high frequency bands use standard 32x32-bit Biquad filters. The input signal used in the example is a logarithmic chirp. 

+

+GEQ_inputchirp.gif
+

+ 

+
The array bandGains specifies the gain in dB to apply in each band. For example, if bandGains={0, -3, 6, 4, -6}; then the output signal will be: 

+

+GEQ_outputchirp.gif
+

+ 

+

+
Note:
The output chirp signal follows the gain or boost of each band. 

+

+
Variables Description:

+
    
+
  • testInput_f32 points to the input data 
    • 
+
  • testRefOutput_f32 points to the reference output data 
    • 
+
  • testOutput points to the test output data 
    • 
+
  • inputQ31 temporary input buffer 
    • 
+
  • outputQ31 temporary output buffer 
    • 
+
  • biquadStateBand1Q31 points to state buffer for band1 
    • 
+
  • biquadStateBand2Q31 points to state buffer for band2 
    • 
+
  • biquadStateBand3Q31 points to state buffer for band3 
    • 
+
  • biquadStateBand4Q31 points to state buffer for band4 
    • 
+
  • biquadStateBand5Q31 points to state buffer for band5 
    • 
+
  • coeffTable points to coefficient buffer for all bands 
    • 
+
  • gainDB gain buffer which has gains applied for all the bands
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_graphic_equalizer_example_q31.c 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___i_i_r___lattice.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___i_i_r___lattice.html
new file mode 100644
index 000000000..085ffb4e0
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___i_i_r___lattice.html
@@ -0,0 +1,478 @@
+
+
+
+
+CMSIS DSP Software Library: Infinite Impulse Response (IIR) Lattice Filters
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Infinite Impulse Response (IIR) Lattice Filters

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_iir_lattice_init_f32 (arm_iir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pkCoeffs, float32_t *pvCoeffs, float32_t *pState, uint32_t blockSize)
void arm_iir_lattice_f32 (const arm_iir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_iir_lattice_init_q31 (arm_iir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pkCoeffs, q31_t *pvCoeffs, q31_t *pState, uint32_t blockSize)
void arm_iir_lattice_q31 (const arm_iir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_iir_lattice_init_q15 (arm_iir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pkCoeffs, q15_t *pvCoeffs, q15_t *pState, uint32_t blockSize)
void arm_iir_lattice_q15 (const arm_iir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+
Detailed Description

+
This set of functions implements lattice filters for Q15, Q31 and floating-point data types. Lattice filters are used in a variety of adaptive filter applications. The filter structure has feedforward and feedback components and the net impulse response is infinite length. The functions operate on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc and pDst point to input and output arrays containing blockSize values.

+
Algorithm: 

+IIRLattice.gif
+
Infinite Impulse Response Lattice filter

+ 
   
+    fN(n)   =  x(n)   
+    fm-1(n) = fm(n) - km * gm-1(n-1)   for m = N, N-1, ...1   
+    gm(n)   = km * fm-1(n) + gm-1(n-1) for m = N, N-1, ...1   
+    y(n)    = vN * gN(n) + vN-1 * gN-1(n) + ...+ v0 * g0(n)   
+ 
 

+
pkCoeffs points to array of reflection coefficients of size numStages. Reflection coefficients are stored in time-reversed order. 

+
   
+    {kN, kN-1, ....k1}   
+ 
 pvCoeffs points to the array of ladder coefficients of size (numStages+1). Ladder coefficients are stored in time-reversed order. 

+
   
+    {vN, vN-1, ...v0}   
+ 
 pState points to a state array of size numStages + blockSize. The state variables shown in the figure above (the g values) are stored in the pState array. The state variables are updated after each block of data is processed; the coefficients are untouched. 

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros and then manually initialize the instance structure as follows: 
   
+arm_iir_lattice_instance_f32 S = {numStages, pState, pkCoeffs, pvCoeffs};   
+arm_iir_lattice_instance_q31 S = {numStages, pState, pkCoeffs, pvCoeffs};   
+arm_iir_lattice_instance_q15 S = {numStages, pState, pkCoeffs, pvCoeffs};   
+ 
 

+
where numStages is the number of stages in the filter; pState points to the state buffer array; pkCoeffs points to array of the reflection coefficients; pvCoeffs points to the array of ladder coefficients. 

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the IIR lattice filter functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

+      
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+      
void arm_iir_lattice_init_f32 (arm_iir_lattice_instance_f32 *  S, 
uint16_t  numStages, 
float32_t *  pkCoeffs, 
float32_t *  pvCoeffs, 
float32_t *  pState, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the floating-point IIR lattice filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point IIR lattice structure. 
[in]numStagesnumber of stages in the filter. 
[in]*pkCoeffspoints to the reflection coefficient buffer. The array is of length numStages. 
[in]*pvCoeffspoints to the ladder coefficient buffer. The array is of length numStages+1. 
[in]*pStatepoints to the state buffer. The array is of length numStages+blockSize. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
+
Definition at line 55 of file arm_iir_lattice_init_f32.c.

+
+

+

+
+

+

+      
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+          
+        
+      
void arm_iir_lattice_f32 (const arm_iir_lattice_instance_f32 *  S, 
float32_t *  pSrc, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the floating-point IIR lattice filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point IIR lattice structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
+
Definition at line 120 of file arm_iir_lattice_f32.c.

+
+

+

+
+

+

+      
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void arm_iir_lattice_init_q31 (arm_iir_lattice_instance_q31 *  S, 
uint16_t  numStages, 
q31_t *  pkCoeffs, 
q31_t *  pvCoeffs, 
q31_t *  pState, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the Q31 IIR lattice filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 IIR lattice structure. 
[in]numStagesnumber of stages in the filter. 
[in]*pkCoeffspoints to the reflection coefficient buffer. The array is of length numStages. 
[in]*pvCoeffspoints to the ladder coefficient buffer. The array is of length numStages+1. 
[in]*pStatepoints to the state buffer. The array is of length numStages+blockSize. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
+
Definition at line 55 of file arm_iir_lattice_init_q31.c.

+
+

+

+
+

+

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void arm_iir_lattice_q31 (const arm_iir_lattice_instance_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q31 IIR lattice filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 IIR lattice structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by 2*log2(numStages) bits. After all multiply-accumulates are performed, the 2.62 accumulator is saturated to 1.32 format and then truncated to 1.31 format. 

+
+
Definition at line 62 of file arm_iir_lattice_q31.c.

+
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void arm_iir_lattice_init_q15 (arm_iir_lattice_instance_q15 *  S, 
uint16_t  numStages, 
q15_t *  pkCoeffs, 
q15_t *  pvCoeffs, 
q15_t *  pState, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the Q15 IIR lattice filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 IIR lattice structure. 
[in]numStagesnumber of stages in the filter. 
[in]*pkCoeffspoints to reflection coefficient buffer. The array is of length numStages. 
[in]*pvCoeffspoints to ladder coefficient buffer. The array is of length numStages+1. 
[in]*pStatepoints to state buffer. The array is of length numStages+blockSize. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none. 

+
+
Definition at line 55 of file arm_iir_lattice_init_q15.c.

+
+

+

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void arm_iir_lattice_q15 (const arm_iir_lattice_instance_q15 *  S, 
q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q15 IIR lattice filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 IIR lattice structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format. 

+
+
Definition at line 63 of file arm_iir_lattice_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___l_m_s.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___l_m_s.html
new file mode 100644
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--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___l_m_s.html
@@ -0,0 +1,557 @@
+
+
+
+
+CMSIS DSP Software Library: Least Mean Square (LMS) Filters
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Least Mean Square (LMS) Filters

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_lms_init_f32 (arm_lms_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize)
void arm_lms_f32 (const arm_lms_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize)
void arm_lms_init_q31 (arm_lms_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint32_t postShift)
void arm_lms_q31 (const arm_lms_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize)
void arm_lms_init_q15 (arm_lms_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint32_t postShift)
void arm_lms_q15 (const arm_lms_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize)

+
Detailed Description

+
LMS filters are a class of adaptive filters that are able to "learn" an unknown transfer functions. LMS filters use a gradient descent method in which the filter coefficients are updated based on the instantaneous error signal. Adaptive filters are often used in communication systems, equalizers, and noise removal. The CMSIS DSP Library contains LMS filter functions that operate on Q15, Q31, and floating-point data types. The library also contains normalized LMS filters in which the filter coefficient adaptation is indepedent of the level of the input signal.

+
An LMS filter consists of two components as shown below. The first component is a standard transversal or FIR filter. The second component is a coefficient update mechanism. The LMS filter has two input signals. The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter. That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input. The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input. This "error signal" tends towards zero as the filter adapts. The LMS processing functions accept the input and reference input signals and generate the filter output and error signal. 

+

+LMS.gif
+
Internal structure of the Least Mean Square filter

+
The functions operate on blocks of data and each call to the function processes blockSize samples through the filter. pSrc points to input signal, pRef points to reference signal, pOut points to output signal and pErr points to error signal. All arrays contain blockSize values.

+
The functions operate on a block-by-block basis. Internally, the filter coefficients b[n] are updated on a sample-by-sample basis. The convergence of the LMS filter is slower compared to the normalized LMS algorithm.

+
Algorithm: 
The output signal y[n] is computed by a standard FIR filter: 
   
+     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]   
+ 

+
The error signal equals the difference between the reference signal d[n] and the filter output: 
   
+     e[n] = d[n] - y[n].   
+ 

+
After each sample of the error signal is computed, the filter coefficients b[k] are updated on a sample-by-sample basis: 
   
+     b[k] = b[k] + e[n] * mu * x[n-k],  for k=0, 1, ..., numTaps-1   
+ 
 where mu is the step size and controls the rate of coefficient convergence. 

+
In the APIs, pCoeffs points to a coefficient array of size numTaps. Coefficients are stored in time reversed order. 

+
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 

+
pState points to a state array of size numTaps + blockSize - 1. Samples in the state buffer are stored in the order: 

+
   
+    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}   
+ 
 

+
Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples. The increased state buffer length allows circular addressing, which is traditionally used in FIR filters, to be avoided and yields a significant speed improvement. The state variables are updated after each block of data is processed. 

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter and coefficient and state arrays cannot be shared among instances. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer. 
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros before static initialization. The code below statically initializes each of the 3 different data type filter instance structures 
   
+    arm_lms_instance_f32 S = {numTaps, pState, pCoeffs, mu};   
+    arm_lms_instance_q31 S = {numTaps, pState, pCoeffs, mu, postShift};   
+    arm_lms_instance_q15 S = {numTaps, pState, pCoeffs, mu, postShift};   
+ 
 where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer; pCoeffs is the address of the coefficient buffer; mu is the step size parameter; and postShift is the shift applied to coefficients.

+
Fixed-Point Behavior: 
Care must be taken when using the Q15 and Q31 versions of the LMS filter. The following issues must be considered:
    
+
  • Scaling of coefficients
    • 
+
  • Overflow and saturation
    • 
+

+

+
Scaling of Coefficients: 
Filter coefficients are represented as fractional values and coefficients are restricted to lie in the range [-1 +1). The fixed-point functions have an additional scaling parameter postShift. At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. This essentially scales the filter coefficients by 2^postShift and allows the filter coefficients to exceed the range [+1 -1). The value of postShift is set by the user based on the expected gain through the system being modeled.

+
Overflow and Saturation: 
Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are described separately as part of the function specific documentation below. 

+
Function Documentation

+
+

+

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void arm_lms_init_f32 (arm_lms_instance_f32 *  S, 
uint16_t  numTaps, 
float32_t *  pCoeffs, 
float32_t *  pState, 
float32_t  mu, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for floating-point LMS filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point LMS filter structure. 
[in]numTapsnumber of filter coefficients. 
[in]*pCoeffspoints to the coefficient buffer. 
[in]*pStatepoints to state buffer. 
[in]mustep size that controls filter coefficient updates. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
Description: 
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 The initial filter coefficients serve as a starting point for the adaptive filter. pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_f32(). 

+
+
Definition at line 61 of file arm_lms_init_f32.c.

+
+

+

+
+

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void arm_lms_f32 (const arm_lms_instance_f32 *  S, 
float32_t *  pSrc, 
float32_t *  pRef, 
float32_t *  pOut, 
float32_t *  pErr, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for floating-point LMS filter. 

+
This function operates on floating-point data types.

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point LMS filter structure. 
[in]*pSrcpoints to the block of input data. 
[in]*pRefpoints to the block of reference data. 
[out]*pOutpoints to the block of output data. 
[out]*pErrpoints to the block of error data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
+
Definition at line 170 of file arm_lms_f32.c.

+
+

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void arm_lms_init_q31 (arm_lms_instance_q31 *  S, 
uint16_t  numTaps, 
q31_t *  pCoeffs, 
q31_t *  pState, 
q31_t  mu, 
uint32_t  blockSize, 
uint32_t  postShift 
)

+

+

+
+
Initialization function for Q31 LMS filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 LMS filter structure. 
[in]numTapsnumber of filter coefficients. 
[in]*pCoeffspoints to coefficient buffer. 
[in]*pStatepoints to state buffer. 
[in]mustep size that controls filter coefficient updates. 
[in]blockSizenumber of samples to process. 
[in]postShiftbit shift applied to coefficients. 

+  

+

+
Returns:
none.

+
Description: 
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 The initial filter coefficients serve as a starting point for the adaptive filter. pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_q31(). 

+
+
Definition at line 66 of file arm_lms_init_q31.c.

+
+

+

+
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void arm_lms_q31 (const arm_lms_instance_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pRef, 
q31_t *  pOut, 
q31_t *  pErr, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for Q31 LMS filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 LMS filter structure. 
[in]*pSrcpoints to the block of input data. 
[in]*pRefpoints to the block of reference data. 
[out]*pOutpoints to the block of output data. 
[out]*pErrpoints to the block of error data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clips. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. The reference signal should not be scaled down. After all multiply-accumulates are performed, the 2.62 accumulator is shifted and saturated to 1.31 format to yield the final result. The output signal and error signal are in 1.31 format.

+
In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted. 

+
+
Definition at line 69 of file arm_lms_q31.c.

+
+

+

+
+

+

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void arm_lms_init_q15 (arm_lms_instance_q15 *  S, 
uint16_t  numTaps, 
q15_t *  pCoeffs, 
q15_t *  pState, 
q15_t  mu, 
uint32_t  blockSize, 
uint32_t  postShift 
)

+

+

+
+
Initialization function for the Q15 LMS filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 LMS filter structure. 
[in]numTapsnumber of filter coefficients. 
[in]*pCoeffspoints to the coefficient buffer. 
[in]*pStatepoints to the state buffer. 
[in]mustep size that controls filter coefficient updates. 
[in]blockSizenumber of samples to process. 
[in]postShiftbit shift applied to coefficients. 

+  

+

+
Returns:
none.

+
Description: 
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 The initial filter coefficients serve as a starting point for the adaptive filter. pState points to the array of state variables and size of array is numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_q15(). 

+
+
Definition at line 66 of file arm_lms_init_q15.c.

+
+

+

+
+

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void arm_lms_q15 (const arm_lms_instance_q15 *  S, 
q15_t *  pSrc, 
q15_t *  pRef, 
q15_t *  pOut, 
q15_t *  pErr, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for Q15 LMS filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 LMS filter structure. 
[in]*pSrcpoints to the block of input data. 
[in]*pRefpoints to the block of reference data. 
[out]*pOutpoints to the block of output data. 
[out]*pErrpoints to the block of error data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 
The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format.

+
In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted. 

+
+
Definition at line 66 of file arm_lms_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___l_m_s___n_o_r_m.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___l_m_s___n_o_r_m.html
new file mode 100644
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--- /dev/null
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+
+
+CMSIS DSP Software Library: Normalized LMS Filters
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Normalized LMS Filters

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_lms_norm_init_f32 (arm_lms_norm_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize)
void arm_lms_norm_f32 (arm_lms_norm_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize)
void arm_lms_norm_init_q31 (arm_lms_norm_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint8_t postShift)
void arm_lms_norm_q31 (arm_lms_norm_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize)
void arm_lms_norm_init_q15 (arm_lms_norm_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint8_t postShift)
void arm_lms_norm_q15 (arm_lms_norm_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize)

+
Detailed Description

+
This set of functions implements a commonly used adaptive filter. It is related to the Least Mean Square (LMS) adaptive filter and includes an additional normalization factor which increases the adaptation rate of the filter. The CMSIS DSP Library contains normalized LMS filter functions that operate on Q15, Q31, and floating-point data types.

+
A normalized least mean square (NLMS) filter consists of two components as shown below. The first component is a standard transversal or FIR filter. The second component is a coefficient update mechanism. The NLMS filter has two input signals. The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter. That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input. The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input. This "error signal" tends towards zero as the filter adapts. The NLMS processing functions accept the input and reference input signals and generate the filter output and error signal. 

+

+LMS.gif
+
Internal structure of the NLMS adaptive filter

+
The functions operate on blocks of data and each call to the function processes blockSize samples through the filter. pSrc points to input signal, pRef points to reference signal, pOut points to output signal and pErr points to error signal. All arrays contain blockSize values.

+
The functions operate on a block-by-block basis. Internally, the filter coefficients b[n] are updated on a sample-by-sample basis. The convergence of the LMS filter is slower compared to the normalized LMS algorithm.

+
Algorithm: 
The output signal y[n] is computed by a standard FIR filter: 
   
+     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]   
+ 

+
The error signal equals the difference between the reference signal d[n] and the filter output: 
   
+     e[n] = d[n] - y[n].   
+ 

+
After each sample of the error signal is computed the instanteous energy of the filter state variables is calculated: 
   
+    E = x[n]^2 + x[n-1]^2 + ... + x[n-numTaps+1]^2.   
+ 
 The filter coefficients b[k] are then updated on a sample-by-sample basis: 
   
+     b[k] = b[k] + e[n] * (mu/E) * x[n-k],  for k=0, 1, ..., numTaps-1   
+ 
 where mu is the step size and controls the rate of coefficient convergence. 

+
In the APIs, pCoeffs points to a coefficient array of size numTaps. Coefficients are stored in time reversed order. 

+
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 

+
pState points to a state array of size numTaps + blockSize - 1. Samples in the state buffer are stored in the order: 

+
   
+    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}   
+ 
 

+
Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples. The increased state buffer length allows circular addressing, which is traditionally used in FIR filters, to be avoided and yields a significant speed improvement. The state variables are updated after each block of data is processed. 

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter and coefficient and state arrays cannot be shared among instances. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer. 
    • 
+

+

+
Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. 

+
Fixed-Point Behavior: 
Care must be taken when using the Q15 and Q31 versions of the normalised LMS filter. The following issues must be considered:
    
+
  • Scaling of coefficients
    • 
+
  • Overflow and saturation
    • 
+

+

+
Scaling of Coefficients: 
Filter coefficients are represented as fractional values and coefficients are restricted to lie in the range [-1 +1). The fixed-point functions have an additional scaling parameter postShift. At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. This essentially scales the filter coefficients by 2^postShift and allows the filter coefficients to exceed the range [+1 -1). The value of postShift is set by the user based on the expected gain through the system being modeled.

+
Overflow and Saturation: 
Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are described separately as part of the function specific documentation below. 

+
Function Documentation

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void arm_lms_norm_init_f32 (arm_lms_norm_instance_f32 *  S, 
uint16_t  numTaps, 
float32_t *  pCoeffs, 
float32_t *  pState, 
float32_t  mu, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for floating-point normalized LMS filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point LMS filter structure. 
[in]numTapsnumber of filter coefficients. 
[in]*pCoeffspoints to coefficient buffer. 
[in]*pStatepoints to state buffer. 
[in]mustep size that controls filter coefficient updates. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
Description: 
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 The initial filter coefficients serve as a starting point for the adaptive filter. pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_norm_f32(). 

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Definition at line 64 of file arm_lms_norm_init_f32.c.

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void arm_lms_norm_f32 (arm_lms_norm_instance_f32 *  S, 
float32_t *  pSrc, 
float32_t *  pRef, 
float32_t *  pOut, 
float32_t *  pErr, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for floating-point normalized LMS filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point normalized LMS filter structure. 
[in]*pSrcpoints to the block of input data. 
[in]*pRefpoints to the block of reference data. 
[out]*pOutpoints to the block of output data. 
[out]*pErrpoints to the block of error data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Definition at line 160 of file arm_lms_norm_f32.c.

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void arm_lms_norm_init_q31 (arm_lms_norm_instance_q31 *  S, 
uint16_t  numTaps, 
q31_t *  pCoeffs, 
q31_t *  pState, 
q31_t  mu, 
uint32_t  blockSize, 
uint8_t  postShift 
)

+

+

+
+
Initialization function for Q31 normalized LMS filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 normalized LMS filter structure. 
[in]numTapsnumber of filter coefficients. 
[in]*pCoeffspoints to coefficient buffer. 
[in]*pStatepoints to state buffer. 
[in]mustep size that controls filter coefficient updates. 
[in]blockSizenumber of samples to process. 
[in]postShiftbit shift applied to coefficients. 

+  

+

+
Returns:
none.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 The initial filter coefficients serve as a starting point for the adaptive filter. pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_norm_q31(). 

+
+
Definition at line 63 of file arm_lms_norm_init_q31.c.

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void arm_lms_norm_q31 (arm_lms_norm_instance_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pRef, 
q31_t *  pOut, 
q31_t *  pErr, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for Q31 normalized LMS filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 normalized LMS filter structure. 
[in]*pSrcpoints to the block of input data. 
[in]*pRefpoints to the block of reference data. 
[out]*pOutpoints to the block of output data. 
[out]*pErrpoints to the block of error data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. The reference signal should not be scaled down. After all multiply-accumulates are performed, the 2.62 accumulator is shifted and saturated to 1.31 format to yield the final result. The output signal and error signal are in 1.31 format.

+
In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted. 

+
+
Definition at line 72 of file arm_lms_norm_q31.c.

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void arm_lms_norm_init_q15 (arm_lms_norm_instance_q15 *  S, 
uint16_t  numTaps, 
q15_t *  pCoeffs, 
q15_t *  pState, 
q15_t  mu, 
uint32_t  blockSize, 
uint8_t  postShift 
)

+

+

+
+
Initialization function for Q15 normalized LMS filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 normalized LMS filter structure. 
[in]numTapsnumber of filter coefficients. 
[in]*pCoeffspoints to coefficient buffer. 
[in]*pStatepoints to state buffer. 
[in]mustep size that controls filter coefficient updates. 
[in]blockSizenumber of samples to process. 
[in]postShiftbit shift applied to coefficients. 

+  

+

+
Returns:
none.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 The initial filter coefficients serve as a starting point for the adaptive filter. pState points to the array of state variables and size of array is numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_norm_q15(). 

+
+
Definition at line 64 of file arm_lms_norm_init_q15.c.

+
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void arm_lms_norm_q15 (arm_lms_norm_instance_q15 *  S, 
q15_t *  pSrc, 
q15_t *  pRef, 
q15_t *  pOut, 
q15_t *  pErr, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for Q15 normalized LMS filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 normalized LMS filter structure. 
[in]*pSrcpoints to the block of input data. 
[in]*pRefpoints to the block of reference data. 
[out]*pOutpoints to the block of output data. 
[out]*pErrpoints to the block of error data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format.

+
In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted. 

+
+
Definition at line 71 of file arm_lms_norm_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___linear_interp_example.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___linear_interp_example.html
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+
+
+
+
+CMSIS DSP Software Library: Linear Interpolate Example
+
+
+
+
+
+
+
+
+
+

+  

+
Linear Interpolate Example

+
+[Examples]
+
  

+

+

+
+

+
 CMSIS DSP Software Library -- Linear Interpolate Example 

+
 Description  This example demonstrates usage of linear interpolate modules and fast math modules. Method 1 uses fast math sine function to calculate sine values using cubic interpolation and method 2 uses linear interpolation function and results are compared to reference output. Example shows linear interpolation function can be used to get higher precision compared to fast math sin calculation.

+
Block Diagram:

+

+linearInterpExampleMethod1.gif
+
Method 1: Sine caluclation using fast math

+ 

+

+linearInterpExampleMethod2.gif
+
Method 2: Sine caluclation using interpolation function

+ 

+
Variables Description:

+
    
+
  • testInputSin_f32 points to the input values for sine calculation 
    • 
+
  • testRefSinOutput32_f32 points to the reference values caculated from sin() matlab function 
    • 
+
  • testOutput points to output buffer calculation from cubic interpolation 
    • 
+
  • testLinIntOutput points to output buffer calculation from linear interpolation 
    • 
+
  • snr1 Signal to noise ratio for reference and cubic interpolation output 
    • 
+
  • snr2 Signal to noise ratio for reference and linear interpolation output
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_linear_interp_example_f32.c 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
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+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___linear_interpolate.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___linear_interpolate.html
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+
+
+
+
+CMSIS DSP Software Library: Linear Interpolation
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Linear Interpolation

+
+[Interpolation Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
static __INLINE float32_t arm_linear_interp_f32 (arm_linear_interp_instance_f32 *S, float32_t x)
static __INLINE q31_t arm_linear_interp_q31 (q31_t *pYData, q31_t x, uint32_t nValues)
static __INLINE q15_t arm_linear_interp_q15 (q15_t *pYData, q31_t x, uint32_t nValues)
static __INLINE q7_t arm_linear_interp_q7 (q7_t *pYData, q31_t x, uint32_t nValues)

+
Detailed Description

+
Linear interpolation is a method of curve fitting using linear polynomials. Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line

+

+LinearInterp.gif
+
Linear interpolation

+ 

+
A Linear Interpolate function calculates an output value(y), for the input(x) using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)

+
Algorithm:
+       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+       where x0, x1 are nearest values of input x
+             y0, y1 are nearest values to output y
+ 

+
This set of functions implements Linear interpolation process for Q7, Q15, Q31, and floating-point data types. The functions operate on a single sample of data and each call to the function returns a single processed value. S points to an instance of the Linear Interpolate function data structure. x is the input sample value. The functions returns the output value.

+
if x is outside of the table boundary, Linear interpolation returns first value of the table if x is below input range and returns last value of table if x is above range. 

+
Function Documentation

+
+

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static __INLINE float32_t arm_linear_interp_f32 (arm_linear_interp_instance_f32 *  S, 
float32_t  x 
) [static]

+

+

+
+
Process function for the floating-point Linear Interpolation Function. 

+
Parameters:

+  
+    
+    
+  
[in,out]*Sis an instance of the floating-point Linear Interpolation structure 
[in]xinput sample to process 

+  

+

+
Returns:
y processed output sample. 

+
Examples: 
arm_linear_interp_example_f32.c.

+

+
Definition at line 5377 of file arm_math.h.

+
+

+

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static __INLINE q31_t arm_linear_interp_q31 (q31_t *  pYData, 
q31_t  x, 
uint32_t  nValues 
) [static]

+

+

+
+
Process function for the Q31 Linear Interpolation Function. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pYDatapointer to Q31 Linear Interpolation table 
[in]xinput sample to process 
[in]nValuesnumber of table values 

+  

+

+
Returns:
y processed output sample.

+
Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. This function can support maximum of table size 2^12. 

+
+
Definition at line 5436 of file arm_math.h.

+
+

+

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static __INLINE q15_t arm_linear_interp_q15 (q15_t *  pYData, 
q31_t  x, 
uint32_t  nValues 
) [static]

+

+

+
+
Process function for the Q15 Linear Interpolation Function. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pYDatapointer to Q15 Linear Interpolation table 
[in]xinput sample to process 
[in]nValuesnumber of table values 

+  

+

+
Returns:
y processed output sample.

+
Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. This function can support maximum of table size 2^12. 

+
+
Definition at line 5496 of file arm_math.h.

+
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static __INLINE q7_t arm_linear_interp_q7 (q7_t *  pYData, 
q31_t  x, 
uint32_t  nValues 
) [static]

+

+

+
+
Process function for the Q7 Linear Interpolation Function. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pYDatapointer to Q7 Linear Interpolation table 
[in]xinput sample to process 
[in]nValuesnumber of table values 

+  

+

+
Returns:
y processed output sample.

+
Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. This function can support maximum of table size 2^12. 

+
+
Definition at line 5553 of file arm_math.h.

+
+

+

+

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+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___matrix_add.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___matrix_add.html
new file mode 100644
index 000000000..6f28611c7
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___matrix_add.html
@@ -0,0 +1,228 @@
+
+
+
+
+CMSIS DSP Software Library: Matrix Addition
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Matrix Addition

+
+[Matrix Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
arm_status arm_mat_add_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
arm_status arm_mat_add_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
arm_status arm_mat_add_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst)

+
Detailed Description

+
Adds two matrices. 

+

+MatrixAddition.gif
+
Addition of two 3 x 3 matrices

+
The functions check to make sure that pSrcA, pSrcB, and pDst have the same number of rows and columns. 

+
Function Documentation

+
+

+

+      
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arm_status arm_mat_add_f32 (const arm_matrix_instance_f32 *  pSrcA, 
const arm_matrix_instance_f32 *  pSrcB, 
arm_matrix_instance_f32 *  pDst 
)

+

+

+
+
Floating-point matrix addition. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 

+
+
Definition at line 68 of file arm_mat_add_f32.c.

+
+

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arm_status arm_mat_add_q31 (const arm_matrix_instance_q31 *  pSrcA, 
const arm_matrix_instance_q31 *  pSrcB, 
arm_matrix_instance_q31 *  pDst 
)

+

+

+
+
Q31 matrix addition. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. 

+
+
Definition at line 61 of file arm_mat_add_q31.c.

+
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arm_status arm_mat_add_q15 (const arm_matrix_instance_q15 *  pSrcA, 
const arm_matrix_instance_q15 *  pSrcB, 
arm_matrix_instance_q15 *  pDst 
)

+

+

+
+
Q15 matrix addition. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 

+
+
Definition at line 61 of file arm_mat_add_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___matrix_example.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___matrix_example.html
new file mode 100644
index 000000000..ca3c0acbd
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___matrix_example.html
@@ -0,0 +1,100 @@
+
+
+
+
+CMSIS DSP Software Library: Matrix Example
+
+
+
+
+
+
+
+
+
+

+  

+
Matrix Example

+
+[Examples]
+
  

+

+

+
+

+
Description: 

+
Demonstrates the use of Matrix Transpose, Matrix Muliplication, and Matrix Inverse functions to apply least squares fitting to input data. Least squares fitting is the procedure for finding the best-fitting curve that minimizes the sum of the squares of the offsets (least square error) from a given set of data.

+
Algorithm:

+
The linear combination of parameters considered is as follows: 

+
A * X = B, where X is the unknown value and can be estimated from A & B. 

+
The least squares estimate X is given by the following equation: 

+
X = Inverse(AT * A) * AT * B

+
Block Diagram:

+

+matrixExample.gif
+

+

+
Variables Description:

+
    
+
  • A_f32 input matrix in the linear combination equation 
    • 
+
  • B_f32 output matrix in the linear combination equation 
    • 
+
  • X_f32 unknown matrix estimated using A_f32 & B_f32 matrices
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_matrix_example_f32.c 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___matrix_init.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___matrix_init.html
new file mode 100644
index 000000000..044685d25
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___matrix_init.html
@@ -0,0 +1,242 @@
+
+
+
+
+CMSIS DSP Software Library: Matrix Initialization
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Matrix Initialization

+
+[Matrix Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_mat_init_f32 (arm_matrix_instance_f32 *S, uint16_t nRows, uint16_t nColumns, float32_t *pData)
void arm_mat_init_q31 (arm_matrix_instance_q31 *S, uint16_t nRows, uint16_t nColumns, q31_t *pData)
void arm_mat_init_q15 (arm_matrix_instance_q15 *S, uint16_t nRows, uint16_t nColumns, q15_t *pData)

+
Detailed Description

+
Initializes the underlying matrix data structure. The functions set the numRows, numCols, and pData fields of the matrix data structure. 

+
Function Documentation

+
+

+

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void arm_mat_init_f32 (arm_matrix_instance_f32 *  S, 
uint16_t  nRows, 
uint16_t  nColumns, 
float32_t *  pData 
)

+

+

+
+
Floating-point matrix initialization. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point matrix structure. 
[in]nRowsnumber of rows in the matrix. 
[in]nColumnsnumber of columns in the matrix. 
[in]*pDatapoints to the matrix data array. 

+  

+

+
Returns:
none 

+
Examples: 
arm_class_marks_example_f32.c, and arm_matrix_example_f32.c.

+

+
Definition at line 65 of file arm_mat_init_f32.c.

+
+

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void arm_mat_init_q31 (arm_matrix_instance_q31 *  S, 
uint16_t  nRows, 
uint16_t  nColumns, 
q31_t *  pData 
)

+

+

+
+
Q31 matrix initialization. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point matrix structure. 
[in]nRowsnumber of rows in the matrix. 
[in]nColumnsnumber of columns in the matrix. 
[in]*pDatapoints to the matrix data array. 

+  

+

+
Returns:
none 

+
+
Definition at line 61 of file arm_mat_init_q31.c.

+
+

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void arm_mat_init_q15 (arm_matrix_instance_q15 *  S, 
uint16_t  nRows, 
uint16_t  nColumns, 
q15_t *  pData 
)

+

+

+
+
Q15 matrix initialization. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point matrix structure. 
[in]nRowsnumber of rows in the matrix. 
[in]nColumnsnumber of columns in the matrix. 
[in]*pDatapoints to the matrix data array. 

+  

+

+
Returns:
none 

+
+
Definition at line 57 of file arm_mat_init_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___matrix_inv.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___matrix_inv.html
new file mode 100644
index 000000000..a8b8e4e05
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___matrix_inv.html
@@ -0,0 +1,126 @@
+
+
+
+
+CMSIS DSP Software Library: Matrix Inverse
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Matrix Inverse

+
+[Matrix Functions]
+
  

+

+

+
+
+
+

+Functions
arm_status arm_mat_inverse_f32 (const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst)

+
Detailed Description

+
Computes the inverse of a matrix.

+
The inverse is defined only if the input matrix is square and non-singular (the determinant is non-zero). The function checks that the input and output matrices are square and of the same size.

+
Matrix inversion is numerically sensitive and the CMSIS DSP library only supports matrix inversion of floating-point matrices.

+
Algorithm 
The Gauss-Jordan method is used to find the inverse. The algorithm performs a sequence of elementary row-operations till it reduces the input matrix to an identity matrix. Applying the same sequence of elementary row-operations to an identity matrix yields the inverse matrix. If the input matrix is singular, then the algorithm terminates and returns error status ARM_MATH_SINGULAR. 

+MatrixInverse.gif
+
Matrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method

+ 

+
Function Documentation

+
+

+

+      
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+      
arm_status arm_mat_inverse_f32 (const arm_matrix_instance_f32 *  pSrc, 
arm_matrix_instance_f32 *  pDst 
)

+

+

+
+
Floating-point matrix inverse. 

+
Parameters:

+  
+    
+    
+  
[in]*pSrcpoints to input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns ARM_MATH_SIZE_MISMATCH if the input matrix is not square or if the size of the output matrix does not match the size of the input matrix. If the input matrix is found to be singular (non-invertible), then the function returns ARM_MATH_SINGULAR. Otherwise, the function returns ARM_MATH_SUCCESS. 

+
Examples: 
arm_matrix_example_f32.c.

+

+
Definition at line 74 of file arm_mat_inverse_f32.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___matrix_mult.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___matrix_mult.html
new file mode 100644
index 000000000..5b5cab263
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___matrix_mult.html
@@ -0,0 +1,347 @@
+
+
+
+
+CMSIS DSP Software Library: Matrix Multiplication
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Matrix Multiplication

+
+[Matrix Functions]
+
  

+

+

+
+
+
+
+
+
+
+

+Functions
arm_status arm_mat_mult_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
arm_status arm_mat_mult_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
arm_status arm_mat_mult_fast_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
arm_status arm_mat_mult_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState)
arm_status arm_mat_mult_fast_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState)

+
Detailed Description

+
Multiplies two matrices.

+

+MatrixMultiplication.gif
+
Multiplication of two 3 x 3 matrices

+
Matrix multiplication is only defined if the number of columns of the first matrix equals the number of rows of the second matrix. Multiplying an M x N matrix with an N x P matrix results in an M x P matrix. When matrix size checking is enabled, the functions check: (1) that the inner dimensions of pSrcA and pSrcB are equal; and (2) that the size of the output matrix equals the outer dimensions of pSrcA and pSrcB. 

+
Function Documentation

+
+

+

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arm_status arm_mat_mult_f32 (const arm_matrix_instance_f32 *  pSrcA, 
const arm_matrix_instance_f32 *  pSrcB, 
arm_matrix_instance_f32 *  pDst 
)

+

+

+
+
Floating-point matrix multiplication. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 

+
Examples: 
arm_class_marks_example_f32.c, and arm_matrix_example_f32.c.

+

+
Definition at line 73 of file arm_mat_mult_f32.c.

+
+

+

+
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arm_status arm_mat_mult_q31 (const arm_matrix_instance_q31 *  pSrcA, 
const arm_matrix_instance_q31 *  pSrcB, 
arm_matrix_instance_q31 *  pDst 
)

+

+

+
+
Q31 matrix multiplication. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior:

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. The input is thus scaled down by log2(numColsA) bits to avoid overflows, as a total of numColsA additions are performed internally. The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.

+
See arm_mat_mult_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4. 

+
+
Definition at line 73 of file arm_mat_mult_q31.c.

+
+

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+
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arm_status arm_mat_mult_fast_q31 (const arm_matrix_instance_q31 *  pSrcA, 
const arm_matrix_instance_q31 *  pSrcB, 
arm_matrix_instance_q31 *  pDst 
)

+

+

+
+
Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior:

+
The difference between the function arm_mat_mult_q31() and this fast variant is that the fast variant use a 32-bit rather than a 64-bit accumulator. The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 format. Finally, the accumulator is saturated and converted to a 1.31 result.

+
The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result. In order to avoid overflows completely the input signals must be scaled down. Scale down one of the input matrices by log2(numColsA) bits to avoid overflows, as a total of numColsA additions are computed internally for each output element.

+
See arm_mat_mult_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. 

+
+
Definition at line 72 of file arm_mat_mult_fast_q31.c.

+
+

+

+
+

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arm_status arm_mat_mult_q15 (const arm_matrix_instance_q15 *  pSrcA, 
const arm_matrix_instance_q15 *  pSrcB, 
arm_matrix_instance_q15 *  pDst, 
q15_t *  pState 
)

+

+

+
+
Q15 matrix multiplication. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 
[in]*pStatepoints to the array for storing intermediate results 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 64-bit internal accumulator. The inputs to the multiplications are in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. This approach provides 33 guard bits and there is no risk of overflow. The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.

+
Refer to arm_mat_mult_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4. 

+
+
Definition at line 74 of file arm_mat_mult_q15.c.

+
+

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arm_status arm_mat_mult_fast_q15 (const arm_matrix_instance_q15 *  pSrcA, 
const arm_matrix_instance_q15 *  pSrcB, 
arm_matrix_instance_q15 *  pDst, 
q15_t *  pState 
)

+

+

+
+
Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 
[in]*pStatepoints to the array for storing intermediate results 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior:

+
The difference between the function arm_mat_mult_q15() and this fast variant is that the fast variant use a 32-bit rather than a 64-bit accumulator. The result of each 1.15 x 1.15 multiplication is truncated to 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 format. Finally, the accumulator is saturated and converted to a 1.15 result.

+
The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 16 bits of each multiplication result. In order to avoid overflows completely the input signals must be scaled down. Scale down one of the input matrices by log2(numColsA) bits to avoid overflows, as a total of numColsA additions are computed internally for each output element.

+
See arm_mat_mult_q15() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. 

+
+
Definition at line 74 of file arm_mat_mult_fast_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___matrix_scale.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___matrix_scale.html
new file mode 100644
index 000000000..067dfb5a4
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___matrix_scale.html
@@ -0,0 +1,245 @@
+
+
+
+
+CMSIS DSP Software Library: Matrix Scale
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Matrix Scale

+
+[Matrix Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
arm_status arm_mat_scale_f32 (const arm_matrix_instance_f32 *pSrc, float32_t scale, arm_matrix_instance_f32 *pDst)
arm_status arm_mat_scale_q31 (const arm_matrix_instance_q31 *pSrc, q31_t scaleFract, int32_t shift, arm_matrix_instance_q31 *pDst)
arm_status arm_mat_scale_q15 (const arm_matrix_instance_q15 *pSrc, q15_t scaleFract, int32_t shift, arm_matrix_instance_q15 *pDst)

+
Detailed Description

+
Multiplies a matrix by a scalar. This is accomplished by multiplying each element in the matrix by the scalar. For example: 

+

+MatrixScale.gif
+
Matrix Scaling of a 3 x 3 matrix

+
The function checks to make sure that the input and output matrices are of the same size.

+
In the fixed-point Q15 and Q31 functions, scale is represented by a fractional multiplication scaleFract and an arithmetic shift shift. The shift allows the gain of the scaling operation to exceed 1.0. The overall scale factor applied to the fixed-point data is 

+
   
+     scale = scaleFract * 2^shift.   
+ 
 
Function Documentation

+
+

+

+      
+        
+          
+          
+          
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+          
+        
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+        
+        
+          
+          
+          
+        
+      
arm_status arm_mat_scale_f32 (const arm_matrix_instance_f32 *  pSrc, 
float32_t  scale, 
arm_matrix_instance_f32 *  pDst 
)

+

+

+
+
Floating-point matrix scaling. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to input matrix structure 
[in]scalescale factor to be applied 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 

+
+
Definition at line 75 of file arm_mat_scale_f32.c.

+
+

+

+
+

+

+      
+        
+          
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+        
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+          
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+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_mat_scale_q31 (const arm_matrix_instance_q31 *  pSrc, 
q31_t  scaleFract, 
int32_t  shift, 
arm_matrix_instance_q31 *  pDst 
)

+

+

+
+
Q31 matrix scaling. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to input matrix 
[in]scaleFractfractional portion of the scale factor 
[in]shiftnumber of bits to shift the result by 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior: 

+
The input data *pSrc and scaleFract are in 1.31 format. These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format. 

+
+
Definition at line 63 of file arm_mat_scale_q31.c.

+
+

+

+
+

+

+      
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+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_mat_scale_q15 (const arm_matrix_instance_q15 *  pSrc, 
q15_t  scaleFract, 
int32_t  shift, 
arm_matrix_instance_q15 *  pDst 
)

+

+

+
+
Q15 matrix scaling. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to input matrix 
[in]scaleFractfractional portion of the scale factor 
[in]shiftnumber of bits to shift the result by 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior: 

+
The input data *pSrc and scaleFract are in 1.15 format. These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format. 

+
+
Definition at line 63 of file arm_mat_scale_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___matrix_sub.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___matrix_sub.html
new file mode 100644
index 000000000..60f826cfa
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___matrix_sub.html
@@ -0,0 +1,228 @@
+
+
+
+
+CMSIS DSP Software Library: Matrix Subtraction
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Matrix Subtraction

+
+[Matrix Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
arm_status arm_mat_sub_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
arm_status arm_mat_sub_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
arm_status arm_mat_sub_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst)

+
Detailed Description

+
Subtract two matrices. 

+

+MatrixSubtraction.gif
+
Subraction of two 3 x 3 matrices

+
The functions check to make sure that pSrcA, pSrcB, and pDst have the same number of rows and columns. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+          
+        
+        
+          
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+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_mat_sub_f32 (const arm_matrix_instance_f32 *  pSrcA, 
const arm_matrix_instance_f32 *  pSrcB, 
arm_matrix_instance_f32 *  pDst 
)

+

+

+
+
Floating-point matrix subtraction. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 

+
+
Definition at line 67 of file arm_mat_sub_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
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+          
+        
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+        
+          
+          
+          
+        
+      
arm_status arm_mat_sub_q31 (const arm_matrix_instance_q31 *  pSrcA, 
const arm_matrix_instance_q31 *  pSrcB, 
arm_matrix_instance_q31 *  pDst 
)

+

+

+
+
Q31 matrix subtraction. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. 

+
+
Definition at line 62 of file arm_mat_sub_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
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+        
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+        
+          
+          
+          
+        
+      
arm_status arm_mat_sub_q15 (const arm_matrix_instance_q15 *  pSrcA, 
const arm_matrix_instance_q15 *  pSrcB, 
arm_matrix_instance_q15 *  pDst 
)

+

+

+
+
Q15 matrix subtraction. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 

+
+
Definition at line 61 of file arm_mat_sub_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___matrix_trans.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___matrix_trans.html
new file mode 100644
index 000000000..cd505b02f
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___matrix_trans.html
@@ -0,0 +1,203 @@
+
+
+
+
+CMSIS DSP Software Library: Matrix Transpose
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Matrix Transpose

+
+[Matrix Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
arm_status arm_mat_trans_f32 (const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst)
arm_status arm_mat_trans_q31 (const arm_matrix_instance_q31 *pSrc, arm_matrix_instance_q31 *pDst)
arm_status arm_mat_trans_q15 (const arm_matrix_instance_q15 *pSrc, arm_matrix_instance_q15 *pDst)

+
Detailed Description

+
Tranposes a matrix. Transposing an M x N matrix flips it around the center diagonal and results in an N x M matrix. 

+

+MatrixTranspose.gif
+
Transpose of a 3 x 3 matrix

+ 
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+          
+        
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+        
+      
arm_status arm_mat_trans_f32 (const arm_matrix_instance_f32 *  pSrc, 
arm_matrix_instance_f32 *  pDst 
)

+

+

+
+
Floating-point matrix transpose. 

+
Parameters:

+  
+    
+    
+  
[in]*pSrcpoints to the input matrix 
[out]*pDstpoints to the output matrix 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 

+
Examples: 
arm_matrix_example_f32.c.

+

+
Definition at line 64 of file arm_mat_trans_f32.c.

+
+

+

+
+

+

+      
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+      
arm_status arm_mat_trans_q31 (const arm_matrix_instance_q31 *  pSrc, 
arm_matrix_instance_q31 *  pDst 
)

+

+

+
+
Q31 matrix transpose. 

+
Parameters:

+  
+    
+    
+  
[in]*pSrcpoints to the input matrix 
[out]*pDstpoints to the output matrix 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 

+
+
Definition at line 55 of file arm_mat_trans_q31.c.

+
+

+

+
+

+

+      
+        
+          
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+        
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+          
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+        
+      
arm_status arm_mat_trans_q15 (const arm_matrix_instance_q15 *  pSrc, 
arm_matrix_instance_q15 *  pDst 
)

+

+

+
+
Q15 matrix transpose. 

+
Parameters:

+  
+    
+    
+  
[in]*pSrcpoints to the input matrix 
[out]*pDstpoints to the output matrix 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 

+
+
Definition at line 55 of file arm_mat_trans_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___max.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___max.html
new file mode 100644
index 000000000..4596fccd3
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___max.html
@@ -0,0 +1,296 @@
+
+
+
+
+CMSIS DSP Software Library: Maximum
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Maximum

+
+[Statistics Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_max_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex)
void arm_max_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex)
void arm_max_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex)
void arm_max_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex)

+
Detailed Description

+
Computes the maximum value of an array of data. The function returns both the maximum value and its position within the array. There are separate functions for floating-point, Q31, Q15, and Q7 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
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+        
+      
void arm_max_f32 (float32_t *  pSrc, 
uint32_t  blockSize, 
float32_t *  pResult, 
uint32_t *  pIndex 
)

+

+

+
+
Maximum value of a floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmaximum value returned here 
[out]*pIndexindex of maximum value returned here 

+  

+

+
Returns:
none. 

+
Examples: 
arm_class_marks_example_f32.c, and arm_fft_bin_example_f32.c.

+

+
Definition at line 59 of file arm_max_f32.c.

+
+

+

+
+

+

+      
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+          
+          
+        
+      
void arm_max_q31 (q31_t *  pSrc, 
uint32_t  blockSize, 
q31_t *  pResult, 
uint32_t *  pIndex 
)

+

+

+
+
Maximum value of a Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmaximum value returned here 
[out]*pIndexindex of maximum value returned here 

+  

+

+
Returns:
none. 

+
+
Definition at line 51 of file arm_max_q31.c.

+
+

+

+
+

+

+      
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+          
+          
+        
+      
void arm_max_q15 (q15_t *  pSrc, 
uint32_t  blockSize, 
q15_t *  pResult, 
uint32_t *  pIndex 
)

+

+

+
+
Maximum value of a Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmaximum value returned here 
[out]*pIndexindex of maximum value returned here 

+  

+

+
Returns:
none. 

+
+
Definition at line 51 of file arm_max_q15.c.

+
+

+

+
+

+

+      
+        
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+          
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+          
+          
+          
+        
+      
void arm_max_q7 (q7_t *  pSrc, 
uint32_t  blockSize, 
q7_t *  pResult, 
uint32_t *  pIndex 
)

+

+

+
+
Maximum value of a Q7 vector. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmaximum value returned here 
[out]*pIndexindex of maximum value returned here 

+  

+

+
Returns:
none. 

+
+
Definition at line 51 of file arm_max_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___min.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___min.html
new file mode 100644
index 000000000..93ca0138e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___min.html
@@ -0,0 +1,296 @@
+
+
+
+
+CMSIS DSP Software Library: Minimum
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Minimum

+
+[Statistics Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_min_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex)
void arm_min_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex)
void arm_min_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex)
void arm_min_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex)

+
Detailed Description

+
Computes the minimum value of an array of data. The function returns both the minimum value and its position within the array. There are separate functions for floating-point, Q31, Q15, and Q7 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
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+        
+      
void arm_min_f32 (float32_t *  pSrc, 
uint32_t  blockSize, 
float32_t *  pResult, 
uint32_t *  pIndex 
)

+

+

+
+
Minimum value of a floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultminimum value returned here 
[out]*pIndexindex of minimum value returned here 

+  

+

+
Returns:
none. 

+
Examples: 
arm_class_marks_example_f32.c, and arm_signal_converge_example_f32.c.

+

+
Definition at line 60 of file arm_min_f32.c.

+
+

+

+
+

+

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+      
void arm_min_q31 (q31_t *  pSrc, 
uint32_t  blockSize, 
q31_t *  pResult, 
uint32_t *  pIndex 
)

+

+

+
+
Minimum value of a Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultminimum value returned here 
[out]*pIndexindex of minimum value returned here 

+  

+

+
Returns:
none. 

+
+
Definition at line 53 of file arm_min_q31.c.

+
+

+

+
+

+

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void arm_min_q15 (q15_t *  pSrc, 
uint32_t  blockSize, 
q15_t *  pResult, 
uint32_t *  pIndex 
)

+

+

+
+
Minimum value of a Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultminimum value returned here 
[out]*pIndexindex of minimum value returned here 

+  

+

+
Returns:
none. 

+
+
Definition at line 53 of file arm_min_q15.c.

+
+

+

+
+

+

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+        
+      
void arm_min_q7 (q7_t *  pSrc, 
uint32_t  blockSize, 
q7_t *  pResult, 
uint32_t *  pIndex 
)

+

+

+
+
Minimum value of a Q7 vector. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultminimum value returned here 
[out]*pIndexindex of minimum value returned here 

+  

+

+
Returns:
none. 

+
+
Definition at line 52 of file arm_min_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___p_i_d.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___p_i_d.html
new file mode 100644
index 000000000..209e2e1f0
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___p_i_d.html
@@ -0,0 +1,443 @@
+
+
+
+
+CMSIS DSP Software Library: PID Motor Control
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
PID Motor Control

+
+[Controller Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_pid_reset_f32 (arm_pid_instance_f32 *S)
void arm_pid_init_f32 (arm_pid_instance_f32 *S, int32_t resetStateFlag)
void arm_pid_reset_q31 (arm_pid_instance_q31 *S)
void arm_pid_init_q31 (arm_pid_instance_q31 *S, int32_t resetStateFlag)
void arm_pid_reset_q15 (arm_pid_instance_q15 *S)
void arm_pid_init_q15 (arm_pid_instance_q15 *S, int32_t resetStateFlag)
static __INLINE float32_t arm_pid_f32 (arm_pid_instance_f32 *S, float32_t in)
static __INLINE q31_t arm_pid_q31 (arm_pid_instance_q31 *S, q31_t in)
static __INLINE q15_t arm_pid_q15 (arm_pid_instance_q15 *S, q15_t in)

+
Detailed Description

+
A Proportional Integral Derivative (PID) controller is a generic feedback control loop mechanism widely used in industrial control systems. A PID controller is the most commonly used type of feedback controller.

+
This set of functions implements (PID) controllers for Q15, Q31, and floating-point data types. The functions operate on a single sample of data and each call to the function returns a single processed value. S points to an instance of the PID control data structure. in is the input sample value. The functions return the output value.

+
Algorithm:
+    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+    A0 = Kp + Ki + Kd
+    A1 = (-Kp ) - (2 * Kd )
+    A2 = Kd  

+
where Kp is proportional constant, Ki is Integral constant and Kd is Derivative constant

+

+PID.gif
+
Proportional Integral Derivative Controller

+

+
The PID controller calculates an "error" value as the difference between the measured output and the reference input. The controller attempts to minimize the error by adjusting the process control inputs. The proportional value determines the reaction to the current error, the integral value determines the reaction based on the sum of recent errors, and the derivative value determines the reaction based on the rate at which the error has been changing.

+
Instance Structure 
The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. A separate instance structure must be defined for each PID Controller. There are separate instance structure declarations for each of the 3 supported data types.

+
Reset Functions 
There is also an associated reset function for each data type which clears the state array.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+

+

+
Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the PID Controller functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void arm_pid_reset_f32 (arm_pid_instance_f32 *  S )

+

+

+
+
Reset function for the floating-point PID Control. 

+
Parameters:

+  
+    
+  
[in]*SInstance pointer of PID control data structure. 

+  

+

+
Returns:
none. 

+
Description: 
The function resets the state buffer to zeros. 

+
+
Definition at line 44 of file arm_pid_reset_f32.c.

+
+

+

+
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void arm_pid_init_f32 (arm_pid_instance_f32 *  S, 
int32_t  resetStateFlag 
)

+

+

+
+
Initialization function for the floating-point PID Control. 

+
Parameters:

+  
+    
+    
+  
[in,out]*Spoints to an instance of the PID structure. 
[in]resetStateFlagflag to reset the state. 0 = no change in state & 1 = reset the state. 

+  

+

+
Returns:
none. 

+
Description: 

+
The resetStateFlag specifies whether to set state to zero or not. 

+ The function computes the structure fields: A0, A1 A2 using the proportional gain( Kp), integral gain( Ki) and derivative gain( Kd) also sets the state variables to all zeros. 

+
+
Definition at line 51 of file arm_pid_init_f32.c.

+
+

+

+
+

+

+      
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void arm_pid_reset_q31 (arm_pid_instance_q31 *  S )

+

+

+
+
Reset function for the Q31 PID Control. 

+
Parameters:

+  
+    
+  
[in]*SInstance pointer of PID control data structure. 

+  

+

+
Returns:
none. 

+
Description: 
The function resets the state buffer to zeros. 

+
+
Definition at line 44 of file arm_pid_reset_q31.c.

+
+

+

+
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void arm_pid_init_q31 (arm_pid_instance_q31 *  S, 
int32_t  resetStateFlag 
)

+

+

+
+
Initialization function for the Q31 PID Control. 

+
Parameters:

+  
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 PID structure. 
[in]resetStateFlagflag to reset the state. 0 = no change in state 1 = reset the state. 

+  

+

+
Returns:
none. 

+
Description: 

+
The resetStateFlag specifies whether to set state to zero or not. 

+ The function computes the structure fields: A0, A1 A2 using the proportional gain( Kp), integral gain( Ki) and derivative gain( Kd) also sets the state variables to all zeros. 

+
+
Definition at line 50 of file arm_pid_init_q31.c.

+
+

+

+
+

+

+      
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+          
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+      
void arm_pid_reset_q15 (arm_pid_instance_q15 *  S )

+

+

+
+
Reset function for the Q15 PID Control. 

+
Parameters:

+  
+    
+  
[in]*SInstance pointer of PID control data structure. 

+  

+

+
Returns:
none. 

+
Description: 
The function resets the state buffer to zeros. 

+
+
Definition at line 44 of file arm_pid_reset_q15.c.

+
+

+

+
+

+

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void arm_pid_init_q15 (arm_pid_instance_q15 *  S, 
int32_t  resetStateFlag 
)

+

+

+
+
Initialization function for the Q15 PID Control. 

+
Parameters:

+  
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 PID structure. 
[in]resetStateFlagflag to reset the state. 0 = no change in state 1 = reset the state. 

+  

+

+
Returns:
none. 

+
Description: 

+
The resetStateFlag specifies whether to set state to zero or not. 

+ The function computes the structure fields: A0, A1 A2 using the proportional gain( Kp), integral gain( Ki) and derivative gain( Kd) also sets the state variables to all zeros. 

+
+
Definition at line 50 of file arm_pid_init_q15.c.

+
+

+

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static __INLINE float32_t arm_pid_f32 (arm_pid_instance_f32 *  S, 
float32_t  in 
) [static]

+

+

+
+
Process function for the floating-point PID Control. 

+
Parameters:

+  
+    
+    
+  
[in,out]*Sis an instance of the floating-point PID Control structure 
[in]ininput sample to process 

+  

+

+
Returns:
out processed output sample. 

+
+
Definition at line 4711 of file arm_math.h.

+
+

+

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+

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static __INLINE q31_t arm_pid_q31 (arm_pid_instance_q31 *  S, 
q31_t  in 
) [static]

+

+

+
+
Process function for the Q31 PID Control. 

+
Parameters:

+  
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 PID Control structure 
[in]ininput sample to process 

+  

+

+
Returns:
out processed output sample.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. 

+
+
Definition at line 4746 of file arm_math.h.

+
+

+

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static __INLINE q15_t arm_pid_q15 (arm_pid_instance_q15 *  S, 
q15_t  in 
) [static]

+

+

+
+
Process function for the Q15 PID Control. 

+
Parameters:

+  
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 PID Control structure 
[in]ininput sample to process 

+  

+

+
Returns:
out processed output sample.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 64-bit internal accumulator. Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format. 

+
+
Definition at line 4794 of file arm_math.h.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___partial_conv.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___partial_conv.html
new file mode 100644
index 000000000..e52879685
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___partial_conv.html
@@ -0,0 +1,535 @@
+
+
+
+
+CMSIS DSP Software Library: Partial Convolution
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Partial Convolution

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+

+Functions
arm_status arm_conv_partial_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst, uint32_t firstIndex, uint32_t numPoints)
arm_status arm_conv_partial_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints)
arm_status arm_conv_partial_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints)
arm_status arm_conv_partial_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints)
arm_status arm_conv_partial_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints)
arm_status arm_conv_partial_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, uint32_t firstIndex, uint32_t numPoints)

+
Detailed Description

+
Partial Convolution is equivalent to Convolution except that a subset of the output samples is generated. Each function has two additional arguments. firstIndex specifies the starting index of the subset of output samples. numPoints is the number of output samples to compute. The function computes the output in the range [firstIndex, ..., firstIndex+numPoints-1]. The output array pDst contains numPoints values.

+
The allowable range of output indices is [0 srcALen+srcBLen-2]. If the requested subset does not fall in this range then the functions return ARM_MATH_ARGUMENT_ERROR. Otherwise the functions return ARM_MATH_SUCCESS. 

+
Note:
Refer arm_conv_f32() for details on fixed point behavior. 

+
Function Documentation

+
+

+

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arm_status arm_conv_partial_f32 (float32_t *  pSrcA, 
uint32_t  srcALen, 
float32_t *  pSrcB, 
uint32_t  srcBLen, 
float32_t *  pDst, 
uint32_t  firstIndex, 
uint32_t  numPoints 
)

+

+

+
+
Partial convolution of floating-point sequences. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 

+  

+

+
Returns:
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. 

+
+
Definition at line 74 of file arm_conv_partial_f32.c.

+
+

+

+
+

+

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+      
arm_status arm_conv_partial_q31 (q31_t *  pSrcA, 
uint32_t  srcALen, 
q31_t *  pSrcB, 
uint32_t  srcBLen, 
q31_t *  pDst, 
uint32_t  firstIndex, 
uint32_t  numPoints 
)

+

+

+
+
Partial convolution of Q31 sequences. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 

+  

+

+
Returns:
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

+
See arm_conv_partial_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4. 

+
+
Definition at line 59 of file arm_conv_partial_q31.c.

+
+

+

+
+

+

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+      
arm_status arm_conv_partial_fast_q31 (q31_t *  pSrcA, 
uint32_t  srcALen, 
q31_t *  pSrcB, 
uint32_t  srcBLen, 
q31_t *  pDst, 
uint32_t  firstIndex, 
uint32_t  numPoints 
)

+

+

+
+
Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 

+  

+

+
Returns:
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

+
See arm_conv_partial_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. 

+
+
Definition at line 56 of file arm_conv_partial_fast_q31.c.

+
+

+

+
+

+

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arm_status arm_conv_partial_q15 (q15_t *  pSrcA, 
uint32_t  srcALen, 
q15_t *  pSrcB, 
uint32_t  srcBLen, 
q15_t *  pDst, 
uint32_t  firstIndex, 
uint32_t  numPoints 
)

+

+

+
+
Partial convolution of Q15 sequences. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 

+  

+

+
Returns:
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

+
Refer to arm_conv_partial_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4. 

+
+
Definition at line 60 of file arm_conv_partial_q15.c.

+
+

+

+
+

+

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arm_status arm_conv_partial_fast_q15 (q15_t *  pSrcA, 
uint32_t  srcALen, 
q15_t *  pSrcB, 
uint32_t  srcBLen, 
q15_t *  pDst, 
uint32_t  firstIndex, 
uint32_t  numPoints 
)

+

+

+
+
Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 

+  

+

+
Returns:
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

+
See arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. 

+
+
Definition at line 56 of file arm_conv_partial_fast_q15.c.

+
+

+

+
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arm_status arm_conv_partial_q7 (q7_t *  pSrcA, 
uint32_t  srcALen, 
q7_t *  pSrcB, 
uint32_t  srcBLen, 
q7_t *  pDst, 
uint32_t  firstIndex, 
uint32_t  numPoints 
)

+

+

+
+
Partial convolution of Q7 sequences. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 

+  

+

+
Returns:
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. 

+
+
Definition at line 58 of file arm_conv_partial_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___r_f_f_t___r_i_f_f_t.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___r_f_f_t___r_i_f_f_t.html
new file mode 100644
index 000000000..6ab41e5bf
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___r_f_f_t___r_i_f_f_t.html
@@ -0,0 +1,611 @@
+
+
+
+
+CMSIS DSP Software Library: Real FFT Functions
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
Real FFT Functions

+
+[Transform Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Functions
arm_status arm_rfft_init_f32 (arm_rfft_instance_f32 *S, arm_cfft_radix4_instance_f32 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
void arm_rfft_f32 (const arm_rfft_instance_f32 *S, float32_t *pSrc, float32_t *pDst)
arm_status arm_rfft_init_q31 (arm_rfft_instance_q31 *S, arm_cfft_radix4_instance_q31 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
void arm_rfft_q31 (const arm_rfft_instance_q31 *S, q31_t *pSrc, q31_t *pDst)
arm_status arm_rfft_init_q15 (arm_rfft_instance_q15 *S, arm_cfft_radix4_instance_q15 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
void arm_rfft_q15 (const arm_rfft_instance_q15 *S, q15_t *pSrc, q15_t *pDst)

+Variables
static const float32_t realCoefA [2048]
static const float32_t realCoefB [2048]
const q31_t realCoefAQ31 [1024]
const q31_t realCoefBQ31 [1024]
static const q15_t realCoefAQ15 [2048]
static const q15_t realCoefBQ15 [2048]

+
Detailed Description

+
Complex FFT/IFFT typically assumes complex input and output. However many applications use real valued data in time domain. Real FFT/IFFT efficiently process real valued sequences with the advantage of requirement of low memory and with less complexity.

+
This set of functions implements Real Fast Fourier Transforms(RFFT) and Real Inverse Fast Fourier Transform(RIFFT) for Q15, Q31, and floating-point data types.

+
Algorithm: 

+
Real Fast Fourier Transform: 

+
Real FFT of N-point is calculated using CFFT of N/2-point and Split RFFT process as shown below figure. 

+

+RFFT.gif
+
Real Fast Fourier Transform

+ 

+
The RFFT functions operate on blocks of input and output data and each call to the function processes fftLenR samples through the transform. pSrc points to input array containing fftLenR values. pDst points to output array containing 2*fftLenR values. 

+ Input for real FFT is in the order of 
{real[0], real[1], real[2], real[3], ..}
 Output for real FFT is complex and are in the order of 
{real(0), imag(0), real(1), imag(1), ...}

+
Real Inverse Fast Fourier Transform: 

+
Real IFFT of N-point is calculated using Split RIFFT process and CFFT of N/2-point as shown below figure. 

+

+RIFFT.gif
+
Real Inverse Fast Fourier Transform

+ 

+
The RIFFT functions operate on blocks of input and output data and each call to the function processes 2*fftLenR samples through the transform. pSrc points to input array containing 2*fftLenR values. pDst points to output array containing fftLenR values. 

+ Input for real IFFT is complex and are in the order of 
{real(0), imag(0), real(1), imag(1), ...}
 Output for real IFFT is real and in the order of 
{real[0], real[1], real[2], real[3], ..}

+
Lengths supported by the transform: 

+
Real FFT/IFFT supports the lengths [128, 512, 2048], as it internally uses CFFT/CIFFT.

+
Instance Structure 
A separate instance structure must be defined for each Instance but the twiddle factors can be reused. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Initializes twiddle factor tables.
    • 
+
  • Initializes CFFT data structure fields. 
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Manually initialize the instance structure as follows: 
   
+arm_rfft_instance_f32 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};   
+arm_rfft_instance_q31 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};   
+arm_rfft_instance_q15 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};   
+ 
 where fftLenReal length of RFFT/RIFFT; fftLenBy2 length of CFFT/CIFFT. ifftFlagR Flag for selection of RFFT or RIFFT(Set ifftFlagR to calculate RIFFT otherwise calculates RFFT); bitReverseFlagR Flag for selection of output order(Set bitReverseFlagR to output in normal order otherwise output in bit reversed order); twidCoefRModifier modifier for twiddle factor table which supports 128, 512, 2048 RFFT lengths with same table; pTwiddleARealpoints to A array of twiddle coefficients; pTwiddleBRealpoints to B array of twiddle coefficients; pCfft points to the CFFT Instance structure. The CFFT structure also needs to be initialized, refer to arm_cfft_radix4_f32() for details regarding static initialization of cfft structure.

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the RFFT/RIFFT function. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

+      
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arm_status arm_rfft_init_f32 (arm_rfft_instance_f32 *  S, 
arm_cfft_radix4_instance_f32 *  S_CFFT, 
uint32_t  fftLenReal, 
uint32_t  ifftFlagR, 
uint32_t  bitReverseFlag 
)

+

+

+
+
Initialization function for the floating-point RFFT/RIFFT. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point RFFT/RIFFT structure. 
[in,out]*S_CFFTpoints to an instance of the floating-point CFFT/CIFFT structure. 
[in]fftLenReallength of the FFT. 
[in]ifftFlagRflag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.

+
Description: 

+
The parameter fftLenReal Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048. 

+
The parameter ifftFlagR controls whether a forward or inverse transform is computed. Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. 

+
The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 

+
This function also initializes Twiddle factor table. 

+
+
Definition at line 1638 of file arm_rfft_init_f32.c.

+
+

+

+
+

+

+      
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+      
void arm_rfft_f32 (const arm_rfft_instance_f32 *  S, 
float32_t *  pSrc, 
float32_t *  pDst 
)

+

+

+
+
Processing function for the floating-point RFFT/RIFFT. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point RFFT/RIFFT structure. 
[in]*pSrcpoints to the input buffer. 
[out]*pDstpoints to the output buffer. 

+  

+

+
Returns:
none. 

+
+
Definition at line 150 of file arm_rfft_f32.c.

+
+

+

+
+

+

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+      
arm_status arm_rfft_init_q31 (arm_rfft_instance_q31 *  S, 
arm_cfft_radix4_instance_q31 *  S_CFFT, 
uint32_t  fftLenReal, 
uint32_t  ifftFlagR, 
uint32_t  bitReverseFlag 
)

+

+

+
+
Initialization function for the Q31 RFFT/RIFFT. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 RFFT/RIFFT structure. 
[in,out]*S_CFFTpoints to an instance of the Q31 CFFT/CIFFT structure. 
[in]fftLenReallength of the FFT. 
[in]ifftFlagRflag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.

+
Description: 

+
The parameter fftLenReal Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048. 

+
The parameter ifftFlagR controls whether a forward or inverse transform is computed. Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. 

+
The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 

+
This function also initializes Twiddle factor table. 

+
+
Definition at line 617 of file arm_rfft_init_q31.c.

+
+

+

+
+

+

+      
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+          
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+        
+      
void arm_rfft_q31 (const arm_rfft_instance_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pDst 
)

+

+

+
+
Processing function for the Q31 RFFT/RIFFT. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 RFFT/RIFFT structure. 
[in]*pSrcpoints to the input buffer. 
[out]*pDstpoints to the output buffer. 

+  

+

+
Returns:
none.

+
Input an output formats: 

+
Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. Hence the output format is different for different RFFT sizes. The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT: 

+

+RFFTQ31.gif
+
Input and Output Formats for Q31 RFFT

+

+

+RIFFTQ31.gif
+
Input and Output Formats for Q31 RIFFT

+ 

+
+
Definition at line 80 of file arm_rfft_q31.c.

+
+

+

+
+

+

+      
+        
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+          
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+          
+          
+          
+        
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+          
+          
+          
+        
+      
arm_status arm_rfft_init_q15 (arm_rfft_instance_q15 *  S, 
arm_cfft_radix4_instance_q15 *  S_CFFT, 
uint32_t  fftLenReal, 
uint32_t  ifftFlagR, 
uint32_t  bitReverseFlag 
)

+

+

+
+
Initialization function for the Q15 RFFT/RIFFT. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 RFFT/RIFFT structure. 
[in]*S_CFFTpoints to an instance of the Q15 CFFT/CIFFT structure. 
[in]fftLenReallength of the FFT. 
[in]ifftFlagRflag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.

+
Description: 

+
The parameter fftLenReal Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048. 

+
The parameter ifftFlagR controls whether a forward or inverse transform is computed. Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. 

+
The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 

+
This function also initializes Twiddle factor table. 

+
+
Definition at line 620 of file arm_rfft_init_q15.c.

+
+

+

+
+

+

+      
+        
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+          
+        
+      
void arm_rfft_q15 (const arm_rfft_instance_q15 *  S, 
q15_t *  pSrc, 
q15_t *  pDst 
)

+

+

+
+
Processing function for the Q15 RFFT/RIFFT. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 RFFT/RIFFT structure. 
[in]*pSrcpoints to the input buffer. 
[out]*pDstpoints to the output buffer. 

+  

+

+
Returns:
none.

+
Input an output formats: 

+
Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. Hence the output format is different for different RFFT sizes. The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT: 

+

+RFFTQ15.gif
+
Input and Output Formats for Q15 RFFT

+ 

+

+RIFFTQ15.gif
+
Input and Output Formats for Q15 RIFFT

+ 

+
+
Definition at line 80 of file arm_rfft_q15.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float32_t realCoefA[2048] [static]

+

+

+
Generation of realCoefA array: 

+
n = 1024 
for (i = 0; i < n; i++)   
+  {   
+    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));   
+    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+  } 
 

+
+
Definition at line 59 of file arm_rfft_init_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t realCoefB[2048] [static]

+

+

+
Generation of realCoefB array: 

+
n = 1024 
for (i = 0; i < n; i++)   
+ {   
+    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));   
+    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+  } 
 

+
+
Definition at line 843 of file arm_rfft_init_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t realCoefAQ31[1024]

+

+

+
Generation floating point realCoefAQ31 array: 

+
n = 1024 
for (i = 0; i < n; i++)   
+ {   
+    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));   
+    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+ }
 

+
Convert to fixed point Q31 format round(pATable[i] * pow(2, 31)) 

+
+
Definition at line 60 of file arm_rfft_init_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t realCoefBQ31[1024]

+

+

+
Generation of realCoefBQ31 array: 

+
n = 512 
for (i = 0; i < n; i++)   
+ {   
+    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));   
+    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+ } 
 

+
Convert to fixed point Q31 format round(pBTable[i] * pow(2, 31)) 

+
+
Definition at line 336 of file arm_rfft_init_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t realCoefAQ15[2048] [static]

+

+

+
Generation floating point real_CoefA array: 

+
n = 1024 
for (i = 0; i < n; i++)   
+  {   
+    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));   
+    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+  } 
 

+
Convert to fixed point Q15 format round(pATable[i] * pow(2, 15)) 

+
+
Definition at line 63 of file arm_rfft_init_q15.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t realCoefBQ15[2048] [static]

+

+

+
Generation of real_CoefB array: 

+
n = 1024 
for (i = 0; i < n; i++)   
+  {   
+    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));   
+    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+  } 
 

+
Convert to fixed point Q15 format round(pBTable[i] * pow(2, 15)) 

+
+
Definition at line 339 of file arm_rfft_init_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___r_m_s.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___r_m_s.html
new file mode 100644
index 000000000..6597a3c87
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___r_m_s.html
@@ -0,0 +1,227 @@
+
+
+
+
+CMSIS DSP Software Library: Root mean square (RMS)
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Root mean square (RMS)

+
+[Statistics Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_rms_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
void arm_rms_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
void arm_rms_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)

+
Detailed Description

+
Calculates the Root Mean Sqaure of the elements in the input vector. The underlying algorithm is used:

+
   
+ 	Result = sqrt(((pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]) / blockSize));   
+ 
There are separate functions for floating point, Q31, and Q15 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_rms_f32 (float32_t *  pSrc, 
uint32_t  blockSize, 
float32_t *  pResult 
)

+

+

+
+
Root Mean Square of the elements of a floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultrms value returned here 

+  

+

+
Returns:
none. 

+
+
Definition at line 65 of file arm_rms_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+          
+        
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+          
+          
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+          
+        
+        
+          
+          
+          
+        
+      
void arm_rms_q31 (q31_t *  pSrc, 
uint32_t  blockSize, 
q31_t *  pResult 
)

+

+

+
+
Root Mean Square of the elements of a Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultrms value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using an internal 64-bit accumulator. The input is represented in 1.31 format, and intermediate multiplication yields a 2.62 format. The accumulator maintains full precision of the intermediate multiplication results, but provides only a single guard bit. There is no saturation on intermediate additions. If the accumulator overflows, it wraps around and distorts the result. In order to avoid overflows completely, the input signal must be scaled down by log2(blockSize) bits, as a total of blockSize additions are performed internally. Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value. 

+
+
Definition at line 62 of file arm_rms_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_rms_q15 (q15_t *  pSrc, 
uint32_t  blockSize, 
q15_t *  pResult 
)

+

+

+
+
Root Mean Square of the elements of a Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultrms value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 64-bit internal accumulator. The input is represented in 1.15 format. Intermediate multiplication yields a 2.30 format, and this result is added without saturation to a 64-bit accumulator in 34.30 format. With 33 guard bits in the accumulator, there is no risk of overflow, and the full precision of the intermediate multiplication is preserved. Finally, the 34.30 result is truncated to 34.15 format by discarding the lower 15 bits, and then saturated to yield a result in 1.15 format. 

+
+
Definition at line 59 of file arm_rms_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___s_q_r_t.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___s_q_r_t.html
new file mode 100644
index 000000000..5805eea24
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___s_q_r_t.html
@@ -0,0 +1,205 @@
+
+
+
+
+CMSIS DSP Software Library: Square Root
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Square Root

+
+[Fast Math Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
arm_status arm_sqrt_q31 (q31_t in, q31_t *pOut)
arm_status arm_sqrt_q15 (q15_t in, q15_t *pOut)
static __INLINE arm_status arm_sqrt_f32 (float32_t in, float32_t *pOut)

+
Detailed Description

+
Computes the square root of a number. There are separate functions for Q15, Q31, and floating-point data types. The square root function is computed using the Newton-Raphson algorithm. This is an iterative algorithm of the form: 

+
+      x1 = x0 - f(x0)/f'(x0)
+ 
 where x1 is the current estimate, x0 is the previous estimate and f'(x0) is the derivative of f() evaluated at x0. For the square root function, the algorithm reduces to: 

+
+     x0 = in/2                         [initial guess]
+     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+ 
 
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_sqrt_q31 (q31_t  in, 
q31_t *  pOut 
)

+

+

+
+
Q31 square root function. 

+
Parameters:

+  
+    
+    
+  
[in]ininput value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. 
[out]*pOutsquare root of input value. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if in is negative value and returns zero output for negative values. 

+
+
Definition at line 47 of file arm_sqrt_q31.c.

+
+

+

+
+

+

+      
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+          
+          
+          
+        
+        
+          
+          
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+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_sqrt_q15 (q15_t  in, 
q15_t *  pOut 
)

+

+

+
+
Q15 square root function. 

+
Parameters:

+  
+    
+    
+  
[in]ininput value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. 
[out]*pOutsquare root of input value. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if in is negative value and returns zero output for negative values. 

+
+
Definition at line 51 of file arm_sqrt_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
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+          
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+        
+        
+          
+          
+          
+        
+      
static __INLINE arm_status arm_sqrt_f32 (float32_t  in, 
float32_t *  pOut 
) [static]

+

+

+
+
Floating-point square root function. 

+
Parameters:

+  
+    
+    
+  
[in]ininput value. 
[out]*pOutsquare root of input value. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if in is negative value and returns zero output for negative values. 

+
+
Definition at line 5695 of file arm_math.h.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___s_t_d.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___s_t_d.html
new file mode 100644
index 000000000..9873206be
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___s_t_d.html
@@ -0,0 +1,228 @@
+
+
+
+
+CMSIS DSP Software Library: Standard deviation
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Standard deviation

+
+[Statistics Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_std_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
void arm_std_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
void arm_std_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)

+
Detailed Description

+
Calculates the standard deviation of the elements in the input vector. The underlying algorithm is used:

+
   
+ 	Result = sqrt((sumOfSquares - sum2 / blockSize) / (blockSize - 1))
	   where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]
	                   sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]  
+ 
There are separate functions for floating point, Q31, and Q15 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_std_f32 (float32_t *  pSrc, 
uint32_t  blockSize, 
float32_t *  pResult 
)

+

+

+
+
Standard deviation of the elements of a floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultstandard deviation value returned here 

+  

+

+
Returns:
none. 

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 69 of file arm_std_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+          
+        
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+          
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+        
+        
+          
+          
+          
+        
+      
void arm_std_q31 (q31_t *  pSrc, 
uint32_t  blockSize, 
q31_t *  pResult 
)

+

+

+
+
Standard deviation of the elements of a Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultstandard deviation value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using an internal 64-bit accumulator. The input is represented in 1.31 format, and intermediate multiplication yields a 2.62 format. The accumulator maintains full precision of the intermediate multiplication results, but provides only a single guard bit. There is no saturation on intermediate additions. If the accumulator overflows it wraps around and distorts the result. In order to avoid overflows completely the input signal must be scaled down by log2(blockSize) bits, as a total of blockSize additions are performed internally. Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value. 

+
+
Definition at line 66 of file arm_std_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_std_q15 (q15_t *  pSrc, 
uint32_t  blockSize, 
q15_t *  pResult 
)

+

+

+
+
Standard deviation of the elements of a Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultstandard deviation value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 64-bit internal accumulator. The input is represented in 1.15 format. Intermediate multiplication yields a 2.30 format, and this result is added without saturation to a 64-bit accumulator in 34.30 format. With 33 guard bits in the accumulator, there is no risk of overflow, and the full precision of the intermediate multiplication is preserved. Finally, the 34.30 result is truncated to 34.15 format by discarding the lower 15 bits, and then saturated to yield a result in 1.15 format. 

+
+
Definition at line 62 of file arm_std_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___signal_convergence.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___signal_convergence.html
new file mode 100644
index 000000000..11690e40c
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___signal_convergence.html
@@ -0,0 +1,107 @@
+
+
+
+
+CMSIS DSP Software Library: Signal Convergence Example
+
+
+
+
+
+
+
+
+
+

+  

+
Signal Convergence Example

+
+[Examples]
+
  

+

+

+
+

+
Description: 

+
Demonstrates the ability of an adaptive filter to "learn" the transfer function of a FIR lowpass filter using the Normalized LMS Filter, Finite Impulse Response (FIR) Filter, and Basic Math Functions.

+
Algorithm:

+
The figure below illustrates the signal flow in this example. Uniformly distributed white noise is passed through an FIR lowpass filter. The output of the FIR filter serves as the reference input of the adaptive filter (normalized LMS filter). The white noise is input to the adaptive filter. The adaptive filter learns the transfer function of the FIR filter. The filter outputs two signals: (1) the output of the internal adaptive FIR filter, and (2) the error signal which is the difference between the adaptive filter and the reference output of the FIR filter. Over time as the adaptive filter learns the transfer function of the FIR filter, the first output approaches the reference output of the FIR filter, and the error signal approaches zero. 

+
The adaptive filter converges properly even if the input signal has a large dynamic range (i.e., varies from small to large values). The coefficients of the adaptive filter are initially zero, and then converge over 1536 samples. The internal function test_signal_converge() implements the stopping condition. The function checks if all of the values of the error signal have a magnitude below a threshold DELTA.

+
Block Diagram:

+

+SignalFlow.gif
+

+

+
Variables Description:

+
    
+
  • testInput_f32 points to the input data 
    • 
+
  • firStateF32 points to FIR state buffer 
    • 
+
  • lmsStateF32 points to Normalised Least mean square FIR filter state buffer 
    • 
+
  • FIRCoeff_f32 points to coefficient buffer 
    • 
+
  • lmsNormCoeff_f32 points to Normalised Least mean square FIR filter coefficient buffer 
    • 
+
  • wire1, wir2, wire3 temporary buffers 
    • 
+
  • errOutput, err_signal temporary error buffers
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_signal_converge_example_f32.c 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___sin_cos.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___sin_cos.html
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--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___sin_cos.html
@@ -0,0 +1,268 @@
+
+
+
+
+CMSIS DSP Software Library: Sine Cosine
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
Sine Cosine

+
+[Controller Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+
+

+Functions
void arm_sin_cos_f32 (float32_t theta, float32_t *pSinVal, float32_t *pCosVal)
void arm_sin_cos_q31 (q31_t theta, q31_t *pSinVal, q31_t *pCosVal)

+Variables
static const float32_t cosTable [360]
static const float32_t sinTable [360]
static const int32_t sinTableQ31 [360]
static const int32_t cosTableQ31 [360]

+
Detailed Description

+
Computes the trigonometric sine and cosine values using a combination of table lookup and linear interpolation. There are separate functions for Q31 and floating-point data types. The input to the floating-point version is in degrees while the fixed-point Q31 have a scaled input with the range [-1 1) mapping to [-180 180) degrees.

+
The implementation is based on table lookup using 360 values together with linear interpolation. The steps used are:

+
    
+
  1. Calculation of the nearest integer table index.
    2. 
+
  2. Compute the fractional portion (fract) of the input.
    3. 
+
  3. Fetch the value corresponding to index from sine table to y0 and also value from index+1 to y1.
    4. 
+
  4. Sine value is computed as  *psinVal = y0 + (fract * (y1 - y0)).
    5. 
+
  5. Fetch the value corresponding to index from cosine table to y0 and also value from index+1 to y1.
    6. 
+
  6. Cosine value is computed as  *pcosVal = y0 + (fract * (y1 - y0)). 
    7. 
+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+          
+        
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+          
+          
+          
+        
+      
void arm_sin_cos_f32 (float32_t  theta, 
float32_t *  pSinVal, 
float32_t *  pCosVal 
)

+

+

+
+
Floating-point sin_cos function. 

+
Parameters:

+  
+    
+    
+    
+  
[in]thetainput value in degrees 
[out]*pSinValpoints to the processed sine output. 
[out]*pCosValpoints to the processed cos output. 

+  

+

+
Returns:
none. 

+
+
Definition at line 367 of file arm_sin_cos_f32.c.

+
+

+

+
+

+

+      
+        
+          
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+          
+          
+        
+      
void arm_sin_cos_q31 (q31_t  theta, 
q31_t *  pSinVal, 
q31_t *  pCosVal 
)

+

+

+
+
Q31 sin_cos function. 

+
Parameters:

+  
+    
+    
+    
+  
[in]thetascaled input value in degrees 
[out]*pSinValpoints to the processed sine output. 
[out]*pCosValpoints to the processed cosine output. 

+  

+

+
Returns:
none.

+
The Q31 input value is in the range [-1 +1) and is mapped to a degree value in the range [-180 180). 

+
+
Definition at line 264 of file arm_sin_cos_q31.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float32_t cosTable[360] [static]

+

+

+
Cosine Table is generated from following loop 
for(i = 0; i < 360; i++)   
+ {   
+    cosTable[i]= cos((i-180) * PI/180.0);   
+ } 
 

+
+
Definition at line 71 of file arm_sin_cos_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t sinTable[360] [static]

+

+

+
Sine Table is generated from following loop 
for(i = 0; i < 360; i++)   
+ {   
+    sinTable[i]= sin((i-180) * PI/180.0);   
+ } 
 

+
+
Definition at line 219 of file arm_sin_cos_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const int32_t sinTableQ31[360] [static]

+

+

+
Sine Table is generated from following loop 
for(i = 0; i < 360; i++)   
+ {   
+    sinTable[i]= sin((i-180) * PI/180.0);   
+ } 
 Convert above coefficients to fixed point 1.31 format. 

+
+
Definition at line 51 of file arm_sin_cos_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const int32_t cosTableQ31[360] [static]

+

+

+
Cosine Table is generated from following loop 
for(i = 0; i < 360; i++)   
+ {   
+    cosTable[i]= cos((i-180) * PI/180.0);   
+ } 
 

+
Convert above coefficients to fixed point 1.31 format. 

+
+
Definition at line 157 of file arm_sin_cos_q31.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___sin_cos_example.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___sin_cos_example.html
new file mode 100644
index 000000000..8772f3f3b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___sin_cos_example.html
@@ -0,0 +1,96 @@
+
+
+
+
+CMSIS DSP Software Library: SineCosine Example
+
+
+
+
+
+
+
+
+
+

+  

+
SineCosine Example

+
+[Examples]
+
  

+

+

+
+

+
Description:

+
Demonstrates the Pythagorean trignometric identity with the use of Cosine, Sine, Vector Multiplication, and Vector Addition functions.

+
Algorithm:

+
Mathematically, the Pythagorean trignometric identity is defined by the following equation: 
sin(x) * sin(x) + cos(x) * cos(x) = 1
 where x is the angle in radians.

+
Block Diagram:

+

+sinCos.gif
+

+

+
Variables Description:

+
    
+
  • testInput_f32 array of input angle in radians 
    • 
+
  • testOutput stores sum of the squares of sine and cosine values of input angle
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_sin_cos_example_f32.c 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___variance_example.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___variance_example.html
new file mode 100644
index 000000000..01d3675af
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group___variance_example.html
@@ -0,0 +1,101 @@
+
+
+
+
+CMSIS DSP Software Library: Variance Example
+
+
+
+
+
+
+
+
+
+

+  

+
Variance Example

+
+[Examples]
+
  

+

+

+
+

+
Description: 

+
Demonstrates the use of Basic Math and Support Functions to calculate the variance of an input sequence with N samples. Uniformly distributed white noise is taken as input.

+
Algorithm:

+
The variance of a sequence is the mean of the squared deviation of the sequence from its mean. 

+
This is denoted by the following equation: 
 variance = ((x[0] - x') * (x[0] - x') + (x[1] - x') * (x[1] - x') + ... + * (x[n-1] - x') * (x[n-1] - x')) / (N-1)
 where, x[n] is the input sequence, N is the number of input samples, and x' is the mean value of the input sequence, x[n]. 

+
The mean value x' is defined as: 
 x' = (x[0] + x[1] + ... + x[n-1]) / N

+
Block Diagram:

+

+Variance.gif
+

+

+
Variables Description:

+
    
+
  • testInput_f32 points to the input data 
    • 
+
  • wire1, wir2, wire3 temporary buffers 
    • 
+
  • blockSize number of samples processed at a time 
    • 
+
  • refVarianceOut reference variance value
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_variance_example_f32.c 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__clarke.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__clarke.html
new file mode 100644
index 000000000..b48719eff
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__clarke.html
@@ -0,0 +1,199 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Clarke Transform
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Clarke Transform

+
+[Controller Functions]
+
  

+

+

+
+
+
+
+

+Functions
static __INLINE void arm_clarke_f32 (float32_t Ia, float32_t Ib, float32_t *pIalpha, float32_t *pIbeta)
static __INLINE void arm_clarke_q31 (q31_t Ia, q31_t Ib, q31_t *pIalpha, q31_t *pIbeta)

+
Detailed Description

+
Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents in the two-phase orthogonal stator axis Ialpha and Ibeta. When Ialpha is superposed with Ia as shown in the figure below 

+

+clarke.gif
+
Stator current space vector and its components in (a,b).

+
 and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta can be calculated using only Ia and Ib.

+
The function operates on a single sample of data and each call to the function returns the processed output. The library provides separate functions for Q31 and floating-point data types. 

+
Algorithm

+clarkeFormula.gif
+

+ where Ia and Ib are the instantaneous stator phases and pIalpha and pIbeta are the two coordinates of time invariant vector. 

+
Fixed-Point Behavior
Care must be taken when using the Q31 version of the Clarke transform. In particular, the overflow and saturation behavior of the accumulator used must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
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+        
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+          
+          
+        
+      
static __INLINE void arm_clarke_f32 (float32_t  Ia, 
float32_t  Ib, 
float32_t *  pIalpha, 
float32_t *  pIbeta 
) [static]

+

+

+
+
Floating-point Clarke transform. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]Iainput three-phase coordinate a 
[in]Ibinput three-phase coordinate b 
[out]*pIalphapoints to output two-phase orthogonal vector axis alpha 
[out]*pIbetapoints to output two-phase orthogonal vector axis beta 

+  

+

+
Returns:
none. 

+
+
Definition at line 4905 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+          
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+          
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+          
+        
+        
+          
+          
+          
+        
+      
static __INLINE void arm_clarke_q31 (q31_t  Ia, 
q31_t  Ib, 
q31_t *  pIalpha, 
q31_t *  pIbeta 
) [static]

+

+

+
+
Clarke transform for Q31 version. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]Iainput three-phase coordinate a 
[in]Ibinput three-phase coordinate b 
[out]*pIalphapoints to output two-phase orthogonal vector axis alpha 
[out]*pIbetapoints to output two-phase orthogonal vector axis beta 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 32-bit accumulator. The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. There is saturation on the addition, hence there is no risk of overflow. 

+
+
Definition at line 4934 of file arm_math.h.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__cmplx__conj.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__cmplx__conj.html
new file mode 100644
index 000000000..75d80dbd7
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__cmplx__conj.html
@@ -0,0 +1,231 @@
+
+
+
+
+CMSIS DSP Software Library: Complex Conjugate
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Complex Conjugate

+
+[Complex Math Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_cmplx_conj_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
void arm_cmplx_conj_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
void arm_cmplx_conj_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)

+
Detailed Description

+
Conjugates the elements of a complex data vector.

+
The pSrc points to the source data and pDst points to the where the result should be written. numSamples specifies the number of complex samples and the data in each array is stored in an interleaved fashion (real, imag, real, imag, ...). Each array has a total of 2*numSamples values. The underlying algorithm is used:

+
   
+ for(n=0; n<numSamples; n++) {   
+     pDst[(2*n)+0)] = pSrc[(2*n)+0];     // real part   
+     pDst[(2*n)+1)] = -pSrc[(2*n)+1];    // imag part   
+ }   
+ 
There are separate functions for floating-point, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_conj_f32 (float32_t *  pSrc, 
float32_t *  pDst, 
uint32_t  numSamples 
)

+

+

+
+
Floating-point complex conjugate. 

+
Parameters:

+  
+    
+    
+    
+  
*pSrcpoints to the input vector 
*pDstpoints to the output vector 
numSamplesnumber of complex samples in each vector 

+  

+

+
Returns:
none. 

+
+
Definition at line 72 of file arm_cmplx_conj_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
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+          
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+          
+          
+        
+      
void arm_cmplx_conj_q31 (q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  numSamples 
)

+

+

+
+
Q31 complex conjugate. 

+
Parameters:

+  
+    
+    
+    
+  
*pSrcpoints to the input vector 
*pDstpoints to the output vector 
numSamplesnumber of complex samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. 

+
+
Definition at line 54 of file arm_cmplx_conj_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+          
+        
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+          
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+        
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+          
+          
+        
+      
void arm_cmplx_conj_q15 (q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  numSamples 
)

+

+

+
+
Q15 complex conjugate. 

+
Parameters:

+  
+    
+    
+    
+  
*pSrcpoints to the input vector 
*pDstpoints to the output vector 
numSamplesnumber of complex samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. 

+
+
Definition at line 54 of file arm_cmplx_conj_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__cmplx__dot__prod.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__cmplx__dot__prod.html
new file mode 100644
index 000000000..749b8ccbe
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__cmplx__dot__prod.html
@@ -0,0 +1,276 @@
+
+
+
+
+CMSIS DSP Software Library: Complex Dot Product
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Complex Dot Product

+
+[Complex Math Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_cmplx_dot_prod_f32 (float32_t *pSrcA, float32_t *pSrcB, uint32_t numSamples, float32_t *realResult, float32_t *imagResult)
void arm_cmplx_dot_prod_q31 (q31_t *pSrcA, q31_t *pSrcB, uint32_t numSamples, q63_t *realResult, q63_t *imagResult)
void arm_cmplx_dot_prod_q15 (q15_t *pSrcA, q15_t *pSrcB, uint32_t numSamples, q31_t *realResult, q31_t *imagResult)

+
Detailed Description

+
Computes the dot product of two complex vectors. The vectors are multiplied element-by-element and then summed.

+
The pSrcA points to the first complex input vector and pSrcB points to the second complex input vector. numSamples specifies the number of complex samples and the data in each array is stored in an interleaved fashion (real, imag, real, imag, ...). Each array has a total of 2*numSamples values.

+
The underlying algorithm is used: 

+
   
+ realResult=0;   
+ imagResult=0;   
+ for(n=0; n<numSamples; n++) {   
+     realResult += pSrcA[(2*n)+0]*pSrcB[(2*n)+0] - pSrcA[(2*n)+1]*pSrcB[(2*n)+1];   
+     imagResult += pSrcA[(2*n)+0]*pSrcB[(2*n)+1] + pSrcA[(2*n)+1]*pSrcB[(2*n)+0];   
+ }   
+ 
There are separate functions for floating-point, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
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+        
+        
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+          
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+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_dot_prod_f32 (float32_t *  pSrcA, 
float32_t *  pSrcB, 
uint32_t  numSamples, 
float32_t *  realResult, 
float32_t *  imagResult 
)

+

+

+
+
Floating-point complex dot product. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
*pSrcApoints to the first input vector 
*pSrcBpoints to the second input vector 
numSamplesnumber of complex samples in each vector 
*realResultreal part of the result returned here 
*imagResultimaginary part of the result returned here 

+  

+

+
Returns:
none. 

+
+
Definition at line 77 of file arm_cmplx_dot_prod_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_dot_prod_q31 (q31_t *  pSrcA, 
q31_t *  pSrcB, 
uint32_t  numSamples, 
q63_t *  realResult, 
q63_t *  imagResult 
)

+

+

+
+
Q31 complex dot product. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
*pSrcApoints to the first input vector 
*pSrcBpoints to the second input vector 
numSamplesnumber of complex samples in each vector 
*realResultreal part of the result returned here 
*imagResultimaginary part of the result returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format. The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits. Additions are nonsaturating and no overflow will occur as long as numSamples is less than 32768. The return results realResult and imagResult are in 16.48 format. Input down scaling is not required. 

+
+
Definition at line 60 of file arm_cmplx_dot_prod_q31.c.

+
+

+

+
+

+

+      
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+        
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+          
+          
+          
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+          
+          
+        
+      
void arm_cmplx_dot_prod_q15 (q15_t *  pSrcA, 
q15_t *  pSrcB, 
uint32_t  numSamples, 
q31_t *  realResult, 
q31_t *  imagResult 
)

+

+

+
+
Q15 complex dot product. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
*pSrcApoints to the first input vector 
*pSrcBpoints to the second input vector 
numSamplesnumber of complex samples in each vector 
*realResultreal part of the result returned here 
*imagResultimaginary part of the result returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The intermediate 1.15 by 1.15 multiplications are performed with full precision and yield a 2.30 result. These are accumulated in a 64-bit accumulator with 34.30 precision. As a final step, the accumulators are converted to 8.24 format. The return results realResult and imagResult are in 8.24 format. 

+
+
Definition at line 59 of file arm_cmplx_dot_prod_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__cmplx__mag.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__cmplx__mag.html
new file mode 100644
index 000000000..b11123759
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__cmplx__mag.html
@@ -0,0 +1,231 @@
+
+
+
+
+CMSIS DSP Software Library: Complex Magnitude
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Complex Magnitude

+
+[Complex Math Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_cmplx_mag_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
void arm_cmplx_mag_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
void arm_cmplx_mag_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)

+
Detailed Description

+
Computes the magnitude of the elements of a complex data vector.

+
The pSrc points to the source data and pDst points to the where the result should be written. numSamples specifies the number of complex samples in the input array and the data is stored in an interleaved fashion (real, imag, real, imag, ...). The input array has a total of 2*numSamples values; the output array has a total of numSamples values. The underlying algorithm is used:

+
   
+ for(n=0; n<numSamples; n++) {   
+     pDst[n] = sqrt(pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2);   
+ }   
+ 
There are separate functions for floating-point, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
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+          
+          
+        
+      
void arm_cmplx_mag_f32 (float32_t *  pSrc, 
float32_t *  pDst, 
uint32_t  numSamples 
)

+

+

+
+
Floating-point complex magnitude. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to complex input buffer 
[out]*pDstpoints to real output buffer 
[in]numSamplesnumber of complex samples in the input vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_fft_bin_example_f32.c.

+

+
Definition at line 73 of file arm_cmplx_mag_f32.c.

+
+

+

+
+

+

+      
+        
+          
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+        
+      
void arm_cmplx_mag_q31 (q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  numSamples 
)

+

+

+
+
Q31 complex magnitude. 

+
Parameters:

+  
+    
+    
+    
+  
*pSrcpoints to the complex input vector 
*pDstpoints to the real output vector 
numSamplesnumber of complex samples in the input vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function implements 1.31 by 1.31 multiplications and finally output is converted into 2.30 format. Input down scaling is not required. 

+
+
Definition at line 54 of file arm_cmplx_mag_q31.c.

+
+

+

+
+

+

+      
+        
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+        
+      
void arm_cmplx_mag_q15 (q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  numSamples 
)

+

+

+
+
Q15 complex magnitude. 

+
Parameters:

+  
+    
+    
+    
+  
*pSrcpoints to the complex input vector 
*pDstpoints to the real output vector 
numSamplesnumber of complex samples in the input vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format. 

+
+
Definition at line 54 of file arm_cmplx_mag_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__cmplx__mag__squared.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__cmplx__mag__squared.html
new file mode 100644
index 000000000..84fe8dc3e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__cmplx__mag__squared.html
@@ -0,0 +1,231 @@
+
+
+
+
+CMSIS DSP Software Library: Complex Magnitude Squared
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Complex Magnitude Squared

+
+[Complex Math Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_cmplx_mag_squared_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
void arm_cmplx_mag_squared_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
void arm_cmplx_mag_squared_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)

+
Detailed Description

+
Computes the magnitude squared of the elements of a complex data vector.

+
The pSrc points to the source data and pDst points to the where the result should be written. numSamples specifies the number of complex samples in the input array and the data is stored in an interleaved fashion (real, imag, real, imag, ...). The input array has a total of 2*numSamples values; the output array has a total of numSamples values.

+
The underlying algorithm is used:

+
   
+ for(n=0; n<numSamples; n++) {   
+     pDst[n] = pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2;   
+ }   
+ 
There are separate functions for floating-point, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_mag_squared_f32 (float32_t *  pSrc, 
float32_t *  pDst, 
uint32_t  numSamples 
)

+

+

+
+
Floating-point complex magnitude squared. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the complex input vector 
[out]*pDstpoints to the real output vector 
[in]numSamplesnumber of complex samples in the input vector 

+  

+

+
Returns:
none. 

+
+
Definition at line 74 of file arm_cmplx_mag_squared_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
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+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_mag_squared_q31 (q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  numSamples 
)

+

+

+
+
Q31 complex magnitude squared. 

+
Parameters:

+  
+    
+    
+    
+  
*pSrcpoints to the complex input vector 
*pDstpoints to the real output vector 
numSamplesnumber of complex samples in the input vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format. Input down scaling is not required. 

+
+
Definition at line 55 of file arm_cmplx_mag_squared_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
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+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_mag_squared_q15 (q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  numSamples 
)

+

+

+
+
Q15 complex magnitude squared. 

+
Parameters:

+  
+    
+    
+    
+  
*pSrcpoints to the complex input vector 
*pDstpoints to the real output vector 
numSamplesnumber of complex samples in the input vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format. 

+
+
Definition at line 53 of file arm_cmplx_mag_squared_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__copy.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__copy.html
new file mode 100644
index 000000000..a511c79ee
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__copy.html
@@ -0,0 +1,271 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Copy
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Copy

+
+[Support Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_copy_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_copy_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_copy_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_copy_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)

+
Detailed Description

+
Copies sample by sample from source vector to destination vector.

+
   
+ 	pDst[n] = pSrc[n];   0 <= n < blockSize.   
+ 
There are separate functions for floating point, Q31, Q15, and Q7 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_copy_f32 (float32_t *  pSrc, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Copies the elements of a floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to input vector 
[out]*pDstpoints to output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_convolution_example_f32.c, arm_signal_converge_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 66 of file arm_copy_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_copy_q31 (q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Copies the elements of a Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to input vector 
[out]*pDstpoints to output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none. 

+
+
Definition at line 53 of file arm_copy_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_copy_q15 (q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Copies the elements of a Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to input vector 
[out]*pDstpoints to output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none. 

+
+
Definition at line 52 of file arm_copy_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_copy_q7 (q7_t *  pSrc, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Copies the elements of a Q7 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to input vector 
[out]*pDstpoints to output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none. 

+
+
Definition at line 53 of file arm_copy_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__cos.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__cos.html
new file mode 100644
index 000000000..763f78b30
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__cos.html
@@ -0,0 +1,258 @@
+
+
+
+
+CMSIS DSP Software Library: Cosine
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
Cosine

+
+[Fast Math Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+
+

+Functions
float32_t arm_cos_f32 (float32_t x)
q31_t arm_cos_q31 (q31_t x)
q15_t arm_cos_q15 (q15_t x)

+Variables
static const float32_t cosTable [259]
static const q31_t cosTableQ31 [259]
static const q15_t cosTableQ15 [259]

+
Detailed Description

+
Computes the trigonometric cosine function using a combination of table lookup and cubic interpolation. There are separate functions for Q15, Q31, and floating-point data types. The input to the floating-point version is in radians while the fixed-point Q15 and Q31 have a scaled input with the range [0 1) mapping to [0 2*pi).

+
The implementation is based on table lookup using 256 values together with cubic interpolation. The steps used are:

+
    
+
  1. Calculation of the nearest integer table index
    2. 
+
  2. Fetch the four table values a, b, c, and d
    3. 
+
  3. Compute the fractional portion (fract) of the table index.
    4. 
+
  4. Calculation of wa, wb, wc, wd
    5. 
+
  5. The final result equals a*wa + b*wb + c*wc + d*wd
    6. 
+

+
where 

+
   
+    a=Table[index-1];   
+    b=Table[index+0];   
+    c=Table[index+1];   
+    d=Table[index+2];   
+ 
 and 

+
   
+    wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;   
+    wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;   
+    wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;   
+    wd=(1/6)*fract.^3 - (1/6)*fract;   
+ 
 
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
float32_t arm_cos_f32 (float32_t  x )

+

+

+
+
Fast approximation to the trigonometric cosine function for floating-point data. 

+
Parameters:

+  
+    
+  
[in]xinput value in radians. 

+  

+

+
Returns:
cos(x). 

+
Examples: 
arm_sin_cos_example_f32.c.

+

+
Definition at line 192 of file arm_cos_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
q31_t arm_cos_q31 (q31_t  x )

+

+

+
+
Fast approximation to the trigonometric cosine function for Q31 data. 

+
Parameters:

+  
+    
+  
[in]xScaled input value in radians. 

+  

+

+
Returns:
cos(x).

+
The Q31 input value is in the range [0 +1) and is mapped to a radian value in the range [0 2*pi). 

+
+
Definition at line 136 of file arm_cos_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
q15_t arm_cos_q15 (q15_t  x )

+

+

+
+
Fast approximation to the trigonometric cosine function for Q15 data. 

+
Parameters:

+  
+    
+  
[in]xScaled input value in radians. 

+  

+

+
Returns:
cos(x).

+
The Q15 input value is in the range [0 +1) and is mapped to a radian value in the range [0 2*pi). 

+
+
Definition at line 105 of file arm_cos_q15.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float32_t cosTable[259] [static]

+

+

+
Example code for Generation of Cos Table: tableSize = 256; 
for(n = -1; n < (tableSize + 1); n++)   
+ {   
+	cosTable[n+1]= cos(2*pi*n/tableSize);   
+ } 
 where pi value is 3.14159265358979 

+
+
Definition at line 86 of file arm_cos_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t cosTableQ31[259] [static]

+

+

+
Table Values are in Q31(1.31 Fixed point format) and generation is done in three steps First Generate cos values in floating point: tableSize = 256; 
for(n = -1; n < (tableSize + 1); n++)   
+ {   
+	cosTable[n+1]= cos(2*pi*n/tableSize);   
+ } 
 where pi value is 3.14159265358979 

+
Secondly Convert Floating point to Q31(Fixed point): (cosTable[i] * pow(2, 31)) 

+
Finally Rounding to nearest integer is done cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5); 

+
+
Definition at line 60 of file arm_cos_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t cosTableQ15[259] [static]

+

+

+
Table Values are in Q15(1.15 Fixed point format) and generation is done in three steps 

+
First Generate cos values in floating point: tableSize = 256; 
for(n = -1; n < (tableSize + 1); n++)   
+ {   
+	cosTable[n+1]= cos(2*pi*n/tableSize);   
+ }
 where pi value is 3.14159265358979 

+
Secondly Convert Floating point to Q15(Fixed point): (cosTable[i] * pow(2, 15)) 

+
Finally Rounding to nearest integer is done cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5); 

+
+
Definition at line 60 of file arm_cos_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__dot__prod.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__dot__prod.html
new file mode 100644
index 000000000..878073c42
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__dot__prod.html
@@ -0,0 +1,302 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Dot Product
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Dot Product

+
+[Basic Math Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_dot_prod_f32 (float32_t *pSrcA, float32_t *pSrcB, uint32_t blockSize, float32_t *result)
void arm_dot_prod_q31 (q31_t *pSrcA, q31_t *pSrcB, uint32_t blockSize, q63_t *result)
void arm_dot_prod_q15 (q15_t *pSrcA, q15_t *pSrcB, uint32_t blockSize, q63_t *result)
void arm_dot_prod_q7 (q7_t *pSrcA, q7_t *pSrcB, uint32_t blockSize, q31_t *result)

+
Detailed Description

+
Computes the dot product of two vectors. The vectors are multiplied element-by-element and then summed. There are separate functions for floating-point, Q7, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_dot_prod_f32 (float32_t *  pSrcA, 
float32_t *  pSrcB, 
uint32_t  blockSize, 
float32_t *  result 
)

+

+

+
+
Dot product of floating-point vectors. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[in]blockSizenumber of samples in each vector 
[out]*resultoutput result returned here 

+  

+

+
Returns:
none. 

+
Examples: 
arm_variance_example_f32.c.

+

+
Definition at line 62 of file arm_dot_prod_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
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+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_dot_prod_q31 (q31_t *  pSrcA, 
q31_t *  pSrcB, 
uint32_t  blockSize, 
q63_t *  result 
)

+

+

+
+
Dot product of Q31 vectors. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[in]blockSizenumber of samples in each vector 
[out]*resultoutput result returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The intermediate multiplications are in 1.31 x 1.31 = 2.62 format and these are truncated to 2.48 format by discarding the lower 14 bits. The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. There are 15 guard bits in the accumulator and there is no risk of overflow as long as the length of the vectors is less than 2^16 elements. The return result is in 16.48 format. 

+
+
Definition at line 62 of file arm_dot_prod_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_dot_prod_q15 (q15_t *  pSrcA, 
q15_t *  pSrcB, 
uint32_t  blockSize, 
q63_t *  result 
)

+

+

+
+
Dot product of Q15 vectors. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[in]blockSizenumber of samples in each vector 
[out]*resultoutput result returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The intermediate multiplications are in 1.15 x 1.15 = 2.30 format and these results are added to a 64-bit accumulator in 34.30 format. Nonsaturating additions are used and given that there are 33 guard bits in the accumulator there is no risk of overflow. The return result is in 34.30 format. 

+
+
Definition at line 61 of file arm_dot_prod_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
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+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_dot_prod_q7 (q7_t *  pSrcA, 
q7_t *  pSrcB, 
uint32_t  blockSize, 
q31_t *  result 
)

+

+

+
+
Dot product of Q7 vectors. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[in]blockSizenumber of samples in each vector 
[out]*resultoutput result returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The intermediate multiplications are in 1.7 x 1.7 = 2.14 format and these results are added to an accumulator in 18.14 format. Nonsaturating additions are used and there is no danger of wrap around as long as the vectors are less than 2^18 elements long. The return result is in 18.14 format. 

+
+
Definition at line 61 of file arm_dot_prod_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__float__to__x.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__float__to__x.html
new file mode 100644
index 000000000..6b4dde568
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__float__to__x.html
@@ -0,0 +1,240 @@
+
+
+
+
+CMSIS DSP Software Library: Convert 32-bit floating point value
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Convert 32-bit floating point value

+
+[Support Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_float_to_q31 (float32_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_float_to_q15 (float32_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_float_to_q7 (float32_t *pSrc, q7_t *pDst, uint32_t blockSize)

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
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+        
+          
+          
+          
+        
+      
void arm_float_to_q31 (float32_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Converts the elements of the floating-point vector to Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the floating-point input vector 
[out]*pDstpoints to the Q31 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
   
+ 	pDst[n] = (q31_t)(pSrc[n] * 2147483648);   0 <= n < blockSize.   
+ 
 Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.

+
Note:
In order to apply rounding, the library should be rebuilt with the ROUNDING macro defined in the preprocessor section of project options. 

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 69 of file arm_float_to_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_float_to_q15 (float32_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Converts the elements of the floating-point vector to Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the floating-point input vector 
[out]*pDstpoints to the Q15 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is: 
   
+ 	pDst[n] = (q15_t)(pSrc[n] * 32768);   0 <= n < blockSize.   
+ 
 

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 

+
Note:
In order to apply rounding, the library should be rebuilt with the ROUNDING macro defined in the preprocessor section of project options. 

+
+
Definition at line 65 of file arm_float_to_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_float_to_q7 (float32_t *  pSrc, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Converts the elements of the floating-point vector to Q7 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the floating-point input vector 
[out]*pDstpoints to the Q7 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is: 
   
+ 	pDst[n] = (q7_t)(pSrc[n] * 128);   0 <= n < blockSize.   
+ 
 

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. 

+
Note:
In order to apply rounding, the library should be rebuilt with the ROUNDING macro defined in the preprocessor section of project options. 

+
+
Definition at line 64 of file arm_float_to_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_cmplx_math.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_cmplx_math.html
new file mode 100644
index 000000000..dc545bf47
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_cmplx_math.html
@@ -0,0 +1,81 @@
+
+
+
+
+CMSIS DSP Software Library: Complex Math Functions
+
+
+
+
+
+
+
+
+
+

+  

+Modules  

+  

+
Complex Math Functions
  

+

+

+
+
+
+
+
+
+
+
+

+Modules
 Complex Conjugate
 Complex Dot Product
 Complex Magnitude
 Complex Magnitude Squared
 Complex-by-Complex Multiplication
 Complex-by-Real Multiplication

+
Detailed Description

+
This set of functions operates on complex data vectors. The data in the complex arrays is stored in an interleaved fashion (real, imag, real, imag, ...). In the API functions, the number of samples in a complex array refers to the number of complex values; the array contains twice this number of real values. 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_controller.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_controller.html
new file mode 100644
index 000000000..276205796
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_controller.html
@@ -0,0 +1,79 @@
+
+
+
+
+CMSIS DSP Software Library: Controller Functions
+
+
+
+
+
+
+
+
+
+

+  

+Modules  

+  

+
Controller Functions
  

+

+

+
+
+
+
+
+
+
+
+

+Modules
 Sine Cosine
 PID Motor Control
 Vector Clarke Transform
 Vector Inverse Clarke Transform
 Vector Park Transform
 Vector Inverse Park transform

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_examples.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_examples.html
new file mode 100644
index 000000000..cc4969cac
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_examples.html
@@ -0,0 +1,84 @@
+
+
+
+
+CMSIS DSP Software Library: Examples
+
+
+
+
+
+
+
+
+
+

+  

+Modules  

+  

+
Examples
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Modules
 Class Marks Example
 Convolution Example
 Dot Product Example
 FIR Lowpass Filter Example
 Frequency Bin Example
 Graphic Audio Equalizer Example
 Linear Interpolate Example
 Matrix Example
 Signal Convergence Example
 SineCosine Example
 Variance Example

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_fast_math.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_fast_math.html
new file mode 100644
index 000000000..2b8978a0e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_fast_math.html
@@ -0,0 +1,78 @@
+
+
+
+
+CMSIS DSP Software Library: Fast Math Functions
+
+
+
+
+
+
+
+
+
+

+  

+Modules  

+  

+
Fast Math Functions
  

+

+

+
+
+
+
+
+

+Modules
 Cosine
 Sine
 Square Root

+
Detailed Description

+
This set of functions provides a fast approximation to sine, cosine, and square root. As compared to most of the other functions in the CMSIS math library, the fast math functions operate on individual values and not arrays. There are separate functions for Q15, Q31, and floating-point data. 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_filters.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_filters.html
new file mode 100644
index 000000000..6a16cc14c
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_filters.html
@@ -0,0 +1,87 @@
+
+
+
+
+CMSIS DSP Software Library: Filtering Functions
+
+
+
+
+
+
+
+
+
+

+  

+Modules  

+  

+
Filtering Functions
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Modules
 Biquad Cascade IIR Filters Using Direct Form I Structure
 Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
 High Precision Q31 Biquad Cascade Filter
 Convolution
 Partial Convolution
 Correlation
 Finite Impulse Response (FIR) Decimator
 Finite Impulse Response (FIR) Filters
 Finite Impulse Response (FIR) Lattice Filters
 Finite Impulse Response (FIR) Sparse Filters
 Infinite Impulse Response (IIR) Lattice Filters
 Least Mean Square (LMS) Filters
 Normalized LMS Filters
 Finite Impulse Response (FIR) Interpolator

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_interpolation.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_interpolation.html
new file mode 100644
index 000000000..9be728096
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_interpolation.html
@@ -0,0 +1,77 @@
+
+
+
+
+CMSIS DSP Software Library: Interpolation Functions
+
+
+
+
+
+
+
+
+
+

+  

+Modules  

+  

+
Interpolation Functions
  

+

+

+
+
+
+
+

+Modules
 Linear Interpolation
 Bilinear Interpolation

+
Detailed Description

+
These functions perform 1- and 2-dimensional interpolation of data. Linear interpolation is used for 1-dimensional data and bilinear interpolation is used for 2-dimensional data. 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_math.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_math.html
new file mode 100644
index 000000000..6797edbbe
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_math.html
@@ -0,0 +1,82 @@
+
+
+
+
+CMSIS DSP Software Library: Basic Math Functions
+
+
+
+
+
+
+
+
+
+

+  

+Modules  

+  

+
Basic Math Functions
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+

+Modules
 Vector Absolute Value
 Vector Addition
 Vector Dot Product
 Vector Multiplication
 Vector Negate
 Vector Offset
 Vector Scale
 Vector Shift
 Vector Subtraction

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_matrix.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_matrix.html
new file mode 100644
index 000000000..db0d3edb1
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_matrix.html
@@ -0,0 +1,106 @@
+
+
+
+
+CMSIS DSP Software Library: Matrix Functions
+
+
+
+
+
+
+
+
+
+

+  

+Modules  

+  

+
Matrix Functions
  

+

+

+
+
+
+
+
+
+
+
+
+

+Modules
 Matrix Addition
 Matrix Initialization
 Matrix Inverse
 Matrix Multiplication
 Matrix Scale
 Matrix Subtraction
 Matrix Transpose

+
Detailed Description

+
This set of functions provides basic matrix math operations. The functions operate on matrix data structures. For example, the type definition for the floating-point matrix structure is shown below: 

+
+     typedef struct
+     {
+       uint16_t numRows;     // number of rows of the matrix.
+       uint16_t numCols;     // number of columns of the matrix.
+       float32_t *pData;     // points to the data of the matrix.
+     } arm_matrix_instance_f32;
+ 
 There are similar definitions for Q15 and Q31 data types.

+
The structure specifies the size of the matrix and then points to an array of data. The array is of size numRows X numCols and the values are arranged in row order. That is, the matrix element (i, j) is stored at: 

+
+     pData[i*numCols + j]
+ 
Init Functions
There is an associated initialization function for each type of matrix data structure. The initialization function sets the values of the internal structure fields. Refer to the function arm_mat_init_f32(), arm_mat_init_q31() and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively.

+
Use of the initialization function is optional. However, if initialization function is used then the instance structure cannot be placed into a const data section. To place the instance structure in a const data section, manually initialize the data structure. For example: 
+ arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ 
 where nRows specifies the number of rows, nColumns specifies the number of columns, and pData points to the data array.

+
Size Checking
By default all of the matrix functions perform size checking on the input and output matrices. For example, the matrix addition function verifies that the two input matrices and the output matrix all have the same number of rows and columns. If the size check fails the functions return: 
+     ARM_MATH_SIZE_MISMATCH
+ 
 Otherwise the functions return 
+     ARM_MATH_SUCCESS
+ 
 There is some overhead associated with this matrix size checking. The matrix size checking is enabled via the define 
+     ARM_MATH_MATRIX_CHECK
+ 
 within the library project settings. By default this macro is defined and size checking is enabled. By changing the project settings and undefining this macro size checking is eliminated and the functions run a bit faster. With size checking disabled the functions always return ARM_MATH_SUCCESS. 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_stats.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_stats.html
new file mode 100644
index 000000000..1e0ed8a7c
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_stats.html
@@ -0,0 +1,80 @@
+
+
+
+
+CMSIS DSP Software Library: Statistics Functions
+
+
+
+
+
+
+
+
+
+

+  

+Modules  

+  

+
Statistics Functions
  

+

+

+
+
+
+
+
+
+
+
+
+

+Modules
 Maximum
 Mean
 Minimum
 Power
 Root mean square (RMS)
 Standard deviation
 Variance

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_support.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_support.html
new file mode 100644
index 000000000..f58098c22
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_support.html
@@ -0,0 +1,79 @@
+
+
+
+
+CMSIS DSP Software Library: Support Functions
+
+
+
+
+
+
+
+
+
+

+  

+Modules  

+  

+
Support Functions
  

+

+

+
+
+
+
+
+
+
+
+

+Modules
 Convert 16-bit Integer value
 Convert 32-bit Integer value
 Convert 32-bit floating point value
 Convert 8-bit Integer value
 Vector Copy
 Vector Fill

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_transforms.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_transforms.html
new file mode 100644
index 000000000..fad94d404
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__group_transforms.html
@@ -0,0 +1,76 @@
+
+
+
+
+CMSIS DSP Software Library: Transform Functions
+
+
+
+
+
+
+
+
+
+

+  

+Modules  

+  

+
Transform Functions
  

+

+

+
+
+
+
+
+

+Modules
 Complex FFT Functions
 DCT Type IV Functions
 Real FFT Functions

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__inv__clarke.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__inv__clarke.html
new file mode 100644
index 000000000..a4d75a062
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__inv__clarke.html
@@ -0,0 +1,195 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Inverse Clarke Transform
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Inverse Clarke Transform

+
+[Controller Functions]
+
  

+

+

+
+
+
+
+

+Functions
static __INLINE void arm_inv_clarke_f32 (float32_t Ialpha, float32_t Ibeta, float32_t *pIa, float32_t *pIb)
static __INLINE void arm_inv_clarke_q31 (q31_t Ialpha, q31_t Ibeta, q31_t *pIa, q31_t *pIb)

+
Detailed Description

+
Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.

+
The function operates on a single sample of data and each call to the function returns the processed output. The library provides separate functions for Q31 and floating-point data types. 

+
Algorithm

+clarkeInvFormula.gif
+

+ where pIa and pIb are the instantaneous stator phases and Ialpha and Ibeta are the two coordinates of time invariant vector. 

+
Fixed-Point Behavior
Care must be taken when using the Q31 version of the Clarke transform. In particular, the overflow and saturation behavior of the accumulator used must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
static __INLINE void arm_inv_clarke_f32 (float32_t  Ialpha, 
float32_t  Ibeta, 
float32_t *  pIa, 
float32_t *  pIb 
) [static]

+

+

+
+
Floating-point Inverse Clarke transform. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]Ialphainput two-phase orthogonal vector axis alpha 
[in]Ibetainput two-phase orthogonal vector axis beta 
[out]*pIapoints to output three-phase coordinate a 
[out]*pIbpoints to output three-phase coordinate b 

+  

+

+
Returns:
none. 

+
+
Definition at line 5009 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
static __INLINE void arm_inv_clarke_q31 (q31_t  Ialpha, 
q31_t  Ibeta, 
q31_t *  pIa, 
q31_t *  pIb 
) [static]

+

+

+
+
Inverse Clarke transform for Q31 version. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]Ialphainput two-phase orthogonal vector axis alpha 
[in]Ibetainput two-phase orthogonal vector axis beta 
[out]*pIapoints to output three-phase coordinate a 
[out]*pIbpoints to output three-phase coordinate b 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 32-bit accumulator. The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. There is saturation on the subtraction, hence there is no risk of overflow. 

+
+
Definition at line 5038 of file arm_math.h.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__inv__park.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__inv__park.html
new file mode 100644
index 000000000..a97fddc0d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__inv__park.html
@@ -0,0 +1,223 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Inverse Park transform
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Inverse Park transform

+
+[Controller Functions]
+
  

+

+

+
+
+
+
+

+Functions
static __INLINE void arm_inv_park_f32 (float32_t Id, float32_t Iq, float32_t *pIalpha, float32_t *pIbeta, float32_t sinVal, float32_t cosVal)
static __INLINE void arm_inv_park_q31 (q31_t Id, q31_t Iq, q31_t *pIalpha, q31_t *pIbeta, q31_t sinVal, q31_t cosVal)

+
Detailed Description

+
Inverse Park transform converts the input flux and torque components to two-coordinate vector.

+
The function operates on a single sample of data and each call to the function returns the processed output. The library provides separate functions for Q31 and floating-point data types. 

+
Algorithm

+parkInvFormula.gif
+

+ where pIalpha and pIbeta are the stator vector components, Id and Iq are rotor vector components and cosVal and sinVal are the cosine and sine values of theta (rotor flux position). 

+
Fixed-Point Behavior
Care must be taken when using the Q31 version of the Park transform. In particular, the overflow and saturation behavior of the accumulator used must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
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+      
static __INLINE void arm_inv_park_f32 (float32_t  Id, 
float32_t  Iq, 
float32_t *  pIalpha, 
float32_t *  pIbeta, 
float32_t  sinVal, 
float32_t  cosVal 
) [static]

+

+

+
+
Floating-point Inverse Park transform. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]Idinput coordinate of rotor reference frame d 
[in]Iqinput coordinate of rotor reference frame q 
[out]*pIalphapoints to output two-phase orthogonal vector axis alpha 
[out]*pIbetapoints to output two-phase orthogonal vector axis beta 
[in]sinValsine value of rotation angle theta 
[in]cosValcosine value of rotation angle theta 

+  

+

+
Returns:
none. 

+
+
Definition at line 5244 of file arm_math.h.

+
+

+

+
+

+

+      
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+      
static __INLINE void arm_inv_park_q31 (q31_t  Id, 
q31_t  Iq, 
q31_t *  pIalpha, 
q31_t *  pIbeta, 
q31_t  sinVal, 
q31_t  cosVal 
) [static]

+

+

+
+
Inverse Park transform for Q31 version. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]Idinput coordinate of rotor reference frame d 
[in]Iqinput coordinate of rotor reference frame q 
[out]*pIalphapoints to output two-phase orthogonal vector axis alpha 
[out]*pIbetapoints to output two-phase orthogonal vector axis beta 
[in]sinValsine value of rotation angle theta 
[in]cosValcosine value of rotation angle theta 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 32-bit accumulator. The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. There is saturation on the addition, hence there is no risk of overflow. 

+
+
Definition at line 5279 of file arm_math.h.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__mean.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__mean.html
new file mode 100644
index 000000000..eeee74c24
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__mean.html
@@ -0,0 +1,277 @@
+
+
+
+
+CMSIS DSP Software Library: Mean
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Mean

+
+[Statistics Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_mean_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
void arm_mean_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
void arm_mean_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)
void arm_mean_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult)

+
Detailed Description

+
Calculates the mean of the input vector. Mean is defined as the average of the elements in the vector. The underlying algorithm is used:

+
   
+ 	Result = (pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]) / blockSize;   
+ 
There are separate functions for floating-point, Q31, Q15, and Q7 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
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+          
+        
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+          
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+        
+      
void arm_mean_f32 (float32_t *  pSrc, 
uint32_t  blockSize, 
float32_t *  pResult 
)

+

+

+
+
Mean value of a floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmean value returned here 

+  

+

+
Returns:
none. 

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 64 of file arm_mean_f32.c.

+
+

+

+
+

+

+      
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+        
+      
void arm_mean_q31 (q31_t *  pSrc, 
uint32_t  blockSize, 
q31_t *  pResult 
)

+

+

+
+
Mean value of a Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmean value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 64-bit internal accumulator. The input is represented in 1.31 format and is accumulated in a 64-bit accumulator in 33.31 format. There is no risk of internal overflow with this approach, and the full precision of intermediate result is preserved. Finally, the accumulator is truncated to yield a result of 1.31 format. 

+
+
Definition at line 61 of file arm_mean_q31.c.

+
+

+

+
+

+

+      
+        
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+          
+          
+          
+        
+      
void arm_mean_q15 (q15_t *  pSrc, 
uint32_t  blockSize, 
q15_t *  pResult 
)

+

+

+
+
Mean value of a Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmean value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 32-bit internal accumulator. The input is represented in 1.15 format and is accumulated in a 32-bit accumulator in 17.15 format. There is no risk of internal overflow with this approach, and the full precision of intermediate result is preserved. Finally, the accumulator is saturated and truncated to yield a result of 1.15 format. 

+
+
Definition at line 61 of file arm_mean_q15.c.

+
+

+

+
+

+

+      
+        
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+          
+          
+          
+        
+      
void arm_mean_q7 (q7_t *  pSrc, 
uint32_t  blockSize, 
q7_t *  pResult 
)

+

+

+
+
Mean value of a Q7 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmean value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 32-bit internal accumulator. The input is represented in 1.7 format and is accumulated in a 32-bit accumulator in 25.7 format. There is no risk of internal overflow with this approach, and the full precision of intermediate result is preserved. Finally, the accumulator is truncated to yield a result of 1.7 format. 

+
+
Definition at line 61 of file arm_mean_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__negate.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__negate.html
new file mode 100644
index 000000000..f12829532
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__negate.html
@@ -0,0 +1,275 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Negate
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Negate

+
+[Basic Math Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_negate_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_negate_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_negate_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_negate_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)

+
Detailed Description

+
Negates the elements of a vector.

+
   
+     pDst[n] = -pSrc[n],   0 <= n < blockSize.   
+ 
 
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
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+        
+      
void arm_negate_f32 (float32_t *  pSrc, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Negates the elements of a floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none. 

+
+
Definition at line 62 of file arm_negate_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
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+          
+          
+        
+      
void arm_negate_q31 (q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Negates the elements of a Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. 

+
+
Definition at line 57 of file arm_negate_q31.c.

+
+

+

+
+

+

+      
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+      
void arm_negate_q15 (q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Negates the elements of a Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. 

+
+
Definition at line 57 of file arm_negate_q15.c.

+
+

+

+
+

+

+      
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+      
void arm_negate_q7 (q7_t *  pSrc, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Negates the elements of a Q7 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. 

+
+
Definition at line 57 of file arm_negate_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__offset.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__offset.html
new file mode 100644
index 000000000..2160d7919
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__offset.html
@@ -0,0 +1,304 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Offset
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Offset

+
+[Basic Math Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_offset_f32 (float32_t *pSrc, float32_t offset, float32_t *pDst, uint32_t blockSize)
void arm_offset_q31 (q31_t *pSrc, q31_t offset, q31_t *pDst, uint32_t blockSize)
void arm_offset_q15 (q15_t *pSrc, q15_t offset, q15_t *pDst, uint32_t blockSize)
void arm_offset_q7 (q7_t *pSrc, q7_t offset, q7_t *pDst, uint32_t blockSize)

+
Detailed Description

+
Adds a constant offset to each element of a vector.

+
   
+     pDst[n] = pSrc[n] + offset,   0 <= n < blockSize.   
+ 
There are separate functions for floating-point, Q7, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
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+          
+          
+        
+      
void arm_offset_f32 (float32_t *  pSrc, 
float32_t  offset, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Adds a constant offset to a floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]offsetis the offset to be added 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none. 

+
+
Definition at line 66 of file arm_offset_f32.c.

+
+

+

+
+

+

+      
+        
+          
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+      
void arm_offset_q31 (q31_t *  pSrc, 
q31_t  offset, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Adds a constant offset to a Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]offsetis the offset to be added 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. 

+
+
Definition at line 58 of file arm_offset_q31.c.

+
+

+

+
+

+

+      
+        
+          
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+          
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+        
+      
void arm_offset_q15 (q15_t *  pSrc, 
q15_t  offset, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Adds a constant offset to a Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]offsetis the offset to be added 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. 

+
+
Definition at line 58 of file arm_offset_q15.c.

+
+

+

+
+

+

+      
+        
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+          
+          
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+        
+      
void arm_offset_q7 (q7_t *  pSrc, 
q7_t  offset, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Adds a constant offset to a Q7 vector. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]offsetis the offset to be added 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q7 range [0x80 0x7F] are saturated. 

+
+
Definition at line 58 of file arm_offset_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__park.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__park.html
new file mode 100644
index 000000000..c29f989b4
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__park.html
@@ -0,0 +1,227 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Park Transform
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Park Transform

+
+[Controller Functions]
+
  

+

+

+
+
+
+
+

+Functions
static __INLINE void arm_park_f32 (float32_t Ialpha, float32_t Ibeta, float32_t *pId, float32_t *pIq, float32_t sinVal, float32_t cosVal)
static __INLINE void arm_park_q31 (q31_t Ialpha, q31_t Ibeta, q31_t *pId, q31_t *pIq, q31_t sinVal, q31_t cosVal)

+
Detailed Description

+
Forward Park transform converts the input two-coordinate vector to flux and torque components. The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents from the stationary to the moving reference frame and control the spatial relationship between the stator vector current and rotor flux vector. If we consider the d axis aligned with the rotor flux, the diagram below shows the current vector and the relationship from the two reference frames: 

+

+park.gif
+
Stator current space vector and its component in (a,b) and in the d,q rotating reference frame

+
 The function operates on a single sample of data and each call to the function returns the processed output. The library provides separate functions for Q31 and floating-point data types. 

+
Algorithm

+parkFormula.gif
+

+ where Ialpha and Ibeta are the stator vector components, pId and pIq are rotor vector components and cosVal and sinVal are the cosine and sine values of theta (rotor flux position). 

+
Fixed-Point Behavior
Care must be taken when using the Q31 version of the Park transform. In particular, the overflow and saturation behavior of the accumulator used must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
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+      
static __INLINE void arm_park_f32 (float32_t  Ialpha, 
float32_t  Ibeta, 
float32_t *  pId, 
float32_t *  pIq, 
float32_t  sinVal, 
float32_t  cosVal 
) [static]

+

+

+
+
Floating-point Park transform. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]Ialphainput two-phase vector coordinate alpha 
[in]Ibetainput two-phase vector coordinate beta 
[out]*pIdpoints to output rotor reference frame d 
[out]*pIqpoints to output rotor reference frame q 
[in]sinValsine value of rotation angle theta 
[in]cosValcosine value of rotation angle theta 

+  

+

+
Returns:
none.

+
The function implements the forward Park transform. 

+
+
Definition at line 5125 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
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+          
+        
+        
+          
+          
+          
+        
+      
static __INLINE void arm_park_q31 (q31_t  Ialpha, 
q31_t  Ibeta, 
q31_t *  pId, 
q31_t *  pIq, 
q31_t  sinVal, 
q31_t  cosVal 
) [static]

+

+

+
+
Park transform for Q31 version. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]Ialphainput two-phase vector coordinate alpha 
[in]Ibetainput two-phase vector coordinate beta 
[out]*pIdpoints to output rotor reference frame d 
[out]*pIqpoints to output rotor reference frame q 
[in]sinValsine value of rotation angle theta 
[in]cosValcosine value of rotation angle theta 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 32-bit accumulator. The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. There is saturation on the addition and subtraction, hence there is no risk of overflow. 

+
+
Definition at line 5159 of file arm_math.h.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__power.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__power.html
new file mode 100644
index 000000000..ffd63a699
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__power.html
@@ -0,0 +1,276 @@
+
+
+
+
+CMSIS DSP Software Library: Power
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Power

+
+[Statistics Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_power_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
void arm_power_q31 (q31_t *pSrc, uint32_t blockSize, q63_t *pResult)
void arm_power_q15 (q15_t *pSrc, uint32_t blockSize, q63_t *pResult)
void arm_power_q7 (q7_t *pSrc, uint32_t blockSize, q31_t *pResult)

+
Detailed Description

+
Calculates the sum of the squares of the elements in the input vector. The underlying algorithm is used:

+
   
+ 	Result = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + pSrc[2] * pSrc[2] + ... + pSrc[blockSize-1] * pSrc[blockSize-1];   
+ 
There are separate functions for floating point, Q31, Q15, and Q7 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_power_f32 (float32_t *  pSrc, 
uint32_t  blockSize, 
float32_t *  pResult 
)

+

+

+
+
Sum of the squares of the elements of a floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultsum of the squares value returned here 

+  

+

+
Returns:
none. 

+
+
Definition at line 68 of file arm_power_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
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+        
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+          
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+        
+        
+          
+          
+          
+        
+      
void arm_power_q31 (q31_t *  pSrc, 
uint32_t  blockSize, 
q63_t *  pResult 
)

+

+

+
+
Sum of the squares of the elements of a Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultsum of the squares value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 64-bit internal accumulator. The input is represented in 1.31 format. Intermediate multiplication yields a 2.62 format, and this result is truncated to 2.48 format by discarding the lower 14 bits. The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. With 15 guard bits in the accumulator, there is no risk of overflow, and the full precision of the intermediate multiplication is preserved. Finally, the return result is in 16.48 format. 

+
+
Definition at line 63 of file arm_power_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_power_q15 (q15_t *  pSrc, 
uint32_t  blockSize, 
q63_t *  pResult 
)

+

+

+
+
Sum of the squares of the elements of a Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultsum of the squares value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 64-bit internal accumulator. The input is represented in 1.15 format. Intermediate multiplication yields a 2.30 format, and this result is added without saturation to a 64-bit accumulator in 34.30 format. With 33 guard bits in the accumulator, there is no risk of overflow, and the full precision of the intermediate multiplication is preserved. Finally, the return result is in 34.30 format. 

+
+
Definition at line 62 of file arm_power_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_power_q7 (q7_t *  pSrc, 
uint32_t  blockSize, 
q31_t *  pResult 
)

+

+

+
+
Sum of the squares of the elements of a Q7 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultsum of the squares value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 32-bit internal accumulator. The input is represented in 1.7 format. Intermediate multiplication yields a 2.14 format, and this result is added without saturation to an accumulator in 18.14 format. With 17 guard bits in the accumulator, there is no risk of overflow, and the full precision of the intermediate multiplication is preserved. Finally, the return result is in 18.14 format. 

+
+
Definition at line 62 of file arm_power_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__q15__to__x.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__q15__to__x.html
new file mode 100644
index 000000000..9db84bf6c
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__q15__to__x.html
@@ -0,0 +1,230 @@
+
+
+
+
+CMSIS DSP Software Library: Convert 16-bit Integer value
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Convert 16-bit Integer value

+
+[Support Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_q15_to_float (q15_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_q15_to_q31 (q15_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_q15_to_q7 (q15_t *pSrc, q7_t *pDst, uint32_t blockSize)

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_q15_to_float (q15_t *  pSrc, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Converts the elements of the Q15 vector to floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q15 input vector 
[out]*pDstpoints to the floating-point output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
   
+ 	pDst[n] = (float32_t) pSrc[n] / 32768;   0 <= n < blockSize.   
+ 
 
+
Definition at line 66 of file arm_q15_to_float.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_q15_to_q31 (q15_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Converts the elements of the Q15 vector to Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q15 input vector 
[out]*pDstpoints to the Q31 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
   
+ 	pDst[n] = (q31_t) pSrc[n] << 16;   0 <= n < blockSize.   
+ 
 
+
Definition at line 59 of file arm_q15_to_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
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+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_q15_to_q7 (q15_t *  pSrc, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Converts the elements of the Q15 vector to Q7 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q15 input vector 
[out]*pDstpoints to the Q7 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
   
+ 	pDst[n] = (q7_t) pSrc[n] >> 8;   0 <= n < blockSize.   
+ 
 
+
Definition at line 60 of file arm_q15_to_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__q31__to__x.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__q31__to__x.html
new file mode 100644
index 000000000..05af0fc53
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__q31__to__x.html
@@ -0,0 +1,231 @@
+
+
+
+
+CMSIS DSP Software Library: Convert 32-bit Integer value
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Convert 32-bit Integer value

+
+[Support Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_q31_to_float (q31_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_q31_to_q15 (q31_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_q31_to_q7 (q31_t *pSrc, q7_t *pDst, uint32_t blockSize)

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_q31_to_float (q31_t *  pSrc, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Converts the elements of the Q31 vector to floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q31 input vector 
[out]*pDstpoints to the floating-point output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
   
+ 	pDst[n] = (float32_t) pSrc[n] / 2147483648;   0 <= n < blockSize.   
+ 
 
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 63 of file arm_q31_to_float.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_q31_to_q15 (q31_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Converts the elements of the Q31 vector to Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q31 input vector 
[out]*pDstpoints to the Q15 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
   
+ 	pDst[n] = (q15_t) pSrc[n] >> 16;   0 <= n < blockSize.   
+ 
 
+
Definition at line 59 of file arm_q31_to_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_q31_to_q7 (q31_t *  pSrc, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Converts the elements of the Q31 vector to Q7 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q31 input vector 
[out]*pDstpoints to the Q7 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
   
+ 	pDst[n] = (q7_t) pSrc[n] >> 24;   0 <= n < blockSize.    
+ 
 
+
Definition at line 59 of file arm_q31_to_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__q7__to__x.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__q7__to__x.html
new file mode 100644
index 000000000..f360d8a39
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__q7__to__x.html
@@ -0,0 +1,230 @@
+
+
+
+
+CMSIS DSP Software Library: Convert 8-bit Integer value
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Convert 8-bit Integer value

+
+[Support Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_q7_to_float (q7_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_q7_to_q31 (q7_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_q7_to_q15 (q7_t *pSrc, q15_t *pDst, uint32_t blockSize)

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_q7_to_float (q7_t *  pSrc, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Converts the elements of the Q7 vector to floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q7 input vector 
[out]*pDstpoints to the floating-point output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
   
+ 	pDst[n] = (float32_t) pSrc[n] / 128;   0 <= n < blockSize.   
+ 
 
+
Definition at line 63 of file arm_q7_to_float.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_q7_to_q31 (q7_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Converts the elements of the Q7 vector to Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q7 input vector 
[out]*pDstpoints to the Q31 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
   
+ 	pDst[n] = (q31_t) pSrc[n] << 24;   0 <= n < blockSize.  
+ 
 
+
Definition at line 59 of file arm_q7_to_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_q7_to_q15 (q7_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Converts the elements of the Q7 vector to Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q7 input vector 
[out]*pDstpoints to the Q15 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
   
+ 	pDst[n] = (q15_t) pSrc[n] << 8;   0 <= n < blockSize.   
+ 
 
+
Definition at line 62 of file arm_q7_to_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__scale.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__scale.html
new file mode 100644
index 000000000..0fa721572
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__scale.html
@@ -0,0 +1,332 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Scale
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Scale

+
+[Basic Math Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_scale_f32 (float32_t *pSrc, float32_t scale, float32_t *pDst, uint32_t blockSize)
void arm_scale_q31 (q31_t *pSrc, q31_t scaleFract, int8_t shift, q31_t *pDst, uint32_t blockSize)
void arm_scale_q15 (q15_t *pSrc, q15_t scaleFract, int8_t shift, q15_t *pDst, uint32_t blockSize)
void arm_scale_q7 (q7_t *pSrc, q7_t scaleFract, int8_t shift, q7_t *pDst, uint32_t blockSize)

+
Detailed Description

+
Multiply a vector by a scalar value. For floating-point data, the algorithm used is:

+
   
+     pDst[n] = pSrc[n] * scale,   0 <= n < blockSize.   
+ 
In the fixed-point Q7, Q15, and Q31 functions, scale is represented by a fractional multiplication scaleFract and an arithmetic shift shift. The shift allows the gain of the scaling operation to exceed 1.0. The algorithm used with fixed-point data is:

+
   
+     pDst[n] = (pSrc[n] * scaleFract) << shift,   0 <= n < blockSize.   
+ 
The overall scale factor applied to the fixed-point data is 

+
   
+     scale = scaleFract * 2^shift.   
+ 
 
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
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+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_scale_f32 (float32_t *  pSrc, 
float32_t  scale, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Multiplies a floating-point vector by a scalar. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]scalescale factor to be applied 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_graphic_equalizer_example_q31.c, and arm_signal_converge_example_f32.c.

+

+
Definition at line 78 of file arm_scale_f32.c.

+
+

+

+
+

+

+      
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+          
+        
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+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_scale_q31 (q31_t *  pSrc, 
q31_t  scaleFract, 
int8_t  shift, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Multiplies a Q31 vector by a scalar. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]scaleFractfractional portion of the scale value 
[in]shiftnumber of bits to shift the result by 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The input data *pSrc and scaleFract are in 1.31 format. These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format. 

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 59 of file arm_scale_q31.c.

+
+

+

+
+

+

+      
+        
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+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_scale_q15 (q15_t *  pSrc, 
q15_t  scaleFract, 
int8_t  shift, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Multiplies a Q15 vector by a scalar. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]scaleFractfractional portion of the scale value 
[in]shiftnumber of bits to shift the result by 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The input data *pSrc and scaleFract are in 1.15 format. These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format. 

+
+
Definition at line 60 of file arm_scale_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
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+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_scale_q7 (q7_t *  pSrc, 
q7_t  scaleFract, 
int8_t  shift, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Multiplies a Q7 vector by a scalar. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]scaleFractfractional portion of the scale value 
[in]shiftnumber of bits to shift the result by 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The input data *pSrc and scaleFract are in 1.7 format. These are multiplied to yield a 2.14 intermediate result and this is shifted with saturation to 1.7 format. 

+
+
Definition at line 59 of file arm_scale_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__shift.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__shift.html
new file mode 100644
index 000000000..e6a73c1ca
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__shift.html
@@ -0,0 +1,250 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Shift
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Shift

+
+[Basic Math Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_shift_q31 (q31_t *pSrc, int8_t shiftBits, q31_t *pDst, uint32_t blockSize)
void arm_shift_q15 (q15_t *pSrc, int8_t shiftBits, q15_t *pDst, uint32_t blockSize)
void arm_shift_q7 (q7_t *pSrc, int8_t shiftBits, q7_t *pDst, uint32_t blockSize)

+
Detailed Description

+
Shifts the elements of a fixed-point vector by a specified number of bits. There are separate functions for Q7, Q15, and Q31 data types. The underlying algorithm used is:

+
   
+     pDst[n] = pSrc[n] << shift,   0 <= n < blockSize.   
+ 
If shift is positive then the elements of the vector are shifted to the left. If shift is negative then the elements of the vector are shifted to the right. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
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+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_shift_q31 (q31_t *  pSrc, 
int8_t  shiftBits, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Shifts the elements of a Q31 vector a specified number of bits. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]shiftBitsnumber of bits to shift. A positive value shifts left; a negative value shifts right. 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. 

+
+
Definition at line 73 of file arm_shift_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
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+        
+        
+          
+          
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+          
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+        
+          
+          
+          
+        
+      
void arm_shift_q15 (q15_t *  pSrc, 
int8_t  shiftBits, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Shifts the elements of a Q15 vector a specified number of bits. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]shiftBitsnumber of bits to shift. A positive value shifts left; a negative value shifts right. 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 

+
+
Definition at line 58 of file arm_shift_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
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+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_shift_q7 (q7_t *  pSrc, 
int8_t  shiftBits, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Shifts the elements of a Q7 vector a specified number of bits. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]shiftBitsnumber of bits to shift. A positive value shifts left; a negative value shifts right. 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q7 range [0x8 0x7F] will be saturated. 

+
+
Definition at line 59 of file arm_shift_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__sin.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__sin.html
new file mode 100644
index 000000000..8e1a751ad
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__sin.html
@@ -0,0 +1,261 @@
+
+
+
+
+CMSIS DSP Software Library: Sine
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
Sine

+
+[Fast Math Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+
+

+Functions
float32_t arm_sin_f32 (float32_t x)
q31_t arm_sin_q31 (q31_t x)
q15_t arm_sin_q15 (q15_t x)

+Variables
static const float32_t sinTable [259]
static const q31_t sinTableQ31 [259]
static const q15_t sinTableQ15 [259]

+
Detailed Description

+
Computes the trigonometric sine function using a combination of table lookup and cubic interpolation. There are separate functions for Q15, Q31, and floating-point data types. The input to the floating-point version is in radians while the fixed-point Q15 and Q31 have a scaled input with the range [0 1) mapping to [0 2*pi).

+
The implementation is based on table lookup using 256 values together with cubic interpolation. The steps used are:

+
    
+
  1. Calculation of the nearest integer table index
    2. 
+
  2. Fetch the four table values a, b, c, and d
    3. 
+
  3. Compute the fractional portion (fract) of the table index.
    4. 
+
  4. Calculation of wa, wb, wc, wd
    5. 
+
  5. The final result equals a*wa + b*wb + c*wc + d*wd
    6. 
+

+
where 

+
   
+    a=Table[index-1];   
+    b=Table[index+0];   
+    c=Table[index+1];   
+    d=Table[index+2];   
+ 
 and 

+
   
+    wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;   
+    wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;   
+    wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;   
+    wd=(1/6)*fract.^3 - (1/6)*fract;   
+ 
 
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
float32_t arm_sin_f32 (float32_t  x )

+

+

+
+
Fast approximation to the trigonometric sine function for floating-point data. 

+
Parameters:

+  
+    
+  
[in]xinput value in radians. 

+  

+

+
Returns:
sin(x). 

+
Examples: 
arm_linear_interp_example_f32.c, and arm_sin_cos_example_f32.c.

+

+
Definition at line 195 of file arm_sin_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
q31_t arm_sin_q31 (q31_t  x )

+

+

+
+
Fast approximation to the trigonometric sine function for Q31 data. 

+
Parameters:

+  
+    
+  
[in]xScaled input value in radians. 

+  

+

+
Returns:
sin(x).

+
The Q31 input value is in the range [0 +1) and is mapped to a radian value in the range [0 2*pi). 

+
+
Definition at line 136 of file arm_sin_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
q15_t arm_sin_q15 (q15_t  x )

+

+

+
+
Fast approximation to the trigonometric sine function for Q15 data. 

+
Parameters:

+  
+    
+  
[in]xScaled input value in radians. 

+  

+

+
Returns:
sin(x).

+
The Q15 input value is in the range [0 +1) and is mapped to a radian value in the range [0 2*pi). 

+
+
Definition at line 106 of file arm_sin_q15.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float32_t sinTable[259] [static]

+

+

+
Example code for Generation of Floating-point Sin Table: tableSize = 256; 
for(n = -1; n < (tableSize + 1); n++)   
+ {   
+	sinTable[n+1]=sin(2*pi*n/tableSize);   
+ }
 

+
where pi value is 3.14159265358979 

+
+
Definition at line 88 of file arm_sin_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t sinTableQ31[259] [static]

+

+

+
Tables generated are in Q31(1.31 Fixed point format) Generation of sin values in floating point: 
tableSize = 256;     
+ for(n = -1; n < (tableSize + 1); n++)   
+ {   
+	sinTable[n+1]= sin(2*pi*n/tableSize);   
+ } 
 where pi value is 3.14159265358979 

+
Convert Floating point to Q31(Fixed point): (sinTable[i] * pow(2, 31)) 

+
rounding to nearest integer is done sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5); 

+
+
Definition at line 59 of file arm_sin_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t sinTableQ15[259] [static]

+

+

+
Example code for Generation of Q15 Sin Table: 

+
tableSize = 256;   
+ for(n = -1; n < (tableSize + 1); n++)   
+ {   
+	sinTable[n+1]=sin(2*pi*n/tableSize);   
+ } 
 where pi value is 3.14159265358979 

+
Convert Floating point to Q15(Fixed point): (sinTable[i] * pow(2, 15)) 

+
rounding to nearest integer is done sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5); 

+
+
Definition at line 61 of file arm_sin_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__variance.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__variance.html
new file mode 100644
index 000000000..478f25ab3
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/group__variance.html
@@ -0,0 +1,228 @@
+
+
+
+
+CMSIS DSP Software Library: Variance
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Variance

+
+[Statistics Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_var_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
void arm_var_q31 (q31_t *pSrc, uint32_t blockSize, q63_t *pResult)
void arm_var_q15 (q15_t *pSrc, uint32_t blockSize, q31_t *pResult)

+
Detailed Description

+
Calculates the variance of the elements in the input vector. The underlying algorithm is used:

+
   
+ 	Result = (sumOfSquares - sum2 / blockSize) / (blockSize - 1)
	   where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]
	                   sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]  
+ 
There are separate functions for floating point, Q31, and Q15 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+          
+        
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+          
+        
+      
void arm_var_f32 (float32_t *  pSrc, 
uint32_t  blockSize, 
float32_t *  pResult 
)

+

+

+
+
Variance of the elements of a floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultvariance value returned here 

+  

+

+
Returns:
none. 

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 69 of file arm_var_f32.c.

+
+

+

+
+

+

+      
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+        
+      
void arm_var_q31 (q31_t *  pSrc, 
uint32_t  blockSize, 
q63_t *  pResult 
)

+

+

+
+
Variance of the elements of a Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultvariance value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using an internal 64-bit accumulator. The input is represented in 1.31 format, and intermediate multiplication yields a 2.62 format. The accumulator maintains full precision of the intermediate multiplication results, but provides only a single guard bit. There is no saturation on intermediate additions. If the accumulator overflows it wraps around and distorts the result. In order to avoid overflows completely the input signal must be scaled down by log2(blockSize) bits, as a total of blockSize additions are performed internally. Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value. 

+
+
Definition at line 66 of file arm_var_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
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+          
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+          
+          
+        
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+        
+        
+          
+          
+          
+        
+      
void arm_var_q15 (q15_t *  pSrc, 
uint32_t  blockSize, 
q31_t *  pResult 
)

+

+

+
+
Variance of the elements of a Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultvariance value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 64-bit internal accumulator. The input is represented in 1.15 format. Intermediate multiplication yields a 2.30 format, and this result is added without saturation to a 64-bit accumulator in 34.30 format. With 33 guard bits in the accumulator, there is no risk of overflow, and the full precision of the intermediate multiplication is preserved. Finally, the 34.30 result is truncated to 34.15 format by discarding the lower 15 bits, and then saturated to yield a result in 1.15 format. 

+
+
Definition at line 64 of file arm_var_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/index.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/index.html
new file mode 100644
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--- /dev/null
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@@ -0,0 +1,124 @@
+
+
+
+
+CMSIS DSP Software Library: CMSIS DSP Software Library
+
+
+
+
+
+
+
+
+
+

+  

+
CMSIS DSP Software Library 
  

+

+

+
Version1.0.10 
Introduction

+
This user manual describes the CMSIS DSP software library, a suite of common signal processing functions for use on Cortex-M processor based devices.

+
The library is divided into a number of modules each covering a specific category:

+
    
+
  • Basic math functions
    • 
+
  • Fast math functions
    • 
+
  • Complex math functions
    • 
+
  • Filters
    • 
+
  • Matrix functions
    • 
+
  • Transforms
    • 
+
  • Motor control functions
    • 
+
  • Statistical functions
    • 
+
  • Support functions
    • 
+
  • Interpolation functions
    • 
+

+
The library has separate functions for operating on 8-bit integers, 16-bit integers, 32-bit integer and 32-bit floating-point values.

+
Processor Support

+
The library is completely written in C and is fully CMSIS compliant. High performance is achieved through maximum use of Cortex-M4 intrinsics.

+
The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor, with the DSP intrinsics being emulated through software.

+
Toolchain Support

+
The library has been developed and tested with MDK-ARM version 4.21. The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.

+
Using the Library

+
The library installer contains prebuilt versions of the libraries in the Lib folder.

+
    
+
  • arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
    • 
+
  • arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
    • 
+
  • arm_cortexM4l_math.lib (Little endian on Cortex-M4)
    • 
+
  • arm_cortexM4b_math.lib (Big endian on Cortex-M4)
    • 
+
  • arm_cortexM3l_math.lib (Little endian on Cortex-M3)
    • 
+
  • arm_cortexM3b_math.lib (Big endian on Cortex-M3)
    • 
+
  • arm_cortexM0l_math.lib (Little endian on Cortex-M0)
    • 
+
  • arm_cortexM0b_math.lib (Big endian on Cortex-M3)
    • 
+

+
The library functions are declared in the public file arm_math.h which is placed in the Include folder. Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single public header file  arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or ARM_MATH_CM0 depending on the target processor in the application.

+
Examples

+
The library ships with a number of examples which demonstrate how to use the library functions.

+
Building the Library

+
The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS folder.

+
    
+
  • arm_cortexM0b_math.uvproj
    • 
+
  • arm_cortexM0l_math.uvproj
    • 
+
  • arm_cortexM3b_math.uvproj
    • 
+
  • arm_cortexM3l_math.uvproj
    • 
+
  • arm_cortexM4b_math.uvproj
    • 
+
  • arm_cortexM4l_math.uvproj
    • 
+
  • arm_cortexM4bf_math.uvproj
    • 
+
  • arm_cortexM4lf_math.uvproj
    • 
+

+
Each library project have differant pre-processor macros.

+
ARM_MATH_CMx: Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target and ARM_MATH_CM0 for building library on cortex-M0 target.

+
ARM_MATH_BIG_ENDIAN: Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.

+
ARM_MATH_MATRIX_CHECK: Define macro for checking on the input and output sizes of matrices

+
ARM_MATH_ROUNDING: Define macro for rounding on support functions

+
__FPU_PRESENT: Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries

+
The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above.

+
Copyright Notice

+
Copyright (C) 2010 ARM Limited. All rights reserved. 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/installdox b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/installdox
new file mode 100644
index 000000000..2697a8177
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/installdox
@@ -0,0 +1,117 @@
+#!/usr/bin/perl
+
+%subst = ( );
+$quiet   = 0;
+
+if (open(F,"search.cfg"))
+{
+  $_= ; s/[ \t\n]*$//g ; $subst{"_doc"} = $_;
+  $_= ; s/[ \t\n]*$//g ; $subst{"_cgi"} = $_;
+}
+
+while ( @ARGV ) {
+  $_ = shift @ARGV;
+  if ( s/^-// ) {
+    if ( /^l(.*)/ ) {
+      $v = ($1 eq "") ? shift @ARGV : $1;
+      ($v =~ /\/$/) || ($v .= "/");
+      $_ = $v;
+      if ( /(.+)\@(.+)/ ) {
+        if ( exists $subst{$1} ) {
+          $subst{$1} = $2;
+        } else {
+          print STDERR "Unknown tag file $1 given with option -l\n";
+          &usage();
+        }
+      } else {
+        print STDERR "Argument $_ is invalid for option -l\n";
+        &usage();
+      }
+    }
+    elsif ( /^q/ ) {
+      $quiet = 1;
+    }
+    elsif ( /^\?|^h/ ) {
+      &usage();
+    }
+    else {
+      print STDERR "Illegal option -$_\n";
+      &usage();
+    }
+  }
+  else {
+    push (@files, $_ );
+  }
+}
+
+foreach $sub (keys %subst)
+{
+  if ( $subst{$sub} eq "" ) 
+  {
+    print STDERR "No substitute given for tag file `$sub'\n";
+    &usage();
+  }
+  elsif ( ! $quiet && $sub ne "_doc" && $sub ne "_cgi" )
+  {
+    print "Substituting $subst{$sub} for each occurrence of tag file $sub\n"; 
+  }
+}
+
+if ( ! @files ) {
+  if (opendir(D,".")) {
+    foreach $file ( readdir(D) ) {
+      $match = ".html";
+      next if ( $file =~ /^\.\.?$/ );
+      ($file =~ /$match/) && (push @files, $file);
+      ($file =~ "tree.js") && (push @files, $file);
+    }
+    closedir(D);
+  }
+}
+
+if ( ! @files ) {
+  print STDERR "Warning: No input files given and none found!\n";
+}
+
+foreach $f (@files)
+{
+  if ( ! $quiet ) {
+    print "Editing: $f...\n";
+  }
+  $oldf = $f;
+  $f   .= ".bak";
+  unless (rename $oldf,$f) {
+    print STDERR "Error: cannot rename file $oldf\n";
+    exit 1;
+  }
+  if (open(F,"<$f")) {
+    unless (open(G,">$oldf")) {
+      print STDERR "Error: opening file $oldf for writing\n";
+      exit 1;
+    }
+    if ($oldf ne "tree.js") {
+      while () {
+        s/doxygen\=\"([^ \"\:\t\>\<]*)\:([^ \"\t\>\<]*)\" (href|src)=\"\2/doxygen\=\"$1:$subst{$1}\" \3=\"$subst{$1}/g;
+        print G "$_";
+      }
+    }
+    else {
+      while () {
+        s/\"([^ \"\:\t\>\<]*)\:([^ \"\t\>\<]*)\", \"\2/\"$1:$subst{$1}\" ,\"$subst{$1}/g;
+        print G "$_";
+      }
+    }
+  } 
+  else {
+    print STDERR "Warning file $f does not exist\n";
+  }
+  unlink $f;
+}
+
+sub usage {
+  print STDERR "Usage: installdox [options] [html-file [html-file ...]]\n";
+  print STDERR "Options:\n";
+  print STDERR "     -l tagfile\@linkName   tag file + URL or directory \n";
+  print STDERR "     -q                    Quiet mode\n\n";
+  exit 1;
+}
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/linearInterpExampleMethod1.gif b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/linearInterpExampleMethod1.gif
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/matrixExample.gif b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/matrixExample.gif
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/modules.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/modules.html
new file mode 100644
index 000000000..cf34dd6a7
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/modules.html
@@ -0,0 +1,176 @@
+
+
+
+
+CMSIS DSP Software Library: Module Index
+
+
+
+
+
+
+
+
+
+

+  

+
Modules
  

+

+

+Here is a list of all modules:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/nav_f.png b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/nav_f.png
new file mode 100644
index 000000000..1b07a1620
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/nav_h.png b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/nav_h.png
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/open.png b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/open.png
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/park.gif b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/park.gif
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/parkFormula.gif b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/parkFormula.gif
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/parkInvFormula.gif b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/parkInvFormula.gif
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_5f.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_5f.html
new file mode 100644
index 000000000..8d75ea27c
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_5f.html
@@ -0,0 +1,38 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  __CMSIS_GENERIC
+  arm_math.h
+ 

+

+

+ 

+  __PACKq7
+  arm_math.h
+ 

+

+

+ 

+  __SIMD32
+  arm_math.h
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_61.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_61.html
new file mode 100644
index 000000000..5ff0deddf
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_61.html
@@ -0,0 +1,4102 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
+
+

+ 

+  A_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  Ak
+  arm_convolution_example_f32.c
+ 

+

+
+

+ 

+  arm_abs_f32.c
+ 

+

+
+

+ 

+  arm_abs_q15.c
+ 

+

+
+

+ 

+  arm_abs_q31.c
+ 

+

+
+

+ 

+  arm_abs_q7.c
+ 

+

+
+

+ 

+  arm_add_f32.c
+ 

+

+
+

+ 

+  arm_add_q15.c
+ 

+

+
+

+ 

+  arm_add_q31.c
+ 

+

+
+

+ 

+  arm_add_q7.c
+ 

+

+

+ 

+  arm_bilinear_interp_f32
+  arm_math.h
+ 

+

+
+
+
+
+

+ 

+  arm_bilinear_interp_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_bilinear_interp_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_bilinear_interp_q7
+  arm_math.h
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
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+
+
+
+
+
+
+
+
+

+ 

+  arm_circularRead_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_circularRead_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_circularRead_q7
+  arm_math.h
+ 

+

+

+ 

+  arm_circularWrite_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_circularWrite_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_circularWrite_q7
+  arm_math.h
+ 

+

+

+ 

+  arm_clarke_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_clarke_q31
+  arm_math.h
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_conv_q7.c
+ 

+

+
+
+
+
+
+
+
+
+

+ 

+  arm_copy_q7.c
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_cos_f32.c
+ 

+

+
+

+ 

+  arm_cos_q15.c
+ 

+

+
+

+ 

+  arm_cos_q31.c
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_fill_q7.c
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_fir_f32.c
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+

+ 

+  arm_fir_q15.c
+ 

+

+
+

+ 

+  arm_fir_q31.c
+ 

+

+
+

+ 

+  arm_fir_q7.c
+ 

+

+
+
+
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+
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+
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+
+
+
+
+
+
+
+

+ 

+  arm_inv_clarke_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_inv_clarke_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_inv_park_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_inv_park_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_linear_interep_table
+  arm_linear_interp_example_f32.c
+ 

+

+
+

+ 

+  arm_linear_interp_f32
+  arm_math.h
+ 

+

+
+

+ 

+  arm_linear_interp_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_linear_interp_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_linear_interp_q7
+  arm_math.h
+ 

+

+
+

+ 

+  arm_lms_f32.c
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_lms_q15.c
+ 

+

+
+

+ 

+  arm_lms_q31.c
+ 

+

+
+
+
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+
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+
+
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+
+
+
+
+
+
+
+
+
+

+ 

+  arm_math.h
+ 

+

+

+ 

+  ARM_MATH_ARGUMENT_ERROR
+  arm_math.h
+ 

+

+

+ 

+  ARM_MATH_LENGTH_ERROR
+  arm_math.h
+ 

+

+

+ 

+  ARM_MATH_NANINF
+  arm_math.h
+ 

+

+

+ 

+  ARM_MATH_SINGULAR
+  arm_math.h
+ 

+

+

+ 

+  ARM_MATH_SIZE_MISMATCH
+  arm_math.h
+ 

+

+

+ 

+  ARM_MATH_SUCCESS
+  arm_math.h
+ 

+

+

+ 

+  ARM_MATH_TEST_FAILURE
+  arm_math.h
+ 

+

+
+
+
+
+
+

+ 

+  arm_max_f32.c
+ 

+

+
+

+ 

+  arm_max_q15.c
+ 

+

+
+

+ 

+  arm_max_q31.c
+ 

+

+
+

+ 

+  arm_max_q7.c
+ 

+

+
+
+
+
+
+
+
+

+ 

+  arm_mean_q7.c
+ 

+

+
+

+ 

+  arm_min_f32.c
+ 

+

+
+

+ 

+  arm_min_q15.c
+ 

+

+
+

+ 

+  arm_min_q31.c
+ 

+

+
+

+ 

+  arm_min_q7.c
+ 

+

+
+
+
+
+
+
+
+

+ 

+  arm_mult_q7.c
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_park_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_park_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_pid_f32
+  arm_math.h
+ 

+

+
+
+
+
+
+
+
+
+
+

+ 

+  arm_pid_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_pid_q31
+  arm_math.h
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_recip_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_recip_q31
+  arm_math.h
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

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+ 

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+ 

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+ 

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+

+ 

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+
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+
+
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+ 

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+ 

+

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+ 

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+ 

+

+
+

+ 

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+ 

+

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+ 

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+  arm_rfft_f32.c
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+

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+  arm_rfft_q15.c
+ 

+

+

+ 

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+  arm_rfft_q31.c
+ 

+

+

+ 

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+  arm_rfft_f32.c
+ 

+

+

+ 

+  arm_split_rifft_q15
+  arm_rfft_q15.c
+ 

+

+

+ 

+  arm_split_rifft_q31
+  arm_rfft_q31.c
+ 

+

+

+ 

+  arm_sqrt_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_sqrt_q15
+  arm_sqrt_q15.c
+ 

+

+
+

+ 

+  arm_sqrt_q31
+  arm_sqrt_q31.c
+ 

+

+
+

+ 

+  arm_status
+  arm_math.h
+ 

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+
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+ 

+  arm_std_f32.c
+ 

+

+
+

+ 

+  arm_std_q15.c
+ 

+

+
+

+ 

+  arm_std_q31.c
+ 

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+
+

+ 

+  arm_sub_f32.c
+ 

+

+
+

+ 

+  arm_sub_q15.c
+ 

+

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+

+ 

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+

+ 

+  arm_sub_q7.c
+ 

+

+
+

+ 

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+ 

+

+
+

+ 

+  arm_var_q15.c
+ 

+

+
+

+ 

+  arm_var_q31.c
+ 

+

+
+

+ 

+  armBitRevTable
+  arm_common_tables.c
+ 

+

+

+ 

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+  arm_common_tables.c
+ 

+

+

+ 

+  armRecipTableQ31
+  arm_common_tables.c
+ 

+

+

+ 

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+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  ATMA_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  ATMAI_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  AxB
+  arm_convolution_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_62.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_62.html
new file mode 100644
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+
+
+
+
+
+
+
+

+
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+

+ 

+  B_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

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+  arm_graphic_equalizer_example_q31.c
+ 

+

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+ 

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+ 

+

+

+ 

+  biquadStateBand3Q31
+  arm_graphic_equalizer_example_q31.c
+ 

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+

+ 

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+  arm_graphic_equalizer_example_q31.c
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+ 

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+  arm_graphic_equalizer_example_q31.c
+ 

+

+
+
+
+

+ 

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+  arm_convolution_example_f32.c
+ 

+

+

+ 

+  BLOCK_SIZE
+  arm_fir_example_f32.c
+ 

+

+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_63.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_63.html
new file mode 100644
index 000000000..94d9ae9fa
--- /dev/null
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@@ -0,0 +1,140 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

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+  arm_math.h
+ 

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+  arm_math.h
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+  arm_math.h
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+ 

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+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  cos_factors_128
+  arm_dct4_init_f32.c
+ 

+

+

+ 

+  cos_factors_2048
+  arm_dct4_init_f32.c
+ 

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+ 

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+  arm_dct4_init_f32.c
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+  arm_dct4_init_q15.c
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+  arm_dct4_init_q15.c
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+  arm_dct4_init_q15.c
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+  arm_dct4_init_q31.c
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+  arm_dct4_init_q31.c
+ 

+

+

+ 

+  cos_factorsQ31_512
+  arm_dct4_init_q31.c
+ 

+

+

+ 

+  cosOutput
+  arm_sin_cos_example_f32.c
+ 

+

+

+ 

+  cosSquareOutput
+  arm_sin_cos_example_f32.c
+ 

+

+
+

+ 

+  cosTableQ15
+  arm_cos_q15.c
+ 

+

+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_64.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_64.html
new file mode 100644
index 000000000..f57088be7
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@@ -0,0 +1,61 @@
+
+
+
+
+
+
+
+

+
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+
+

+ 

+  DELTA_COEFF
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  DELTA_ERROR
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

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+  arm_math.h
+ 

+

+

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+  DELTA_Q31
+  arm_math.h
+ 

+

+

+ 

+  doBitReverse
+  arm_fft_bin_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_65.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_65.html
new file mode 100644
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+
+
+
+
+
+
+
+

+
Loading...

+
+

+ 

+  err_signal
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  errOutput
+  arm_signal_converge_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_66.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_66.html
new file mode 100644
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--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_66.html
@@ -0,0 +1,89 @@
+
+
+
+
+
+
+
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+
Loading...

+
+
+
+

+ 

+  fftSize
+  arm_fft_bin_example_f32.c
+ 

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+

+ 

+  FIRCoeff_f32
+  arm_signal_converge_example_f32.c
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+ 

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+  arm_fir_example_f32.c
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+

+ 

+  float32_t
+  arm_math.h
+ 

+

+

+ 

+  float64_t
+  arm_math.h
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_67.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_67.html
new file mode 100644
index 000000000..581840676
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_67.html
@@ -0,0 +1,32 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  gainDB
+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  getinput
+  arm_signal_converge_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_69.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_69.html
new file mode 100644
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--- /dev/null
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+
+
+
+
+
+
+
+

+
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+
+
+

+ 

+  INDEX_MASK
+  arm_math.h
+ 

+

+

+ 

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+  arm_math.h
+ 

+

+

+ 

+  inputQ31
+  arm_graphic_equalizer_example_q31.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_6b.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_6b.html
new file mode 100644
index 000000000..286eb6dbf
--- /dev/null
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+
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+
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+
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_6c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_6c.html
new file mode 100644
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--- /dev/null
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+
+
+
+
+
+
+
+

+
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+
+

+ 

+  lmsNorm_instance
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  lmsNormCoeff_f32
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  lmsStateF32
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  LPF_instance
+  arm_signal_converge_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_6d.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_6d.html
new file mode 100644
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--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_6d.html
@@ -0,0 +1,114 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
+
+

+ 

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+  arm_class_marks_example_f32.c
+ 

+

+
+

+ 

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+ 

+

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+  arm_class_marks_example_f32.c
+ 

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+
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+ 

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+  arm_math.h
+ 

+

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+ 

+  multOutput
+  arm_dotproduct_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_6e.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_6e.html
new file mode 100644
index 000000000..c3faa80c6
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_6e.html
@@ -0,0 +1,167 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
+
+

+ 

+  NUM_TAPS
+  arm_fir_example_f32.c
+ 

+

+
+
+

+ 

+  NUMFRAMES
+  arm_signal_converge_example_f32.c
+ 

+

+
+
+
+
+
+

+ 

+  nValues
+  arm_linear_interp_instance_f32
+ 

+

+
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+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_6f.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_6f.html
new file mode 100644
index 000000000..c29c257e0
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_6f.html
@@ -0,0 +1,38 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  onebyfftLen
+  arm_cfft_radix4_instance_f32
+ 

+

+

+ 

+  outLen
+  arm_convolution_example_f32.c
+ 

+

+

+ 

+  outputQ31
+  arm_graphic_equalizer_example_q31.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_70.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_70.html
new file mode 100644
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--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_70.html
@@ -0,0 +1,250 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
+
+
+
+
+

+ 

+  PI
+  arm_math.h
+ 

+

+
+
+
+
+
+
+
+
+
+

+ 

+  pYData
+  arm_linear_interp_instance_f32
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_71.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_71.html
new file mode 100644
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--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_71.html
@@ -0,0 +1,44 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  q15_t
+  arm_math.h
+ 

+

+

+ 

+  q31_t
+  arm_math.h
+ 

+

+

+ 

+  q63_t
+  arm_math.h
+ 

+

+

+ 

+  q7_t
+  arm_math.h
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_72.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_72.html
new file mode 100644
index 000000000..ee66bb6e4
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_72.html
@@ -0,0 +1,89 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  realCoefA
+  arm_rfft_init_f32.c
+ 

+

+

+ 

+  realCoefAQ15
+  arm_rfft_init_q15.c
+ 

+

+

+ 

+  realCoefAQ31
+  arm_rfft_init_q31.c
+ 

+

+

+ 

+  realCoefB
+  arm_rfft_init_f32.c
+ 

+

+

+ 

+  realCoefBQ15
+  arm_rfft_init_q15.c
+ 

+

+

+ 

+  realCoefBQ31
+  arm_rfft_init_q31.c
+ 

+

+
+

+ 

+  refDotProdOut
+  arm_dotproduct_example_f32.c
+ 

+

+

+ 

+  refIndex
+  arm_fft_bin_example_f32.c
+ 

+

+

+ 

+  refOutput
+  arm_fir_example_f32.c
+ 

+

+

+ 

+  refVarianceOut
+  arm_variance_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_73.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_73.html
new file mode 100644
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--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_73.html
@@ -0,0 +1,164 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  sinOutput
+  arm_sin_cos_example_f32.c
+ 

+

+

+ 

+  sinSquareOutput
+  arm_sin_cos_example_f32.c
+ 

+

+
+

+ 

+  sinTableQ15
+  arm_sin_q15.c
+ 

+

+
+
+

+ 

+  snr1
+  arm_linear_interp_example_f32.c
+ 

+

+

+ 

+  snr2
+  arm_linear_interp_example_f32.c
+ 

+

+
+
+

+ 

+  srcA_buf_f32
+  arm_dotproduct_example_f32.c
+ 

+

+

+ 

+  srcALen
+  arm_convolution_example_f32.c
+ 

+

+

+ 

+  srcB_buf_f32
+  arm_dotproduct_example_f32.c
+ 

+

+

+ 

+  srcBLen
+  arm_convolution_example_f32.c
+ 

+

+
+
+
+

+ 

+  std
+  arm_class_marks_example_f32.c
+ 

+

+

+ 

+  student_num
+  arm_class_marks_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_74.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_74.html
new file mode 100644
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--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_74.html
@@ -0,0 +1,201 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  TABLE_SIZE
+  arm_math.h
+ 

+

+

+ 

+  TABLE_SPACING_Q15
+  arm_math.h
+ 

+

+

+ 

+  TABLE_SPACING_Q31
+  arm_math.h
+ 

+

+
+

+ 

+  test_signal_converge
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  test_signal_converge_example
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  testIndex
+  arm_fft_bin_example_f32.c
+ 

+

+
+

+ 

+  testInput_f32_10khz
+  arm_fft_bin_example_f32.c
+ 

+

+

+ 

+  testInput_f32_1kHz_15kHz
+  arm_fir_example_f32.c
+ 

+

+

+ 

+  testInputA_f32
+  arm_convolution_example_f32.c
+ 

+

+

+ 

+  testInputB_f32
+  arm_convolution_example_f32.c
+ 

+

+

+ 

+  testInputSin_f32
+  arm_linear_interp_example_f32.c
+ 

+

+

+ 

+  TESTLENGTH
+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  testLinIntOutput
+  arm_linear_interp_example_f32.c
+ 

+

+

+ 

+  testMarks_f32
+  arm_class_marks_example_f32.c
+ 

+

+
+
+

+ 

+  testRefSinOutput32_f32
+  arm_linear_interp_example_f32.c
+ 

+

+

+ 

+  testUnity_f32
+  arm_class_marks_example_f32.c
+ 

+

+
+
+

+ 

+  twiddleCoef
+  arm_cfft_radix4_init_f32.c
+ 

+

+

+ 

+  twiddleCoefQ15
+  arm_cfft_radix4_init_q15.c
+ 

+

+

+ 

+  twiddleCoefQ31
+  arm_cfft_radix4_init_q31.c
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_75.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_75.html
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+
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+ 

+  USE_STATIC_INIT
+  arm_class_marks_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_76.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_76.html
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+
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+ 

+  var
+  arm_class_marks_example_f32.c
+ 

+

+
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+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_77.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_77.html
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+
+
+
+
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+

+
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+

+ 

+  Weights_128
+  arm_dct4_init_f32.c
+ 

+

+

+ 

+  Weights_2048
+  arm_dct4_init_f32.c
+ 

+

+

+ 

+  Weights_512
+  arm_dct4_init_f32.c
+ 

+

+

+ 

+  WeightsQ15_128
+  arm_dct4_init_q15.c
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+

+

+ 

+  WeightsQ15_2048
+  arm_dct4_init_q15.c
+ 

+

+

+ 

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+ 

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+

+ 

+  WeightsQ31_128
+  arm_dct4_init_q31.c
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+  arm_dct4_init_q31.c
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+

+

+ 

+  WeightsQ31_512
+  arm_dct4_init_q31.c
+ 

+

+
+
+
+
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+
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+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_78.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/all_78.html
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+
+
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+

+
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+
+

+ 

+  x1
+  arm_linear_interp_instance_f32
+ 

+

+

+ 

+  X_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  xRef_f32
+  arm_matrix_example_f32.c
+ 

+

+
+
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+
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+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/classes_61.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/classes_61.html
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+
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+

+ 

+  __CMSIS_GENERIC
+  arm_math.h
+ 

+

+

+ 

+  __PACKq7
+  arm_math.h
+ 

+

+

+ 

+  __SIMD32
+  arm_math.h
+ 

+

+
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+
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+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/defines_62.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/defines_62.html
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+

+
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+

+ 

+  BLOCK_SIZE
+  arm_fir_example_f32.c
+ 

+

+
+
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+
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+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/defines_64.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/defines_64.html
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+
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+

+
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+
+

+ 

+  DELTA_COEFF
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  DELTA_ERROR
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  DELTA_Q15
+  arm_math.h
+ 

+

+

+ 

+  DELTA_Q31
+  arm_math.h
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/defines_69.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/defines_69.html
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+
+
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+

+
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+

+ 

+  INDEX_MASK
+  arm_math.h
+ 

+

+

+ 

+  INPUT_SPACING
+  arm_math.h
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/defines_6d.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/defines_6d.html
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+
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+ 

+  MU
+  arm_signal_converge_example_f32.c
+ 

+

+
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+
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+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/defines_6e.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/defines_6e.html
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+
+
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+

+
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+

+ 

+  NUM_TAPS
+  arm_fir_example_f32.c
+ 

+

+

+ 

+  NUMBLOCKS
+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  NUMFRAMES
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  NUMSTAGES
+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  NUMSTUDENTS
+  arm_class_marks_example_f32.c
+ 

+

+

+ 

+  NUMSUBJECTS
+  arm_class_marks_example_f32.c
+ 

+

+

+ 

+  NUMTAPS
+  arm_signal_converge_example_f32.c
+ 

+

+
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+
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+
+

+
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/defines_70.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/defines_70.html
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+
+
+
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+
+
+

+
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+

+ 

+  PI
+  arm_math.h
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/defines_73.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/defines_73.html
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+
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/defines_74.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/defines_74.html
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+
+
+
+
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+
+
+

+
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+

+ 

+  TABLE_SIZE
+  arm_math.h
+ 

+

+

+ 

+  TABLE_SPACING_Q15
+  arm_math.h
+ 

+

+

+ 

+  TABLE_SPACING_Q31
+  arm_math.h
+ 

+

+
+

+ 

+  TESTLENGTH
+  arm_graphic_equalizer_example_q31.c
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/defines_75.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/defines_75.html
new file mode 100644
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+
+
+
+
+
+
+
+

+
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+

+ 

+  USE_STATIC_INIT
+  arm_class_marks_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/defines_78.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/defines_78.html
new file mode 100644
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+
+
+
+
+
+
+
+

+
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+

+ 

+  XSPACING
+  arm_linear_interp_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/enums_61.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/enums_61.html
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+
+
+
+
+
+
+
+

+
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+

+ 

+  arm_status
+  arm_math.h
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/enumvalues_61.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/enumvalues_61.html
new file mode 100644
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+
+
+
+
+
+
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+

+
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+

+ 

+  ARM_MATH_ARGUMENT_ERROR
+  arm_math.h
+ 

+

+

+ 

+  ARM_MATH_LENGTH_ERROR
+  arm_math.h
+ 

+

+

+ 

+  ARM_MATH_NANINF
+  arm_math.h
+ 

+

+

+ 

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+  arm_math.h
+ 

+

+

+ 

+  ARM_MATH_SIZE_MISMATCH
+  arm_math.h
+ 

+

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+  arm_math.h
+ 

+

+

+ 

+  ARM_MATH_TEST_FAILURE
+  arm_math.h
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/files_61.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/files_61.html
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+
+
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+

+
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+

+ 

+  arm_abs_f32.c
+ 

+

+

+ 

+  arm_abs_q15.c
+ 

+

+

+ 

+  arm_abs_q31.c
+ 

+

+

+ 

+  arm_abs_q7.c
+ 

+

+

+ 

+  arm_add_f32.c
+ 

+

+

+ 

+  arm_add_q15.c
+ 

+

+

+ 

+  arm_add_q31.c
+ 

+

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+  arm_add_q7.c
+ 

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+ 

+

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+ 

+  arm_copy_q7.c
+ 

+

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+ 

+  arm_cos_f32.c
+ 

+

+

+ 

+  arm_cos_q15.c
+ 

+

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+ 

+  arm_cos_q31.c
+ 

+

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+ 

+  arm_fill_q7.c
+ 

+

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+ 

+  arm_fir_f32.c
+ 

+

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+

+ 

+  arm_fir_q15.c
+ 

+

+

+ 

+  arm_fir_q31.c
+ 

+

+

+ 

+  arm_fir_q7.c
+ 

+

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+ 

+  arm_lms_f32.c
+ 

+

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+

+ 

+  arm_lms_q15.c
+ 

+

+

+ 

+  arm_lms_q31.c
+ 

+

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+
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+

+ 

+  arm_math.h
+ 

+

+
+

+ 

+  arm_max_f32.c
+ 

+

+

+ 

+  arm_max_q15.c
+ 

+

+

+ 

+  arm_max_q31.c
+ 

+

+

+ 

+  arm_max_q7.c
+ 

+

+
+
+
+

+ 

+  arm_mean_q7.c
+ 

+

+

+ 

+  arm_min_f32.c
+ 

+

+

+ 

+  arm_min_q15.c
+ 

+

+

+ 

+  arm_min_q31.c
+ 

+

+

+ 

+  arm_min_q7.c
+ 

+

+
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+ 

+  arm_mult_q7.c
+ 

+

+
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+

+ 

+  arm_rms_f32.c
+ 

+

+

+ 

+  arm_rms_q15.c
+ 

+

+

+ 

+  arm_rms_q31.c
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_sin_f32.c
+ 

+

+

+ 

+  arm_sin_q15.c
+ 

+

+

+ 

+  arm_sin_q31.c
+ 

+

+
+
+

+ 

+  arm_std_f32.c
+ 

+

+

+ 

+  arm_std_q15.c
+ 

+

+

+ 

+  arm_std_q31.c
+ 

+

+

+ 

+  arm_sub_f32.c
+ 

+

+

+ 

+  arm_sub_q15.c
+ 

+

+

+ 

+  arm_sub_q31.c
+ 

+

+

+ 

+  arm_sub_q7.c
+ 

+

+

+ 

+  arm_var_f32.c
+ 

+

+

+ 

+  arm_var_q15.c
+ 

+

+

+ 

+  arm_var_q31.c
+ 

+

+
+
Searching...

+
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+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/functions_61.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/functions_61.html
new file mode 100644
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--- /dev/null
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+
+
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+

+
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+
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+ 

+  arm_bilinear_interp_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_bilinear_interp_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_bilinear_interp_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_bilinear_interp_q7
+  arm_math.h
+ 

+

+
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+ 

+  arm_circularRead_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_circularRead_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_circularRead_q7
+  arm_math.h
+ 

+

+

+ 

+  arm_circularWrite_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_circularWrite_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_circularWrite_q7
+  arm_math.h
+ 

+

+

+ 

+  arm_clarke_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_clarke_q31
+  arm_math.h
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_inv_clarke_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_inv_clarke_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_inv_park_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_inv_park_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_linear_interp_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_linear_interp_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_linear_interp_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_linear_interp_q7
+  arm_math.h
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_park_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_park_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_pid_f32
+  arm_math.h
+ 

+

+
+
+
+

+ 

+  arm_pid_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_pid_q31
+  arm_math.h
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_recip_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_recip_q31
+  arm_math.h
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_split_rfft_f32
+  arm_rfft_f32.c
+ 

+

+

+ 

+  arm_split_rfft_q15
+  arm_rfft_q15.c
+ 

+

+

+ 

+  arm_split_rfft_q31
+  arm_rfft_q31.c
+ 

+

+

+ 

+  arm_split_rifft_f32
+  arm_rfft_f32.c
+ 

+

+

+ 

+  arm_split_rifft_q15
+  arm_rfft_q15.c
+ 

+

+

+ 

+  arm_split_rifft_q31
+  arm_rfft_q31.c
+ 

+

+

+ 

+  arm_sqrt_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_sqrt_q15
+  arm_sqrt_q15.c
+ 

+

+

+ 

+  arm_sqrt_q31
+  arm_sqrt_q31.c
+ 

+

+
+
+
+
+
+
+
+
+
+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/functions_63.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/functions_63.html
new file mode 100644
index 000000000..8f7169e08
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/functions_63.html
@@ -0,0 +1,44 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  clip_q31_to_q15
+  arm_math.h
+ 

+

+

+ 

+  clip_q31_to_q7
+  arm_math.h
+ 

+

+

+ 

+  clip_q63_to_q15
+  arm_math.h
+ 

+

+

+ 

+  clip_q63_to_q31
+  arm_math.h
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/functions_67.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/functions_67.html
new file mode 100644
index 000000000..0a70c9ecd
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/functions_67.html
@@ -0,0 +1,26 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  getinput
+  arm_signal_converge_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/functions_6d.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/functions_6d.html
new file mode 100644
index 000000000..7eb63ba6b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/functions_6d.html
@@ -0,0 +1,44 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+

+ 

+  mult32x64
+  arm_math.h
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/functions_74.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/functions_74.html
new file mode 100644
index 000000000..bf5b59a4b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/functions_74.html
@@ -0,0 +1,32 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  test_signal_converge
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  test_signal_converge_example
+  arm_signal_converge_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/mag_sel.png b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/mag_sel.png
new file mode 100644
index 000000000..81f6040a2
Binary files /dev/null and b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/mag_sel.png differ
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/nomatches.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/nomatches.html
new file mode 100644
index 000000000..b1ded27e9
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/nomatches.html
@@ -0,0 +1,12 @@
+
+
+
+
+
+
+
+

+
No Matches

+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/search.css b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/search.css
new file mode 100644
index 000000000..50249e56d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/search.css
@@ -0,0 +1,240 @@
+/*---------------- Search Box */
+
+#FSearchBox {
+    float: left;
+}
+
+#searchli {
+    float: right;
+    display: block;
+    width: 170px;
+    height: 36px;
+}
+
+#MSearchBox {
+    white-space : nowrap;
+    position: absolute;
+    float: none;
+    display: inline;
+    margin-top: 8px;
+    right: 0px;
+    width: 170px;
+    z-index: 102;
+}
+
+#MSearchBox .left
+{
+    display:block;
+    position:absolute;
+    left:10px;
+    width:20px;
+    height:19px;
+    background:url('search_l.png') no-repeat;
+    background-position:right;
+}
+
+#MSearchSelect {
+    display:block;
+    position:absolute;
+    width:20px;
+    height:19px;
+}
+
+.left #MSearchSelect {
+    left:4px;
+}
+
+.right #MSearchSelect {
+    right:5px;
+}
+
+#MSearchField {
+    display:block;
+    position:absolute;
+    height:19px;
+    background:url('search_m.png') repeat-x;
+    border:none;
+    width:116px;
+    margin-left:20px;
+    padding-left:4px;
+    color: #909090;
+    outline: none;
+    font: 9pt Arial, Verdana, sans-serif;
+}
+
+#FSearchBox #MSearchField {
+    margin-left:15px;
+}
+
+#MSearchBox .right {
+    display:block;
+    position:absolute;
+    right:10px;
+    top:0px;
+    width:20px;
+    height:19px;
+    background:url('search_r.png') no-repeat;
+    background-position:left;
+}
+
+#MSearchClose {
+    display: none;
+    position: absolute;
+    top: 4px;
+    background : none;
+    border: none;
+    margin: 0px 4px 0px 0px;
+    padding: 0px 0px;
+    outline: none;
+}
+
+.left #MSearchClose {
+    left: 6px;
+}
+
+.right #MSearchClose {
+    right: 2px;
+}
+
+.MSearchBoxActive #MSearchField {
+    color: #000000;
+}
+
+/*---------------- Search filter selection */
+
+#MSearchSelectWindow {
+    display: none;
+    position: absolute;
+    left: 0; top: 0;
+    border: 1px solid #90A5CE;
+    background-color: #F9FAFC;
+    z-index: 1;
+    padding-top: 4px;
+    padding-bottom: 4px;
+    -moz-border-radius: 4px;
+    -webkit-border-top-left-radius: 4px;
+    -webkit-border-top-right-radius: 4px;
+    -webkit-border-bottom-left-radius: 4px;
+    -webkit-border-bottom-right-radius: 4px;
+    -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+}
+
+.SelectItem {
+    font: 8pt Arial, Verdana, sans-serif;
+    padding-left:  2px;
+    padding-right: 12px;
+    border: 0px;
+}
+
+span.SelectionMark {
+    margin-right: 4px;
+    font-family: monospace;
+    outline-style: none;
+    text-decoration: none;
+}
+
+a.SelectItem {
+    display: block;
+    outline-style: none;
+    color: #000000; 
+    text-decoration: none;
+    padding-left:   6px;
+    padding-right: 12px;
+}
+
+a.SelectItem:focus,
+a.SelectItem:active {
+    color: #000000; 
+    outline-style: none;
+    text-decoration: none;
+}
+
+a.SelectItem:hover {
+    color: #FFFFFF;
+    background-color: #3D578C;
+    outline-style: none;
+    text-decoration: none;
+    cursor: pointer;
+    display: block;
+}
+
+/*---------------- Search results window */
+
+iframe#MSearchResults {
+    width: 60ex;
+    height: 15em;
+}
+
+#MSearchResultsWindow {
+    display: none;
+    position: absolute;
+    left: 0; top: 0;
+    border: 1px solid #000;
+    background-color: #EEF1F7;
+}
+
+/* ----------------------------------- */
+
+
+#SRIndex {
+    clear:both; 
+    padding-bottom: 15px;
+}
+
+.SREntry {
+    font-size: 10pt;
+    padding-left: 1ex;
+}
+
+.SRPage .SREntry {
+    font-size: 8pt;
+    padding: 1px 5px;
+}
+
+body.SRPage {
+    margin: 5px 2px;
+}
+
+.SRChildren {
+    padding-left: 3ex; padding-bottom: .5em 
+}
+
+.SRPage .SRChildren {
+    display: none;
+}
+
+.SRSymbol {
+    font-weight: bold; 
+    color: #425E97;
+    font-family: Arial, Verdana, sans-serif;
+    text-decoration: none;
+    outline: none;
+}
+
+a.SRScope {
+    display: block;
+    color: #425E97; 
+    font-family: Arial, Verdana, sans-serif;
+    text-decoration: none;
+    outline: none;
+}
+
+a.SRSymbol:focus, a.SRSymbol:active,
+a.SRScope:focus, a.SRScope:active {
+    text-decoration: underline;
+}
+
+.SRPage .SRStatus {
+    padding: 2px 5px;
+    font-size: 8pt;
+    font-style: italic;
+}
+
+.SRResult {
+    display: none;
+}
+
+DIV.searchresults {
+    margin-left: 10px;
+    margin-right: 10px;
+}
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/search.js b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/search.js
new file mode 100644
index 000000000..29a24bd58
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/search.js
@@ -0,0 +1,742 @@
+// Search script generated by doxygen
+// Copyright (C) 2009 by Dimitri van Heesch.
+
+// The code in this file is loosly based on main.js, part of Natural Docs,
+// which is Copyright (C) 2003-2008 Greg Valure
+// Natural Docs is licensed under the GPL.
+
+var indexSectionsWithContent =
+{
+  0: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010111111101011111111111111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  1: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  2: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  3: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101000100000100000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  4: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111101011111101110111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  5: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  6: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  7: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  8: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010010100001000110100111001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
+};
+
+var indexSectionNames =
+{
+  0: "all",
+  1: "classes",
+  2: "files",
+  3: "functions",
+  4: "variables",
+  5: "typedefs",
+  6: "enums",
+  7: "enumvalues",
+  8: "defines"
+};
+
+function convertToId(search)
+{
+  var result = '';
+  for (i=0;i do a search
+    {
+      this.Search();
+    }
+  }
+
+  this.OnSearchSelectKey = function(evt)
+  {
+    var e = (evt) ? evt : window.event; // for IE
+    if (e.keyCode==40 && this.searchIndex0) // Up
+    {
+      this.searchIndex--;
+      this.OnSelectItem(this.searchIndex);
+    }
+    else if (e.keyCode==13 || e.keyCode==27)
+    {
+      this.OnSelectItem(this.searchIndex);
+      this.CloseSelectionWindow();
+      this.DOMSearchField().focus();
+    }
+    return false;
+  }
+
+  // --------- Actions
+
+  // Closes the results window.
+  this.CloseResultsWindow = function()
+  {
+    this.DOMPopupSearchResultsWindow().style.display = 'none';
+    this.DOMSearchClose().style.display = 'none';
+    this.Activate(false);
+  }
+
+  this.CloseSelectionWindow = function()
+  {
+    this.DOMSearchSelectWindow().style.display = 'none';
+  }
+
+  // Performs a search.
+  this.Search = function()
+  {
+    this.keyTimeout = 0;
+
+    // strip leading whitespace
+    var searchValue = this.DOMSearchField().value.replace(/^ +/, "");
+
+    var code = searchValue.toLowerCase().charCodeAt(0);
+    var hexCode;
+    if (code<16) 
+    {
+      hexCode="0"+code.toString(16);
+    }
+    else 
+    {
+      hexCode=code.toString(16);
+    }
+
+    var resultsPage;
+    var resultsPageWithSearch;
+    var hasResultsPage;
+
+    if (indexSectionsWithContent[this.searchIndex].charAt(code) == '1')
+    {
+       resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + '.html';
+       resultsPageWithSearch = resultsPage+'?'+escape(searchValue);
+       hasResultsPage = true;
+    }
+    else // nothing available for this search term
+    {
+       resultsPage = this.resultsPath + '/nomatches.html';
+       resultsPageWithSearch = resultsPage;
+       hasResultsPage = false;
+    }
+
+    window.frames.MSearchResults.location.href = resultsPageWithSearch;  
+    var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow();
+
+    if (domPopupSearchResultsWindow.style.display!='block')
+    {
+       var domSearchBox = this.DOMSearchBox();
+       this.DOMSearchClose().style.display = 'inline';
+       if (this.insideFrame)
+       {
+         var domPopupSearchResults = this.DOMPopupSearchResults();
+         domPopupSearchResultsWindow.style.position = 'relative';
+         domPopupSearchResultsWindow.style.display  = 'block';
+         var width = document.body.clientWidth - 8; // the -8 is for IE :-(
+         domPopupSearchResultsWindow.style.width    = width + 'px';
+         domPopupSearchResults.style.width          = width + 'px';
+       }
+       else
+       {
+         var domPopupSearchResults = this.DOMPopupSearchResults();
+         var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth;
+         var top  = getYPos(domSearchBox) + 20;  // domSearchBox.offsetHeight + 1;
+         domPopupSearchResultsWindow.style.display = 'block';
+         left -= domPopupSearchResults.offsetWidth;
+         domPopupSearchResultsWindow.style.top     = top  + 'px';
+         domPopupSearchResultsWindow.style.left    = left + 'px';
+       }
+    }
+
+    this.lastSearchValue = searchValue;
+    this.lastResultsPage = resultsPage;
+  }
+
+  // -------- Activation Functions
+
+  // Activates or deactivates the search panel, resetting things to 
+  // their default values if necessary. 
+  this.Activate = function(isActive)
+  {
+    if (isActive || // open it
+        this.DOMPopupSearchResultsWindow().style.display == 'block' 
+       )
+    {
+      this.DOMSearchBox().className = 'MSearchBoxActive';
+
+      var searchField = this.DOMSearchField();
+
+      if (searchField.value == this.searchLabel) // clear "Search" term upon entry
+      {  
+        searchField.value = '';  
+        this.searchActive = true;
+      }
+    }
+    else if (!isActive) // directly remove the panel
+    {
+      this.DOMSearchBox().className = 'MSearchBoxInactive';
+      this.DOMSearchField().value   = this.searchLabel;
+      this.searchActive             = false;
+      this.lastSearchValue          = ''
+      this.lastResultsPage          = '';
+    }
+  }
+}
+
+// -----------------------------------------------------------------------
+
+// The class that handles everything on the search results page.
+function SearchResults(name)
+{
+    // The number of matches from the last run of .
+    this.lastMatchCount = 0;
+    this.lastKey = 0;
+    this.repeatOn = false;
+
+    // Toggles the visibility of the passed element ID.
+    this.FindChildElement = function(id)
+    {
+      var parentElement = document.getElementById(id);
+      var element = parentElement.firstChild;
+
+      while (element && element!=parentElement)
+      {
+        if (element.nodeName == 'DIV' && element.className == 'SRChildren')
+        {
+          return element;
+        }
+
+        if (element.nodeName == 'DIV' && element.hasChildNodes())
+        {  
+           element = element.firstChild;  
+        }
+        else if (element.nextSibling)
+        {  
+           element = element.nextSibling;  
+        }
+        else
+        {
+          do
+          {
+            element = element.parentNode;
+          }
+          while (element && element!=parentElement && !element.nextSibling);
+
+          if (element && element!=parentElement)
+          {  
+            element = element.nextSibling;  
+          }
+        }
+      }
+    }
+
+    this.Toggle = function(id)
+    {
+      var element = this.FindChildElement(id);
+      if (element)
+      {
+        if (element.style.display == 'block')
+        {
+          element.style.display = 'none';
+        }
+        else
+        {
+          element.style.display = 'block';
+        }
+      }
+    }
+
+    // Searches for the passed string.  If there is no parameter,
+    // it takes it from the URL query.
+    //
+    // Always returns true, since other documents may try to call it
+    // and that may or may not be possible.
+    this.Search = function(search)
+    {
+      if (!search) // get search word from URL
+      {
+        search = window.location.search;
+        search = search.substring(1);  // Remove the leading '?'
+        search = unescape(search);
+      }
+
+      search = search.replace(/^ +/, ""); // strip leading spaces
+      search = search.replace(/ +$/, ""); // strip trailing spaces
+      search = search.toLowerCase();
+      search = convertToId(search);
+
+      var resultRows = document.getElementsByTagName("div");
+      var matches = 0;
+
+      var i = 0;
+      while (i < resultRows.length)
+      {
+        var row = resultRows.item(i);
+        if (row.className == "SRResult")
+        {
+          var rowMatchName = row.id.toLowerCase();
+          rowMatchName = rowMatchName.replace(/^sr\d*_/, ''); // strip 'sr123_'
+
+          if (search.length<=rowMatchName.length && 
+             rowMatchName.substr(0, search.length)==search)
+          {
+            row.style.display = 'block';
+            matches++;
+          }
+          else
+          {
+            row.style.display = 'none';
+          }
+        }
+        i++;
+      }
+      document.getElementById("Searching").style.display='none';
+      if (matches == 0) // no results
+      {
+        document.getElementById("NoMatches").style.display='block';
+      }
+      else // at least one result
+      {
+        document.getElementById("NoMatches").style.display='none';
+      }
+      this.lastMatchCount = matches;
+      return true;
+    }
+
+    // return the first item with index index or higher that is visible
+    this.NavNext = function(index)
+    {
+      var focusItem;
+      while (1)
+      {
+        var focusName = 'Item'+index;
+        focusItem = document.getElementById(focusName);
+        if (focusItem && focusItem.parentNode.parentNode.style.display=='block')
+        {
+          break;
+        }
+        else if (!focusItem) // last element
+        {
+          break;
+        }
+        focusItem=null;
+        index++;
+      }
+      return focusItem;
+    }
+
+    this.NavPrev = function(index)
+    {
+      var focusItem;
+      while (1)
+      {
+        var focusName = 'Item'+index;
+        focusItem = document.getElementById(focusName);
+        if (focusItem && focusItem.parentNode.parentNode.style.display=='block')
+        {
+          break;
+        }
+        else if (!focusItem) // last element
+        {
+          break;
+        }
+        focusItem=null;
+        index--;
+      }
+      return focusItem;
+    }
+
+    this.ProcessKeys = function(e)
+    {
+      if (e.type == "keydown") 
+      {
+        this.repeatOn = false;
+        this.lastKey = e.keyCode;
+      }
+      else if (e.type == "keypress")
+      {
+        if (!this.repeatOn)
+        {
+          if (this.lastKey) this.repeatOn = true;
+          return false; // ignore first keypress after keydown
+        }
+      }
+      else if (e.type == "keyup")
+      {
+        this.lastKey = 0;
+        this.repeatOn = false;
+      }
+      return this.lastKey!=0;
+    }
+
+    this.Nav = function(evt,itemIndex) 
+    {
+      var e  = (evt) ? evt : window.event; // for IE
+      if (e.keyCode==13) return true;
+      if (!this.ProcessKeys(e)) return false;
+
+      if (this.lastKey==38) // Up
+      {
+        var newIndex = itemIndex-1;
+        var focusItem = this.NavPrev(newIndex);
+        if (focusItem)
+        {
+          var child = this.FindChildElement(focusItem.parentNode.parentNode.id);
+          if (child && child.style.display == 'block') // children visible
+          { 
+            var n=0;
+            var tmpElem;
+            while (1) // search for last child
+            {
+              tmpElem = document.getElementById('Item'+newIndex+'_c'+n);
+              if (tmpElem)
+              {
+                focusItem = tmpElem;
+              }
+              else // found it!
+              {
+                break;
+              }
+              n++;
+            }
+          }
+        }
+        if (focusItem)
+        {
+          focusItem.focus();
+        }
+        else // return focus to search field
+        {
+           parent.document.getElementById("MSearchField").focus();
+        }
+      }
+      else if (this.lastKey==40) // Down
+      {
+        var newIndex = itemIndex+1;
+        var focusItem;
+        var item = document.getElementById('Item'+itemIndex);
+        var elem = this.FindChildElement(item.parentNode.parentNode.id);
+        if (elem && elem.style.display == 'block') // children visible
+        {
+          focusItem = document.getElementById('Item'+itemIndex+'_c0');
+        }
+        if (!focusItem) focusItem = this.NavNext(newIndex);
+        if (focusItem)  focusItem.focus();
+      }
+      else if (this.lastKey==39) // Right
+      {
+        var item = document.getElementById('Item'+itemIndex);
+        var elem = this.FindChildElement(item.parentNode.parentNode.id);
+        if (elem) elem.style.display = 'block';
+      }
+      else if (this.lastKey==37) // Left
+      {
+        var item = document.getElementById('Item'+itemIndex);
+        var elem = this.FindChildElement(item.parentNode.parentNode.id);
+        if (elem) elem.style.display = 'none';
+      }
+      else if (this.lastKey==27) // Escape
+      {
+        parent.searchBox.CloseResultsWindow();
+        parent.document.getElementById("MSearchField").focus();
+      }
+      else if (this.lastKey==13) // Enter
+      {
+        return true;
+      }
+      return false;
+    }
+
+    this.NavChild = function(evt,itemIndex,childIndex)
+    {
+      var e  = (evt) ? evt : window.event; // for IE
+      if (e.keyCode==13) return true;
+      if (!this.ProcessKeys(e)) return false;
+
+      if (this.lastKey==38) // Up
+      {
+        if (childIndex>0)
+        {
+          var newIndex = childIndex-1;
+          document.getElementById('Item'+itemIndex+'_c'+newIndex).focus();
+        }
+        else // already at first child, jump to parent
+        {
+          document.getElementById('Item'+itemIndex).focus();
+        }
+      }
+      else if (this.lastKey==40) // Down
+      {
+        var newIndex = childIndex+1;
+        var elem = document.getElementById('Item'+itemIndex+'_c'+newIndex);
+        if (!elem) // last child, jump to parent next parent
+        {
+          elem = this.NavNext(itemIndex+1);
+        }
+        if (elem)
+        {
+          elem.focus();
+        } 
+      }
+      else if (this.lastKey==27) // Escape
+      {
+        parent.searchBox.CloseResultsWindow();
+        parent.document.getElementById("MSearchField").focus();
+      }
+      else if (this.lastKey==13) // Enter
+      {
+        return true;
+      }
+      return false;
+    }
+}
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/search_l.png b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/search_l.png
new file mode 100644
index 000000000..c872f4da4
Binary files /dev/null and b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/search_l.png differ
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/search_m.png b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/search_m.png
new file mode 100644
index 000000000..b429a16ba
Binary files /dev/null and b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/search_m.png differ
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/search_r.png b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/search_r.png
new file mode 100644
index 000000000..97ee8b439
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/typedefs_66.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/typedefs_66.html
new file mode 100644
index 000000000..3f3d94fd5
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/typedefs_66.html
@@ -0,0 +1,32 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  float32_t
+  arm_math.h
+ 

+

+

+ 

+  float64_t
+  arm_math.h
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/typedefs_71.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/typedefs_71.html
new file mode 100644
index 000000000..c889272b9
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/typedefs_71.html
@@ -0,0 +1,44 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  q15_t
+  arm_math.h
+ 

+

+

+ 

+  q31_t
+  arm_math.h
+ 

+

+

+ 

+  q63_t
+  arm_math.h
+ 

+

+

+ 

+  q7_t
+  arm_math.h
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_61.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_61.html
new file mode 100644
index 000000000..2da279f14
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_61.html
@@ -0,0 +1,109 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
+
+

+ 

+  A_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  Ak
+  arm_convolution_example_f32.c
+ 

+

+

+ 

+  arm_linear_interep_table
+  arm_linear_interp_example_f32.c
+ 

+

+

+ 

+  armBitRevTable
+  arm_common_tables.c
+ 

+

+

+ 

+  armRecipTableQ15
+  arm_common_tables.c
+ 

+

+

+ 

+  armRecipTableQ31
+  arm_common_tables.c
+ 

+

+

+ 

+  AT_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  ATMA_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  ATMAI_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  AxB
+  arm_convolution_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_62.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_62.html
new file mode 100644
index 000000000..edeb3083c
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_62.html
@@ -0,0 +1,102 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  B_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  biquadStateBand1Q31
+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  biquadStateBand2Q31
+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  biquadStateBand3Q31
+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  biquadStateBand4Q31
+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  biquadStateBand5Q31
+  arm_graphic_equalizer_example_q31.c
+ 

+

+
+
+
+

+ 

+  Bk
+  arm_convolution_example_f32.c
+ 

+

+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_63.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_63.html
new file mode 100644
index 000000000..854bab0b1
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_63.html
@@ -0,0 +1,116 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  coeffTable
+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  cos_factors_128
+  arm_dct4_init_f32.c
+ 

+

+

+ 

+  cos_factors_2048
+  arm_dct4_init_f32.c
+ 

+

+

+ 

+  cos_factors_512
+  arm_dct4_init_f32.c
+ 

+

+

+ 

+  cos_factorsQ15_128
+  arm_dct4_init_q15.c
+ 

+

+

+ 

+  cos_factorsQ15_2048
+  arm_dct4_init_q15.c
+ 

+

+

+ 

+  cos_factorsQ15_512
+  arm_dct4_init_q15.c
+ 

+

+

+ 

+  cos_factorsQ31_128
+  arm_dct4_init_q31.c
+ 

+

+

+ 

+  cos_factorsQ31_2048
+  arm_dct4_init_q31.c
+ 

+

+

+ 

+  cos_factorsQ31_512
+  arm_dct4_init_q31.c
+ 

+

+

+ 

+  cosOutput
+  arm_sin_cos_example_f32.c
+ 

+

+

+ 

+  cosSquareOutput
+  arm_sin_cos_example_f32.c
+ 

+

+
+

+ 

+  cosTableQ15
+  arm_cos_q15.c
+ 

+

+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_64.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_64.html
new file mode 100644
index 000000000..7da528e30
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_64.html
@@ -0,0 +1,26 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  doBitReverse
+  arm_fft_bin_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_65.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_65.html
new file mode 100644
index 000000000..c06f61fb4
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_65.html
@@ -0,0 +1,42 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+

+ 

+  err_signal
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  errOutput
+  arm_signal_converge_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_66.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_66.html
new file mode 100644
index 000000000..68114c4fa
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_66.html
@@ -0,0 +1,77 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
+
+

+ 

+  fftSize
+  arm_fft_bin_example_f32.c
+ 

+

+

+ 

+  FIRCoeff_f32
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  firCoeffs32
+  arm_fir_example_f32.c
+ 

+

+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_67.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_67.html
new file mode 100644
index 000000000..e2b59957a
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_67.html
@@ -0,0 +1,26 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  gainDB
+  arm_graphic_equalizer_example_q31.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_69.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_69.html
new file mode 100644
index 000000000..5571299d3
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_69.html
@@ -0,0 +1,47 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
+

+ 

+  inputQ31
+  arm_graphic_equalizer_example_q31.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_6b.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_6b.html
new file mode 100644
index 000000000..286eb6dbf
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_6b.html
@@ -0,0 +1,50 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_6c.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_6c.html
new file mode 100644
index 000000000..7378accbc
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_6c.html
@@ -0,0 +1,54 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+

+ 

+  lmsNorm_instance
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  lmsNormCoeff_f32
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  lmsStateF32
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  LPF_instance
+  arm_signal_converge_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_6d.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_6d.html
new file mode 100644
index 000000000..45f41dae9
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_6d.html
@@ -0,0 +1,78 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+

+ 

+  max_marks
+  arm_class_marks_example_f32.c
+ 

+

+
+

+ 

+  mean
+  arm_class_marks_example_f32.c
+ 

+

+

+ 

+  min_marks
+  arm_class_marks_example_f32.c
+ 

+

+
+

+ 

+  multOutput
+  arm_dotproduct_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_6e.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_6e.html
new file mode 100644
index 000000000..e3578fbce
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_6e.html
@@ -0,0 +1,144 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
+
+

+ 

+  numBlocks
+  arm_fir_example_f32.c
+ 

+

+
+
+
+

+ 

+  numStudents
+  arm_class_marks_example_f32.c
+ 

+

+

+ 

+  numSubjects
+  arm_class_marks_example_f32.c
+ 

+

+
+

+ 

+  nValues
+  arm_linear_interp_instance_f32
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_6f.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_6f.html
new file mode 100644
index 000000000..c29c257e0
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_6f.html
@@ -0,0 +1,38 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  onebyfftLen
+  arm_cfft_radix4_instance_f32
+ 

+

+

+ 

+  outLen
+  arm_convolution_example_f32.c
+ 

+

+

+ 

+  outputQ31
+  arm_graphic_equalizer_example_q31.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_70.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_70.html
new file mode 100644
index 000000000..c2bc27043
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_70.html
@@ -0,0 +1,244 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  pYData
+  arm_linear_interp_instance_f32
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_72.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_72.html
new file mode 100644
index 000000000..ee66bb6e4
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_72.html
@@ -0,0 +1,89 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  realCoefA
+  arm_rfft_init_f32.c
+ 

+

+

+ 

+  realCoefAQ15
+  arm_rfft_init_q15.c
+ 

+

+

+ 

+  realCoefAQ31
+  arm_rfft_init_q31.c
+ 

+

+

+ 

+  realCoefB
+  arm_rfft_init_f32.c
+ 

+

+

+ 

+  realCoefBQ15
+  arm_rfft_init_q15.c
+ 

+

+

+ 

+  realCoefBQ31
+  arm_rfft_init_q31.c
+ 

+

+
+

+ 

+  refDotProdOut
+  arm_dotproduct_example_f32.c
+ 

+

+

+ 

+  refIndex
+  arm_fft_bin_example_f32.c
+ 

+

+

+ 

+  refOutput
+  arm_fir_example_f32.c
+ 

+

+

+ 

+  refVarianceOut
+  arm_variance_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_73.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_73.html
new file mode 100644
index 000000000..de0b2b425
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_73.html
@@ -0,0 +1,145 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  sinOutput
+  arm_sin_cos_example_f32.c
+ 

+

+

+ 

+  sinSquareOutput
+  arm_sin_cos_example_f32.c
+ 

+

+
+

+ 

+  sinTableQ15
+  arm_sin_q15.c
+ 

+

+
+
+

+ 

+  snr1
+  arm_linear_interp_example_f32.c
+ 

+

+

+ 

+  snr2
+  arm_linear_interp_example_f32.c
+ 

+

+

+ 

+  srcA_buf_f32
+  arm_dotproduct_example_f32.c
+ 

+

+

+ 

+  srcALen
+  arm_convolution_example_f32.c
+ 

+

+

+ 

+  srcB_buf_f32
+  arm_dotproduct_example_f32.c
+ 

+

+

+ 

+  srcBLen
+  arm_convolution_example_f32.c
+ 

+

+
+
+
+

+ 

+  std
+  arm_class_marks_example_f32.c
+ 

+

+

+ 

+  student_num
+  arm_class_marks_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_74.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_74.html
new file mode 100644
index 000000000..d9f01edba
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_74.html
@@ -0,0 +1,153 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  testIndex
+  arm_fft_bin_example_f32.c
+ 

+

+
+

+ 

+  testInput_f32_10khz
+  arm_fft_bin_example_f32.c
+ 

+

+

+ 

+  testInput_f32_1kHz_15kHz
+  arm_fir_example_f32.c
+ 

+

+

+ 

+  testInputA_f32
+  arm_convolution_example_f32.c
+ 

+

+

+ 

+  testInputB_f32
+  arm_convolution_example_f32.c
+ 

+

+

+ 

+  testInputSin_f32
+  arm_linear_interp_example_f32.c
+ 

+

+

+ 

+  testLinIntOutput
+  arm_linear_interp_example_f32.c
+ 

+

+

+ 

+  testMarks_f32
+  arm_class_marks_example_f32.c
+ 

+

+
+
+

+ 

+  testRefSinOutput32_f32
+  arm_linear_interp_example_f32.c
+ 

+

+

+ 

+  testUnity_f32
+  arm_class_marks_example_f32.c
+ 

+

+
+
+

+ 

+  twiddleCoef
+  arm_cfft_radix4_init_f32.c
+ 

+

+

+ 

+  twiddleCoefQ15
+  arm_cfft_radix4_init_q15.c
+ 

+

+

+ 

+  twiddleCoefQ31
+  arm_cfft_radix4_init_q31.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_76.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_76.html
new file mode 100644
index 000000000..4366f2a09
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_76.html
@@ -0,0 +1,26 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  var
+  arm_class_marks_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_77.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_77.html
new file mode 100644
index 000000000..050963930
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_77.html
@@ -0,0 +1,101 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  Weights_128
+  arm_dct4_init_f32.c
+ 

+

+

+ 

+  Weights_2048
+  arm_dct4_init_f32.c
+ 

+

+

+ 

+  Weights_512
+  arm_dct4_init_f32.c
+ 

+

+

+ 

+  WeightsQ15_128
+  arm_dct4_init_q15.c
+ 

+

+

+ 

+  WeightsQ15_2048
+  arm_dct4_init_q15.c
+ 

+

+

+ 

+  WeightsQ15_512
+  arm_dct4_init_q15.c
+ 

+

+

+ 

+  WeightsQ31_128
+  arm_dct4_init_q31.c
+ 

+

+

+ 

+  WeightsQ31_2048
+  arm_dct4_init_q31.c
+ 

+

+

+ 

+  WeightsQ31_512
+  arm_dct4_init_q31.c
+ 

+

+
+
+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_78.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_78.html
new file mode 100644
index 000000000..8bffbb6b0
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/search/variables_78.html
@@ -0,0 +1,54 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+

+ 

+  x1
+  arm_linear_interp_instance_f32
+ 

+

+

+ 

+  X_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  xRef_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  xSpacing
+  arm_linear_interp_instance_f32
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/sinCos.gif b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/sinCos.gif
new file mode 100644
index 000000000..b31221f9c
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__bilinear__interp__instance__f32.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__bilinear__interp__instance__f32.html
new file mode 100644
index 000000000..92861ccbf
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__bilinear__interp__instance__f32.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_bilinear_interp_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_bilinear_interp_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point bilinear interpolation function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numRows
uint16_t numCols
float32_t * pData

+
Detailed Description

+
Instance structure for the floating-point bilinear interpolation function. 

+
+
Definition at line 1783 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_bilinear_interp_instance_f32::numRows

+

+

+
number of rows in the data table. 

+
+
Definition at line 1785 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_bilinear_interp_instance_f32::numCols

+

+

+
number of columns in the data table. 

+
+
Definition at line 1786 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_bilinear_interp_instance_f32::pData

+

+

+
points to the data table. 

+
+
Definition at line 1787 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__bilinear__interp__instance__q15.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__bilinear__interp__instance__q15.html
new file mode 100644
index 000000000..46988fef1
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__bilinear__interp__instance__q15.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_bilinear_interp_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_bilinear_interp_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 bilinear interpolation function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numRows
uint16_t numCols
q15_t * pData

+
Detailed Description

+
Instance structure for the Q15 bilinear interpolation function. 

+
+
Definition at line 1805 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_bilinear_interp_instance_q15::numRows

+

+

+
number of rows in the data table. 

+
+
Definition at line 1807 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_bilinear_interp_instance_q15::numCols

+

+

+
number of columns in the data table. 

+
+
Definition at line 1808 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_bilinear_interp_instance_q15::pData

+

+

+
points to the data table. 

+
+
Definition at line 1809 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__bilinear__interp__instance__q31.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__bilinear__interp__instance__q31.html
new file mode 100644
index 000000000..664677329
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__bilinear__interp__instance__q31.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_bilinear_interp_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_bilinear_interp_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 bilinear interpolation function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numRows
uint16_t numCols
q31_t * pData

+
Detailed Description

+
Instance structure for the Q31 bilinear interpolation function. 

+
+
Definition at line 1794 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_bilinear_interp_instance_q31::numRows

+

+

+
number of rows in the data table. 

+
+
Definition at line 1796 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_bilinear_interp_instance_q31::numCols

+

+

+
number of columns in the data table. 

+
+
Definition at line 1797 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_bilinear_interp_instance_q31::pData

+

+

+
points to the data table. 

+
+
Definition at line 1798 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__bilinear__interp__instance__q7.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__bilinear__interp__instance__q7.html
new file mode 100644
index 000000000..67de8f651
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__bilinear__interp__instance__q7.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_bilinear_interp_instance_q7 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_bilinear_interp_instance_q7 Struct Reference
  

+

+

+
+
Instance structure for the Q15 bilinear interpolation function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numRows
uint16_t numCols
q7_t * pData

+
Detailed Description

+
Instance structure for the Q15 bilinear interpolation function. 

+
+
Definition at line 1816 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_bilinear_interp_instance_q7::numRows

+

+

+
number of rows in the data table. 

+
+
Definition at line 1818 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_bilinear_interp_instance_q7::numCols

+

+

+
number of columns in the data table. 

+
+
Definition at line 1819 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q7_t* arm_bilinear_interp_instance_q7::pData

+

+

+
points to the data table. 

+
+
Definition at line 1820 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__cas__df1__32x64__ins__q31.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__cas__df1__32x64__ins__q31.html
new file mode 100644
index 000000000..018882632
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__cas__df1__32x64__ins__q31.html
@@ -0,0 +1,163 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cas_df1_32x64_ins_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_biquad_cas_df1_32x64_ins_q31 Struct Reference
  

+

+

+
+
Instance structure for the high precision Q31 Biquad cascade filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
uint8_t numStages
q63_t * pState
q31_t * pCoeffs
uint8_t postShift

+
Detailed Description

+
Instance structure for the high precision Q31 Biquad cascade filter. 

+
Examples: 

+
arm_graphic_equalizer_example_q31.c.

+

+

+
Definition at line 3539 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_biquad_cas_df1_32x64_ins_q31::numStages

+

+

+
number of 2nd order stages in the filter. Overall order is 2*numStages. 

+
+
Definition at line 3541 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q63_t* arm_biquad_cas_df1_32x64_ins_q31::pState

+

+

+
points to the array of state coefficients. The array is of length 4*numStages. 

+
+
Definition at line 3542 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_biquad_cas_df1_32x64_ins_q31::pCoeffs

+

+

+
points to the array of coefficients. The array is of length 5*numStages. 

+
+
Definition at line 3543 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_biquad_cas_df1_32x64_ins_q31::postShift

+

+

+
additional shift, in bits, applied to each output sample. 

+
+
Definition at line 3544 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__cascade__df2_t__instance__f32.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__cascade__df2_t__instance__f32.html
new file mode 100644
index 000000000..8e5a8a49d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__cascade__df2_t__instance__f32.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df2T_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_biquad_cascade_df2T_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point transposed direct form II Biquad cascade filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint8_t numStages
float32_t * pState
float32_t * pCoeffs

+
Detailed Description

+
Instance structure for the floating-point transposed direct form II Biquad cascade filter. 

+
+
Definition at line 3586 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_biquad_cascade_df2T_instance_f32::numStages

+

+

+
number of 2nd order stages in the filter. Overall order is 2*numStages. 

+
+
Definition at line 3588 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_biquad_cascade_df2T_instance_f32::pState

+

+

+
points to the array of state coefficients. The array is of length 2*numStages. 

+
+
Definition at line 3589 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_biquad_cascade_df2T_instance_f32::pCoeffs

+

+

+
points to the array of coefficients. The array is of length 5*numStages. 

+
+
Definition at line 3590 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__casd__df1__inst__f32.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__casd__df1__inst__f32.html
new file mode 100644
index 000000000..fb6327bb3
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__casd__df1__inst__f32.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_casd_df1_inst_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_biquad_casd_df1_inst_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point Biquad cascade filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint32_t numStages
float32_t * pState
float32_t * pCoeffs

+
Detailed Description

+
Instance structure for the floating-point Biquad cascade filter. 

+
+
Definition at line 1195 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_biquad_casd_df1_inst_f32::numStages

+

+

+
number of 2nd order stages in the filter. Overall order is 2*numStages. 

+
+
Definition at line 1197 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_biquad_casd_df1_inst_f32::pState

+

+

+
Points to the array of state coefficients. The array is of length 4*numStages. 

+
+
Definition at line 1198 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_biquad_casd_df1_inst_f32::pCoeffs

+

+

+
Points to the array of coefficients. The array is of length 5*numStages. 

+
+
Definition at line 1199 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__casd__df1__inst__q15.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__casd__df1__inst__q15.html
new file mode 100644
index 000000000..f0f77eb93
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__casd__df1__inst__q15.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_casd_df1_inst_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_biquad_casd_df1_inst_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 Biquad cascade filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
int8_t numStages
q15_t * pState
q15_t * pCoeffs
int8_t postShift

+
Detailed Description

+
Instance structure for the Q15 Biquad cascade filter. 

+
+
Definition at line 1170 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
int8_t arm_biquad_casd_df1_inst_q15::numStages

+

+

+
number of 2nd order stages in the filter. Overall order is 2*numStages. 

+
+
Definition at line 1172 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_biquad_casd_df1_inst_q15::pState

+

+

+
Points to the array of state coefficients. The array is of length 4*numStages. 

+
+
Definition at line 1173 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_biquad_casd_df1_inst_q15::pCoeffs

+

+

+
Points to the array of coefficients. The array is of length 5*numStages. 

+
+
Definition at line 1174 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
int8_t arm_biquad_casd_df1_inst_q15::postShift

+

+

+
Additional shift, in bits, applied to each output sample. 

+
+
Definition at line 1175 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__casd__df1__inst__q31.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__casd__df1__inst__q31.html
new file mode 100644
index 000000000..2eb8acbcc
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__casd__df1__inst__q31.html
@@ -0,0 +1,163 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_casd_df1_inst_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_biquad_casd_df1_inst_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 Biquad cascade filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
uint32_t numStages
q31_t * pState
q31_t * pCoeffs
uint8_t postShift

+
Detailed Description

+
Instance structure for the Q31 Biquad cascade filter. 

+
Examples: 

+
arm_graphic_equalizer_example_q31.c.

+

+

+
Definition at line 1183 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_biquad_casd_df1_inst_q31::numStages

+

+

+
number of 2nd order stages in the filter. Overall order is 2*numStages. 

+
+
Definition at line 1185 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_biquad_casd_df1_inst_q31::pState

+

+

+
Points to the array of state coefficients. The array is of length 4*numStages. 

+
+
Definition at line 1186 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_biquad_casd_df1_inst_q31::pCoeffs

+

+

+
Points to the array of coefficients. The array is of length 5*numStages. 

+
+
Definition at line 1187 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_biquad_casd_df1_inst_q31::postShift

+

+

+
Additional shift, in bits, applied to each output sample. 

+
+
Definition at line 1188 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__cfft__radix4__instance__f32.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__cfft__radix4__instance__f32.html
new file mode 100644
index 000000000..eba95d4f9
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__cfft__radix4__instance__f32.html
@@ -0,0 +1,231 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cfft_radix4_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_cfft_radix4_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point CFFT/CIFFT function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t fftLen
uint8_t ifftFlag
uint8_t bitReverseFlag
float32_t * pTwiddle
uint16_t * pBitRevTable
uint16_t twidCoefModifier
uint16_t bitRevFactor
float32_t onebyfftLen

+
Detailed Description

+
Instance structure for the floating-point CFFT/CIFFT function. 

+
Examples: 

+
arm_convolution_example_f32.c, and arm_fft_bin_example_f32.c.

+

+

+
Definition at line 1919 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_f32::fftLen

+

+

+
length of the FFT. 

+
+
Definition at line 1921 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_cfft_radix4_instance_f32::ifftFlag

+

+

+
flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 

+
+
Definition at line 1922 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_cfft_radix4_instance_f32::bitReverseFlag

+

+

+
flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+
+
Definition at line 1923 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_cfft_radix4_instance_f32::pTwiddle

+

+

+
points to the twiddle factor table. 

+
+
Definition at line 1924 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t* arm_cfft_radix4_instance_f32::pBitRevTable

+

+

+
points to the bit reversal table. 

+
+
Definition at line 1925 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_f32::twidCoefModifier

+

+

+
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+
+
Definition at line 1926 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_f32::bitRevFactor

+

+

+
bit reversal modifier that supports different size FFTs with the same bit reversal table. 

+
+
Definition at line 1927 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_cfft_radix4_instance_f32::onebyfftLen

+

+

+
value of 1/fftLen. 

+
+
Definition at line 1928 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__cfft__radix4__instance__q15.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__cfft__radix4__instance__q15.html
new file mode 100644
index 000000000..7604ba243
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__cfft__radix4__instance__q15.html
@@ -0,0 +1,211 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cfft_radix4_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_cfft_radix4_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 CFFT/CIFFT function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t fftLen
uint8_t ifftFlag
uint8_t bitReverseFlag
q15_t * pTwiddle
uint16_t * pBitRevTable
uint16_t twidCoefModifier
uint16_t bitRevFactor

+
Detailed Description

+
Instance structure for the Q15 CFFT/CIFFT function. 

+
+
Definition at line 1889 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_q15::fftLen

+

+

+
length of the FFT. 

+
+
Definition at line 1891 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_cfft_radix4_instance_q15::ifftFlag

+

+

+
flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 

+
+
Definition at line 1892 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_cfft_radix4_instance_q15::bitReverseFlag

+

+

+
flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+
+
Definition at line 1893 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_cfft_radix4_instance_q15::pTwiddle

+

+

+
points to the twiddle factor table. 

+
+
Definition at line 1894 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t* arm_cfft_radix4_instance_q15::pBitRevTable

+

+

+
points to the bit reversal table. 

+
+
Definition at line 1895 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_q15::twidCoefModifier

+

+

+
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+
+
Definition at line 1896 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_q15::bitRevFactor

+

+

+
bit reversal modifier that supports different size FFTs with the same bit reversal table. 

+
+
Definition at line 1897 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__cfft__radix4__instance__q31.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__cfft__radix4__instance__q31.html
new file mode 100644
index 000000000..f8d1e7863
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__cfft__radix4__instance__q31.html
@@ -0,0 +1,211 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cfft_radix4_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_cfft_radix4_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 CFFT/CIFFT function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t fftLen
uint8_t ifftFlag
uint8_t bitReverseFlag
q31_t * pTwiddle
uint16_t * pBitRevTable
uint16_t twidCoefModifier
uint16_t bitRevFactor

+
Detailed Description

+
Instance structure for the Q31 CFFT/CIFFT function. 

+
+
Definition at line 1904 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_q31::fftLen

+

+

+
length of the FFT. 

+
+
Definition at line 1906 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_cfft_radix4_instance_q31::ifftFlag

+

+

+
flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 

+
+
Definition at line 1907 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_cfft_radix4_instance_q31::bitReverseFlag

+

+

+
flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+
+
Definition at line 1908 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_cfft_radix4_instance_q31::pTwiddle

+

+

+
points to the twiddle factor table. 

+
+
Definition at line 1909 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t* arm_cfft_radix4_instance_q31::pBitRevTable

+

+

+
points to the bit reversal table. 

+
+
Definition at line 1910 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_q31::twidCoefModifier

+

+

+
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+
+
Definition at line 1911 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_q31::bitRevFactor

+

+

+
bit reversal modifier that supports different size FFTs with the same bit reversal table. 

+
+
Definition at line 1912 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__dct4__instance__f32.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__dct4__instance__f32.html
new file mode 100644
index 000000000..d3efbc52e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__dct4__instance__f32.html
@@ -0,0 +1,211 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_dct4_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point DCT4/IDCT4 function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t N
uint16_t Nby2
float32_t normalize
float32_t * pTwiddle
float32_t * pCosFactor
arm_rfft_instance_f32 * pRfft
arm_cfft_radix4_instance_f32 * pCfft

+
Detailed Description

+
Instance structure for the floating-point DCT4/IDCT4 function. 

+
+
Definition at line 2294 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_dct4_instance_f32::N

+

+

+
length of the DCT4. 

+
+
Definition at line 2296 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_dct4_instance_f32::Nby2

+

+

+
half of the length of the DCT4. 

+
+
Definition at line 2297 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_dct4_instance_f32::normalize

+

+

+
normalizing factor. 

+
+
Definition at line 2298 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_dct4_instance_f32::pTwiddle

+

+

+
points to the twiddle factor table. 

+
+
Definition at line 2299 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_dct4_instance_f32::pCosFactor

+

+

+
points to the cosFactor table. 

+
+
Definition at line 2300 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_rfft_instance_f32* arm_dct4_instance_f32::pRfft

+

+

+
points to the real FFT instance. 

+
+
Definition at line 2301 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_cfft_radix4_instance_f32* arm_dct4_instance_f32::pCfft

+

+

+
points to the complex FFT instance. 

+
+
Definition at line 2302 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__dct4__instance__q15.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__dct4__instance__q15.html
new file mode 100644
index 000000000..426d11826
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__dct4__instance__q15.html
@@ -0,0 +1,211 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_dct4_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 DCT4/IDCT4 function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t N
uint16_t Nby2
q15_t normalize
q15_t * pTwiddle
q15_t * pCosFactor
arm_rfft_instance_q15 * pRfft
arm_cfft_radix4_instance_q15 * pCfft

+
Detailed Description

+
Instance structure for the Q15 DCT4/IDCT4 function. 

+
+
Definition at line 2388 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_dct4_instance_q15::N

+

+

+
length of the DCT4. 

+
+
Definition at line 2390 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_dct4_instance_q15::Nby2

+

+

+
half of the length of the DCT4. 

+
+
Definition at line 2391 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t arm_dct4_instance_q15::normalize

+

+

+
normalizing factor. 

+
+
Definition at line 2392 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_dct4_instance_q15::pTwiddle

+

+

+
points to the twiddle factor table. 

+
+
Definition at line 2393 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_dct4_instance_q15::pCosFactor

+

+

+
points to the cosFactor table. 

+
+
Definition at line 2394 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_rfft_instance_q15* arm_dct4_instance_q15::pRfft

+

+

+
points to the real FFT instance. 

+
+
Definition at line 2395 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_cfft_radix4_instance_q15* arm_dct4_instance_q15::pCfft

+

+

+
points to the complex FFT instance. 

+
+
Definition at line 2396 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__dct4__instance__q31.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__dct4__instance__q31.html
new file mode 100644
index 000000000..680576ee7
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__dct4__instance__q31.html
@@ -0,0 +1,211 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_dct4_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 DCT4/IDCT4 function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t N
uint16_t Nby2
q31_t normalize
q31_t * pTwiddle
q31_t * pCosFactor
arm_rfft_instance_q31 * pRfft
arm_cfft_radix4_instance_q31 * pCfft

+
Detailed Description

+
Instance structure for the Q31 DCT4/IDCT4 function. 

+
+
Definition at line 2341 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_dct4_instance_q31::N

+

+

+
length of the DCT4. 

+
+
Definition at line 2343 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_dct4_instance_q31::Nby2

+

+

+
half of the length of the DCT4. 

+
+
Definition at line 2344 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_dct4_instance_q31::normalize

+

+

+
normalizing factor. 

+
+
Definition at line 2345 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_dct4_instance_q31::pTwiddle

+

+

+
points to the twiddle factor table. 

+
+
Definition at line 2346 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_dct4_instance_q31::pCosFactor

+

+

+
points to the cosFactor table. 

+
+
Definition at line 2347 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_rfft_instance_q31* arm_dct4_instance_q31::pRfft

+

+

+
points to the real FFT instance. 

+
+
Definition at line 2348 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_cfft_radix4_instance_q31* arm_dct4_instance_q31::pCfft

+

+

+
points to the complex FFT instance. 

+
+
Definition at line 2349 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__decimate__instance__f32.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__decimate__instance__f32.html
new file mode 100644
index 000000000..f77169ada
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__decimate__instance__f32.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_decimate_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point FIR decimator.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
uint8_t M
uint16_t numTaps
float32_t * pCoeffs
float32_t * pState

+
Detailed Description

+
Instance structure for the floating-point FIR decimator. 

+
+
Definition at line 3239 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_fir_decimate_instance_f32::M

+

+

+
decimation factor. 

+
+
Definition at line 3241 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_decimate_instance_f32::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Definition at line 3242 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_decimate_instance_f32::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 3243 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_decimate_instance_f32::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Definition at line 3244 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__decimate__instance__q15.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__decimate__instance__q15.html
new file mode 100644
index 000000000..1a9d0d6d9
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__decimate__instance__q15.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_decimate_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 FIR decimator.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
uint8_t M
uint16_t numTaps
q15_t * pCoeffs
q15_t * pState

+
Detailed Description

+
Instance structure for the Q15 FIR decimator. 

+
+
Definition at line 3214 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_fir_decimate_instance_q15::M

+

+

+
decimation factor. 

+
+
Definition at line 3216 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_decimate_instance_q15::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Definition at line 3217 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_decimate_instance_q15::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 3218 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_decimate_instance_q15::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Definition at line 3219 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__decimate__instance__q31.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__decimate__instance__q31.html
new file mode 100644
index 000000000..60dfe5bec
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__decimate__instance__q31.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_decimate_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 FIR decimator.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
uint8_t M
uint16_t numTaps
q31_t * pCoeffs
q31_t * pState

+
Detailed Description

+
Instance structure for the Q31 FIR decimator. 

+
+
Definition at line 3226 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_fir_decimate_instance_q31::M

+

+

+
decimation factor. 

+
+
Definition at line 3228 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_decimate_instance_q31::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Definition at line 3229 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_decimate_instance_q31::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 3230 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_decimate_instance_q31::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Definition at line 3231 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__instance__f32.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__instance__f32.html
new file mode 100644
index 000000000..ae49eef84
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__instance__f32.html
@@ -0,0 +1,146 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point FIR filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numTaps
float32_t * pState
float32_t * pCoeffs

+
Detailed Description

+
Instance structure for the floating-point FIR filter. 

+
Examples: 

+
arm_fir_example_f32.c, and arm_signal_converge_example_f32.c.

+

+

+
Definition at line 1006 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_instance_f32::numTaps

+

+

+
number of filter coefficients in the filter. 

+
+
Definition at line 1008 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_instance_f32::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Definition at line 1009 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_instance_f32::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 1010 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__instance__q15.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__instance__q15.html
new file mode 100644
index 000000000..bd33eab79
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__instance__q15.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 FIR filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numTaps
q15_t * pState
q15_t * pCoeffs

+
Detailed Description

+
Instance structure for the Q15 FIR filter. 

+
+
Definition at line 986 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_instance_q15::numTaps

+

+

+
number of filter coefficients in the filter. 

+
+
Definition at line 988 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_instance_q15::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Definition at line 989 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_instance_q15::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 990 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__instance__q31.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__instance__q31.html
new file mode 100644
index 000000000..3e6e20a8e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__instance__q31.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 FIR filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numTaps
q31_t * pState
q31_t * pCoeffs

+
Detailed Description

+
Instance structure for the Q31 FIR filter. 

+
+
Definition at line 996 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_instance_q31::numTaps

+

+

+
number of filter coefficients in the filter. 

+
+
Definition at line 998 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_instance_q31::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Definition at line 999 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_instance_q31::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 1000 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__instance__q7.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__instance__q7.html
new file mode 100644
index 000000000..37e77a024
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__instance__q7.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_instance_q7 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_instance_q7 Struct Reference
  

+

+

+
+
Instance structure for the Q7 FIR filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numTaps
q7_t * pState
q7_t * pCoeffs

+
Detailed Description

+
Instance structure for the Q7 FIR filter. 

+
+
Definition at line 976 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_instance_q7::numTaps

+

+

+
number of filter coefficients in the filter. 

+
+
Definition at line 978 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q7_t* arm_fir_instance_q7::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Definition at line 979 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q7_t* arm_fir_instance_q7::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 980 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__interpolate__instance__f32.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__interpolate__instance__f32.html
new file mode 100644
index 000000000..3cbdb4768
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__interpolate__instance__f32.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_interpolate_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point FIR interpolator.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
uint8_t L
uint16_t phaseLength
float32_t * pCoeffs
float32_t * pState

+
Detailed Description

+
Instance structure for the floating-point FIR interpolator. 

+
+
Definition at line 3419 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_fir_interpolate_instance_f32::L

+

+

+
upsample factor. 

+
+
Definition at line 3421 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_interpolate_instance_f32::phaseLength

+

+

+
length of each polyphase filter component. 

+
+
Definition at line 3422 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_interpolate_instance_f32::pCoeffs

+

+

+
points to the coefficient array. The array is of length L*phaseLength. 

+
+
Definition at line 3423 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_interpolate_instance_f32::pState

+

+

+
points to the state variable array. The array is of length phaseLength+numTaps-1. 

+
+
Definition at line 3424 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__interpolate__instance__q15.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__interpolate__instance__q15.html
new file mode 100644
index 000000000..5ff68a783
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__interpolate__instance__q15.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_interpolate_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 FIR interpolator.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
uint8_t L
uint16_t phaseLength
q15_t * pCoeffs
q15_t * pState

+
Detailed Description

+
Instance structure for the Q15 FIR interpolator. 

+
+
Definition at line 3395 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_fir_interpolate_instance_q15::L

+

+

+
upsample factor. 

+
+
Definition at line 3397 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_interpolate_instance_q15::phaseLength

+

+

+
length of each polyphase filter component. 

+
+
Definition at line 3398 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_interpolate_instance_q15::pCoeffs

+

+

+
points to the coefficient array. The array is of length L*phaseLength. 

+
+
Definition at line 3399 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_interpolate_instance_q15::pState

+

+

+
points to the state variable array. The array is of length blockSize+phaseLength-1. 

+
+
Definition at line 3400 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__interpolate__instance__q31.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__interpolate__instance__q31.html
new file mode 100644
index 000000000..7c65829bd
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__interpolate__instance__q31.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_interpolate_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 FIR interpolator.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
uint8_t L
uint16_t phaseLength
q31_t * pCoeffs
q31_t * pState

+
Detailed Description

+
Instance structure for the Q31 FIR interpolator. 

+
+
Definition at line 3407 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_fir_interpolate_instance_q31::L

+

+

+
upsample factor. 

+
+
Definition at line 3409 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_interpolate_instance_q31::phaseLength

+

+

+
length of each polyphase filter component. 

+
+
Definition at line 3410 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_interpolate_instance_q31::pCoeffs

+

+

+
points to the coefficient array. The array is of length L*phaseLength. 

+
+
Definition at line 3411 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_interpolate_instance_q31::pState

+

+

+
points to the state variable array. The array is of length blockSize+phaseLength-1. 

+
+
Definition at line 3412 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__lattice__instance__f32.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__lattice__instance__f32.html
new file mode 100644
index 000000000..0a4a838d8
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__lattice__instance__f32.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_lattice_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point FIR lattice filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numStages
float32_t * pState
float32_t * pCoeffs

+
Detailed Description

+
Instance structure for the floating-point FIR lattice filter. 

+
+
Definition at line 3653 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_lattice_instance_f32::numStages

+

+

+
number of filter stages. 

+
+
Definition at line 3655 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_lattice_instance_f32::pState

+

+

+
points to the state variable array. The array is of length numStages. 

+
+
Definition at line 3656 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_lattice_instance_f32::pCoeffs

+

+

+
points to the coefficient array. The array is of length numStages. 

+
+
Definition at line 3657 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__lattice__instance__q15.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__lattice__instance__q15.html
new file mode 100644
index 000000000..b98bfa6f9
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__lattice__instance__q15.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_lattice_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 FIR lattice filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numStages
q15_t * pState
q15_t * pCoeffs

+
Detailed Description

+
Instance structure for the Q15 FIR lattice filter. 

+
+
Definition at line 3631 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_lattice_instance_q15::numStages

+

+

+
number of filter stages. 

+
+
Definition at line 3633 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_lattice_instance_q15::pState

+

+

+
points to the state variable array. The array is of length numStages. 

+
+
Definition at line 3634 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_lattice_instance_q15::pCoeffs

+

+

+
points to the coefficient array. The array is of length numStages. 

+
+
Definition at line 3635 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__lattice__instance__q31.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__lattice__instance__q31.html
new file mode 100644
index 000000000..bbfdc9317
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__lattice__instance__q31.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_lattice_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 FIR lattice filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numStages
q31_t * pState
q31_t * pCoeffs

+
Detailed Description

+
Instance structure for the Q31 FIR lattice filter. 

+
+
Definition at line 3642 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_lattice_instance_q31::numStages

+

+

+
number of filter stages. 

+
+
Definition at line 3644 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_lattice_instance_q31::pState

+

+

+
points to the state variable array. The array is of length numStages. 

+
+
Definition at line 3645 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_lattice_instance_q31::pCoeffs

+

+

+
points to the coefficient array. The array is of length numStages. 

+
+
Definition at line 3646 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__sparse__instance__f32.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__sparse__instance__f32.html
new file mode 100644
index 000000000..209ddd3eb
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__sparse__instance__f32.html
@@ -0,0 +1,194 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_sparse_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point sparse FIR filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
uint16_t stateIndex
float32_t * pState
float32_t * pCoeffs
uint16_t maxDelay
int32_t * pTapDelay

+
Detailed Description

+
Instance structure for the floating-point sparse FIR filter. 

+
+
Definition at line 4319 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_f32::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Definition at line 4321 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_f32::stateIndex

+

+

+
state buffer index. Points to the oldest sample in the state buffer. 

+
+
Definition at line 4322 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_sparse_instance_f32::pState

+

+

+
points to the state buffer array. The array is of length maxDelay+blockSize-1. 

+
+
Definition at line 4323 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_sparse_instance_f32::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 4324 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_f32::maxDelay

+

+

+
maximum offset specified by the pTapDelay array. 

+
+
Definition at line 4325 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
int32_t* arm_fir_sparse_instance_f32::pTapDelay

+

+

+
points to the array of delay values. The array is of length numTaps. 

+
+
Definition at line 4326 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__sparse__instance__q15.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__sparse__instance__q15.html
new file mode 100644
index 000000000..98cc50420
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__sparse__instance__q15.html
@@ -0,0 +1,194 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_sparse_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 sparse FIR filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
uint16_t stateIndex
q15_t * pState
q15_t * pCoeffs
uint16_t maxDelay
int32_t * pTapDelay

+
Detailed Description

+
Instance structure for the Q15 sparse FIR filter. 

+
+
Definition at line 4347 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q15::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Definition at line 4349 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q15::stateIndex

+

+

+
state buffer index. Points to the oldest sample in the state buffer. 

+
+
Definition at line 4350 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_sparse_instance_q15::pState

+

+

+
points to the state buffer array. The array is of length maxDelay+blockSize-1. 

+
+
Definition at line 4351 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_sparse_instance_q15::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 4352 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q15::maxDelay

+

+

+
maximum offset specified by the pTapDelay array. 

+
+
Definition at line 4353 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
int32_t* arm_fir_sparse_instance_q15::pTapDelay

+

+

+
points to the array of delay values. The array is of length numTaps. 

+
+
Definition at line 4354 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__sparse__instance__q31.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__sparse__instance__q31.html
new file mode 100644
index 000000000..3071cb5c5
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__sparse__instance__q31.html
@@ -0,0 +1,194 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_sparse_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 sparse FIR filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
uint16_t stateIndex
q31_t * pState
q31_t * pCoeffs
uint16_t maxDelay
int32_t * pTapDelay

+
Detailed Description

+
Instance structure for the Q31 sparse FIR filter. 

+
+
Definition at line 4333 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q31::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Definition at line 4335 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q31::stateIndex

+

+

+
state buffer index. Points to the oldest sample in the state buffer. 

+
+
Definition at line 4336 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_sparse_instance_q31::pState

+

+

+
points to the state buffer array. The array is of length maxDelay+blockSize-1. 

+
+
Definition at line 4337 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_sparse_instance_q31::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 4338 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q31::maxDelay

+

+

+
maximum offset specified by the pTapDelay array. 

+
+
Definition at line 4339 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
int32_t* arm_fir_sparse_instance_q31::pTapDelay

+

+

+
points to the array of delay values. The array is of length numTaps. 

+
+
Definition at line 4340 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__sparse__instance__q7.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__sparse__instance__q7.html
new file mode 100644
index 000000000..6002906e6
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__fir__sparse__instance__q7.html
@@ -0,0 +1,194 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_instance_q7 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_sparse_instance_q7 Struct Reference
  

+

+

+
+
Instance structure for the Q7 sparse FIR filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
uint16_t stateIndex
q7_t * pState
q7_t * pCoeffs
uint16_t maxDelay
int32_t * pTapDelay

+
Detailed Description

+
Instance structure for the Q7 sparse FIR filter. 

+
+
Definition at line 4361 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q7::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Definition at line 4363 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q7::stateIndex

+

+

+
state buffer index. Points to the oldest sample in the state buffer. 

+
+
Definition at line 4364 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q7_t* arm_fir_sparse_instance_q7::pState

+

+

+
points to the state buffer array. The array is of length maxDelay+blockSize-1. 

+
+
Definition at line 4365 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q7_t* arm_fir_sparse_instance_q7::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 4366 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q7::maxDelay

+

+

+
maximum offset specified by the pTapDelay array. 

+
+
Definition at line 4367 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
int32_t* arm_fir_sparse_instance_q7::pTapDelay

+

+

+
points to the array of delay values. The array is of length numTaps. 

+
+
Definition at line 4368 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__iir__lattice__instance__f32.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__iir__lattice__instance__f32.html
new file mode 100644
index 000000000..0b4bbdfb2
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__iir__lattice__instance__f32.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_iir_lattice_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_iir_lattice_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point IIR lattice filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
uint16_t numStages
float32_t * pState
float32_t * pkCoeffs
float32_t * pvCoeffs

+
Detailed Description

+
Instance structure for the floating-point IIR lattice filter. 

+
+
Definition at line 3776 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_iir_lattice_instance_f32::numStages

+

+

+
number of stages in the filter. 

+
+
Definition at line 3778 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_iir_lattice_instance_f32::pState

+

+

+
points to the state variable array. The array is of length numStages+blockSize. 

+
+
Definition at line 3779 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_iir_lattice_instance_f32::pkCoeffs

+

+

+
points to the reflection coefficient array. The array is of length numStages. 

+
+
Definition at line 3780 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_iir_lattice_instance_f32::pvCoeffs

+

+

+
points to the ladder coefficient array. The array is of length numStages+1. 

+
+
Definition at line 3781 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__iir__lattice__instance__q15.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__iir__lattice__instance__q15.html
new file mode 100644
index 000000000..8c1dfefa7
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__iir__lattice__instance__q15.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_iir_lattice_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_iir_lattice_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 IIR lattice filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
uint16_t numStages
q15_t * pState
q15_t * pkCoeffs
q15_t * pvCoeffs

+
Detailed Description

+
Instance structure for the Q15 IIR lattice filter. 

+
+
Definition at line 3754 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_iir_lattice_instance_q15::numStages

+

+

+
number of stages in the filter. 

+
+
Definition at line 3756 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_iir_lattice_instance_q15::pState

+

+

+
points to the state variable array. The array is of length numStages+blockSize. 

+
+
Definition at line 3757 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_iir_lattice_instance_q15::pkCoeffs

+

+

+
points to the reflection coefficient array. The array is of length numStages. 

+
+
Definition at line 3758 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_iir_lattice_instance_q15::pvCoeffs

+

+

+
points to the ladder coefficient array. The array is of length numStages+1. 

+
+
Definition at line 3759 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__iir__lattice__instance__q31.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__iir__lattice__instance__q31.html
new file mode 100644
index 000000000..29ed0956c
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__iir__lattice__instance__q31.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_iir_lattice_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_iir_lattice_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 IIR lattice filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
uint16_t numStages
q31_t * pState
q31_t * pkCoeffs
q31_t * pvCoeffs

+
Detailed Description

+
Instance structure for the Q31 IIR lattice filter. 

+
+
Definition at line 3765 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_iir_lattice_instance_q31::numStages

+

+

+
number of stages in the filter. 

+
+
Definition at line 3767 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_iir_lattice_instance_q31::pState

+

+

+
points to the state variable array. The array is of length numStages+blockSize. 

+
+
Definition at line 3768 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_iir_lattice_instance_q31::pkCoeffs

+

+

+
points to the reflection coefficient array. The array is of length numStages. 

+
+
Definition at line 3769 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_iir_lattice_instance_q31::pvCoeffs

+

+

+
points to the ladder coefficient array. The array is of length numStages+1. 

+
+
Definition at line 3770 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__linear__interp__instance__f32.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__linear__interp__instance__f32.html
new file mode 100644
index 000000000..6a7c4bafc
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__linear__interp__instance__f32.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_linear_interp_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_linear_interp_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point Linear Interpolate function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
uint32_t nValues
float32_t x1
float32_t xSpacing
float32_t * pYData

+
Detailed Description

+
Instance structure for the floating-point Linear Interpolate function. 

+
Examples: 

+
arm_linear_interp_example_f32.c.

+

+

+
Definition at line 1771 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_linear_interp_instance_f32::nValues

+

+

+
+
Definition at line 1773 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_linear_interp_instance_f32::x1

+

+

+
+
Definition at line 1774 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_linear_interp_instance_f32::xSpacing

+

+

+
+
Definition at line 1775 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_linear_interp_instance_f32::pYData

+

+

+
pointer to the table of Y values 

+
+
Definition at line 1776 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__lms__instance__f32.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__lms__instance__f32.html
new file mode 100644
index 000000000..00173fe09
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__lms__instance__f32.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_lms_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point LMS filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
float32_t * pState
float32_t * pCoeffs
float32_t mu

+
Detailed Description

+
Instance structure for the floating-point LMS filter. 

+
+
Definition at line 3894 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_lms_instance_f32::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Definition at line 3896 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_lms_instance_f32::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Definition at line 3897 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_lms_instance_f32::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 3898 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_lms_instance_f32::mu

+

+

+
step size that controls filter coefficient updates. 

+
+
Definition at line 3899 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__lms__instance__q15.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__lms__instance__q15.html
new file mode 100644
index 000000000..d9f5e32b1
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__lms__instance__q15.html
@@ -0,0 +1,177 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_lms_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 LMS filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
q15_t * pState
q15_t * pCoeffs
q15_t mu
uint32_t postShift

+
Detailed Description

+
Instance structure for the Q15 LMS filter. 

+
+
Definition at line 3944 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_lms_instance_q15::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Definition at line 3946 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_lms_instance_q15::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Definition at line 3947 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_lms_instance_q15::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 3948 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t arm_lms_instance_q15::mu

+

+

+
step size that controls filter coefficient updates. 

+
+
Definition at line 3949 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_lms_instance_q15::postShift

+

+

+
bit shift applied to coefficients. 

+
+
Definition at line 3950 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__lms__instance__q31.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__lms__instance__q31.html
new file mode 100644
index 000000000..0bddeb327
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__lms__instance__q31.html
@@ -0,0 +1,177 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_lms_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 LMS filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
q31_t * pState
q31_t * pCoeffs
q31_t mu
uint32_t postShift

+
Detailed Description

+
Instance structure for the Q31 LMS filter. 

+
+
Definition at line 3999 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_lms_instance_q31::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Definition at line 4001 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_lms_instance_q31::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Definition at line 4002 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_lms_instance_q31::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 4003 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_lms_instance_q31::mu

+

+

+
step size that controls filter coefficient updates. 

+
+
Definition at line 4004 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_lms_instance_q31::postShift

+

+

+
bit shift applied to coefficients. 

+
+
Definition at line 4005 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__lms__norm__instance__f32.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__lms__norm__instance__f32.html
new file mode 100644
index 000000000..b017ecdb0
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__lms__norm__instance__f32.html
@@ -0,0 +1,197 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_lms_norm_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point normalized LMS filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
float32_t * pState
float32_t * pCoeffs
float32_t mu
float32_t energy
float32_t x0

+
Detailed Description

+
Instance structure for the floating-point normalized LMS filter. 

+
Examples: 

+
arm_signal_converge_example_f32.c.

+

+

+
Definition at line 4053 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_lms_norm_instance_f32::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Definition at line 4055 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_lms_norm_instance_f32::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Definition at line 4056 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_lms_norm_instance_f32::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 4057 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_lms_norm_instance_f32::mu

+

+

+
step size that control filter coefficient updates. 

+
+
Definition at line 4058 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_lms_norm_instance_f32::energy

+

+

+
saves previous frame energy. 

+
+
Definition at line 4059 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_lms_norm_instance_f32::x0

+

+

+
saves previous input sample. 

+
+
Definition at line 4060 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__lms__norm__instance__q15.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__lms__norm__instance__q15.html
new file mode 100644
index 000000000..da6419f54
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__lms__norm__instance__q15.html
@@ -0,0 +1,228 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_lms_norm_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 normalized LMS filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
q15_t * pState
q15_t * pCoeffs
q15_t mu
uint8_t postShift
q15_t * recipTable
q15_t energy
q15_t x0

+
Detailed Description

+
Instance structure for the Q15 normalized LMS filter. 

+
+
Definition at line 4161 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_lms_norm_instance_q15::numTaps

+

+

+
Number of coefficients in the filter. 

+
+
Definition at line 4163 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_lms_norm_instance_q15::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Definition at line 4164 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_lms_norm_instance_q15::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 4165 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t arm_lms_norm_instance_q15::mu

+

+

+
step size that controls filter coefficient updates. 

+
+
Definition at line 4166 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_lms_norm_instance_q15::postShift

+

+

+
bit shift applied to coefficients. 

+
+
Definition at line 4167 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_lms_norm_instance_q15::recipTable

+

+

+
Points to the reciprocal initial value table. 

+
+
Definition at line 4168 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t arm_lms_norm_instance_q15::energy

+

+

+
saves previous frame energy. 

+
+
Definition at line 4169 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t arm_lms_norm_instance_q15::x0

+

+

+
saves previous input sample. 

+
+
Definition at line 4170 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__lms__norm__instance__q31.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__lms__norm__instance__q31.html
new file mode 100644
index 000000000..1f12878b5
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__lms__norm__instance__q31.html
@@ -0,0 +1,228 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_lms_norm_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 normalized LMS filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
q31_t * pState
q31_t * pCoeffs
q31_t mu
uint8_t postShift
q31_t * recipTable
q31_t energy
q31_t x0

+
Detailed Description

+
Instance structure for the Q31 normalized LMS filter. 

+
+
Definition at line 4105 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_lms_norm_instance_q31::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Definition at line 4107 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_lms_norm_instance_q31::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Definition at line 4108 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_lms_norm_instance_q31::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 4109 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_lms_norm_instance_q31::mu

+

+

+
step size that controls filter coefficient updates. 

+
+
Definition at line 4110 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_lms_norm_instance_q31::postShift

+

+

+
bit shift applied to coefficients. 

+
+
Definition at line 4111 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_lms_norm_instance_q31::recipTable

+

+

+
points to the reciprocal initial value table. 

+
+
Definition at line 4112 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_lms_norm_instance_q31::energy

+

+

+
saves previous frame energy. 

+
+
Definition at line 4113 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_lms_norm_instance_q31::x0

+

+

+
saves previous input sample. 

+
+
Definition at line 4114 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__matrix__instance__f32.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__matrix__instance__f32.html
new file mode 100644
index 000000000..ed0056058
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__matrix__instance__f32.html
@@ -0,0 +1,146 @@
+
+
+
+
+CMSIS DSP Software Library: arm_matrix_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_matrix_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point matrix structure.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numRows
uint16_t numCols
float32_t * pData

+
Detailed Description

+
Instance structure for the floating-point matrix structure. 

+
Examples: 

+
arm_class_marks_example_f32.c, and arm_matrix_example_f32.c.

+

+

+
Definition at line 1337 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_matrix_instance_f32::numRows

+

+

+
number of rows of the matrix. 

+
+
Definition at line 1339 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_matrix_instance_f32::numCols

+

+

+
number of columns of the matrix. 

+
+
Definition at line 1340 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_matrix_instance_f32::pData

+

+

+
points to the data of the matrix. 

+
+
Definition at line 1341 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__matrix__instance__q15.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__matrix__instance__q15.html
new file mode 100644
index 000000000..ad220397d
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__matrix__instance__q15.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_matrix_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_matrix_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 matrix structure.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numRows
uint16_t numCols
q15_t * pData

+
Detailed Description

+
Instance structure for the Q15 matrix structure. 

+
+
Definition at line 1348 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_matrix_instance_q15::numRows

+

+

+
number of rows of the matrix. 

+
+
Definition at line 1350 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_matrix_instance_q15::numCols

+

+

+
number of columns of the matrix. 

+
+
Definition at line 1351 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_matrix_instance_q15::pData

+

+

+
points to the data of the matrix. 

+
+
Definition at line 1352 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__matrix__instance__q31.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__matrix__instance__q31.html
new file mode 100644
index 000000000..655ce0b4e
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__matrix__instance__q31.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_matrix_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_matrix_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 matrix structure.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numRows
uint16_t numCols
q31_t * pData

+
Detailed Description

+
Instance structure for the Q31 matrix structure. 

+
+
Definition at line 1360 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_matrix_instance_q31::numRows

+

+

+
number of rows of the matrix. 

+
+
Definition at line 1362 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_matrix_instance_q31::numCols

+

+

+
number of columns of the matrix. 

+
+
Definition at line 1363 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_matrix_instance_q31::pData

+

+

+
points to the data of the matrix. 

+
+
Definition at line 1364 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__pid__instance__f32.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__pid__instance__f32.html
new file mode 100644
index 000000000..9dfc2579a
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__pid__instance__f32.html
@@ -0,0 +1,211 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_pid_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point PID Control.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+
+

+Data Fields
float32_t A0
float32_t A1
float32_t A2
float32_t state [3]
float32_t Kp
float32_t Ki
float32_t Kd

+
Detailed Description

+
Instance structure for the floating-point PID Control. 

+
+
Definition at line 1697 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t arm_pid_instance_f32::A0

+

+

+
The derived gain, A0 = Kp + Ki + Kd . 

+
+
Definition at line 1699 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_pid_instance_f32::A1

+

+

+
The derived gain, A1 = -Kp - 2Kd. 

+
+
Definition at line 1700 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_pid_instance_f32::A2

+

+

+
The derived gain, A2 = Kd . 

+
+
Definition at line 1701 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_pid_instance_f32::state[3]

+

+

+
The state array of length 3. 

+
+
Definition at line 1702 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_pid_instance_f32::Kp

+

+

+
The proportional gain. 

+
+
Definition at line 1703 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_pid_instance_f32::Ki

+

+

+
The integral gain. 

+
+
Definition at line 1704 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_pid_instance_f32::Kd

+

+

+
The derivative gain. 

+
+
Definition at line 1705 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__pid__instance__q15.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__pid__instance__q15.html
new file mode 100644
index 000000000..a39c90993
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__pid__instance__q15.html
@@ -0,0 +1,194 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_pid_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 PID Control.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+

+Data Fields
q15_t A0
q31_t A1
q15_t state [3]
q15_t Kp
q15_t Ki
q15_t Kd

+
Detailed Description

+
Instance structure for the Q15 PID Control. 

+
+
Definition at line 1664 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
q15_t arm_pid_instance_q15::A0

+

+

+
The derived gain, A0 = Kp + Ki + Kd . 

+
+
Definition at line 1666 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_pid_instance_q15::A1

+

+

+
The derived gain A1 = -Kp - 2Kd | Kd. 

+
+
Definition at line 1671 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t arm_pid_instance_q15::state[3]

+

+

+
The state array of length 3. 

+
+
Definition at line 1673 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t arm_pid_instance_q15::Kp

+

+

+
The proportional gain. 

+
+
Definition at line 1674 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t arm_pid_instance_q15::Ki

+

+

+
The integral gain. 

+
+
Definition at line 1675 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t arm_pid_instance_q15::Kd

+

+

+
The derivative gain. 

+
+
Definition at line 1676 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__pid__instance__q31.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__pid__instance__q31.html
new file mode 100644
index 000000000..ee06a18ca
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__pid__instance__q31.html
@@ -0,0 +1,211 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_pid_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 PID Control.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+
+

+Data Fields
q31_t A0
q31_t A1
q31_t A2
q31_t state [3]
q31_t Kp
q31_t Ki
q31_t Kd

+
Detailed Description

+
Instance structure for the Q31 PID Control. 

+
+
Definition at line 1682 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
q31_t arm_pid_instance_q31::A0

+

+

+
The derived gain, A0 = Kp + Ki + Kd . 

+
+
Definition at line 1684 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_pid_instance_q31::A1

+

+

+
The derived gain, A1 = -Kp - 2Kd. 

+
+
Definition at line 1685 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_pid_instance_q31::A2

+

+

+
The derived gain, A2 = Kd . 

+
+
Definition at line 1686 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_pid_instance_q31::state[3]

+

+

+
The state array of length 3. 

+
+
Definition at line 1687 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_pid_instance_q31::Kp

+

+

+
The proportional gain. 

+
+
Definition at line 1688 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_pid_instance_q31::Ki

+

+

+
The integral gain. 

+
+
Definition at line 1689 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_pid_instance_q31::Kd

+

+

+
The derivative gain. 

+
+
Definition at line 1690 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__rfft__instance__f32.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__rfft__instance__f32.html
new file mode 100644
index 000000000..852ee354c
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__rfft__instance__f32.html
@@ -0,0 +1,228 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_rfft_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point RFFT/RIFFT function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+
+
+

+Data Fields
uint32_t fftLenReal
uint16_t fftLenBy2
uint8_t ifftFlagR
uint8_t bitReverseFlagR
uint32_t twidCoefRModifier
float32_t * pTwiddleAReal
float32_t * pTwiddleBReal
arm_cfft_radix4_instance_f32 * pCfft

+
Detailed Description

+
Instance structure for the floating-point RFFT/RIFFT function. 

+
+
Definition at line 2188 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_rfft_instance_f32::fftLenReal

+

+

+
length of the real FFT. 

+
+
Definition at line 2190 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_rfft_instance_f32::fftLenBy2

+

+

+
length of the complex FFT. 

+
+
Definition at line 2191 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_rfft_instance_f32::ifftFlagR

+

+

+
flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. 

+
+
Definition at line 2192 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_rfft_instance_f32::bitReverseFlagR

+

+

+
flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. 

+
+
Definition at line 2193 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_rfft_instance_f32::twidCoefRModifier

+

+

+
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+
+
Definition at line 2194 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_rfft_instance_f32::pTwiddleAReal

+

+

+
points to the real twiddle factor table. 

+
+
Definition at line 2195 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_rfft_instance_f32::pTwiddleBReal

+

+

+
points to the imag twiddle factor table. 

+
+
Definition at line 2196 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_cfft_radix4_instance_f32* arm_rfft_instance_f32::pCfft

+

+

+
points to the complex FFT instance. 

+
+
Definition at line 2197 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__rfft__instance__q15.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__rfft__instance__q15.html
new file mode 100644
index 000000000..7f5a1b2ed
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__rfft__instance__q15.html
@@ -0,0 +1,228 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_rfft_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 RFFT/RIFFT function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+
+
+

+Data Fields
uint32_t fftLenReal
uint32_t fftLenBy2
uint8_t ifftFlagR
uint8_t bitReverseFlagR
uint32_t twidCoefRModifier
q15_t * pTwiddleAReal
q15_t * pTwiddleBReal
arm_cfft_radix4_instance_q15 * pCfft

+
Detailed Description

+
Instance structure for the Q15 RFFT/RIFFT function. 

+
+
Definition at line 2156 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_rfft_instance_q15::fftLenReal

+

+

+
length of the real FFT. 

+
+
Definition at line 2158 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_rfft_instance_q15::fftLenBy2

+

+

+
length of the complex FFT. 

+
+
Definition at line 2159 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_rfft_instance_q15::ifftFlagR

+

+

+
flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. 

+
+
Definition at line 2160 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_rfft_instance_q15::bitReverseFlagR

+

+

+
flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. 

+
+
Definition at line 2161 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_rfft_instance_q15::twidCoefRModifier

+

+

+
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+
+
Definition at line 2162 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_rfft_instance_q15::pTwiddleAReal

+

+

+
points to the real twiddle factor table. 

+
+
Definition at line 2163 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_rfft_instance_q15::pTwiddleBReal

+

+

+
points to the imag twiddle factor table. 

+
+
Definition at line 2164 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_cfft_radix4_instance_q15* arm_rfft_instance_q15::pCfft

+

+

+
points to the complex FFT instance. 

+
+
Definition at line 2165 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__rfft__instance__q31.html b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__rfft__instance__q31.html
new file mode 100644
index 000000000..50d6ce98a
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/structarm__rfft__instance__q31.html
@@ -0,0 +1,228 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_rfft_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 RFFT/RIFFT function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+
+
+

+Data Fields
uint32_t fftLenReal
uint32_t fftLenBy2
uint8_t ifftFlagR
uint8_t bitReverseFlagR
uint32_t twidCoefRModifier
q31_t * pTwiddleAReal
q31_t * pTwiddleBReal
arm_cfft_radix4_instance_q31 * pCfft

+
Detailed Description

+
Instance structure for the Q31 RFFT/RIFFT function. 

+
+
Definition at line 2172 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_rfft_instance_q31::fftLenReal

+

+

+
length of the real FFT. 

+
+
Definition at line 2174 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_rfft_instance_q31::fftLenBy2

+

+

+
length of the complex FFT. 

+
+
Definition at line 2175 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_rfft_instance_q31::ifftFlagR

+

+

+
flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. 

+
+
Definition at line 2176 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_rfft_instance_q31::bitReverseFlagR

+

+

+
flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. 

+
+
Definition at line 2177 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_rfft_instance_q31::twidCoefRModifier

+

+

+
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+
+
Definition at line 2178 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_rfft_instance_q31::pTwiddleAReal

+

+

+
points to the real twiddle factor table. 

+
+
Definition at line 2179 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_rfft_instance_q31::pTwiddleBReal

+

+

+
points to the imag twiddle factor table. 

+
+
Definition at line 2180 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_cfft_radix4_instance_q31* arm_rfft_instance_q31::pCfft

+

+

+
points to the complex FFT instance. 

+
+
Definition at line 2181 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/tab_a.png b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/tab_a.png
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/tab_h.png b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/tab_h.png
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/tab_s.png b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/tab_s.png
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diff --git a/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/tabs.css b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/tabs.css
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--- /dev/null
+++ b/hardware/sam/system/CMSIS/Documentation/DSP_Lib/html/tabs.css
@@ -0,0 +1,59 @@
+.tabs, .tabs2, .tabs3 {
+    background-image: url('tab_b.png');
+    width: 100%;
+    z-index: 101;
+    font-size: 13px;
+}
+
+.tabs2 {
+    font-size: 10px;
+}
+.tabs3 {
+    font-size: 9px;
+}
+
+.tablist {
+    margin: 0;
+    padding: 0;
+    display: table;
+}
+
+.tablist li {
+    float: left;
+    display: table-cell;
+    background-image: url('tab_b.png');
+    line-height: 36px;
+    list-style: none;
+}
+
+.tablist a {
+    display: block;
+    padding: 0 20px;
+    font-weight: bold;
+    background-image:url('tab_s.png');
+    background-repeat:no-repeat;
+    background-position:right;
+    color: #283A5D;
+    text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
+    text-decoration: none;
+    outline: none;
+}
+
+.tabs3 .tablist a {
+    padding: 0 10px;
+}
+
+.tablist a:hover {
+    background-image: url('tab_h.png');
+    background-repeat:repeat-x;
+    color: #fff;
+    text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);
+    text-decoration: none;
+}
+
+.tablist li.current a {
+    background-image: url('tab_a.png');
+    background-repeat:repeat-x;
+    color: #fff;
+    text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);
+}
diff --git a/hardware/sam/system/CMSIS/Include/arm_common_tables.h b/hardware/sam/system/CMSIS/Include/arm_common_tables.h
new file mode 100644
index 000000000..7245c4f12
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Include/arm_common_tables.h
@@ -0,0 +1,35 @@
+/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved. 
+* 
+* $Date:        11. November 2010  
+* $Revision: 	V1.0.2  
+* 
+* Project: 	    CMSIS DSP Library 
+* Title:	    arm_common_tables.h 
+* 
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions 
+* 
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.2 2010/11/11 
+*    Documentation updated.  
+* 
+* Version 1.0.1 2010/10/05  
+*    Production release and review comments incorporated. 
+* 
+* Version 1.0.0 2010/09/20  
+*    Production release and review comments incorporated. 
+* -------------------------------------------------------------------- */ 
+ 
+#ifndef _ARM_COMMON_TABLES_H 
+#define _ARM_COMMON_TABLES_H 
+ 
+#include "arm_math.h" 
+ 
+extern uint16_t armBitRevTable[256]; 
+extern q15_t armRecipTableQ15[64]; 
+extern q31_t armRecipTableQ31[64]; 
+extern const q31_t realCoefAQ31[1024];
+extern const q31_t realCoefBQ31[1024];
+ 
+#endif /*  ARM_COMMON_TABLES_H */ 
diff --git a/hardware/sam/system/CMSIS/Include/arm_math.h b/hardware/sam/system/CMSIS/Include/arm_math.h
new file mode 100644
index 000000000..ffa03b6fd
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Include/arm_math.h
@@ -0,0 +1,7051 @@
+/* ----------------------------------------------------------------------   
+ * Copyright (C) 2010 ARM Limited. All rights reserved.   
+ *   
+ * $Date:        15. July 2011  
+ * $Revision: 	V1.0.10  
+ *   
+ * Project: 	    CMSIS DSP Library   
+ * Title:	     arm_math.h
+ *   
+ * Description:	 Public header file for CMSIS DSP Library
+ *   
+ * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+ *  
+ * Version 1.0.10 2011/7/15 
+ *    Big Endian support added and Merged M0 and M3/M4 Source code.  
+ *   
+ * Version 1.0.3 2010/11/29  
+ *    Re-organized the CMSIS folders and updated documentation.   
+ *    
+ * Version 1.0.2 2010/11/11   
+ *    Documentation updated.    
+ *   
+ * Version 1.0.1 2010/10/05    
+ *    Production release and review comments incorporated.   
+ *   
+ * Version 1.0.0 2010/09/20    
+ *    Production release and review comments incorporated.   
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   *
+   * This user manual describes the CMSIS DSP software library, 
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of modules each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values. 
+   *
+   * Processor Support
+   *
+   * The library is completely written in C and is fully CMSIS compliant. 
+   * High performance is achieved through maximum use of Cortex-M4 intrinsics. 
+   *
+   * The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor,
+   * with the DSP intrinsics being emulated through software. 
+   *
+   *
+   * Toolchain Support
+   *
+   * The library has been developed and tested with MDK-ARM version 4.21. 
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Using the Library
+   *
+   * The library installer contains prebuilt versions of the libraries in the Lib folder.
+   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
+   *
+   * The library functions are declared in the public file arm_math.h which is placed in the Include folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single 
+   * public header file  arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. 
+   * Define the appropriate pre processor MACRO ARM_MATH_CM4 or  ARM_MATH_CM3 or 
+   * ARM_MATH_CM0 depending on the target processor in the application.
+   *
+   * Examples
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Building the Library
+   *
+   * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\DSP_Lib\Source\ARM folder.
+   * - arm_cortexM0b_math.uvproj
+   * - arm_cortexM0l_math.uvproj
+   * - arm_cortexM3b_math.uvproj
+   * - arm_cortexM3l_math.uvproj  
+   * - arm_cortexM4b_math.uvproj
+   * - arm_cortexM4l_math.uvproj
+   * - arm_cortexM4bf_math.uvproj
+   * - arm_cortexM4lf_math.uvproj
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * ARM_MATH_CMx:
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on cortex-M0 target.
+   *
+   * ARM_MATH_BIG_ENDIAN:
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * ARM_MATH_MATRIX_CHECK:
+   * Define macro for checking on the input and output sizes of matrices
+   *
+   * ARM_MATH_ROUNDING:
+   * Define macro for rounding on support functions
+   *
+   * __FPU_PRESENT:
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries 
+   *
+   *
+   * The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above.
+   *
+   * Copyright Notice
+   *
+   * Copyright (C) 2010 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * 

+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size numRows X numCols
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * 
+ *     pData[i*numCols + j]
+ * 

+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function arm_mat_init_f32(), arm_mat_init_q31()
+ * and arm_mat_init_q15() for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ * 

+ * where nRows specifies the number of rows, nColumns
+ * specifies the number of columns, and pData points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * 
+ *     ARM_MATH_SIZE_MISMATCH
+ * 

+ * Otherwise the functions return
+ * 
+ *     ARM_MATH_SUCCESS
+ * 

+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the #define
+ * 
+ *     ARM_MATH_MATRIX_CHECK
+ * 

+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return ARM_MATH_SUCCESS.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC              /* disable NVIC and Systick functions */
+
+#if defined (ARM_MATH_CM4)
+  #include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+  #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+  #include "core_cm0.h"
+#else
+#include "ARMCM4.h"
+#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
+#endif
+
+#undef  __CMSIS_GENERIC              /* enable NVIC and Systick functions */
+#include "string.h"
+    #include "math.h"
+#ifdef	__cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31 			(0x100)
+#define DELTA_Q15 			0x5
+#define INDEX_MASK 			0x0000003F
+#define PI					3.14159265358979f
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define TABLE_SIZE			256
+#define TABLE_SPACING_Q31	0x800000
+#define TABLE_SPACING_Q15	0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING			0xB60B61
+
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+    {
+      ARM_MATH_SUCCESS = 0,              /**< No error */
+      ARM_MATH_ARGUMENT_ERROR = -1,      /**< One or more arguments are incorrect */
+      ARM_MATH_LENGTH_ERROR = -2,        /**< Length of data buffer is incorrect */
+      ARM_MATH_SIZE_MISMATCH = -3,       /**< Size of matrices is not compatible with the operation. */
+      ARM_MATH_NANINF = -4,              /**< Not-a-number (NaN) or infinity is generated */
+      ARM_MATH_SINGULAR = -5,            /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+      ARM_MATH_TEST_FAILURE = -6         /**< Test Failed  */
+    } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#define __SIMD32(addr)  (*(int32_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
+                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+
+#endif
+
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else								
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+								
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  static __INLINE q31_t clip_q63_to_q31(
+					q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  static __INLINE q15_t clip_q63_to_q15(
+					q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  static __INLINE q7_t clip_q31_to_q7(
+				      q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  static __INLINE q15_t clip_q31_to_q15(
+					q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  static __INLINE q63_t mult32x64(
+				  q63_t x,
+				  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+
+#if defined (ARM_MATH_CM0) && defined ( __CC_ARM   )
+#define __CLZ __clz
+#endif 
+
+#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
+
+  static __INLINE  uint32_t __CLZ(q31_t data);
+
+
+  static __INLINE uint32_t __CLZ(q31_t data)
+  {
+	  uint32_t count = 0;
+	  uint32_t mask = 0x80000000;
+
+	  while((data & mask) ==  0)
+	  {
+		  count += 1u;
+		  mask = mask >> 1u;
+	  }
+
+	  return(count);
+
+  }
+
+#endif 
+
+  /**
+   * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type.
+   */
+
+  static __INLINE uint32_t arm_recip_q31(
+					 q31_t in,
+					 q31_t * dst,
+					 q31_t * pRecipTable)
+  {
+
+    uint32_t out, tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if(in > 0)
+      {
+	signBits = __CLZ(in) - 1;
+      }
+    else
+      {
+	signBits = __CLZ(-in) - 1;
+      }
+
+    /* Convert input sample to 1.31 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t) (in >> 24u);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+      {
+	tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+	tempVal = 0x7FFFFFFF - tempVal;
+	/*      1.31 with exp 1 */
+	//out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+	out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+      }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+
+  }
+
+  /**
+   * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type.
+   */
+  static __INLINE uint32_t arm_recip_q15(
+					 q15_t in,
+					 q15_t * dst,
+					 q15_t * pRecipTable)
+  {
+
+    uint32_t out = 0, tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if(in > 0)
+      {
+	signBits = __CLZ(in) - 17;
+      }
+    else
+      {
+	signBits = __CLZ(-in) - 17;
+      }
+
+    /* Convert input sample to 1.15 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = in >> 8;
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0; i < 2; i++)
+      {
+	tempVal = (q15_t) (((q31_t) in * out) >> 15);
+	tempVal = 0x7FFF - tempVal;
+	/*      1.15 with exp 1 */
+	out = (q15_t) (((q31_t) out * tempVal) >> 14);
+      }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+
+  }
+
+
+  /*
+   * @brief C custom defined intrinisic function for only M0 processors
+   */
+#if defined(ARM_MATH_CM0)
+
+  static __INLINE q31_t __SSAT(
+			       q31_t x,
+			       uint32_t y)
+  {
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++)
+      {
+	posMax = posMax * 2;
+      }
+
+    if(x > 0)
+      {
+	posMax = (posMax - 1);
+
+	if(x > posMax)
+	  {
+	    x = posMax;
+	  }
+      }
+    else
+      {
+	negMin = -posMax;
+
+	if(x < negMin)
+	  {
+	    x = negMin;
+	  }
+      }
+    return (x);
+
+
+  }
+
+#endif /* end of ARM_MATH_CM0 */
+
+
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD8(
+				q31_t x,
+				q31_t y)
+  {
+
+    q31_t sum;
+    q7_t r, s, t, u;
+
+    r = (char) x;
+    s = (char) y;
+
+    r = __SSAT((q31_t) (r + s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+    sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB8(
+				q31_t x,
+				q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s, t, u;
+
+    r = (char) x;
+    s = (char) y;
+
+    r = __SSAT((r - s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+    sum =
+      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD16(
+				 q31_t x,
+				 q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = __SSAT(r + s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHADD16(
+				  q31_t x,
+				  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) + (s >> 1));
+    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB16(
+				 q31_t x,
+				 q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = __SSAT(r - s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSUB16(
+				  q31_t x,
+				  q31_t y)
+  {
+
+    q31_t diff;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) - (s >> 1));
+    s = (((x >> 17) - (y >> 17)) << 16);
+
+    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return diff;
+  }
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QASX(
+			       q31_t x,
+			       q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHASX(
+				q31_t x,
+				q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) - (y >> 17));
+    s = (((x >> 17) + (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSAX(
+			       q31_t x,
+			       q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSAX(
+				q31_t x,
+				q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) + (y >> 17));
+    s = (((x >> 17) - (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSDX(
+				 q31_t x,
+				 q31_t y)
+  {
+
+    return ((q31_t)(((short) x * (short) (y >> 16)) -
+		    ((short) (x >> 16) * (short) y)));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUADX(
+				 q31_t x,
+				 q31_t y)
+  {
+
+    return ((q31_t)(((short) x * (short) (y >> 16)) +
+		    ((short) (x >> 16) * (short) y)));
+  }
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD(
+			       q31_t x,
+			       q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x + y);
+  }
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB(
+			       q31_t x,
+			       q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x - y);
+  }
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLAD(
+				q31_t x,
+				q31_t y,
+				q31_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+            ((short) x * (short) y));
+  }
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLADX(
+				 q31_t x,
+				 q31_t y,
+				 q31_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y)) +
+            ((short) x * (short) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLSDX(
+				 q31_t x,
+				 q31_t y,
+				 q31_t sum)
+  {
+
+    return (sum - ((short) (x >> 16) * (short) (y)) +
+            ((short) x * (short) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALD(
+				 q31_t x,
+				 q31_t y,
+				 q63_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+            ((short) x * (short) y));
+  }
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALDX(
+				  q31_t x,
+				  q31_t y,
+				  q63_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) y)) +
+      ((short) x * (short) (y >> 16));
+  }
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUAD(
+				q31_t x,
+				q31_t y)
+  {
+
+    return (((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSD(
+				q31_t x,
+				q31_t y)
+  {
+
+    return (-((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+
+
+
+#endif /* (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in] *S points to an instance of the Q7 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q7(
+		  const arm_fir_instance_q7 * S,
+		   q7_t * pSrc,
+		  q7_t * pDst,
+		  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] *S points to an instance of the Q7 FIR structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed.
+   * @return none
+   */
+  void arm_fir_init_q7(
+		       arm_fir_instance_q7 * S,
+		       uint16_t numTaps,
+		       q7_t * pCoeffs,
+		       q7_t * pState,
+		       uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in] *S points to an instance of the Q15 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q15(
+		   const arm_fir_instance_q15 * S,
+		    q15_t * pSrc,
+		   q15_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q15(
+			const arm_fir_instance_q15 * S,
+			 q15_t * pSrc,
+			q15_t * pDst,
+			uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * numTaps is not a supported value.
+   */
+   
+       arm_status arm_fir_init_q15(
+			      arm_fir_instance_q15 * S,
+			      uint16_t numTaps,
+			      q15_t * pCoeffs,
+			      q15_t * pState,
+			      uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in] *S points to an instance of the Q31 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q31(
+		   const arm_fir_instance_q31 * S,
+		    q31_t * pSrc,
+		   q31_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q31(
+			const arm_fir_instance_q31 * S,
+			 q31_t * pSrc,
+			q31_t * pDst,
+			uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] *S points to an instance of the Q31 FIR structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return 		none.
+   */
+  void arm_fir_init_q31(
+			arm_fir_instance_q31 * S,
+			uint16_t numTaps,
+			q31_t * pCoeffs,
+			q31_t * pState,
+			uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in] *S points to an instance of the floating-point FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_f32(
+		   const arm_fir_instance_f32 * S,
+		    float32_t * pSrc,
+		   float32_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return    	none.
+   */
+  void arm_fir_init_f32(
+			arm_fir_instance_f32 * S,
+			uint16_t numTaps,
+			float32_t * pCoeffs,
+			float32_t * pState,
+			uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q15;
+
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+
+
+  } arm_biquad_casd_df1_inst_f32;
+
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q15(
+				  const arm_biquad_casd_df1_inst_q15 * S,
+				   q15_t * pSrc,
+				  q15_t * pDst,
+				  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q15(
+				       arm_biquad_casd_df1_inst_q15 * S,
+				       uint8_t numStages,
+				       q15_t * pCoeffs,
+				       q15_t * pState,
+				       int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q15(
+				       const arm_biquad_casd_df1_inst_q15 * S,
+				        q15_t * pSrc,
+				       q15_t * pDst,
+				       uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q31(
+				  const arm_biquad_casd_df1_inst_q31 * S,
+				   q31_t * pSrc,
+				  q31_t * pDst,
+				  uint32_t blockSize);
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q31(
+				       const arm_biquad_casd_df1_inst_q31 * S,
+				        q31_t * pSrc,
+				       q31_t * pDst,
+				       uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages      number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q31(
+				       arm_biquad_casd_df1_inst_q31 * S,
+				       uint8_t numStages,
+				       q31_t * pCoeffs,
+				       q31_t * pState,
+				       int8_t postShift);
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_f32(
+				  const arm_biquad_casd_df1_inst_f32 * S,
+				   float32_t * pSrc,
+				  float32_t * pDst,
+				  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_f32(
+				       arm_biquad_casd_df1_inst_f32 * S,
+				       uint8_t numStages,
+				       float32_t * pCoeffs,
+				       float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q31;
+
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_f32(
+			     const arm_matrix_instance_f32 * pSrcA,
+			     const arm_matrix_instance_f32 * pSrcB,
+			     arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q15(
+			     const arm_matrix_instance_q15 * pSrcA,
+			     const arm_matrix_instance_q15 * pSrcB,
+			     arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q31(
+			     const arm_matrix_instance_q31 * pSrcA,
+			     const arm_matrix_instance_q31 * pSrcB,
+			     arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH
+   * or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_f32(
+			       const arm_matrix_instance_f32 * pSrc,
+			       arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH
+   * or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q15(
+			       const arm_matrix_instance_q15 * pSrc,
+			       arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH
+   * or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q31(
+			       const arm_matrix_instance_q31 * pSrc,
+			       arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_f32(
+			      const arm_matrix_instance_f32 * pSrcA,
+			      const arm_matrix_instance_f32 * pSrcB,
+			      arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q15(
+			      const arm_matrix_instance_q15 * pSrcA,
+			      const arm_matrix_instance_q15 * pSrcB,
+			      arm_matrix_instance_q15 * pDst,
+			      q15_t * pState);
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA  points to the first input matrix structure
+   * @param[in]       *pSrcB  points to the second input matrix structure
+   * @param[out]      *pDst   points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results  
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q15(
+				   const arm_matrix_instance_q15 * pSrcA,
+				   const arm_matrix_instance_q15 * pSrcB,
+				   arm_matrix_instance_q15 * pDst,
+				   q15_t * pState);
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q31(
+			      const arm_matrix_instance_q31 * pSrcA,
+			      const arm_matrix_instance_q31 * pSrcB,
+			      arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q31(
+				   const arm_matrix_instance_q31 * pSrcA,
+				   const arm_matrix_instance_q31 * pSrcB,
+				   arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_f32(
+			     const arm_matrix_instance_f32 * pSrcA,
+			     const arm_matrix_instance_f32 * pSrcB,
+			     arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q15(
+			     const arm_matrix_instance_q15 * pSrcA,
+			     const arm_matrix_instance_q15 * pSrcB,
+			     arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q31(
+			     const arm_matrix_instance_q31 * pSrcA,
+			     const arm_matrix_instance_q31 * pSrcB,
+			     arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[in]  scale scale factor
+   * @param[out] *pDst points to the output matrix
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_f32(
+			       const arm_matrix_instance_f32 * pSrc,
+			       float32_t scale,
+			       arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q15(
+			       const arm_matrix_instance_q15 * pSrc,
+			       q15_t scaleFract,
+			       int32_t shift,
+			       arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q31(
+			       const arm_matrix_instance_q31 * pSrc,
+			       q31_t scaleFract,
+			       int32_t shift,
+			       arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q31(
+			arm_matrix_instance_q31 * S,
+			uint16_t nRows,
+			uint16_t nColumns,
+			q31_t   *pData);
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q15(
+			arm_matrix_instance_q15 * S,
+			uint16_t nRows,
+			uint16_t nColumns,
+			q15_t    *pData);
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_f32(
+			arm_matrix_instance_f32 * S,
+			uint16_t nRows,
+			uint16_t nColumns,
+			float32_t   *pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0; 	 /**< The derived gain, A0 = Kp + Ki + Kd . */
+	#ifdef ARM_MATH_CM0  
+	q15_t A1;
+	q15_t A2; 
+	#else 	      
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+	#endif 
+    q15_t state[3];       /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;               /**< The proportional gain. */
+    float32_t Ki;               /**< The integral gain. */
+    float32_t Kd;               /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] *S      points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_f32(
+			arm_pid_instance_f32 * S,
+			int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_f32(
+			 arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q31(
+			arm_pid_instance_q31 * S,
+			int32_t resetStateFlag);
+
+ 
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @return none
+   */
+
+  void arm_pid_reset_q31(
+			 arm_pid_instance_q31 * S);
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q15(
+			arm_pid_instance_q15 * S,
+			int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the q15 PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_q15(
+			 arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;
+    float32_t x1;
+    float32_t xSpacing;
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;	/**< number of rows in the data table. */
+    uint16_t numCols;	/**< number of columns in the data table. */
+    float32_t *pData;	/**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;	/**< number of rows in the data table. */
+    uint16_t numCols;	/**< number of columns in the data table. */
+    q31_t *pData;	/**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;	/**< number of rows in the data table. */
+    uint16_t numCols;	/**< number of columns in the data table. */
+    q15_t *pData;	/**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows; 	/**< number of rows in the data table. */
+    uint16_t numCols;	/**< number of columns in the data table. */
+    q7_t *pData;		/**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q7(
+		    q7_t * pSrcA,
+		    q7_t * pSrcB,
+		   q7_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q15(
+		     q15_t * pSrcA,
+		     q15_t * pSrcB,
+		    q15_t * pDst,
+		    uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q31(
+		     q31_t * pSrcA,
+		     q31_t * pSrcB,
+		    q31_t * pDst,
+		    uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_f32(
+		     float32_t * pSrcA,
+		     float32_t * pSrcB,
+		    float32_t * pDst,
+		    uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t  fftLen;                /**< length of the FFT. */
+    uint8_t   ifftFlag;              /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t   bitReverseFlag;        /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t     *pTwiddle;             /**< points to the twiddle factor table. */
+    uint16_t  *pBitRevTable;         /**< points to the bit reversal table. */
+    uint16_t  twidCoefModifier;      /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t  bitRevFactor;          /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t    fftLen;              /**< length of the FFT. */
+    uint8_t     ifftFlag;            /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t     bitReverseFlag;      /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t       *pTwiddle;           /**< points to the twiddle factor table. */
+    uint16_t    *pBitRevTable;       /**< points to the bit reversal table. */
+    uint16_t    twidCoefModifier;    /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t    bitRevFactor;        /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t     fftLen;               /**< length of the FFT. */
+    uint8_t      ifftFlag;             /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t      bitReverseFlag;       /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t    *pTwiddle;            /**< points to the twiddle factor table. */
+    uint16_t     *pBitRevTable;        /**< points to the bit reversal table. */
+    uint16_t     twidCoefModifier;     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t     bitRevFactor;         /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+	float32_t    onebyfftLen;          /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+  /**
+   * @brief Processing function for the Q15 CFFT/CIFFT.
+   * @param[in]      *S    points to an instance of the Q15 CFFT/CIFFT structure.
+   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+   * @return none.
+   */
+
+  void arm_cfft_radix4_q15(
+			   const arm_cfft_radix4_instance_q15 * S,
+			   q15_t * pSrc);
+
+  /**
+   * @brief Initialization function for the Q15 CFFT/CIFFT.
+   * @param[in,out] *S             points to an instance of the Q15 CFFT/CIFFT structure.
+   * @param[in]     fftLen         length of the FFT.
+   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return        arm_status     function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+   */
+
+  arm_status arm_cfft_radix4_init_q15(
+				      arm_cfft_radix4_instance_q15 * S,
+				      uint16_t fftLen,
+				      uint8_t ifftFlag,
+				      uint8_t bitReverseFlag);
+
+  /**
+   * @brief Processing function for the Q31 CFFT/CIFFT.
+   * @param[in]      *S    points to an instance of the Q31 CFFT/CIFFT structure.
+   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+   * @return none.
+   */
+
+  void arm_cfft_radix4_q31(
+			   const arm_cfft_radix4_instance_q31 * S,
+			   q31_t * pSrc);
+
+  /**
+   * @brief  Initialization function for the Q31 CFFT/CIFFT.
+   * @param[in,out] *S             points to an instance of the Q31 CFFT/CIFFT structure.
+   * @param[in]     fftLen         length of the FFT.
+   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return        arm_status     function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+   */
+  
+  arm_status arm_cfft_radix4_init_q31(
+				      arm_cfft_radix4_instance_q31 * S,
+				      uint16_t fftLen,
+				      uint8_t ifftFlag,
+				      uint8_t bitReverseFlag);
+
+  /**
+   * @brief Processing function for the floating-point CFFT/CIFFT.
+   * @param[in]      *S    points to an instance of the floating-point CFFT/CIFFT structure.
+   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+   * @return none.
+   */
+
+  void arm_cfft_radix4_f32(
+			   const arm_cfft_radix4_instance_f32 * S,
+			   float32_t * pSrc);
+
+  /**
+   * @brief  Initialization function for the floating-point CFFT/CIFFT.
+   * @param[in,out] *S             points to an instance of the floating-point CFFT/CIFFT structure.
+   * @param[in]     fftLen         length of the FFT.
+   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+   */
+  
+  arm_status arm_cfft_radix4_init_f32(
+				      arm_cfft_radix4_instance_f32 * S,
+				      uint16_t fftLen,
+				      uint8_t ifftFlag,
+				      uint8_t bitReverseFlag);
+
+
+
+  /*----------------------------------------------------------------------
+   *		Internal functions prototypes FFT function
+   ----------------------------------------------------------------------*/
+
+  /**
+   * @brief  Core function for the floating-point CFFT butterfly process.
+   * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef           points to the twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+  
+  void arm_radix4_butterfly_f32(
+				float32_t * pSrc,
+				uint16_t fftLen,
+				float32_t * pCoef,
+				uint16_t twidCoefModifier);
+
+  /**
+   * @brief  Core function for the floating-point CIFFT butterfly process.
+   * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef           points to twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @param[in]      onebyfftLen      value of 1/fftLen.
+   * @return none.
+   */
+  
+  void arm_radix4_butterfly_inverse_f32(
+					float32_t * pSrc,
+					uint16_t fftLen,
+					float32_t * pCoef,
+					uint16_t twidCoefModifier,
+					float32_t onebyfftLen);
+
+  /**
+   * @brief  In-place bit reversal function.
+   * @param[in, out] *pSrc        points to the in-place buffer of floating-point data type.
+   * @param[in]      fftSize      length of the FFT.
+   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.
+   * @param[in]      *pBitRevTab  points to the bit reversal table.
+   * @return none.
+   */
+
+  void arm_bitreversal_f32(
+			   float32_t *pSrc,
+			   uint16_t fftSize,
+			   uint16_t bitRevFactor,
+			   uint16_t *pBitRevTab);
+
+  /**
+   * @brief  Core function for the Q31 CFFT butterfly process.
+   * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef           points to twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+  
+  void arm_radix4_butterfly_q31(
+				q31_t *pSrc,
+				uint32_t fftLen,
+				q31_t *pCoef,
+				uint32_t twidCoefModifier);
+
+  /**
+   * @brief  Core function for the Q31 CIFFT butterfly process.
+   * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef           points to twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+  
+  void arm_radix4_butterfly_inverse_q31(
+					q31_t * pSrc,
+					uint32_t fftLen,
+					q31_t * pCoef,
+					uint32_t twidCoefModifier);
+  
+  /**
+   * @brief  In-place bit reversal function.
+   * @param[in, out] *pSrc        points to the in-place buffer of Q31 data type.
+   * @param[in]      fftLen       length of the FFT.
+   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
+   * @param[in]      *pBitRevTab  points to bit reversal table.
+   * @return none.
+   */
+
+  void arm_bitreversal_q31(
+			   q31_t * pSrc,
+			   uint32_t fftLen,
+			   uint16_t bitRevFactor,
+			   uint16_t *pBitRevTab);
+
+  /**
+   * @brief  Core function for the Q15 CFFT butterfly process.
+   * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef16         points to twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+
+  void arm_radix4_butterfly_q15(
+				q15_t *pSrc16,
+				uint32_t fftLen,
+				q15_t *pCoef16,
+				uint32_t twidCoefModifier);
+
+  /**
+   * @brief  Core function for the Q15 CIFFT butterfly process.
+   * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef16         points to twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+
+  void arm_radix4_butterfly_inverse_q15(
+					q15_t *pSrc16,
+					uint32_t fftLen,
+					q15_t *pCoef16,
+					uint32_t twidCoefModifier);
+
+  /**
+   * @brief  In-place bit reversal function.
+   * @param[in, out] *pSrc        points to the in-place buffer of Q15 data type.
+   * @param[in]      fftLen       length of the FFT.
+   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
+   * @param[in]      *pBitRevTab  points to bit reversal table.
+   * @return none.
+   */
+
+  void arm_bitreversal_q15(
+			   q15_t * pSrc,
+			   uint32_t fftLen,
+			   uint16_t bitRevFactor,
+			   uint16_t *pBitRevTab);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint32_t fftLenBy2;                       /**< length of the complex FFT. */
+    uint8_t  ifftFlagR;                       /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+	uint8_t  bitReverseFlagR;                 /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */  
+    q15_t    *pTwiddleAReal;                  /**< points to the real twiddle factor table. */
+    q15_t    *pTwiddleBReal;                  /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_q15 *pCfft;	  /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint32_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t  ifftFlagR;                         /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+	uint8_t  bitReverseFlagR;                   /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t    *pTwiddleAReal;                    /**< points to the real twiddle factor table. */
+    q31_t    *pTwiddleBReal;                    /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_q31 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t  fftLenReal;                       /**< length of the real FFT. */
+    uint16_t  fftLenBy2;                        /**< length of the complex FFT. */
+    uint8_t   ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t   bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+	uint32_t  twidCoefRModifier;                /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  /**
+   * @brief Processing function for the Q15 RFFT/RIFFT.
+   * @param[in]  *S    points to an instance of the Q15 RFFT/RIFFT structure.
+   * @param[in]  *pSrc points to the input buffer.
+   * @param[out] *pDst points to the output buffer.
+   * @return none.
+   */
+
+  void arm_rfft_q15(
+		    const arm_rfft_instance_q15 * S,
+		    q15_t * pSrc,
+		    q15_t * pDst);
+
+  /**
+   * @brief  Initialization function for the Q15 RFFT/RIFFT.
+   * @param[in, out] *S             points to an instance of the Q15 RFFT/RIFFT structure.
+   * @param[in]      *S_CFFT        points to an instance of the Q15 CFFT/CIFFT structure.
+   * @param[in]      fftLenReal     length of the FFT.
+   * @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+   * @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+   */
+
+  arm_status arm_rfft_init_q15(
+			       arm_rfft_instance_q15 * S,
+			       arm_cfft_radix4_instance_q15 * S_CFFT,
+			       uint32_t fftLenReal,
+			       uint32_t ifftFlagR,
+			       uint32_t bitReverseFlag);
+
+  /**
+   * @brief Processing function for the Q31 RFFT/RIFFT.
+   * @param[in]  *S    points to an instance of the Q31 RFFT/RIFFT structure.
+   * @param[in]  *pSrc points to the input buffer.
+   * @param[out] *pDst points to the output buffer.
+   * @return none.
+   */
+
+  void arm_rfft_q31(
+		    const arm_rfft_instance_q31 * S,
+		    q31_t * pSrc,
+		    q31_t * pDst);
+
+  /**
+   * @brief  Initialization function for the Q31 RFFT/RIFFT.
+   * @param[in, out] *S             points to an instance of the Q31 RFFT/RIFFT structure.
+   * @param[in, out] *S_CFFT        points to an instance of the Q31 CFFT/CIFFT structure.
+   * @param[in]      fftLenReal     length of the FFT.
+   * @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+   * @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+   */
+
+  arm_status arm_rfft_init_q31(
+			       arm_rfft_instance_q31 * S,
+			       arm_cfft_radix4_instance_q31 * S_CFFT,
+			       uint32_t fftLenReal,
+			       uint32_t ifftFlagR,
+			       uint32_t bitReverseFlag);
+
+  /**
+   * @brief  Initialization function for the floating-point RFFT/RIFFT.
+   * @param[in,out] *S             points to an instance of the floating-point RFFT/RIFFT structure.
+   * @param[in,out] *S_CFFT        points to an instance of the floating-point CFFT/CIFFT structure.
+   * @param[in]     fftLenReal     length of the FFT.
+   * @param[in]     ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+   */
+
+  arm_status arm_rfft_init_f32(
+			       arm_rfft_instance_f32 * S,
+			       arm_cfft_radix4_instance_f32 * S_CFFT,
+			       uint32_t fftLenReal,
+			       uint32_t ifftFlagR,
+			       uint32_t bitReverseFlag);
+
+  /**
+   * @brief Processing function for the floating-point RFFT/RIFFT.
+   * @param[in]  *S    points to an instance of the floating-point RFFT/RIFFT structure.
+   * @param[in]  *pSrc points to the input buffer.
+   * @param[out] *pDst points to the output buffer.
+   * @return none.
+   */
+
+  void arm_rfft_f32(
+		    const arm_rfft_instance_f32 * S,
+		    float32_t * pSrc,
+		    float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    float32_t normalize;                /**< normalizing factor. */
+    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;              /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_f32(
+			       arm_dct4_instance_f32 * S,
+			       arm_rfft_instance_f32 * S_RFFT,
+			       arm_cfft_radix4_instance_f32 * S_CFFT,
+			       uint16_t N,
+			       uint16_t Nby2,
+			       float32_t normalize);
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_f32(
+		    const arm_dct4_instance_f32 * S,
+		    float32_t * pState,
+		    float32_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q31_t normalize;                    /**< normalizing factor. */
+    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q31(
+			       arm_dct4_instance_q31 * S,
+			       arm_rfft_instance_q31 * S_RFFT,
+			       arm_cfft_radix4_instance_q31 * S_CFFT,
+			       uint16_t N,
+			       uint16_t Nby2,
+			       q31_t normalize);
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q31(
+		    const arm_dct4_instance_q31 * S,
+		    q31_t * pState,
+		    q31_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q15_t normalize;                    /**< normalizing factor. */
+    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q15(
+			       arm_dct4_instance_q15 * S,
+			       arm_rfft_instance_q15 * S_RFFT,
+			       arm_cfft_radix4_instance_q15 * S_CFFT,
+			       uint16_t N,
+			       uint16_t Nby2,
+			       q15_t normalize);
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q15(
+		    const arm_dct4_instance_q15 * S,
+		    q15_t * pState,
+		    q15_t * pInlineBuffer);
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_f32(
+		   float32_t * pSrcA,
+		   float32_t * pSrcB,
+		   float32_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q7(
+		  q7_t * pSrcA,
+		  q7_t * pSrcB,
+		  q7_t * pDst,
+		  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q15(
+		    q15_t * pSrcA,
+		    q15_t * pSrcB,
+		   q15_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q31(
+		    q31_t * pSrcA,
+		    q31_t * pSrcB,
+		   q31_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_f32(
+		    float32_t * pSrcA,
+		    float32_t * pSrcB,
+		   float32_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q7(
+		   q7_t * pSrcA,
+		   q7_t * pSrcB,
+		  q7_t * pDst,
+		  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q15(
+		    q15_t * pSrcA,
+		    q15_t * pSrcB,
+		   q15_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q31(
+		    q31_t * pSrcA,
+		    q31_t * pSrcB,
+		   q31_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scale scale factor to be applied
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_f32(
+		      float32_t * pSrc,
+		     float32_t scale,
+		     float32_t * pDst,
+		     uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q7(
+		     q7_t * pSrc,
+		    q7_t scaleFract,
+		    int8_t shift,
+		    q7_t * pDst,
+		    uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q15(
+		      q15_t * pSrc,
+		     q15_t scaleFract,
+		     int8_t shift,
+		     q15_t * pDst,
+		     uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q31(
+		      q31_t * pSrc,
+		     q31_t scaleFract,
+		     int8_t shift,
+		     q31_t * pDst,
+		     uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q7(
+		   q7_t * pSrc,
+		  q7_t * pDst,
+		  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_f32(
+		    float32_t * pSrc,
+		   float32_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q15(
+		    q15_t * pSrc,
+		   q15_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q31(
+		    q31_t * pSrc,
+		   q31_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_f32(
+			 float32_t * pSrcA,
+			 float32_t * pSrcB,
+			uint32_t blockSize,
+			float32_t * result);
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q7(
+		        q7_t * pSrcA,
+		        q7_t * pSrcB,
+		       uint32_t blockSize,
+		       q31_t * result);
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q15(
+			 q15_t * pSrcA,
+			 q15_t * pSrcB,
+			uint32_t blockSize,
+			q63_t * result);
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q31(
+			 q31_t * pSrcA,
+			 q31_t * pSrcB,
+			uint32_t blockSize,
+			q63_t * result);
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q7(
+		     q7_t * pSrc,
+		    int8_t shiftBits,
+		    q7_t * pDst,
+		    uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q15(
+		      q15_t * pSrc,
+		     int8_t shiftBits,
+		     q15_t * pDst,
+		     uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q31(
+		      q31_t * pSrc,
+		     int8_t shiftBits,
+		     q31_t * pDst,
+		     uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_f32(
+		       float32_t * pSrc,
+		      float32_t offset,
+		      float32_t * pDst,
+		      uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q7(
+		      q7_t * pSrc,
+		     q7_t offset,
+		     q7_t * pDst,
+		     uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q15(
+		       q15_t * pSrc,
+		      q15_t offset,
+		      q15_t * pDst,
+		      uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q31(
+		       q31_t * pSrc,
+		      q31_t offset,
+		      q31_t * pDst,
+		      uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_f32(
+		       float32_t * pSrc,
+		      float32_t * pDst,
+		      uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q7(
+		      q7_t * pSrc,
+		     q7_t * pDst,
+		     uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q15(
+		       q15_t * pSrc,
+		      q15_t * pDst,
+		      uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q31(
+		       q31_t * pSrc,
+		      q31_t * pDst,
+		      uint32_t blockSize);
+  /**
+   * @brief  Copies the elements of a floating-point vector. 
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_f32(
+		     float32_t * pSrc,
+		    float32_t * pDst,
+		    uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q7 vector. 
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q7(
+		    q7_t * pSrc,
+		   q7_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q15 vector. 
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q15(
+		     q15_t * pSrc,
+		    q15_t * pDst,
+		    uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q31 vector. 
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q31(
+		     q31_t * pSrc,
+		    q31_t * pDst,
+		    uint32_t blockSize);
+  /**
+   * @brief  Fills a constant value into a floating-point vector. 
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_f32(
+		     float32_t value,
+		    float32_t * pDst,
+		    uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector. 
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q7(
+		    q7_t value,
+		   q7_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector. 
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q15(
+		     q15_t value,
+		    q15_t * pDst,
+		    uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector. 
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q31(
+		     q31_t value,
+		    q31_t * pDst,
+		    uint32_t blockSize);
+
+/**  
+ * @brief Convolution of floating-point sequences.  
+ * @param[in] *pSrcA points to the first input sequence.  
+ * @param[in] srcALen length of the first input sequence.  
+ * @param[in] *pSrcB points to the second input sequence.  
+ * @param[in] srcBLen length of the second input sequence.  
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.  
+ * @return none.  
+ */ 
+
+  void arm_conv_f32(
+		     float32_t * pSrcA,
+		    uint32_t srcALen,
+		     float32_t * pSrcB,
+		    uint32_t srcBLen,
+		    float32_t * pDst);
+
+/**  
+ * @brief Convolution of Q15 sequences.  
+ * @param[in] *pSrcA points to the first input sequence.  
+ * @param[in] srcALen length of the first input sequence.  
+ * @param[in] *pSrcB points to the second input sequence.  
+ * @param[in] srcBLen length of the second input sequence.  
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.  
+ * @return none.  
+ */
+
+  void arm_conv_q15(
+		     q15_t * pSrcA,
+		    uint32_t srcALen,
+		     q15_t * pSrcB,
+		    uint32_t srcBLen,
+		    q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q15(
+			  q15_t * pSrcA,
+			 uint32_t srcALen,
+			  q15_t * pSrcB,
+			 uint32_t srcBLen,
+			 q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q31(
+		     q31_t * pSrcA,
+		    uint32_t srcALen,
+		     q31_t * pSrcB,
+		    uint32_t srcBLen,
+		    q31_t * pDst);
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q31(
+			  q31_t * pSrcA,
+			 uint32_t srcALen,
+			  q31_t * pSrcB,
+			 uint32_t srcBLen,
+			 q31_t * pDst);
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q7(
+		    q7_t * pSrcA,
+		   uint32_t srcALen,
+		    q7_t * pSrcB,
+		   uint32_t srcBLen,
+		   q7_t * pDst);
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_f32(
+				   float32_t * pSrcA,
+				  uint32_t srcALen,
+				   float32_t * pSrcB,
+				  uint32_t srcBLen,
+				  float32_t * pDst,
+				  uint32_t firstIndex,
+				  uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q15(
+				   q15_t * pSrcA,
+				  uint32_t srcALen,
+				   q15_t * pSrcB,
+				  uint32_t srcBLen,
+				  q15_t * pDst,
+				  uint32_t firstIndex,
+				  uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q15(
+				        q15_t * pSrcA,
+				       uint32_t srcALen,
+				        q15_t * pSrcB,
+				       uint32_t srcBLen,
+				       q15_t * pDst,
+				       uint32_t firstIndex,
+				       uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q31(
+				   q31_t * pSrcA,
+				  uint32_t srcALen,
+				   q31_t * pSrcB,
+				  uint32_t srcBLen,
+				  q31_t * pDst,
+				  uint32_t firstIndex,
+				  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q31(
+				        q31_t * pSrcA,
+				       uint32_t srcALen,
+				        q31_t * pSrcB,
+				       uint32_t srcBLen,
+				       q31_t * pDst,
+				       uint32_t firstIndex,
+				       uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q7(
+				  q7_t * pSrcA,
+				 uint32_t srcALen,
+				  q7_t * pSrcB,
+				 uint32_t srcBLen,
+				 q7_t * pDst,
+				 uint32_t firstIndex,
+				 uint32_t numPoints);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                      /**< decimation factor. */
+    uint16_t numTaps;               /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                          /**< decimation factor. */
+    uint16_t numTaps;                   /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_f32;
+
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_f32(
+			    const arm_fir_decimate_instance_f32 * S,
+			     float32_t * pSrc,
+			    float32_t * pDst,
+			    uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * blockSize is not a multiple of M.
+   */
+
+  arm_status arm_fir_decimate_init_f32(
+				       arm_fir_decimate_instance_f32 * S,
+				       uint16_t numTaps,
+				       uint8_t M,
+				       float32_t * pCoeffs,
+				       float32_t * pState,
+				       uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q15(
+			    const arm_fir_decimate_instance_q15 * S,
+			     q15_t * pSrc,
+			    q15_t * pDst,
+			    uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q15(
+				 const arm_fir_decimate_instance_q15 * S,
+				  q15_t * pSrc,
+				 q15_t * pDst,
+				 uint32_t blockSize);
+
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * blockSize is not a multiple of M.
+   */
+
+  arm_status arm_fir_decimate_init_q15(
+				       arm_fir_decimate_instance_q15 * S,
+				       uint16_t numTaps,
+				       uint8_t M,
+				       q15_t * pCoeffs,
+				       q15_t * pState,
+				       uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q31(
+			    const arm_fir_decimate_instance_q31 * S,
+			     q31_t * pSrc,
+			    q31_t * pDst,
+			    uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q31(
+				 arm_fir_decimate_instance_q31 * S,
+				  q31_t * pSrc,
+				 q31_t * pDst,
+				 uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * blockSize is not a multiple of M.
+   */
+
+  arm_status arm_fir_decimate_init_q31(
+				       arm_fir_decimate_instance_q31 * S,
+				       uint16_t numTaps,
+				       uint8_t M,
+				       q31_t * pCoeffs,
+				       q31_t * pState,
+				       uint32_t blockSize);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q15(
+			       const arm_fir_interpolate_instance_q15 * S,
+			        q15_t * pSrc,
+			       q15_t * pDst,
+			       uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length numTaps is not a multiple of the interpolation factor L.
+   */
+
+  arm_status arm_fir_interpolate_init_q15(
+					  arm_fir_interpolate_instance_q15 * S,
+					  uint8_t L,
+					  uint16_t numTaps,
+					  q15_t * pCoeffs,
+					  q15_t * pState,
+					  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q31(
+			       const arm_fir_interpolate_instance_q31 * S,
+			        q31_t * pSrc,
+			       q31_t * pDst,
+			       uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length numTaps is not a multiple of the interpolation factor L.
+   */
+
+  arm_status arm_fir_interpolate_init_q31(
+					  arm_fir_interpolate_instance_q31 * S,
+					  uint8_t L,
+					  uint16_t numTaps,
+					  q31_t * pCoeffs,
+					  q31_t * pState,
+					  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_f32(
+			       const arm_fir_interpolate_instance_f32 * S,
+			        float32_t * pSrc,
+			       float32_t * pDst,
+			       uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length numTaps is not a multiple of the interpolation factor L.
+   */
+
+  arm_status arm_fir_interpolate_init_f32(
+					  arm_fir_interpolate_instance_f32 * S,
+					  uint8_t L,
+					  uint16_t numTaps,
+					  float32_t * pCoeffs,
+					  float32_t * pState,
+					  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cas_df1_32x64_q31(
+				    const arm_biquad_cas_df1_32x64_ins_q31 * S,
+				     q31_t * pSrc,
+				    q31_t * pDst,
+				    uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cas_df1_32x64_init_q31(
+					 arm_biquad_cas_df1_32x64_ins_q31 * S,
+					 uint8_t numStages,
+					 q31_t * pCoeffs,
+					 q63_t * pState,
+					 uint8_t postShift);
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t   numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f32(
+				   const arm_biquad_cascade_df2T_instance_f32 * S,
+				    float32_t * pSrc,
+				   float32_t * pDst,
+				   uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f32(
+					arm_biquad_cascade_df2T_instance_f32 * S,
+					uint8_t numStages,
+					float32_t * pCoeffs,
+					float32_t * pState);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages. 
+   * @param[in] *pState points to the state buffer.  The array is of length numStages. 
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q15(
+				arm_fir_lattice_instance_q15 * S,
+				uint16_t numStages,
+				q15_t * pCoeffs,
+				q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_lattice_q15(
+			   const arm_fir_lattice_instance_q15 * S,
+			    q15_t * pSrc,
+			   q15_t * pDst,
+			   uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q31(
+				arm_fir_lattice_instance_q31 * S,
+				uint16_t numStages,
+				q31_t * pCoeffs,
+				q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_q31(
+			   const arm_fir_lattice_instance_q31 * S,
+			    q31_t * pSrc,
+			   q31_t * pDst,
+			   uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+  void arm_fir_lattice_init_f32(
+				arm_fir_lattice_instance_f32 * S,
+				uint16_t numStages,
+				float32_t * pCoeffs,
+				float32_t * pState);
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_f32(
+			   const arm_fir_lattice_instance_f32 * S,
+			    float32_t * pSrc,
+			   float32_t * pDst,
+			   uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_f32(
+			   const arm_iir_lattice_instance_f32 * S,
+			    float32_t * pSrc,
+			   float32_t * pDst,
+			   uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_f32(
+				arm_iir_lattice_instance_f32 * S,
+				uint16_t numStages,
+				float32_t *pkCoeffs,
+				float32_t *pvCoeffs,
+				float32_t *pState,
+				uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q31(
+			   const arm_iir_lattice_instance_q31 * S,
+			    q31_t * pSrc,
+			   q31_t * pDst,
+			   uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_q31(
+				arm_iir_lattice_instance_q31 * S,
+				uint16_t numStages,
+				q31_t *pkCoeffs,
+				q31_t *pvCoeffs,
+				q31_t *pState,
+				uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q15(
+			   const arm_iir_lattice_instance_q15 * S,
+			    q15_t * pSrc,
+			   q15_t * pDst,
+			   uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+  void arm_iir_lattice_init_q15(
+				arm_iir_lattice_instance_q15 * S,
+				uint16_t numStages,
+				q15_t *pkCoeffs,
+				q15_t *pvCoeffs,
+				q15_t *pState,
+				uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_f32(
+		   const arm_lms_instance_f32 * S,
+		    float32_t * pSrc,
+		    float32_t * pRef,
+		   float32_t * pOut,
+		   float32_t * pErr,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_init_f32(
+			arm_lms_instance_f32 * S,
+			uint16_t numTaps,
+			float32_t * pCoeffs,
+			float32_t * pState,
+			float32_t mu,
+			uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return    none.
+   */
+
+  void arm_lms_init_q15(
+			arm_lms_instance_q15 * S,
+			uint16_t numTaps,
+			q15_t * pCoeffs,
+			q15_t * pState,
+			q15_t mu,
+			uint32_t blockSize,
+			uint32_t postShift);
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_q15(
+		   const arm_lms_instance_q15 * S,
+		    q15_t * pSrc,
+		    q15_t * pRef,
+		   q15_t * pOut,
+		   q15_t * pErr,
+		   uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+
+  } arm_lms_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_q31(
+		   const arm_lms_instance_q31 * S,
+		    q31_t * pSrc,
+		    q31_t * pRef,
+		   q31_t * pOut,
+		   q31_t * pErr,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_init_q31(
+			arm_lms_instance_q31 * S,
+			uint16_t numTaps,
+			q31_t *pCoeffs,
+			q31_t *pState,
+			q31_t mu,
+			uint32_t blockSize,
+			uint32_t postShift);
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t  numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that control filter coefficient updates. */
+    float32_t energy;    /**< saves previous frame energy. */
+    float32_t x0;        /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_f32(
+			arm_lms_norm_instance_f32 * S,
+			 float32_t * pSrc,
+			 float32_t * pRef,
+			float32_t * pOut,
+			float32_t * pErr,
+			uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_f32(
+			     arm_lms_norm_instance_f32 * S,
+			     uint16_t numTaps,
+			     float32_t * pCoeffs,
+			     float32_t * pState,
+			     float32_t mu,
+			     uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q31(
+			arm_lms_norm_instance_q31 * S,
+			 q31_t * pSrc,
+			 q31_t * pRef,
+			q31_t * pOut,
+			q31_t * pErr,
+			uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q31(
+			     arm_lms_norm_instance_q31 * S,
+			     uint16_t numTaps,
+			     q31_t * pCoeffs,
+			     q31_t * pState,
+			     q31_t mu,
+			     uint32_t blockSize,
+			     uint8_t postShift);
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;   /**< bit shift applied to coefficients. */
+    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
+    q15_t energy;        /**< saves previous frame energy. */
+    q15_t x0;            /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q15(
+			arm_lms_norm_instance_q15 * S,
+			 q15_t * pSrc,
+			 q15_t * pRef,
+			q15_t * pOut,
+			q15_t * pErr,
+			uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q15(
+			     arm_lms_norm_instance_q15 * S,
+			     uint16_t numTaps,
+			     q15_t * pCoeffs,
+			     q15_t * pState,
+			     q15_t mu,
+			     uint32_t blockSize,
+			     uint8_t postShift);
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_f32(
+			  float32_t * pSrcA,
+			 uint32_t srcALen,
+			  float32_t * pSrcB,
+			 uint32_t srcBLen,
+			 float32_t * pDst);
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q15(
+			  q15_t * pSrcA,
+			 uint32_t srcALen,
+			  q15_t * pSrcB,
+			 uint32_t srcBLen,
+			 q15_t * pDst);
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q15(
+			       q15_t * pSrcA,
+			      uint32_t srcALen,
+			       q15_t * pSrcB,
+			      uint32_t srcBLen,
+			      q15_t * pDst);
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q31(
+			  q31_t * pSrcA,
+			 uint32_t srcALen,
+			  q31_t * pSrcB,
+			 uint32_t srcBLen,
+			 q31_t * pDst);
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q31(
+			       q31_t * pSrcA,
+			      uint32_t srcALen,
+			       q31_t * pSrcB,
+			      uint32_t srcBLen,
+			      q31_t * pDst);
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q7(
+			 q7_t * pSrcA,
+			uint32_t srcALen,
+			 q7_t * pSrcB,
+			uint32_t srcBLen,
+			q7_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_f32(
+			  arm_fir_sparse_instance_f32 * S,
+			   float32_t * pSrc,
+			  float32_t * pDst,
+			  float32_t * pScratchIn,
+			  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_f32(
+			       arm_fir_sparse_instance_f32 * S,
+			       uint16_t numTaps,
+			       float32_t * pCoeffs,
+			       float32_t * pState,
+			       int32_t * pTapDelay,
+			       uint16_t maxDelay,
+			       uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q31(
+			  arm_fir_sparse_instance_q31 * S,
+			   q31_t * pSrc,
+			  q31_t * pDst,
+			  q31_t * pScratchIn,
+			  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q31(
+			       arm_fir_sparse_instance_q31 * S,
+			       uint16_t numTaps,
+			       q31_t * pCoeffs,
+			       q31_t * pState,
+			       int32_t * pTapDelay,
+			       uint16_t maxDelay,
+			       uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q15(
+			  arm_fir_sparse_instance_q15 * S,
+			   q15_t * pSrc,
+			  q15_t * pDst,
+			  q15_t * pScratchIn,
+			  q31_t * pScratchOut,
+			  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q15(
+			       arm_fir_sparse_instance_q15 * S,
+			       uint16_t numTaps,
+			       q15_t * pCoeffs,
+			       q15_t * pState,
+			       int32_t * pTapDelay,
+			       uint16_t maxDelay,
+			       uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q7(
+			 arm_fir_sparse_instance_q7 * S,
+			  q7_t * pSrc,
+			 q7_t * pDst,
+			 q7_t * pScratchIn,
+			 q31_t * pScratchOut,
+			 uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q7(
+			      arm_fir_sparse_instance_q7 * S,
+			      uint16_t numTaps,
+			      q7_t * pCoeffs,
+			      q7_t * pState,
+			      int32_t *pTapDelay,
+			      uint16_t maxDelay,
+			      uint32_t blockSize);
+
+
+  /*
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta    input value in degrees 
+   * @param[out] *pSinVal points to the processed sine output. 
+   * @param[out] *pCosVal points to the processed cos output. 
+   * @return none.
+   */
+
+  void arm_sin_cos_f32(
+		       float32_t theta,
+		       float32_t *pSinVal,
+		       float32_t *pCcosVal);
+
+  /*
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees 
+   * @param[out] *pSinVal points to the processed sine output. 
+   * @param[out] *pCosVal points to the processed cosine output. 
+   * @return none.
+   */
+
+  void arm_sin_cos_q31(
+		       q31_t theta,
+		       q31_t *pSinVal,
+		       q31_t *pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_f32(
+			   float32_t * pSrc,
+			  float32_t * pDst,
+			  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q31(
+			   q31_t * pSrc,
+			  q31_t * pDst,
+			  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q15(
+			   q15_t * pSrc,
+			  q15_t * pDst,
+			  uint32_t numSamples);
+
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_f32(
+				  float32_t * pSrc,
+				 float32_t * pDst,
+				 uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q31(
+				  q31_t * pSrc,
+				 q31_t * pDst,
+				 uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q15(
+				  q15_t * pSrc,
+				 q15_t * pDst,
+				 uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control 
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * S points to an instance of the PID control data structure.  in
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  

+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   * 
+   * \par 
+   * \image html PID.gif "Proportional Integral Derivative Controller" 
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.  
+   * The proportional value determines the reaction to the current error, 
+   * the integral value determines the reaction based on the sum of recent errors, 
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure 
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. 
+   * A separate instance structure must be defined for each PID Controller. 
+   * There are separate instance structure declarations for each of the 3 supported data types. 
+   * 
+   * \par Reset Functions 
+   * There is also an associated reset function for each data type which clears the state array. 
+   *
+   * \par Initialization Functions 
+   * There is also an associated initialization function for each data type. 
+   * The initialization function performs the following operations: 
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.   
+   * 
+   * \par 
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. 
+   *
+   * \par Fixed-Point Behavior 
+   * Care must be taken when using the fixed-point versions of the PID Controller functions. 
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. 
+   * Refer to the function specific documentation below for usage guidelines. 
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   */
+
+
+  static __INLINE float32_t arm_pid_f32(
+					arm_pid_instance_f32 * S,
+					float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * Scaling and Overflow Behavior: 
+   * \par 
+   * The function is implemented using an internal 64-bit accumulator. 
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. 
+   * Thus, if the accumulator result overflows it wraps around rather than clip. 
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. 
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. 
+   */
+
+  static __INLINE q31_t arm_pid_q31(
+				    arm_pid_instance_q31 * S,
+				    q31_t in)
+  {
+    q63_t acc;
+	q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * Scaling and Overflow Behavior: 
+   * \par 
+   * The function is implemented using a 64-bit internal accumulator. 
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. 
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. 
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. 
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. 
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+
+  static __INLINE q15_t arm_pid_q15(
+				    arm_pid_instance_q15 * S,
+				    q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+    /* Implementation of PID controller */
+
+	#ifdef ARM_MATH_CM0
+
+ 	/* acc = A0 * x[n]  */
+	acc = ((q31_t) S->A0 )* in ;
+
+    #else
+				
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD(S->A0, in);
+	
+	#endif
+
+	#ifdef ARM_MATH_CM0
+						   
+	/* acc += A1 * x[n-1] + A2 * x[n-2]  */
+	acc += (q31_t) S->A1  *  S->state[0] ;
+	acc += (q31_t) S->A2  *  S->state[1] ;
+
+	#else
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc = __SMLALD(S->A1, (q31_t)__SIMD32(S->state), acc);
+
+	#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+  
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f32(
+				 const arm_matrix_instance_f32 * src,
+				 arm_matrix_instance_f32 * dst);
+
+  
+ 
+  /**
+   * @ingroup groupController
+   */
+
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents
+   * in the two-phase orthogonal stator axis Ialpha and Ibeta.
+   * When Ialpha is superposed with Ia as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta
+   * can be calculated using only Ia and Ib.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output. 
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where Ia and Ib are the instantaneous stator phases and
+   * pIalpha and pIbeta are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]       Ia       input three-phase coordinate a
+   * @param[in]       Ib       input three-phase coordinate b
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   */
+
+  static __INLINE void arm_clarke_f32(
+				      float32_t Ia,
+				      float32_t Ib,
+				      float32_t * pIalpha,
+				      float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+  }
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]       Ia       input three-phase coordinate a
+   * @param[in]       Ib       input three-phase coordinate b
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   *
+   * Scaling and Overflow Behavior:
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_clarke_q31(
+				      q31_t Ia,
+				      q31_t Ib,
+				      q31_t * pIalpha,
+				      q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out]  *pDst    output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q31(
+		     q7_t * pSrc,
+		     q31_t * pDst,
+		     uint32_t blockSize);
+
+
+ 
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   * 
+   * The function operates on a single sample of data and each call to the function returns the processed output. 
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where pIa and pIb are the instantaneous stator phases and
+   * Ialpha and Ibeta are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate a
+   * @param[out]      *pIb    points to output three-phase coordinate b
+   * @return none.
+   */
+
+
+  static __INLINE void arm_inv_clarke_f32(
+					  float32_t Ialpha,
+					  float32_t Ibeta,
+					  float32_t * pIa,
+					  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+  }
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version 
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate a
+   * @param[out]      *pIb    points to output three-phase coordinate b
+   * @return none.
+   *
+   * Scaling and Overflow Behavior:
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_inv_clarke_q31(
+					  q31_t Ialpha,
+					  q31_t Ibeta,
+					  q31_t * pIa,
+					  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out] *pDst     output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q15(
+		      q7_t * pSrc,
+		     q15_t * pDst,
+		     uint32_t blockSize);
+
+  
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents 
+   * from the stationary to the moving reference frame and control the spatial relationship between 
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the 
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output. 
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where Ialpha and Ibeta are the stator vector components,  
+   * pId and pIq are rotor vector components and cosVal and sinVal are the 
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output	rotor reference frame d
+   * @param[out]      *pIq   points to output	rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+
+  static __INLINE void arm_park_f32(
+				    float32_t Ialpha,
+				    float32_t Ibeta,
+				    float32_t * pId,
+				    float32_t * pIq,
+				    float32_t sinVal,
+				    float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+  }
+
+  /**
+   * @brief  Park transform for Q31 version 
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output rotor reference frame d
+   * @param[out]      *pIq   points to output rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * Scaling and Overflow Behavior:
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_park_q31(
+				    q31_t Ialpha,
+				    q31_t Ibeta,
+				    q31_t * pId,
+				    q31_t * pIq,
+				    q31_t sinVal,
+				    q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_float(
+		        q7_t * pSrc,
+		       float32_t * pDst,
+		       uint32_t blockSize);
+
+ 
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output. 
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where pIalpha and pIbeta are the stator vector components,  
+   * Id and Iq are rotor vector components and cosVal and sinVal are the 
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   */
+
+  static __INLINE void arm_inv_park_f32(
+					float32_t Id,
+					float32_t Iq,
+					float32_t * pIalpha,
+					float32_t * pIbeta,
+					float32_t sinVal,
+					float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for	Q31 version 
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   *
+   * Scaling and Overflow Behavior:
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_inv_park_q31(
+					q31_t Id,
+					q31_t Iq,
+					q31_t * pIalpha,
+					q31_t * pIbeta,
+					q31_t sinVal,
+					q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+   
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_float(
+			 q31_t * pSrc,
+			float32_t * pDst,
+			uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par 
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * 

+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * S points to an instance of the Linear Interpolate function data structure.
+   * x is the input sample value. The functions returns the output value.
+   * 
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table 
+   * if x is below input range and returns last value of table if x is above range.  
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+   * @param[in] x input sample to process
+   * @return y processed output sample.
+   *
+   */
+
+  static __INLINE float32_t arm_linear_interp_f32(
+						  arm_linear_interp_instance_f32 * S,
+						  float32_t x)
+  {
+
+	  float32_t y;
+	  float32_t x0, x1;						/* Nearest input values */
+	  float32_t y0, y1;	  					/* Nearest output values */
+	  float32_t xSpacing = S->xSpacing;		/* spacing between input values */
+	  int32_t i;  							/* Index variable */
+	  float32_t *pYData = S->pYData;	    /* pointer to output table */
+
+	  /* Calculation of index */
+	  i =   (x - S->x1) / xSpacing;
+
+	  if(i < 0)
+	  {
+	     /* Iniatilize output for below specified range as least output value of table */
+		 y = pYData[0];
+	  }
+	  else if(i >= S->nValues)
+	  {
+	  	  /* Iniatilize output for above specified range as last output value of table */
+	  	  y = pYData[S->nValues-1];	
+	  }
+	  else
+	  {	 
+	  	  /* Calculation of nearest input values */
+		  x0 = S->x1 + i * xSpacing;
+		  x1 = S->x1 + (i +1) * xSpacing;
+		 
+		 /* Read of nearest output values */
+		  y0 = pYData[i];
+		  y1 = pYData[i + 1];
+		
+		  /* Calculation of output */
+		  y = y0 + (x - x0) * ((y1 - y0)/(x1-x0));	
+		
+	  }
+
+      /* returns output value */
+	  return (y);
+  }
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q31_t arm_linear_interp_q31(q31_t *pYData,
+					      q31_t x, uint32_t nValues)
+  {
+    q31_t y;                                   /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                              /* Index to read nearest output values */
+    
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20);
+
+	if(index >= (nValues - 1))
+	{
+		return(pYData[nValues - 1]);
+	}
+	else if(index < 0)
+	{
+		return(pYData[0]);
+	}
+	else
+	{
+
+	    /* 20 bits for the fractional part */
+	    /* shift left by 11 to keep fract in 1.31 format */
+	    fract = (x & 0x000FFFFF) << 11;
+	
+	    /* Read two nearest output values from the index in 1.31(q31) format */
+	    y0 = pYData[index];
+	    y1 = pYData[index + 1u];
+	
+	    /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+	    y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+	
+	    /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+	    y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+	
+	    /* Convert y to 1.31 format */
+	    return (y << 1u);
+
+	}
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12. 
+   *
+   */
+
+
+  static __INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues)
+  {
+    q63_t y;                                   /* output */
+    q15_t y0, y1;                              /* Nearest output values */
+    q31_t fract;                               /* fractional part */
+    int32_t index;                            /* Index to read nearest output values */ 
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u); 
+
+	if(index >= (nValues - 1))
+	{
+		return(pYData[nValues - 1]);
+	}
+	else if(index < 0)
+	{
+		return(pYData[0]);
+	}
+	else
+	{	
+	    /* 20 bits for the fractional part */
+	    /* fract is in 12.20 format */
+	    fract = (x & 0x000FFFFF);
+	
+	    /* Read two nearest output values from the index */
+	    y0 = pYData[index];
+	    y1 = pYData[index + 1u];
+	
+	    /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+	    y = ((q63_t) y0 * (0xFFFFF - fract));
+	
+	    /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+	    y += ((q63_t) y1 * (fract));
+	
+	    /* convert y to 1.15 format */
+	    return (y >> 20);
+	}
+
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+
+
+  static __INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x,  uint32_t nValues)
+  {
+    q31_t y;                                   /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                              /* Index to read nearest output values */
+    
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+
+    if(index >= (nValues - 1))
+	{
+		return(pYData[nValues - 1]);
+	}
+	else if(index < 0)
+	{
+		return(pYData[0]);
+	}
+	else
+	{
+
+	    /* 20 bits for the fractional part */
+	    /* fract is in 12.20 format */
+	    fract = (x & 0x000FFFFF);
+	
+	    /* Read two nearest output values from the index and are in 1.7(q7) format */
+	    y0 = pYData[index];
+	    y1 = pYData[index + 1u];
+	
+	    /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+	    y = ((y0 * (0xFFFFF - fract)));
+	
+	    /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+	    y += (y1 * fract);
+	
+	    /* convert y to 1.7(q7) format */
+	    return (y >> 20u);
+
+	}
+
+  }
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  sin(x).
+   */
+
+  float32_t arm_sin_f32(
+			 float32_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q31_t arm_sin_q31(
+		     q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q15_t arm_sin_q15(
+		     q15_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  cos(x).
+   */
+
+  float32_t arm_cos_f32(
+			 float32_t x);
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q31_t arm_cos_q31(
+		     q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q15_t arm_cos_q15(
+		     q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.  
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   * 

+   * where x1 is the current estimate,
+   * x0 is the previous estimate and
+   * f'(x0) is the derivative of f() evaluated at x0.
+   * For the square root function, the algorithm reduces to:
+   * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * 

+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in     input value.
+   * @param[out] *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * in is negative value and returns zero output for negative values.
+   */
+
+  static __INLINE arm_status  arm_sqrt_f32(
+					  float32_t in, float32_t *pOut)
+  {
+  	if(in > 0)
+	{
+
+//	#if __FPU_USED
+    #if (__FPU_USED == 1) && defined ( __CC_ARM   )
+		*pOut = __sqrtf(in);
+	#else	  
+		*pOut = sqrtf(in);
+	#endif
+
+		return (ARM_MATH_SUCCESS);
+	}
+  	else
+	{
+		*pOut = 0.0f;
+		return (ARM_MATH_ARGUMENT_ERROR);
+	}
+
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out]  *pOut square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * in is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+		      q31_t in, q31_t *pOut);
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out]  *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * in is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+		      q15_t in, q15_t *pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+
+
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_f32(
+					     int32_t * circBuffer,
+					     int32_t L,
+					     uint16_t * writeOffset,
+					     int32_t bufferInc,
+					     const int32_t * src,
+					     int32_t srcInc,
+					     uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+      {
+	/* copy the input sample to the circular buffer */
+	circBuffer[wOffset] = *src;
+
+	/* Update the input pointer */
+	src += srcInc;
+
+	/* Circularly update wOffset.  Watch out for positive and negative value */
+	wOffset += bufferInc;
+	if(wOffset >= L)
+	  wOffset -= L;
+
+	/* Decrement the loop counter */
+	i--;
+      }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  static __INLINE void arm_circularRead_f32(
+					    int32_t * circBuffer,
+					    int32_t L,
+					    int32_t * readOffset,
+					    int32_t bufferInc,
+					    int32_t * dst,
+					    int32_t * dst_base,
+					    int32_t dst_length,
+					    int32_t dstInc,
+					    uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+      {
+	/* copy the sample from the circular buffer to the destination buffer */
+	*dst = circBuffer[rOffset];
+
+	/* Update the input pointer */
+	dst += dstInc;
+
+	if(dst == (int32_t *) dst_end)
+	  {
+	    dst = dst_base;
+	  }
+
+	/* Circularly update rOffset.  Watch out for positive and negative value  */
+	rOffset += bufferInc;
+
+	if(rOffset >= L)
+	  {
+	    rOffset -= L;
+	  }
+
+	/* Decrement the loop counter */
+	i--;
+      }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q15(
+					     q15_t * circBuffer,
+					     int32_t L,
+					     uint16_t * writeOffset,
+					     int32_t bufferInc,
+					     const q15_t * src,
+					     int32_t srcInc,
+					     uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+      {
+	/* copy the input sample to the circular buffer */
+	circBuffer[wOffset] = *src;
+
+	/* Update the input pointer */
+	src += srcInc;
+
+	/* Circularly update wOffset.  Watch out for positive and negative value */
+	wOffset += bufferInc;
+	if(wOffset >= L)
+	  wOffset -= L;
+
+	/* Decrement the loop counter */
+	i--;
+      }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q15(
+					    q15_t * circBuffer,
+					    int32_t L,
+					    int32_t * readOffset,
+					    int32_t bufferInc,
+					    q15_t * dst,
+					    q15_t * dst_base,
+					    int32_t dst_length,
+					    int32_t dstInc,
+					    uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+      {
+	/* copy the sample from the circular buffer to the destination buffer */
+	*dst = circBuffer[rOffset];
+
+	/* Update the input pointer */
+	dst += dstInc;
+
+	if(dst == (q15_t *) dst_end)
+	  {
+	    dst = dst_base;
+	  }
+
+	/* Circularly update wOffset.  Watch out for positive and negative value */
+	rOffset += bufferInc;
+
+	if(rOffset >= L)
+	  {
+	    rOffset -= L;
+	  }
+
+	/* Decrement the loop counter */
+	i--;
+      }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q7(
+					    q7_t * circBuffer,
+					    int32_t L,
+					    uint16_t * writeOffset,
+					    int32_t bufferInc,
+					    const q7_t * src,
+					    int32_t srcInc,
+					    uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+      {
+	/* copy the input sample to the circular buffer */
+	circBuffer[wOffset] = *src;
+
+	/* Update the input pointer */
+	src += srcInc;
+
+	/* Circularly update wOffset.  Watch out for positive and negative value */
+	wOffset += bufferInc;
+	if(wOffset >= L)
+	  wOffset -= L;
+
+	/* Decrement the loop counter */
+	i--;
+      }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q7(
+					   q7_t * circBuffer,
+					   int32_t L,
+					   int32_t * readOffset,
+					   int32_t bufferInc,
+					   q7_t * dst,
+					   q7_t * dst_base,
+					   int32_t dst_length,
+					   int32_t dstInc,
+					   uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+      {
+	/* copy the sample from the circular buffer to the destination buffer */
+	*dst = circBuffer[rOffset];
+
+	/* Update the input pointer */
+	dst += dstInc;
+
+	if(dst == (q7_t *) dst_end)
+	  {
+	    dst = dst_base;
+	  }
+
+	/* Circularly update rOffset.  Watch out for positive and negative value */
+	rOffset += bufferInc;
+
+	if(rOffset >= L)
+	  {
+	    rOffset -= L;
+	  }
+
+	/* Decrement the loop counter */
+	i--;
+      }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q31(
+		      q31_t * pSrc,
+		     uint32_t blockSize,
+		     q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_f32(
+		      float32_t * pSrc,
+		     uint32_t blockSize,
+		     float32_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q15(
+		      q15_t * pSrc,
+		     uint32_t blockSize,
+		     q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q7(
+		     q7_t * pSrc,
+		    uint32_t blockSize,
+		    q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_mean_q7(
+		    q7_t * pSrc,
+		   uint32_t blockSize,
+		   q7_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q15(
+		     q15_t * pSrc,
+		    uint32_t blockSize,
+		    q15_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q31(
+		     q31_t * pSrc,
+		    uint32_t blockSize,
+		    q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_f32(
+		     float32_t * pSrc,
+		    uint32_t blockSize,
+		    float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_f32(
+		    float32_t * pSrc,
+		   uint32_t blockSize,
+		   float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q31(
+		    q31_t * pSrc,
+		   uint32_t blockSize,
+		   q63_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q15(
+		    q15_t * pSrc,
+		   uint32_t blockSize,
+		   q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_f32(
+		    float32_t * pSrc,
+		   uint32_t blockSize,
+		   float32_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q31(
+		    q31_t * pSrc,
+		   uint32_t blockSize,
+		   q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q15(
+		    q15_t * pSrc,
+		   uint32_t blockSize,
+		   q15_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_f32(
+		    float32_t * pSrc,
+		   uint32_t blockSize,
+		   float32_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q31(
+		    q31_t * pSrc,
+		   uint32_t blockSize,
+		   q31_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q15(
+		    q15_t * pSrc,
+		   uint32_t blockSize,
+		   q15_t * pResult);
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_f32(
+			  float32_t * pSrc,
+			 float32_t * pDst,
+			 uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q31(
+			  q31_t * pSrc,
+			 q31_t * pDst,
+			 uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q15(
+			  q15_t * pSrc,
+			 q15_t * pDst,
+			 uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q15(
+			       q15_t * pSrcA,
+			       q15_t * pSrcB,
+			      uint32_t numSamples,
+			      q31_t * realResult,
+			      q31_t * imagResult);
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q31(
+			       q31_t * pSrcA,
+			       q31_t * pSrcB,
+			      uint32_t numSamples,
+			      q63_t * realResult,
+			      q63_t * imagResult);
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_f32(
+			       float32_t * pSrcA,
+			       float32_t * pSrcB,
+			      uint32_t numSamples,
+			      float32_t * realResult,
+			      float32_t * imagResult);
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q15(
+			        q15_t * pSrcCmplx,
+			        q15_t * pSrcReal,
+			       q15_t * pCmplxDst,
+			       uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q31(
+			        q31_t * pSrcCmplx,
+			        q31_t * pSrcReal,
+			       q31_t * pCmplxDst,
+			       uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_f32(
+			        float32_t * pSrcCmplx,
+			        float32_t * pSrcReal,
+			       float32_t * pCmplxDst,
+			       uint32_t numSamples);
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *result is output pointer
+   * @param[in]  index is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q7(
+		   q7_t * pSrc,
+		  uint32_t blockSize,
+		  q7_t * result,
+		  uint32_t * index);
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q15(
+		    q15_t * pSrc,
+		   uint32_t blockSize,
+		   q15_t * pResult,
+		   uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+  void arm_min_q31(
+		    q31_t * pSrc,
+		   uint32_t blockSize,
+		   q31_t * pResult,
+		   uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_f32(
+		    float32_t * pSrc,
+		   uint32_t blockSize,
+		   float32_t * pResult,
+		   uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q7(
+		   q7_t * pSrc,
+		  uint32_t blockSize,
+		  q7_t * pResult,
+		  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q15(
+		    q15_t * pSrc,
+		   uint32_t blockSize,
+		   q15_t * pResult,
+		   uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q31(
+		    q31_t * pSrc,
+		   uint32_t blockSize,
+		   q31_t * pResult,
+		   uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_f32(
+		    float32_t * pSrc,
+		   uint32_t blockSize,
+		   float32_t * pResult,
+		   uint32_t * pIndex);
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q15(
+			        q15_t * pSrcA,
+			        q15_t * pSrcB,
+			       q15_t * pDst,
+			       uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q31(
+			        q31_t * pSrcA,
+			        q31_t * pSrcB,
+			       q31_t * pDst,
+			       uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_f32(
+			        float32_t * pSrcA,
+			        float32_t * pSrcB,
+			       float32_t * pDst,
+			       uint32_t numSamples);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector. 
+   * @param[in]       *pSrc points to the floating-point input vector 
+   * @param[out]      *pDst points to the Q31 output vector
+   * @param[in]       blockSize length of the input vector 
+   * @return none. 
+   */
+  void arm_float_to_q31(
+			       float32_t * pSrc,
+			      q31_t * pDst,
+			      uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector. 
+   * @param[in]       *pSrc points to the floating-point input vector 
+   * @param[out]      *pDst points to the Q15 output vector
+   * @param[in]       blockSize length of the input vector 
+   * @return          none
+   */
+  void arm_float_to_q15(
+			       float32_t * pSrc,
+			      q15_t * pDst,
+			      uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector. 
+   * @param[in]       *pSrc points to the floating-point input vector 
+   * @param[out]      *pDst points to the Q7 output vector
+   * @param[in]       blockSize length of the input vector 
+   * @return          none
+   */
+  void arm_float_to_q7(
+			      float32_t * pSrc,
+			     q7_t * pDst,
+			     uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q15(
+		       q31_t * pSrc,
+		      q15_t * pDst,
+		      uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q7(
+		      q31_t * pSrc,
+		     q7_t * pDst,
+		     uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_float(
+			 q15_t * pSrc,
+			float32_t * pDst,
+			uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q31(
+		       q15_t * pSrc,
+		      q31_t * pDst,
+		      uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q7(
+		      q15_t * pSrc,
+		     q7_t * pDst,
+		     uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function f(x, y) is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * Algorithm
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * 

+   *
+   * \par
+   * where numRows specifies the number of rows in the table;
+   * numCols specifies the number of columns in the table;
+   * and pData points to an array of size numRows*numCols values.
+   * The data table pTable is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.
+   *
+   * \par
+   * Let (x, y) specify the desired interpolation point.  Then define:
+   * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * 

+   * \par
+   * The interpolated output point is computed as:
+   * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * 

+   * Note that the coordinates (x, y) contain integer and fractional components.  
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. 
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate.
+  * @param[in] Y interpolation coordinate.
+  * @return out interpolated value.
+  */
+
+  
+  static __INLINE float32_t arm_bilinear_interp_f32(
+						    const arm_bilinear_interp_instance_f32 * S,
+						    float32_t X,
+						    float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+	/* Care taken for table outside boundary */
+	/* Returns zero output when values are outside table boundary */
+	if(xIndex < 0 || xIndex > (S->numRows-1) || yIndex < 0  || yIndex > ( S->numCols-1))
+	{
+		return(0);
+	}
+	
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex-1) *  S->numCols ;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex-1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+     out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+   /* return to application */
+    return (out);
+
+  }
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q31_t arm_bilinear_interp_q31(
+						arm_bilinear_interp_instance_q31 * S,
+						q31_t X,
+						q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                             /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20u);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20u);
+
+	/* Care taken for table outside boundary */
+	/* Returns zero output when values are outside table boundary */
+	if(rI < 0 || rI > (S->numRows-1) || cI < 0  || cI > ( S->numCols-1))
+	{
+		return(0);
+	}
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return (acc << 2u);
+
+  }
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q15_t arm_bilinear_interp_q15(
+						arm_bilinear_interp_instance_q15 * S,
+						q31_t X,
+						q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                             /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+	/* Care taken for table outside boundary */
+	/* Returns zero output when values are outside table boundary */
+	if(rI < 0 || rI > (S->numRows-1) || cI < 0  || cI > ( S->numCols-1))
+	{
+		return(0);
+	}
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return (acc >> 36);
+
+  }
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q7_t arm_bilinear_interp_q7(
+					      arm_bilinear_interp_instance_q7 * S,
+					      q31_t X,
+					      q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                             /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+	/* Care taken for table outside boundary */
+	/* Returns zero output when values are outside table boundary */
+	if(rI < 0 || rI > (S->numRows-1) || cI < 0  || cI > ( S->numCols-1))
+	{
+		return(0);
+	}
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return (acc >> 40);
+
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+
+
+
+
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+
+/**
+ *
+ * End of file.
+ */
diff --git a/hardware/sam/system/CMSIS/Include/core_cm0.h b/hardware/sam/system/CMSIS/Include/core_cm0.h
new file mode 100644
index 000000000..9d7a19f9a
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Include/core_cm0.h
@@ -0,0 +1,665 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V2.10
+ * @date     19. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+
+/** \mainpage CMSIS Cortex-M0
+
+  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
+  It consists of:
+
+     - Cortex-M Core Register Definitions
+     - Cortex-M functions
+     - Cortex-M instructions
+
+  The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease
+  access to the Cortex-M Core
+ */
+
+/** \defgroup CMSIS_MISRA_Exceptions  CMSIS MISRA-C:2004 Compliance Exceptions
+  CMSIS violates following MISRA-C2004 Rules:
+  
+   - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'. 
+
+   - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+   
+   - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code. 
+
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
+  This file defines all structures and symbols for CMSIS core:
+   - CMSIS version number
+   - Cortex-M core
+   - Cortex-M core Revision Number
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (0x10)                                                       /*!< [15:0]  CMSIS HAL sub version  */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
+
+#define __CORTEX_M                (0x00)                                                       /*!< Cortex core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+    /* add preprocessor checks */
+#endif
+
+#include                       /*!< standard types definitions                      */
+#include "core_cmInstr.h"                /*!< Core Instruction Access                         */
+#include "core_cmFunc.h"                 /*!< Core Function Access                            */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< defines 'write only' permissions                */
+#define     __IO    volatile             /*!< defines 'read / write' permissions              */
+
+/*@} end of group CMSIS_core_definitions */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register CMSIS Core Register
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+*/
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CORE CMSIS Core
+  Type definitions for the Cortex-M Core Registers
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_NVIC CMSIS NVIC
+  Type definitions for the Cortex-M NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB CMSIS SCB
+  Type definitions for the Cortex-M System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+       uint32_t RESERVED0;
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick CMSIS SysTick
+  Type definitions for the Cortex-M System Timer Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug CMSIS Core Debug
+  Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP
+  and not via processor. Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup  CMSIS_core_register
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address           */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
+  @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    This function enables a device specific interrupt in the NVIC interrupt controller.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the external interrupt to enable
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    This function disables a device specific interrupt in the NVIC interrupt controller.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the external interrupt to disable
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    This function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Number of the interrupt for get pending
+    \return             0  Interrupt status is not pending
+    \return             1  Interrupt status is pending
+ */
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    This function sets the pending bit for the specified interrupt.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the interrupt for set pending
+ */
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    This function clears the pending bit for the specified interrupt.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the interrupt for clear pending
+ */
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    This function sets the priority for the specified interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+    Note: The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Number of the interrupt for set priority
+    \param [in]  priority  Priority to set
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    This function reads the priority for the specified interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+    The returned priority value is automatically aligned to the implemented
+    priority bits of the microcontroller.
+
+    \param [in]   IRQn  Number of the interrupt for get priority
+    \return             Interrupt Priority
+ */
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    This function initiate a system reset request to reset the MCU.
+ */
+static __INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    This function initialises the system tick timer and its interrupt and start the system tick timer.
+    Counter is in free running mode to generate periodical interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/hardware/sam/system/CMSIS/Include/core_cm3.h b/hardware/sam/system/CMSIS/Include/core_cm3.h
new file mode 100644
index 000000000..185688f14
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1244 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V2.11
+ * @date     08. September 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+
+/** \mainpage CMSIS Cortex-M3
+
+  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
+  It consists of:
+
+     - Cortex-M Core Register Definitions
+     - Cortex-M functions
+     - Cortex-M instructions
+
+  The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease
+  access to the Cortex-M Core
+ */
+
+/** \defgroup CMSIS_MISRA_Exceptions  CMSIS MISRA-C:2004 Compliance Exceptions
+  CMSIS violates following MISRA-C2004 Rules:
+  
+   - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'. 
+
+   - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+   
+   - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code. 
+
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
+  This file defines all structures and symbols for CMSIS core:
+   - CMSIS version number
+   - Cortex-M core
+   - Cortex-M core Revision Number
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB   (0x10)                                                       /*!< [15:0]  CMSIS HAL sub version  */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
+
+#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+
+#define __FPU_USED       0 /*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+    /* add preprocessor checks */
+#endif
+
+#include                       /*!< standard types definitions                      */
+#include "core_cmInstr.h"                /*!< Core Instruction Access                         */
+#include "core_cmFunc.h"                 /*!< Core Function Access                            */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< defines 'write only' permissions                */
+#define     __IO    volatile             /*!< defines 'read / write' permissions              */
+
+/*@} end of group CMSIS_core_definitions */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register CMSIS Core Register
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+*/
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CORE CMSIS Core
+  Type definitions for the Cortex-M Core Registers
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_NVIC CMSIS NVIC
+  Type definitions for the Cortex-M NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB CMSIS SCB
+  Type definitions for the Cortex-M System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB
+  Type definitions for the Cortex-M System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick CMSIS SysTick
+  Type definitions for the Cortex-M System Timer Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM CMSIS ITM
+  Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                          /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)             /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                          /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                   /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                          /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)          /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                          /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                          /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)             /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                          /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                 /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_TXENA_Pos                   3                                          /*!< ITM TCR: TXENA Position */
+#define ITM_TCR_TXENA_Msk                  (1UL << ITM_TCR_TXENA_Pos)                  /*!< ITM TCR: TXENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                          /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                          /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                  /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                          /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                 /*!< ITM TCR: ITM Enable bit Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU CMSIS MPU
+  Type definitions for the Cortex-M Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug CMSIS Core Debug
+  Type definitions for the Cortex-M Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup  CMSIS_core_register
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
+  @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  This function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field
+ */
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  This function gets the priority grouping from NVIC Interrupt Controller.
+  Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+
+    \return                Priority grouping field
+ */
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    This function enables a device specific interrupt in the NVIC interrupt controller.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the external interrupt to enable
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    This function disables a device specific interrupt in the NVIC interrupt controller.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the external interrupt to disable
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    This function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Number of the interrupt for get pending
+    \return             0  Interrupt status is not pending
+    \return             1  Interrupt status is pending
+ */
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    This function sets the pending bit for the specified interrupt.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the interrupt for set pending
+ */
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    This function clears the pending bit for the specified interrupt.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the interrupt for clear pending
+ */
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    This function reads the active register in NVIC and returns the active bit.
+    \param [in]      IRQn  Number of the interrupt for get active
+    \return             0  Interrupt status is not active
+    \return             1  Interrupt status is active
+ */
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    This function sets the priority for the specified interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+    Note: The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Number of the interrupt for set priority
+    \param [in]  priority  Priority to set
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    This function reads the priority for the specified interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+    The returned priority value is automatically aligned to the implemented
+    priority bits of the microcontroller.
+
+    \param [in]   IRQn  Number of the interrupt for get priority
+    \return             Interrupt Priority
+ */
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    This function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value and sub priority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    The returned priority value can be used for NVIC_SetPriority(...) function
+
+    \param [in]     PriorityGroup  Used priority group
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0)
+    \param [in]       SubPriority  Sub priority value (starting from 0)
+    \return                        Encoded priority for the interrupt
+ */
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    This function decodes an interrupt priority value with the given priority group to
+    preemptive priority value and sub priority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    The priority value can be retrieved with NVIC_GetPriority(...) function
+
+    \param [in]         Priority   Priority value
+    \param [in]     PriorityGroup  Used priority group
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0)
+    \param [out]     pSubPriority  Sub priority value (starting from 0)
+ */
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    This function initiate a system reset request to reset the MCU.
+ */
+static __INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    This function initialises the system tick timer and its interrupt and start the system tick timer.
+    Counter is in free running mode to generate periodical interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< external variable to receive characters                    */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
+
+
+/** \brief  ITM Send Character
+
+    This function transmits a character via the ITM channel 0.
+    It just returns when no debugger is connected that has booked the output.
+    It is blocking when a debugger is connected, but the previous character send is not transmitted.
+
+    \param [in]     ch  Character to transmit
+    \return             Character to transmit
+ */
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
+      (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    This function inputs a character via external variable ITM_RxBuffer.
+    It just returns when no debugger is connected that has booked the output.
+    It is blocking when a debugger is connected, but the previous character send is not transmitted.
+
+    \return             Received character
+    \return         -1  No character received
+ */
+static __INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    This function checks external variable ITM_RxBuffer whether a character is available or not.
+    It returns '1' if a character is available and '0' if no character is available.
+
+    \return          0  No character available
+    \return          1  Character available
+ */
+static __INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/hardware/sam/system/CMSIS/Include/core_cm4.h b/hardware/sam/system/CMSIS/Include/core_cm4.h
new file mode 100644
index 000000000..bf022ba67
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Include/core_cm4.h
@@ -0,0 +1,1378 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V2.10
+ * @date     19. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+
+/** \mainpage CMSIS Cortex-M4
+
+  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
+  It consists of:
+
+     - Cortex-M Core Register Definitions
+     - Cortex-M functions
+     - Cortex-M instructions
+     - Cortex-M SIMD instructions
+
+  The CMSIS Cortex-M4 Core Peripheral Access Layer contains C and assembly functions that ease
+  access to the Cortex-M Core
+ */
+
+/** \defgroup CMSIS_MISRA_Exceptions  CMSIS MISRA-C:2004 Compliance Exceptions
+  CMSIS violates following MISRA-C2004 Rules:
+  
+   - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'. 
+
+   - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+   
+   - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code. 
+
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
+  This file defines all structures and symbols for CMSIS core:
+   - CMSIS version number
+   - Cortex-M core
+   - Cortex-M core Revision Number
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB   (0x10)                                                       /*!< [15:0]  CMSIS HAL sub version  */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
+
+#define __CORTEX_M                (0x04)                                                       /*!< Cortex core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+    /* add preprocessor checks to define __FPU_USED */
+    #define __FPU_USED         0
+#endif
+
+#include                       /*!< standard types definitions                      */
+#include                 /*!< Core Instruction Access                         */
+#include                  /*!< Core Function Access                            */
+#include                /*!< Compiler specific SIMD Intrinsics               */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< defines 'write only' permissions                */
+#define     __IO    volatile             /*!< defines 'read / write' permissions              */
+
+/*@} end of group CMSIS_core_definitions */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register CMSIS Core Register
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+*/
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CORE CMSIS Core
+  Type definitions for the Cortex-M Core Registers
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_NVIC CMSIS NVIC
+  Type definitions for the Cortex-M NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB CMSIS SCB
+  Type definitions for the Cortex-M System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB
+  Type definitions for the Cortex-M System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick CMSIS SysTick
+  Type definitions for the Cortex-M System Timer Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM CMSIS ITM
+  Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                          /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)             /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                          /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                   /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                          /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)          /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                          /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                          /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)             /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                          /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                 /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_TXENA_Pos                   3                                          /*!< ITM TCR: TXENA Position */
+#define ITM_TCR_TXENA_Msk                  (1UL << ITM_TCR_TXENA_Pos)                  /*!< ITM TCR: TXENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                          /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                          /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                  /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                          /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                 /*!< ITM TCR: ITM Enable bit Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU CMSIS MPU
+  Type definitions for the Cortex-M Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU CMSIS FPU
+  Type definitions for the Cortex-M Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug CMSIS Core Debug
+  Type definitions for the Cortex-M Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup  CMSIS_core_register
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
+  @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  This function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field
+ */
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  This function gets the priority grouping from NVIC Interrupt Controller.
+  Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+
+    \return                Priority grouping field
+ */
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    This function enables a device specific interrupt in the NVIC interrupt controller.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the external interrupt to enable
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    This function disables a device specific interrupt in the NVIC interrupt controller.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the external interrupt to disable
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    This function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Number of the interrupt for get pending
+    \return             0  Interrupt status is not pending
+    \return             1  Interrupt status is pending
+ */
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    This function sets the pending bit for the specified interrupt.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the interrupt for set pending
+ */
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    This function clears the pending bit for the specified interrupt.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the interrupt for clear pending
+ */
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    This function reads the active register in NVIC and returns the active bit.
+    \param [in]      IRQn  Number of the interrupt for get active
+    \return             0  Interrupt status is not active
+    \return             1  Interrupt status is active
+ */
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    This function sets the priority for the specified interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+    Note: The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Number of the interrupt for set priority
+    \param [in]  priority  Priority to set
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    This function reads the priority for the specified interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+    The returned priority value is automatically aligned to the implemented
+    priority bits of the microcontroller.
+
+    \param [in]   IRQn  Number of the interrupt for get priority
+    \return             Interrupt Priority
+ */
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    This function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value and sub priority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    The returned priority value can be used for NVIC_SetPriority(...) function
+
+    \param [in]     PriorityGroup  Used priority group
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0)
+    \param [in]       SubPriority  Sub priority value (starting from 0)
+    \return                        Encoded priority for the interrupt
+ */
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    This function decodes an interrupt priority value with the given priority group to
+    preemptive priority value and sub priority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    The priority value can be retrieved with NVIC_GetPriority(...) function
+
+    \param [in]         Priority   Priority value
+    \param [in]     PriorityGroup  Used priority group
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0)
+    \param [out]     pSubPriority  Sub priority value (starting from 0)
+ */
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    This function initiate a system reset request to reset the MCU.
+ */
+static __INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    This function initialises the system tick timer and its interrupt and start the system tick timer.
+    Counter is in free running mode to generate periodical interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< external variable to receive characters                    */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
+
+
+/** \brief  ITM Send Character
+
+    This function transmits a character via the ITM channel 0.
+    It just returns when no debugger is connected that has booked the output.
+    It is blocking when a debugger is connected, but the previous character send is not transmitted.
+
+    \param [in]     ch  Character to transmit
+    \return             Character to transmit
+ */
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
+      (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    This function inputs a character via external variable ITM_RxBuffer.
+    It just returns when no debugger is connected that has booked the output.
+    It is blocking when a debugger is connected, but the previous character send is not transmitted.
+
+    \return             Received character
+    \return         -1  No character received
+ */
+static __INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    This function checks external variable ITM_RxBuffer whether a character is available or not.
+    It returns '1' if a character is available and '0' if no character is available.
+
+    \return          0  No character available
+    \return          1  Character available
+ */
+static __INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/hardware/sam/system/CMSIS/Include/core_cm4_simd.h b/hardware/sam/system/CMSIS/Include/core_cm4_simd.h
new file mode 100644
index 000000000..e7b676522
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Include/core_cm4_simd.h
@@ -0,0 +1,701 @@
+/**************************************************************************//**
+ * @file     core_cm4_simd.h
+ * @brief    CMSIS Cortex-M4 SIMD Header File
+ * @version  V2.10
+ * @date     19. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include 
+
+/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/
+/* intrinsic __SADD8      see intrinsics.h */
+/* intrinsic __QADD8      see intrinsics.h */
+/* intrinsic __SHADD8     see intrinsics.h */
+/* intrinsic __UADD8      see intrinsics.h */
+/* intrinsic __UQADD8     see intrinsics.h */
+/* intrinsic __UHADD8     see intrinsics.h */
+/* intrinsic __SSUB8      see intrinsics.h */
+/* intrinsic __QSUB8      see intrinsics.h */
+/* intrinsic __SHSUB8     see intrinsics.h */
+/* intrinsic __USUB8      see intrinsics.h */
+/* intrinsic __UQSUB8     see intrinsics.h */
+/* intrinsic __UHSUB8     see intrinsics.h */
+/* intrinsic __SADD16     see intrinsics.h */
+/* intrinsic __QADD16     see intrinsics.h */
+/* intrinsic __SHADD16    see intrinsics.h */
+/* intrinsic __UADD16     see intrinsics.h */
+/* intrinsic __UQADD16    see intrinsics.h */
+/* intrinsic __UHADD16    see intrinsics.h */
+/* intrinsic __SSUB16     see intrinsics.h */
+/* intrinsic __QSUB16     see intrinsics.h */
+/* intrinsic __SHSUB16    see intrinsics.h */
+/* intrinsic __USUB16     see intrinsics.h */
+/* intrinsic __UQSUB16    see intrinsics.h */
+/* intrinsic __UHSUB16    see intrinsics.h */
+/* intrinsic __SASX       see intrinsics.h */
+/* intrinsic __QASX       see intrinsics.h */
+/* intrinsic __SHASX      see intrinsics.h */
+/* intrinsic __UASX       see intrinsics.h */
+/* intrinsic __UQASX      see intrinsics.h */
+/* intrinsic __UHASX      see intrinsics.h */
+/* intrinsic __SSAX       see intrinsics.h */
+/* intrinsic __QSAX       see intrinsics.h */
+/* intrinsic __SHSAX      see intrinsics.h */
+/* intrinsic __USAX       see intrinsics.h */
+/* intrinsic __UQSAX      see intrinsics.h */
+/* intrinsic __UHSAX      see intrinsics.h */
+/* intrinsic __USAD8      see intrinsics.h */
+/* intrinsic __USADA8     see intrinsics.h */
+/* intrinsic __SSAT16     see intrinsics.h */
+/* intrinsic __USAT16     see intrinsics.h */
+/* intrinsic __UXTB16     see intrinsics.h */
+/* intrinsic __SXTB16     see intrinsics.h */
+/* intrinsic __UXTAB16    see intrinsics.h */
+/* intrinsic __SXTAB16    see intrinsics.h */
+/* intrinsic __SMUAD      see intrinsics.h */
+/* intrinsic __SMUADX     see intrinsics.h */
+/* intrinsic __SMLAD      see intrinsics.h */
+/* intrinsic __SMLADX     see intrinsics.h */
+/* intrinsic __SMLALD     see intrinsics.h */
+/* intrinsic __SMLALDX    see intrinsics.h */
+/* intrinsic __SMUSD      see intrinsics.h */
+/* intrinsic __SMUSDX     see intrinsics.h */
+/* intrinsic __SMLSD      see intrinsics.h */
+/* intrinsic __SMLSDX     see intrinsics.h */
+/* intrinsic __SMLSLD     see intrinsics.h */
+/* intrinsic __SMLSLDX    see intrinsics.h */
+/* intrinsic __SEL        see intrinsics.h */
+/* intrinsic __QADD       see intrinsics.h */
+/* intrinsic __QSUB       see intrinsics.h */
+/* intrinsic __PKHBT      see intrinsics.h */
+/* intrinsic __PKHTB      see intrinsics.h */
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+  
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else	\
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/hardware/sam/system/CMSIS/Include/core_cmFunc.h b/hardware/sam/system/CMSIS/Include/core_cmFunc.h
new file mode 100644
index 000000000..88819f9dd
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Include/core_cmFunc.h
@@ -0,0 +1,609 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V2.10
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface   
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+static __INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+static __INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get ISPR Register
+
+    This function returns the content of the ISPR Register.
+
+    \return               ISPR Register value
+ */
+static __INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+static __INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+static __INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+static __INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+static __INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+static __INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+static __INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+static __INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+ 
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+static __INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+static __INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+ 
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+static __INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+static __INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+static __INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include 
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/** \brief  Get ISPR Register
+
+    This function returns the content of the ISPR Register.
+
+    \return               ISPR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+ 
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+ 
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+ 
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+  
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+  
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/hardware/sam/system/CMSIS/Include/core_cmInstr.h b/hardware/sam/system/CMSIS/Include/core_cmInstr.h
new file mode 100644
index 000000000..78d2ef80b
--- /dev/null
+++ b/hardware/sam/system/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,585 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V2.10
+ * @date     19. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor, 
+    so that all instructions following the ISB are fetched from cache or 
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier. 
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before 
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+static __INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+static __INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz 
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include 
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor, 
+    so that all instructions following the ISB are fetched from cache or 
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier. 
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before 
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
+{
+  uint32_t result;
+  
+  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+  
+  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
+{
+  uint32_t result;
+  
+  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint8_t result;
+  
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint16_t result;
+  
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+  
+   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+  
+   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+  
+   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+  
+   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
+{
+  uint8_t result;
+  
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/hardware/sam/system/CMSIS/Lib/ARM/arm_cortexM0b_math.lib b/hardware/sam/system/CMSIS/Lib/ARM/arm_cortexM0b_math.lib
new file mode 100644
index 000000000..5f6ebf829
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diff --git a/hardware/sam/system/CMSIS/Lib/ARM/arm_cortexM0l_math.lib b/hardware/sam/system/CMSIS/Lib/ARM/arm_cortexM0l_math.lib
new file mode 100644
index 000000000..77f70750b
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diff --git a/hardware/sam/system/CMSIS/Lib/ARM/arm_cortexM3b_math.lib b/hardware/sam/system/CMSIS/Lib/ARM/arm_cortexM3b_math.lib
new file mode 100644
index 000000000..bad330612
Binary files /dev/null and b/hardware/sam/system/CMSIS/Lib/ARM/arm_cortexM3b_math.lib differ
diff --git a/hardware/sam/system/CMSIS/Lib/ARM/arm_cortexM3l_math.lib b/hardware/sam/system/CMSIS/Lib/ARM/arm_cortexM3l_math.lib
new file mode 100644
index 000000000..1139c730f
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diff --git a/hardware/sam/system/CMSIS/Lib/ARM/arm_cortexM4b_math.lib b/hardware/sam/system/CMSIS/Lib/ARM/arm_cortexM4b_math.lib
new file mode 100644
index 000000000..36e9098cc
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diff --git a/hardware/sam/system/CMSIS/Lib/ARM/arm_cortexM4bf_math.lib b/hardware/sam/system/CMSIS/Lib/ARM/arm_cortexM4bf_math.lib
new file mode 100644
index 000000000..914e0d2da
Binary files /dev/null and b/hardware/sam/system/CMSIS/Lib/ARM/arm_cortexM4bf_math.lib differ
diff --git a/hardware/sam/system/CMSIS/Lib/ARM/arm_cortexM4l_math.lib b/hardware/sam/system/CMSIS/Lib/ARM/arm_cortexM4l_math.lib
new file mode 100644
index 000000000..7fb98ba7f
Binary files /dev/null and b/hardware/sam/system/CMSIS/Lib/ARM/arm_cortexM4l_math.lib differ
diff --git a/hardware/sam/system/CMSIS/Lib/ARM/arm_cortexM4lf_math.lib b/hardware/sam/system/CMSIS/Lib/ARM/arm_cortexM4lf_math.lib
new file mode 100644
index 000000000..f5ddea42a
Binary files /dev/null and b/hardware/sam/system/CMSIS/Lib/ARM/arm_cortexM4lf_math.lib differ
diff --git a/hardware/sam/system/CMSIS/README.txt b/hardware/sam/system/CMSIS/README.txt
new file mode 100644
index 000000000..b0416f548
--- /dev/null
+++ b/hardware/sam/system/CMSIS/README.txt
@@ -0,0 +1,34 @@
+* -------------------------------------------------------------------
+* Copyright (C) 2011 ARM Limited. All rights reserved.  
+* 
+* Date:        25 July 2011  
+* Revision:    V2.10 
+*  
+* Project:     Cortex Microcontroller Software Interface Standard (CMSIS)
+* Title:       Release Note for CMSIS
+*
+* -------------------------------------------------------------------
+
+
+NOTE - Open the index.html file to access CMSIS documentation
+
+
+The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all 
+Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects 
+and reduces time-to-market for new embedded applications.
+
+CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf").
+Any user of the software package is bound to the terms and conditions of the end user license agreement.
+
+
+You will find the following sub-directories:
+
+Documentation           - Contains CMSIS documentation.
+ 
+DSP_Lib                 - MDK project files, Examples and source files etc.. to build the 
+                          CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.
+
+Include                 - CMSIS Core Support and CMSIS DSP Include Files.
+
+Lib                     - CMSIS DSP Binaries 
+---
\ No newline at end of file
diff --git a/hardware/sam/system/CMSIS/index.htm b/hardware/sam/system/CMSIS/index.htm
new file mode 100644
index 000000000..823b36164
--- /dev/null
+++ b/hardware/sam/system/CMSIS/index.htm
@@ -0,0 +1,115 @@
+
+
+
+CMSIS Release Notes
+
+
+
+
+
+
+
+
+
CMSIS Release Notes

+
Release Notes for CMSIS V2.00

+
November 2010

+
+
Information in this file, the accompany manuals, and software is

+                 Copyright © ARM Ltd.
All rights reserved.
+

+

+
+

+
+
Contents

+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/hardware/sam/system/libsam/build_gcc/Makefile b/hardware/sam/system/libsam/build_gcc/Makefile
new file mode 100644
index 000000000..6beb5821d
--- /dev/null
+++ b/hardware/sam/system/libsam/build_gcc/Makefile
@@ -0,0 +1,72 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Makefile for compiling libchip
+
+SUBMAKE_OPTIONS=--no-builtin-rules --no-builtin-variables
+
+#-------------------------------------------------------------------------------
+# Rules
+#-------------------------------------------------------------------------------
+
+# libsam_sam3s4c_gcc_rel.a libsam_sam3u4e_gcc_rel.a
+all: libsam_sam3s4c_gcc_dbg.a libsam_sam3u4e_gcc_dbg.a
+
+.PHONY: libsam_sam3s4c_gcc_dbg.a
+libsam_sam3s4c_gcc_dbg.a:
+	@echo --- 
+	@echo --- 
+	@echo --- Making $@
+	@echo --- 
+	@$(MAKE) CHIP=__SAM3S4C__ DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk
+
+.PHONY: libsam_sam3s4c_gcc_rel.a
+libsam_sam3s4c_gcc_rel.a:
+	@echo --- 
+	@echo --- 
+	@echo --- Making $@
+	@echo --- 
+	@$(MAKE) CHIP=__SAM3S4C__ $(SUBMAKE_OPTIONS) -f sam3.mk
+
+.PHONY: libsam_sam3u4e_gcc_dbg.a
+libsam_sam3u4e_gcc_dbg.a:
+	@echo --- 
+	@echo --- 
+	@echo --- Making $@
+	@echo --- 
+	@$(MAKE) CHIP=__SAM3U4E__ DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk
+
+.PHONY: libsam_sam3u4e_gcc_rel.a
+libsam_sam3u4e_gcc_rel.a:
+	@echo --- 
+	@echo --- 
+	@echo --- Making $@
+	@echo --- 
+	@$(MAKE) CHIP=__SAM3U4E__ $(SUBMAKE_OPTIONS) -f sam3.mk
+
+.PHONY: clean
+clean:
+	@echo --- Cleaning sam3s4c release and debug
+	@$(MAKE) CHIP=__SAM3S4C__ $(SUBMAKE_OPTIONS) -f sam3.mk $@
+	@$(MAKE) CHIP=__SAM3S4C__ DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk $@
+
+	@echo --- Cleaning sam3u4e release and debug
+	@$(MAKE) CHIP=__SAM3U4E__ $(SUBMAKE_OPTIONS) -f sam3.mk $@
+	@$(MAKE) CHIP=__SAM3U4E__ DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk $@
+
+
diff --git a/hardware/sam/system/libsam/build_gcc/debug.mk b/hardware/sam/system/libsam/build_gcc/debug.mk
new file mode 100644
index 000000000..d0716744a
--- /dev/null
+++ b/hardware/sam/system/libsam/build_gcc/debug.mk
@@ -0,0 +1,25 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Optimization level
+# -O1 Optimize
+# -O2 Optimize even more
+# -O3 Optimize yet more
+# -O0 Reduce compilation time and make debugging produce the expected results
+# -Os Optimize for size
+OPTIMIZATION = -g -O0 -DDEBUG
diff --git a/hardware/sam/system/libsam/build_gcc/gcc.mk b/hardware/sam/system/libsam/build_gcc/gcc.mk
new file mode 100644
index 000000000..97d3eff99
--- /dev/null
+++ b/hardware/sam/system/libsam/build_gcc/gcc.mk
@@ -0,0 +1,57 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Tool suffix when cross-compiling
+#CROSS_COMPILE = ../../CodeSourcery_arm/bin/arm-none-eabi-
+#CROSS_COMPILE = C:/CodeSourcery_2011.03-42/bin/arm-none-eabi-
+CROSS_COMPILE = $(ARM_GCC_TOOLCHAIN)/arm-none-eabi-
+
+# Compilation tools
+AR = $(CROSS_COMPILE)ar
+CC = $(CROSS_COMPILE)gcc
+AS = $(CROSS_COMPILE)as
+#LD = $(CROSS_COMPILE)ld
+#SIZE = $(CROSS_COMPILE)size
+NM = $(CROSS_COMPILE)nm
+#OBJCOPY = $(CROSS_COMPILE)objcopy
+RM=cs-rm -Rf
+SEP=/
+
+# Flags
+
+CFLAGS += -Wall -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int
+CFLAGS += -Werror-implicit-function-declaration -Wmain -Wparentheses
+CFLAGS += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused
+CFLAGS += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef
+CFLAGS += -Wshadow -Wpointer-arith -Wbad-function-cast -Wwrite-strings
+CFLAGS += -Wsign-compare -Waggregate-return -Wstrict-prototypes
+CFLAGS += -Wmissing-prototypes -Wmissing-declarations
+CFLAGS += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations
+CFLAGS += -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long
+CFLAGS += -Wunreachable-code
+CFLAGS += -Wcast-align
+#CFLAGS += -Wmissing-noreturn
+#CFLAGS += -Wconversion
+
+# To reduce application size use only integer printf function.
+CFLAGS += -Dprintf=iprintf
+
+CFLAGS += --param max-inline-insns-single=500 -mcpu=cortex-m3 -mthumb -mlong-calls -ffunction-sections
+CFLAGS += $(OPTIMIZATION) $(INCLUDES) -D$(CHIP)
+
+ASFLAGS = -mcpu=cortex-m3 -mthumb -Wall -a -g $(INCLUDES)
diff --git a/hardware/sam/system/libsam/build_gcc/release.mk b/hardware/sam/system/libsam/build_gcc/release.mk
new file mode 100644
index 000000000..0d15157f4
--- /dev/null
+++ b/hardware/sam/system/libsam/build_gcc/release.mk
@@ -0,0 +1,25 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Optimization level
+# -O1 Optimize
+# -O2 Optimize even more
+# -O3 Optimize yet more
+# -O0 Reduce compilation time and make debugging produce the expected results
+# -Os Optimize for size
+OPTIMIZATION = -Os
diff --git a/hardware/sam/system/libsam/build_gcc/sam3.mk b/hardware/sam/system/libsam/build_gcc/sam3.mk
new file mode 100644
index 000000000..6e9c4fb51
--- /dev/null
+++ b/hardware/sam/system/libsam/build_gcc/sam3.mk
@@ -0,0 +1,175 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Makefile for compiling libchip
+.SUFFIXES: .o .a .c .s
+SUB_MAKEFILES=debug.mk gcc.mk release.mk win.mk sam3s.mk
+
+LIBNAME=libsam
+TOOLCHAIN=gcc
+
+ifeq ($(CHIP),)
+$(error CHIP not defined)
+endif
+
+#CHIP_NAME=$(subst __,,$(CHIP))
+#CHIP_NAME=$(subst __,,$(call lc,$(CHIP)))
+
+#-------------------------------------------------------------------------------
+# Path
+#-------------------------------------------------------------------------------
+
+# Output directories
+#OUTPUT_BIN = ../lib
+OUTPUT_BIN = ../../../cores/sam
+
+# Libraries
+PROJECT_BASE_PATH = ..
+CMSIS_BASE_PATH = $(PROJECT_BASE_PATH)/../CMSIS/Include
+
+ifeq ($(CHIP), __SAM3S4C__)
+CHIP_NAME=sam3s4c
+CHIP_SERIE=sam3s
+else ifeq ($(CHIP), __SAM3U4E__)
+CHIP_NAME=sam3u4e
+CHIP_SERIE=sam3u
+else ifeq ($(CHIP), __SAM3N4C__)
+CHIP_NAME=sam3n4c
+CHIP_SERIE=sam3n
+else ifeq ($(CHIP), __SAM3X8H__)
+CHIP_NAME=sam3x8h
+CHIP_SERIE=sam3xa
+else
+endif
+
+CMSIS_CHIP_PATH=$(PROJECT_BASE_PATH)/cmsis/$(CHIP_SERIE)
+
+#-------------------------------------------------------------------------------
+# Files
+#-------------------------------------------------------------------------------
+
+vpath %.h $(PROJECT_BASE_PATH)/include $(PROJECT_BASE_PATH)/../cmsis/$(CHIP_SERIE)/include
+vpath %.c $(PROJECT_BASE_PATH)/source $(CMSIS_BASE_PATH) $(CMSIS_CHIP_PATH)/source/templates $(CMSIS_CHIP_PATH)/source/templates
+
+VPATH+=$(PROJECT_BASE_PATH)/source
+VPATH+=$(CMSIS_BASE_PATH)
+VPATH+=$(CMSIS_CHIP_PATH)/include
+VPATH+=$(CMSIS_CHIP_PATH)/source/templates
+VPATH+=$(CMSIS_CHIP_PATH)/source/templates/gcc
+
+INCLUDES = -I$(PROJECT_BASE_PATH)
+INCLUDES += -I$(PROJECT_BASE_PATH)/include
+INCLUDES += -I$(CMSIS_BASE_PATH)
+INCLUDES += -I$(CMSIS_CHIP_PATH)/include
+INCLUDES += -I$(CMSIS_CHIP_PATH)/source/templates
+
+#-------------------------------------------------------------------------------
+ifdef DEBUG
+include debug.mk
+else
+include release.mk
+endif
+
+#-------------------------------------------------------------------------------
+# Tools
+#-------------------------------------------------------------------------------
+
+include $(TOOLCHAIN).mk
+
+#-------------------------------------------------------------------------------
+ifdef DEBUG
+OUTPUT_OBJ=debug
+OUTPUT_LIB=$(LIBNAME)_$(CHIP_NAME)_$(TOOLCHAIN)_dbg.a
+else
+OUTPUT_OBJ=release
+OUTPUT_LIB=$(LIBNAME)_$(CHIP_NAME)_$(TOOLCHAIN)_rel.a
+endif
+
+OUTPUT_PATH=$(OUTPUT_OBJ)_$(CHIP_NAME)
+
+#-------------------------------------------------------------------------------
+# C source files and objects
+#-------------------------------------------------------------------------------
+C_SRC=$(wildcard $(PROJECT_BASE_PATH)/source/*.c)
+C_SRC+=$(wildcard $(CMSIS_CHIP_PATH)/source/templates/*.c)
+C_SRC+=$(wildcard $(CMSIS_CHIP_PATH)/source/templates/gcc/*.c)
+
+C_OBJ_TEMP=$(patsubst %.c, %.o, $(notdir $(C_SRC)))
+
+# during development, remove some files
+C_OBJ_FILTER=pio_it.o adc.o
+
+C_OBJ=$(filter-out $(C_OBJ_FILTER), $(C_OBJ_TEMP))
+
+#-------------------------------------------------------------------------------
+# Assembler source files and objects
+#-------------------------------------------------------------------------------
+A_SRC=$(wildcard $(PROJECT_BASE_PATH)/source/*.s)
+
+A_OBJ_TEMP=$(patsubst %.s, %.o, $(notdir $(A_SRC)))
+
+# during development, remove some files
+A_OBJ_FILTER=
+
+A_OBJ=$(filter-out $(A_OBJ_FILTER), $(A_OBJ_TEMP))
+
+#-------------------------------------------------------------------------------
+# Rules
+#-------------------------------------------------------------------------------
+all: $(CHIP)
+
+$(CHIP): create_output $(OUTPUT_LIB)
+
+.PHONY: create_output
+create_output:
+	@echo --- Preparing $(CHIP) files $(OUTPUT_PATH) $(OUTPUT_BIN)
+	@echo -------------------------
+	@echo *$(C_SRC)
+	@echo -------------------------
+	@echo *$(C_OBJ)
+	@echo -------------------------
+#	@echo *$(addprefix $(OUTPUT_PATH)/, $(C_OBJ))
+#	@echo -------------------------
+#	@echo *$(A_SRC)
+#	@echo -------------------------
+
+	-@mkdir $(subst /,$(SEP),$(OUTPUT_BIN)) 1>NUL 2>&1
+	-@mkdir $(OUTPUT_PATH) 1>NUL 2>&1
+
+$(addprefix $(OUTPUT_PATH)/,$(C_OBJ)): $(OUTPUT_PATH)/%.o: %.c
+#	"$(CC)" -v -c $(CFLAGS) -Wa,aln=$(subst .o,.s,$@) $< -o $@
+#	@"$(CC)" -c $(CFLAGS) $< -o $@
+	"$(CC)" -c $(CFLAGS) $< -o $@
+
+$(addprefix $(OUTPUT_PATH)/,$(A_OBJ)): $(OUTPUT_PATH)/%.o: %.s
+	@"$(AS)" -c $(ASFLAGS) $< -o $@
+
+$(OUTPUT_LIB): $(addprefix $(OUTPUT_PATH)/, $(C_OBJ)) $(addprefix $(OUTPUT_PATH)/, $(A_OBJ))
+	@"$(AR)" -r "$(OUTPUT_BIN)/$@" $^
+	@"$(NM)" "$(OUTPUT_BIN)/$@" > "$(OUTPUT_BIN)/$@.txt"
+
+.PHONY: clean
+clean:
+	@echo --- Cleaning $(CHIP) files
+	-@$(RM) $(OUTPUT_PATH) 1>NUL 2>&1
+	-@$(RM) $(subst /,$(SEP),$(OUTPUT_BIN)/$(OUTPUT_LIB)) 1>NUL 2>&1
+	-@$(RM) $(subst /,$(SEP),$(OUTPUT_BIN)/$(OUTPUT_LIB)).txt 1>NUL 2>&1
+
+# dependencies
+$(addprefix $(OUTPUT_PATH)/,$(C_OBJ)): $(OUTPUT_PATH)/%.o: $(PROJECT_BASE_PATH)/chip.h $(wildcard $(PROJECT_BASE_PATH)/include/*.h) $(wildcard $(CMSIS_BASE_PATH)/*.h)
+
diff --git a/hardware/sam/system/libsam/build_iar/libsam.ewd b/hardware/sam/system/libsam/build_iar/libsam.ewd
new file mode 100644
index 000000000..2570bbc89
--- /dev/null
+++ b/hardware/sam/system/libsam/build_iar/libsam.ewd
@@ -0,0 +1,3447 @@
+
+
+
+  2
+  
+    Debug
+    
+      ARM
+    
+    1
+    
+      C-SPY
+      2
+      
+        22
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ARMSIM_ID
+      2
+      
+        1
+        1
+        1
+        
+        
+        
+        
+      
+    
+    
+      ANGEL_ID
+      2
+      
+        0
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      GDBSERVER_ID
+      2
+      
+        0
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARROM_ID
+      2
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      JLINK_ID
+      2
+      
+        13
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      LMIFTDI_ID
+      2
+      
+        2
+        1
+        1
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      MACRAIGOR_ID
+      2
+      
+        3
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      PEMICRO_ID
+      2
+      
+        0
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      RDI_ID
+      2
+      
+        2
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      STLINK_ID
+      2
+      
+        2
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      THIRDPARTY_ID
+      2
+      
+        0
+        1
+        1
+        
+        
+        
+        
+      
+    
+    
+      
+        $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+        0
+      
+      
+        $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+        1
+      
+      
+        $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+        0
+      
+      
+        $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin
+        1
+      
+    
+  
+  
+    Release
+    
+      ARM
+    
+    0
+    
+      C-SPY
+      2
+      
+        22
+        1
+        0
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ARMSIM_ID
+      2
+      
+        1
+        1
+        0
+        
+        
+        
+        
+      
+    
+    
+      ANGEL_ID
+      2
+      
+        0
+        1
+        0
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      GDBSERVER_ID
+      2
+      
+        0
+        1
+        0
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARROM_ID
+      2
+      
+        1
+        1
+        0
+        
+        
+        
+        
+        
+      
+    
+    
+      JLINK_ID
+      2
+      
+        13
+        1
+        0
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      LMIFTDI_ID
+      2
+      
+        2
+        1
+        0
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      MACRAIGOR_ID
+      2
+      
+        3
+        1
+        0
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      PEMICRO_ID
+      2
+      
+        0
+        1
+        0
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      RDI_ID
+      2
+      
+        2
+        1
+        0
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      STLINK_ID
+      2
+      
+        2
+        1
+        0
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      THIRDPARTY_ID
+      2
+      
+        0
+        1
+        0
+        
+        
+        
+        
+      
+    
+    
+      
+        $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+        0
+      
+      
+        $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+        1
+      
+      
+        $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+        0
+      
+      
+        $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin
+        1
+      
+    
+  
+  
+    Debug_sam3s
+    
+      ARM
+    
+    1
+    
+      C-SPY
+      2
+      
+        22
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ARMSIM_ID
+      2
+      
+        1
+        1
+        1
+        
+        
+        
+        
+      
+    
+    
+      ANGEL_ID
+      2
+      
+        0
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      GDBSERVER_ID
+      2
+      
+        0
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARROM_ID
+      2
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      JLINK_ID
+      2
+      
+        13
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      LMIFTDI_ID
+      2
+      
+        2
+        1
+        1
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      MACRAIGOR_ID
+      2
+      
+        3
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      PEMICRO_ID
+      2
+      
+        0
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
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+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\smc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\spi.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\ssc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\supc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\tc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\twi.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\uart.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\udp.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\usart.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\wdt.h
+          
+        
+        
+          instance
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\acc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\adc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\chipid.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\crccu.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\dacc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\efc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\gpbr.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\hsmci.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\matrix.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\pioa.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\piob.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\pioc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\pmc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\pwm.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\rstc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\rtc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\rtt.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\smc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\spi.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\ssc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\supc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\tc0.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\tc1.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\twi0.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\twi1.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\uart0.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\uart1.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\udp.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\usart0.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\usart1.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\wdt.h
+          
+        
+        
+          pio
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\pio\sam3s1a.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\pio\sam3s1b.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\pio\sam3s1c.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\pio\sam3s2a.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\pio\sam3s2b.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\pio\sam3s2c.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\pio\sam3s4a.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\pio\sam3s4b.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\pio\sam3s4c.h
+          
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3s\include\sam3s.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3s\include\sam3s1a.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3s\include\sam3s1b.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3s\include\sam3s1c.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3s\include\sam3s2a.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3s\include\sam3s2b.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3s\include\sam3s2c.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3s\include\sam3s4a.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3s\include\sam3s4b.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3s\include\sam3s4c.h
+        
+      
+      
+        source
+        
+          templates
+          
+            iar
+            
+              $PROJ_DIR$\..\cmsis\sam3s\source\templates\iar\startup_sam3s.c
+            
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\source\templates\exceptions.c
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\source\templates\exceptions.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\source\templates\system_sam3s.c
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\source\templates\system_sam3s.h
+          
+        
+      
+    
+    
+      sam3u
+      
+        Debug
+      
+      
+        include
+        
+          component
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\adc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\adc12b.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\chipid.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\dmac.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\efc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\gpbr.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\hsmci.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\matrix.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\pdc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\pio.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\pmc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\pwm.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\rstc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\rtc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\rtt.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\smc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\spi.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\ssc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\supc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\tc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\twi.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\uart.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\udphs.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\usart.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\wdt.h
+          
+        
+        
+          instance
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\adc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\adc12b.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\chipid.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\dmac.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\efc0.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\efc1.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\gpbr.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\hsmci.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\matrix.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\pioa.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\piob.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\pioc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\pmc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\pwm.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\rstc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\rtc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\rtt.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\smc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\spi.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\ssc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\supc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\tc0.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\twi0.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\twi1.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\uart.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\udphs.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\usart0.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\usart1.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\usart2.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\usart3.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\wdt.h
+          
+        
+        
+          pio
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\pio\sam3u1c.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\pio\sam3u1e.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\pio\sam3u2c.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\pio\sam3u2e.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\pio\sam3u4c.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\pio\sam3u4e.h
+          
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3u\include\sam3u.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3u\include\sam3u1c.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3u\include\sam3u1e.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3u\include\sam3u2c.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3u\include\sam3u2e.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3u\include\sam3u4c.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3u\include\sam3u4e.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3u\include\system_sam3u.h
+        
+      
+      
+        source
+        
+          templates
+          
+            iar
+            
+              $PROJ_DIR$\..\cmsis\sam3u\source\templates\iar\startup_sam3u.c
+            
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\source\templates\exceptions.c
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\source\templates\exceptions.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\source\templates\system_sam3u.c
+          
+        
+      
+    
+  
+  
+    include
+    
+      $PROJ_DIR$\..\include\adc.h
+    
+    
+      $PROJ_DIR$\..\include\pio.h
+    
+    
+      $PROJ_DIR$\..\include\pio_it.h
+    
+    
+      $PROJ_DIR$\..\include\pmc.h
+    
+    
+      $PROJ_DIR$\..\include\pwmc.h
+    
+    
+      $PROJ_DIR$\..\include\rtc.h
+    
+    
+      $PROJ_DIR$\..\include\rtt.h
+    
+    
+      $PROJ_DIR$\..\include\sam3.h
+    
+    
+      $PROJ_DIR$\..\include\spi.h
+    
+    
+      $PROJ_DIR$\..\include\tc.h
+    
+    
+      $PROJ_DIR$\..\include\timetick.h
+    
+    
+      $PROJ_DIR$\..\include\twi.h
+    
+    
+      $PROJ_DIR$\..\include\usart.h
+    
+    
+      $PROJ_DIR$\..\include\wdt.h
+    
+  
+  
+    source
+    
+      $PROJ_DIR$\..\source\adc.c
+    
+    
+      $PROJ_DIR$\..\source\pio.c
+    
+    
+      $PROJ_DIR$\..\source\pio_it.c
+      
+        Debug
+        Debug_sam3s
+      
+    
+    
+      $PROJ_DIR$\..\source\pmc.c
+    
+    
+      $PROJ_DIR$\..\source\pwmc.c
+    
+    
+      $PROJ_DIR$\..\source\rtc.c
+    
+    
+      $PROJ_DIR$\..\source\rtt.c
+    
+    
+      $PROJ_DIR$\..\source\spi.c
+    
+    
+      $PROJ_DIR$\..\source\tc.c
+    
+    
+      $PROJ_DIR$\..\source\timetick.c
+    
+    
+      $PROJ_DIR$\..\source\twi.c
+    
+    
+      $PROJ_DIR$\..\source\usart.c
+    
+    
+      $PROJ_DIR$\..\source\wdt.c
+    
+  
+  
+    $PROJ_DIR$\..\chip.h
+  
+
+
+
diff --git a/hardware/sam/system/libsam/build_iar/libsam.eww b/hardware/sam/system/libsam/build_iar/libsam.eww
new file mode 100644
index 000000000..1e4c9ea5d
--- /dev/null
+++ b/hardware/sam/system/libsam/build_iar/libsam.eww
@@ -0,0 +1,39 @@
+
+
+
+  
+    $WS_DIR$\..\..\..\cores\sam\build_iar\libarduino.ewp
+  
+  
+    $WS_DIR$\libsam.ewp
+  
+  
+    $WS_DIR$\..\..\..\variants\sam3s_ek\build_iar\libvariant_sam3s_ek.ewp
+  
+  
+    $WS_DIR$\..\..\..\cores\sam\validation\build_iar\test.ewp
+  
+  
+    
+      all_debug_sam3s
+      
+        libsam
+        Debug
+      
+      
+        libarduino
+        Debug
+      
+      
+        libsam3s_ek
+        Debug
+      
+      
+        test
+        Debug
+      
+    
+  
+
+
+
diff --git a/hardware/sam/system/libsam/chip.h b/hardware/sam/system/libsam/chip.h
new file mode 100644
index 000000000..01619527c
--- /dev/null
+++ b/hardware/sam/system/libsam/chip.h
@@ -0,0 +1,58 @@
+/*
+  Copyright (c) 2011 Arduino.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#ifndef _LIB_SAM_
+#define _LIB_SAM_
+
+/*
+ * Core and peripherals registers definitions
+ */
+#include "include/sam.h"
+
+/* Define attribute */
+#if defined (  __GNUC__  ) /* GCC CS3 */
+    #define WEAK __attribute__ ((weak))
+#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
+    #define WEAK __weak
+#endif
+
+/* Define NO_INIT attribute */
+#if defined (  __GNUC__  )
+    #define NO_INIT
+#elif defined ( __ICCARM__ )
+    #define NO_INIT __no_init
+#endif
+
+/*
+ * Peripherals
+ */
+#include "include/adc.h"
+#include "include/pio.h"
+#include "include/pmc.h"
+#include "include/pwmc.h"
+#include "include/rtc.h"
+#include "include/rtt.h"
+#include "include/spi.h"
+#include "include/tc.h"
+#include "include/twi.h"
+#include "include/usart.h"
+#include "include/wdt.h"
+
+#include "include/timetick.h"
+
+#endif /* _LIB_SAM_ */
diff --git a/hardware/sam/system/libsam/cmsis/ReadMe.txt b/hardware/sam/system/libsam/cmsis/ReadMe.txt
new file mode 100644
index 000000000..ba985a988
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/ReadMe.txt
@@ -0,0 +1,64 @@
+/*****************************************************************************
+ * @file     ReadMe.txt
+ * @purpose  Explanation how to use the Device folder and template files 
+ * @version  V2.10
+ * @date     25. July 2011
+ *****************************************************************************/
+
+Following directory structure and template files are given:
+
+  - 
+      |
+      +-- 
+            |
+            +-- Include
+            |     +- .h                           header file 
+            |     +- system_Device.h                      system include file 
+            +-- Source
+                  |
+                  + Templates
+                      +- system_.c                system source file 
+                      |
+                      +-- ARM
+                      |    +- startup_.s          startup file for ARMCC
+                      |
+                      +-- GCC
+                      |
+                      +-- IAR
+
+
+Copy the complete folder including files and replace:
+  - folder name 'Vendor' with the abbreviation for the device vendor  e.g.: NXP. 
+  - folder name 'Device' with your specific device name e.g.: LPC17xx.
+  - in the filenames 'Device' with your specific device name e.g.: LPC17xx. 
+
+
+The template files contain comments starting with 'ToDo: '
+There it is described what you need to do.
+
+
+The template files contain following placeholder:
+
+  
+   should be replaced with your specific device name.
+   e.g.: LPC17xx
+  
+  
+   should be replaced with a specific device interrupt name.
+  e.g.: TIM1 for Timer#1 interrupt.
+
+  
+   should be replaced with a dedicated device family
+  abbreviation (e.g.: LPC for LPC17xx device family)
+
+  Cortex-M#
+  Cortex-M# can be replaced with the specific Cortex-M number
+  e.g.: Cortex-M3
+
+
+
+Note:
+  Template files (i.e. startup_Device.s, system_Device.c) are application
+  specific and therefore expected to be copied into the application project
+  folder prior to use!
+  
\ No newline at end of file
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_adc.h b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_adc.h
new file mode 100644
index 000000000..4b4687b3f
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_adc.h
@@ -0,0 +1,380 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_ADC_COMPONENT_
+#define _SAM3N_ADC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Analog-to-digital Converter */
+/* ============================================================================= */
+/** \addtogroup SAM3N_ADC Analog-to-digital Converter */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Adc hardware registers */
+typedef struct {
+  WoReg ADC_CR;        /**< \brief (Adc Offset: 0x00) Control Register */
+  RwReg ADC_MR;        /**< \brief (Adc Offset: 0x04) Mode Register */
+  RwReg ADC_SEQR1;     /**< \brief (Adc Offset: 0x08) Channel Sequence Register 1 */
+  RwReg ADC_SEQR2;     /**< \brief (Adc Offset: 0x0C) Channel Sequence Register 2 */
+  WoReg ADC_CHER;      /**< \brief (Adc Offset: 0x10) Channel Enable Register */
+  WoReg ADC_CHDR;      /**< \brief (Adc Offset: 0x14) Channel Disable Register */
+  RoReg ADC_CHSR;      /**< \brief (Adc Offset: 0x18) Channel Status Register */
+  RoReg Reserved1[1];
+  RoReg ADC_LCDR;      /**< \brief (Adc Offset: 0x20) Last Converted Data Register */
+  WoReg ADC_IER;       /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */
+  WoReg ADC_IDR;       /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */
+  RoReg ADC_IMR;       /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */
+  RoReg ADC_ISR;       /**< \brief (Adc Offset: 0x30) Interrupt Status Register */
+  RoReg Reserved2[2];
+  RoReg ADC_OVER;      /**< \brief (Adc Offset: 0x3C) Overrun Status Register */
+  RwReg ADC_EMR;       /**< \brief (Adc Offset: 0x40) Extended Mode Register */
+  RwReg ADC_CWR;       /**< \brief (Adc Offset: 0x44) Compare Window Register */
+  RoReg Reserved3[2];
+  RoReg ADC_CDR[16];   /**< \brief (Adc Offset: 0x50) Channel Data Register */
+  RoReg Reserved4[12];
+  RwReg ADC_TRGR;      /**< \brief (Adc Offset: 0xC0) Trigger Register */
+  RoReg Reserved5[8];
+  RwReg ADC_WPMR;      /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */
+  RoReg ADC_WPSR;      /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved6[5];
+  RwReg ADC_RPR;       /**< \brief (Adc Offset: 0x100) Receive Pointer Register */
+  RwReg ADC_RCR;       /**< \brief (Adc Offset: 0x104) Receive Counter Register */
+  RwReg ADC_TPR;       /**< \brief (Adc Offset: 0x108) Transmit Pointer Register */
+  RwReg ADC_TCR;       /**< \brief (Adc Offset: 0x10C) Transmit Counter Register */
+  RwReg ADC_RNPR;      /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */
+  RwReg ADC_RNCR;      /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */
+  RwReg ADC_TNPR;      /**< \brief (Adc Offset: 0x118) Transmit Next Pointer Register */
+  RwReg ADC_TNCR;      /**< \brief (Adc Offset: 0x11C) Transmit Next Counter Register */
+  WoReg ADC_PTCR;      /**< \brief (Adc Offset: 0x120) Transfer Control Register */
+  RoReg ADC_PTSR;      /**< \brief (Adc Offset: 0x124) Transfer Status Register */
+} Adc;
+#endif /* __ASSEMBLY__ */
+/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */
+#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */
+#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */
+/* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */
+#define ADC_SEQR1_USCH1_Pos 0
+#define ADC_SEQR1_USCH1_Msk (0xfu << ADC_SEQR1_USCH1_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 1 */
+#define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos)))
+#define ADC_SEQR1_USCH2_Pos 4
+#define ADC_SEQR1_USCH2_Msk (0xfu << ADC_SEQR1_USCH2_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 2 */
+#define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos)))
+#define ADC_SEQR1_USCH3_Pos 8
+#define ADC_SEQR1_USCH3_Msk (0xfu << ADC_SEQR1_USCH3_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 3 */
+#define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos)))
+#define ADC_SEQR1_USCH4_Pos 12
+#define ADC_SEQR1_USCH4_Msk (0xfu << ADC_SEQR1_USCH4_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 4 */
+#define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos)))
+#define ADC_SEQR1_USCH5_Pos 16
+#define ADC_SEQR1_USCH5_Msk (0xfu << ADC_SEQR1_USCH5_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 5 */
+#define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos)))
+#define ADC_SEQR1_USCH6_Pos 20
+#define ADC_SEQR1_USCH6_Msk (0xfu << ADC_SEQR1_USCH6_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 6 */
+#define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos)))
+#define ADC_SEQR1_USCH7_Pos 24
+#define ADC_SEQR1_USCH7_Msk (0xfu << ADC_SEQR1_USCH7_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 7 */
+#define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos)))
+#define ADC_SEQR1_USCH8_Pos 28
+#define ADC_SEQR1_USCH8_Msk (0xfu << ADC_SEQR1_USCH8_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 8 */
+#define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos)))
+/* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */
+#define ADC_SEQR2_USCH9_Pos 0
+#define ADC_SEQR2_USCH9_Msk (0xfu << ADC_SEQR2_USCH9_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 9 */
+#define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos)))
+#define ADC_SEQR2_USCH10_Pos 4
+#define ADC_SEQR2_USCH10_Msk (0xfu << ADC_SEQR2_USCH10_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 10 */
+#define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos)))
+#define ADC_SEQR2_USCH11_Pos 8
+#define ADC_SEQR2_USCH11_Msk (0xfu << ADC_SEQR2_USCH11_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 11 */
+#define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos)))
+#define ADC_SEQR2_USCH12_Pos 12
+#define ADC_SEQR2_USCH12_Msk (0xfu << ADC_SEQR2_USCH12_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 12 */
+#define ADC_SEQR2_USCH12(value) ((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos)))
+#define ADC_SEQR2_USCH13_Pos 16
+#define ADC_SEQR2_USCH13_Msk (0xfu << ADC_SEQR2_USCH13_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 13 */
+#define ADC_SEQR2_USCH13(value) ((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos)))
+#define ADC_SEQR2_USCH14_Pos 20
+#define ADC_SEQR2_USCH14_Msk (0xfu << ADC_SEQR2_USCH14_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 14 */
+#define ADC_SEQR2_USCH14(value) ((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos)))
+#define ADC_SEQR2_USCH15_Pos 24
+#define ADC_SEQR2_USCH15_Msk (0xfu << ADC_SEQR2_USCH15_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 15 */
+#define ADC_SEQR2_USCH15(value) ((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos)))
+#define ADC_SEQR2_USCH16_Pos 28
+#define ADC_SEQR2_USCH16_Msk (0xfu << ADC_SEQR2_USCH16_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 16 */
+#define ADC_SEQR2_USCH16(value) ((ADC_SEQR2_USCH16_Msk & ((value) << ADC_SEQR2_USCH16_Pos)))
+/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */
+#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */
+#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */
+#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */
+#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */
+#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */
+#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */
+#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */
+#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */
+#define ADC_CHER_CH8 (0x1u << 8) /**< \brief (ADC_CHER) Channel 8 Enable */
+#define ADC_CHER_CH9 (0x1u << 9) /**< \brief (ADC_CHER) Channel 9 Enable */
+#define ADC_CHER_CH10 (0x1u << 10) /**< \brief (ADC_CHER) Channel 10 Enable */
+#define ADC_CHER_CH11 (0x1u << 11) /**< \brief (ADC_CHER) Channel 11 Enable */
+#define ADC_CHER_CH12 (0x1u << 12) /**< \brief (ADC_CHER) Channel 12 Enable */
+#define ADC_CHER_CH13 (0x1u << 13) /**< \brief (ADC_CHER) Channel 13 Enable */
+#define ADC_CHER_CH14 (0x1u << 14) /**< \brief (ADC_CHER) Channel 14 Enable */
+#define ADC_CHER_CH15 (0x1u << 15) /**< \brief (ADC_CHER) Channel 15 Enable */
+/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */
+#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */
+#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */
+#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */
+#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */
+#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */
+#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */
+#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */
+#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */
+#define ADC_CHDR_CH8 (0x1u << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */
+#define ADC_CHDR_CH9 (0x1u << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */
+#define ADC_CHDR_CH10 (0x1u << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */
+#define ADC_CHDR_CH11 (0x1u << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */
+#define ADC_CHDR_CH12 (0x1u << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */
+#define ADC_CHDR_CH13 (0x1u << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */
+#define ADC_CHDR_CH14 (0x1u << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */
+#define ADC_CHDR_CH15 (0x1u << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */
+/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */
+#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */
+#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */
+#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */
+#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */
+#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */
+#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */
+#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */
+#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */
+#define ADC_CHSR_CH8 (0x1u << 8) /**< \brief (ADC_CHSR) Channel 8 Status */
+#define ADC_CHSR_CH9 (0x1u << 9) /**< \brief (ADC_CHSR) Channel 9 Status */
+#define ADC_CHSR_CH10 (0x1u << 10) /**< \brief (ADC_CHSR) Channel 10 Status */
+#define ADC_CHSR_CH11 (0x1u << 11) /**< \brief (ADC_CHSR) Channel 11 Status */
+#define ADC_CHSR_CH12 (0x1u << 12) /**< \brief (ADC_CHSR) Channel 12 Status */
+#define ADC_CHSR_CH13 (0x1u << 13) /**< \brief (ADC_CHSR) Channel 13 Status */
+#define ADC_CHSR_CH14 (0x1u << 14) /**< \brief (ADC_CHSR) Channel 14 Status */
+#define ADC_CHSR_CH15 (0x1u << 15) /**< \brief (ADC_CHSR) Channel 15 Status */
+/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */
+#define ADC_LCDR_LDATA_Pos 0
+#define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */
+#define ADC_LCDR_CHNB_Pos 12
+#define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) /**< \brief (ADC_LCDR) Channel Number */
+/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */
+#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */
+#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */
+#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */
+#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */
+#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */
+#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */
+#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */
+#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */
+#define ADC_IER_EOC8 (0x1u << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */
+#define ADC_IER_EOC9 (0x1u << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */
+#define ADC_IER_EOC10 (0x1u << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */
+#define ADC_IER_EOC11 (0x1u << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */
+#define ADC_IER_EOC12 (0x1u << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */
+#define ADC_IER_EOC13 (0x1u << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */
+#define ADC_IER_EOC14 (0x1u << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */
+#define ADC_IER_EOC15 (0x1u << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */
+#define ADC_IER_DRDY (0x1u << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */
+#define ADC_IER_GOVRE (0x1u << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */
+#define ADC_IER_COMPE (0x1u << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */
+#define ADC_IER_ENDRX (0x1u << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */
+#define ADC_IER_RXBUFF (0x1u << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */
+/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */
+#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */
+#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */
+#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */
+#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */
+#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */
+#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */
+#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */
+#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */
+#define ADC_IDR_EOC8 (0x1u << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */
+#define ADC_IDR_EOC9 (0x1u << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */
+#define ADC_IDR_EOC10 (0x1u << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */
+#define ADC_IDR_EOC11 (0x1u << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */
+#define ADC_IDR_EOC12 (0x1u << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */
+#define ADC_IDR_EOC13 (0x1u << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */
+#define ADC_IDR_EOC14 (0x1u << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */
+#define ADC_IDR_EOC15 (0x1u << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */
+#define ADC_IDR_DRDY (0x1u << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */
+#define ADC_IDR_GOVRE (0x1u << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */
+#define ADC_IDR_COMPE (0x1u << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */
+#define ADC_IDR_ENDRX (0x1u << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */
+#define ADC_IDR_RXBUFF (0x1u << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */
+/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */
+#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */
+#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */
+#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */
+#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */
+#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */
+#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */
+#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */
+#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */
+#define ADC_IMR_EOC8 (0x1u << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */
+#define ADC_IMR_EOC9 (0x1u << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */
+#define ADC_IMR_EOC10 (0x1u << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */
+#define ADC_IMR_EOC11 (0x1u << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */
+#define ADC_IMR_EOC12 (0x1u << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */
+#define ADC_IMR_EOC13 (0x1u << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */
+#define ADC_IMR_EOC14 (0x1u << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */
+#define ADC_IMR_EOC15 (0x1u << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */
+#define ADC_IMR_DRDY (0x1u << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */
+#define ADC_IMR_GOVRE (0x1u << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */
+#define ADC_IMR_COMPE (0x1u << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */
+#define ADC_IMR_ENDRX (0x1u << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */
+#define ADC_IMR_RXBUFF (0x1u << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */
+/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */
+#define ADC_ISR_EOC0 (0x1u << 0) /**< \brief (ADC_ISR) End of Conversion 0 */
+#define ADC_ISR_EOC1 (0x1u << 1) /**< \brief (ADC_ISR) End of Conversion 1 */
+#define ADC_ISR_EOC2 (0x1u << 2) /**< \brief (ADC_ISR) End of Conversion 2 */
+#define ADC_ISR_EOC3 (0x1u << 3) /**< \brief (ADC_ISR) End of Conversion 3 */
+#define ADC_ISR_EOC4 (0x1u << 4) /**< \brief (ADC_ISR) End of Conversion 4 */
+#define ADC_ISR_EOC5 (0x1u << 5) /**< \brief (ADC_ISR) End of Conversion 5 */
+#define ADC_ISR_EOC6 (0x1u << 6) /**< \brief (ADC_ISR) End of Conversion 6 */
+#define ADC_ISR_EOC7 (0x1u << 7) /**< \brief (ADC_ISR) End of Conversion 7 */
+#define ADC_ISR_EOC8 (0x1u << 8) /**< \brief (ADC_ISR) End of Conversion 8 */
+#define ADC_ISR_EOC9 (0x1u << 9) /**< \brief (ADC_ISR) End of Conversion 9 */
+#define ADC_ISR_EOC10 (0x1u << 10) /**< \brief (ADC_ISR) End of Conversion 10 */
+#define ADC_ISR_EOC11 (0x1u << 11) /**< \brief (ADC_ISR) End of Conversion 11 */
+#define ADC_ISR_EOC12 (0x1u << 12) /**< \brief (ADC_ISR) End of Conversion 12 */
+#define ADC_ISR_EOC13 (0x1u << 13) /**< \brief (ADC_ISR) End of Conversion 13 */
+#define ADC_ISR_EOC14 (0x1u << 14) /**< \brief (ADC_ISR) End of Conversion 14 */
+#define ADC_ISR_EOC15 (0x1u << 15) /**< \brief (ADC_ISR) End of Conversion 15 */
+#define ADC_ISR_DRDY (0x1u << 24) /**< \brief (ADC_ISR) Data Ready */
+#define ADC_ISR_GOVRE (0x1u << 25) /**< \brief (ADC_ISR) General Overrun Error */
+#define ADC_ISR_COMPE (0x1u << 26) /**< \brief (ADC_ISR) Comparison Error */
+#define ADC_ISR_ENDRX (0x1u << 27) /**< \brief (ADC_ISR) End of RX Buffer */
+#define ADC_ISR_RXBUFF (0x1u << 28) /**< \brief (ADC_ISR) RX Buffer Full */
+/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */
+#define ADC_OVER_OVRE0 (0x1u << 0) /**< \brief (ADC_OVER) Overrun Error 0 */
+#define ADC_OVER_OVRE1 (0x1u << 1) /**< \brief (ADC_OVER) Overrun Error 1 */
+#define ADC_OVER_OVRE2 (0x1u << 2) /**< \brief (ADC_OVER) Overrun Error 2 */
+#define ADC_OVER_OVRE3 (0x1u << 3) /**< \brief (ADC_OVER) Overrun Error 3 */
+#define ADC_OVER_OVRE4 (0x1u << 4) /**< \brief (ADC_OVER) Overrun Error 4 */
+#define ADC_OVER_OVRE5 (0x1u << 5) /**< \brief (ADC_OVER) Overrun Error 5 */
+#define ADC_OVER_OVRE6 (0x1u << 6) /**< \brief (ADC_OVER) Overrun Error 6 */
+#define ADC_OVER_OVRE7 (0x1u << 7) /**< \brief (ADC_OVER) Overrun Error 7 */
+#define ADC_OVER_OVRE8 (0x1u << 8) /**< \brief (ADC_OVER) Overrun Error 8 */
+#define ADC_OVER_OVRE9 (0x1u << 9) /**< \brief (ADC_OVER) Overrun Error 9 */
+#define ADC_OVER_OVRE10 (0x1u << 10) /**< \brief (ADC_OVER) Overrun Error 10 */
+#define ADC_OVER_OVRE11 (0x1u << 11) /**< \brief (ADC_OVER) Overrun Error 11 */
+#define ADC_OVER_OVRE12 (0x1u << 12) /**< \brief (ADC_OVER) Overrun Error 12 */
+#define ADC_OVER_OVRE13 (0x1u << 13) /**< \brief (ADC_OVER) Overrun Error 13 */
+#define ADC_OVER_OVRE14 (0x1u << 14) /**< \brief (ADC_OVER) Overrun Error 14 */
+#define ADC_OVER_OVRE15 (0x1u << 15) /**< \brief (ADC_OVER) Overrun Error 15 */
+/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */
+#define ADC_EMR_CMPMODE_Pos 0
+#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /**< \brief (ADC_EMR) Comparison Mode */
+#define   ADC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */
+#define   ADC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */
+#define   ADC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is in the comparison window. */
+#define   ADC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is out of the comparison window. */
+#define ADC_EMR_CMPSEL_Pos 4
+#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /**< \brief (ADC_EMR) Comparison Selected Channel */
+#define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos)))
+#define ADC_EMR_CMPALL (0x1u << 9) /**< \brief (ADC_EMR) Compare All Channels */
+#define ADC_EMR_TAG (0x1u << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */
+/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */
+#define ADC_CWR_LOWTHRES_Pos 0
+#define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) /**< \brief (ADC_CWR) Low Threshold */
+#define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos)))
+#define ADC_CWR_HIGHTHRES_Pos 16
+#define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) /**< \brief (ADC_CWR) High Threshold */
+#define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos)))
+/* -------- ADC_CDR[16] : (ADC Offset: 0x50) Channel Data Register -------- */
+#define ADC_CDR_DATA_Pos 0
+#define ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[16]) Converted Data */
+/* -------- ADC_TRGR : (ADC Offset: 0xC0) Trigger Register -------- */
+#define ADC_TRGR_TRGMOD_Pos 0
+#define ADC_TRGR_TRGMOD_Msk (0x7u << ADC_TRGR_TRGMOD_Pos) /**< \brief (ADC_TRGR) Trigger Mode */
+#define   ADC_TRGR_TRGMOD_NO_TRIGGER (0x0u << 0) /**< \brief (ADC_TRGR) No trigger, only software trigger can start conversions */
+#define   ADC_TRGR_TRGMOD_EXT_TRIG_RISE (0x1u << 0) /**< \brief (ADC_TRGR) External Trigger Rising Edge */
+#define   ADC_TRGR_TRGMOD_EXT_TRIG_FALL (0x2u << 0) /**< \brief (ADC_TRGR) External Trigger Falling Edge */
+#define   ADC_TRGR_TRGMOD_EXT_TRIG_ANY (0x3u << 0) /**< \brief (ADC_TRGR) External Trigger Any Edge */
+#define   ADC_TRGR_TRGMOD_PERIOD_TRIG (0x5u << 0) /**< \brief (ADC_TRGR) Periodic Trigger (TRGPER shall be initiated appropriately) */
+#define   ADC_TRGR_TRGMOD_CONTINUOUS (0x6u << 0) /**< \brief (ADC_TRGR) Continuous Mode */
+#define ADC_TRGR_TRGPER_Pos 16
+#define ADC_TRGR_TRGPER_Msk (0xffffu << ADC_TRGR_TRGPER_Pos) /**< \brief (ADC_TRGR) Trigger Period */
+#define ADC_TRGR_TRGPER(value) ((ADC_TRGR_TRGPER_Msk & ((value) << ADC_TRGR_TRGPER_Pos)))
+/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */
+#define ADC_WPMR_WPEN (0x1u << 0) /**< \brief (ADC_WPMR) Write Protect Enable */
+#define ADC_WPMR_WPKEY_Pos 8
+#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /**< \brief (ADC_WPMR) Write Protect KEY */
+#define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos)))
+/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */
+#define ADC_WPSR_WPVS (0x1u << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */
+#define ADC_WPSR_WPVSRC_Pos 8
+#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /**< \brief (ADC_WPSR) Write Protect Violation Source */
+/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */
+#define ADC_RPR_RXPTR_Pos 0
+#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */
+#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos)))
+/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */
+#define ADC_RCR_RXCTR_Pos 0
+#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */
+#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos)))
+/* -------- ADC_TPR : (ADC Offset: 0x108) Transmit Pointer Register -------- */
+#define ADC_TPR_TXPTR_Pos 0
+#define ADC_TPR_TXPTR_Msk (0xffffffffu << ADC_TPR_TXPTR_Pos) /**< \brief (ADC_TPR) Transmit Counter Register */
+#define ADC_TPR_TXPTR(value) ((ADC_TPR_TXPTR_Msk & ((value) << ADC_TPR_TXPTR_Pos)))
+/* -------- ADC_TCR : (ADC Offset: 0x10C) Transmit Counter Register -------- */
+#define ADC_TCR_TXCTR_Pos 0
+#define ADC_TCR_TXCTR_Msk (0xffffu << ADC_TCR_TXCTR_Pos) /**< \brief (ADC_TCR) Transmit Counter Register */
+#define ADC_TCR_TXCTR(value) ((ADC_TCR_TXCTR_Msk & ((value) << ADC_TCR_TXCTR_Pos)))
+/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */
+#define ADC_RNPR_RXNPTR_Pos 0
+#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */
+#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos)))
+/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */
+#define ADC_RNCR_RXNCTR_Pos 0
+#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */
+#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos)))
+/* -------- ADC_TNPR : (ADC Offset: 0x118) Transmit Next Pointer Register -------- */
+#define ADC_TNPR_TXNPTR_Pos 0
+#define ADC_TNPR_TXNPTR_Msk (0xffffffffu << ADC_TNPR_TXNPTR_Pos) /**< \brief (ADC_TNPR) Transmit Next Pointer */
+#define ADC_TNPR_TXNPTR(value) ((ADC_TNPR_TXNPTR_Msk & ((value) << ADC_TNPR_TXNPTR_Pos)))
+/* -------- ADC_TNCR : (ADC Offset: 0x11C) Transmit Next Counter Register -------- */
+#define ADC_TNCR_TXNCTR_Pos 0
+#define ADC_TNCR_TXNCTR_Msk (0xffffu << ADC_TNCR_TXNCTR_Pos) /**< \brief (ADC_TNCR) Transmit Counter Next */
+#define ADC_TNCR_TXNCTR(value) ((ADC_TNCR_TXNCTR_Msk & ((value) << ADC_TNCR_TXNCTR_Pos)))
+/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */
+#define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */
+#define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */
+#define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */
+#define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */
+/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */
+#define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */
+#define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3N_ADC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_chipid.h b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_chipid.h
new file mode 100644
index 000000000..a008d67ae
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_chipid.h
@@ -0,0 +1,159 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_CHIPID_COMPONENT_
+#define _SAM3N_CHIPID_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Chip Identifier */
+/* ============================================================================= */
+/** \addtogroup SAM3N_CHIPID Chip Identifier */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Chipid hardware registers */
+typedef struct {
+  RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */
+  RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */
+} Chipid;
+#endif /* __ASSEMBLY__ */
+/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */
+#define CHIPID_CIDR_VERSION_Pos 0
+#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */
+#define CHIPID_CIDR_EPROC_Pos 5
+#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */
+#define   CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */
+#define   CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */
+#define   CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */
+#define   CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */
+#define   CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */
+#define   CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */
+#define   CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */
+#define CHIPID_CIDR_NVPSIZ_Pos 8
+#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */
+#define   CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */
+#define   CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define   CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define   CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_NVPSIZ2_Pos 12
+#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */
+#define   CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */
+#define   CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_SRAMSIZ_Pos 16
+#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */
+#define   CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_1K (0x1u << 16) /**< \brief (CHIPID_CIDR) 1K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define CHIPID_CIDR_ARCH_Pos 20
+#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */
+#define   CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */
+#define   CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */
+#define   CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */
+#define   CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */
+#define   CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */
+#define   CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */
+#define   CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */
+#define   CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */
+#define   CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */
+#define   CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM4AxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM4XxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM4XxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxG Series (208/217-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM4XxG Series (208/217-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM3SxASeries (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM4SxA Series (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM3SxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM4SxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM3SxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM4SxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */
+#define   CHIPID_CIDR_ARCH_SAM3NxA (0x93u << 20) /**< \brief (CHIPID_CIDR) SAM3NxA Series (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3NxB (0x94u << 20) /**< \brief (CHIPID_CIDR) SAM3NxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3NxC (0x95u << 20) /**< \brief (CHIPID_CIDR) SAM3NxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */
+#define   CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */
+#define CHIPID_CIDR_NVPTYP_Pos 28
+#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */
+#define   CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */
+#define   CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */
+#define   CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */
+#define   CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size      NVPSIZ2 is Flash size */
+#define   CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */
+#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */
+/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */
+#define CHIPID_EXID_EXID_Pos 0
+#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */
+
+/*@}*/
+
+
+#endif /* _SAM3N_CHIPID_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_dacc.h b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_dacc.h
new file mode 100644
index 000000000..5608c129c
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_dacc.h
@@ -0,0 +1,156 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_DACC_COMPONENT_
+#define _SAM3N_DACC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3N_DACC Digital-to-Analog Converter Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Dacc hardware registers */
+typedef struct {
+  WoReg DACC_CR;       /**< \brief (Dacc Offset: 0x00) Control Register */
+  RwReg DACC_MR;       /**< \brief (Dacc Offset: 0x04) Mode Register */
+  WoReg DACC_CDR;      /**< \brief (Dacc Offset: 0x08) Conversion Data Register */
+  WoReg DACC_IER;      /**< \brief (Dacc Offset: 0x0C) Interrupt Enable Register */
+  WoReg DACC_IDR;      /**< \brief (Dacc Offset: 0x10) Interrupt Disable Register */
+  RoReg DACC_IMR;      /**< \brief (Dacc Offset: 0x14) Interrupt Mask Register */
+  RoReg DACC_ISR;      /**< \brief (Dacc Offset: 0x18) Interrupt Status Register */
+  RoReg Reserved1[50];
+  RwReg DACC_WPMR;     /**< \brief (Dacc Offset: 0xE4) Write Protect Mode Register */
+  RoReg DACC_WPSR;     /**< \brief (Dacc Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved2[5];
+  RwReg DACC_RPR;      /**< \brief (Dacc Offset: 0x100) Receive Pointer Register */
+  RwReg DACC_RCR;      /**< \brief (Dacc Offset: 0x104) Receive Counter Register */
+  RwReg DACC_TPR;      /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */
+  RwReg DACC_TCR;      /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */
+  RwReg DACC_RNPR;     /**< \brief (Dacc Offset: 0x110) Receive Next Pointer Register */
+  RwReg DACC_RNCR;     /**< \brief (Dacc Offset: 0x114) Receive Next Counter Register */
+  RwReg DACC_TNPR;     /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */
+  RwReg DACC_TNCR;     /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */
+  WoReg DACC_PTCR;     /**< \brief (Dacc Offset: 0x120) Transfer Control Register */
+  RoReg DACC_PTSR;     /**< \brief (Dacc Offset: 0x124) Transfer Status Register */
+} Dacc;
+#endif /* __ASSEMBLY__ */
+/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */
+#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */
+/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */
+#define DACC_MR_TRGEN (0x1u << 0) /**< \brief (DACC_MR) Trigger Enable */
+#define DACC_MR_TRGSEL_Pos 1
+#define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) /**< \brief (DACC_MR) Trigger Selection */
+#define   DACC_MR_TRGSEL_TRGSEL0 (0x0u << 1) /**< \brief (DACC_MR) External trigger */
+#define   DACC_MR_TRGSEL_TRGSEL1 (0x1u << 1) /**< \brief (DACC_MR) TIO Output of the Timer Counter Channel 0 */
+#define   DACC_MR_TRGSEL_TRGSEL2 (0x2u << 1) /**< \brief (DACC_MR) TIO Output of the Timer Counter Channel 1 */
+#define   DACC_MR_TRGSEL_TRGSEL3 (0x3u << 1) /**< \brief (DACC_MR) TIO Output of the Timer Counter Channel 2 */
+#define DACC_MR_DACEN (0x1u << 4) /**< \brief (DACC_MR) DAC enable */
+#define DACC_MR_WORD (0x1u << 5) /**< \brief (DACC_MR) Word Transfer */
+#define DACC_MR_STARTUP_Pos 8
+#define DACC_MR_STARTUP_Msk (0xffu << DACC_MR_STARTUP_Pos) /**< \brief (DACC_MR) Startup Time Selection */
+#define DACC_MR_STARTUP(value) ((DACC_MR_STARTUP_Msk & ((value) << DACC_MR_STARTUP_Pos)))
+#define DACC_MR_CLKDIV_Pos 16
+#define DACC_MR_CLKDIV_Msk (0xffffu << DACC_MR_CLKDIV_Pos) /**< \brief (DACC_MR) DAC Clock Divider for Internal Trigger */
+#define DACC_MR_CLKDIV(value) ((DACC_MR_CLKDIV_Msk & ((value) << DACC_MR_CLKDIV_Pos)))
+/* -------- DACC_CDR : (DACC Offset: 0x08) Conversion Data Register -------- */
+#define DACC_CDR_DATA_Pos 0
+#define DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos) /**< \brief (DACC_CDR) Data to Convert */
+#define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos)))
+/* -------- DACC_IER : (DACC Offset: 0x0C) Interrupt Enable Register -------- */
+#define DACC_IER_TXRDY (0x1u << 0) /**< \brief (DACC_IER) Transmission Ready Interrupt Enable */
+#define DACC_IER_ENDTX (0x1u << 1) /**< \brief (DACC_IER) End of PDC Interrupt Enable */
+#define DACC_IER_TXBUFE (0x1u << 2) /**< \brief (DACC_IER) Buffer Empty Interrupt Enable */
+/* -------- DACC_IDR : (DACC Offset: 0x10) Interrupt Disable Register -------- */
+#define DACC_IDR_TXRDY (0x1u << 0) /**< \brief (DACC_IDR) Transmission Ready Interrupt Disable */
+#define DACC_IDR_ENDTX (0x1u << 1) /**< \brief (DACC_IDR) End of PDC Interrupt Disable */
+#define DACC_IDR_TXBUFE (0x1u << 2) /**< \brief (DACC_IDR) Buffer Empty Interrupt Disable */
+/* -------- DACC_IMR : (DACC Offset: 0x14) Interrupt Mask Register -------- */
+#define DACC_IMR_TXRDY (0x1u << 0) /**< \brief (DACC_IMR) Transmission Ready Interrupt Mask */
+#define DACC_IMR_ENDTX (0x1u << 1) /**< \brief (DACC_IMR) End of PDC Interrupt Mask */
+#define DACC_IMR_TXBUFE (0x1u << 2) /**< \brief (DACC_IMR) Buffer Empty Interrupt Mask */
+/* -------- DACC_ISR : (DACC Offset: 0x18) Interrupt Status Register -------- */
+#define DACC_ISR_TXRDY (0x1u << 0) /**< \brief (DACC_ISR) Transmission Ready Interrupt Flag */
+#define DACC_ISR_ENDTX (0x1u << 1) /**< \brief (DACC_ISR) End of PDC Interrupt Flag */
+#define DACC_ISR_TXBUFE (0x1u << 2) /**< \brief (DACC_ISR) Buffer Empty Interrupt Flag */
+/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode Register -------- */
+#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protect Enable */
+#define DACC_WPMR_WPKEY_Pos 8
+#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect KEY */
+#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))
+/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status Register -------- */
+#define DACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (DACC_WPSR) Write protection error */
+#define DACC_WPSR_WPROTADDR_Pos 8
+#define DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos) /**< \brief (DACC_WPSR) Write protection error address */
+/* -------- DACC_RPR : (DACC Offset: 0x100) Receive Pointer Register -------- */
+#define DACC_RPR_RXPTR_Pos 0
+#define DACC_RPR_RXPTR_Msk (0xffffffffu << DACC_RPR_RXPTR_Pos) /**< \brief (DACC_RPR) Receive Pointer Register */
+#define DACC_RPR_RXPTR(value) ((DACC_RPR_RXPTR_Msk & ((value) << DACC_RPR_RXPTR_Pos)))
+/* -------- DACC_RCR : (DACC Offset: 0x104) Receive Counter Register -------- */
+#define DACC_RCR_RXCTR_Pos 0
+#define DACC_RCR_RXCTR_Msk (0xffffu << DACC_RCR_RXCTR_Pos) /**< \brief (DACC_RCR) Receive Counter Register */
+#define DACC_RCR_RXCTR(value) ((DACC_RCR_RXCTR_Msk & ((value) << DACC_RCR_RXCTR_Pos)))
+/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */
+#define DACC_TPR_TXPTR_Pos 0
+#define DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos) /**< \brief (DACC_TPR) Transmit Counter Register */
+#define DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos)))
+/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */
+#define DACC_TCR_TXCTR_Pos 0
+#define DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos) /**< \brief (DACC_TCR) Transmit Counter Register */
+#define DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos)))
+/* -------- DACC_RNPR : (DACC Offset: 0x110) Receive Next Pointer Register -------- */
+#define DACC_RNPR_RXNPTR_Pos 0
+#define DACC_RNPR_RXNPTR_Msk (0xffffffffu << DACC_RNPR_RXNPTR_Pos) /**< \brief (DACC_RNPR) Receive Next Pointer */
+#define DACC_RNPR_RXNPTR(value) ((DACC_RNPR_RXNPTR_Msk & ((value) << DACC_RNPR_RXNPTR_Pos)))
+/* -------- DACC_RNCR : (DACC Offset: 0x114) Receive Next Counter Register -------- */
+#define DACC_RNCR_RXNCTR_Pos 0
+#define DACC_RNCR_RXNCTR_Msk (0xffffu << DACC_RNCR_RXNCTR_Pos) /**< \brief (DACC_RNCR) Receive Next Counter */
+#define DACC_RNCR_RXNCTR(value) ((DACC_RNCR_RXNCTR_Msk & ((value) << DACC_RNCR_RXNCTR_Pos)))
+/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */
+#define DACC_TNPR_TXNPTR_Pos 0
+#define DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos) /**< \brief (DACC_TNPR) Transmit Next Pointer */
+#define DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos)))
+/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */
+#define DACC_TNCR_TXNCTR_Pos 0
+#define DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos) /**< \brief (DACC_TNCR) Transmit Counter Next */
+#define DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos)))
+/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */
+#define DACC_PTCR_RXTEN (0x1u << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */
+#define DACC_PTCR_RXTDIS (0x1u << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */
+#define DACC_PTCR_TXTEN (0x1u << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */
+#define DACC_PTCR_TXTDIS (0x1u << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */
+/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */
+#define DACC_PTSR_RXTEN (0x1u << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */
+#define DACC_PTSR_TXTEN (0x1u << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3N_DACC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_efc.h b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_efc.h
new file mode 100644
index 000000000..113eedb40
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_efc.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_EFC_COMPONENT_
+#define _SAM3N_EFC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Embedded Flash Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3N_EFC Embedded Flash Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Efc hardware registers */
+typedef struct {
+  RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */
+  WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */
+  RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */
+  RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */
+} Efc;
+#endif /* __ASSEMBLY__ */
+/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
+#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */
+#define EEFC_FMR_FWS_Pos 8
+#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */
+#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))
+#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */
+#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */
+/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
+#define EEFC_FCR_FCMD_Pos 0
+#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */
+#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))
+#define EEFC_FCR_FARG_Pos 8
+#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */
+#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))
+#define EEFC_FCR_FKEY_Pos 24
+#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */
+#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)))
+/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
+#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */
+#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */
+#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */
+/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
+#define EEFC_FRR_FVALUE_Pos 0
+#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */
+
+/*@}*/
+
+
+#endif /* _SAM3N_EFC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_gpbr.h b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_gpbr.h
new file mode 100644
index 000000000..5e72e4029
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_gpbr.h
@@ -0,0 +1,53 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_GPBR_COMPONENT_
+#define _SAM3N_GPBR_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR General Purpose Backup Register */
+/* ============================================================================= */
+/** \addtogroup SAM3N_GPBR General Purpose Backup Register */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Gpbr hardware registers */
+typedef struct {
+  RwReg SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */
+} Gpbr;
+#endif /* __ASSEMBLY__ */
+/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */
+#define SYS_GPBR_GPBR_VALUE_Pos 0
+#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */
+#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3N_GPBR_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_matrix.h b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_matrix.h
new file mode 100644
index 000000000..af565e258
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_matrix.h
@@ -0,0 +1,149 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_MATRIX_COMPONENT_
+#define _SAM3N_MATRIX_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR AHB Bus Matrix */
+/* ============================================================================= */
+/** \addtogroup SAM3N_MATRIX AHB Bus Matrix */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Matrix hardware registers */
+typedef struct {
+  RwReg MATRIX_MCFG[3]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */
+  RoReg Reserved1[13];
+  RwReg MATRIX_SCFG[4]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */
+  RoReg Reserved2[12];
+  RwReg MATRIX_PRAS0;   /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */
+  RoReg Reserved3[1];
+  RwReg MATRIX_PRAS1;   /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */
+  RoReg Reserved4[1];
+  RwReg MATRIX_PRAS2;   /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */
+  RoReg Reserved5[1];
+  RwReg MATRIX_PRAS3;   /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */
+  RoReg Reserved6[1];
+  RoReg Reserved7[29];
+  RwReg CCFG_SYSIO;     /**< \brief (Matrix Offset: 0x0114) System I/O Configuration register */
+  RoReg Reserved8[51];
+  RwReg MATRIX_WPMR;    /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */
+  RoReg MATRIX_WPSR;    /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */
+} Matrix;
+#endif /* __ASSEMBLY__ */
+/* -------- MATRIX_MCFG[3] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */
+#define MATRIX_MCFG_ULBT_Pos 0
+#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[3]) Undefined Length Burst Type */
+#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))
+/* -------- MATRIX_SCFG[4] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
+#define MATRIX_SCFG_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[4]) Maximum Number of Allowed Cycles for a Burst */
+#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[4]) Default Master Type */
+#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
+#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[4]) Fixed Default Master */
+#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
+#define MATRIX_SCFG_ARBT_Pos 24
+#define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[4]) Arbitration Type */
+#define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos)))
+/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */
+#define MATRIX_PRAS0_M0PR_Pos 0
+#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */
+#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))
+#define MATRIX_PRAS0_M1PR_Pos 4
+#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */
+#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))
+#define MATRIX_PRAS0_M2PR_Pos 8
+#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */
+#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))
+#define MATRIX_PRAS0_M3PR_Pos 12
+#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */
+#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))
+/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */
+#define MATRIX_PRAS1_M0PR_Pos 0
+#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */
+#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))
+#define MATRIX_PRAS1_M1PR_Pos 4
+#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */
+#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))
+#define MATRIX_PRAS1_M2PR_Pos 8
+#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */
+#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))
+#define MATRIX_PRAS1_M3PR_Pos 12
+#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */
+#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))
+/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */
+#define MATRIX_PRAS2_M0PR_Pos 0
+#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */
+#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))
+#define MATRIX_PRAS2_M1PR_Pos 4
+#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */
+#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))
+#define MATRIX_PRAS2_M2PR_Pos 8
+#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */
+#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))
+#define MATRIX_PRAS2_M3PR_Pos 12
+#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */
+#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))
+/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */
+#define MATRIX_PRAS3_M0PR_Pos 0
+#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */
+#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))
+#define MATRIX_PRAS3_M1PR_Pos 4
+#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */
+#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))
+#define MATRIX_PRAS3_M2PR_Pos 8
+#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */
+#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))
+#define MATRIX_PRAS3_M3PR_Pos 12
+#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */
+#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))
+/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration register -------- */
+#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */
+#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */
+#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */
+#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */
+#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */
+/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */
+#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */
+#define MATRIX_WPMR_WPKEY_Pos 8
+#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */
+#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
+/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */
+#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */
+#define MATRIX_WPSR_WPVSRC_Pos 8
+#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3N_MATRIX_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_pdc.h b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_pdc.h
new file mode 100644
index 000000000..6034cf850
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_pdc.h
@@ -0,0 +1,98 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_PDC_COMPONENT_
+#define _SAM3N_PDC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3N_PDC Peripheral DMA Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Pdc hardware registers */
+typedef struct {
+  RwReg PERIPH_RPR;  /**< \brief (Pdc Offset: 0x0) Receive Pointer Register */
+  RwReg PERIPH_RCR;  /**< \brief (Pdc Offset: 0x4) Receive Counter Register */
+  RwReg PERIPH_TPR;  /**< \brief (Pdc Offset: 0x8) Transmit Pointer Register */
+  RwReg PERIPH_TCR;  /**< \brief (Pdc Offset: 0xC) Transmit Counter Register */
+  RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */
+  RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */
+  RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */
+  RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */
+  WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */
+  RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */
+} Pdc;
+#endif /* __ASSEMBLY__ */
+/* -------- PERIPH_RPR : (PDC Offset: 0x0) Receive Pointer Register -------- */
+#define PERIPH_RPR_RXPTR_Pos 0
+#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */
+#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos)))
+/* -------- PERIPH_RCR : (PDC Offset: 0x4) Receive Counter Register -------- */
+#define PERIPH_RCR_RXCTR_Pos 0
+#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */
+#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos)))
+/* -------- PERIPH_TPR : (PDC Offset: 0x8) Transmit Pointer Register -------- */
+#define PERIPH_TPR_TXPTR_Pos 0
+#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */
+#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos)))
+/* -------- PERIPH_TCR : (PDC Offset: 0xC) Transmit Counter Register -------- */
+#define PERIPH_TCR_TXCTR_Pos 0
+#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */
+#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos)))
+/* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */
+#define PERIPH_RNPR_RXNPTR_Pos 0
+#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */
+#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos)))
+/* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */
+#define PERIPH_RNCR_RXNCTR_Pos 0
+#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */
+#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos)))
+/* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */
+#define PERIPH_TNPR_TXNPTR_Pos 0
+#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */
+#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos)))
+/* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */
+#define PERIPH_TNCR_TXNCTR_Pos 0
+#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */
+#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos)))
+/* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */
+#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */
+#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */
+#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */
+#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */
+/* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */
+#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */
+#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3N_PDC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_pio.h b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_pio.h
new file mode 100644
index 000000000..e83076a7a
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_pio.h
@@ -0,0 +1,1572 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_PIO_COMPONENT_
+#define _SAM3N_PIO_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3N_PIO Parallel Input/Output Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Pio hardware registers */
+typedef struct {
+  WoReg PIO_PER;       /**< \brief (Pio Offset: 0x0000) PIO Enable Register */
+  WoReg PIO_PDR;       /**< \brief (Pio Offset: 0x0004) PIO Disable Register */
+  RoReg PIO_PSR;       /**< \brief (Pio Offset: 0x0008) PIO Status Register */
+  RoReg Reserved1[1];
+  WoReg PIO_OER;       /**< \brief (Pio Offset: 0x0010) Output Enable Register */
+  WoReg PIO_ODR;       /**< \brief (Pio Offset: 0x0014) Output Disable Register */
+  RoReg PIO_OSR;       /**< \brief (Pio Offset: 0x0018) Output Status Register */
+  RoReg Reserved2[1];
+  WoReg PIO_IFER;      /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */
+  WoReg PIO_IFDR;      /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */
+  RoReg PIO_IFSR;      /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */
+  RoReg Reserved3[1];
+  WoReg PIO_SODR;      /**< \brief (Pio Offset: 0x0030) Set Output Data Register */
+  WoReg PIO_CODR;      /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */
+  RwReg PIO_ODSR;      /**< \brief (Pio Offset: 0x0038) Output Data Status Register */
+  RoReg PIO_PDSR;      /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */
+  WoReg PIO_IER;       /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */
+  WoReg PIO_IDR;       /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */
+  RoReg PIO_IMR;       /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */
+  RoReg PIO_ISR;       /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */
+  WoReg PIO_MDER;      /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */
+  WoReg PIO_MDDR;      /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */
+  RoReg PIO_MDSR;      /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */
+  RoReg Reserved4[1];
+  WoReg PIO_PUDR;      /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */
+  WoReg PIO_PUER;      /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */
+  RoReg PIO_PUSR;      /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */
+  RoReg Reserved5[1];
+  RwReg PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */
+  RoReg Reserved6[2];
+  WoReg PIO_IFSCDR;    /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */
+  WoReg PIO_IFSCER;    /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */
+  RoReg PIO_IFSCSR;    /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */
+  RwReg PIO_SCDR;      /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */
+  WoReg PIO_PPDDR;     /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */
+  WoReg PIO_PPDER;     /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */
+  RoReg PIO_PPDSR;     /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */
+  RoReg Reserved7[1];
+  WoReg PIO_OWER;      /**< \brief (Pio Offset: 0x00A0) Output Write Enable */
+  WoReg PIO_OWDR;      /**< \brief (Pio Offset: 0x00A4) Output Write Disable */
+  RoReg PIO_OWSR;      /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */
+  RoReg Reserved8[1];
+  WoReg PIO_AIMER;     /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */
+  WoReg PIO_AIMDR;     /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */
+  RoReg PIO_AIMMR;     /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */
+  RoReg Reserved9[1];
+  WoReg PIO_ESR;       /**< \brief (Pio Offset: 0x00C0) Edge Select Register */
+  WoReg PIO_LSR;       /**< \brief (Pio Offset: 0x00C4) Level Select Register */
+  RoReg PIO_ELSR;      /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */
+  RoReg Reserved10[1];
+  WoReg PIO_FELLSR;    /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */
+  WoReg PIO_REHLSR;    /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */
+  RoReg PIO_FRLHSR;    /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */
+  RoReg Reserved11[1];
+  RoReg PIO_LOCKSR;    /**< \brief (Pio Offset: 0x00E0) Lock Status */
+  RwReg PIO_WPMR;      /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */
+  RoReg PIO_WPSR;      /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */
+  RoReg Reserved12[5];
+  RwReg PIO_SCHMITT;   /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */
+} Pio;
+#endif /* __ASSEMBLY__ */
+/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */
+#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */
+/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */
+#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */
+/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */
+#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */
+/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */
+#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */
+/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */
+#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */
+/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */
+#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */
+/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */
+#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */
+/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */
+#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */
+/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */
+#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */
+/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */
+#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */
+/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */
+#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */
+/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */
+#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */
+/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */
+#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */
+/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */
+#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */
+#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */
+#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */
+#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */
+#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */
+/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */
+#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */
+#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */
+/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */
+#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */
+/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */
+#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull Up Enable. */
+/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */
+#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull Up Status. */
+/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */
+#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */
+#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */
+#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */
+#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */
+#define PIO_SCDR_DIV_Pos 0
+#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR)  */
+#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)))
+/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */
+#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */
+#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */
+/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */
+#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */
+/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */
+#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable. */
+/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */
+#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable. */
+/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */
+#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status. */
+/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */
+#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */
+#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */
+#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */
+#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */
+#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */
+#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */
+#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */
+#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */
+#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */
+#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status. */
+/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protect Enable */
+#define PIO_WPMR_WPKEY_Pos 8
+#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protect KEY */
+#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)))
+/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */
+#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */
+#define PIO_WPSR_WPVSRC_Pos 8
+#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protect Violation Source */
+/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */
+#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT)  */
+
+/*@}*/
+
+
+#endif /* _SAM3N_PIO_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_pmc.h b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_pmc.h
new file mode 100644
index 000000000..723107e76
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_pmc.h
@@ -0,0 +1,324 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_PMC_COMPONENT_
+#define _SAM3N_PMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Power Management Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3N_PMC Power Management Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Pmc hardware registers */
+typedef struct {
+  WoReg PMC_SCER;      /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */
+  WoReg PMC_SCDR;      /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */
+  RoReg PMC_SCSR;      /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */
+  RoReg Reserved1[1];
+  WoReg PMC_PCER0;     /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */
+  WoReg PMC_PCDR0;     /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */
+  RoReg PMC_PCSR0;     /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */
+  RoReg Reserved2[1];
+  RwReg CKGR_MOR;      /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */
+  RoReg CKGR_MCFR;     /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */
+  RwReg CKGR_PLLAR;    /**< \brief (Pmc Offset: 0x0028) PLLA Register */
+  RoReg Reserved3[1];
+  RwReg PMC_MCKR;      /**< \brief (Pmc Offset: 0x0030) Master Clock Register */
+  RoReg Reserved4[3];
+  RwReg PMC_PCK[3];    /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */
+  RoReg Reserved5[5];
+  WoReg PMC_IER;       /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */
+  WoReg PMC_IDR;       /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */
+  RoReg PMC_SR;        /**< \brief (Pmc Offset: 0x0068) Status Register */
+  RoReg PMC_IMR;       /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */
+  RwReg PMC_FSMR;      /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */
+  RwReg PMC_FSPR;      /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */
+  WoReg PMC_FOCR;      /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */
+  RoReg Reserved6[26];
+  RwReg PMC_WPMR;      /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */
+  RoReg PMC_WPSR;      /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */
+} Pmc;
+#endif /* __ASSEMBLY__ */
+/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
+#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */
+#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */
+#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */
+/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
+#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */
+#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */
+#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */
+/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
+#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */
+#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */
+#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */
+/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
+#define PMC_PCER0_PID2 (0x1u << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */
+#define PMC_PCER0_PID3 (0x1u << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */
+#define PMC_PCER0_PID4 (0x1u << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */
+#define PMC_PCER0_PID5 (0x1u << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */
+#define PMC_PCER0_PID6 (0x1u << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */
+#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */
+#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */
+#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */
+#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */
+#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */
+#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */
+#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */
+#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */
+#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */
+#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */
+#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */
+#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */
+#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */
+#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */
+#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */
+#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */
+#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */
+#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */
+#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */
+#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */
+#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */
+/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
+#define PMC_PCDR0_PID2 (0x1u << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */
+#define PMC_PCDR0_PID3 (0x1u << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */
+#define PMC_PCDR0_PID4 (0x1u << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */
+#define PMC_PCDR0_PID5 (0x1u << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */
+#define PMC_PCDR0_PID6 (0x1u << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */
+#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */
+#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */
+#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */
+#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */
+#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */
+#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */
+#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */
+#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */
+#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */
+#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */
+#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */
+#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */
+#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */
+#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */
+#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */
+#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */
+#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */
+#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */
+#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */
+#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */
+#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */
+/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
+#define PMC_PCSR0_PID2 (0x1u << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */
+#define PMC_PCSR0_PID3 (0x1u << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */
+#define PMC_PCSR0_PID4 (0x1u << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */
+#define PMC_PCSR0_PID5 (0x1u << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */
+#define PMC_PCSR0_PID6 (0x1u << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */
+#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */
+#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */
+#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */
+#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */
+#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */
+#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */
+#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */
+#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */
+#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */
+#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */
+#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */
+#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */
+#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */
+#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */
+#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */
+#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */
+#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */
+#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */
+#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */
+#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */
+#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */
+/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
+#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */
+#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */
+#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */
+#define CKGR_MOR_MOSCRCF_Pos 4
+#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */
+#define   CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default) */
+#define   CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz */
+#define   CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz */
+#define CKGR_MOR_MOSCXTST_Pos 8
+#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */
+#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
+#define CKGR_MOR_KEY_Pos 16
+#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */
+#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
+#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */
+#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */
+/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
+#define CKGR_MCFR_MAINF_Pos 0
+#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */
+#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */
+/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
+#define CKGR_PLLAR_DIVA_Pos 0
+#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider */
+#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
+#define CKGR_PLLAR_PLLACOUNT_Pos 8
+#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */
+#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
+#define CKGR_PLLAR_MULA_Pos 16
+#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */
+#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
+#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */
+/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
+#define PMC_MCKR_CSS_Pos 0
+#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */
+#define   PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */
+#define   PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */
+#define   PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */
+#define PMC_MCKR_PRES_Pos 4
+#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */
+#define   PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */
+#define   PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */
+#define   PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */
+#define   PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */
+#define   PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */
+#define   PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */
+#define   PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */
+#define   PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */
+#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */
+/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
+#define PMC_PCK_CSS_Pos 0
+#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */
+#define   PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */
+#define   PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */
+#define   PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */
+#define   PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */
+#define PMC_PCK_PRES_Pos 4
+#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */
+#define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos)))
+#define   PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */
+#define   PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */
+#define   PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */
+#define   PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */
+#define   PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */
+#define   PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */
+#define   PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */
+/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
+#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */
+#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */
+#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */
+#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */
+#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */
+#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */
+#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */
+#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */
+#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */
+/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
+#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */
+#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */
+#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */
+#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */
+#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */
+#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */
+#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */
+#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */
+#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */
+/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
+#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */
+#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */
+#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */
+#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */
+#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */
+#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */
+#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */
+#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */
+#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */
+/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
+#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */
+#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */
+#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */
+#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */
+#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */
+#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */
+#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */
+#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */
+#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */
+/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
+#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */
+#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */
+#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */
+#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */
+#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */
+#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */
+#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */
+#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */
+#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */
+#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */
+#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */
+#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */
+#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */
+#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */
+#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */
+#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */
+#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */
+#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */
+#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low Power Mode */
+/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
+#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
+#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */
+/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */
+#define PMC_WPMR_WPKEY_Pos 8
+#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */
+#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
+/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */
+#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */
+#define PMC_WPSR_WPVSRC_Pos 8
+#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3N_PMC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_pwm.h b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_pwm.h
new file mode 100644
index 000000000..fb81edc12
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_pwm.h
@@ -0,0 +1,172 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_PWM_COMPONENT_
+#define _SAM3N_PWM_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3N_PWM Pulse Width Modulation Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief PwmCh_num hardware registers */
+typedef struct {
+  RwReg      PWM_CMR;        /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */
+  RwReg      PWM_CDTY;       /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */
+  RwReg      PWM_CPRD;       /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Period Register */
+  RwReg      PWM_CCNT;       /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Counter Register */
+  RwReg      PWM_CUPD;       /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Update Register */
+  RoReg      Reserved1[3];
+} PwmCh_num;
+/** \brief Pwm hardware registers */
+#define PWMCH_NUM_NUMBER 4
+typedef struct {
+  RwReg      PWM_MR;         /**< \brief (Pwm Offset: 0x00) PWM Mode Register */
+  WoReg      PWM_ENA;        /**< \brief (Pwm Offset: 0x04) PWM Enable Register */
+  WoReg      PWM_DIS;        /**< \brief (Pwm Offset: 0x08) PWM Disable Register */
+  RoReg      PWM_SR;         /**< \brief (Pwm Offset: 0x0C) PWM Status Register */
+  WoReg      PWM_IER;        /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register */
+  WoReg      PWM_IDR;        /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register */
+  RoReg      PWM_IMR;        /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register */
+  RoReg      PWM_ISR;        /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register */
+  RoReg      Reserved1[120];
+  PwmCh_num  PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */
+} Pwm;
+#endif /* __ASSEMBLY__ */
+/* -------- PWM_MR : (PWM Offset: 0x00) PWM Mode Register -------- */
+#define PWM_MR_DIVA_Pos 0
+#define PWM_MR_DIVA_Msk (0xffu << PWM_MR_DIVA_Pos) /**< \brief (PWM_MR) CLKA, CLKB Divide Factor */
+#define   PWM_MR_DIVA_CLK_OFF (0x0u << 0) /**< \brief (PWM_MR) CLKA, CLKB clock is turned off */
+#define   PWM_MR_DIVA_CLK_DIV1 (0x1u << 0) /**< \brief (PWM_MR) CLKA, CLKB clock is clock selected by PREA, PREB */
+#define PWM_MR_PREA_Pos 8
+#define PWM_MR_PREA_Msk (0xfu << PWM_MR_PREA_Pos) /**< \brief (PWM_MR)  */
+#define   PWM_MR_PREA_MCK (0x0u << 8) /**< \brief (PWM_MR) Master Clock */
+#define   PWM_MR_PREA_MCKDIV2 (0x1u << 8) /**< \brief (PWM_MR) Master Clock divided by 2 */
+#define   PWM_MR_PREA_MCKDIV4 (0x2u << 8) /**< \brief (PWM_MR) Master Clock divided by 4 */
+#define   PWM_MR_PREA_MCKDIV8 (0x3u << 8) /**< \brief (PWM_MR) Master Clock divided by 8 */
+#define   PWM_MR_PREA_MCKDIV16 (0x4u << 8) /**< \brief (PWM_MR) Master Clock divided by 16 */
+#define   PWM_MR_PREA_MCKDIV32 (0x5u << 8) /**< \brief (PWM_MR) Master Clock divided by 32 */
+#define   PWM_MR_PREA_MCKDIV64 (0x6u << 8) /**< \brief (PWM_MR) Master Clock divided by 64 */
+#define   PWM_MR_PREA_MCKDIV128 (0x7u << 8) /**< \brief (PWM_MR) Master Clock divided by 128 */
+#define   PWM_MR_PREA_MCKDIV256 (0x8u << 8) /**< \brief (PWM_MR) Master Clock divided by 256 */
+#define   PWM_MR_PREA_MCKDIV512 (0x9u << 8) /**< \brief (PWM_MR) Master Clock divided by 512 */
+#define   PWM_MR_PREA_MCKDIV1024 (0xAu << 8) /**< \brief (PWM_MR) Master Clock divided by 1024 */
+#define PWM_MR_DIVB_Pos 16
+#define PWM_MR_DIVB_Msk (0xffu << PWM_MR_DIVB_Pos) /**< \brief (PWM_MR) CLKA, CLKB Divide Factor */
+#define   PWM_MR_DIVB_CLK_OFF (0x0u << 16) /**< \brief (PWM_MR) CLKA, CLKB clock is turned off */
+#define   PWM_MR_DIVB_CLK_DIV1 (0x1u << 16) /**< \brief (PWM_MR) CLKA, CLKB clock is clock selected by PREA, PREB */
+#define PWM_MR_PREB_Pos 24
+#define PWM_MR_PREB_Msk (0xfu << PWM_MR_PREB_Pos) /**< \brief (PWM_MR)  */
+#define   PWM_MR_PREB_MCK (0x0u << 24) /**< \brief (PWM_MR) Master Clock */
+#define   PWM_MR_PREB_MCKDIV2 (0x1u << 24) /**< \brief (PWM_MR) Master Clock divided by 2 */
+#define   PWM_MR_PREB_MCKDIV4 (0x2u << 24) /**< \brief (PWM_MR) Master Clock divided by 4 */
+#define   PWM_MR_PREB_MCKDIV8 (0x3u << 24) /**< \brief (PWM_MR) Master Clock divided by 8 */
+#define   PWM_MR_PREB_MCKDIV16 (0x4u << 24) /**< \brief (PWM_MR) Master Clock divided by 16 */
+#define   PWM_MR_PREB_MCKDIV32 (0x5u << 24) /**< \brief (PWM_MR) Master Clock divided by 32 */
+#define   PWM_MR_PREB_MCKDIV64 (0x6u << 24) /**< \brief (PWM_MR) Master Clock divided by 64 */
+#define   PWM_MR_PREB_MCKDIV128 (0x7u << 24) /**< \brief (PWM_MR) Master Clock divided by 128 */
+#define   PWM_MR_PREB_MCKDIV256 (0x8u << 24) /**< \brief (PWM_MR) Master Clock divided by 256 */
+#define   PWM_MR_PREB_MCKDIV512 (0x9u << 24) /**< \brief (PWM_MR) Master Clock divided by 512 */
+#define   PWM_MR_PREB_MCKDIV1024 (0xAu << 24) /**< \brief (PWM_MR) Master Clock divided by 1024 */
+/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
+#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */
+/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
+#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */
+/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
+#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */
+/* -------- PWM_IER : (PWM Offset: 0x10) PWM Interrupt Enable Register -------- */
+#define PWM_IER_CHID0 (0x1u << 0) /**< \brief (PWM_IER) Channel ID. */
+#define PWM_IER_CHID1 (0x1u << 1) /**< \brief (PWM_IER) Channel ID. */
+#define PWM_IER_CHID2 (0x1u << 2) /**< \brief (PWM_IER) Channel ID. */
+#define PWM_IER_CHID3 (0x1u << 3) /**< \brief (PWM_IER) Channel ID. */
+/* -------- PWM_IDR : (PWM Offset: 0x14) PWM Interrupt Disable Register -------- */
+#define PWM_IDR_CHID0 (0x1u << 0) /**< \brief (PWM_IDR) Channel ID. */
+#define PWM_IDR_CHID1 (0x1u << 1) /**< \brief (PWM_IDR) Channel ID. */
+#define PWM_IDR_CHID2 (0x1u << 2) /**< \brief (PWM_IDR) Channel ID. */
+#define PWM_IDR_CHID3 (0x1u << 3) /**< \brief (PWM_IDR) Channel ID. */
+/* -------- PWM_IMR : (PWM Offset: 0x18) PWM Interrupt Mask Register -------- */
+#define PWM_IMR_CHID0 (0x1u << 0) /**< \brief (PWM_IMR) Channel ID. */
+#define PWM_IMR_CHID1 (0x1u << 1) /**< \brief (PWM_IMR) Channel ID. */
+#define PWM_IMR_CHID2 (0x1u << 2) /**< \brief (PWM_IMR) Channel ID. */
+#define PWM_IMR_CHID3 (0x1u << 3) /**< \brief (PWM_IMR) Channel ID. */
+/* -------- PWM_ISR : (PWM Offset: 0x1C) PWM Interrupt Status Register -------- */
+#define PWM_ISR_CHID0 (0x1u << 0) /**< \brief (PWM_ISR) Channel ID */
+#define PWM_ISR_CHID1 (0x1u << 1) /**< \brief (PWM_ISR) Channel ID */
+#define PWM_ISR_CHID2 (0x1u << 2) /**< \brief (PWM_ISR) Channel ID */
+#define PWM_ISR_CHID3 (0x1u << 3) /**< \brief (PWM_ISR) Channel ID */
+/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */
+#define PWM_CMR_CPRE_Pos 0
+#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */
+#define   PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master Clock */
+#define   PWM_CMR_CPRE_MCKDIV2 (0x1u << 0) /**< \brief (PWM_CMR) Master Clock divided by 2 */
+#define   PWM_CMR_CPRE_MCKDIV4 (0x2u << 0) /**< \brief (PWM_CMR) Master Clock divided by 4 */
+#define   PWM_CMR_CPRE_MCKDIV8 (0x3u << 0) /**< \brief (PWM_CMR) Master Clock divided by 8 */
+#define   PWM_CMR_CPRE_MCKDIV16 (0x4u << 0) /**< \brief (PWM_CMR) Master Clock divided by 16 */
+#define   PWM_CMR_CPRE_MCKDIV32 (0x5u << 0) /**< \brief (PWM_CMR) Master Clock divided by 32 */
+#define   PWM_CMR_CPRE_MCKDIV64 (0x6u << 0) /**< \brief (PWM_CMR) Master Clock divided by 64 */
+#define   PWM_CMR_CPRE_MCKDIV128 (0x7u << 0) /**< \brief (PWM_CMR) Master Clock divided by 128 */
+#define   PWM_CMR_CPRE_MCKDIV256 (0x8u << 0) /**< \brief (PWM_CMR) Master Clock divided by 256 */
+#define   PWM_CMR_CPRE_MCKDIV512 (0x9u << 0) /**< \brief (PWM_CMR) Master Clock divided by 512 */
+#define   PWM_CMR_CPRE_MCKDIV1024 (0xAu << 0) /**< \brief (PWM_CMR) Master Clock divided by 1024 */
+#define   PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */
+#define   PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */
+#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */
+#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */
+#define PWM_CMR_CPD (0x1u << 10) /**< \brief (PWM_CMR) Channel Update Period */
+/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */
+#define PWM_CDTY_CDTY_Pos 0
+#define PWM_CDTY_CDTY_Msk (0xffffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty Cycle */
+#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))
+/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */
+#define PWM_CPRD_CPRD_Pos 0
+#define PWM_CPRD_CPRD_Msk (0xffffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */
+#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))
+/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */
+#define PWM_CCNT_CNT_Pos 0
+#define PWM_CCNT_CNT_Msk (0xffffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */
+/* -------- PWM_CUPD : (PWM Offset: N/A) PWM Channel Update Register -------- */
+#define PWM_CUPD_CUPD_Pos 0
+#define PWM_CUPD_CUPD_Msk (0xffffffffu << PWM_CUPD_CUPD_Pos) /**< \brief (PWM_CUPD)  */
+#define PWM_CUPD_CUPD(value) ((PWM_CUPD_CUPD_Msk & ((value) << PWM_CUPD_CUPD_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3N_PWM_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_rstc.h b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_rstc.h
new file mode 100644
index 000000000..1ef3fd5ff
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_rstc.h
@@ -0,0 +1,73 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_RSTC_COMPONENT_
+#define _SAM3N_RSTC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Reset Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3N_RSTC Reset Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Rstc hardware registers */
+typedef struct {
+  WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
+  RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
+  RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
+} Rstc;
+#endif /* __ASSEMBLY__ */
+/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
+#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */
+#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */
+#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */
+#define RSTC_CR_KEY_Pos 24
+#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Password */
+#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
+/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
+#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */
+#define RSTC_SR_RSTTYP_Pos 8
+#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */
+#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
+#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
+/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
+#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */
+#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
+#define RSTC_MR_ERSTL_Pos 8
+#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */
+#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
+#define RSTC_MR_KEY_Pos 24
+#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */
+#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3N_RSTC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_rtc.h b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_rtc.h
new file mode 100644
index 000000000..8077c401c
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_rtc.h
@@ -0,0 +1,168 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_RTC_COMPONENT_
+#define _SAM3N_RTC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Real-time Clock */
+/* ============================================================================= */
+/** \addtogroup SAM3N_RTC Real-time Clock */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Rtc hardware registers */
+typedef struct {
+  RwReg RTC_CR;        /**< \brief (Rtc Offset: 0x00) Control Register */
+  RwReg RTC_MR;        /**< \brief (Rtc Offset: 0x04) Mode Register */
+  RwReg RTC_TIMR;      /**< \brief (Rtc Offset: 0x08) Time Register */
+  RwReg RTC_CALR;      /**< \brief (Rtc Offset: 0x0C) Calendar Register */
+  RwReg RTC_TIMALR;    /**< \brief (Rtc Offset: 0x10) Time Alarm Register */
+  RwReg RTC_CALALR;    /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */
+  RoReg RTC_SR;        /**< \brief (Rtc Offset: 0x18) Status Register */
+  WoReg RTC_SCCR;      /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */
+  WoReg RTC_IER;       /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */
+  WoReg RTC_IDR;       /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */
+  RoReg RTC_IMR;       /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */
+  RoReg RTC_VER;       /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */
+  RoReg Reserved1[45];
+  RwReg RTC_WPMR;      /**< \brief (Rtc Offset: 0xE4) Write Protect Mode Register */
+} Rtc;
+#endif /* __ASSEMBLY__ */
+/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
+#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */
+#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */
+#define RTC_CR_TIMEVSEL_Pos 8
+#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */
+#define   RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */
+#define   RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */
+#define   RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */
+#define   RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */
+#define RTC_CR_CALEVSEL_Pos 16
+#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */
+#define   RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */
+#define   RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */
+#define   RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */
+/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
+#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */
+/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
+#define RTC_TIMR_SEC_Pos 0
+#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */
+#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
+#define RTC_TIMR_MIN_Pos 8
+#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */
+#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
+#define RTC_TIMR_HOUR_Pos 16
+#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */
+#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
+#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */
+/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
+#define RTC_CALR_CENT_Pos 0
+#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */
+#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
+#define RTC_CALR_YEAR_Pos 8
+#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */
+#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
+#define RTC_CALR_MONTH_Pos 16
+#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */
+#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
+#define RTC_CALR_DAY_Pos 21
+#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */
+#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
+#define RTC_CALR_DATE_Pos 24
+#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */
+#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
+/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
+#define RTC_TIMALR_SEC_Pos 0
+#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */
+#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
+#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */
+#define RTC_TIMALR_MIN_Pos 8
+#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */
+#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
+#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */
+#define RTC_TIMALR_HOUR_Pos 16
+#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */
+#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
+#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */
+#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */
+/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
+#define RTC_CALALR_MONTH_Pos 16
+#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */
+#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
+#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */
+#define RTC_CALALR_DATE_Pos 24
+#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */
+#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
+#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */
+/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
+#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */
+#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */
+#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */
+#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */
+#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */
+/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
+#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */
+#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */
+#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */
+#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */
+#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */
+/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
+#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */
+#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */
+#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */
+#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */
+#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */
+/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
+#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */
+#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */
+#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */
+#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */
+#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */
+/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
+#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */
+#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */
+#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */
+#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */
+#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */
+/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
+#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */
+#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */
+#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */
+#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */
+/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protect Mode Register -------- */
+#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protect Enable */
+#define RTC_WPMR_WPKEY_Pos 8
+#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR)  */
+#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3N_RTC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_rtt.h b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_rtt.h
new file mode 100644
index 000000000..17d2ac764
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_rtt.h
@@ -0,0 +1,69 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_RTT_COMPONENT_
+#define _SAM3N_RTT_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Real-time Timer */
+/* ============================================================================= */
+/** \addtogroup SAM3N_RTT Real-time Timer */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Rtt hardware registers */
+typedef struct {
+  RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */
+  RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */
+  RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */
+  RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */
+} Rtt;
+#endif /* __ASSEMBLY__ */
+/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */
+#define RTT_MR_RTPRES_Pos 0
+#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */
+#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)))
+#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */
+#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */
+#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */
+/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */
+#define RTT_AR_ALMV_Pos 0
+#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */
+#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)))
+/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */
+#define RTT_VR_CRTV_Pos 0
+#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */
+/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */
+#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */
+#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */
+
+/*@}*/
+
+
+#endif /* _SAM3N_RTT_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_spi.h b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_spi.h
new file mode 100644
index 000000000..a3a3f0253
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_spi.h
@@ -0,0 +1,227 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_SPI_COMPONENT_
+#define _SAM3N_SPI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Serial Peripheral Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3N_SPI Serial Peripheral Interface */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Spi hardware registers */
+typedef struct {
+  WoReg SPI_CR;        /**< \brief (Spi Offset: 0x00) Control Register */
+  RwReg SPI_MR;        /**< \brief (Spi Offset: 0x04) Mode Register */
+  RoReg SPI_RDR;       /**< \brief (Spi Offset: 0x08) Receive Data Register */
+  WoReg SPI_TDR;       /**< \brief (Spi Offset: 0x0C) Transmit Data Register */
+  RoReg SPI_SR;        /**< \brief (Spi Offset: 0x10) Status Register */
+  WoReg SPI_IER;       /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */
+  WoReg SPI_IDR;       /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */
+  RoReg SPI_IMR;       /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */
+  RoReg Reserved1[4];
+  RwReg SPI_CSR[4];    /**< \brief (Spi Offset: 0x30) Chip Select Register */
+  RoReg Reserved2[41];
+  RwReg SPI_WPMR;      /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */
+  RoReg SPI_WPSR;      /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */
+  RoReg Reserved3[5];
+  RwReg SPI_RPR;       /**< \brief (Spi Offset: 0x100) Receive Pointer Register */
+  RwReg SPI_RCR;       /**< \brief (Spi Offset: 0x104) Receive Counter Register */
+  RwReg SPI_TPR;       /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */
+  RwReg SPI_TCR;       /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */
+  RwReg SPI_RNPR;      /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */
+  RwReg SPI_RNCR;      /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */
+  RwReg SPI_TNPR;      /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */
+  RwReg SPI_TNCR;      /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */
+  WoReg SPI_PTCR;      /**< \brief (Spi Offset: 0x120) Transfer Control Register */
+  RoReg SPI_PTSR;      /**< \brief (Spi Offset: 0x124) Transfer Status Register */
+} Spi;
+#endif /* __ASSEMBLY__ */
+/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
+#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */
+#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */
+#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */
+#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */
+/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
+#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */
+#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */
+#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */
+#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */
+#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */
+#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */
+#define SPI_MR_PCS_Pos 16
+#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */
+#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
+#define SPI_MR_DLYBCS_Pos 24
+#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */
+#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
+/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
+#define SPI_RDR_RD_Pos 0
+#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */
+#define SPI_RDR_PCS_Pos 16
+#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */
+/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
+#define SPI_TDR_TD_Pos 0
+#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */
+#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
+#define SPI_TDR_PCS_Pos 16
+#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */
+#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
+#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
+#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */
+#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */
+#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */
+#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */
+#define SPI_SR_ENDRX (0x1u << 4) /**< \brief (SPI_SR) End of RX buffer */
+#define SPI_SR_ENDTX (0x1u << 5) /**< \brief (SPI_SR) End of TX buffer */
+#define SPI_SR_RXBUFF (0x1u << 6) /**< \brief (SPI_SR) RX Buffer Full */
+#define SPI_SR_TXBUFE (0x1u << 7) /**< \brief (SPI_SR) TX Buffer Empty */
+#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */
+#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */
+#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */
+#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
+#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */
+#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */
+#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */
+#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */
+#define SPI_IER_ENDRX (0x1u << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */
+#define SPI_IER_ENDTX (0x1u << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */
+#define SPI_IER_RXBUFF (0x1u << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */
+#define SPI_IER_TXBUFE (0x1u << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */
+#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */
+#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */
+#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */
+#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */
+#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */
+#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */
+#define SPI_IDR_ENDRX (0x1u << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */
+#define SPI_IDR_ENDTX (0x1u << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */
+#define SPI_IDR_RXBUFF (0x1u << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */
+#define SPI_IDR_TXBUFE (0x1u << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */
+#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */
+#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */
+#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */
+/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
+#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */
+#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */
+#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */
+#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */
+#define SPI_IMR_ENDRX (0x1u << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */
+#define SPI_IMR_ENDTX (0x1u << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */
+#define SPI_IMR_RXBUFF (0x1u << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */
+#define SPI_IMR_TXBUFE (0x1u << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */
+#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */
+#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */
+#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */
+/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
+#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */
+#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */
+#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_BITS_Pos 4
+#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */
+#define   SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */
+#define   SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */
+#define   SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */
+#define   SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */
+#define   SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */
+#define   SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */
+#define   SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */
+#define   SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */
+#define   SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */
+#define SPI_CSR_SCBR_Pos 8
+#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */
+#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
+#define SPI_CSR_DLYBS_Pos 16
+#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */
+#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
+#define SPI_CSR_DLYBCT_Pos 24
+#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */
+#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
+/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */
+#define SPI_WPMR_SPIWPEN (0x1u << 0) /**< \brief (SPI_WPMR) SPI Write Protection Enable */
+#define SPI_WPMR_SPIWPKEY_Pos 8
+#define SPI_WPMR_SPIWPKEY_Msk (0xffffffu << SPI_WPMR_SPIWPKEY_Pos) /**< \brief (SPI_WPMR) SPI Write Protection Key Password */
+#define SPI_WPMR_SPIWPKEY(value) ((SPI_WPMR_SPIWPKEY_Msk & ((value) << SPI_WPMR_SPIWPKEY_Pos)))
+/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
+#define SPI_WPSR_SPIWPVS_Pos 0
+#define SPI_WPSR_SPIWPVS_Msk (0x7u << SPI_WPSR_SPIWPVS_Pos) /**< \brief (SPI_WPSR) SPI Write Protection Violation Status */
+#define SPI_WPSR_SPIWPVSRC_Pos 8
+#define SPI_WPSR_SPIWPVSRC_Msk (0xffu << SPI_WPSR_SPIWPVSRC_Pos) /**< \brief (SPI_WPSR) SPI Write Protection Violation Source */
+/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */
+#define SPI_RPR_RXPTR_Pos 0
+#define SPI_RPR_RXPTR_Msk (0xffffffffu << SPI_RPR_RXPTR_Pos) /**< \brief (SPI_RPR) Receive Pointer Register */
+#define SPI_RPR_RXPTR(value) ((SPI_RPR_RXPTR_Msk & ((value) << SPI_RPR_RXPTR_Pos)))
+/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */
+#define SPI_RCR_RXCTR_Pos 0
+#define SPI_RCR_RXCTR_Msk (0xffffu << SPI_RCR_RXCTR_Pos) /**< \brief (SPI_RCR) Receive Counter Register */
+#define SPI_RCR_RXCTR(value) ((SPI_RCR_RXCTR_Msk & ((value) << SPI_RCR_RXCTR_Pos)))
+/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */
+#define SPI_TPR_TXPTR_Pos 0
+#define SPI_TPR_TXPTR_Msk (0xffffffffu << SPI_TPR_TXPTR_Pos) /**< \brief (SPI_TPR) Transmit Counter Register */
+#define SPI_TPR_TXPTR(value) ((SPI_TPR_TXPTR_Msk & ((value) << SPI_TPR_TXPTR_Pos)))
+/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */
+#define SPI_TCR_TXCTR_Pos 0
+#define SPI_TCR_TXCTR_Msk (0xffffu << SPI_TCR_TXCTR_Pos) /**< \brief (SPI_TCR) Transmit Counter Register */
+#define SPI_TCR_TXCTR(value) ((SPI_TCR_TXCTR_Msk & ((value) << SPI_TCR_TXCTR_Pos)))
+/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */
+#define SPI_RNPR_RXNPTR_Pos 0
+#define SPI_RNPR_RXNPTR_Msk (0xffffffffu << SPI_RNPR_RXNPTR_Pos) /**< \brief (SPI_RNPR) Receive Next Pointer */
+#define SPI_RNPR_RXNPTR(value) ((SPI_RNPR_RXNPTR_Msk & ((value) << SPI_RNPR_RXNPTR_Pos)))
+/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */
+#define SPI_RNCR_RXNCTR_Pos 0
+#define SPI_RNCR_RXNCTR_Msk (0xffffu << SPI_RNCR_RXNCTR_Pos) /**< \brief (SPI_RNCR) Receive Next Counter */
+#define SPI_RNCR_RXNCTR(value) ((SPI_RNCR_RXNCTR_Msk & ((value) << SPI_RNCR_RXNCTR_Pos)))
+/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define SPI_TNPR_TXNPTR_Pos 0
+#define SPI_TNPR_TXNPTR_Msk (0xffffffffu << SPI_TNPR_TXNPTR_Pos) /**< \brief (SPI_TNPR) Transmit Next Pointer */
+#define SPI_TNPR_TXNPTR(value) ((SPI_TNPR_TXNPTR_Msk & ((value) << SPI_TNPR_TXNPTR_Pos)))
+/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define SPI_TNCR_TXNCTR_Pos 0
+#define SPI_TNCR_TXNCTR_Msk (0xffffu << SPI_TNCR_TXNCTR_Pos) /**< \brief (SPI_TNCR) Transmit Counter Next */
+#define SPI_TNCR_TXNCTR(value) ((SPI_TNCR_TXNCTR_Msk & ((value) << SPI_TNCR_TXNCTR_Pos)))
+/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */
+#define SPI_PTCR_RXTEN (0x1u << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */
+#define SPI_PTCR_RXTDIS (0x1u << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */
+#define SPI_PTCR_TXTEN (0x1u << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */
+#define SPI_PTCR_TXTDIS (0x1u << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */
+/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */
+#define SPI_PTSR_RXTEN (0x1u << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */
+#define SPI_PTSR_TXTEN (0x1u << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3N_SPI_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_supc.h b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_supc.h
new file mode 100644
index 000000000..f264c05fa
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_supc.h
@@ -0,0 +1,297 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_SUPC_COMPONENT_
+#define _SAM3N_SUPC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Supply Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3N_SUPC Supply Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Supc hardware registers */
+typedef struct {
+  WoReg SUPC_CR;   /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */
+  RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */
+  RwReg SUPC_MR;   /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */
+  RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */
+  RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */
+  RoReg SUPC_SR;   /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */
+} Supc;
+#endif /* __ASSEMBLY__ */
+/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */
+#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */
+#define   SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */
+#define   SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */
+#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */
+#define   SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */
+#define   SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */
+#define SUPC_CR_KEY_Pos 24
+#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */
+#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))
+/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */
+#define SUPC_SMMR_SMTH_Pos 0
+#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */
+#define   SUPC_SMMR_SMTH_1_9V (0x0u << 0) /**< \brief (SUPC_SMMR) 1.9 V */
+#define   SUPC_SMMR_SMTH_2_0V (0x1u << 0) /**< \brief (SUPC_SMMR) 2.0 V */
+#define   SUPC_SMMR_SMTH_2_1V (0x2u << 0) /**< \brief (SUPC_SMMR) 2.1 V */
+#define   SUPC_SMMR_SMTH_2_2V (0x3u << 0) /**< \brief (SUPC_SMMR) 2.2 V */
+#define   SUPC_SMMR_SMTH_2_3V (0x4u << 0) /**< \brief (SUPC_SMMR) 2.3 V */
+#define   SUPC_SMMR_SMTH_2_4V (0x5u << 0) /**< \brief (SUPC_SMMR) 2.4 V */
+#define   SUPC_SMMR_SMTH_2_5V (0x6u << 0) /**< \brief (SUPC_SMMR) 2.5 V */
+#define   SUPC_SMMR_SMTH_2_6V (0x7u << 0) /**< \brief (SUPC_SMMR) 2.6 V */
+#define   SUPC_SMMR_SMTH_2_7V (0x8u << 0) /**< \brief (SUPC_SMMR) 2.7 V */
+#define   SUPC_SMMR_SMTH_2_8V (0x9u << 0) /**< \brief (SUPC_SMMR) 2.8 V */
+#define   SUPC_SMMR_SMTH_2_9V (0xAu << 0) /**< \brief (SUPC_SMMR) 2.9 V */
+#define   SUPC_SMMR_SMTH_3_0V (0xBu << 0) /**< \brief (SUPC_SMMR) 3.0 V */
+#define   SUPC_SMMR_SMTH_3_1V (0xCu << 0) /**< \brief (SUPC_SMMR) 3.1 V */
+#define   SUPC_SMMR_SMTH_3_2V (0xDu << 0) /**< \brief (SUPC_SMMR) 3.2 V */
+#define   SUPC_SMMR_SMTH_3_3V (0xEu << 0) /**< \brief (SUPC_SMMR) 3.3 V */
+#define   SUPC_SMMR_SMTH_3_4V (0xFu << 0) /**< \brief (SUPC_SMMR) 3.4 V */
+#define SUPC_SMMR_SMSMPL_Pos 8
+#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */
+#define   SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */
+#define   SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */
+#define   SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */
+#define   SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */
+#define   SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */
+#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */
+#define   SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */
+#define   SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */
+#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */
+#define   SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */
+#define   SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */
+/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */
+#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */
+#define   SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */
+#define   SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */
+#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */
+#define   SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */
+#define   SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */
+#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */
+#define   SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Voltage Regulator is not used */
+#define   SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator is used */
+#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */
+#define   SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */
+#define   SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */
+#define SUPC_MR_KEY_Pos 24
+#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */
+#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))
+/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */
+#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */
+#define   SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */
+#define   SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */
+#define   SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */
+#define   SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */
+#define   SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */
+#define   SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_WKUPDBC_Pos 12
+#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer Period */
+#define   SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
+#define   SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */
+/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */
+#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */
+#define   SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */
+#define   SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */
+#define   SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */
+#define   SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */
+#define   SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */
+#define   SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */
+#define   SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */
+#define   SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */
+#define   SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */
+#define   SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */
+#define   SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */
+#define   SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */
+#define   SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */
+#define   SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */
+#define   SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */
+#define   SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */
+#define   SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */
+#define   SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */
+#define   SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */
+#define   SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */
+#define   SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */
+#define   SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */
+#define   SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */
+#define   SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */
+#define   SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */
+#define   SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */
+#define   SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */
+#define   SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */
+#define   SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */
+#define   SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */
+#define   SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */
+#define   SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */
+#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */
+#define   SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */
+#define   SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */
+#define   SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */
+#define   SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */
+#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */
+#define   SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define   SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */
+#define   SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */
+#define   SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */
+#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */
+#define   SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */
+#define   SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */
+#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */
+#define   SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */
+#define   SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */
+#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */
+#define   SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */
+#define   SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */
+#define   SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */
+#define   SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */
+#define   SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */
+#define   SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */
+#define   SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */
+#define   SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */
+#define   SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */
+#define   SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */
+#define   SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */
+#define   SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */
+#define   SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */
+#define   SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */
+#define   SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */
+#define   SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+
+/*@}*/
+
+
+#endif /* _SAM3N_SUPC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_tc.h b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_tc.h
new file mode 100644
index 000000000..7dbeba940
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_tc.h
@@ -0,0 +1,299 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_TC_COMPONENT_
+#define _SAM3N_TC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Timer Counter */
+/* ============================================================================= */
+/** \addtogroup SAM3N_TC Timer Counter */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief TcChannel hardware registers */
+typedef struct {
+  RwReg      TC_CCR;        /**< \brief (TcChannel Offset: 0x0) Channel Control Register */
+  RwReg      TC_CMR;        /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */
+  RwReg      TC_SMMR;       /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */
+  RoReg      Reserved1[1];
+  RwReg      TC_CV;         /**< \brief (TcChannel Offset: 0x10) Counter Value */
+  RwReg      TC_RA;         /**< \brief (TcChannel Offset: 0x14) Register A */
+  RwReg      TC_RB;         /**< \brief (TcChannel Offset: 0x18) Register B */
+  RwReg      TC_RC;         /**< \brief (TcChannel Offset: 0x1C) Register C */
+  RwReg      TC_SR;         /**< \brief (TcChannel Offset: 0x20) Status Register */
+  RwReg      TC_IER;        /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
+  RwReg      TC_IDR;        /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
+  RwReg      TC_IMR;        /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */
+  RoReg      Reserved2[4];
+} TcChannel;
+/** \brief Tc hardware registers */
+#define TCCHANNEL_NUMBER 3
+typedef struct {
+  TcChannel  TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */
+  WoReg      TC_BCR;        /**< \brief (Tc Offset: 0xC0) Block Control Register */
+  RwReg      TC_BMR;        /**< \brief (Tc Offset: 0xC4) Block Mode Register */
+  WoReg      TC_QIER;       /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */
+  WoReg      TC_QIDR;       /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */
+  RoReg      TC_QIMR;       /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */
+  RoReg      TC_QISR;       /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */
+  RoReg      Reserved1[3];
+  RwReg      TC_WPMR;       /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */
+} Tc;
+#endif /* __ASSEMBLY__ */
+/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */
+#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */
+#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */
+#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */
+/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */
+#define TC_CMR_TCCLKS_Pos 0
+#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */
+#define   TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */
+#define   TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */
+#define   TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */
+#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */
+#define TC_CMR_BURST_Pos 4
+#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */
+#define   TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define   TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */
+#define   TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */
+#define   TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */
+#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */
+#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */
+#define TC_CMR_ETRGEDG_Pos 8
+#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */
+#define   TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define   TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define   TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define   TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */
+#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */
+#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */
+#define TC_CMR_LDRA_Pos 16
+#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */
+#define   TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define   TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define   TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define   TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_LDRB_Pos 18
+#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */
+#define   TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define   TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define   TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define   TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */
+#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */
+#define TC_CMR_EEVTEDG_Pos 8
+#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */
+#define   TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */
+#define   TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define   TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define   TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_EEVT_Pos 10
+#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */
+#define   TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */
+#define   TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */
+#define   TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */
+#define   TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */
+#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */
+#define TC_CMR_WAVSEL_Pos 13
+#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */
+#define   TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */
+#define TC_CMR_ACPA_Pos 16
+#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */
+#define   TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ACPC_Pos 18
+#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */
+#define   TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_AEEVT_Pos 20
+#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */
+#define   TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */
+#define   TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ASWTRG_Pos 22
+#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */
+#define   TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPB_Pos 24
+#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */
+#define   TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPC_Pos 26
+#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */
+#define   TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BEEVT_Pos 28
+#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */
+#define   TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BSWTRG_Pos 30
+#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */
+#define   TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */
+/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */
+#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */
+#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) DOWN Count */
+/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */
+#define TC_CV_CV_Pos 0
+#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */
+/* -------- TC_RA : (TC Offset: N/A) Register A -------- */
+#define TC_RA_RA_Pos 0
+#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */
+#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))
+/* -------- TC_RB : (TC Offset: N/A) Register B -------- */
+#define TC_RB_RB_Pos 0
+#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */
+#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))
+/* -------- TC_RC : (TC Offset: N/A) Register C -------- */
+#define TC_RC_RC_Pos 0
+#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */
+#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))
+/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */
+#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */
+#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */
+#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */
+#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */
+#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */
+#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */
+#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */
+#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */
+#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */
+#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */
+#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */
+/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */
+#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */
+#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */
+#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */
+#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */
+#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */
+#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */
+#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */
+#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */
+/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */
+#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */
+#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */
+#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */
+#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */
+#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */
+#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */
+#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */
+#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */
+/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */
+#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */
+#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */
+#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */
+#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */
+#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */
+#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */
+#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */
+#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */
+/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
+#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */
+/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
+#define TC_BMR_TC0XC0S_Pos 0
+#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */
+#define   TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */
+#define   TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */
+#define   TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */
+#define TC_BMR_TC1XC1S_Pos 2
+#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */
+#define   TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */
+#define   TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */
+#define   TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */
+#define TC_BMR_TC2XC2S_Pos 4
+#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */
+#define   TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */
+#define   TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */
+#define   TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */
+#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */
+#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */
+#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */
+#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */
+#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */
+#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */
+#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */
+#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */
+#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */
+#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */
+#define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR)  */
+#define TC_BMR_MAXFILT_Pos 20
+#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */
+#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))
+/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */
+#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */
+#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */
+#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */
+/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */
+#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */
+#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */
+#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */
+/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */
+#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */
+#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */
+#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */
+/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */
+#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */
+#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */
+#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */
+#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */
+/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */
+#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protect Enable */
+#define TC_WPMR_WPKEY_Pos 8
+#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protect KEY */
+#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3N_TC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_twi.h b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_twi.h
new file mode 100644
index 000000000..0bfed3297
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_twi.h
@@ -0,0 +1,217 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_TWI_COMPONENT_
+#define _SAM3N_TWI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Two-wire Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3N_TWI Two-wire Interface */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Twi hardware registers */
+typedef struct {
+  WoReg TWI_CR;        /**< \brief (Twi Offset: 0x00) Control Register */
+  RwReg TWI_MMR;       /**< \brief (Twi Offset: 0x04) Master Mode Register */
+  RwReg TWI_SMR;       /**< \brief (Twi Offset: 0x08) Slave Mode Register */
+  RwReg TWI_IADR;      /**< \brief (Twi Offset: 0x0C) Internal Address Register */
+  RwReg TWI_CWGR;      /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */
+  RoReg Reserved1[3];
+  RoReg TWI_SR;        /**< \brief (Twi Offset: 0x20) Status Register */
+  WoReg TWI_IER;       /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */
+  WoReg TWI_IDR;       /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */
+  RoReg TWI_IMR;       /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */
+  RoReg TWI_RHR;       /**< \brief (Twi Offset: 0x30) Receive Holding Register */
+  WoReg TWI_THR;       /**< \brief (Twi Offset: 0x34) Transmit Holding Register */
+  RoReg Reserved2[50];
+  RwReg TWI_RPR;       /**< \brief (Twi Offset: 0x100) Receive Pointer Register */
+  RwReg TWI_RCR;       /**< \brief (Twi Offset: 0x104) Receive Counter Register */
+  RwReg TWI_TPR;       /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */
+  RwReg TWI_TCR;       /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */
+  RwReg TWI_RNPR;      /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */
+  RwReg TWI_RNCR;      /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */
+  RwReg TWI_TNPR;      /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */
+  RwReg TWI_TNCR;      /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */
+  WoReg TWI_PTCR;      /**< \brief (Twi Offset: 0x120) Transfer Control Register */
+  RoReg TWI_PTSR;      /**< \brief (Twi Offset: 0x124) Transfer Status Register */
+} Twi;
+#endif /* __ASSEMBLY__ */
+/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */
+#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */
+#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */
+#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */
+#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */
+#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */
+#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */
+#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */
+#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */
+/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */
+#define TWI_MMR_IADRSZ_Pos 8
+#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */
+#define   TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */
+#define   TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */
+#define   TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */
+#define   TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */
+#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */
+#define TWI_MMR_DADR_Pos 16
+#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */
+#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))
+/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */
+#define TWI_SMR_SADR_Pos 16
+#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */
+#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))
+/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */
+#define TWI_IADR_IADR_Pos 0
+#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */
+#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))
+/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */
+#define TWI_CWGR_CLDIV_Pos 0
+#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */
+#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))
+#define TWI_CWGR_CHDIV_Pos 8
+#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */
+#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))
+#define TWI_CWGR_CKDIV_Pos 16
+#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */
+#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))
+/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */
+#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */
+#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */
+#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */
+#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */
+#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */
+#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */
+#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */
+#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */
+#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */
+#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */
+#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */
+#define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */
+#define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */
+#define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */
+#define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */
+/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */
+#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */
+#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */
+#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */
+#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */
+#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */
+#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */
+#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */
+#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */
+#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */
+#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */
+#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */
+#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */
+#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */
+#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */
+/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */
+#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */
+#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */
+#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */
+#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */
+#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */
+#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */
+#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */
+#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */
+#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */
+#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */
+#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */
+#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */
+#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */
+#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */
+/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */
+#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */
+#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */
+#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */
+#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */
+#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */
+#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */
+#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */
+#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */
+#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */
+#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */
+#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */
+#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */
+#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */
+#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */
+/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */
+#define TWI_RHR_RXDATA_Pos 0
+#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */
+/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */
+#define TWI_THR_TXDATA_Pos 0
+#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */
+#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))
+/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */
+#define TWI_RPR_RXPTR_Pos 0
+#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */
+#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos)))
+/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */
+#define TWI_RCR_RXCTR_Pos 0
+#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */
+#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos)))
+/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */
+#define TWI_TPR_TXPTR_Pos 0
+#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */
+#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos)))
+/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */
+#define TWI_TCR_TXCTR_Pos 0
+#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */
+#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos)))
+/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */
+#define TWI_RNPR_RXNPTR_Pos 0
+#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */
+#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos)))
+/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */
+#define TWI_RNCR_RXNCTR_Pos 0
+#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */
+#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos)))
+/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define TWI_TNPR_TXNPTR_Pos 0
+#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */
+#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos)))
+/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define TWI_TNCR_TXNCTR_Pos 0
+#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */
+#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos)))
+/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */
+#define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */
+#define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */
+#define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */
+#define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */
+/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */
+#define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */
+#define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3N_TWI_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_uart.h b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_uart.h
new file mode 100644
index 000000000..9ad0dd077
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_uart.h
@@ -0,0 +1,185 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_UART_COMPONENT_
+#define _SAM3N_UART_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM3N_UART Universal Asynchronous Receiver Transmitter */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Uart hardware registers */
+typedef struct {
+  WoReg UART_CR;       /**< \brief (Uart Offset: 0x0000) Control Register */
+  RwReg UART_MR;       /**< \brief (Uart Offset: 0x0004) Mode Register */
+  WoReg UART_IER;      /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */
+  WoReg UART_IDR;      /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */
+  RoReg UART_IMR;      /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */
+  RoReg UART_SR;       /**< \brief (Uart Offset: 0x0014) Status Register */
+  RoReg UART_RHR;      /**< \brief (Uart Offset: 0x0018) Receive Holding Register */
+  WoReg UART_THR;      /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */
+  RwReg UART_BRGR;     /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */
+  RoReg Reserved1[55];
+  RwReg UART_RPR;      /**< \brief (Uart Offset: 0x100) Receive Pointer Register */
+  RwReg UART_RCR;      /**< \brief (Uart Offset: 0x104) Receive Counter Register */
+  RwReg UART_TPR;      /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */
+  RwReg UART_TCR;      /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */
+  RwReg UART_RNPR;     /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */
+  RwReg UART_RNCR;     /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */
+  RwReg UART_TNPR;     /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */
+  RwReg UART_TNCR;     /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */
+  WoReg UART_PTCR;     /**< \brief (Uart Offset: 0x120) Transfer Control Register */
+  RoReg UART_PTSR;     /**< \brief (Uart Offset: 0x124) Transfer Status Register */
+} Uart;
+#endif /* __ASSEMBLY__ */
+/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
+#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */
+#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */
+#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */
+#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */
+#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */
+#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */
+#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */
+/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
+#define UART_MR_PAR_Pos 9
+#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */
+#define   UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */
+#define   UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */
+#define   UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */
+#define   UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */
+#define   UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */
+#define UART_MR_CHMODE_Pos 14
+#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */
+#define   UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */
+#define   UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */
+#define   UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */
+#define   UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */
+/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
+#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */
+#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */
+#define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */
+#define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */
+#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */
+#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */
+#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */
+#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */
+#define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */
+#define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */
+/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
+#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */
+#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */
+#define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */
+#define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */
+#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */
+#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */
+#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */
+#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */
+#define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */
+#define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */
+/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
+#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */
+#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */
+#define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */
+#define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */
+#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */
+#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */
+#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */
+#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */
+#define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */
+#define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */
+/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
+#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */
+#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */
+#define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */
+#define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */
+#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */
+#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */
+#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */
+#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */
+#define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */
+#define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */
+/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
+#define UART_RHR_RXCHR_Pos 0
+#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */
+/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
+#define UART_THR_TXCHR_Pos 0
+#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */
+#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
+/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define UART_BRGR_CD_Pos 0
+#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */
+#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
+/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */
+#define UART_RPR_RXPTR_Pos 0
+#define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */
+#define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos)))
+/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */
+#define UART_RCR_RXCTR_Pos 0
+#define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */
+#define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos)))
+/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */
+#define UART_TPR_TXPTR_Pos 0
+#define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */
+#define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos)))
+/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */
+#define UART_TCR_TXCTR_Pos 0
+#define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */
+#define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos)))
+/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */
+#define UART_RNPR_RXNPTR_Pos 0
+#define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */
+#define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos)))
+/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */
+#define UART_RNCR_RXNCTR_Pos 0
+#define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */
+#define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos)))
+/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define UART_TNPR_TXNPTR_Pos 0
+#define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */
+#define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos)))
+/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define UART_TNCR_TXNCTR_Pos 0
+#define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */
+#define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos)))
+/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */
+#define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */
+#define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */
+#define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */
+#define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */
+/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */
+#define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */
+#define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3N_UART_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_usart.h b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_usart.h
new file mode 100644
index 000000000..f944a30f7
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_usart.h
@@ -0,0 +1,305 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_USART_COMPONENT_
+#define _SAM3N_USART_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM3N_USART Universal Synchronous Asynchronous Receiver Transmitter */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Usart hardware registers */
+typedef struct {
+  WoReg US_CR;         /**< \brief (Usart Offset: 0x0000) Control Register */
+  RwReg US_MR;         /**< \brief (Usart Offset: 0x0004) Mode Register */
+  WoReg US_IER;        /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */
+  WoReg US_IDR;        /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */
+  RoReg US_IMR;        /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */
+  RoReg US_CSR;        /**< \brief (Usart Offset: 0x0014) Channel Status Register */
+  RoReg US_RHR;        /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */
+  WoReg US_THR;        /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */
+  RwReg US_BRGR;       /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */
+  RwReg US_RTOR;       /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */
+  RwReg US_TTGR;       /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */
+  RoReg Reserved1[5];
+  RwReg US_FIDI;       /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */
+  RoReg US_NER;        /**< \brief (Usart Offset: 0x0044) Number of Errors Register */
+  RoReg Reserved2[1];
+  RwReg US_IF;         /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */
+  RoReg Reserved3[37];
+  RwReg US_WPMR;       /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */
+  RoReg US_WPSR;       /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved4[5];
+  RwReg US_RPR;        /**< \brief (Usart Offset: 0x100) Receive Pointer Register */
+  RwReg US_RCR;        /**< \brief (Usart Offset: 0x104) Receive Counter Register */
+  RwReg US_TPR;        /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */
+  RwReg US_TCR;        /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */
+  RwReg US_RNPR;       /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */
+  RwReg US_RNCR;       /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */
+  RwReg US_TNPR;       /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */
+  RwReg US_TNCR;       /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */
+  WoReg US_PTCR;       /**< \brief (Usart Offset: 0x120) Transfer Control Register */
+  RoReg US_PTSR;       /**< \brief (Usart Offset: 0x124) Transfer Status Register */
+} Usart;
+#endif /* __ASSEMBLY__ */
+/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
+#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */
+#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */
+#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */
+#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */
+#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */
+#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */
+#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */
+#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */
+#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */
+#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */
+#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */
+#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */
+#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */
+#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */
+#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */
+#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */
+#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */
+#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */
+/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
+#define US_MR_USART_MODE_Pos 0
+#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR)  */
+#define   US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */
+#define   US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */
+#define   US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */
+#define   US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */
+#define   US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */
+#define   US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */
+#define   US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */
+#define   US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */
+#define US_MR_USCLKS_Pos 4
+#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */
+#define   US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */
+#define   US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */
+#define   US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */
+#define US_MR_CHRL_Pos 6
+#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */
+#define   US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */
+#define   US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */
+#define   US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */
+#define   US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */
+#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */
+#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */
+#define US_MR_PAR_Pos 9
+#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */
+#define   US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */
+#define   US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */
+#define   US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */
+#define   US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */
+#define   US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */
+#define   US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */
+#define US_MR_NBSTOP_Pos 12
+#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */
+#define   US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */
+#define   US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */
+#define   US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */
+#define US_MR_CHMODE_Pos 14
+#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */
+#define   US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */
+#define   US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */
+#define   US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */
+#define   US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */
+#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */
+#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */
+#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */
+#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */
+#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */
+#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */
+#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */
+#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) INverted Data */
+#define US_MR_MAX_ITERATION_Pos 24
+#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR)  */
+#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))
+#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */
+/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
+#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */
+#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */
+#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */
+#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */
+#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */
+#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */
+#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */
+#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */
+#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */
+#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */
+#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached */
+#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error */
+#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */
+#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */
+#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non AcknowledgeInterrupt Enable */
+#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
+/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
+#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */
+#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */
+#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */
+#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */
+#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */
+#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */
+#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */
+#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */
+#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */
+#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */
+#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max number of Repetitions Reached Disable */
+#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Disable */
+#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */
+#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */
+#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non AcknowledgeInterrupt Disable */
+#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
+/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
+#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */
+#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */
+#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */
+#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */
+#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */
+#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */
+#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */
+#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */
+#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */
+#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
+#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max number of Repetitions Reached Mask */
+#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Mask */
+#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */
+#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */
+#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non AcknowledgeInterrupt Mask */
+#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
+/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
+#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */
+#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */
+#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */
+#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */
+#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */
+#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */
+#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */
+#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */
+#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */
+#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */
+#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max number of Repetitions Reached */
+#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) SPI Underrun Error */
+#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */
+#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */
+#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non AcknowledgeInterrupt */
+#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */
+#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */
+/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */
+#define US_RHR_RXCHR_Pos 0
+#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */
+#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */
+/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */
+#define US_THR_TXCHR_Pos 0
+#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */
+#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
+#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be transmitted */
+/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define US_BRGR_CD_Pos 0
+#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */
+#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
+#define US_BRGR_FP_Pos 16
+#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */
+#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
+/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
+#define US_RTOR_TO_Pos 0
+#define US_RTOR_TO_Msk (0xffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */
+#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
+/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
+#define US_TTGR_TG_Pos 0
+#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */
+#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
+/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */
+#define US_FIDI_FI_DI_RATIO_Pos 0
+#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */
+#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))
+/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */
+#define US_NER_NB_ERRORS_Pos 0
+#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */
+/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */
+#define US_IF_IRDA_FILTER_Pos 0
+#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */
+#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))
+/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */
+#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */
+#define US_WPMR_WPKEY_Pos 8
+#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */
+#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))
+/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */
+#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */
+#define US_WPSR_WPVSRC_Pos 8
+#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */
+/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */
+#define US_RPR_RXPTR_Pos 0
+#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */
+#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos)))
+/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */
+#define US_RCR_RXCTR_Pos 0
+#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */
+#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos)))
+/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */
+#define US_TPR_TXPTR_Pos 0
+#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */
+#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos)))
+/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */
+#define US_TCR_TXCTR_Pos 0
+#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */
+#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos)))
+/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */
+#define US_RNPR_RXNPTR_Pos 0
+#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */
+#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos)))
+/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */
+#define US_RNCR_RXNCTR_Pos 0
+#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */
+#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos)))
+/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define US_TNPR_TXNPTR_Pos 0
+#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */
+#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos)))
+/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define US_TNCR_TXNCTR_Pos 0
+#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */
+#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos)))
+/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */
+#define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */
+#define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */
+#define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */
+#define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */
+/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */
+#define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */
+#define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3N_USART_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_wdt.h b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_wdt.h
new file mode 100644
index 000000000..41b038831
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/component/component_wdt.h
@@ -0,0 +1,72 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_WDT_COMPONENT_
+#define _SAM3N_WDT_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Watchdog Timer */
+/* ============================================================================= */
+/** \addtogroup SAM3N_WDT Watchdog Timer */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Wdt hardware registers */
+typedef struct {
+  WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */
+  RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */
+  RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */
+} Wdt;
+#endif /* __ASSEMBLY__ */
+/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */
+#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */
+#define WDT_CR_KEY_Pos 24
+#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */
+#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))
+/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */
+#define WDT_MR_WDV_Pos 0
+#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */
+#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))
+#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */
+#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */
+#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */
+#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */
+#define WDT_MR_WDD_Pos 16
+#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */
+#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))
+#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */
+#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */
+/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */
+#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */
+#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */
+
+/*@}*/
+
+
+#endif /* _SAM3N_WDT_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_adc.h b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_adc.h
new file mode 100644
index 000000000..d19255b9c
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_adc.h
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_ADC_INSTANCE_
+#define _SAM3N_ADC_INSTANCE_
+
+/* ========== Register definition for ADC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_ADC_CR               (0x40038000U) /**< \brief (ADC) Control Register */
+#define REG_ADC_MR               (0x40038004U) /**< \brief (ADC) Mode Register */
+#define REG_ADC_SEQR1            (0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */
+#define REG_ADC_SEQR2            (0x4003800CU) /**< \brief (ADC) Channel Sequence Register 2 */
+#define REG_ADC_CHER             (0x40038010U) /**< \brief (ADC) Channel Enable Register */
+#define REG_ADC_CHDR             (0x40038014U) /**< \brief (ADC) Channel Disable Register */
+#define REG_ADC_CHSR             (0x40038018U) /**< \brief (ADC) Channel Status Register */
+#define REG_ADC_LCDR             (0x40038020U) /**< \brief (ADC) Last Converted Data Register */
+#define REG_ADC_IER              (0x40038024U) /**< \brief (ADC) Interrupt Enable Register */
+#define REG_ADC_IDR              (0x40038028U) /**< \brief (ADC) Interrupt Disable Register */
+#define REG_ADC_IMR              (0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */
+#define REG_ADC_ISR              (0x40038030U) /**< \brief (ADC) Interrupt Status Register */
+#define REG_ADC_OVER             (0x4003803CU) /**< \brief (ADC) Overrun Status Register */
+#define REG_ADC_EMR              (0x40038040U) /**< \brief (ADC) Extended Mode Register */
+#define REG_ADC_CWR              (0x40038044U) /**< \brief (ADC) Compare Window Register */
+#define REG_ADC_CDR              (0x40038050U) /**< \brief (ADC) Channel Data Register */
+#define REG_ADC_TRGR             (0x400380C0U) /**< \brief (ADC) Trigger Register */
+#define REG_ADC_WPMR             (0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */
+#define REG_ADC_WPSR             (0x400380E8U) /**< \brief (ADC) Write Protect Status Register */
+#define REG_ADC_RPR              (0x40038100U) /**< \brief (ADC) Receive Pointer Register */
+#define REG_ADC_RCR              (0x40038104U) /**< \brief (ADC) Receive Counter Register */
+#define REG_ADC_TPR              (0x40038108U) /**< \brief (ADC) Transmit Pointer Register */
+#define REG_ADC_TCR              (0x4003810CU) /**< \brief (ADC) Transmit Counter Register */
+#define REG_ADC_RNPR             (0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */
+#define REG_ADC_RNCR             (0x40038114U) /**< \brief (ADC) Receive Next Counter Register */
+#define REG_ADC_TNPR             (0x40038118U) /**< \brief (ADC) Transmit Next Pointer Register */
+#define REG_ADC_TNCR             (0x4003811CU) /**< \brief (ADC) Transmit Next Counter Register */
+#define REG_ADC_PTCR             (0x40038120U) /**< \brief (ADC) Transfer Control Register */
+#define REG_ADC_PTSR             (0x40038124U) /**< \brief (ADC) Transfer Status Register */
+#else
+#define REG_ADC_CR      (*(WoReg*)0x40038000U) /**< \brief (ADC) Control Register */
+#define REG_ADC_MR      (*(RwReg*)0x40038004U) /**< \brief (ADC) Mode Register */
+#define REG_ADC_SEQR1   (*(RwReg*)0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */
+#define REG_ADC_SEQR2   (*(RwReg*)0x4003800CU) /**< \brief (ADC) Channel Sequence Register 2 */
+#define REG_ADC_CHER    (*(WoReg*)0x40038010U) /**< \brief (ADC) Channel Enable Register */
+#define REG_ADC_CHDR    (*(WoReg*)0x40038014U) /**< \brief (ADC) Channel Disable Register */
+#define REG_ADC_CHSR    (*(RoReg*)0x40038018U) /**< \brief (ADC) Channel Status Register */
+#define REG_ADC_LCDR    (*(RoReg*)0x40038020U) /**< \brief (ADC) Last Converted Data Register */
+#define REG_ADC_IER     (*(WoReg*)0x40038024U) /**< \brief (ADC) Interrupt Enable Register */
+#define REG_ADC_IDR     (*(WoReg*)0x40038028U) /**< \brief (ADC) Interrupt Disable Register */
+#define REG_ADC_IMR     (*(RoReg*)0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */
+#define REG_ADC_ISR     (*(RoReg*)0x40038030U) /**< \brief (ADC) Interrupt Status Register */
+#define REG_ADC_OVER    (*(RoReg*)0x4003803CU) /**< \brief (ADC) Overrun Status Register */
+#define REG_ADC_EMR     (*(RwReg*)0x40038040U) /**< \brief (ADC) Extended Mode Register */
+#define REG_ADC_CWR     (*(RwReg*)0x40038044U) /**< \brief (ADC) Compare Window Register */
+#define REG_ADC_CDR     (*(RoReg*)0x40038050U) /**< \brief (ADC) Channel Data Register */
+#define REG_ADC_TRGR    (*(RwReg*)0x400380C0U) /**< \brief (ADC) Trigger Register */
+#define REG_ADC_WPMR    (*(RwReg*)0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */
+#define REG_ADC_WPSR    (*(RoReg*)0x400380E8U) /**< \brief (ADC) Write Protect Status Register */
+#define REG_ADC_RPR     (*(RwReg*)0x40038100U) /**< \brief (ADC) Receive Pointer Register */
+#define REG_ADC_RCR     (*(RwReg*)0x40038104U) /**< \brief (ADC) Receive Counter Register */
+#define REG_ADC_TPR     (*(RwReg*)0x40038108U) /**< \brief (ADC) Transmit Pointer Register */
+#define REG_ADC_TCR     (*(RwReg*)0x4003810CU) /**< \brief (ADC) Transmit Counter Register */
+#define REG_ADC_RNPR    (*(RwReg*)0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */
+#define REG_ADC_RNCR    (*(RwReg*)0x40038114U) /**< \brief (ADC) Receive Next Counter Register */
+#define REG_ADC_TNPR    (*(RwReg*)0x40038118U) /**< \brief (ADC) Transmit Next Pointer Register */
+#define REG_ADC_TNCR    (*(RwReg*)0x4003811CU) /**< \brief (ADC) Transmit Next Counter Register */
+#define REG_ADC_PTCR    (*(WoReg*)0x40038120U) /**< \brief (ADC) Transfer Control Register */
+#define REG_ADC_PTSR    (*(RoReg*)0x40038124U) /**< \brief (ADC) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3N_ADC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_chipid.h b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_chipid.h
new file mode 100644
index 000000000..8c6c112c3
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_chipid.h
@@ -0,0 +1,42 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_CHIPID_INSTANCE_
+#define _SAM3N_CHIPID_INSTANCE_
+
+/* ========== Register definition for CHIPID peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_CHIPID_CIDR          (0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
+#define REG_CHIPID_EXID          (0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
+#else
+#define REG_CHIPID_CIDR (*(RoReg*)0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
+#define REG_CHIPID_EXID (*(RoReg*)0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3N_CHIPID_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_dacc.h b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_dacc.h
new file mode 100644
index 000000000..0fac96ac3
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_dacc.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_DACC_INSTANCE_
+#define _SAM3N_DACC_INSTANCE_
+
+/* ========== Register definition for DACC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_DACC_CR            (0x4003C000U) /**< \brief (DACC) Control Register */
+#define REG_DACC_MR            (0x4003C004U) /**< \brief (DACC) Mode Register */
+#define REG_DACC_CDR           (0x4003C008U) /**< \brief (DACC) Conversion Data Register */
+#define REG_DACC_IER           (0x4003C00CU) /**< \brief (DACC) Interrupt Enable Register */
+#define REG_DACC_IDR           (0x4003C010U) /**< \brief (DACC) Interrupt Disable Register */
+#define REG_DACC_IMR           (0x4003C014U) /**< \brief (DACC) Interrupt Mask Register */
+#define REG_DACC_ISR           (0x4003C018U) /**< \brief (DACC) Interrupt Status Register */
+#define REG_DACC_WPMR          (0x4003C0E4U) /**< \brief (DACC) Write Protect Mode Register */
+#define REG_DACC_WPSR          (0x4003C0E8U) /**< \brief (DACC) Write Protect Status Register */
+#define REG_DACC_RPR           (0x4003C100U) /**< \brief (DACC) Receive Pointer Register */
+#define REG_DACC_RCR           (0x4003C104U) /**< \brief (DACC) Receive Counter Register */
+#define REG_DACC_TPR           (0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */
+#define REG_DACC_TCR           (0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */
+#define REG_DACC_RNPR          (0x4003C110U) /**< \brief (DACC) Receive Next Pointer Register */
+#define REG_DACC_RNCR          (0x4003C114U) /**< \brief (DACC) Receive Next Counter Register */
+#define REG_DACC_TNPR          (0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */
+#define REG_DACC_TNCR          (0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */
+#define REG_DACC_PTCR          (0x4003C120U) /**< \brief (DACC) Transfer Control Register */
+#define REG_DACC_PTSR          (0x4003C124U) /**< \brief (DACC) Transfer Status Register */
+#else
+#define REG_DACC_CR   (*(WoReg*)0x4003C000U) /**< \brief (DACC) Control Register */
+#define REG_DACC_MR   (*(RwReg*)0x4003C004U) /**< \brief (DACC) Mode Register */
+#define REG_DACC_CDR  (*(WoReg*)0x4003C008U) /**< \brief (DACC) Conversion Data Register */
+#define REG_DACC_IER  (*(WoReg*)0x4003C00CU) /**< \brief (DACC) Interrupt Enable Register */
+#define REG_DACC_IDR  (*(WoReg*)0x4003C010U) /**< \brief (DACC) Interrupt Disable Register */
+#define REG_DACC_IMR  (*(RoReg*)0x4003C014U) /**< \brief (DACC) Interrupt Mask Register */
+#define REG_DACC_ISR  (*(RoReg*)0x4003C018U) /**< \brief (DACC) Interrupt Status Register */
+#define REG_DACC_WPMR (*(RwReg*)0x4003C0E4U) /**< \brief (DACC) Write Protect Mode Register */
+#define REG_DACC_WPSR (*(RoReg*)0x4003C0E8U) /**< \brief (DACC) Write Protect Status Register */
+#define REG_DACC_RPR  (*(RwReg*)0x4003C100U) /**< \brief (DACC) Receive Pointer Register */
+#define REG_DACC_RCR  (*(RwReg*)0x4003C104U) /**< \brief (DACC) Receive Counter Register */
+#define REG_DACC_TPR  (*(RwReg*)0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */
+#define REG_DACC_TCR  (*(RwReg*)0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */
+#define REG_DACC_RNPR (*(RwReg*)0x4003C110U) /**< \brief (DACC) Receive Next Pointer Register */
+#define REG_DACC_RNCR (*(RwReg*)0x4003C114U) /**< \brief (DACC) Receive Next Counter Register */
+#define REG_DACC_TNPR (*(RwReg*)0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */
+#define REG_DACC_TNCR (*(RwReg*)0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */
+#define REG_DACC_PTCR (*(WoReg*)0x4003C120U) /**< \brief (DACC) Transfer Control Register */
+#define REG_DACC_PTSR (*(RoReg*)0x4003C124U) /**< \brief (DACC) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3N_DACC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_efc.h b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_efc.h
new file mode 100644
index 000000000..88d6a66ff
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_efc.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_EFC_INSTANCE_
+#define _SAM3N_EFC_INSTANCE_
+
+/* ========== Register definition for EFC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_EFC_FMR           (0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */
+#define REG_EFC_FCR           (0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */
+#define REG_EFC_FSR           (0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */
+#define REG_EFC_FRR           (0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */
+#else
+#define REG_EFC_FMR  (*(RwReg*)0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */
+#define REG_EFC_FCR  (*(WoReg*)0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */
+#define REG_EFC_FSR  (*(RoReg*)0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */
+#define REG_EFC_FRR  (*(RoReg*)0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3N_EFC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_gpbr.h b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_gpbr.h
new file mode 100644
index 000000000..e872de813
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_gpbr.h
@@ -0,0 +1,40 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_GPBR_INSTANCE_
+#define _SAM3N_GPBR_INSTANCE_
+
+/* ========== Register definition for GPBR peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_GPBR_GPBR            (0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */
+#else
+#define REG_GPBR_GPBR   (*(RwReg*)0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3N_GPBR_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_matrix.h b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_matrix.h
new file mode 100644
index 000000000..fee8e9ebc
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_matrix.h
@@ -0,0 +1,56 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_MATRIX_INSTANCE_
+#define _SAM3N_MATRIX_INSTANCE_
+
+/* ========== Register definition for MATRIX peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_MATRIX_MCFG             (0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
+#define REG_MATRIX_SCFG             (0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
+#define REG_MATRIX_PRAS0            (0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
+#define REG_MATRIX_PRAS1            (0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
+#define REG_MATRIX_PRAS2            (0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
+#define REG_MATRIX_PRAS3            (0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
+#define REG_CCFG_SYSIO              (0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */
+#define REG_MATRIX_WPMR             (0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
+#define REG_MATRIX_WPSR             (0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
+#else
+#define REG_MATRIX_MCFG    (*(RwReg*)0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
+#define REG_MATRIX_SCFG    (*(RwReg*)0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
+#define REG_MATRIX_PRAS0   (*(RwReg*)0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
+#define REG_MATRIX_PRAS1   (*(RwReg*)0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
+#define REG_MATRIX_PRAS2   (*(RwReg*)0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
+#define REG_MATRIX_PRAS3   (*(RwReg*)0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
+#define REG_CCFG_SYSIO     (*(RwReg*)0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */
+#define REG_MATRIX_WPMR    (*(RwReg*)0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
+#define REG_MATRIX_WPSR    (*(RoReg*)0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3N_MATRIX_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_pioa.h b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_pioa.h
new file mode 100644
index 000000000..484e6996c
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_pioa.h
@@ -0,0 +1,132 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_PIOA_INSTANCE_
+#define _SAM3N_PIOA_INSTANCE_
+
+/* ========== Register definition for PIOA peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PIOA_PER                (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
+#define REG_PIOA_PDR                (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
+#define REG_PIOA_PSR                (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
+#define REG_PIOA_OER                (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
+#define REG_PIOA_ODR                (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
+#define REG_PIOA_OSR                (0x400E0E18U) /**< \brief (PIOA) Output Status Register */
+#define REG_PIOA_IFER               (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
+#define REG_PIOA_IFDR               (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
+#define REG_PIOA_IFSR               (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
+#define REG_PIOA_SODR               (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
+#define REG_PIOA_CODR               (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
+#define REG_PIOA_ODSR               (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
+#define REG_PIOA_PDSR               (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
+#define REG_PIOA_IER                (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
+#define REG_PIOA_IDR                (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
+#define REG_PIOA_IMR                (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
+#define REG_PIOA_ISR                (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
+#define REG_PIOA_MDER               (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
+#define REG_PIOA_MDDR               (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
+#define REG_PIOA_MDSR               (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
+#define REG_PIOA_PUDR               (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
+#define REG_PIOA_PUER               (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
+#define REG_PIOA_PUSR               (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
+#define REG_PIOA_ABCDSR             (0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
+#define REG_PIOA_IFSCDR             (0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
+#define REG_PIOA_IFSCER             (0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
+#define REG_PIOA_IFSCSR             (0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
+#define REG_PIOA_SCDR               (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
+#define REG_PIOA_PPDDR              (0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
+#define REG_PIOA_PPDER              (0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
+#define REG_PIOA_PPDSR              (0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
+#define REG_PIOA_OWER               (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
+#define REG_PIOA_OWDR               (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
+#define REG_PIOA_OWSR               (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
+#define REG_PIOA_AIMER              (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
+#define REG_PIOA_AIMDR              (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
+#define REG_PIOA_AIMMR              (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
+#define REG_PIOA_ESR                (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
+#define REG_PIOA_LSR                (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
+#define REG_PIOA_ELSR               (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
+#define REG_PIOA_FELLSR             (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
+#define REG_PIOA_REHLSR             (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
+#define REG_PIOA_FRLHSR             (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
+#define REG_PIOA_LOCKSR             (0x400E0EE0U) /**< \brief (PIOA) Lock Status */
+#define REG_PIOA_WPMR               (0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
+#define REG_PIOA_WPSR               (0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
+#define REG_PIOA_SCHMITT            (0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
+#else
+#define REG_PIOA_PER       (*(WoReg*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
+#define REG_PIOA_PDR       (*(WoReg*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
+#define REG_PIOA_PSR       (*(RoReg*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
+#define REG_PIOA_OER       (*(WoReg*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
+#define REG_PIOA_ODR       (*(WoReg*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
+#define REG_PIOA_OSR       (*(RoReg*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */
+#define REG_PIOA_IFER      (*(WoReg*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
+#define REG_PIOA_IFDR      (*(WoReg*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
+#define REG_PIOA_IFSR      (*(RoReg*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
+#define REG_PIOA_SODR      (*(WoReg*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
+#define REG_PIOA_CODR      (*(WoReg*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
+#define REG_PIOA_ODSR      (*(RwReg*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
+#define REG_PIOA_PDSR      (*(RoReg*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
+#define REG_PIOA_IER       (*(WoReg*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
+#define REG_PIOA_IDR       (*(WoReg*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
+#define REG_PIOA_IMR       (*(RoReg*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
+#define REG_PIOA_ISR       (*(RoReg*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
+#define REG_PIOA_MDER      (*(WoReg*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
+#define REG_PIOA_MDDR      (*(WoReg*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
+#define REG_PIOA_MDSR      (*(RoReg*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
+#define REG_PIOA_PUDR      (*(WoReg*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
+#define REG_PIOA_PUER      (*(WoReg*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
+#define REG_PIOA_PUSR      (*(RoReg*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
+#define REG_PIOA_ABCDSR    (*(RwReg*)0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
+#define REG_PIOA_IFSCDR    (*(WoReg*)0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
+#define REG_PIOA_IFSCER    (*(WoReg*)0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
+#define REG_PIOA_IFSCSR    (*(RoReg*)0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
+#define REG_PIOA_SCDR      (*(RwReg*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
+#define REG_PIOA_PPDDR     (*(WoReg*)0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
+#define REG_PIOA_PPDER     (*(WoReg*)0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
+#define REG_PIOA_PPDSR     (*(RoReg*)0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
+#define REG_PIOA_OWER      (*(WoReg*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
+#define REG_PIOA_OWDR      (*(WoReg*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
+#define REG_PIOA_OWSR      (*(RoReg*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
+#define REG_PIOA_AIMER     (*(WoReg*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
+#define REG_PIOA_AIMDR     (*(WoReg*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
+#define REG_PIOA_AIMMR     (*(RoReg*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
+#define REG_PIOA_ESR       (*(WoReg*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
+#define REG_PIOA_LSR       (*(WoReg*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
+#define REG_PIOA_ELSR      (*(RoReg*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
+#define REG_PIOA_FELLSR    (*(WoReg*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
+#define REG_PIOA_REHLSR    (*(WoReg*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
+#define REG_PIOA_FRLHSR    (*(RoReg*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
+#define REG_PIOA_LOCKSR    (*(RoReg*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */
+#define REG_PIOA_WPMR      (*(RwReg*)0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
+#define REG_PIOA_WPSR      (*(RoReg*)0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
+#define REG_PIOA_SCHMITT   (*(RwReg*)0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3N_PIOA_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_piob.h b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_piob.h
new file mode 100644
index 000000000..fb87acb2e
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_piob.h
@@ -0,0 +1,132 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_PIOB_INSTANCE_
+#define _SAM3N_PIOB_INSTANCE_
+
+/* ========== Register definition for PIOB peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PIOB_PER                (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
+#define REG_PIOB_PDR                (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
+#define REG_PIOB_PSR                (0x400E1008U) /**< \brief (PIOB) PIO Status Register */
+#define REG_PIOB_OER                (0x400E1010U) /**< \brief (PIOB) Output Enable Register */
+#define REG_PIOB_ODR                (0x400E1014U) /**< \brief (PIOB) Output Disable Register */
+#define REG_PIOB_OSR                (0x400E1018U) /**< \brief (PIOB) Output Status Register */
+#define REG_PIOB_IFER               (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
+#define REG_PIOB_IFDR               (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
+#define REG_PIOB_IFSR               (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
+#define REG_PIOB_SODR               (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
+#define REG_PIOB_CODR               (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
+#define REG_PIOB_ODSR               (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
+#define REG_PIOB_PDSR               (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
+#define REG_PIOB_IER                (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
+#define REG_PIOB_IDR                (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
+#define REG_PIOB_IMR                (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
+#define REG_PIOB_ISR                (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
+#define REG_PIOB_MDER               (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
+#define REG_PIOB_MDDR               (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
+#define REG_PIOB_MDSR               (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
+#define REG_PIOB_PUDR               (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
+#define REG_PIOB_PUER               (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
+#define REG_PIOB_PUSR               (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
+#define REG_PIOB_ABCDSR             (0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */
+#define REG_PIOB_IFSCDR             (0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
+#define REG_PIOB_IFSCER             (0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
+#define REG_PIOB_IFSCSR             (0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
+#define REG_PIOB_SCDR               (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
+#define REG_PIOB_PPDDR              (0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */
+#define REG_PIOB_PPDER              (0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */
+#define REG_PIOB_PPDSR              (0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */
+#define REG_PIOB_OWER               (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
+#define REG_PIOB_OWDR               (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
+#define REG_PIOB_OWSR               (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
+#define REG_PIOB_AIMER              (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
+#define REG_PIOB_AIMDR              (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
+#define REG_PIOB_AIMMR              (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
+#define REG_PIOB_ESR                (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
+#define REG_PIOB_LSR                (0x400E10C4U) /**< \brief (PIOB) Level Select Register */
+#define REG_PIOB_ELSR               (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
+#define REG_PIOB_FELLSR             (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
+#define REG_PIOB_REHLSR             (0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
+#define REG_PIOB_FRLHSR             (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
+#define REG_PIOB_LOCKSR             (0x400E10E0U) /**< \brief (PIOB) Lock Status */
+#define REG_PIOB_WPMR               (0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
+#define REG_PIOB_WPSR               (0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
+#define REG_PIOB_SCHMITT            (0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */
+#else
+#define REG_PIOB_PER       (*(WoReg*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
+#define REG_PIOB_PDR       (*(WoReg*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
+#define REG_PIOB_PSR       (*(RoReg*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */
+#define REG_PIOB_OER       (*(WoReg*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */
+#define REG_PIOB_ODR       (*(WoReg*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */
+#define REG_PIOB_OSR       (*(RoReg*)0x400E1018U) /**< \brief (PIOB) Output Status Register */
+#define REG_PIOB_IFER      (*(WoReg*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
+#define REG_PIOB_IFDR      (*(WoReg*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
+#define REG_PIOB_IFSR      (*(RoReg*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
+#define REG_PIOB_SODR      (*(WoReg*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
+#define REG_PIOB_CODR      (*(WoReg*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
+#define REG_PIOB_ODSR      (*(RwReg*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
+#define REG_PIOB_PDSR      (*(RoReg*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
+#define REG_PIOB_IER       (*(WoReg*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
+#define REG_PIOB_IDR       (*(WoReg*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
+#define REG_PIOB_IMR       (*(RoReg*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
+#define REG_PIOB_ISR       (*(RoReg*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
+#define REG_PIOB_MDER      (*(WoReg*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
+#define REG_PIOB_MDDR      (*(WoReg*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
+#define REG_PIOB_MDSR      (*(RoReg*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
+#define REG_PIOB_PUDR      (*(WoReg*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
+#define REG_PIOB_PUER      (*(WoReg*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
+#define REG_PIOB_PUSR      (*(RoReg*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
+#define REG_PIOB_ABCDSR    (*(RwReg*)0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */
+#define REG_PIOB_IFSCDR    (*(WoReg*)0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
+#define REG_PIOB_IFSCER    (*(WoReg*)0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
+#define REG_PIOB_IFSCSR    (*(RoReg*)0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
+#define REG_PIOB_SCDR      (*(RwReg*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
+#define REG_PIOB_PPDDR     (*(WoReg*)0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */
+#define REG_PIOB_PPDER     (*(WoReg*)0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */
+#define REG_PIOB_PPDSR     (*(RoReg*)0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */
+#define REG_PIOB_OWER      (*(WoReg*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
+#define REG_PIOB_OWDR      (*(WoReg*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
+#define REG_PIOB_OWSR      (*(RoReg*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
+#define REG_PIOB_AIMER     (*(WoReg*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
+#define REG_PIOB_AIMDR     (*(WoReg*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
+#define REG_PIOB_AIMMR     (*(RoReg*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
+#define REG_PIOB_ESR       (*(WoReg*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
+#define REG_PIOB_LSR       (*(WoReg*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */
+#define REG_PIOB_ELSR      (*(RoReg*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
+#define REG_PIOB_FELLSR    (*(WoReg*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
+#define REG_PIOB_REHLSR    (*(WoReg*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
+#define REG_PIOB_FRLHSR    (*(RoReg*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
+#define REG_PIOB_LOCKSR    (*(RoReg*)0x400E10E0U) /**< \brief (PIOB) Lock Status */
+#define REG_PIOB_WPMR      (*(RwReg*)0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
+#define REG_PIOB_WPSR      (*(RoReg*)0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
+#define REG_PIOB_SCHMITT   (*(RwReg*)0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3N_PIOB_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_pioc.h b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_pioc.h
new file mode 100644
index 000000000..c684e8013
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_pioc.h
@@ -0,0 +1,132 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_PIOC_INSTANCE_
+#define _SAM3N_PIOC_INSTANCE_
+
+/* ========== Register definition for PIOC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PIOC_PER                (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
+#define REG_PIOC_PDR                (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
+#define REG_PIOC_PSR                (0x400E1208U) /**< \brief (PIOC) PIO Status Register */
+#define REG_PIOC_OER                (0x400E1210U) /**< \brief (PIOC) Output Enable Register */
+#define REG_PIOC_ODR                (0x400E1214U) /**< \brief (PIOC) Output Disable Register */
+#define REG_PIOC_OSR                (0x400E1218U) /**< \brief (PIOC) Output Status Register */
+#define REG_PIOC_IFER               (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
+#define REG_PIOC_IFDR               (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
+#define REG_PIOC_IFSR               (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
+#define REG_PIOC_SODR               (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
+#define REG_PIOC_CODR               (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
+#define REG_PIOC_ODSR               (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
+#define REG_PIOC_PDSR               (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
+#define REG_PIOC_IER                (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
+#define REG_PIOC_IDR                (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
+#define REG_PIOC_IMR                (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
+#define REG_PIOC_ISR                (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
+#define REG_PIOC_MDER               (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
+#define REG_PIOC_MDDR               (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
+#define REG_PIOC_MDSR               (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
+#define REG_PIOC_PUDR               (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
+#define REG_PIOC_PUER               (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
+#define REG_PIOC_PUSR               (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
+#define REG_PIOC_ABCDSR             (0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */
+#define REG_PIOC_IFSCDR             (0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
+#define REG_PIOC_IFSCER             (0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
+#define REG_PIOC_IFSCSR             (0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
+#define REG_PIOC_SCDR               (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
+#define REG_PIOC_PPDDR              (0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */
+#define REG_PIOC_PPDER              (0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */
+#define REG_PIOC_PPDSR              (0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */
+#define REG_PIOC_OWER               (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
+#define REG_PIOC_OWDR               (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
+#define REG_PIOC_OWSR               (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
+#define REG_PIOC_AIMER              (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
+#define REG_PIOC_AIMDR              (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
+#define REG_PIOC_AIMMR              (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
+#define REG_PIOC_ESR                (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
+#define REG_PIOC_LSR                (0x400E12C4U) /**< \brief (PIOC) Level Select Register */
+#define REG_PIOC_ELSR               (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
+#define REG_PIOC_FELLSR             (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
+#define REG_PIOC_REHLSR             (0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
+#define REG_PIOC_FRLHSR             (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
+#define REG_PIOC_LOCKSR             (0x400E12E0U) /**< \brief (PIOC) Lock Status */
+#define REG_PIOC_WPMR               (0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
+#define REG_PIOC_WPSR               (0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
+#define REG_PIOC_SCHMITT            (0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */
+#else
+#define REG_PIOC_PER       (*(WoReg*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
+#define REG_PIOC_PDR       (*(WoReg*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
+#define REG_PIOC_PSR       (*(RoReg*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */
+#define REG_PIOC_OER       (*(WoReg*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */
+#define REG_PIOC_ODR       (*(WoReg*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */
+#define REG_PIOC_OSR       (*(RoReg*)0x400E1218U) /**< \brief (PIOC) Output Status Register */
+#define REG_PIOC_IFER      (*(WoReg*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
+#define REG_PIOC_IFDR      (*(WoReg*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
+#define REG_PIOC_IFSR      (*(RoReg*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
+#define REG_PIOC_SODR      (*(WoReg*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
+#define REG_PIOC_CODR      (*(WoReg*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
+#define REG_PIOC_ODSR      (*(RwReg*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
+#define REG_PIOC_PDSR      (*(RoReg*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
+#define REG_PIOC_IER       (*(WoReg*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
+#define REG_PIOC_IDR       (*(WoReg*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
+#define REG_PIOC_IMR       (*(RoReg*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
+#define REG_PIOC_ISR       (*(RoReg*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
+#define REG_PIOC_MDER      (*(WoReg*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
+#define REG_PIOC_MDDR      (*(WoReg*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
+#define REG_PIOC_MDSR      (*(RoReg*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
+#define REG_PIOC_PUDR      (*(WoReg*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
+#define REG_PIOC_PUER      (*(WoReg*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
+#define REG_PIOC_PUSR      (*(RoReg*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
+#define REG_PIOC_ABCDSR    (*(RwReg*)0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */
+#define REG_PIOC_IFSCDR    (*(WoReg*)0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
+#define REG_PIOC_IFSCER    (*(WoReg*)0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
+#define REG_PIOC_IFSCSR    (*(RoReg*)0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
+#define REG_PIOC_SCDR      (*(RwReg*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
+#define REG_PIOC_PPDDR     (*(WoReg*)0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */
+#define REG_PIOC_PPDER     (*(WoReg*)0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */
+#define REG_PIOC_PPDSR     (*(RoReg*)0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */
+#define REG_PIOC_OWER      (*(WoReg*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
+#define REG_PIOC_OWDR      (*(WoReg*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
+#define REG_PIOC_OWSR      (*(RoReg*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
+#define REG_PIOC_AIMER     (*(WoReg*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
+#define REG_PIOC_AIMDR     (*(WoReg*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
+#define REG_PIOC_AIMMR     (*(RoReg*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
+#define REG_PIOC_ESR       (*(WoReg*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
+#define REG_PIOC_LSR       (*(WoReg*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */
+#define REG_PIOC_ELSR      (*(RoReg*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
+#define REG_PIOC_FELLSR    (*(WoReg*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
+#define REG_PIOC_REHLSR    (*(WoReg*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
+#define REG_PIOC_FRLHSR    (*(RoReg*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
+#define REG_PIOC_LOCKSR    (*(RoReg*)0x400E12E0U) /**< \brief (PIOC) Lock Status */
+#define REG_PIOC_WPMR      (*(RwReg*)0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
+#define REG_PIOC_WPSR      (*(RoReg*)0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
+#define REG_PIOC_SCHMITT   (*(RwReg*)0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3N_PIOC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_pmc.h b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_pmc.h
new file mode 100644
index 000000000..8dfd17247
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_pmc.h
@@ -0,0 +1,78 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_PMC_INSTANCE_
+#define _SAM3N_PMC_INSTANCE_
+
+/* ========== Register definition for PMC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PMC_SCER            (0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
+#define REG_PMC_SCDR            (0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
+#define REG_PMC_SCSR            (0x400E0408U) /**< \brief (PMC) System Clock Status Register */
+#define REG_PMC_PCER0           (0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
+#define REG_PMC_PCDR0           (0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
+#define REG_PMC_PCSR0           (0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
+#define REG_CKGR_MOR            (0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
+#define REG_CKGR_MCFR           (0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
+#define REG_CKGR_PLLAR          (0x400E0428U) /**< \brief (PMC) PLLA Register */
+#define REG_PMC_MCKR            (0x400E0430U) /**< \brief (PMC) Master Clock Register */
+#define REG_PMC_PCK             (0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
+#define REG_PMC_IER             (0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
+#define REG_PMC_IDR             (0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
+#define REG_PMC_SR              (0x400E0468U) /**< \brief (PMC) Status Register */
+#define REG_PMC_IMR             (0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
+#define REG_PMC_FSMR            (0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
+#define REG_PMC_FSPR            (0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
+#define REG_PMC_FOCR            (0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
+#define REG_PMC_WPMR            (0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
+#define REG_PMC_WPSR            (0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
+#else
+#define REG_PMC_SCER   (*(WoReg*)0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
+#define REG_PMC_SCDR   (*(WoReg*)0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
+#define REG_PMC_SCSR   (*(RoReg*)0x400E0408U) /**< \brief (PMC) System Clock Status Register */
+#define REG_PMC_PCER0  (*(WoReg*)0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
+#define REG_PMC_PCDR0  (*(WoReg*)0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
+#define REG_PMC_PCSR0  (*(RoReg*)0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
+#define REG_CKGR_MOR   (*(RwReg*)0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
+#define REG_CKGR_MCFR  (*(RoReg*)0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
+#define REG_CKGR_PLLAR (*(RwReg*)0x400E0428U) /**< \brief (PMC) PLLA Register */
+#define REG_PMC_MCKR   (*(RwReg*)0x400E0430U) /**< \brief (PMC) Master Clock Register */
+#define REG_PMC_PCK    (*(RwReg*)0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
+#define REG_PMC_IER    (*(WoReg*)0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
+#define REG_PMC_IDR    (*(WoReg*)0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
+#define REG_PMC_SR     (*(RoReg*)0x400E0468U) /**< \brief (PMC) Status Register */
+#define REG_PMC_IMR    (*(RoReg*)0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
+#define REG_PMC_FSMR   (*(RwReg*)0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
+#define REG_PMC_FSPR   (*(RwReg*)0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
+#define REG_PMC_FOCR   (*(WoReg*)0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
+#define REG_PMC_WPMR   (*(RwReg*)0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
+#define REG_PMC_WPSR   (*(RoReg*)0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3N_PMC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_pwm.h b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_pwm.h
new file mode 100644
index 000000000..53aec885c
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_pwm.h
@@ -0,0 +1,94 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_PWM_INSTANCE_
+#define _SAM3N_PWM_INSTANCE_
+
+/* ========== Register definition for PWM peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PWM_MR             (0x40020000U) /**< \brief (PWM) PWM Mode Register */
+#define REG_PWM_ENA            (0x40020004U) /**< \brief (PWM) PWM Enable Register */
+#define REG_PWM_DIS            (0x40020008U) /**< \brief (PWM) PWM Disable Register */
+#define REG_PWM_SR             (0x4002000CU) /**< \brief (PWM) PWM Status Register */
+#define REG_PWM_IER            (0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register */
+#define REG_PWM_IDR            (0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register */
+#define REG_PWM_IMR            (0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register */
+#define REG_PWM_ISR            (0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register */
+#define REG_PWM_CMR0           (0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
+#define REG_PWM_CDTY0          (0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
+#define REG_PWM_CPRD0          (0x40020208U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
+#define REG_PWM_CCNT0          (0x4002020CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
+#define REG_PWM_CUPD0          (0x40020210U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 0) */
+#define REG_PWM_CMR1           (0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
+#define REG_PWM_CDTY1          (0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
+#define REG_PWM_CPRD1          (0x40020228U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
+#define REG_PWM_CCNT1          (0x4002022CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
+#define REG_PWM_CUPD1          (0x40020230U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 1) */
+#define REG_PWM_CMR2           (0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
+#define REG_PWM_CDTY2          (0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
+#define REG_PWM_CPRD2          (0x40020248U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
+#define REG_PWM_CCNT2          (0x4002024CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
+#define REG_PWM_CUPD2          (0x40020250U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 2) */
+#define REG_PWM_CMR3           (0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
+#define REG_PWM_CDTY3          (0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
+#define REG_PWM_CPRD3          (0x40020268U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
+#define REG_PWM_CCNT3          (0x4002026CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
+#define REG_PWM_CUPD3          (0x40020270U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 3) */
+#else
+#define REG_PWM_MR    (*(RwReg*)0x40020000U) /**< \brief (PWM) PWM Mode Register */
+#define REG_PWM_ENA   (*(WoReg*)0x40020004U) /**< \brief (PWM) PWM Enable Register */
+#define REG_PWM_DIS   (*(WoReg*)0x40020008U) /**< \brief (PWM) PWM Disable Register */
+#define REG_PWM_SR    (*(RoReg*)0x4002000CU) /**< \brief (PWM) PWM Status Register */
+#define REG_PWM_IER   (*(WoReg*)0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register */
+#define REG_PWM_IDR   (*(WoReg*)0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register */
+#define REG_PWM_IMR   (*(RoReg*)0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register */
+#define REG_PWM_ISR   (*(RoReg*)0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register */
+#define REG_PWM_CMR0  (*(RwReg*)0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
+#define REG_PWM_CDTY0 (*(RwReg*)0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
+#define REG_PWM_CPRD0 (*(RwReg*)0x40020208U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
+#define REG_PWM_CCNT0 (*(RoReg*)0x4002020CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
+#define REG_PWM_CUPD0 (*(WoReg*)0x40020210U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 0) */
+#define REG_PWM_CMR1  (*(RwReg*)0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
+#define REG_PWM_CDTY1 (*(RwReg*)0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
+#define REG_PWM_CPRD1 (*(RwReg*)0x40020228U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
+#define REG_PWM_CCNT1 (*(RoReg*)0x4002022CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
+#define REG_PWM_CUPD1 (*(WoReg*)0x40020230U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 1) */
+#define REG_PWM_CMR2  (*(RwReg*)0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
+#define REG_PWM_CDTY2 (*(RwReg*)0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
+#define REG_PWM_CPRD2 (*(RwReg*)0x40020248U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
+#define REG_PWM_CCNT2 (*(RoReg*)0x4002024CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
+#define REG_PWM_CUPD2 (*(WoReg*)0x40020250U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 2) */
+#define REG_PWM_CMR3  (*(RwReg*)0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
+#define REG_PWM_CDTY3 (*(RwReg*)0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
+#define REG_PWM_CPRD3 (*(RwReg*)0x40020268U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
+#define REG_PWM_CCNT3 (*(RoReg*)0x4002026CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
+#define REG_PWM_CUPD3 (*(WoReg*)0x40020270U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 3) */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3N_PWM_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_rstc.h b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_rstc.h
new file mode 100644
index 000000000..6feb7e70b
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_rstc.h
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_RSTC_INSTANCE_
+#define _SAM3N_RSTC_INSTANCE_
+
+/* ========== Register definition for RSTC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_RSTC_CR          (0x400E1400U) /**< \brief (RSTC) Control Register */
+#define REG_RSTC_SR          (0x400E1404U) /**< \brief (RSTC) Status Register */
+#define REG_RSTC_MR          (0x400E1408U) /**< \brief (RSTC) Mode Register */
+#else
+#define REG_RSTC_CR (*(WoReg*)0x400E1400U) /**< \brief (RSTC) Control Register */
+#define REG_RSTC_SR (*(RoReg*)0x400E1404U) /**< \brief (RSTC) Status Register */
+#define REG_RSTC_MR (*(RwReg*)0x400E1408U) /**< \brief (RSTC) Mode Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3N_RSTC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_rtc.h b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_rtc.h
new file mode 100644
index 000000000..9af94a706
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_rtc.h
@@ -0,0 +1,64 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_RTC_INSTANCE_
+#define _SAM3N_RTC_INSTANCE_
+
+/* ========== Register definition for RTC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_RTC_CR              (0x400E1460U) /**< \brief (RTC) Control Register */
+#define REG_RTC_MR              (0x400E1464U) /**< \brief (RTC) Mode Register */
+#define REG_RTC_TIMR            (0x400E1468U) /**< \brief (RTC) Time Register */
+#define REG_RTC_CALR            (0x400E146CU) /**< \brief (RTC) Calendar Register */
+#define REG_RTC_TIMALR          (0x400E1470U) /**< \brief (RTC) Time Alarm Register */
+#define REG_RTC_CALALR          (0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */
+#define REG_RTC_SR              (0x400E1478U) /**< \brief (RTC) Status Register */
+#define REG_RTC_SCCR            (0x400E147CU) /**< \brief (RTC) Status Clear Command Register */
+#define REG_RTC_IER             (0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */
+#define REG_RTC_IDR             (0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */
+#define REG_RTC_IMR             (0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */
+#define REG_RTC_VER             (0x400E148CU) /**< \brief (RTC) Valid Entry Register */
+#define REG_RTC_WPMR            (0x400E1544U) /**< \brief (RTC) Write Protect Mode Register */
+#else
+#define REG_RTC_CR     (*(RwReg*)0x400E1460U) /**< \brief (RTC) Control Register */
+#define REG_RTC_MR     (*(RwReg*)0x400E1464U) /**< \brief (RTC) Mode Register */
+#define REG_RTC_TIMR   (*(RwReg*)0x400E1468U) /**< \brief (RTC) Time Register */
+#define REG_RTC_CALR   (*(RwReg*)0x400E146CU) /**< \brief (RTC) Calendar Register */
+#define REG_RTC_TIMALR (*(RwReg*)0x400E1470U) /**< \brief (RTC) Time Alarm Register */
+#define REG_RTC_CALALR (*(RwReg*)0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */
+#define REG_RTC_SR     (*(RoReg*)0x400E1478U) /**< \brief (RTC) Status Register */
+#define REG_RTC_SCCR   (*(WoReg*)0x400E147CU) /**< \brief (RTC) Status Clear Command Register */
+#define REG_RTC_IER    (*(WoReg*)0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */
+#define REG_RTC_IDR    (*(WoReg*)0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */
+#define REG_RTC_IMR    (*(RoReg*)0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */
+#define REG_RTC_VER    (*(RoReg*)0x400E148CU) /**< \brief (RTC) Valid Entry Register */
+#define REG_RTC_WPMR   (*(RwReg*)0x400E1544U) /**< \brief (RTC) Write Protect Mode Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3N_RTC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_rtt.h b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_rtt.h
new file mode 100644
index 000000000..ef32565c9
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_rtt.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_RTT_INSTANCE_
+#define _SAM3N_RTT_INSTANCE_
+
+/* ========== Register definition for RTT peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_RTT_MR          (0x400E1430U) /**< \brief (RTT) Mode Register */
+#define REG_RTT_AR          (0x400E1434U) /**< \brief (RTT) Alarm Register */
+#define REG_RTT_VR          (0x400E1438U) /**< \brief (RTT) Value Register */
+#define REG_RTT_SR          (0x400E143CU) /**< \brief (RTT) Status Register */
+#else
+#define REG_RTT_MR (*(RwReg*)0x400E1430U) /**< \brief (RTT) Mode Register */
+#define REG_RTT_AR (*(RwReg*)0x400E1434U) /**< \brief (RTT) Alarm Register */
+#define REG_RTT_VR (*(RoReg*)0x400E1438U) /**< \brief (RTT) Value Register */
+#define REG_RTT_SR (*(RoReg*)0x400E143CU) /**< \brief (RTT) Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3N_RTT_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_spi.h b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_spi.h
new file mode 100644
index 000000000..659e194f8
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_spi.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_SPI_INSTANCE_
+#define _SAM3N_SPI_INSTANCE_
+
+/* ========== Register definition for SPI peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_SPI_CR              (0x40008000U) /**< \brief (SPI) Control Register */
+#define REG_SPI_MR              (0x40008004U) /**< \brief (SPI) Mode Register */
+#define REG_SPI_RDR             (0x40008008U) /**< \brief (SPI) Receive Data Register */
+#define REG_SPI_TDR             (0x4000800CU) /**< \brief (SPI) Transmit Data Register */
+#define REG_SPI_SR              (0x40008010U) /**< \brief (SPI) Status Register */
+#define REG_SPI_IER             (0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
+#define REG_SPI_IDR             (0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
+#define REG_SPI_IMR             (0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
+#define REG_SPI_CSR             (0x40008030U) /**< \brief (SPI) Chip Select Register */
+#define REG_SPI_WPMR            (0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
+#define REG_SPI_WPSR            (0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
+#define REG_SPI_RPR             (0x40008100U) /**< \brief (SPI) Receive Pointer Register */
+#define REG_SPI_RCR             (0x40008104U) /**< \brief (SPI) Receive Counter Register */
+#define REG_SPI_TPR             (0x40008108U) /**< \brief (SPI) Transmit Pointer Register */
+#define REG_SPI_TCR             (0x4000810CU) /**< \brief (SPI) Transmit Counter Register */
+#define REG_SPI_RNPR            (0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */
+#define REG_SPI_RNCR            (0x40008114U) /**< \brief (SPI) Receive Next Counter Register */
+#define REG_SPI_TNPR            (0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */
+#define REG_SPI_TNCR            (0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */
+#define REG_SPI_PTCR            (0x40008120U) /**< \brief (SPI) Transfer Control Register */
+#define REG_SPI_PTSR            (0x40008124U) /**< \brief (SPI) Transfer Status Register */
+#else
+#define REG_SPI_CR     (*(WoReg*)0x40008000U) /**< \brief (SPI) Control Register */
+#define REG_SPI_MR     (*(RwReg*)0x40008004U) /**< \brief (SPI) Mode Register */
+#define REG_SPI_RDR    (*(RoReg*)0x40008008U) /**< \brief (SPI) Receive Data Register */
+#define REG_SPI_TDR    (*(WoReg*)0x4000800CU) /**< \brief (SPI) Transmit Data Register */
+#define REG_SPI_SR     (*(RoReg*)0x40008010U) /**< \brief (SPI) Status Register */
+#define REG_SPI_IER    (*(WoReg*)0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
+#define REG_SPI_IDR    (*(WoReg*)0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
+#define REG_SPI_IMR    (*(RoReg*)0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
+#define REG_SPI_CSR    (*(RwReg*)0x40008030U) /**< \brief (SPI) Chip Select Register */
+#define REG_SPI_WPMR   (*(RwReg*)0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
+#define REG_SPI_WPSR   (*(RoReg*)0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
+#define REG_SPI_RPR    (*(RwReg*)0x40008100U) /**< \brief (SPI) Receive Pointer Register */
+#define REG_SPI_RCR    (*(RwReg*)0x40008104U) /**< \brief (SPI) Receive Counter Register */
+#define REG_SPI_TPR    (*(RwReg*)0x40008108U) /**< \brief (SPI) Transmit Pointer Register */
+#define REG_SPI_TCR    (*(RwReg*)0x4000810CU) /**< \brief (SPI) Transmit Counter Register */
+#define REG_SPI_RNPR   (*(RwReg*)0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */
+#define REG_SPI_RNCR   (*(RwReg*)0x40008114U) /**< \brief (SPI) Receive Next Counter Register */
+#define REG_SPI_TNPR   (*(RwReg*)0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */
+#define REG_SPI_TNCR   (*(RwReg*)0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */
+#define REG_SPI_PTCR   (*(WoReg*)0x40008120U) /**< \brief (SPI) Transfer Control Register */
+#define REG_SPI_PTSR   (*(RoReg*)0x40008124U) /**< \brief (SPI) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3N_SPI_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_supc.h b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_supc.h
new file mode 100644
index 000000000..bb743121a
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_supc.h
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_SUPC_INSTANCE_
+#define _SAM3N_SUPC_INSTANCE_
+
+/* ========== Register definition for SUPC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_SUPC_CR            (0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */
+#define REG_SUPC_SMMR          (0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
+#define REG_SUPC_MR            (0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */
+#define REG_SUPC_WUMR          (0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
+#define REG_SUPC_WUIR          (0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
+#define REG_SUPC_SR            (0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */
+#else
+#define REG_SUPC_CR   (*(WoReg*)0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */
+#define REG_SUPC_SMMR (*(RwReg*)0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
+#define REG_SUPC_MR   (*(RwReg*)0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */
+#define REG_SUPC_WUMR (*(RwReg*)0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
+#define REG_SUPC_WUIR (*(RwReg*)0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
+#define REG_SUPC_SR   (*(RoReg*)0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3N_SUPC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_tc0.h b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_tc0.h
new file mode 100644
index 000000000..223ff6070
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_tc0.h
@@ -0,0 +1,118 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_TC0_INSTANCE_
+#define _SAM3N_TC0_INSTANCE_
+
+/* ========== Register definition for TC0 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_TC0_CCR0           (0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
+#define REG_TC0_CMR0           (0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
+#define REG_TC0_SMMR0          (0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC0_CV0            (0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */
+#define REG_TC0_RA0            (0x40010014U) /**< \brief (TC0) Register A (channel = 0) */
+#define REG_TC0_RB0            (0x40010018U) /**< \brief (TC0) Register B (channel = 0) */
+#define REG_TC0_RC0            (0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */
+#define REG_TC0_SR0            (0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */
+#define REG_TC0_IER0           (0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
+#define REG_TC0_IDR0           (0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
+#define REG_TC0_IMR0           (0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
+#define REG_TC0_CCR1           (0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
+#define REG_TC0_CMR1           (0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
+#define REG_TC0_SMMR1          (0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC0_CV1            (0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */
+#define REG_TC0_RA1            (0x40010054U) /**< \brief (TC0) Register A (channel = 1) */
+#define REG_TC0_RB1            (0x40010058U) /**< \brief (TC0) Register B (channel = 1) */
+#define REG_TC0_RC1            (0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */
+#define REG_TC0_SR1            (0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */
+#define REG_TC0_IER1           (0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
+#define REG_TC0_IDR1           (0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
+#define REG_TC0_IMR1           (0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
+#define REG_TC0_CCR2           (0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
+#define REG_TC0_CMR2           (0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
+#define REG_TC0_SMMR2          (0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC0_CV2            (0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */
+#define REG_TC0_RA2            (0x40010094U) /**< \brief (TC0) Register A (channel = 2) */
+#define REG_TC0_RB2            (0x40010098U) /**< \brief (TC0) Register B (channel = 2) */
+#define REG_TC0_RC2            (0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */
+#define REG_TC0_SR2            (0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */
+#define REG_TC0_IER2           (0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
+#define REG_TC0_IDR2           (0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
+#define REG_TC0_IMR2           (0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
+#define REG_TC0_BCR            (0x400100C0U) /**< \brief (TC0) Block Control Register */
+#define REG_TC0_BMR            (0x400100C4U) /**< \brief (TC0) Block Mode Register */
+#define REG_TC0_QIER           (0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
+#define REG_TC0_QIDR           (0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
+#define REG_TC0_QIMR           (0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
+#define REG_TC0_QISR           (0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
+#define REG_TC0_WPMR           (0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */
+#else
+#define REG_TC0_CCR0  (*(WoReg*)0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
+#define REG_TC0_CMR0  (*(RwReg*)0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
+#define REG_TC0_SMMR0 (*(RwReg*)0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC0_CV0   (*(RoReg*)0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */
+#define REG_TC0_RA0   (*(RwReg*)0x40010014U) /**< \brief (TC0) Register A (channel = 0) */
+#define REG_TC0_RB0   (*(RwReg*)0x40010018U) /**< \brief (TC0) Register B (channel = 0) */
+#define REG_TC0_RC0   (*(RwReg*)0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */
+#define REG_TC0_SR0   (*(RoReg*)0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */
+#define REG_TC0_IER0  (*(WoReg*)0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
+#define REG_TC0_IDR0  (*(WoReg*)0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
+#define REG_TC0_IMR0  (*(RoReg*)0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
+#define REG_TC0_CCR1  (*(WoReg*)0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
+#define REG_TC0_CMR1  (*(RwReg*)0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
+#define REG_TC0_SMMR1 (*(RwReg*)0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC0_CV1   (*(RoReg*)0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */
+#define REG_TC0_RA1   (*(RwReg*)0x40010054U) /**< \brief (TC0) Register A (channel = 1) */
+#define REG_TC0_RB1   (*(RwReg*)0x40010058U) /**< \brief (TC0) Register B (channel = 1) */
+#define REG_TC0_RC1   (*(RwReg*)0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */
+#define REG_TC0_SR1   (*(RoReg*)0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */
+#define REG_TC0_IER1  (*(WoReg*)0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
+#define REG_TC0_IDR1  (*(WoReg*)0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
+#define REG_TC0_IMR1  (*(RoReg*)0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
+#define REG_TC0_CCR2  (*(WoReg*)0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
+#define REG_TC0_CMR2  (*(RwReg*)0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
+#define REG_TC0_SMMR2 (*(RwReg*)0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC0_CV2   (*(RoReg*)0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */
+#define REG_TC0_RA2   (*(RwReg*)0x40010094U) /**< \brief (TC0) Register A (channel = 2) */
+#define REG_TC0_RB2   (*(RwReg*)0x40010098U) /**< \brief (TC0) Register B (channel = 2) */
+#define REG_TC0_RC2   (*(RwReg*)0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */
+#define REG_TC0_SR2   (*(RoReg*)0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */
+#define REG_TC0_IER2  (*(WoReg*)0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
+#define REG_TC0_IDR2  (*(WoReg*)0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
+#define REG_TC0_IMR2  (*(RoReg*)0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
+#define REG_TC0_BCR   (*(WoReg*)0x400100C0U) /**< \brief (TC0) Block Control Register */
+#define REG_TC0_BMR   (*(RwReg*)0x400100C4U) /**< \brief (TC0) Block Mode Register */
+#define REG_TC0_QIER  (*(WoReg*)0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
+#define REG_TC0_QIDR  (*(WoReg*)0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
+#define REG_TC0_QIMR  (*(RoReg*)0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
+#define REG_TC0_QISR  (*(RoReg*)0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
+#define REG_TC0_WPMR  (*(RwReg*)0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3N_TC0_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_tc1.h b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_tc1.h
new file mode 100644
index 000000000..819faebc6
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_tc1.h
@@ -0,0 +1,118 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_TC1_INSTANCE_
+#define _SAM3N_TC1_INSTANCE_
+
+/* ========== Register definition for TC1 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_TC1_CCR0           (0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
+#define REG_TC1_CMR0           (0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
+#define REG_TC1_SMMR0          (0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC1_CV0            (0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */
+#define REG_TC1_RA0            (0x40014014U) /**< \brief (TC1) Register A (channel = 0) */
+#define REG_TC1_RB0            (0x40014018U) /**< \brief (TC1) Register B (channel = 0) */
+#define REG_TC1_RC0            (0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */
+#define REG_TC1_SR0            (0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */
+#define REG_TC1_IER0           (0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
+#define REG_TC1_IDR0           (0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
+#define REG_TC1_IMR0           (0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
+#define REG_TC1_CCR1           (0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
+#define REG_TC1_CMR1           (0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
+#define REG_TC1_SMMR1          (0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC1_CV1            (0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */
+#define REG_TC1_RA1            (0x40014054U) /**< \brief (TC1) Register A (channel = 1) */
+#define REG_TC1_RB1            (0x40014058U) /**< \brief (TC1) Register B (channel = 1) */
+#define REG_TC1_RC1            (0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */
+#define REG_TC1_SR1            (0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */
+#define REG_TC1_IER1           (0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
+#define REG_TC1_IDR1           (0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
+#define REG_TC1_IMR1           (0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
+#define REG_TC1_CCR2           (0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
+#define REG_TC1_CMR2           (0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
+#define REG_TC1_SMMR2          (0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC1_CV2            (0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */
+#define REG_TC1_RA2            (0x40014094U) /**< \brief (TC1) Register A (channel = 2) */
+#define REG_TC1_RB2            (0x40014098U) /**< \brief (TC1) Register B (channel = 2) */
+#define REG_TC1_RC2            (0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */
+#define REG_TC1_SR2            (0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */
+#define REG_TC1_IER2           (0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
+#define REG_TC1_IDR2           (0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
+#define REG_TC1_IMR2           (0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
+#define REG_TC1_BCR            (0x400140C0U) /**< \brief (TC1) Block Control Register */
+#define REG_TC1_BMR            (0x400140C4U) /**< \brief (TC1) Block Mode Register */
+#define REG_TC1_QIER           (0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
+#define REG_TC1_QIDR           (0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
+#define REG_TC1_QIMR           (0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
+#define REG_TC1_QISR           (0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
+#define REG_TC1_WPMR           (0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */
+#else
+#define REG_TC1_CCR0  (*(WoReg*)0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
+#define REG_TC1_CMR0  (*(RwReg*)0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
+#define REG_TC1_SMMR0 (*(RwReg*)0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC1_CV0   (*(RoReg*)0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */
+#define REG_TC1_RA0   (*(RwReg*)0x40014014U) /**< \brief (TC1) Register A (channel = 0) */
+#define REG_TC1_RB0   (*(RwReg*)0x40014018U) /**< \brief (TC1) Register B (channel = 0) */
+#define REG_TC1_RC0   (*(RwReg*)0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */
+#define REG_TC1_SR0   (*(RoReg*)0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */
+#define REG_TC1_IER0  (*(WoReg*)0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
+#define REG_TC1_IDR0  (*(WoReg*)0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
+#define REG_TC1_IMR0  (*(RoReg*)0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
+#define REG_TC1_CCR1  (*(WoReg*)0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
+#define REG_TC1_CMR1  (*(RwReg*)0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
+#define REG_TC1_SMMR1 (*(RwReg*)0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC1_CV1   (*(RoReg*)0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */
+#define REG_TC1_RA1   (*(RwReg*)0x40014054U) /**< \brief (TC1) Register A (channel = 1) */
+#define REG_TC1_RB1   (*(RwReg*)0x40014058U) /**< \brief (TC1) Register B (channel = 1) */
+#define REG_TC1_RC1   (*(RwReg*)0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */
+#define REG_TC1_SR1   (*(RoReg*)0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */
+#define REG_TC1_IER1  (*(WoReg*)0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
+#define REG_TC1_IDR1  (*(WoReg*)0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
+#define REG_TC1_IMR1  (*(RoReg*)0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
+#define REG_TC1_CCR2  (*(WoReg*)0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
+#define REG_TC1_CMR2  (*(RwReg*)0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
+#define REG_TC1_SMMR2 (*(RwReg*)0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC1_CV2   (*(RoReg*)0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */
+#define REG_TC1_RA2   (*(RwReg*)0x40014094U) /**< \brief (TC1) Register A (channel = 2) */
+#define REG_TC1_RB2   (*(RwReg*)0x40014098U) /**< \brief (TC1) Register B (channel = 2) */
+#define REG_TC1_RC2   (*(RwReg*)0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */
+#define REG_TC1_SR2   (*(RoReg*)0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */
+#define REG_TC1_IER2  (*(WoReg*)0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
+#define REG_TC1_IDR2  (*(WoReg*)0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
+#define REG_TC1_IMR2  (*(RoReg*)0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
+#define REG_TC1_BCR   (*(WoReg*)0x400140C0U) /**< \brief (TC1) Block Control Register */
+#define REG_TC1_BMR   (*(RwReg*)0x400140C4U) /**< \brief (TC1) Block Mode Register */
+#define REG_TC1_QIER  (*(WoReg*)0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
+#define REG_TC1_QIDR  (*(WoReg*)0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
+#define REG_TC1_QIMR  (*(RoReg*)0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
+#define REG_TC1_QISR  (*(RoReg*)0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
+#define REG_TC1_WPMR  (*(RwReg*)0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3N_TC1_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_twi0.h b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_twi0.h
new file mode 100644
index 000000000..1bd648e09
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_twi0.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_TWI0_INSTANCE_
+#define _SAM3N_TWI0_INSTANCE_
+
+/* ========== Register definition for TWI0 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_TWI0_CR            (0x40018000U) /**< \brief (TWI0) Control Register */
+#define REG_TWI0_MMR           (0x40018004U) /**< \brief (TWI0) Master Mode Register */
+#define REG_TWI0_SMR           (0x40018008U) /**< \brief (TWI0) Slave Mode Register */
+#define REG_TWI0_IADR          (0x4001800CU) /**< \brief (TWI0) Internal Address Register */
+#define REG_TWI0_CWGR          (0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */
+#define REG_TWI0_SR            (0x40018020U) /**< \brief (TWI0) Status Register */
+#define REG_TWI0_IER           (0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */
+#define REG_TWI0_IDR           (0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */
+#define REG_TWI0_IMR           (0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */
+#define REG_TWI0_RHR           (0x40018030U) /**< \brief (TWI0) Receive Holding Register */
+#define REG_TWI0_THR           (0x40018034U) /**< \brief (TWI0) Transmit Holding Register */
+#define REG_TWI0_RPR           (0x40018100U) /**< \brief (TWI0) Receive Pointer Register */
+#define REG_TWI0_RCR           (0x40018104U) /**< \brief (TWI0) Receive Counter Register */
+#define REG_TWI0_TPR           (0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */
+#define REG_TWI0_TCR           (0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */
+#define REG_TWI0_RNPR          (0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */
+#define REG_TWI0_RNCR          (0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */
+#define REG_TWI0_TNPR          (0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */
+#define REG_TWI0_TNCR          (0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */
+#define REG_TWI0_PTCR          (0x40018120U) /**< \brief (TWI0) Transfer Control Register */
+#define REG_TWI0_PTSR          (0x40018124U) /**< \brief (TWI0) Transfer Status Register */
+#else
+#define REG_TWI0_CR   (*(WoReg*)0x40018000U) /**< \brief (TWI0) Control Register */
+#define REG_TWI0_MMR  (*(RwReg*)0x40018004U) /**< \brief (TWI0) Master Mode Register */
+#define REG_TWI0_SMR  (*(RwReg*)0x40018008U) /**< \brief (TWI0) Slave Mode Register */
+#define REG_TWI0_IADR (*(RwReg*)0x4001800CU) /**< \brief (TWI0) Internal Address Register */
+#define REG_TWI0_CWGR (*(RwReg*)0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */
+#define REG_TWI0_SR   (*(RoReg*)0x40018020U) /**< \brief (TWI0) Status Register */
+#define REG_TWI0_IER  (*(WoReg*)0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */
+#define REG_TWI0_IDR  (*(WoReg*)0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */
+#define REG_TWI0_IMR  (*(RoReg*)0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */
+#define REG_TWI0_RHR  (*(RoReg*)0x40018030U) /**< \brief (TWI0) Receive Holding Register */
+#define REG_TWI0_THR  (*(WoReg*)0x40018034U) /**< \brief (TWI0) Transmit Holding Register */
+#define REG_TWI0_RPR  (*(RwReg*)0x40018100U) /**< \brief (TWI0) Receive Pointer Register */
+#define REG_TWI0_RCR  (*(RwReg*)0x40018104U) /**< \brief (TWI0) Receive Counter Register */
+#define REG_TWI0_TPR  (*(RwReg*)0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */
+#define REG_TWI0_TCR  (*(RwReg*)0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */
+#define REG_TWI0_RNPR (*(RwReg*)0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */
+#define REG_TWI0_RNCR (*(RwReg*)0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */
+#define REG_TWI0_TNPR (*(RwReg*)0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */
+#define REG_TWI0_TNCR (*(RwReg*)0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */
+#define REG_TWI0_PTCR (*(WoReg*)0x40018120U) /**< \brief (TWI0) Transfer Control Register */
+#define REG_TWI0_PTSR (*(RoReg*)0x40018124U) /**< \brief (TWI0) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3N_TWI0_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_twi1.h b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_twi1.h
new file mode 100644
index 000000000..80027043f
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_twi1.h
@@ -0,0 +1,60 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_TWI1_INSTANCE_
+#define _SAM3N_TWI1_INSTANCE_
+
+/* ========== Register definition for TWI1 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_TWI1_CR            (0x4001C000U) /**< \brief (TWI1) Control Register */
+#define REG_TWI1_MMR           (0x4001C004U) /**< \brief (TWI1) Master Mode Register */
+#define REG_TWI1_SMR           (0x4001C008U) /**< \brief (TWI1) Slave Mode Register */
+#define REG_TWI1_IADR          (0x4001C00CU) /**< \brief (TWI1) Internal Address Register */
+#define REG_TWI1_CWGR          (0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */
+#define REG_TWI1_SR            (0x4001C020U) /**< \brief (TWI1) Status Register */
+#define REG_TWI1_IER           (0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */
+#define REG_TWI1_IDR           (0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */
+#define REG_TWI1_IMR           (0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */
+#define REG_TWI1_RHR           (0x4001C030U) /**< \brief (TWI1) Receive Holding Register */
+#define REG_TWI1_THR           (0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */
+#else
+#define REG_TWI1_CR   (*(WoReg*)0x4001C000U) /**< \brief (TWI1) Control Register */
+#define REG_TWI1_MMR  (*(RwReg*)0x4001C004U) /**< \brief (TWI1) Master Mode Register */
+#define REG_TWI1_SMR  (*(RwReg*)0x4001C008U) /**< \brief (TWI1) Slave Mode Register */
+#define REG_TWI1_IADR (*(RwReg*)0x4001C00CU) /**< \brief (TWI1) Internal Address Register */
+#define REG_TWI1_CWGR (*(RwReg*)0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */
+#define REG_TWI1_SR   (*(RoReg*)0x4001C020U) /**< \brief (TWI1) Status Register */
+#define REG_TWI1_IER  (*(WoReg*)0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */
+#define REG_TWI1_IDR  (*(WoReg*)0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */
+#define REG_TWI1_IMR  (*(RoReg*)0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */
+#define REG_TWI1_RHR  (*(RoReg*)0x4001C030U) /**< \brief (TWI1) Receive Holding Register */
+#define REG_TWI1_THR  (*(WoReg*)0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3N_TWI1_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_uart0.h b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_uart0.h
new file mode 100644
index 000000000..8df44997c
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_uart0.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_UART0_INSTANCE_
+#define _SAM3N_UART0_INSTANCE_
+
+/* ========== Register definition for UART0 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_UART0_CR            (0x400E0600U) /**< \brief (UART0) Control Register */
+#define REG_UART0_MR            (0x400E0604U) /**< \brief (UART0) Mode Register */
+#define REG_UART0_IER           (0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */
+#define REG_UART0_IDR           (0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */
+#define REG_UART0_IMR           (0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */
+#define REG_UART0_SR            (0x400E0614U) /**< \brief (UART0) Status Register */
+#define REG_UART0_RHR           (0x400E0618U) /**< \brief (UART0) Receive Holding Register */
+#define REG_UART0_THR           (0x400E061CU) /**< \brief (UART0) Transmit Holding Register */
+#define REG_UART0_BRGR          (0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */
+#define REG_UART0_RPR           (0x400E0700U) /**< \brief (UART0) Receive Pointer Register */
+#define REG_UART0_RCR           (0x400E0704U) /**< \brief (UART0) Receive Counter Register */
+#define REG_UART0_TPR           (0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */
+#define REG_UART0_TCR           (0x400E070CU) /**< \brief (UART0) Transmit Counter Register */
+#define REG_UART0_RNPR          (0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */
+#define REG_UART0_RNCR          (0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */
+#define REG_UART0_TNPR          (0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */
+#define REG_UART0_TNCR          (0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */
+#define REG_UART0_PTCR          (0x400E0720U) /**< \brief (UART0) Transfer Control Register */
+#define REG_UART0_PTSR          (0x400E0724U) /**< \brief (UART0) Transfer Status Register */
+#else
+#define REG_UART0_CR   (*(WoReg*)0x400E0600U) /**< \brief (UART0) Control Register */
+#define REG_UART0_MR   (*(RwReg*)0x400E0604U) /**< \brief (UART0) Mode Register */
+#define REG_UART0_IER  (*(WoReg*)0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */
+#define REG_UART0_IDR  (*(WoReg*)0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */
+#define REG_UART0_IMR  (*(RoReg*)0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */
+#define REG_UART0_SR   (*(RoReg*)0x400E0614U) /**< \brief (UART0) Status Register */
+#define REG_UART0_RHR  (*(RoReg*)0x400E0618U) /**< \brief (UART0) Receive Holding Register */
+#define REG_UART0_THR  (*(WoReg*)0x400E061CU) /**< \brief (UART0) Transmit Holding Register */
+#define REG_UART0_BRGR (*(RwReg*)0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */
+#define REG_UART0_RPR  (*(RwReg*)0x400E0700U) /**< \brief (UART0) Receive Pointer Register */
+#define REG_UART0_RCR  (*(RwReg*)0x400E0704U) /**< \brief (UART0) Receive Counter Register */
+#define REG_UART0_TPR  (*(RwReg*)0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */
+#define REG_UART0_TCR  (*(RwReg*)0x400E070CU) /**< \brief (UART0) Transmit Counter Register */
+#define REG_UART0_RNPR (*(RwReg*)0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */
+#define REG_UART0_RNCR (*(RwReg*)0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */
+#define REG_UART0_TNPR (*(RwReg*)0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */
+#define REG_UART0_TNCR (*(RwReg*)0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */
+#define REG_UART0_PTCR (*(WoReg*)0x400E0720U) /**< \brief (UART0) Transfer Control Register */
+#define REG_UART0_PTSR (*(RoReg*)0x400E0724U) /**< \brief (UART0) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3N_UART0_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_uart1.h b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_uart1.h
new file mode 100644
index 000000000..970f792ec
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_uart1.h
@@ -0,0 +1,56 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_UART1_INSTANCE_
+#define _SAM3N_UART1_INSTANCE_
+
+/* ========== Register definition for UART1 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_UART1_CR            (0x400E0800U) /**< \brief (UART1) Control Register */
+#define REG_UART1_MR            (0x400E0804U) /**< \brief (UART1) Mode Register */
+#define REG_UART1_IER           (0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */
+#define REG_UART1_IDR           (0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */
+#define REG_UART1_IMR           (0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */
+#define REG_UART1_SR            (0x400E0814U) /**< \brief (UART1) Status Register */
+#define REG_UART1_RHR           (0x400E0818U) /**< \brief (UART1) Receive Holding Register */
+#define REG_UART1_THR           (0x400E081CU) /**< \brief (UART1) Transmit Holding Register */
+#define REG_UART1_BRGR          (0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */
+#else
+#define REG_UART1_CR   (*(WoReg*)0x400E0800U) /**< \brief (UART1) Control Register */
+#define REG_UART1_MR   (*(RwReg*)0x400E0804U) /**< \brief (UART1) Mode Register */
+#define REG_UART1_IER  (*(WoReg*)0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */
+#define REG_UART1_IDR  (*(WoReg*)0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */
+#define REG_UART1_IMR  (*(RoReg*)0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */
+#define REG_UART1_SR   (*(RoReg*)0x400E0814U) /**< \brief (UART1) Status Register */
+#define REG_UART1_RHR  (*(RoReg*)0x400E0818U) /**< \brief (UART1) Receive Holding Register */
+#define REG_UART1_THR  (*(WoReg*)0x400E081CU) /**< \brief (UART1) Transmit Holding Register */
+#define REG_UART1_BRGR (*(RwReg*)0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3N_UART1_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_usart0.h b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_usart0.h
new file mode 100644
index 000000000..a974b6af6
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_usart0.h
@@ -0,0 +1,90 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_USART0_INSTANCE_
+#define _SAM3N_USART0_INSTANCE_
+
+/* ========== Register definition for USART0 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_USART0_CR          (0x40024000U) /**< \brief (USART0) Control Register */
+#define REG_USART0_MR          (0x40024004U) /**< \brief (USART0) Mode Register */
+#define REG_USART0_IER          (0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
+#define REG_USART0_IDR          (0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
+#define REG_USART0_IMR          (0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
+#define REG_USART0_CSR          (0x40024014U) /**< \brief (USART0) Channel Status Register */
+#define REG_USART0_RHR          (0x40024018U) /**< \brief (USART0) Receiver Holding Register */
+#define REG_USART0_THR          (0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */
+#define REG_USART0_BRGR          (0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
+#define REG_USART0_RTOR          (0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
+#define REG_USART0_TTGR          (0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
+#define REG_USART0_FIDI          (0x40024040U) /**< \brief (USART0) FI DI Ratio Register */
+#define REG_USART0_NER          (0x40024044U) /**< \brief (USART0) Number of Errors Register */
+#define REG_USART0_IF          (0x4002404CU) /**< \brief (USART0) IrDA Filter Register */
+#define REG_USART0_WPMR          (0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */
+#define REG_USART0_WPSR          (0x400240E8U) /**< \brief (USART0) Write Protect Status Register */
+#define REG_USART0_RPR          (0x40024100U) /**< \brief (USART0) Receive Pointer Register */
+#define REG_USART0_RCR          (0x40024104U) /**< \brief (USART0) Receive Counter Register */
+#define REG_USART0_TPR          (0x40024108U) /**< \brief (USART0) Transmit Pointer Register */
+#define REG_USART0_TCR          (0x4002410CU) /**< \brief (USART0) Transmit Counter Register */
+#define REG_USART0_RNPR          (0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */
+#define REG_USART0_RNCR          (0x40024114U) /**< \brief (USART0) Receive Next Counter Register */
+#define REG_USART0_TNPR          (0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */
+#define REG_USART0_TNCR          (0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */
+#define REG_USART0_PTCR          (0x40024120U) /**< \brief (USART0) Transfer Control Register */
+#define REG_USART0_PTSR          (0x40024124U) /**< \brief (USART0) Transfer Status Register */
+#else
+#define REG_USART0_CR (*(WoReg*)0x40024000U) /**< \brief (USART0) Control Register */
+#define REG_USART0_MR (*(RwReg*)0x40024004U) /**< \brief (USART0) Mode Register */
+#define REG_USART0_IER (*(WoReg*)0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
+#define REG_USART0_IDR (*(WoReg*)0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
+#define REG_USART0_IMR (*(RoReg*)0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
+#define REG_USART0_CSR (*(RoReg*)0x40024014U) /**< \brief (USART0) Channel Status Register */
+#define REG_USART0_RHR (*(RoReg*)0x40024018U) /**< \brief (USART0) Receiver Holding Register */
+#define REG_USART0_THR (*(WoReg*)0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */
+#define REG_USART0_BRGR (*(RwReg*)0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
+#define REG_USART0_RTOR (*(RwReg*)0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
+#define REG_USART0_TTGR (*(RwReg*)0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
+#define REG_USART0_FIDI (*(RwReg*)0x40024040U) /**< \brief (USART0) FI DI Ratio Register */
+#define REG_USART0_NER (*(RoReg*)0x40024044U) /**< \brief (USART0) Number of Errors Register */
+#define REG_USART0_IF (*(RwReg*)0x4002404CU) /**< \brief (USART0) IrDA Filter Register */
+#define REG_USART0_WPMR (*(RwReg*)0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */
+#define REG_USART0_WPSR (*(RoReg*)0x400240E8U) /**< \brief (USART0) Write Protect Status Register */
+#define REG_USART0_RPR (*(RwReg*)0x40024100U) /**< \brief (USART0) Receive Pointer Register */
+#define REG_USART0_RCR (*(RwReg*)0x40024104U) /**< \brief (USART0) Receive Counter Register */
+#define REG_USART0_TPR (*(RwReg*)0x40024108U) /**< \brief (USART0) Transmit Pointer Register */
+#define REG_USART0_TCR (*(RwReg*)0x4002410CU) /**< \brief (USART0) Transmit Counter Register */
+#define REG_USART0_RNPR (*(RwReg*)0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */
+#define REG_USART0_RNCR (*(RwReg*)0x40024114U) /**< \brief (USART0) Receive Next Counter Register */
+#define REG_USART0_TNPR (*(RwReg*)0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */
+#define REG_USART0_TNCR (*(RwReg*)0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */
+#define REG_USART0_PTCR (*(WoReg*)0x40024120U) /**< \brief (USART0) Transfer Control Register */
+#define REG_USART0_PTSR (*(RoReg*)0x40024124U) /**< \brief (USART0) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3N_USART0_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_usart1.h b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_usart1.h
new file mode 100644
index 000000000..cf49ff402
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_usart1.h
@@ -0,0 +1,70 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_USART1_INSTANCE_
+#define _SAM3N_USART1_INSTANCE_
+
+/* ========== Register definition for USART1 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_USART1_CR          (0x40028000U) /**< \brief (USART1) Control Register */
+#define REG_USART1_MR          (0x40028004U) /**< \brief (USART1) Mode Register */
+#define REG_USART1_IER          (0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
+#define REG_USART1_IDR          (0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
+#define REG_USART1_IMR          (0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
+#define REG_USART1_CSR          (0x40028014U) /**< \brief (USART1) Channel Status Register */
+#define REG_USART1_RHR          (0x40028018U) /**< \brief (USART1) Receiver Holding Register */
+#define REG_USART1_THR          (0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */
+#define REG_USART1_BRGR          (0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
+#define REG_USART1_RTOR          (0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
+#define REG_USART1_TTGR          (0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
+#define REG_USART1_FIDI          (0x40028040U) /**< \brief (USART1) FI DI Ratio Register */
+#define REG_USART1_NER          (0x40028044U) /**< \brief (USART1) Number of Errors Register */
+#define REG_USART1_IF          (0x4002804CU) /**< \brief (USART1) IrDA Filter Register */
+#define REG_USART1_WPMR          (0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */
+#define REG_USART1_WPSR          (0x400280E8U) /**< \brief (USART1) Write Protect Status Register */
+#else
+#define REG_USART1_CR (*(WoReg*)0x40028000U) /**< \brief (USART1) Control Register */
+#define REG_USART1_MR (*(RwReg*)0x40028004U) /**< \brief (USART1) Mode Register */
+#define REG_USART1_IER (*(WoReg*)0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
+#define REG_USART1_IDR (*(WoReg*)0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
+#define REG_USART1_IMR (*(RoReg*)0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
+#define REG_USART1_CSR (*(RoReg*)0x40028014U) /**< \brief (USART1) Channel Status Register */
+#define REG_USART1_RHR (*(RoReg*)0x40028018U) /**< \brief (USART1) Receiver Holding Register */
+#define REG_USART1_THR (*(WoReg*)0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */
+#define REG_USART1_BRGR (*(RwReg*)0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
+#define REG_USART1_RTOR (*(RwReg*)0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
+#define REG_USART1_TTGR (*(RwReg*)0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
+#define REG_USART1_FIDI (*(RwReg*)0x40028040U) /**< \brief (USART1) FI DI Ratio Register */
+#define REG_USART1_NER (*(RoReg*)0x40028044U) /**< \brief (USART1) Number of Errors Register */
+#define REG_USART1_IF (*(RwReg*)0x4002804CU) /**< \brief (USART1) IrDA Filter Register */
+#define REG_USART1_WPMR (*(RwReg*)0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */
+#define REG_USART1_WPSR (*(RoReg*)0x400280E8U) /**< \brief (USART1) Write Protect Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3N_USART1_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_wdt.h b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_wdt.h
new file mode 100644
index 000000000..7dd688377
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/instance/instance_wdt.h
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_WDT_INSTANCE_
+#define _SAM3N_WDT_INSTANCE_
+
+/* ========== Register definition for WDT peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_WDT_CR          (0x400E1450U) /**< \brief (WDT) Control Register */
+#define REG_WDT_MR          (0x400E1454U) /**< \brief (WDT) Mode Register */
+#define REG_WDT_SR          (0x400E1458U) /**< \brief (WDT) Status Register */
+#else
+#define REG_WDT_CR (*(WoReg*)0x400E1450U) /**< \brief (WDT) Control Register */
+#define REG_WDT_MR (*(RwReg*)0x400E1454U) /**< \brief (WDT) Mode Register */
+#define REG_WDT_SR (*(RoReg*)0x400E1458U) /**< \brief (WDT) Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3N_WDT_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n1a.h b/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n1a.h
new file mode 100644
index 000000000..2c8269454
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n1a.h
@@ -0,0 +1,207 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N1A_PIO_
+#define _SAM3N1A_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0    (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1    (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10   (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11   (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12   (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13   (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14   (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PC31X1_AD15   (1u << 31) /**< \brief Adc signal: AD15 */
+#define PIO_PA19X1_AD2    (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9  (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3    (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4     (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5     (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6     (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12  (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7     (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8    (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9    (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG    (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0   (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PA2C_DATRG    (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0     (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0    (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PC16B_PCK0    (1u << 16) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1    (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PC17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2    (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2    (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2     (1u << 3)  /**< \brief Pmc signal: PCK2 */
+#define PIO_PC14B_PCK2    (1u << 14) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PA11B_PWM0    (1u << 11) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA23B_PWM0    (1u << 23) /**< \brief Pwm signal: PWM0 */
+#define PIO_PB0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC8B_PWM0     (1u << 8)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC18B_PWM0    (1u << 18) /**< \brief Pwm signal: PWM0 */
+#define PIO_PC22B_PWM0    (1u << 22) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PA12B_PWM1    (1u << 12) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA24B_PWM1    (1u << 24) /**< \brief Pwm signal: PWM1 */
+#define PIO_PB1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC9B_PWM1     (1u << 9)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC19B_PWM1    (1u << 19) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA2A_PWM2     (1u << 2)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PA13B_PWM2    (1u << 13) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA25B_PWM2    (1u << 25) /**< \brief Pwm signal: PWM2 */
+#define PIO_PB4B_PWM2     (1u << 4)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PC10B_PWM2    (1u << 10) /**< \brief Pwm signal: PWM2 */
+#define PIO_PC20B_PWM2    (1u << 20) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA7B_PWM3     (1u << 7)  /**< \brief Pwm signal: PWM3 */
+#define PIO_PA14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PB14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC11B_PWM3    (1u << 11) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC21B_PWM3    (1u << 21) /**< \brief Pwm signal: PWM3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO    (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI    (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0   (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1    (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1   (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1   (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1    (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2   (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2   (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2    (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC7B_NPCS2    (1u << 7)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3    (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3   (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK    (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0    (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1   (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2   (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0    (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1   (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2   (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0    (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1   (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2   (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0    (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0     (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1    (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1     (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0    (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0   (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1    (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1    (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0     (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0     (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0     (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+
+#endif /* _SAM3N1A_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n1b.h b/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n1b.h
new file mode 100644
index 000000000..7ad975cc4
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n1b.h
@@ -0,0 +1,239 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N1B_PIO_
+#define _SAM3N1B_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0    (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1    (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10   (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11   (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12   (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13   (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14   (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PC31X1_AD15   (1u << 31) /**< \brief Adc signal: AD15 */
+#define PIO_PA19X1_AD2    (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9  (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3    (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4     (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5     (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6     (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12  (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7     (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8    (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9    (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG    (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0   (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PA2C_DATRG    (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0     (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0    (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PC16B_PCK0    (1u << 16) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1    (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PC17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2    (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2    (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2     (1u << 3)  /**< \brief Pmc signal: PCK2 */
+#define PIO_PC14B_PCK2    (1u << 14) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PA11B_PWM0    (1u << 11) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA23B_PWM0    (1u << 23) /**< \brief Pwm signal: PWM0 */
+#define PIO_PB0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC8B_PWM0     (1u << 8)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC18B_PWM0    (1u << 18) /**< \brief Pwm signal: PWM0 */
+#define PIO_PC22B_PWM0    (1u << 22) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PA12B_PWM1    (1u << 12) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA24B_PWM1    (1u << 24) /**< \brief Pwm signal: PWM1 */
+#define PIO_PB1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC9B_PWM1     (1u << 9)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC19B_PWM1    (1u << 19) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA2A_PWM2     (1u << 2)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PA13B_PWM2    (1u << 13) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA25B_PWM2    (1u << 25) /**< \brief Pwm signal: PWM2 */
+#define PIO_PB4B_PWM2     (1u << 4)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PC10B_PWM2    (1u << 10) /**< \brief Pwm signal: PWM2 */
+#define PIO_PC20B_PWM2    (1u << 20) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA7B_PWM3     (1u << 7)  /**< \brief Pwm signal: PWM3 */
+#define PIO_PA14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PB14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC11B_PWM3    (1u << 11) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC21B_PWM3    (1u << 21) /**< \brief Pwm signal: PWM3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO    (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI    (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0   (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1    (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1   (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1   (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1    (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2   (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2   (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2    (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC7B_NPCS2    (1u << 7)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3    (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3   (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK    (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0    (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1   (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2   (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0    (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1   (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2   (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0    (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1   (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2   (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0    (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0     (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1    (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1     (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0    (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0   (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1    (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1    (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0     (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0     (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0     (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1    (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA24A_RTS1    (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1    (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1    (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+
+#endif /* _SAM3N1B_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n1c.h b/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n1c.h
new file mode 100644
index 000000000..34b412fc5
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n1c.h
@@ -0,0 +1,313 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N1C_PIO_
+#define _SAM3N1C_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PC0           (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1           (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2           (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3           (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4           (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5           (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6           (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7           (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8           (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9           (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10          (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11          (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12          (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13          (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14          (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15          (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16          (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17          (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18          (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19          (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20          (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21          (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22          (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23          (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24          (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25          (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26          (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27          (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28          (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29          (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30          (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31          (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0    (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1    (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10   (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11   (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12   (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13   (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14   (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PC31X1_AD15   (1u << 31) /**< \brief Adc signal: AD15 */
+#define PIO_PA19X1_AD2    (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9  (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3    (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4     (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5     (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6     (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12  (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7     (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8    (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9    (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG    (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0   (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PA2C_DATRG    (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0     (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0    (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PC16B_PCK0    (1u << 16) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1    (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PC17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2    (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2    (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2     (1u << 3)  /**< \brief Pmc signal: PCK2 */
+#define PIO_PC14B_PCK2    (1u << 14) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PA11B_PWM0    (1u << 11) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA23B_PWM0    (1u << 23) /**< \brief Pwm signal: PWM0 */
+#define PIO_PB0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC8B_PWM0     (1u << 8)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC18B_PWM0    (1u << 18) /**< \brief Pwm signal: PWM0 */
+#define PIO_PC22B_PWM0    (1u << 22) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PA12B_PWM1    (1u << 12) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA24B_PWM1    (1u << 24) /**< \brief Pwm signal: PWM1 */
+#define PIO_PB1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC9B_PWM1     (1u << 9)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC19B_PWM1    (1u << 19) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA2A_PWM2     (1u << 2)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PA13B_PWM2    (1u << 13) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA25B_PWM2    (1u << 25) /**< \brief Pwm signal: PWM2 */
+#define PIO_PB4B_PWM2     (1u << 4)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PC10B_PWM2    (1u << 10) /**< \brief Pwm signal: PWM2 */
+#define PIO_PC20B_PWM2    (1u << 20) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA7B_PWM3     (1u << 7)  /**< \brief Pwm signal: PWM3 */
+#define PIO_PA14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PB14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC11B_PWM3    (1u << 11) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC21B_PWM3    (1u << 21) /**< \brief Pwm signal: PWM3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO    (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI    (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0   (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1    (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1   (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1   (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1    (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2   (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2   (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2    (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC7B_NPCS2    (1u << 7)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3    (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3   (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK    (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0    (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1   (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2   (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0    (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1   (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2   (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0    (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1   (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2   (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PC25B_TCLK3   (1u << 25) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PC28B_TCLK4   (1u << 28) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PC31B_TCLK5   (1u << 31) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PC23B_TIOA3   (1u << 23) /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PC26B_TIOA4   (1u << 26) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PC29B_TIOA5   (1u << 29) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PC24B_TIOB3   (1u << 24) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PC27B_TIOB4   (1u << 27) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PC30B_TIOB5   (1u << 30) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0    (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0     (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1    (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1     (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0    (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0   (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1    (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1    (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0     (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0     (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0     (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1    (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA24A_RTS1    (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1    (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1    (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+#define PIO_PC0_IDX       64
+#define PIO_PC1_IDX       65
+#define PIO_PC2_IDX       66
+#define PIO_PC3_IDX       67
+#define PIO_PC4_IDX       68
+#define PIO_PC5_IDX       69
+#define PIO_PC6_IDX       70
+#define PIO_PC7_IDX       71
+#define PIO_PC8_IDX       72
+#define PIO_PC9_IDX       73
+#define PIO_PC10_IDX      74
+#define PIO_PC11_IDX      75
+#define PIO_PC12_IDX      76
+#define PIO_PC13_IDX      77
+#define PIO_PC14_IDX      78
+#define PIO_PC15_IDX      79
+#define PIO_PC16_IDX      80
+#define PIO_PC17_IDX      81
+#define PIO_PC18_IDX      82
+#define PIO_PC19_IDX      83
+#define PIO_PC20_IDX      84
+#define PIO_PC21_IDX      85
+#define PIO_PC22_IDX      86
+#define PIO_PC23_IDX      87
+#define PIO_PC24_IDX      88
+#define PIO_PC25_IDX      89
+#define PIO_PC26_IDX      90
+#define PIO_PC27_IDX      91
+#define PIO_PC28_IDX      92
+#define PIO_PC29_IDX      93
+#define PIO_PC30_IDX      94
+#define PIO_PC31_IDX      95
+
+#endif /* _SAM3N1C_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n2a.h b/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n2a.h
new file mode 100644
index 000000000..f116941ba
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n2a.h
@@ -0,0 +1,207 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N2A_PIO_
+#define _SAM3N2A_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0    (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1    (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10   (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11   (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12   (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13   (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14   (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PC31X1_AD15   (1u << 31) /**< \brief Adc signal: AD15 */
+#define PIO_PA19X1_AD2    (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9  (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3    (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4     (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5     (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6     (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12  (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7     (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8    (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9    (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG    (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0   (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PA2C_DATRG    (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0     (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0    (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PC16B_PCK0    (1u << 16) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1    (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PC17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2    (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2    (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2     (1u << 3)  /**< \brief Pmc signal: PCK2 */
+#define PIO_PC14B_PCK2    (1u << 14) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PA11B_PWM0    (1u << 11) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA23B_PWM0    (1u << 23) /**< \brief Pwm signal: PWM0 */
+#define PIO_PB0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC8B_PWM0     (1u << 8)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC18B_PWM0    (1u << 18) /**< \brief Pwm signal: PWM0 */
+#define PIO_PC22B_PWM0    (1u << 22) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PA12B_PWM1    (1u << 12) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA24B_PWM1    (1u << 24) /**< \brief Pwm signal: PWM1 */
+#define PIO_PB1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC9B_PWM1     (1u << 9)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC19B_PWM1    (1u << 19) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA2A_PWM2     (1u << 2)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PA13B_PWM2    (1u << 13) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA25B_PWM2    (1u << 25) /**< \brief Pwm signal: PWM2 */
+#define PIO_PB4B_PWM2     (1u << 4)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PC10B_PWM2    (1u << 10) /**< \brief Pwm signal: PWM2 */
+#define PIO_PC20B_PWM2    (1u << 20) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA7B_PWM3     (1u << 7)  /**< \brief Pwm signal: PWM3 */
+#define PIO_PA14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PB14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC11B_PWM3    (1u << 11) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC21B_PWM3    (1u << 21) /**< \brief Pwm signal: PWM3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO    (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI    (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0   (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1    (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1   (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1   (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1    (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2   (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2   (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2    (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC7B_NPCS2    (1u << 7)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3    (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3   (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK    (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0    (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1   (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2   (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0    (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1   (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2   (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0    (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1   (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2   (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0    (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0     (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1    (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1     (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0    (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0   (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1    (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1    (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0     (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0     (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0     (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+
+#endif /* _SAM3N2A_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n2b.h b/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n2b.h
new file mode 100644
index 000000000..fdca60545
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n2b.h
@@ -0,0 +1,239 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N2B_PIO_
+#define _SAM3N2B_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0    (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1    (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10   (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11   (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12   (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13   (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14   (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PC31X1_AD15   (1u << 31) /**< \brief Adc signal: AD15 */
+#define PIO_PA19X1_AD2    (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9  (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3    (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4     (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5     (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6     (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12  (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7     (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8    (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9    (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG    (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0   (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PA2C_DATRG    (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0     (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0    (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PC16B_PCK0    (1u << 16) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1    (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PC17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2    (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2    (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2     (1u << 3)  /**< \brief Pmc signal: PCK2 */
+#define PIO_PC14B_PCK2    (1u << 14) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PA11B_PWM0    (1u << 11) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA23B_PWM0    (1u << 23) /**< \brief Pwm signal: PWM0 */
+#define PIO_PB0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC8B_PWM0     (1u << 8)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC18B_PWM0    (1u << 18) /**< \brief Pwm signal: PWM0 */
+#define PIO_PC22B_PWM0    (1u << 22) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PA12B_PWM1    (1u << 12) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA24B_PWM1    (1u << 24) /**< \brief Pwm signal: PWM1 */
+#define PIO_PB1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC9B_PWM1     (1u << 9)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC19B_PWM1    (1u << 19) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA2A_PWM2     (1u << 2)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PA13B_PWM2    (1u << 13) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA25B_PWM2    (1u << 25) /**< \brief Pwm signal: PWM2 */
+#define PIO_PB4B_PWM2     (1u << 4)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PC10B_PWM2    (1u << 10) /**< \brief Pwm signal: PWM2 */
+#define PIO_PC20B_PWM2    (1u << 20) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA7B_PWM3     (1u << 7)  /**< \brief Pwm signal: PWM3 */
+#define PIO_PA14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PB14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC11B_PWM3    (1u << 11) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC21B_PWM3    (1u << 21) /**< \brief Pwm signal: PWM3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO    (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI    (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0   (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1    (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1   (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1   (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1    (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2   (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2   (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2    (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC7B_NPCS2    (1u << 7)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3    (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3   (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK    (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0    (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1   (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2   (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0    (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1   (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2   (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0    (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1   (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2   (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0    (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0     (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1    (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1     (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0    (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0   (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1    (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1    (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0     (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0     (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0     (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1    (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA24A_RTS1    (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1    (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1    (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+
+#endif /* _SAM3N2B_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n2c.h b/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n2c.h
new file mode 100644
index 000000000..6238d66ad
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n2c.h
@@ -0,0 +1,313 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N2C_PIO_
+#define _SAM3N2C_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PC0           (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1           (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2           (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3           (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4           (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5           (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6           (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7           (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8           (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9           (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10          (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11          (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12          (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13          (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14          (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15          (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16          (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17          (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18          (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19          (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20          (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21          (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22          (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23          (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24          (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25          (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26          (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27          (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28          (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29          (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30          (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31          (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0    (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1    (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10   (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11   (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12   (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13   (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14   (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PC31X1_AD15   (1u << 31) /**< \brief Adc signal: AD15 */
+#define PIO_PA19X1_AD2    (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9  (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3    (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4     (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5     (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6     (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12  (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7     (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8    (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9    (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG    (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0   (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PA2C_DATRG    (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0     (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0    (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PC16B_PCK0    (1u << 16) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1    (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PC17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2    (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2    (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2     (1u << 3)  /**< \brief Pmc signal: PCK2 */
+#define PIO_PC14B_PCK2    (1u << 14) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PA11B_PWM0    (1u << 11) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA23B_PWM0    (1u << 23) /**< \brief Pwm signal: PWM0 */
+#define PIO_PB0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC8B_PWM0     (1u << 8)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC18B_PWM0    (1u << 18) /**< \brief Pwm signal: PWM0 */
+#define PIO_PC22B_PWM0    (1u << 22) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PA12B_PWM1    (1u << 12) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA24B_PWM1    (1u << 24) /**< \brief Pwm signal: PWM1 */
+#define PIO_PB1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC9B_PWM1     (1u << 9)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC19B_PWM1    (1u << 19) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA2A_PWM2     (1u << 2)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PA13B_PWM2    (1u << 13) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA25B_PWM2    (1u << 25) /**< \brief Pwm signal: PWM2 */
+#define PIO_PB4B_PWM2     (1u << 4)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PC10B_PWM2    (1u << 10) /**< \brief Pwm signal: PWM2 */
+#define PIO_PC20B_PWM2    (1u << 20) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA7B_PWM3     (1u << 7)  /**< \brief Pwm signal: PWM3 */
+#define PIO_PA14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PB14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC11B_PWM3    (1u << 11) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC21B_PWM3    (1u << 21) /**< \brief Pwm signal: PWM3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO    (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI    (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0   (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1    (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1   (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1   (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1    (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2   (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2   (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2    (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC7B_NPCS2    (1u << 7)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3    (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3   (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK    (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0    (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1   (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2   (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0    (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1   (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2   (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0    (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1   (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2   (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PC25B_TCLK3   (1u << 25) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PC28B_TCLK4   (1u << 28) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PC31B_TCLK5   (1u << 31) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PC23B_TIOA3   (1u << 23) /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PC26B_TIOA4   (1u << 26) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PC29B_TIOA5   (1u << 29) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PC24B_TIOB3   (1u << 24) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PC27B_TIOB4   (1u << 27) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PC30B_TIOB5   (1u << 30) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0    (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0     (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1    (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1     (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0    (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0   (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1    (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1    (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0     (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0     (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0     (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1    (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA24A_RTS1    (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1    (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1    (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+#define PIO_PC0_IDX       64
+#define PIO_PC1_IDX       65
+#define PIO_PC2_IDX       66
+#define PIO_PC3_IDX       67
+#define PIO_PC4_IDX       68
+#define PIO_PC5_IDX       69
+#define PIO_PC6_IDX       70
+#define PIO_PC7_IDX       71
+#define PIO_PC8_IDX       72
+#define PIO_PC9_IDX       73
+#define PIO_PC10_IDX      74
+#define PIO_PC11_IDX      75
+#define PIO_PC12_IDX      76
+#define PIO_PC13_IDX      77
+#define PIO_PC14_IDX      78
+#define PIO_PC15_IDX      79
+#define PIO_PC16_IDX      80
+#define PIO_PC17_IDX      81
+#define PIO_PC18_IDX      82
+#define PIO_PC19_IDX      83
+#define PIO_PC20_IDX      84
+#define PIO_PC21_IDX      85
+#define PIO_PC22_IDX      86
+#define PIO_PC23_IDX      87
+#define PIO_PC24_IDX      88
+#define PIO_PC25_IDX      89
+#define PIO_PC26_IDX      90
+#define PIO_PC27_IDX      91
+#define PIO_PC28_IDX      92
+#define PIO_PC29_IDX      93
+#define PIO_PC30_IDX      94
+#define PIO_PC31_IDX      95
+
+#endif /* _SAM3N2C_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n4a.h b/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n4a.h
new file mode 100644
index 000000000..0f3c1f280
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n4a.h
@@ -0,0 +1,207 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N4A_PIO_
+#define _SAM3N4A_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0    (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1    (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10   (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11   (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12   (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13   (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14   (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PC31X1_AD15   (1u << 31) /**< \brief Adc signal: AD15 */
+#define PIO_PA19X1_AD2    (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9  (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3    (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4     (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5     (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6     (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12  (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7     (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8    (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9    (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG    (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0   (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PA2C_DATRG    (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0     (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0    (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PC16B_PCK0    (1u << 16) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1    (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PC17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2    (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2    (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2     (1u << 3)  /**< \brief Pmc signal: PCK2 */
+#define PIO_PC14B_PCK2    (1u << 14) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PA11B_PWM0    (1u << 11) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA23B_PWM0    (1u << 23) /**< \brief Pwm signal: PWM0 */
+#define PIO_PB0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC8B_PWM0     (1u << 8)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC18B_PWM0    (1u << 18) /**< \brief Pwm signal: PWM0 */
+#define PIO_PC22B_PWM0    (1u << 22) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PA12B_PWM1    (1u << 12) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA24B_PWM1    (1u << 24) /**< \brief Pwm signal: PWM1 */
+#define PIO_PB1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC9B_PWM1     (1u << 9)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC19B_PWM1    (1u << 19) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA2A_PWM2     (1u << 2)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PA13B_PWM2    (1u << 13) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA25B_PWM2    (1u << 25) /**< \brief Pwm signal: PWM2 */
+#define PIO_PB4B_PWM2     (1u << 4)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PC10B_PWM2    (1u << 10) /**< \brief Pwm signal: PWM2 */
+#define PIO_PC20B_PWM2    (1u << 20) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA7B_PWM3     (1u << 7)  /**< \brief Pwm signal: PWM3 */
+#define PIO_PA14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PB14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC11B_PWM3    (1u << 11) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC21B_PWM3    (1u << 21) /**< \brief Pwm signal: PWM3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO    (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI    (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0   (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1    (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1   (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1   (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1    (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2   (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2   (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2    (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC7B_NPCS2    (1u << 7)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3    (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3   (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK    (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0    (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1   (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2   (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0    (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1   (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2   (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0    (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1   (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2   (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0    (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0     (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1    (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1     (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0    (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0   (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1    (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1    (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0     (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0     (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0     (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+
+#endif /* _SAM3N4A_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n4b.h b/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n4b.h
new file mode 100644
index 000000000..ee99ea68e
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n4b.h
@@ -0,0 +1,239 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N4B_PIO_
+#define _SAM3N4B_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0    (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1    (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10   (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11   (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12   (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13   (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14   (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PC31X1_AD15   (1u << 31) /**< \brief Adc signal: AD15 */
+#define PIO_PA19X1_AD2    (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9  (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3    (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4     (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5     (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6     (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12  (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7     (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8    (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9    (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG    (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0   (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PA2C_DATRG    (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0     (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0    (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PC16B_PCK0    (1u << 16) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1    (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PC17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2    (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2    (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2     (1u << 3)  /**< \brief Pmc signal: PCK2 */
+#define PIO_PC14B_PCK2    (1u << 14) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PA11B_PWM0    (1u << 11) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA23B_PWM0    (1u << 23) /**< \brief Pwm signal: PWM0 */
+#define PIO_PB0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC8B_PWM0     (1u << 8)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC18B_PWM0    (1u << 18) /**< \brief Pwm signal: PWM0 */
+#define PIO_PC22B_PWM0    (1u << 22) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PA12B_PWM1    (1u << 12) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA24B_PWM1    (1u << 24) /**< \brief Pwm signal: PWM1 */
+#define PIO_PB1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC9B_PWM1     (1u << 9)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC19B_PWM1    (1u << 19) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA2A_PWM2     (1u << 2)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PA13B_PWM2    (1u << 13) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA25B_PWM2    (1u << 25) /**< \brief Pwm signal: PWM2 */
+#define PIO_PB4B_PWM2     (1u << 4)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PC10B_PWM2    (1u << 10) /**< \brief Pwm signal: PWM2 */
+#define PIO_PC20B_PWM2    (1u << 20) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA7B_PWM3     (1u << 7)  /**< \brief Pwm signal: PWM3 */
+#define PIO_PA14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PB14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC11B_PWM3    (1u << 11) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC21B_PWM3    (1u << 21) /**< \brief Pwm signal: PWM3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO    (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI    (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0   (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1    (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1   (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1   (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1    (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2   (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2   (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2    (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC7B_NPCS2    (1u << 7)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3    (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3   (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK    (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0    (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1   (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2   (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0    (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1   (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2   (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0    (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1   (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2   (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0    (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0     (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1    (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1     (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0    (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0   (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1    (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1    (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0     (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0     (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0     (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1    (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA24A_RTS1    (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1    (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1    (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+
+#endif /* _SAM3N4B_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n4c.h b/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n4c.h
new file mode 100644
index 000000000..30f256f7d
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/pio/pio_sam3n4c.h
@@ -0,0 +1,313 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N4C_PIO_
+#define _SAM3N4C_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PC0           (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1           (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2           (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3           (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4           (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5           (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6           (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7           (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8           (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9           (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10          (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11          (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12          (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13          (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14          (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15          (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16          (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17          (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18          (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19          (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20          (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21          (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22          (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23          (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24          (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25          (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26          (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27          (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28          (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29          (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30          (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31          (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0    (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1    (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10   (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11   (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12   (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13   (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14   (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PC31X1_AD15   (1u << 31) /**< \brief Adc signal: AD15 */
+#define PIO_PA19X1_AD2    (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9  (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3    (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4     (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5     (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6     (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12  (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7     (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8    (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9    (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG    (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0   (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PA2C_DATRG    (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0     (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0    (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PC16B_PCK0    (1u << 16) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1    (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PC17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2    (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2    (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2     (1u << 3)  /**< \brief Pmc signal: PCK2 */
+#define PIO_PC14B_PCK2    (1u << 14) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PA11B_PWM0    (1u << 11) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA23B_PWM0    (1u << 23) /**< \brief Pwm signal: PWM0 */
+#define PIO_PB0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC8B_PWM0     (1u << 8)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC18B_PWM0    (1u << 18) /**< \brief Pwm signal: PWM0 */
+#define PIO_PC22B_PWM0    (1u << 22) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PA12B_PWM1    (1u << 12) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA24B_PWM1    (1u << 24) /**< \brief Pwm signal: PWM1 */
+#define PIO_PB1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC9B_PWM1     (1u << 9)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC19B_PWM1    (1u << 19) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA2A_PWM2     (1u << 2)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PA13B_PWM2    (1u << 13) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA25B_PWM2    (1u << 25) /**< \brief Pwm signal: PWM2 */
+#define PIO_PB4B_PWM2     (1u << 4)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PC10B_PWM2    (1u << 10) /**< \brief Pwm signal: PWM2 */
+#define PIO_PC20B_PWM2    (1u << 20) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA7B_PWM3     (1u << 7)  /**< \brief Pwm signal: PWM3 */
+#define PIO_PA14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PB14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC11B_PWM3    (1u << 11) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC21B_PWM3    (1u << 21) /**< \brief Pwm signal: PWM3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO    (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI    (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0   (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1    (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1   (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1   (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1    (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2   (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2   (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2    (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC7B_NPCS2    (1u << 7)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3    (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3   (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK    (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0    (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1   (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2   (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0    (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1   (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2   (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0    (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1   (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2   (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PC25B_TCLK3   (1u << 25) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PC28B_TCLK4   (1u << 28) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PC31B_TCLK5   (1u << 31) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PC23B_TIOA3   (1u << 23) /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PC26B_TIOA4   (1u << 26) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PC29B_TIOA5   (1u << 29) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PC24B_TIOB3   (1u << 24) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PC27B_TIOB4   (1u << 27) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PC30B_TIOB5   (1u << 30) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0    (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0     (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1    (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1     (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0    (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0   (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1    (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1    (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0     (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0     (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0     (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1    (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA24A_RTS1    (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1    (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1    (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+#define PIO_PC0_IDX       64
+#define PIO_PC1_IDX       65
+#define PIO_PC2_IDX       66
+#define PIO_PC3_IDX       67
+#define PIO_PC4_IDX       68
+#define PIO_PC5_IDX       69
+#define PIO_PC6_IDX       70
+#define PIO_PC7_IDX       71
+#define PIO_PC8_IDX       72
+#define PIO_PC9_IDX       73
+#define PIO_PC10_IDX      74
+#define PIO_PC11_IDX      75
+#define PIO_PC12_IDX      76
+#define PIO_PC13_IDX      77
+#define PIO_PC14_IDX      78
+#define PIO_PC15_IDX      79
+#define PIO_PC16_IDX      80
+#define PIO_PC17_IDX      81
+#define PIO_PC18_IDX      82
+#define PIO_PC19_IDX      83
+#define PIO_PC20_IDX      84
+#define PIO_PC21_IDX      85
+#define PIO_PC22_IDX      86
+#define PIO_PC23_IDX      87
+#define PIO_PC24_IDX      88
+#define PIO_PC25_IDX      89
+#define PIO_PC26_IDX      90
+#define PIO_PC27_IDX      91
+#define PIO_PC28_IDX      92
+#define PIO_PC29_IDX      93
+#define PIO_PC30_IDX      94
+#define PIO_PC31_IDX      95
+
+#endif /* _SAM3N4C_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n.h b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n.h
new file mode 100644
index 000000000..5fab9c49a
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n.h
@@ -0,0 +1,55 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_
+#define _SAM3N_
+
+#if defined __SAM3N1A__
+  #include "sam3n1a.h"
+#elif defined __SAM3N1B__
+  #include "sam3n1b.h"
+#elif defined __SAM3N1C__
+  #include "sam3n1c.h"
+#elif defined __SAM3N2A__
+  #include "sam3n2a.h"
+#elif defined __SAM3N2B__
+  #include "sam3n2b.h"
+#elif defined __SAM3N2C__
+  #include "sam3n2c.h"
+#elif defined __SAM3N4A__
+  #include "sam3n4a.h"
+#elif defined __SAM3N4B__
+  #include "sam3n4b.h"
+#elif defined __SAM3N4C__
+  #include "sam3n4c.h"
+#else
+  #error Library does not support the specified device.
+#endif
+
+#endif /* _SAM3N_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n1a.h b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n1a.h
new file mode 100644
index 000000000..f3550a462
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n1a.h
@@ -0,0 +1,316 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N1A_
+#define _SAM3N1A_
+
+/** \addtogroup SAM3N1A_definitions SAM3N1A definitions
+  This file defines all structures and symbols for SAM3N1A:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3N1A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1A_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3N1A specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3N1A Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3N1A Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3N1A Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3N1A Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3N1A Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3N1A Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3N1A Enhanced Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3N1A UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3N1A UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3N1A Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3N1A Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3N1A USART 0 (USART0) */
+  TWI0_IRQn            = 19, /**< 19 SAM3N1A Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3N1A Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3N1A Serial Peripheral Interface (SPI) */
+  TC0_IRQn             = 23, /**< 23 SAM3N1A Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3N1A Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3N1A Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3N1A Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3N1A Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31  /**< 31 SAM3N1A Pulse Width Modulation (PWM) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3N1A core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N1A does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N1A uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N1A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1A_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3N1A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3N1A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1A_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3N1A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3N1A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1A_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3n1a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3N1A */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x10000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (256u)
+#define IFLASH_NB_OF_LOCK_BITS  (4u)
+#define IRAM_SIZE               (0x2000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR   (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3N1A */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (48000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3N1A_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n1b.h b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n1b.h
new file mode 100644
index 000000000..1e0e63243
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n1b.h
@@ -0,0 +1,321 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N1B_
+#define _SAM3N1B_
+
+/** \addtogroup SAM3N1B_definitions SAM3N1B definitions
+  This file defines all structures and symbols for SAM3N1B:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3N1B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1B_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3N1B specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3N1B Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3N1B Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3N1B Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3N1B Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3N1B Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3N1B Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3N1B Enhanced Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3N1B UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3N1B UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3N1B Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3N1B Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3N1B USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3N1B USART 1 (USART1) */
+  TWI0_IRQn            = 19, /**< 19 SAM3N1B Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3N1B Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3N1B Serial Peripheral Interface (SPI) */
+  TC0_IRQn             = 23, /**< 23 SAM3N1B Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3N1B Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3N1B Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3N1B Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3N1B Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31  /**< 31 SAM3N1B Pulse Width Modulation (PWM) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3N1B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N1B does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N1B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N1B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1B_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3N1B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3N1B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1B_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3N1B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3N1B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1B_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3n1b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3N1B */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x10000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (256u)
+#define IFLASH_NB_OF_LOCK_BITS  (4u)
+#define IRAM_SIZE               (0x2000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR   (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3N1B */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (48000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3N1B_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n1c.h b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n1c.h
new file mode 100644
index 000000000..49b67392e
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n1c.h
@@ -0,0 +1,335 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N1C_
+#define _SAM3N1C_
+
+/** \addtogroup SAM3N1C_definitions SAM3N1C definitions
+  This file defines all structures and symbols for SAM3N1C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3N1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3N1C specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3N1C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3N1C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3N1C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3N1C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3N1C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3N1C Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3N1C Enhanced Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3N1C UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3N1C UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3N1C Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3N1C Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM3N1C Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 14, /**< 14 SAM3N1C USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3N1C USART 1 (USART1) */
+  TWI0_IRQn            = 19, /**< 19 SAM3N1C Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3N1C Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3N1C Serial Peripheral Interface (SPI) */
+  TC0_IRQn             = 23, /**< 23 SAM3N1C Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3N1C Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3N1C Timer/Counter 2 (TC2) */
+  TC3_IRQn             = 26, /**< 26 SAM3N1C Timer/Counter 3 (TC3) */
+  TC4_IRQn             = 27, /**< 27 SAM3N1C Timer/Counter 4 (TC4) */
+  TC5_IRQn             = 28, /**< 28 SAM3N1C Timer/Counter 5 (TC5) */
+  ADC_IRQn             = 29, /**< 29 SAM3N1C Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3N1C Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31  /**< 31 SAM3N1C Pulse Width Modulation (PWM) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3N1C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N1C does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N1C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3N1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3N1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_TC3    (26) /**< \brief Timer/Counter 3 (TC3) */
+#define ID_TC4    (27) /**< \brief Timer/Counter 4 (TC4) */
+#define ID_TC5    (28) /**< \brief Timer/Counter 5 (TC5) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3N1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3N1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3n1c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3N1C */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x10000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (256u)
+#define IFLASH_NB_OF_LOCK_BITS  (4u)
+#define IRAM_SIZE               (0x2000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR   (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3N1C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (48000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3N1C_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n2a.h b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n2a.h
new file mode 100644
index 000000000..7bece6d33
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n2a.h
@@ -0,0 +1,316 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N2A_
+#define _SAM3N2A_
+
+/** \addtogroup SAM3N2A_definitions SAM3N2A definitions
+  This file defines all structures and symbols for SAM3N2A:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3N2A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2A_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3N2A specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3N2A Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3N2A Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3N2A Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3N2A Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3N2A Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3N2A Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3N2A Enhanced Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3N2A UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3N2A UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3N2A Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3N2A Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3N2A USART 0 (USART0) */
+  TWI0_IRQn            = 19, /**< 19 SAM3N2A Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3N2A Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3N2A Serial Peripheral Interface (SPI) */
+  TC0_IRQn             = 23, /**< 23 SAM3N2A Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3N2A Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3N2A Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3N2A Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3N2A Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31  /**< 31 SAM3N2A Pulse Width Modulation (PWM) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3N2A core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N2A does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N2A uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N2A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2A_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3N2A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3N2A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2A_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3N2A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3N2A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2A_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3n2a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3N2A */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x20000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (512u)
+#define IFLASH_NB_OF_LOCK_BITS  (8u)
+#define IRAM_SIZE               (0x4000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR   (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3N2A */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (48000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3N2A_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n2b.h b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n2b.h
new file mode 100644
index 000000000..075fa2aae
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n2b.h
@@ -0,0 +1,321 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N2B_
+#define _SAM3N2B_
+
+/** \addtogroup SAM3N2B_definitions SAM3N2B definitions
+  This file defines all structures and symbols for SAM3N2B:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3N2B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2B_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3N2B specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3N2B Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3N2B Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3N2B Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3N2B Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3N2B Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3N2B Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3N2B Enhanced Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3N2B UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3N2B UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3N2B Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3N2B Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3N2B USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3N2B USART 1 (USART1) */
+  TWI0_IRQn            = 19, /**< 19 SAM3N2B Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3N2B Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3N2B Serial Peripheral Interface (SPI) */
+  TC0_IRQn             = 23, /**< 23 SAM3N2B Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3N2B Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3N2B Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3N2B Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3N2B Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31  /**< 31 SAM3N2B Pulse Width Modulation (PWM) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3N2B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N2B does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N2B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N2B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2B_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3N2B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3N2B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2B_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3N2B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3N2B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2B_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3n2b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3N2B */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x20000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (512u)
+#define IFLASH_NB_OF_LOCK_BITS  (8u)
+#define IRAM_SIZE               (0x4000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR   (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3N2B */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (48000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3N2B_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n2c.h b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n2c.h
new file mode 100644
index 000000000..2e47fac70
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n2c.h
@@ -0,0 +1,335 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N2C_
+#define _SAM3N2C_
+
+/** \addtogroup SAM3N2C_definitions SAM3N2C definitions
+  This file defines all structures and symbols for SAM3N2C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3N2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3N2C specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3N2C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3N2C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3N2C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3N2C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3N2C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3N2C Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3N2C Enhanced Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3N2C UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3N2C UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3N2C Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3N2C Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM3N2C Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 14, /**< 14 SAM3N2C USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3N2C USART 1 (USART1) */
+  TWI0_IRQn            = 19, /**< 19 SAM3N2C Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3N2C Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3N2C Serial Peripheral Interface (SPI) */
+  TC0_IRQn             = 23, /**< 23 SAM3N2C Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3N2C Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3N2C Timer/Counter 2 (TC2) */
+  TC3_IRQn             = 26, /**< 26 SAM3N2C Timer/Counter 3 (TC3) */
+  TC4_IRQn             = 27, /**< 27 SAM3N2C Timer/Counter 4 (TC4) */
+  TC5_IRQn             = 28, /**< 28 SAM3N2C Timer/Counter 5 (TC5) */
+  ADC_IRQn             = 29, /**< 29 SAM3N2C Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3N2C Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31  /**< 31 SAM3N2C Pulse Width Modulation (PWM) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3N2C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N2C does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N2C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3N2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3N2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_TC3    (26) /**< \brief Timer/Counter 3 (TC3) */
+#define ID_TC4    (27) /**< \brief Timer/Counter 4 (TC4) */
+#define ID_TC5    (28) /**< \brief Timer/Counter 5 (TC5) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3N2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3N2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3n2c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3N2C */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x20000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (512u)
+#define IFLASH_NB_OF_LOCK_BITS  (8u)
+#define IRAM_SIZE               (0x4000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR   (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3N2C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (48000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3N2C_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n4a.h b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n4a.h
new file mode 100644
index 000000000..a303cb3a4
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n4a.h
@@ -0,0 +1,316 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N4A_
+#define _SAM3N4A_
+
+/** \addtogroup SAM3N4A_definitions SAM3N4A definitions
+  This file defines all structures and symbols for SAM3N4A:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3N4A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4A_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3N4A specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3N4A Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3N4A Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3N4A Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3N4A Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3N4A Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3N4A Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3N4A Enhanced Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3N4A UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3N4A UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3N4A Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3N4A Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3N4A USART 0 (USART0) */
+  TWI0_IRQn            = 19, /**< 19 SAM3N4A Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3N4A Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3N4A Serial Peripheral Interface (SPI) */
+  TC0_IRQn             = 23, /**< 23 SAM3N4A Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3N4A Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3N4A Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3N4A Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3N4A Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31  /**< 31 SAM3N4A Pulse Width Modulation (PWM) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3N4A core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N4A does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N4A uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N4A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4A_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3N4A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3N4A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4A_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3N4A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3N4A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4A_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3n4a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3N4A */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x40000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (1024u)
+#define IFLASH_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE               (0x6000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR   (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3N4A */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (48000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3N4A_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n4b.h b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n4b.h
new file mode 100644
index 000000000..0c7a6763b
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n4b.h
@@ -0,0 +1,321 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N4B_
+#define _SAM3N4B_
+
+/** \addtogroup SAM3N4B_definitions SAM3N4B definitions
+  This file defines all structures and symbols for SAM3N4B:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3N4B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4B_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3N4B specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3N4B Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3N4B Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3N4B Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3N4B Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3N4B Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3N4B Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3N4B Enhanced Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3N4B UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3N4B UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3N4B Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3N4B Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3N4B USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3N4B USART 1 (USART1) */
+  TWI0_IRQn            = 19, /**< 19 SAM3N4B Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3N4B Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3N4B Serial Peripheral Interface (SPI) */
+  TC0_IRQn             = 23, /**< 23 SAM3N4B Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3N4B Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3N4B Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3N4B Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3N4B Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31  /**< 31 SAM3N4B Pulse Width Modulation (PWM) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3N4B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N4B does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N4B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N4B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4B_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3N4B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3N4B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4B_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3N4B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3N4B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4B_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3n4b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3N4B */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x40000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (1024u)
+#define IFLASH_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE               (0x6000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR   (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3N4B */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (48000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3N4B_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n4c.h b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n4c.h
new file mode 100644
index 000000000..90541382f
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n4c.h
@@ -0,0 +1,335 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N4C_
+#define _SAM3N4C_
+
+/** \addtogroup SAM3N4C_definitions SAM3N4C definitions
+  This file defines all structures and symbols for SAM3N4C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3N4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3N4C specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3N4C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3N4C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3N4C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3N4C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3N4C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3N4C Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3N4C Enhanced Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3N4C UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3N4C UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3N4C Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3N4C Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM3N4C Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 14, /**< 14 SAM3N4C USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3N4C USART 1 (USART1) */
+  TWI0_IRQn            = 19, /**< 19 SAM3N4C Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3N4C Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3N4C Serial Peripheral Interface (SPI) */
+  TC0_IRQn             = 23, /**< 23 SAM3N4C Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3N4C Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3N4C Timer/Counter 2 (TC2) */
+  TC3_IRQn             = 26, /**< 26 SAM3N4C Timer/Counter 3 (TC3) */
+  TC4_IRQn             = 27, /**< 27 SAM3N4C Timer/Counter 4 (TC4) */
+  TC5_IRQn             = 28, /**< 28 SAM3N4C Timer/Counter 5 (TC5) */
+  ADC_IRQn             = 29, /**< 29 SAM3N4C Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3N4C Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31  /**< 31 SAM3N4C Pulse Width Modulation (PWM) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3N4C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N4C does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N4C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3N4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3N4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_TC3    (26) /**< \brief Timer/Counter 3 (TC3) */
+#define ID_TC4    (27) /**< \brief Timer/Counter 4 (TC4) */
+#define ID_TC5    (28) /**< \brief Timer/Counter 5 (TC5) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3N4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3N4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3n4c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3N4C */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x40000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (1024u)
+#define IFLASH_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE               (0x6000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR   (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3N4C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (48000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3N4C_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/source/templates/exceptions.c b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/exceptions.c
new file mode 100644
index 000000000..4e9831ac1
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/exceptions.c
@@ -0,0 +1,131 @@
+/*! \file *********************************************************************
+ *
+ * \brief This file contains the default exception handlers.
+ *
+ * $asf_license$
+ *
+ * \par Purpose
+ *
+ * This file provides basic support for Cortex-M processor based 
+ * microcontrollers.
+ *
+ * \note
+ * The exception handler has weak aliases.
+ * As they are weak aliases, any function with the same name will override
+ * this definition.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+#include "exceptions.h"
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#ifdef __GNUC__
+/* Cortex-M3 core handlers */
+void Reset_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void NMI_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SUPC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOA_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void ADC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void DACC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PWM_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* __GNUC__ */
+
+#ifdef __ICCARM__
+/* Cortex-M3 core handlers */
+#pragma weak Reset_Handler=Dummy_Handler
+#pragma weak NMI_Handler=Dummy_Handler
+#pragma weak HardFault_Handler=Dummy_Handler
+#pragma weak MemManage_Handler=Dummy_Handler
+#pragma weak BusFault_Handler=Dummy_Handler
+#pragma weak UsageFault_Handler=Dummy_Handler
+#pragma weak SVC_Handler=Dummy_Handler
+#pragma weak DebugMon_Handler=Dummy_Handler
+#pragma weak PendSV_Handler=Dummy_Handler
+#pragma weak SysTick_Handler=Dummy_Handler
+
+/* Peripherals handlers */
+#pragma weak SUPC_IrqHandler=Dummy_Handler
+#pragma weak RSTC_IrqHandler=Dummy_Handler
+#pragma weak RTC_IrqHandler=Dummy_Handler
+#pragma weak RTT_IrqHandler=Dummy_Handler
+#pragma weak WDT_IrqHandler=Dummy_Handler
+#pragma weak PMC_IrqHandler=Dummy_Handler
+#pragma weak EFC_IrqHandler=Dummy_Handler
+#pragma weak UART0_IrqHandler=Dummy_Handler
+#pragma weak UART1_IrqHandler=Dummy_Handler
+#pragma weak PIOA_IrqHandler=Dummy_Handler
+#pragma weak PIOB_IrqHandler=Dummy_Handler
+#pragma weak PIOC_IrqHandler=Dummy_Handler
+#pragma weak USART0_IrqHandler=Dummy_Handler
+#pragma weak USART1_IrqHandler=Dummy_Handler
+#pragma weak TWI0_IrqHandler=Dummy_Handler
+#pragma weak TWI1_IrqHandler=Dummy_Handler
+#pragma weak SPI_IrqHandler=Dummy_Handler
+#pragma weak TC0_IrqHandler=Dummy_Handler
+#pragma weak TC1_IrqHandler=Dummy_Handler
+#pragma weak TC2_IrqHandler=Dummy_Handler
+#pragma weak TC3_IrqHandler=Dummy_Handler
+#pragma weak TC4_IrqHandler=Dummy_Handler
+#pragma weak TC5_IrqHandler=Dummy_Handler
+#pragma weak ADC_IrqHandler=Dummy_Handler
+#pragma weak DACC_IrqHandler=Dummy_Handler
+#pragma weak PWM_IrqHandler=Dummy_Handler
+#endif /* __ICCARM__ */
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/source/templates/exceptions.h b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/exceptions.h
new file mode 100644
index 000000000..6130e1e78
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/exceptions.h
@@ -0,0 +1,82 @@
+/*! \file *********************************************************************
+ *
+ * \brief This file contains the interface for default exception handlers.
+ *
+ * $asf_license$
+ *
+ * \par Purpose
+ *
+ * This file provides basic support for Cortex-M processor based 
+ * microcontrollers.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+#ifndef EXCEPTIONS_H_INCLUDED
+#define EXCEPTIONS_H_INCLUDED
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+/* Function prototype for exception table items (interrupt handler). */
+typedef void (*IntFunc) (void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+void Reset_Handler(void);
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+
+/* Peripherals handlers */
+void SUPC_IrqHandler(void);
+void RSTC_IrqHandler(void);
+void RTC_IrqHandler(void);
+void RTT_IrqHandler(void);
+void WDT_IrqHandler(void);
+void PMC_IrqHandler(void);
+void EFC_IrqHandler(void);
+void UART0_IrqHandler(void);
+void UART1_IrqHandler(void);
+void PIOA_IrqHandler(void);
+void PIOB_IrqHandler(void);
+void PIOC_IrqHandler(void);
+void USART0_IrqHandler(void);
+void USART1_IrqHandler(void);
+void TWI0_IrqHandler(void);
+void TWI1_IrqHandler(void);
+void SPI_IrqHandler(void);
+void TC0_IrqHandler(void);
+void TC1_IrqHandler(void);
+void TC2_IrqHandler(void);
+void TC3_IrqHandler(void);
+void TC4_IrqHandler(void);
+void TC5_IrqHandler(void);
+void ADC_IrqHandler(void);
+void DACC_IrqHandler(void);
+void PWM_IrqHandler(void);
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#endif /* EXCEPTIONS_H_INCLUDED */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/source/templates/gcc/startup_sam3n.c b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/gcc/startup_sam3n.c
new file mode 100644
index 000000000..7ccde5fcb
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/gcc/startup_sam3n.c
@@ -0,0 +1,134 @@
+/*! \file *********************************************************************
+ *
+ * \brief Startup file for SAM3N.
+ *
+ * $asf_license$
+ *
+ * This file defines common SAM series.
+ *
+ * - Compiler:           ARMGCC
+ * - Supported devices:  All SAM3N devices can be used.
+ * - AppNote:
+ *
+ ******************************************************************************/
+
+#include "../exceptions.h"
+#include "sam3.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+IntFunc exception_table[] = {
+
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(IntFunc) (&_estack),
+	Reset_Handler,
+
+	NMI_Handler,
+	HardFault_Handler,
+	MemManage_Handler,
+	BusFault_Handler,
+	UsageFault_Handler,
+	0, 0, 0, 0,         /* Reserved */
+	SVC_Handler,
+	DebugMon_Handler,
+	0,                  /* Reserved  */
+	PendSV_Handler,
+	SysTick_Handler,
+
+	/* Configurable interrupts  */
+	SUPC_IrqHandler,    /* 0  Supply Controller */
+	RSTC_IrqHandler,    /* 1  Reset Controller */
+	RTC_IrqHandler,     /* 2  Real Time Clock */
+	RTT_IrqHandler,     /* 3  Real Time Timer */
+	WDT_IrqHandler,     /* 4  Watchdog Timer */
+ 	PMC_IrqHandler,     /* 5  PMC */
+	EFC_IrqHandler,     /* 6  EEFC */
+	Dummy_Handler,      /* 7  Reserved */
+ 	UART0_IrqHandler,   /* 8  UART0 */
+	UART1_IrqHandler,   /* 9  UART1 */
+	Dummy_Handler,  	/* 10 Reserved */
+	PIOA_IrqHandler,    /* 11 Parallel IO Controller A */
+	PIOB_IrqHandler,    /* 12 Parallel IO Controller B */
+	PIOC_IrqHandler,    /* 13 Parallel IO Controller C */
+	USART0_IrqHandler,  /* 14 USART 0 */
+	USART1_IrqHandler,  /* 15 USART 1 */
+	Dummy_Handler,  	/* 16 Reserved */
+	Dummy_Handler,  	/* 17 Reserved */
+	Dummy_Handler,  	/* 18 Reserved */
+	TWI0_IrqHandler,    /* 19 TWI 0 */
+	TWI1_IrqHandler,    /* 20 TWI 1 */
+ 	SPI_IrqHandler,     /* 21 SPI */
+	Dummy_Handler,  	/* 22 Reserved */
+	TC0_IrqHandler,     /* 23 Timer Counter 0 */
+	TC1_IrqHandler,     /* 24 Timer Counter 1 */
+	TC2_IrqHandler,     /* 25 Timer Counter 2 */
+	TC3_IrqHandler,     /* 26 Timer Counter 3 */
+ 	TC4_IrqHandler,     /* 27 Timer Counter 4 */
+	TC5_IrqHandler,     /* 28 Timer Counter 5 */
+	ADC_IrqHandler,     /* 29 ADC controller */
+	DACC_IrqHandler,    /* 30 DAC controller */
+	PWM_IrqHandler,		/* 31 PWM */
+	Dummy_Handler   	/* 32 not used */
+};
+
+/* TEMPORARY PATCH FOR SCB */
+#define SCB_VTOR_TBLBASE_Pos               29                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/source/templates/iar/startup_sam3n.c b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/iar/startup_sam3n.c
new file mode 100644
index 000000000..292af9a69
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/iar/startup_sam3n.c
@@ -0,0 +1,110 @@
+/*! \file *********************************************************************
+ *
+ * \brief Startup file for SAM3N.
+ *
+ * $asf_license$
+ *
+ * This file defines common SAM series.
+ *
+ * - Compiler:           IAR EWARM
+ * - Supported devices:  All SAM3N devices can be used.
+ * - AppNote:
+ *
+ ******************************************************************************/
+
+#include "../exceptions.h"
+#include "sam3.h"
+
+typedef void (*intfunc) (void);
+typedef union { intfunc __fun; void * __ptr; } intvec_elem;
+
+void __iar_program_start(void);
+int __low_level_init(void);
+
+/* Exception Table */
+#pragma language=extended
+#pragma segment="CSTACK"
+
+/* The name "__vector_table" has special meaning for C-SPY: */
+/* it is where the SP start value is found, and the NVIC vector */
+/* table register (VTOR) is initialized to this address if != 0 */
+
+#pragma section = ".intvec"
+#pragma location = ".intvec"
+const intvec_elem __vector_table[] = {
+	{.__ptr = __sfe("CSTACK")},
+	Reset_Handler,
+
+	NMI_Handler,
+	HardFault_Handler,
+	MemManage_Handler,
+	BusFault_Handler,
+	UsageFault_Handler,
+	0, 0, 0, 0,	/*  Reserved */
+	SVC_Handler,
+	DebugMon_Handler,
+	0,	/*  Reserved */
+	PendSV_Handler,
+	SysTick_Handler,
+
+	/* Configurable interrupts */
+	SUPC_IrqHandler,    /* 0  Supply Controller */
+	RSTC_IrqHandler,    /* 1  Reset Controller */
+	RTC_IrqHandler,	    /* 2  Real Time Clock */
+	RTT_IrqHandler,	    /* 3  Real Time Timer */
+	WDT_IrqHandler,     /* 4  Watchdog Timer */
+	PMC_IrqHandler,	    /* 5  PMC */
+	EFC_IrqHandler,	    /* 6  EEFC */
+	Dummy_Handler,	    /* 7  Reserved */
+	UART0_IrqHandler,	/* 8  UART0 */
+	UART1_IrqHandler,	/* 9  UART1 */
+	Dummy_Handler,	    /* 10 Reserved */
+	PIOA_IrqHandler,	/* 11 Parallel IO Controller A */
+	PIOB_IrqHandler,	/* 12 Parallel IO Controller B */
+	PIOC_IrqHandler,	/* 13 Parallel IO Controller C */
+	USART0_IrqHandler,	/* 14 USART 0 */
+	USART1_IrqHandler,	/* 15 USART 1 */
+	Dummy_Handler,      /* 16 Reserved */
+	Dummy_Handler,      /* 17 Reserved */
+	Dummy_Handler,      /* 18 Reserved */
+	TWI0_IrqHandler,	/* 19 TWI 0 */
+	TWI1_IrqHandler,	/* 20 TWI 1 */
+	SPI_IrqHandler,     /* 21 SPI */
+	Dummy_Handler,      /* 22 Reserved */
+	TC0_IrqHandler,     /* 23 Timer Counter 0 */
+	TC1_IrqHandler,     /* 24 Timer Counter 1 */
+	TC2_IrqHandler,     /* 25 Timer Counter 2 */
+	TC3_IrqHandler,     /* 26 Timer Counter 3 */
+	TC4_IrqHandler,     /* 27 Timer Counter 4 */
+	TC5_IrqHandler,     /* 28 Timer Counter 5 */
+	ADC_IrqHandler,     /* 29 ADC controller */
+	DACC_IrqHandler,	/* 30 DAC controller */
+	PWM_IrqHandler,     /* 31 PWM */
+	Dummy_Handler       /* 32 not used */
+};
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+int __low_level_init(void)
+{
+	uint32_t *pSrc = __section_begin(".intvec");
+
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	return 1; /* if return 0, the data sections will not be initialized */
+}
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+	__iar_program_start();
+}
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/source/templates/system_sam3n.c b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/system_sam3n.c
new file mode 100644
index 000000000..59b99d8a1
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/system_sam3n.c
@@ -0,0 +1,191 @@
+/*! \file *********************************************************************
+ *
+ * \brief Provides the low-level initialization functions that called 
+ * on chip startup.
+ *
+ * $asf_license$
+ *
+ * \par Purpose
+ *
+ * This file provides basic support for Cortex-M processor based 
+ * microcontrollers.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+#include "system_sam3n.h"
+#include "sam3n.h"
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+/* Clock settings (48MHz) */
+#define SYS_BOARD_OSCOUNT   (CKGR_MOR_MOSCXTST(0x8))
+#define SYS_BOARD_PLLAR		(CKGR_PLLAR_ONE \
+							| CKGR_PLLAR_MULA(0x3) \
+							| CKGR_PLLAR_PLLACOUNT(0x3f) \
+							| CKGR_PLLAR_DIVA(0x1))
+#define SYS_BOARD_MCKR      (PMC_MCKR_PRES_CLK_1 | PMC_MCKR_CSS_PLLA_CLK)
+
+/* Clock Definitions */
+#define SYS_FREQ_XTAL_32K      	(32768UL)		/* External 32K crystal frequency */
+#define SYS_FREQ_XTAL_XTAL12M	(12000000UL)	/* External 12M crystal frequency */
+
+#define SYS_FREQ_FWS_0	(21000000UL)	/* Maximum operating frequency when FWS is 0 */
+#define SYS_FREQ_FWS_1	(32000000UL)	/* Maximum operating frequency when FWS is 1 */
+#define SYS_FREQ_FWS_2	(48000000UL)	/* Maximum operating frequency when FWS is 2 */
+
+
+#define SYS_CKGR_MOR_KEY_VALUE	CKGR_MOR_KEY(0x37U) /* Key to unlock MOR register */
+
+/* FIXME: should be generated by sock */
+uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+/**
+ * \brief Setup the microcontroller system.
+ * Initialize the System and update the SystemFrequency variable.
+ */
+void SystemInit(void)
+{
+	/* Set 3 FWS for Embedded Flash Access */
+	EFC->EEFC_FMR = EEFC_FMR_FWS(CHIP_FLASH_WAIT_STATE);
+
+	/* Initialize main oscillator */
+	if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {
+		PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | 
+			                     CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
+		while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
+		}
+	}
+
+	/* Switch to 3-20MHz Xtal oscillator */
+	PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | 
+	CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
+
+	while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
+	}
+	PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | 
+		                    PMC_MCKR_CSS_MAIN_CLK;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	/* Initialize PLL */
+	PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
+	while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
+	}
+
+	/* Switch to main clock */
+	PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | 
+	PMC_MCKR_CSS_MAIN_CLK;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	/* Switch to PLLA */
+	PMC->PMC_MCKR = SYS_BOARD_MCKR;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	SystemCoreClock = CHIP_FREQ_CPU_MAX;
+}
+
+void SystemCoreClockUpdate(void)
+{
+	/* Determine clock frequency according to clock register values */
+	switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {
+	case PMC_MCKR_CSS_SLOW_CLK:	/* Slow clock */
+		if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
+			SystemCoreClock = SYS_FREQ_XTAL_32K;
+		} else {
+			SystemCoreClock = CHIP_FREQ_SLCK_RC;
+		}
+		break;
+	case PMC_MCKR_CSS_MAIN_CLK:	/* Main clock */
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
+			SystemCoreClock = SYS_FREQ_XTAL_XTAL12M;
+		} else {
+			SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+			switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
+			case CKGR_MOR_MOSCRCF_4_MHz:
+				break;
+			case CKGR_MOR_MOSCRCF_8_MHz:
+				SystemCoreClock *= 2U;
+				break;
+			case CKGR_MOR_MOSCRCF_12_MHz:
+				SystemCoreClock *= 3U;
+				break;
+			default:
+				break;
+			}
+		}
+		break;
+	case PMC_MCKR_CSS_PLLA_CLK:	/* PLLA clock */
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
+			SystemCoreClock = SYS_FREQ_XTAL_XTAL12M;
+		} else {
+			SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+			switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
+			case CKGR_MOR_MOSCRCF_4_MHz:
+				break;
+			case CKGR_MOR_MOSCRCF_8_MHz:
+				SystemCoreClock *= 2U;
+				break;
+			case CKGR_MOR_MOSCRCF_12_MHz:
+				SystemCoreClock *= 3U;
+				break;
+			default:
+				break;
+			}
+		}
+		SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> 
+			                         CKGR_PLLAR_MULA_Pos) + 1U);
+		SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >> 
+			                         CKGR_PLLAR_DIVA_Pos));
+		break;
+	}
+
+	if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
+		SystemCoreClock /= 3U;
+	} else { 
+		SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> 
+			                           PMC_MCKR_PRES_Pos);
+	}
+}
+
+/** 
+ * Initialize flash and watchdog.
+ */
+void system_init_flash_and_watchdog(uint32_t dw_clk)
+{
+	/* Set FWS for embedded Flash access according to operating frequency */
+	if (dw_clk < SYS_FREQ_FWS_0) {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(0);
+	} else if (dw_clk < SYS_FREQ_FWS_1) {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(1);
+	} else if (dw_clk < SYS_FREQ_FWS_2) {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(2);
+	} else {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(3);
+	}
+	
+#ifndef CONFIG_KEEP_WATCHDOG_AFTER_INIT 
+	/* Disable the watchdog */
+	WDT->WDT_MR = WDT_MR_WDDIS;
+#endif
+}
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/source/templates/system_sam3n.h b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/system_sam3n.h
new file mode 100644
index 000000000..a2427b239
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/system_sam3n.h
@@ -0,0 +1,58 @@
+/*! \file *********************************************************************
+ *
+ * \brief CMSIS Cortex-M# Device Peripheral Access Layer Header File
+ *           for SAM3 devices.
+ *
+ * $asf_license$
+ *
+ * \par Purpose
+ *
+ * This file provides basic support for Cortex-M processor based 
+ * microcontrollers.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+#ifndef SYSTEM_SAM3N_H_INCLUDED
+#define SYSTEM_SAM3N_H_INCLUDED
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#include 
+
+extern uint32_t SystemCoreClock;	/* System Clock Frequency (Core Clock) */
+
+/**
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+void SystemInit(void);
+
+/**
+ * @brief Updates the SystemCoreClock with current core Clock 
+ * retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void);
+
+/** 
+ * Initialize flash and watchdog.
+ */
+void system_init_flash_and_watchdog(uint32_t dw_clk);
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#endif /* SYSTEM_SAM3N_H_INCLUDED */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_acc.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_acc.h
new file mode 100644
index 000000000..490c8bfac
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_acc.h
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_ACC_COMPONENT_
+#define _SAM3S_ACC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Analog Comparator Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S_ACC Analog Comparator Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Acc hardware registers */
+typedef struct {
+  WoReg ACC_CR;        /**< \brief (Acc Offset: 0x00) Control Register */
+  RwReg ACC_MR;        /**< \brief (Acc Offset: 0x04) Mode Register */
+  RoReg Reserved1[7];
+  WoReg ACC_IER;       /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */
+  WoReg ACC_IDR;       /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */
+  RoReg ACC_IMR;       /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */
+  RoReg ACC_ISR;       /**< \brief (Acc Offset: 0x30) Interrupt Status Register */
+  RoReg Reserved2[24];
+  RwReg ACC_ACR;       /**< \brief (Acc Offset: 0x94) Analog Control Register */
+  RoReg Reserved3[19];
+  RwReg ACC_WPMR;      /**< \brief (Acc Offset: 0xE4) Write Protect Mode Register */
+  RoReg ACC_WPSR;      /**< \brief (Acc Offset: 0xE8) Write Protect Status Register */
+} Acc;
+#endif /* __ASSEMBLY__ */
+/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */
+#define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) SoftWare ReSeT */
+/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */
+#define ACC_MR_SELMINUS_Pos 0
+#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) SELection for MINUS comparator input */
+#define   ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) SelectTS */
+#define   ACC_MR_SELMINUS_ADVREF (0x1u << 0) /**< \brief (ACC_MR) Select ADVREF */
+#define   ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */
+#define   ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */
+#define   ACC_MR_SELMINUS_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AD0 */
+#define   ACC_MR_SELMINUS_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AD1 */
+#define   ACC_MR_SELMINUS_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AD2 */
+#define   ACC_MR_SELMINUS_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AD3 */
+#define ACC_MR_SELPLUS_Pos 4
+#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) SELection for PLUS comparator input */
+#define   ACC_MR_SELPLUS_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AD0 */
+#define   ACC_MR_SELPLUS_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AD1 */
+#define   ACC_MR_SELPLUS_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AD2 */
+#define   ACC_MR_SELPLUS_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AD3 */
+#define   ACC_MR_SELPLUS_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AD4 */
+#define   ACC_MR_SELPLUS_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AD5 */
+#define   ACC_MR_SELPLUS_AD6 (0x6u << 4) /**< \brief (ACC_MR) Select AD6 */
+#define   ACC_MR_SELPLUS_AD7 (0x7u << 4) /**< \brief (ACC_MR) Select AD7 */
+#define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator ENable */
+#define   ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog Comparator Disabled. */
+#define   ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enabled. */
+#define ACC_MR_EDGETYP_Pos 9
+#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) EDGE TYPe */
+#define   ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) only rising edge of comparator output */
+#define   ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) falling edge of comparator output */
+#define   ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) any edge of comparator output */
+#define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) INVert comparator output */
+#define   ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog Comparator output is directly processed. */
+#define   ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog Comparator output is inverted prior to being processed. */
+#define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) SELection of Fault Source */
+#define   ACC_MR_SELFS_CF (0x0u << 13) /**< \brief (ACC_MR) the CF flag is used to drive the FAULT output. */
+#define   ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) the output of the Analog Comparator flag is used to drive the FAULT output. */
+#define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */
+#define   ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) the FAULT output is tied to 0. */
+#define   ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) the FAULT output is driven by the signal defined by SELFS. */
+/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */
+#define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */
+/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */
+#define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */
+/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */
+#define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */
+/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */
+#define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge */
+#define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */
+#define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR)  */
+/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */
+#define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current SELection */
+#define   ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) low power option. */
+#define   ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) high speed option. */
+#define ACC_ACR_HYST_Pos 1
+#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) HYSTeresis selection */
+#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos)))
+/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protect Mode Register -------- */
+#define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protect Enable */
+#define ACC_WPMR_WPKEY_Pos 8
+#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protect KEY */
+#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos)))
+/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protect Status Register -------- */
+#define ACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (ACC_WPSR) Write PROTection ERRor */
+
+/*@}*/
+
+
+#endif /* _SAM3S_ACC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_adc.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_adc.h
new file mode 100644
index 000000000..9137596ad
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_adc.h
@@ -0,0 +1,519 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_ADC_COMPONENT_
+#define _SAM3S_ADC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Analog-to-digital Converter */
+/* ============================================================================= */
+/** \addtogroup SAM3S_ADC Analog-to-digital Converter */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Adc hardware registers */
+typedef struct {
+  WoReg ADC_CR;        /**< \brief (Adc Offset: 0x00) Control Register */
+  RwReg ADC_MR;        /**< \brief (Adc Offset: 0x04) Mode Register */
+  RwReg ADC_SEQR1;     /**< \brief (Adc Offset: 0x08) Channel Sequence Register 1 */
+  RwReg ADC_SEQR2;     /**< \brief (Adc Offset: 0x0C) Channel Sequence Register 2 */
+  WoReg ADC_CHER;      /**< \brief (Adc Offset: 0x10) Channel Enable Register */
+  WoReg ADC_CHDR;      /**< \brief (Adc Offset: 0x14) Channel Disable Register */
+  RoReg ADC_CHSR;      /**< \brief (Adc Offset: 0x18) Channel Status Register */
+  RoReg Reserved1[1];
+  RoReg ADC_LCDR;      /**< \brief (Adc Offset: 0x20) Last Converted Data Register */
+  WoReg ADC_IER;       /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */
+  WoReg ADC_IDR;       /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */
+  RoReg ADC_IMR;       /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */
+  RoReg ADC_ISR;       /**< \brief (Adc Offset: 0x30) Interrupt Status Register */
+  RoReg Reserved2[2];
+  RoReg ADC_OVER;      /**< \brief (Adc Offset: 0x3C) Overrun Status Register */
+  RwReg ADC_EMR;       /**< \brief (Adc Offset: 0x40) Extended Mode Register */
+  RwReg ADC_CWR;       /**< \brief (Adc Offset: 0x44) Compare Window Register */
+  RwReg ADC_CGR;       /**< \brief (Adc Offset: 0x48) Channel Gain Register */
+  RwReg ADC_COR;       /**< \brief (Adc Offset: 0x4C) Channel Offset Register */
+  RoReg ADC_CDR[15];   /**< \brief (Adc Offset: 0x50) Channel Data Register */
+  RoReg Reserved3[2];
+  RwReg ADC_ACR;       /**< \brief (Adc Offset: 0x94) Analog Control Register */
+  RoReg Reserved4[19];
+  RwReg ADC_WPMR;      /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */
+  RoReg ADC_WPSR;      /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved5[5];
+  RwReg ADC_RPR;       /**< \brief (Adc Offset: 0x100) Receive Pointer Register */
+  RwReg ADC_RCR;       /**< \brief (Adc Offset: 0x104) Receive Counter Register */
+  RwReg ADC_TPR;       /**< \brief (Adc Offset: 0x108) Transmit Pointer Register */
+  RwReg ADC_TCR;       /**< \brief (Adc Offset: 0x10C) Transmit Counter Register */
+  RwReg ADC_RNPR;      /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */
+  RwReg ADC_RNCR;      /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */
+  RwReg ADC_TNPR;      /**< \brief (Adc Offset: 0x118) Transmit Next Pointer Register */
+  RwReg ADC_TNCR;      /**< \brief (Adc Offset: 0x11C) Transmit Next Counter Register */
+  WoReg ADC_PTCR;      /**< \brief (Adc Offset: 0x120) Transfer Control Register */
+  RoReg ADC_PTSR;      /**< \brief (Adc Offset: 0x124) Transfer Status Register */
+} Adc;
+#endif /* __ASSEMBLY__ */
+/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */
+#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */
+#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */
+/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */
+#define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */
+#define   ADC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */
+#define   ADC_MR_TRGEN_EN (0x1u << 0) /**< \brief (ADC_MR) Hardware trigger selected by TRGSEL field is enabled. */
+#define ADC_MR_TRGSEL_Pos 1
+#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */
+#define   ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC_MR) External trigger */
+#define   ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 0 */
+#define   ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 1 */
+#define   ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 2 */
+#define   ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) /**< \brief (ADC_MR) PWM Event Line 0 */
+#define   ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) /**< \brief (ADC_MR) PWM Event Line 1 */
+#define ADC_MR_LOWRES (0x1u << 4) /**< \brief (ADC_MR) Resolution */
+#define   ADC_MR_LOWRES_BITS_12 (0x0u << 4) /**< \brief (ADC_MR) 12-bit resolution */
+#define   ADC_MR_LOWRES_BITS_10 (0x1u << 4) /**< \brief (ADC_MR) 10-bit resolution */
+#define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */
+#define   ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions */
+#define   ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions */
+#define ADC_MR_FWUP (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up */
+#define   ADC_MR_FWUP_OFF (0x0u << 6) /**< \brief (ADC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit */
+#define   ADC_MR_FWUP_ON (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF */
+#define ADC_MR_FREERUN (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode */
+#define   ADC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (ADC_MR) Normal Mode */
+#define   ADC_MR_FREERUN_ON (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode: Never wait for any trigger. */
+#define ADC_MR_PRESCAL_Pos 8
+#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */
+#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos)))
+#define ADC_MR_STARTUP_Pos 16
+#define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */
+#define   ADC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (ADC_MR) 0 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (ADC_MR) 8 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (ADC_MR) 16 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (ADC_MR) 24 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (ADC_MR) 64 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (ADC_MR) 80 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (ADC_MR) 96 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (ADC_MR) 112 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (ADC_MR) 512 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (ADC_MR) 576 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (ADC_MR) 640 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (ADC_MR) 704 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (ADC_MR) 768 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (ADC_MR) 832 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (ADC_MR) 896 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (ADC_MR) 960 periods of ADCClock */
+#define ADC_MR_SETTLING_Pos 20
+#define ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos) /**< \brief (ADC_MR) Analog Settling Time */
+#define   ADC_MR_SETTLING_AST3 (0x0u << 20) /**< \brief (ADC_MR) 3 periods of ADCClock */
+#define   ADC_MR_SETTLING_AST5 (0x1u << 20) /**< \brief (ADC_MR) 5 periods of ADCClock */
+#define   ADC_MR_SETTLING_AST9 (0x2u << 20) /**< \brief (ADC_MR) 9 periods of ADCClock */
+#define   ADC_MR_SETTLING_AST17 (0x3u << 20) /**< \brief (ADC_MR) 17 periods of ADCClock */
+#define ADC_MR_ANACH (0x1u << 23) /**< \brief (ADC_MR) Analog Change */
+#define   ADC_MR_ANACH_NONE (0x0u << 23) /**< \brief (ADC_MR) No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels */
+#define   ADC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (ADC_MR) Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers */
+#define ADC_MR_TRACKTIM_Pos 24
+#define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) /**< \brief (ADC_MR) Tracking Time */
+#define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos)))
+#define ADC_MR_TRANSFER_Pos 28
+#define ADC_MR_TRANSFER_Msk (0x3u << ADC_MR_TRANSFER_Pos) /**< \brief (ADC_MR) Transfer Period */
+#define ADC_MR_TRANSFER(value) ((ADC_MR_TRANSFER_Msk & ((value) << ADC_MR_TRANSFER_Pos)))
+#define ADC_MR_USEQ (0x1u << 31) /**< \brief (ADC_MR) Use Sequence Enable */
+#define   ADC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (ADC_MR) Normal Mode: The controller converts channels in a simple numeric order. */
+#define   ADC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers. */
+/* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */
+#define ADC_SEQR1_USCH1_Pos 0
+#define ADC_SEQR1_USCH1_Msk (0x7u << ADC_SEQR1_USCH1_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 1 */
+#define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos)))
+#define ADC_SEQR1_USCH2_Pos 4
+#define ADC_SEQR1_USCH2_Msk (0x7u << ADC_SEQR1_USCH2_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 2 */
+#define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos)))
+#define ADC_SEQR1_USCH3_Pos 8
+#define ADC_SEQR1_USCH3_Msk (0x7u << ADC_SEQR1_USCH3_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 3 */
+#define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos)))
+#define ADC_SEQR1_USCH4_Pos 12
+#define ADC_SEQR1_USCH4_Msk (0x7u << ADC_SEQR1_USCH4_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 4 */
+#define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos)))
+#define ADC_SEQR1_USCH5_Pos 16
+#define ADC_SEQR1_USCH5_Msk (0x7u << ADC_SEQR1_USCH5_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 5 */
+#define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos)))
+#define ADC_SEQR1_USCH6_Pos 20
+#define ADC_SEQR1_USCH6_Msk (0x7u << ADC_SEQR1_USCH6_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 6 */
+#define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos)))
+#define ADC_SEQR1_USCH7_Pos 24
+#define ADC_SEQR1_USCH7_Msk (0x7u << ADC_SEQR1_USCH7_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 7 */
+#define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos)))
+#define ADC_SEQR1_USCH8_Pos 28
+#define ADC_SEQR1_USCH8_Msk (0x7u << ADC_SEQR1_USCH8_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 8 */
+#define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos)))
+/* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */
+#define ADC_SEQR2_USCH9_Pos 0
+#define ADC_SEQR2_USCH9_Msk (0x7u << ADC_SEQR2_USCH9_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 9 */
+#define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos)))
+#define ADC_SEQR2_USCH10_Pos 4
+#define ADC_SEQR2_USCH10_Msk (0x7u << ADC_SEQR2_USCH10_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 10 */
+#define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos)))
+#define ADC_SEQR2_USCH11_Pos 8
+#define ADC_SEQR2_USCH11_Msk (0x7u << ADC_SEQR2_USCH11_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 11 */
+#define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos)))
+#define ADC_SEQR2_USCH12_Pos 12
+#define ADC_SEQR2_USCH12_Msk (0x7u << ADC_SEQR2_USCH12_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 12 */
+#define ADC_SEQR2_USCH12(value) ((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos)))
+#define ADC_SEQR2_USCH13_Pos 16
+#define ADC_SEQR2_USCH13_Msk (0x7u << ADC_SEQR2_USCH13_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 13 */
+#define ADC_SEQR2_USCH13(value) ((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos)))
+#define ADC_SEQR2_USCH14_Pos 20
+#define ADC_SEQR2_USCH14_Msk (0x7u << ADC_SEQR2_USCH14_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 14 */
+#define ADC_SEQR2_USCH14(value) ((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos)))
+#define ADC_SEQR2_USCH15_Pos 24
+#define ADC_SEQR2_USCH15_Msk (0x7u << ADC_SEQR2_USCH15_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 15 */
+#define ADC_SEQR2_USCH15(value) ((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos)))
+#define ADC_SEQR2_USCH16_Pos 28
+#define ADC_SEQR2_USCH16_Msk (0x7u << ADC_SEQR2_USCH16_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 16 */
+#define ADC_SEQR2_USCH16(value) ((ADC_SEQR2_USCH16_Msk & ((value) << ADC_SEQR2_USCH16_Pos)))
+/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */
+#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */
+#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */
+#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */
+#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */
+#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */
+#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */
+#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */
+#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */
+#define ADC_CHER_CH8 (0x1u << 8) /**< \brief (ADC_CHER) Channel 8 Enable */
+#define ADC_CHER_CH9 (0x1u << 9) /**< \brief (ADC_CHER) Channel 9 Enable */
+#define ADC_CHER_CH10 (0x1u << 10) /**< \brief (ADC_CHER) Channel 10 Enable */
+#define ADC_CHER_CH11 (0x1u << 11) /**< \brief (ADC_CHER) Channel 11 Enable */
+#define ADC_CHER_CH12 (0x1u << 12) /**< \brief (ADC_CHER) Channel 12 Enable */
+#define ADC_CHER_CH13 (0x1u << 13) /**< \brief (ADC_CHER) Channel 13 Enable */
+#define ADC_CHER_CH14 (0x1u << 14) /**< \brief (ADC_CHER) Channel 14 Enable */
+#define ADC_CHER_CH15 (0x1u << 15) /**< \brief (ADC_CHER) Channel 15 Enable */
+/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */
+#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */
+#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */
+#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */
+#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */
+#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */
+#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */
+#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */
+#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */
+#define ADC_CHDR_CH8 (0x1u << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */
+#define ADC_CHDR_CH9 (0x1u << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */
+#define ADC_CHDR_CH10 (0x1u << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */
+#define ADC_CHDR_CH11 (0x1u << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */
+#define ADC_CHDR_CH12 (0x1u << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */
+#define ADC_CHDR_CH13 (0x1u << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */
+#define ADC_CHDR_CH14 (0x1u << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */
+#define ADC_CHDR_CH15 (0x1u << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */
+/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */
+#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */
+#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */
+#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */
+#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */
+#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */
+#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */
+#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */
+#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */
+#define ADC_CHSR_CH8 (0x1u << 8) /**< \brief (ADC_CHSR) Channel 8 Status */
+#define ADC_CHSR_CH9 (0x1u << 9) /**< \brief (ADC_CHSR) Channel 9 Status */
+#define ADC_CHSR_CH10 (0x1u << 10) /**< \brief (ADC_CHSR) Channel 10 Status */
+#define ADC_CHSR_CH11 (0x1u << 11) /**< \brief (ADC_CHSR) Channel 11 Status */
+#define ADC_CHSR_CH12 (0x1u << 12) /**< \brief (ADC_CHSR) Channel 12 Status */
+#define ADC_CHSR_CH13 (0x1u << 13) /**< \brief (ADC_CHSR) Channel 13 Status */
+#define ADC_CHSR_CH14 (0x1u << 14) /**< \brief (ADC_CHSR) Channel 14 Status */
+#define ADC_CHSR_CH15 (0x1u << 15) /**< \brief (ADC_CHSR) Channel 15 Status */
+/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */
+#define ADC_LCDR_LDATA_Pos 0
+#define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */
+#define ADC_LCDR_CHNB_Pos 12
+#define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) /**< \brief (ADC_LCDR) Channel Number */
+/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */
+#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */
+#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */
+#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */
+#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */
+#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */
+#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */
+#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */
+#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */
+#define ADC_IER_EOC8 (0x1u << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */
+#define ADC_IER_EOC9 (0x1u << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */
+#define ADC_IER_EOC10 (0x1u << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */
+#define ADC_IER_EOC11 (0x1u << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */
+#define ADC_IER_EOC12 (0x1u << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */
+#define ADC_IER_EOC13 (0x1u << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */
+#define ADC_IER_EOC14 (0x1u << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */
+#define ADC_IER_EOC15 (0x1u << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */
+#define ADC_IER_DRDY (0x1u << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */
+#define ADC_IER_GOVRE (0x1u << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */
+#define ADC_IER_COMPE (0x1u << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */
+#define ADC_IER_ENDRX (0x1u << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */
+#define ADC_IER_RXBUFF (0x1u << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */
+/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */
+#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */
+#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */
+#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */
+#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */
+#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */
+#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */
+#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */
+#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */
+#define ADC_IDR_EOC8 (0x1u << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */
+#define ADC_IDR_EOC9 (0x1u << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */
+#define ADC_IDR_EOC10 (0x1u << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */
+#define ADC_IDR_EOC11 (0x1u << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */
+#define ADC_IDR_EOC12 (0x1u << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */
+#define ADC_IDR_EOC13 (0x1u << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */
+#define ADC_IDR_EOC14 (0x1u << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */
+#define ADC_IDR_EOC15 (0x1u << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */
+#define ADC_IDR_DRDY (0x1u << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */
+#define ADC_IDR_GOVRE (0x1u << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */
+#define ADC_IDR_COMPE (0x1u << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */
+#define ADC_IDR_ENDRX (0x1u << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */
+#define ADC_IDR_RXBUFF (0x1u << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */
+/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */
+#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */
+#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */
+#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */
+#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */
+#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */
+#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */
+#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */
+#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */
+#define ADC_IMR_EOC8 (0x1u << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */
+#define ADC_IMR_EOC9 (0x1u << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */
+#define ADC_IMR_EOC10 (0x1u << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */
+#define ADC_IMR_EOC11 (0x1u << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */
+#define ADC_IMR_EOC12 (0x1u << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */
+#define ADC_IMR_EOC13 (0x1u << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */
+#define ADC_IMR_EOC14 (0x1u << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */
+#define ADC_IMR_EOC15 (0x1u << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */
+#define ADC_IMR_DRDY (0x1u << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */
+#define ADC_IMR_GOVRE (0x1u << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */
+#define ADC_IMR_COMPE (0x1u << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */
+#define ADC_IMR_ENDRX (0x1u << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */
+#define ADC_IMR_RXBUFF (0x1u << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */
+/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */
+#define ADC_ISR_EOC0 (0x1u << 0) /**< \brief (ADC_ISR) End of Conversion 0 */
+#define ADC_ISR_EOC1 (0x1u << 1) /**< \brief (ADC_ISR) End of Conversion 1 */
+#define ADC_ISR_EOC2 (0x1u << 2) /**< \brief (ADC_ISR) End of Conversion 2 */
+#define ADC_ISR_EOC3 (0x1u << 3) /**< \brief (ADC_ISR) End of Conversion 3 */
+#define ADC_ISR_EOC4 (0x1u << 4) /**< \brief (ADC_ISR) End of Conversion 4 */
+#define ADC_ISR_EOC5 (0x1u << 5) /**< \brief (ADC_ISR) End of Conversion 5 */
+#define ADC_ISR_EOC6 (0x1u << 6) /**< \brief (ADC_ISR) End of Conversion 6 */
+#define ADC_ISR_EOC7 (0x1u << 7) /**< \brief (ADC_ISR) End of Conversion 7 */
+#define ADC_ISR_EOC8 (0x1u << 8) /**< \brief (ADC_ISR) End of Conversion 8 */
+#define ADC_ISR_EOC9 (0x1u << 9) /**< \brief (ADC_ISR) End of Conversion 9 */
+#define ADC_ISR_EOC10 (0x1u << 10) /**< \brief (ADC_ISR) End of Conversion 10 */
+#define ADC_ISR_EOC11 (0x1u << 11) /**< \brief (ADC_ISR) End of Conversion 11 */
+#define ADC_ISR_EOC12 (0x1u << 12) /**< \brief (ADC_ISR) End of Conversion 12 */
+#define ADC_ISR_EOC13 (0x1u << 13) /**< \brief (ADC_ISR) End of Conversion 13 */
+#define ADC_ISR_EOC14 (0x1u << 14) /**< \brief (ADC_ISR) End of Conversion 14 */
+#define ADC_ISR_EOC15 (0x1u << 15) /**< \brief (ADC_ISR) End of Conversion 15 */
+#define ADC_ISR_DRDY (0x1u << 24) /**< \brief (ADC_ISR) Data Ready */
+#define ADC_ISR_GOVRE (0x1u << 25) /**< \brief (ADC_ISR) General Overrun Error */
+#define ADC_ISR_COMPE (0x1u << 26) /**< \brief (ADC_ISR) Comparison Error */
+#define ADC_ISR_ENDRX (0x1u << 27) /**< \brief (ADC_ISR) End of RX Buffer */
+#define ADC_ISR_RXBUFF (0x1u << 28) /**< \brief (ADC_ISR) RX Buffer Full */
+/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */
+#define ADC_OVER_OVRE0 (0x1u << 0) /**< \brief (ADC_OVER) Overrun Error 0 */
+#define ADC_OVER_OVRE1 (0x1u << 1) /**< \brief (ADC_OVER) Overrun Error 1 */
+#define ADC_OVER_OVRE2 (0x1u << 2) /**< \brief (ADC_OVER) Overrun Error 2 */
+#define ADC_OVER_OVRE3 (0x1u << 3) /**< \brief (ADC_OVER) Overrun Error 3 */
+#define ADC_OVER_OVRE4 (0x1u << 4) /**< \brief (ADC_OVER) Overrun Error 4 */
+#define ADC_OVER_OVRE5 (0x1u << 5) /**< \brief (ADC_OVER) Overrun Error 5 */
+#define ADC_OVER_OVRE6 (0x1u << 6) /**< \brief (ADC_OVER) Overrun Error 6 */
+#define ADC_OVER_OVRE7 (0x1u << 7) /**< \brief (ADC_OVER) Overrun Error 7 */
+#define ADC_OVER_OVRE8 (0x1u << 8) /**< \brief (ADC_OVER) Overrun Error 8 */
+#define ADC_OVER_OVRE9 (0x1u << 9) /**< \brief (ADC_OVER) Overrun Error 9 */
+#define ADC_OVER_OVRE10 (0x1u << 10) /**< \brief (ADC_OVER) Overrun Error 10 */
+#define ADC_OVER_OVRE11 (0x1u << 11) /**< \brief (ADC_OVER) Overrun Error 11 */
+#define ADC_OVER_OVRE12 (0x1u << 12) /**< \brief (ADC_OVER) Overrun Error 12 */
+#define ADC_OVER_OVRE13 (0x1u << 13) /**< \brief (ADC_OVER) Overrun Error 13 */
+#define ADC_OVER_OVRE14 (0x1u << 14) /**< \brief (ADC_OVER) Overrun Error 14 */
+#define ADC_OVER_OVRE15 (0x1u << 15) /**< \brief (ADC_OVER) Overrun Error 15 */
+/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */
+#define ADC_EMR_CMPMODE_Pos 0
+#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /**< \brief (ADC_EMR) Comparison Mode */
+#define   ADC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */
+#define   ADC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */
+#define   ADC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is in the comparison window. */
+#define   ADC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is out of the comparison window. */
+#define ADC_EMR_CMPSEL_Pos 4
+#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /**< \brief (ADC_EMR) Comparison Selected Channel */
+#define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos)))
+#define ADC_EMR_CMPALL (0x1u << 9) /**< \brief (ADC_EMR) Compare All Channels */
+#define ADC_EMR_TAG (0x1u << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */
+/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */
+#define ADC_CWR_LOWTHRES_Pos 0
+#define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) /**< \brief (ADC_CWR) Low Threshold */
+#define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos)))
+#define ADC_CWR_HIGHTHRES_Pos 16
+#define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) /**< \brief (ADC_CWR) High Threshold */
+#define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos)))
+/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */
+#define ADC_CGR_GAIN0_Pos 0
+#define ADC_CGR_GAIN0_Msk (0x3u << ADC_CGR_GAIN0_Pos) /**< \brief (ADC_CGR) Gain for channel 0 */
+#define ADC_CGR_GAIN0(value) ((ADC_CGR_GAIN0_Msk & ((value) << ADC_CGR_GAIN0_Pos)))
+#define ADC_CGR_GAIN1_Pos 2
+#define ADC_CGR_GAIN1_Msk (0x3u << ADC_CGR_GAIN1_Pos) /**< \brief (ADC_CGR) Gain for channel 1 */
+#define ADC_CGR_GAIN1(value) ((ADC_CGR_GAIN1_Msk & ((value) << ADC_CGR_GAIN1_Pos)))
+#define ADC_CGR_GAIN2_Pos 4
+#define ADC_CGR_GAIN2_Msk (0x3u << ADC_CGR_GAIN2_Pos) /**< \brief (ADC_CGR) Gain for channel 2 */
+#define ADC_CGR_GAIN2(value) ((ADC_CGR_GAIN2_Msk & ((value) << ADC_CGR_GAIN2_Pos)))
+#define ADC_CGR_GAIN3_Pos 6
+#define ADC_CGR_GAIN3_Msk (0x3u << ADC_CGR_GAIN3_Pos) /**< \brief (ADC_CGR) Gain for channel 3 */
+#define ADC_CGR_GAIN3(value) ((ADC_CGR_GAIN3_Msk & ((value) << ADC_CGR_GAIN3_Pos)))
+#define ADC_CGR_GAIN4_Pos 8
+#define ADC_CGR_GAIN4_Msk (0x3u << ADC_CGR_GAIN4_Pos) /**< \brief (ADC_CGR) Gain for channel 4 */
+#define ADC_CGR_GAIN4(value) ((ADC_CGR_GAIN4_Msk & ((value) << ADC_CGR_GAIN4_Pos)))
+#define ADC_CGR_GAIN5_Pos 10
+#define ADC_CGR_GAIN5_Msk (0x3u << ADC_CGR_GAIN5_Pos) /**< \brief (ADC_CGR) Gain for channel 5 */
+#define ADC_CGR_GAIN5(value) ((ADC_CGR_GAIN5_Msk & ((value) << ADC_CGR_GAIN5_Pos)))
+#define ADC_CGR_GAIN6_Pos 12
+#define ADC_CGR_GAIN6_Msk (0x3u << ADC_CGR_GAIN6_Pos) /**< \brief (ADC_CGR) Gain for channel 6 */
+#define ADC_CGR_GAIN6(value) ((ADC_CGR_GAIN6_Msk & ((value) << ADC_CGR_GAIN6_Pos)))
+#define ADC_CGR_GAIN7_Pos 14
+#define ADC_CGR_GAIN7_Msk (0x3u << ADC_CGR_GAIN7_Pos) /**< \brief (ADC_CGR) Gain for channel 7 */
+#define ADC_CGR_GAIN7(value) ((ADC_CGR_GAIN7_Msk & ((value) << ADC_CGR_GAIN7_Pos)))
+#define ADC_CGR_GAIN8_Pos 16
+#define ADC_CGR_GAIN8_Msk (0x3u << ADC_CGR_GAIN8_Pos) /**< \brief (ADC_CGR) Gain for channel 8 */
+#define ADC_CGR_GAIN8(value) ((ADC_CGR_GAIN8_Msk & ((value) << ADC_CGR_GAIN8_Pos)))
+#define ADC_CGR_GAIN9_Pos 18
+#define ADC_CGR_GAIN9_Msk (0x3u << ADC_CGR_GAIN9_Pos) /**< \brief (ADC_CGR) Gain for channel 9 */
+#define ADC_CGR_GAIN9(value) ((ADC_CGR_GAIN9_Msk & ((value) << ADC_CGR_GAIN9_Pos)))
+#define ADC_CGR_GAIN10_Pos 20
+#define ADC_CGR_GAIN10_Msk (0x3u << ADC_CGR_GAIN10_Pos) /**< \brief (ADC_CGR) Gain for channel 10 */
+#define ADC_CGR_GAIN10(value) ((ADC_CGR_GAIN10_Msk & ((value) << ADC_CGR_GAIN10_Pos)))
+#define ADC_CGR_GAIN11_Pos 22
+#define ADC_CGR_GAIN11_Msk (0x3u << ADC_CGR_GAIN11_Pos) /**< \brief (ADC_CGR) Gain for channel 11 */
+#define ADC_CGR_GAIN11(value) ((ADC_CGR_GAIN11_Msk & ((value) << ADC_CGR_GAIN11_Pos)))
+#define ADC_CGR_GAIN12_Pos 24
+#define ADC_CGR_GAIN12_Msk (0x3u << ADC_CGR_GAIN12_Pos) /**< \brief (ADC_CGR) Gain for channel 12 */
+#define ADC_CGR_GAIN12(value) ((ADC_CGR_GAIN12_Msk & ((value) << ADC_CGR_GAIN12_Pos)))
+#define ADC_CGR_GAIN13_Pos 26
+#define ADC_CGR_GAIN13_Msk (0x3u << ADC_CGR_GAIN13_Pos) /**< \brief (ADC_CGR) Gain for channel 13 */
+#define ADC_CGR_GAIN13(value) ((ADC_CGR_GAIN13_Msk & ((value) << ADC_CGR_GAIN13_Pos)))
+#define ADC_CGR_GAIN14_Pos 28
+#define ADC_CGR_GAIN14_Msk (0x3u << ADC_CGR_GAIN14_Pos) /**< \brief (ADC_CGR) Gain for channel 14 */
+#define ADC_CGR_GAIN14(value) ((ADC_CGR_GAIN14_Msk & ((value) << ADC_CGR_GAIN14_Pos)))
+#define ADC_CGR_GAIN15_Pos 30
+#define ADC_CGR_GAIN15_Msk (0x3u << ADC_CGR_GAIN15_Pos) /**< \brief (ADC_CGR) Gain for channel 15 */
+#define ADC_CGR_GAIN15(value) ((ADC_CGR_GAIN15_Msk & ((value) << ADC_CGR_GAIN15_Pos)))
+/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */
+#define ADC_COR_OFF0 (0x1u << 0) /**< \brief (ADC_COR) Offset for channel 0 */
+#define ADC_COR_OFF1 (0x1u << 1) /**< \brief (ADC_COR) Offset for channel 1 */
+#define ADC_COR_OFF2 (0x1u << 2) /**< \brief (ADC_COR) Offset for channel 2 */
+#define ADC_COR_OFF3 (0x1u << 3) /**< \brief (ADC_COR) Offset for channel 3 */
+#define ADC_COR_OFF4 (0x1u << 4) /**< \brief (ADC_COR) Offset for channel 4 */
+#define ADC_COR_OFF5 (0x1u << 5) /**< \brief (ADC_COR) Offset for channel 5 */
+#define ADC_COR_OFF6 (0x1u << 6) /**< \brief (ADC_COR) Offset for channel 6 */
+#define ADC_COR_OFF7 (0x1u << 7) /**< \brief (ADC_COR) Offset for channel 7 */
+#define ADC_COR_OFF8 (0x1u << 8) /**< \brief (ADC_COR) Offset for channel 8 */
+#define ADC_COR_OFF9 (0x1u << 9) /**< \brief (ADC_COR) Offset for channel 9 */
+#define ADC_COR_OFF10 (0x1u << 10) /**< \brief (ADC_COR) Offset for channel 10 */
+#define ADC_COR_OFF11 (0x1u << 11) /**< \brief (ADC_COR) Offset for channel 11 */
+#define ADC_COR_OFF12 (0x1u << 12) /**< \brief (ADC_COR) Offset for channel 12 */
+#define ADC_COR_OFF13 (0x1u << 13) /**< \brief (ADC_COR) Offset for channel 13 */
+#define ADC_COR_OFF14 (0x1u << 14) /**< \brief (ADC_COR) Offset for channel 14 */
+#define ADC_COR_OFF15 (0x1u << 15) /**< \brief (ADC_COR) Offset for channel 15 */
+#define ADC_COR_DIFF0 (0x1u << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */
+#define ADC_COR_DIFF1 (0x1u << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */
+#define ADC_COR_DIFF2 (0x1u << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */
+#define ADC_COR_DIFF3 (0x1u << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */
+#define ADC_COR_DIFF4 (0x1u << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */
+#define ADC_COR_DIFF5 (0x1u << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */
+#define ADC_COR_DIFF6 (0x1u << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */
+#define ADC_COR_DIFF7 (0x1u << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */
+#define ADC_COR_DIFF8 (0x1u << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */
+#define ADC_COR_DIFF9 (0x1u << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */
+#define ADC_COR_DIFF10 (0x1u << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */
+#define ADC_COR_DIFF11 (0x1u << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */
+#define ADC_COR_DIFF12 (0x1u << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */
+#define ADC_COR_DIFF13 (0x1u << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */
+#define ADC_COR_DIFF14 (0x1u << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */
+#define ADC_COR_DIFF15 (0x1u << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */
+/* -------- ADC_CDR[15] : (ADC Offset: 0x50) Channel Data Register -------- */
+#define ADC_CDR_DATA_Pos 0
+#define ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[15]) Converted Data */
+/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */
+#define ADC_ACR_TSON (0x1u << 4) /**< \brief (ADC_ACR) Temperature Sensor On */
+#define ADC_ACR_IBCTL_Pos 8
+#define ADC_ACR_IBCTL_Msk (0x3u << ADC_ACR_IBCTL_Pos) /**< \brief (ADC_ACR) ADC Bias Current Control */
+#define ADC_ACR_IBCTL(value) ((ADC_ACR_IBCTL_Msk & ((value) << ADC_ACR_IBCTL_Pos)))
+/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */
+#define ADC_WPMR_WPEN (0x1u << 0) /**< \brief (ADC_WPMR) Write Protect Enable */
+#define ADC_WPMR_WPKEY_Pos 8
+#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /**< \brief (ADC_WPMR) Write Protect KEY */
+#define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos)))
+/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */
+#define ADC_WPSR_WPVS (0x1u << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */
+#define ADC_WPSR_WPVSRC_Pos 8
+#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /**< \brief (ADC_WPSR) Write Protect Violation Source */
+/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */
+#define ADC_RPR_RXPTR_Pos 0
+#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */
+#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos)))
+/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */
+#define ADC_RCR_RXCTR_Pos 0
+#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */
+#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos)))
+/* -------- ADC_TPR : (ADC Offset: 0x108) Transmit Pointer Register -------- */
+#define ADC_TPR_TXPTR_Pos 0
+#define ADC_TPR_TXPTR_Msk (0xffffffffu << ADC_TPR_TXPTR_Pos) /**< \brief (ADC_TPR) Transmit Counter Register */
+#define ADC_TPR_TXPTR(value) ((ADC_TPR_TXPTR_Msk & ((value) << ADC_TPR_TXPTR_Pos)))
+/* -------- ADC_TCR : (ADC Offset: 0x10C) Transmit Counter Register -------- */
+#define ADC_TCR_TXCTR_Pos 0
+#define ADC_TCR_TXCTR_Msk (0xffffu << ADC_TCR_TXCTR_Pos) /**< \brief (ADC_TCR) Transmit Counter Register */
+#define ADC_TCR_TXCTR(value) ((ADC_TCR_TXCTR_Msk & ((value) << ADC_TCR_TXCTR_Pos)))
+/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */
+#define ADC_RNPR_RXNPTR_Pos 0
+#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */
+#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos)))
+/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */
+#define ADC_RNCR_RXNCTR_Pos 0
+#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */
+#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos)))
+/* -------- ADC_TNPR : (ADC Offset: 0x118) Transmit Next Pointer Register -------- */
+#define ADC_TNPR_TXNPTR_Pos 0
+#define ADC_TNPR_TXNPTR_Msk (0xffffffffu << ADC_TNPR_TXNPTR_Pos) /**< \brief (ADC_TNPR) Transmit Next Pointer */
+#define ADC_TNPR_TXNPTR(value) ((ADC_TNPR_TXNPTR_Msk & ((value) << ADC_TNPR_TXNPTR_Pos)))
+/* -------- ADC_TNCR : (ADC Offset: 0x11C) Transmit Next Counter Register -------- */
+#define ADC_TNCR_TXNCTR_Pos 0
+#define ADC_TNCR_TXNCTR_Msk (0xffffu << ADC_TNCR_TXNCTR_Pos) /**< \brief (ADC_TNCR) Transmit Counter Next */
+#define ADC_TNCR_TXNCTR(value) ((ADC_TNCR_TXNCTR_Msk & ((value) << ADC_TNCR_TXNCTR_Pos)))
+/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */
+#define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */
+#define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */
+#define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */
+#define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */
+/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */
+#define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */
+#define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S_ADC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_chipid.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_chipid.h
new file mode 100644
index 000000000..a3f52bf5e
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_chipid.h
@@ -0,0 +1,159 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_CHIPID_COMPONENT_
+#define _SAM3S_CHIPID_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Chip Identifier */
+/* ============================================================================= */
+/** \addtogroup SAM3S_CHIPID Chip Identifier */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Chipid hardware registers */
+typedef struct {
+  RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */
+  RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */
+} Chipid;
+#endif /* __ASSEMBLY__ */
+/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */
+#define CHIPID_CIDR_VERSION_Pos 0
+#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */
+#define CHIPID_CIDR_EPROC_Pos 5
+#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */
+#define   CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */
+#define   CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */
+#define   CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */
+#define   CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */
+#define   CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */
+#define   CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */
+#define   CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */
+#define CHIPID_CIDR_NVPSIZ_Pos 8
+#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */
+#define   CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */
+#define   CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define   CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define   CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_NVPSIZ2_Pos 12
+#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */
+#define   CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */
+#define   CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_SRAMSIZ_Pos 16
+#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */
+#define   CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_1K (0x1u << 16) /**< \brief (CHIPID_CIDR) 1K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define CHIPID_CIDR_ARCH_Pos 20
+#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */
+#define   CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */
+#define   CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */
+#define   CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */
+#define   CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */
+#define   CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */
+#define   CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */
+#define   CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */
+#define   CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */
+#define   CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */
+#define   CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM4AxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM4XxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM4XxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxG Series (208/217-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM4XxG Series (208/217-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM3SxASeries (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM4SxA Series (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM3SxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM4SxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM3SxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM4SxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */
+#define   CHIPID_CIDR_ARCH_SAM3NxA (0x93u << 20) /**< \brief (CHIPID_CIDR) SAM3NxA Series (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3NxB (0x94u << 20) /**< \brief (CHIPID_CIDR) SAM3NxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3NxC (0x95u << 20) /**< \brief (CHIPID_CIDR) SAM3NxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */
+#define   CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */
+#define CHIPID_CIDR_NVPTYP_Pos 28
+#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */
+#define   CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */
+#define   CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */
+#define   CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */
+#define   CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size      NVPSIZ2 is Flash size */
+#define   CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */
+#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */
+/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */
+#define CHIPID_EXID_EXID_Pos 0
+#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */
+
+/*@}*/
+
+
+#endif /* _SAM3S_CHIPID_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_crccu.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_crccu.h
new file mode 100644
index 000000000..c53302745
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_crccu.h
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_CRCCU_COMPONENT_
+#define _SAM3S_CRCCU_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */
+/* ============================================================================= */
+/** \addtogroup SAM3S_CRCCU Cyclic Redundancy Check Calculation Unit */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Crccu hardware registers */
+typedef struct {
+  RwReg CRCCU_DSCR;    /**< \brief (Crccu Offset: 0x00000000) CRCCU Descriptor Base Register */
+  RoReg Reserved1[1];
+  WoReg CRCCU_DMA_EN;  /**< \brief (Crccu Offset: 0x00000008) CRCCU DMA Enable Register */
+  WoReg CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x0000000C) CRCCU DMA Disable Register */
+  RoReg CRCCU_DMA_SR;  /**< \brief (Crccu Offset: 0x00000010) CRCCU DMA Status Register */
+  WoReg CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x00000014) CRCCU DMA Interrupt Enable Register */
+  WoReg CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x00000018) CRCCU DMA Interrupt Disable Register */
+  RoReg CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register */
+  RoReg CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x00000020) CRCCU DMA Interrupt Status Register */
+  RoReg Reserved2[4];
+  WoReg CRCCU_CR;      /**< \brief (Crccu Offset: 0x00000034) CRCCU Control Register */
+  RwReg CRCCU_MR;      /**< \brief (Crccu Offset: 0x00000038) CRCCU Mode Register */
+  RoReg CRCCU_SR;      /**< \brief (Crccu Offset: 0x0000003C) CRCCU Status Register */
+  WoReg CRCCU_IER;     /**< \brief (Crccu Offset: 0x00000040) CRCCU Interrupt Enable Register */
+  WoReg CRCCU_IDR;     /**< \brief (Crccu Offset: 0x00000044) CRCCU Interrupt Disable Register */
+  RoReg CRCCU_IMR;     /**< \brief (Crccu Offset: 0x00000048) CRCCU Interrupt Mask Register */
+  RoReg CRCCU_ISR;     /**< \brief (Crccu Offset: 0x0000004C) CRCCU Interrupt Status Register */
+} Crccu;
+#endif /* __ASSEMBLY__ */
+/* -------- CRCCU_DSCR : (CRCCU Offset: 0x00000000) CRCCU Descriptor Base Register -------- */
+#define CRCCU_DSCR_DSCR_Pos 9
+#define CRCCU_DSCR_DSCR_Msk (0x7fffffu << CRCCU_DSCR_DSCR_Pos) /**< \brief (CRCCU_DSCR) Descriptor Base Address */
+#define CRCCU_DSCR_DSCR(value) ((CRCCU_DSCR_DSCR_Msk & ((value) << CRCCU_DSCR_DSCR_Pos)))
+/* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x00000008) CRCCU DMA Enable Register -------- */
+#define CRCCU_DMA_EN_DMAEN (0x1u << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable Register */
+/* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x0000000C) CRCCU DMA Disable Register -------- */
+#define CRCCU_DMA_DIS_DMADIS (0x1u << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable Register */
+/* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x00000010) CRCCU DMA Status Register -------- */
+#define CRCCU_DMA_SR_DMASR (0x1u << 0) /**< \brief (CRCCU_DMA_SR) DMA Status Register */
+/* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x00000014) CRCCU DMA Interrupt Enable Register -------- */
+#define CRCCU_DMA_IER_DMAIER (0x1u << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable register */
+/* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x00000018) CRCCU DMA Interrupt Disable Register -------- */
+#define CRCCU_DMA_IDR_DMAIDR (0x1u << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable register */
+/* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register -------- */
+#define CRCCU_DMA_IMR_DMAIMR (0x1u << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask Register */
+/* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x00000020) CRCCU DMA Interrupt Status Register -------- */
+#define CRCCU_DMA_ISR_DMAISR (0x1u << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status register */
+/* -------- CRCCU_CR : (CRCCU Offset: 0x00000034) CRCCU Control Register -------- */
+#define CRCCU_CR_RESET (0x1u << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */
+/* -------- CRCCU_MR : (CRCCU Offset: 0x00000038) CRCCU Mode Register -------- */
+#define CRCCU_MR_ENABLE (0x1u << 0) /**< \brief (CRCCU_MR) CRC Enable */
+#define CRCCU_MR_COMPARE (0x1u << 1) /**< \brief (CRCCU_MR) CRC Compare */
+#define CRCCU_MR_PTYPE_Pos 2
+#define CRCCU_MR_PTYPE_Msk (0x3u << CRCCU_MR_PTYPE_Pos) /**< \brief (CRCCU_MR) Primitive Polynomial */
+#define   CRCCU_MR_PTYPE_CCITT8023 (0x0u << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */
+#define   CRCCU_MR_PTYPE_CASTAGNOLI (0x1u << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */
+#define   CRCCU_MR_PTYPE_CCITT16 (0x2u << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */
+#define CRCCU_MR_DIVIDER_Pos 4
+#define CRCCU_MR_DIVIDER_Msk (0xfu << CRCCU_MR_DIVIDER_Pos) /**< \brief (CRCCU_MR) Request Divider */
+#define CRCCU_MR_DIVIDER(value) ((CRCCU_MR_DIVIDER_Msk & ((value) << CRCCU_MR_DIVIDER_Pos)))
+/* -------- CRCCU_SR : (CRCCU Offset: 0x0000003C) CRCCU Status Register -------- */
+#define CRCCU_SR_CRC_Pos 0
+#define CRCCU_SR_CRC_Msk (0xffffffffu << CRCCU_SR_CRC_Pos) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */
+/* -------- CRCCU_IER : (CRCCU Offset: 0x00000040) CRCCU Interrupt Enable Register -------- */
+#define CRCCU_IER_ERRIER (0x1u << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */
+/* -------- CRCCU_IDR : (CRCCU Offset: 0x00000044) CRCCU Interrupt Disable Register -------- */
+#define CRCCU_IDR_ERRIDR (0x1u << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */
+/* -------- CRCCU_IMR : (CRCCU Offset: 0x00000048) CRCCU Interrupt Mask Register -------- */
+#define CRCCU_IMR_ERRIMR (0x1u << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */
+/* -------- CRCCU_ISR : (CRCCU Offset: 0x0000004C) CRCCU Interrupt Status Register -------- */
+#define CRCCU_ISR_ERRISR (0x1u << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */
+
+/*@}*/
+
+
+#endif /* _SAM3S_CRCCU_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_dacc.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_dacc.h
new file mode 100644
index 000000000..69271175a
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_dacc.h
@@ -0,0 +1,227 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_DACC_COMPONENT_
+#define _SAM3S_DACC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S_DACC Digital-to-Analog Converter Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Dacc hardware registers */
+typedef struct {
+  WoReg DACC_CR;       /**< \brief (Dacc Offset: 0x00) Control Register */
+  RwReg DACC_MR;       /**< \brief (Dacc Offset: 0x04) Mode Register */
+  RoReg Reserved1[2];
+  WoReg DACC_CHER;     /**< \brief (Dacc Offset: 0x10) Channel Enable Register */
+  WoReg DACC_CHDR;     /**< \brief (Dacc Offset: 0x14) Channel Disable Register */
+  RoReg DACC_CHSR;     /**< \brief (Dacc Offset: 0x18) Channel Status Register */
+  RoReg Reserved2[1];
+  WoReg DACC_CDR;      /**< \brief (Dacc Offset: 0x20) Conversion Data Register */
+  WoReg DACC_IER;      /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */
+  WoReg DACC_IDR;      /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */
+  RoReg DACC_IMR;      /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */
+  RoReg DACC_ISR;      /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */
+  RoReg Reserved3[24];
+  RwReg DACC_ACR;      /**< \brief (Dacc Offset: 0x94) Analog Current Register */
+  RoReg Reserved4[19];
+  RwReg DACC_WPMR;     /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */
+  RoReg DACC_WPSR;     /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */
+  RoReg Reserved5[5];
+  RwReg DACC_RPR;      /**< \brief (Dacc Offset: 0x100) Receive Pointer Register */
+  RwReg DACC_RCR;      /**< \brief (Dacc Offset: 0x104) Receive Counter Register */
+  RwReg DACC_TPR;      /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */
+  RwReg DACC_TCR;      /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */
+  RwReg DACC_RNPR;     /**< \brief (Dacc Offset: 0x110) Receive Next Pointer Register */
+  RwReg DACC_RNCR;     /**< \brief (Dacc Offset: 0x114) Receive Next Counter Register */
+  RwReg DACC_TNPR;     /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */
+  RwReg DACC_TNCR;     /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */
+  WoReg DACC_PTCR;     /**< \brief (Dacc Offset: 0x120) Transfer Control Register */
+  RoReg DACC_PTSR;     /**< \brief (Dacc Offset: 0x124) Transfer Status Register */
+} Dacc;
+#endif /* __ASSEMBLY__ */
+/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */
+#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */
+/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */
+#define DACC_MR_TRGEN (0x1u << 0) /**< \brief (DACC_MR) Trigger Enable */
+#define   DACC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (DACC_MR) External trigger mode disabled. DACC in free running mode. */
+#define   DACC_MR_TRGEN_EN (0x1u << 0) /**< \brief (DACC_MR) External trigger mode enabled. */
+#define DACC_MR_TRGSEL_Pos 1
+#define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) /**< \brief (DACC_MR) Trigger Selection */
+#define DACC_MR_TRGSEL(value) ((DACC_MR_TRGSEL_Msk & ((value) << DACC_MR_TRGSEL_Pos)))
+#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */
+#define   DACC_MR_WORD_HALF (0x0u << 4) /**< \brief (DACC_MR) Half-Word transfer */
+#define   DACC_MR_WORD_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */
+#define DACC_MR_SLEEP (0x1u << 5) /**< \brief (DACC_MR) Sleep Mode */
+#define DACC_MR_FASTWKUP (0x1u << 6) /**< \brief (DACC_MR) Fast Wake up Mode */
+#define DACC_MR_REFRESH_Pos 8
+#define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */
+#define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos)))
+#define DACC_MR_USER_SEL_Pos 16
+#define DACC_MR_USER_SEL_Msk (0x3u << DACC_MR_USER_SEL_Pos) /**< \brief (DACC_MR) User Channel Selection */
+#define   DACC_MR_USER_SEL_CHANNEL0 (0x0u << 16) /**< \brief (DACC_MR) Channel 0 */
+#define   DACC_MR_USER_SEL_CHANNEL1 (0x1u << 16) /**< \brief (DACC_MR) Channel 1 */
+#define DACC_MR_TAG (0x1u << 20) /**< \brief (DACC_MR) Tag Selection Mode */
+#define   DACC_MR_TAG_DIS (0x0u << 20) /**< \brief (DACC_MR) Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. */
+#define   DACC_MR_TAG_EN (0x1u << 20) /**< \brief (DACC_MR) Tag selection mode enabled */
+#define DACC_MR_MAXS (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode */
+#define DACC_MR_STARTUP_Pos 24
+#define DACC_MR_STARTUP_Msk (0x3fu << DACC_MR_STARTUP_Pos) /**< \brief (DACC_MR) Startup Time Selection */
+#define   DACC_MR_STARTUP_0 (0x0u << 24) /**< \brief (DACC_MR) 0 periods of DACClock */
+#define   DACC_MR_STARTUP_8 (0x1u << 24) /**< \brief (DACC_MR) 8 periods of DACClock */
+#define   DACC_MR_STARTUP_16 (0x2u << 24) /**< \brief (DACC_MR) 16 periods of DACClock */
+#define   DACC_MR_STARTUP_24 (0x3u << 24) /**< \brief (DACC_MR) 24 periods of DACClock */
+#define   DACC_MR_STARTUP_64 (0x4u << 24) /**< \brief (DACC_MR) 64 periods of DACClock */
+#define   DACC_MR_STARTUP_80 (0x5u << 24) /**< \brief (DACC_MR) 80 periods of DACClock */
+#define   DACC_MR_STARTUP_96 (0x6u << 24) /**< \brief (DACC_MR) 96 periods of DACClock */
+#define   DACC_MR_STARTUP_112 (0x7u << 24) /**< \brief (DACC_MR) 112 periods of DACClock */
+#define   DACC_MR_STARTUP_512 (0x8u << 24) /**< \brief (DACC_MR) 512 periods of DACClock */
+#define   DACC_MR_STARTUP_576 (0x9u << 24) /**< \brief (DACC_MR) 576 periods of DACClock */
+#define   DACC_MR_STARTUP_640 (0xAu << 24) /**< \brief (DACC_MR) 640 periods of DACClock */
+#define   DACC_MR_STARTUP_704 (0xBu << 24) /**< \brief (DACC_MR) 704 periods of DACClock */
+#define   DACC_MR_STARTUP_768 (0xCu << 24) /**< \brief (DACC_MR) 768 periods of DACClock */
+#define   DACC_MR_STARTUP_832 (0xDu << 24) /**< \brief (DACC_MR) 832 periods of DACClock */
+#define   DACC_MR_STARTUP_896 (0xEu << 24) /**< \brief (DACC_MR) 896 periods of DACClock */
+#define   DACC_MR_STARTUP_960 (0xFu << 24) /**< \brief (DACC_MR) 960 periods of DACClock */
+#define   DACC_MR_STARTUP_1024 (0x10u << 24) /**< \brief (DACC_MR) 1024 periods of DACClock */
+#define   DACC_MR_STARTUP_1088 (0x11u << 24) /**< \brief (DACC_MR) 1088 periods of DACClock */
+#define   DACC_MR_STARTUP_1152 (0x12u << 24) /**< \brief (DACC_MR) 1152 periods of DACClock */
+#define   DACC_MR_STARTUP_1216 (0x13u << 24) /**< \brief (DACC_MR) 1216 periods of DACClock */
+#define   DACC_MR_STARTUP_1280 (0x14u << 24) /**< \brief (DACC_MR) 1280 periods of DACClock */
+#define   DACC_MR_STARTUP_1344 (0x15u << 24) /**< \brief (DACC_MR) 1344 periods of DACClock */
+#define   DACC_MR_STARTUP_1408 (0x16u << 24) /**< \brief (DACC_MR) 1408 periods of DACClock */
+#define   DACC_MR_STARTUP_1472 (0x17u << 24) /**< \brief (DACC_MR) 1472 periods of DACClock */
+#define   DACC_MR_STARTUP_1536 (0x18u << 24) /**< \brief (DACC_MR) 1536 periods of DACClock */
+#define   DACC_MR_STARTUP_1600 (0x19u << 24) /**< \brief (DACC_MR) 1600 periods of DACClock */
+#define   DACC_MR_STARTUP_1664 (0x1Au << 24) /**< \brief (DACC_MR) 1664 periods of DACClock */
+#define   DACC_MR_STARTUP_1728 (0x1Bu << 24) /**< \brief (DACC_MR) 1728 periods of DACClock */
+#define   DACC_MR_STARTUP_1792 (0x1Cu << 24) /**< \brief (DACC_MR) 1792 periods of DACClock */
+#define   DACC_MR_STARTUP_1856 (0x1Du << 24) /**< \brief (DACC_MR) 1856 periods of DACClock */
+#define   DACC_MR_STARTUP_1920 (0x1Eu << 24) /**< \brief (DACC_MR) 1920 periods of DACClock */
+#define   DACC_MR_STARTUP_1984 (0x1Fu << 24) /**< \brief (DACC_MR) 1984 periods of DACClock */
+/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */
+#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */
+#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */
+/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */
+#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */
+#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */
+/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */
+#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */
+#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */
+/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */
+#define DACC_CDR_DATA_Pos 0
+#define DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos) /**< \brief (DACC_CDR) Data to Convert */
+#define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos)))
+/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */
+#define DACC_IER_TXRDY (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */
+#define DACC_IER_EOC (0x1u << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */
+#define DACC_IER_ENDTX (0x1u << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */
+#define DACC_IER_TXBUFE (0x1u << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */
+/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */
+#define DACC_IDR_TXRDY (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */
+#define DACC_IDR_EOC (0x1u << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */
+#define DACC_IDR_ENDTX (0x1u << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */
+#define DACC_IDR_TXBUFE (0x1u << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */
+/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */
+#define DACC_IMR_TXRDY (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */
+#define DACC_IMR_EOC (0x1u << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */
+#define DACC_IMR_ENDTX (0x1u << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */
+#define DACC_IMR_TXBUFE (0x1u << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */
+/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */
+#define DACC_ISR_TXRDY (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */
+#define DACC_ISR_EOC (0x1u << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */
+#define DACC_ISR_ENDTX (0x1u << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */
+#define DACC_ISR_TXBUFE (0x1u << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */
+/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */
+#define DACC_ACR_IBCTLCH0_Pos 0
+#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */
+#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)))
+#define DACC_ACR_IBCTLCH1_Pos 2
+#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */
+#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)))
+#define DACC_ACR_IBCTLDACCORE_Pos 8
+#define DACC_ACR_IBCTLDACCORE_Msk (0x3u << DACC_ACR_IBCTLDACCORE_Pos) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */
+#define DACC_ACR_IBCTLDACCORE(value) ((DACC_ACR_IBCTLDACCORE_Msk & ((value) << DACC_ACR_IBCTLDACCORE_Pos)))
+/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */
+#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protect Enable */
+#define DACC_WPMR_WPKEY_Pos 8
+#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect KEY */
+#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))
+/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */
+#define DACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (DACC_WPSR) Write protection error */
+#define DACC_WPSR_WPROTADDR_Pos 8
+#define DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos) /**< \brief (DACC_WPSR) Write protection error address */
+/* -------- DACC_RPR : (DACC Offset: 0x100) Receive Pointer Register -------- */
+#define DACC_RPR_RXPTR_Pos 0
+#define DACC_RPR_RXPTR_Msk (0xffffffffu << DACC_RPR_RXPTR_Pos) /**< \brief (DACC_RPR) Receive Pointer Register */
+#define DACC_RPR_RXPTR(value) ((DACC_RPR_RXPTR_Msk & ((value) << DACC_RPR_RXPTR_Pos)))
+/* -------- DACC_RCR : (DACC Offset: 0x104) Receive Counter Register -------- */
+#define DACC_RCR_RXCTR_Pos 0
+#define DACC_RCR_RXCTR_Msk (0xffffu << DACC_RCR_RXCTR_Pos) /**< \brief (DACC_RCR) Receive Counter Register */
+#define DACC_RCR_RXCTR(value) ((DACC_RCR_RXCTR_Msk & ((value) << DACC_RCR_RXCTR_Pos)))
+/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */
+#define DACC_TPR_TXPTR_Pos 0
+#define DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos) /**< \brief (DACC_TPR) Transmit Counter Register */
+#define DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos)))
+/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */
+#define DACC_TCR_TXCTR_Pos 0
+#define DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos) /**< \brief (DACC_TCR) Transmit Counter Register */
+#define DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos)))
+/* -------- DACC_RNPR : (DACC Offset: 0x110) Receive Next Pointer Register -------- */
+#define DACC_RNPR_RXNPTR_Pos 0
+#define DACC_RNPR_RXNPTR_Msk (0xffffffffu << DACC_RNPR_RXNPTR_Pos) /**< \brief (DACC_RNPR) Receive Next Pointer */
+#define DACC_RNPR_RXNPTR(value) ((DACC_RNPR_RXNPTR_Msk & ((value) << DACC_RNPR_RXNPTR_Pos)))
+/* -------- DACC_RNCR : (DACC Offset: 0x114) Receive Next Counter Register -------- */
+#define DACC_RNCR_RXNCTR_Pos 0
+#define DACC_RNCR_RXNCTR_Msk (0xffffu << DACC_RNCR_RXNCTR_Pos) /**< \brief (DACC_RNCR) Receive Next Counter */
+#define DACC_RNCR_RXNCTR(value) ((DACC_RNCR_RXNCTR_Msk & ((value) << DACC_RNCR_RXNCTR_Pos)))
+/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */
+#define DACC_TNPR_TXNPTR_Pos 0
+#define DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos) /**< \brief (DACC_TNPR) Transmit Next Pointer */
+#define DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos)))
+/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */
+#define DACC_TNCR_TXNCTR_Pos 0
+#define DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos) /**< \brief (DACC_TNCR) Transmit Counter Next */
+#define DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos)))
+/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */
+#define DACC_PTCR_RXTEN (0x1u << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */
+#define DACC_PTCR_RXTDIS (0x1u << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */
+#define DACC_PTCR_TXTEN (0x1u << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */
+#define DACC_PTCR_TXTDIS (0x1u << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */
+/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */
+#define DACC_PTSR_RXTEN (0x1u << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */
+#define DACC_PTSR_TXTEN (0x1u << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S_DACC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_efc.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_efc.h
new file mode 100644
index 000000000..f3ff9e65e
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_efc.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_EFC_COMPONENT_
+#define _SAM3S_EFC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Embedded Flash Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S_EFC Embedded Flash Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Efc hardware registers */
+typedef struct {
+  RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */
+  WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */
+  RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */
+  RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */
+} Efc;
+#endif /* __ASSEMBLY__ */
+/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
+#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */
+#define EEFC_FMR_FWS_Pos 8
+#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */
+#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))
+#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */
+#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */
+/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
+#define EEFC_FCR_FCMD_Pos 0
+#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */
+#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))
+#define EEFC_FCR_FARG_Pos 8
+#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */
+#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))
+#define EEFC_FCR_FKEY_Pos 24
+#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */
+#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)))
+/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
+#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */
+#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */
+#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */
+/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
+#define EEFC_FRR_FVALUE_Pos 0
+#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */
+
+/*@}*/
+
+
+#endif /* _SAM3S_EFC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_gpbr.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_gpbr.h
new file mode 100644
index 000000000..a7122df98
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_gpbr.h
@@ -0,0 +1,53 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_GPBR_COMPONENT_
+#define _SAM3S_GPBR_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR General Purpose Backup Register */
+/* ============================================================================= */
+/** \addtogroup SAM3S_GPBR General Purpose Backup Register */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Gpbr hardware registers */
+typedef struct {
+  RwReg SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */
+} Gpbr;
+#endif /* __ASSEMBLY__ */
+/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */
+#define SYS_GPBR_GPBR_VALUE_Pos 0
+#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */
+#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3S_GPBR_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_hsmci.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_hsmci.h
new file mode 100644
index 000000000..35e709b39
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_hsmci.h
@@ -0,0 +1,388 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_HSMCI_COMPONENT_
+#define _SAM3S_HSMCI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3S_HSMCI High Speed MultiMedia Card Interface */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Hsmci hardware registers */
+typedef struct {
+  WoReg HSMCI_CR;        /**< \brief (Hsmci Offset: 0x00) Control Register */
+  RwReg HSMCI_MR;        /**< \brief (Hsmci Offset: 0x04) Mode Register */
+  RwReg HSMCI_DTOR;      /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */
+  RwReg HSMCI_SDCR;      /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */
+  RwReg HSMCI_ARGR;      /**< \brief (Hsmci Offset: 0x10) Argument Register */
+  WoReg HSMCI_CMDR;      /**< \brief (Hsmci Offset: 0x14) Command Register */
+  RwReg HSMCI_BLKR;      /**< \brief (Hsmci Offset: 0x18) Block Register */
+  RwReg HSMCI_CSTOR;     /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */
+  RoReg HSMCI_RSPR[4];   /**< \brief (Hsmci Offset: 0x20) Response Register */
+  RoReg HSMCI_RDR;       /**< \brief (Hsmci Offset: 0x30) Receive Data Register */
+  WoReg HSMCI_TDR;       /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */
+  RoReg Reserved1[2];
+  RoReg HSMCI_SR;        /**< \brief (Hsmci Offset: 0x40) Status Register */
+  WoReg HSMCI_IER;       /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */
+  WoReg HSMCI_IDR;       /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */
+  RoReg HSMCI_IMR;       /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */
+  RoReg Reserved2[1];
+  RwReg HSMCI_CFG;       /**< \brief (Hsmci Offset: 0x54) Configuration Register */
+  RoReg Reserved3[35];
+  RwReg HSMCI_WPMR;      /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */
+  RoReg HSMCI_WPSR;      /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */
+  RoReg Reserved4[5];
+  RwReg HSMCI_RPR;       /**< \brief (Hsmci Offset: 0x100) Receive Pointer Register */
+  RwReg HSMCI_RCR;       /**< \brief (Hsmci Offset: 0x104) Receive Counter Register */
+  RwReg HSMCI_TPR;       /**< \brief (Hsmci Offset: 0x108) Transmit Pointer Register */
+  RwReg HSMCI_TCR;       /**< \brief (Hsmci Offset: 0x10C) Transmit Counter Register */
+  RwReg HSMCI_RNPR;      /**< \brief (Hsmci Offset: 0x110) Receive Next Pointer Register */
+  RwReg HSMCI_RNCR;      /**< \brief (Hsmci Offset: 0x114) Receive Next Counter Register */
+  RwReg HSMCI_TNPR;      /**< \brief (Hsmci Offset: 0x118) Transmit Next Pointer Register */
+  RwReg HSMCI_TNCR;      /**< \brief (Hsmci Offset: 0x11C) Transmit Next Counter Register */
+  WoReg HSMCI_PTCR;      /**< \brief (Hsmci Offset: 0x120) Transfer Control Register */
+  RoReg HSMCI_PTSR;      /**< \brief (Hsmci Offset: 0x124) Transfer Status Register */
+  RoReg Reserved5[54];
+  RwReg HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */
+} Hsmci;
+#endif /* __ASSEMBLY__ */
+/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */
+#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */
+#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */
+#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */
+#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */
+#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */
+/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */
+#define HSMCI_MR_CLKDIV_Pos 0
+#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */
+#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))
+#define HSMCI_MR_PWSDIV_Pos 8
+#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */
+#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))
+#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR)  */
+#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR)  */
+#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */
+#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */
+#define HSMCI_MR_PDCMODE (0x1u << 15) /**< \brief (HSMCI_MR) PDC-oriented Mode */
+/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */
+#define HSMCI_DTOR_DTOCYC_Pos 0
+#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */
+#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))
+#define HSMCI_DTOR_DTOMUL_Pos 4
+#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */
+#define   HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */
+#define   HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */
+#define   HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */
+#define   HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */
+#define   HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */
+#define   HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */
+#define   HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */
+#define   HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */
+/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */
+#define HSMCI_SDCR_SDCSEL_Pos 0
+#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */
+#define   HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */
+#define   HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) - */
+#define   HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */
+#define   HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */
+#define HSMCI_SDCR_SDCBUS_Pos 6
+#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */
+#define   HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */
+#define   HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */
+#define   HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */
+/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */
+#define HSMCI_ARGR_ARG_Pos 0
+#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */
+#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))
+/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */
+#define HSMCI_CMDR_CMDNB_Pos 0
+#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */
+#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))
+#define HSMCI_CMDR_RSPTYP_Pos 6
+#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */
+#define   HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */
+#define   HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */
+#define   HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */
+#define   HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */
+#define HSMCI_CMDR_SPCMD_Pos 8
+#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */
+#define   HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */
+#define   HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */
+#define   HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */
+#define   HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */
+#define   HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */
+#define   HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */
+#define   HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */
+#define   HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */
+#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */
+#define   HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */
+#define   HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */
+#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */
+#define   HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */
+#define   HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */
+#define HSMCI_CMDR_TRCMD_Pos 16
+#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */
+#define   HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */
+#define   HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */
+#define   HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */
+#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */
+#define   HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */
+#define   HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */
+#define HSMCI_CMDR_TRTYP_Pos 19
+#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */
+#define   HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */
+#define   HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */
+#define   HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */
+#define   HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */
+#define   HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */
+#define HSMCI_CMDR_IOSPCMD_Pos 24
+#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */
+#define   HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */
+#define   HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */
+#define   HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */
+#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */
+#define   HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */
+#define   HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */
+#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */
+/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */
+#define HSMCI_BLKR_BCNT_Pos 0
+#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */
+#define   HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. */
+#define   HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */
+#define   HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */
+#define HSMCI_BLKR_BLKLEN_Pos 16
+#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */
+#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))
+/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */
+#define HSMCI_CSTOR_CSTOCYC_Pos 0
+#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */
+#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))
+#define HSMCI_CSTOR_CSTOMUL_Pos 4
+#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */
+#define   HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */
+#define   HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */
+#define   HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */
+#define   HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */
+#define   HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */
+#define   HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */
+#define   HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */
+#define   HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */
+/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */
+#define HSMCI_RSPR_RSP_Pos 0
+#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */
+/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */
+#define HSMCI_RDR_DATA_Pos 0
+#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */
+/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */
+#define HSMCI_TDR_DATA_Pos 0
+#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */
+#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))
+/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */
+#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */
+#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */
+#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */
+#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */
+#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */
+#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */
+#define HSMCI_SR_ENDRX (0x1u << 6) /**< \brief (HSMCI_SR) End of RX Buffer */
+#define HSMCI_SR_ENDTX (0x1u << 7) /**< \brief (HSMCI_SR) End of TX Buffer */
+#define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */
+#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */
+#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */
+#define HSMCI_SR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_SR) RX Buffer Full */
+#define HSMCI_SR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_SR) TX Buffer Empty */
+#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */
+#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */
+#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */
+#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */
+#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */
+#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */
+#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */
+#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */
+#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */
+#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */
+#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */
+#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */
+#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */
+#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */
+/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */
+#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */
+#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */
+#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */
+#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */
+#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */
+#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */
+#define HSMCI_IER_ENDRX (0x1u << 6) /**< \brief (HSMCI_IER) End of Receive Buffer Interrupt Enable */
+#define HSMCI_IER_ENDTX (0x1u << 7) /**< \brief (HSMCI_IER) End of Transmit Buffer Interrupt Enable */
+#define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */
+#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */
+#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */
+#define HSMCI_IER_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IER) Receive Buffer Full Interrupt Enable */
+#define HSMCI_IER_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IER) Transmit Buffer Empty Interrupt Enable */
+#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */
+#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */
+#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */
+#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */
+#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */
+#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */
+#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */
+#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */
+#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */
+#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */
+#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */
+#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */
+#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */
+#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */
+/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */
+#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */
+#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */
+#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */
+#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */
+#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */
+#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */
+#define HSMCI_IDR_ENDRX (0x1u << 6) /**< \brief (HSMCI_IDR) End of Receive Buffer Interrupt Disable */
+#define HSMCI_IDR_ENDTX (0x1u << 7) /**< \brief (HSMCI_IDR) End of Transmit Buffer Interrupt Disable */
+#define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */
+#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */
+#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */
+#define HSMCI_IDR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IDR) Receive Buffer Full Interrupt Disable */
+#define HSMCI_IDR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IDR) Transmit Buffer Empty Interrupt Disable */
+#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */
+#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */
+#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */
+#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */
+#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */
+#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */
+#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */
+#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */
+#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */
+#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */
+#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */
+#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */
+#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */
+#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */
+/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */
+#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */
+#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */
+#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */
+#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */
+#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */
+#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */
+#define HSMCI_IMR_ENDRX (0x1u << 6) /**< \brief (HSMCI_IMR) End of Receive Buffer Interrupt Mask */
+#define HSMCI_IMR_ENDTX (0x1u << 7) /**< \brief (HSMCI_IMR) End of Transmit Buffer Interrupt Mask */
+#define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */
+#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */
+#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */
+#define HSMCI_IMR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IMR) Receive Buffer Full Interrupt Mask */
+#define HSMCI_IMR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IMR) Transmit Buffer Empty Interrupt Mask */
+#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */
+#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */
+#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */
+#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */
+#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */
+#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */
+#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */
+#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */
+#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */
+#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */
+#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */
+#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */
+#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */
+#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */
+/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */
+#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */
+#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */
+#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */
+#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */
+/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */
+#define HSMCI_WPMR_WP_EN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */
+#define HSMCI_WPMR_WP_KEY_Pos 8
+#define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) /**< \brief (HSMCI_WPMR) Write Protection Key password */
+#define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos)))
+/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */
+#define HSMCI_WPSR_WP_VS_Pos 0
+#define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */
+#define   HSMCI_WPSR_WP_VS_NONE (0x0u << 0) /**< \brief (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) */
+#define   HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) */
+#define   HSMCI_WPSR_WP_VS_RESET (0x2u << 0) /**< \brief (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). */
+#define   HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) /**< \brief (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. */
+#define HSMCI_WPSR_WP_VSRC_Pos 8
+#define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */
+/* -------- HSMCI_RPR : (HSMCI Offset: 0x100) Receive Pointer Register -------- */
+#define HSMCI_RPR_RXPTR_Pos 0
+#define HSMCI_RPR_RXPTR_Msk (0xffffffffu << HSMCI_RPR_RXPTR_Pos) /**< \brief (HSMCI_RPR) Receive Pointer Register */
+#define HSMCI_RPR_RXPTR(value) ((HSMCI_RPR_RXPTR_Msk & ((value) << HSMCI_RPR_RXPTR_Pos)))
+/* -------- HSMCI_RCR : (HSMCI Offset: 0x104) Receive Counter Register -------- */
+#define HSMCI_RCR_RXCTR_Pos 0
+#define HSMCI_RCR_RXCTR_Msk (0xffffu << HSMCI_RCR_RXCTR_Pos) /**< \brief (HSMCI_RCR) Receive Counter Register */
+#define HSMCI_RCR_RXCTR(value) ((HSMCI_RCR_RXCTR_Msk & ((value) << HSMCI_RCR_RXCTR_Pos)))
+/* -------- HSMCI_TPR : (HSMCI Offset: 0x108) Transmit Pointer Register -------- */
+#define HSMCI_TPR_TXPTR_Pos 0
+#define HSMCI_TPR_TXPTR_Msk (0xffffffffu << HSMCI_TPR_TXPTR_Pos) /**< \brief (HSMCI_TPR) Transmit Counter Register */
+#define HSMCI_TPR_TXPTR(value) ((HSMCI_TPR_TXPTR_Msk & ((value) << HSMCI_TPR_TXPTR_Pos)))
+/* -------- HSMCI_TCR : (HSMCI Offset: 0x10C) Transmit Counter Register -------- */
+#define HSMCI_TCR_TXCTR_Pos 0
+#define HSMCI_TCR_TXCTR_Msk (0xffffu << HSMCI_TCR_TXCTR_Pos) /**< \brief (HSMCI_TCR) Transmit Counter Register */
+#define HSMCI_TCR_TXCTR(value) ((HSMCI_TCR_TXCTR_Msk & ((value) << HSMCI_TCR_TXCTR_Pos)))
+/* -------- HSMCI_RNPR : (HSMCI Offset: 0x110) Receive Next Pointer Register -------- */
+#define HSMCI_RNPR_RXNPTR_Pos 0
+#define HSMCI_RNPR_RXNPTR_Msk (0xffffffffu << HSMCI_RNPR_RXNPTR_Pos) /**< \brief (HSMCI_RNPR) Receive Next Pointer */
+#define HSMCI_RNPR_RXNPTR(value) ((HSMCI_RNPR_RXNPTR_Msk & ((value) << HSMCI_RNPR_RXNPTR_Pos)))
+/* -------- HSMCI_RNCR : (HSMCI Offset: 0x114) Receive Next Counter Register -------- */
+#define HSMCI_RNCR_RXNCTR_Pos 0
+#define HSMCI_RNCR_RXNCTR_Msk (0xffffu << HSMCI_RNCR_RXNCTR_Pos) /**< \brief (HSMCI_RNCR) Receive Next Counter */
+#define HSMCI_RNCR_RXNCTR(value) ((HSMCI_RNCR_RXNCTR_Msk & ((value) << HSMCI_RNCR_RXNCTR_Pos)))
+/* -------- HSMCI_TNPR : (HSMCI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define HSMCI_TNPR_TXNPTR_Pos 0
+#define HSMCI_TNPR_TXNPTR_Msk (0xffffffffu << HSMCI_TNPR_TXNPTR_Pos) /**< \brief (HSMCI_TNPR) Transmit Next Pointer */
+#define HSMCI_TNPR_TXNPTR(value) ((HSMCI_TNPR_TXNPTR_Msk & ((value) << HSMCI_TNPR_TXNPTR_Pos)))
+/* -------- HSMCI_TNCR : (HSMCI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define HSMCI_TNCR_TXNCTR_Pos 0
+#define HSMCI_TNCR_TXNCTR_Msk (0xffffu << HSMCI_TNCR_TXNCTR_Pos) /**< \brief (HSMCI_TNCR) Transmit Counter Next */
+#define HSMCI_TNCR_TXNCTR(value) ((HSMCI_TNCR_TXNCTR_Msk & ((value) << HSMCI_TNCR_TXNCTR_Pos)))
+/* -------- HSMCI_PTCR : (HSMCI Offset: 0x120) Transfer Control Register -------- */
+#define HSMCI_PTCR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTCR) Receiver Transfer Enable */
+#define HSMCI_PTCR_RXTDIS (0x1u << 1) /**< \brief (HSMCI_PTCR) Receiver Transfer Disable */
+#define HSMCI_PTCR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTCR) Transmitter Transfer Enable */
+#define HSMCI_PTCR_TXTDIS (0x1u << 9) /**< \brief (HSMCI_PTCR) Transmitter Transfer Disable */
+/* -------- HSMCI_PTSR : (HSMCI Offset: 0x124) Transfer Status Register -------- */
+#define HSMCI_PTSR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTSR) Receiver Transfer Enable */
+#define HSMCI_PTSR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTSR) Transmitter Transfer Enable */
+/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */
+#define HSMCI_FIFO_DATA_Pos 0
+#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */
+#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3S_HSMCI_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_matrix.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_matrix.h
new file mode 100644
index 000000000..71fcc67dd
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_matrix.h
@@ -0,0 +1,188 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_MATRIX_COMPONENT_
+#define _SAM3S_MATRIX_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR AHB Bus Matrix */
+/* ============================================================================= */
+/** \addtogroup SAM3S_MATRIX AHB Bus Matrix */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Matrix hardware registers */
+typedef struct {
+  RwReg MATRIX_MCFG[4]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */
+  RoReg Reserved1[12];
+  RwReg MATRIX_SCFG[5]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */
+  RoReg Reserved2[11];
+  RwReg MATRIX_PRAS0;   /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */
+  RoReg Reserved3[1];
+  RwReg MATRIX_PRAS1;   /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */
+  RoReg Reserved4[1];
+  RwReg MATRIX_PRAS2;   /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */
+  RoReg Reserved5[1];
+  RwReg MATRIX_PRAS3;   /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */
+  RoReg Reserved6[1];
+  RwReg MATRIX_PRAS4;   /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */
+  RoReg Reserved7[1];
+  RoReg Reserved8[27];
+  RwReg CCFG_SYSIO;     /**< \brief (Matrix Offset: 0x0114) System I/O Configuration register */
+  RoReg Reserved9[1];
+  RwReg CCFG_SMCNFCS;   /**< \brief (Matrix Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register */
+  RoReg Reserved10[49];
+  RwReg MATRIX_WPMR;    /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */
+  RoReg MATRIX_WPSR;    /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */
+} Matrix;
+#endif /* __ASSEMBLY__ */
+/* -------- MATRIX_MCFG[4] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */
+#define MATRIX_MCFG_ULBT_Pos 0
+#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[4]) Undefined Length Burst Type */
+#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))
+/* -------- MATRIX_SCFG[5] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
+#define MATRIX_SCFG_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[5]) Maximum Number of Allowed Cycles for a Burst */
+#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[5]) Default Master Type */
+#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
+#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[5]) Fixed Default Master */
+#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
+#define MATRIX_SCFG_ARBT_Pos 24
+#define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[5]) Arbitration Type */
+#define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos)))
+/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */
+#define MATRIX_PRAS0_M0PR_Pos 0
+#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */
+#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))
+#define MATRIX_PRAS0_M1PR_Pos 4
+#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */
+#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))
+#define MATRIX_PRAS0_M2PR_Pos 8
+#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */
+#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))
+#define MATRIX_PRAS0_M3PR_Pos 12
+#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */
+#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))
+#define MATRIX_PRAS0_M4PR_Pos 16
+#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */
+#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos)))
+/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */
+#define MATRIX_PRAS1_M0PR_Pos 0
+#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */
+#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))
+#define MATRIX_PRAS1_M1PR_Pos 4
+#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */
+#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))
+#define MATRIX_PRAS1_M2PR_Pos 8
+#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */
+#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))
+#define MATRIX_PRAS1_M3PR_Pos 12
+#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */
+#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))
+#define MATRIX_PRAS1_M4PR_Pos 16
+#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */
+#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos)))
+/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */
+#define MATRIX_PRAS2_M0PR_Pos 0
+#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */
+#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))
+#define MATRIX_PRAS2_M1PR_Pos 4
+#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */
+#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))
+#define MATRIX_PRAS2_M2PR_Pos 8
+#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */
+#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))
+#define MATRIX_PRAS2_M3PR_Pos 12
+#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */
+#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))
+#define MATRIX_PRAS2_M4PR_Pos 16
+#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */
+#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos)))
+/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */
+#define MATRIX_PRAS3_M0PR_Pos 0
+#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */
+#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))
+#define MATRIX_PRAS3_M1PR_Pos 4
+#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */
+#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))
+#define MATRIX_PRAS3_M2PR_Pos 8
+#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */
+#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))
+#define MATRIX_PRAS3_M3PR_Pos 12
+#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */
+#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))
+#define MATRIX_PRAS3_M4PR_Pos 16
+#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */
+#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos)))
+/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */
+#define MATRIX_PRAS4_M0PR_Pos 0
+#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */
+#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos)))
+#define MATRIX_PRAS4_M1PR_Pos 4
+#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */
+#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos)))
+#define MATRIX_PRAS4_M2PR_Pos 8
+#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */
+#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos)))
+#define MATRIX_PRAS4_M3PR_Pos 12
+#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */
+#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos)))
+#define MATRIX_PRAS4_M4PR_Pos 16
+#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */
+#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos)))
+/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration register -------- */
+#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */
+#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */
+#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */
+#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */
+#define CCFG_SYSIO_SYSIO10 (0x1u << 10) /**< \brief (CCFG_SYSIO) PB10 or DDM Assignment */
+#define CCFG_SYSIO_SYSIO11 (0x1u << 11) /**< \brief (CCFG_SYSIO) PB11 or DDP Assignment */
+#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */
+/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register -------- */
+#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */
+#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */
+#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */
+#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */
+/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */
+#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */
+#define MATRIX_WPMR_WPKEY_Pos 8
+#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */
+#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
+/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */
+#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */
+#define MATRIX_WPSR_WPVSRC_Pos 8
+#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3S_MATRIX_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_pdc.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_pdc.h
new file mode 100644
index 000000000..ab02d9497
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_pdc.h
@@ -0,0 +1,98 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_PDC_COMPONENT_
+#define _SAM3S_PDC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S_PDC Peripheral DMA Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Pdc hardware registers */
+typedef struct {
+  RwReg PERIPH_RPR;  /**< \brief (Pdc Offset: 0x0) Receive Pointer Register */
+  RwReg PERIPH_RCR;  /**< \brief (Pdc Offset: 0x4) Receive Counter Register */
+  RwReg PERIPH_TPR;  /**< \brief (Pdc Offset: 0x8) Transmit Pointer Register */
+  RwReg PERIPH_TCR;  /**< \brief (Pdc Offset: 0xC) Transmit Counter Register */
+  RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */
+  RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */
+  RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */
+  RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */
+  WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */
+  RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */
+} Pdc;
+#endif /* __ASSEMBLY__ */
+/* -------- PERIPH_RPR : (PDC Offset: 0x0) Receive Pointer Register -------- */
+#define PERIPH_RPR_RXPTR_Pos 0
+#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */
+#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos)))
+/* -------- PERIPH_RCR : (PDC Offset: 0x4) Receive Counter Register -------- */
+#define PERIPH_RCR_RXCTR_Pos 0
+#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */
+#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos)))
+/* -------- PERIPH_TPR : (PDC Offset: 0x8) Transmit Pointer Register -------- */
+#define PERIPH_TPR_TXPTR_Pos 0
+#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */
+#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos)))
+/* -------- PERIPH_TCR : (PDC Offset: 0xC) Transmit Counter Register -------- */
+#define PERIPH_TCR_TXCTR_Pos 0
+#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */
+#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos)))
+/* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */
+#define PERIPH_RNPR_RXNPTR_Pos 0
+#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */
+#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos)))
+/* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */
+#define PERIPH_RNCR_RXNCTR_Pos 0
+#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */
+#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos)))
+/* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */
+#define PERIPH_TNPR_TXNPTR_Pos 0
+#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */
+#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos)))
+/* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */
+#define PERIPH_TNCR_TXNCTR_Pos 0
+#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */
+#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos)))
+/* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */
+#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */
+#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */
+#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */
+#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */
+/* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */
+#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */
+#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S_PDC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_pio.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_pio.h
new file mode 100644
index 000000000..985ca5041
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_pio.h
@@ -0,0 +1,1662 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_PIO_COMPONENT_
+#define _SAM3S_PIO_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S_PIO Parallel Input/Output Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Pio hardware registers */
+typedef struct {
+  WoReg PIO_PER;        /**< \brief (Pio Offset: 0x0000) PIO Enable Register */
+  WoReg PIO_PDR;        /**< \brief (Pio Offset: 0x0004) PIO Disable Register */
+  RoReg PIO_PSR;        /**< \brief (Pio Offset: 0x0008) PIO Status Register */
+  RoReg Reserved1[1];
+  WoReg PIO_OER;        /**< \brief (Pio Offset: 0x0010) Output Enable Register */
+  WoReg PIO_ODR;        /**< \brief (Pio Offset: 0x0014) Output Disable Register */
+  RoReg PIO_OSR;        /**< \brief (Pio Offset: 0x0018) Output Status Register */
+  RoReg Reserved2[1];
+  WoReg PIO_IFER;       /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */
+  WoReg PIO_IFDR;       /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */
+  RoReg PIO_IFSR;       /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */
+  RoReg Reserved3[1];
+  WoReg PIO_SODR;       /**< \brief (Pio Offset: 0x0030) Set Output Data Register */
+  WoReg PIO_CODR;       /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */
+  RwReg PIO_ODSR;       /**< \brief (Pio Offset: 0x0038) Output Data Status Register */
+  RoReg PIO_PDSR;       /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */
+  WoReg PIO_IER;        /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */
+  WoReg PIO_IDR;        /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */
+  RoReg PIO_IMR;        /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */
+  RoReg PIO_ISR;        /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */
+  WoReg PIO_MDER;       /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */
+  WoReg PIO_MDDR;       /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */
+  RoReg PIO_MDSR;       /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */
+  RoReg Reserved4[1];
+  WoReg PIO_PUDR;       /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */
+  WoReg PIO_PUER;       /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */
+  RoReg PIO_PUSR;       /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */
+  RoReg Reserved5[1];
+  RwReg PIO_ABCDSR[2];  /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */
+  RoReg Reserved6[2];
+  WoReg PIO_IFSCDR;     /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */
+  WoReg PIO_IFSCER;     /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */
+  RoReg PIO_IFSCSR;     /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */
+  RwReg PIO_SCDR;       /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */
+  WoReg PIO_PPDDR;      /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */
+  WoReg PIO_PPDER;      /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */
+  RoReg PIO_PPDSR;      /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */
+  RoReg Reserved7[1];
+  WoReg PIO_OWER;       /**< \brief (Pio Offset: 0x00A0) Output Write Enable */
+  WoReg PIO_OWDR;       /**< \brief (Pio Offset: 0x00A4) Output Write Disable */
+  RoReg PIO_OWSR;       /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */
+  RoReg Reserved8[1];
+  WoReg PIO_AIMER;      /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */
+  WoReg PIO_AIMDR;      /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */
+  RoReg PIO_AIMMR;      /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */
+  RoReg Reserved9[1];
+  WoReg PIO_ESR;        /**< \brief (Pio Offset: 0x00C0) Edge Select Register */
+  WoReg PIO_LSR;        /**< \brief (Pio Offset: 0x00C4) Level Select Register */
+  RoReg PIO_ELSR;       /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */
+  RoReg Reserved10[1];
+  WoReg PIO_FELLSR;     /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */
+  WoReg PIO_REHLSR;     /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */
+  RoReg PIO_FRLHSR;     /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */
+  RoReg Reserved11[1];
+  RoReg PIO_LOCKSR;     /**< \brief (Pio Offset: 0x00E0) Lock Status */
+  RwReg PIO_WPMR;       /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */
+  RoReg PIO_WPSR;       /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */
+  RoReg Reserved12[5];
+  RwReg PIO_SCHMITT;    /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */
+  RoReg Reserved13[19];
+  RwReg PIO_PCMR;       /**< \brief (Pio Offset: 0x150) Parallel Capture Mode Register */
+  WoReg PIO_PCIER;      /**< \brief (Pio Offset: 0x154) Parallel Capture Interrupt Enable Register */
+  WoReg PIO_PCIDR;      /**< \brief (Pio Offset: 0x158) Parallel Capture Interrupt Disable Register */
+  RoReg PIO_PCIMR;      /**< \brief (Pio Offset: 0x15C) Parallel Capture Interrupt Mask Register */
+  RoReg PIO_PCISR;      /**< \brief (Pio Offset: 0x160) Parallel Capture Interrupt Status Register */
+  RoReg PIO_PCRHR;      /**< \brief (Pio Offset: 0x164) Parallel Capture Reception Holding Register */
+  RwReg PIO_RPR;        /**< \brief (Pio Offset: 0x168) Receive Pointer Register */
+  RwReg PIO_RCR;        /**< \brief (Pio Offset: 0x16C) Receive Counter Register */
+  RwReg PIO_TPR;        /**< \brief (Pio Offset: 0x170) Transmit Pointer Register */
+  RwReg PIO_TCR;        /**< \brief (Pio Offset: 0x174) Transmit Counter Register */
+  RwReg PIO_RNPR;       /**< \brief (Pio Offset: 0x178) Receive Next Pointer Register */
+  RwReg PIO_RNCR;       /**< \brief (Pio Offset: 0x17C) Receive Next Counter Register */
+  RwReg PIO_TNPR;       /**< \brief (Pio Offset: 0x180) Transmit Next Pointer Register */
+  RwReg PIO_TNCR;       /**< \brief (Pio Offset: 0x184) Transmit Next Counter Register */
+  WoReg PIO_PTCR;       /**< \brief (Pio Offset: 0x188) Transfer Control Register */
+  RoReg PIO_PTSR;       /**< \brief (Pio Offset: 0x18C) Transfer Status Register */
+} Pio;
+#endif /* __ASSEMBLY__ */
+/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */
+#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */
+/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */
+#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */
+/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */
+#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */
+/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */
+#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */
+/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */
+#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */
+/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */
+#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */
+/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */
+#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */
+/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */
+#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */
+/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */
+#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */
+/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */
+#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */
+/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */
+#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */
+/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */
+#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */
+/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */
+#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */
+/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */
+#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */
+#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */
+#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */
+#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */
+#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */
+/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */
+#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */
+#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */
+/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */
+#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */
+/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */
+#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull Up Enable. */
+/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */
+#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull Up Status. */
+/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */
+#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */
+#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */
+#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */
+#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */
+#define PIO_SCDR_DIV_Pos 0
+#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR)  */
+#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)))
+/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */
+#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */
+#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */
+/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */
+#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */
+/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */
+#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable. */
+/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */
+#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable. */
+/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */
+#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status. */
+/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */
+#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */
+#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */
+#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */
+#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */
+#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */
+#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */
+#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */
+#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */
+#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */
+#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status. */
+/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protect Enable */
+#define PIO_WPMR_WPKEY_Pos 8
+#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protect KEY */
+#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)))
+/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */
+#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */
+#define PIO_WPSR_WPVSRC_Pos 8
+#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protect Violation Source */
+/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */
+#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT)  */
+/* -------- PIO_PCMR : (PIO Offset: 0x150) Parallel Capture Mode Register -------- */
+#define PIO_PCMR_PCEN (0x1u << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */
+#define PIO_PCMR_DSIZE_Pos 4
+#define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */
+#define   PIO_PCMR_DSIZE_BYTE (0x0u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR register is a BYTE (8-bit) */
+#define   PIO_PCMR_DSIZE_HALFWORD (0x1u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit) */
+#define   PIO_PCMR_DSIZE_WORD (0x2u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR register is a WORD (32-bit) */
+#define PIO_PCMR_ALWYS (0x1u << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */
+#define PIO_PCMR_HALFS (0x1u << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */
+#define PIO_PCMR_FRSTS (0x1u << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */
+/* -------- PIO_PCIER : (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register -------- */
+#define PIO_PCIER_DRDY (0x1u << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */
+#define PIO_PCIER_OVRE (0x1u << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */
+#define PIO_PCIER_ENDRX (0x1u << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */
+#define PIO_PCIER_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */
+/* -------- PIO_PCIDR : (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register -------- */
+#define PIO_PCIDR_DRDY (0x1u << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */
+#define PIO_PCIDR_OVRE (0x1u << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */
+#define PIO_PCIDR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */
+#define PIO_PCIDR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */
+/* -------- PIO_PCIMR : (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register -------- */
+#define PIO_PCIMR_DRDY (0x1u << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */
+#define PIO_PCIMR_OVRE (0x1u << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */
+#define PIO_PCIMR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */
+#define PIO_PCIMR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */
+/* -------- PIO_PCISR : (PIO Offset: 0x160) Parallel Capture Interrupt Status Register -------- */
+#define PIO_PCISR_DRDY (0x1u << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */
+#define PIO_PCISR_OVRE (0x1u << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error. */
+#define PIO_PCISR_ENDRX (0x1u << 2) /**< \brief (PIO_PCISR) End of Reception Transfer. */
+#define PIO_PCISR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCISR) Reception Buffer Full */
+/* -------- PIO_PCRHR : (PIO Offset: 0x164) Parallel Capture Reception Holding Register -------- */
+#define PIO_PCRHR_RDATA_Pos 0
+#define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data. */
+/* -------- PIO_RPR : (PIO Offset: 0x168) Receive Pointer Register -------- */
+#define PIO_RPR_RXPTR_Pos 0
+#define PIO_RPR_RXPTR_Msk (0xffffffffu << PIO_RPR_RXPTR_Pos) /**< \brief (PIO_RPR) Receive Pointer Register */
+#define PIO_RPR_RXPTR(value) ((PIO_RPR_RXPTR_Msk & ((value) << PIO_RPR_RXPTR_Pos)))
+/* -------- PIO_RCR : (PIO Offset: 0x16C) Receive Counter Register -------- */
+#define PIO_RCR_RXCTR_Pos 0
+#define PIO_RCR_RXCTR_Msk (0xffffu << PIO_RCR_RXCTR_Pos) /**< \brief (PIO_RCR) Receive Counter Register */
+#define PIO_RCR_RXCTR(value) ((PIO_RCR_RXCTR_Msk & ((value) << PIO_RCR_RXCTR_Pos)))
+/* -------- PIO_TPR : (PIO Offset: 0x170) Transmit Pointer Register -------- */
+#define PIO_TPR_TXPTR_Pos 0
+#define PIO_TPR_TXPTR_Msk (0xffffffffu << PIO_TPR_TXPTR_Pos) /**< \brief (PIO_TPR) Transmit Counter Register */
+#define PIO_TPR_TXPTR(value) ((PIO_TPR_TXPTR_Msk & ((value) << PIO_TPR_TXPTR_Pos)))
+/* -------- PIO_TCR : (PIO Offset: 0x174) Transmit Counter Register -------- */
+#define PIO_TCR_TXCTR_Pos 0
+#define PIO_TCR_TXCTR_Msk (0xffffu << PIO_TCR_TXCTR_Pos) /**< \brief (PIO_TCR) Transmit Counter Register */
+#define PIO_TCR_TXCTR(value) ((PIO_TCR_TXCTR_Msk & ((value) << PIO_TCR_TXCTR_Pos)))
+/* -------- PIO_RNPR : (PIO Offset: 0x178) Receive Next Pointer Register -------- */
+#define PIO_RNPR_RXNPTR_Pos 0
+#define PIO_RNPR_RXNPTR_Msk (0xffffffffu << PIO_RNPR_RXNPTR_Pos) /**< \brief (PIO_RNPR) Receive Next Pointer */
+#define PIO_RNPR_RXNPTR(value) ((PIO_RNPR_RXNPTR_Msk & ((value) << PIO_RNPR_RXNPTR_Pos)))
+/* -------- PIO_RNCR : (PIO Offset: 0x17C) Receive Next Counter Register -------- */
+#define PIO_RNCR_RXNCTR_Pos 0
+#define PIO_RNCR_RXNCTR_Msk (0xffffu << PIO_RNCR_RXNCTR_Pos) /**< \brief (PIO_RNCR) Receive Next Counter */
+#define PIO_RNCR_RXNCTR(value) ((PIO_RNCR_RXNCTR_Msk & ((value) << PIO_RNCR_RXNCTR_Pos)))
+/* -------- PIO_TNPR : (PIO Offset: 0x180) Transmit Next Pointer Register -------- */
+#define PIO_TNPR_TXNPTR_Pos 0
+#define PIO_TNPR_TXNPTR_Msk (0xffffffffu << PIO_TNPR_TXNPTR_Pos) /**< \brief (PIO_TNPR) Transmit Next Pointer */
+#define PIO_TNPR_TXNPTR(value) ((PIO_TNPR_TXNPTR_Msk & ((value) << PIO_TNPR_TXNPTR_Pos)))
+/* -------- PIO_TNCR : (PIO Offset: 0x184) Transmit Next Counter Register -------- */
+#define PIO_TNCR_TXNCTR_Pos 0
+#define PIO_TNCR_TXNCTR_Msk (0xffffu << PIO_TNCR_TXNCTR_Pos) /**< \brief (PIO_TNCR) Transmit Counter Next */
+#define PIO_TNCR_TXNCTR(value) ((PIO_TNCR_TXNCTR_Msk & ((value) << PIO_TNCR_TXNCTR_Pos)))
+/* -------- PIO_PTCR : (PIO Offset: 0x188) Transfer Control Register -------- */
+#define PIO_PTCR_RXTEN (0x1u << 0) /**< \brief (PIO_PTCR) Receiver Transfer Enable */
+#define PIO_PTCR_RXTDIS (0x1u << 1) /**< \brief (PIO_PTCR) Receiver Transfer Disable */
+#define PIO_PTCR_TXTEN (0x1u << 8) /**< \brief (PIO_PTCR) Transmitter Transfer Enable */
+#define PIO_PTCR_TXTDIS (0x1u << 9) /**< \brief (PIO_PTCR) Transmitter Transfer Disable */
+/* -------- PIO_PTSR : (PIO Offset: 0x18C) Transfer Status Register -------- */
+#define PIO_PTSR_RXTEN (0x1u << 0) /**< \brief (PIO_PTSR) Receiver Transfer Enable */
+#define PIO_PTSR_TXTEN (0x1u << 8) /**< \brief (PIO_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S_PIO_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_pmc.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_pmc.h
new file mode 100644
index 000000000..c726e5569
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_pmc.h
@@ -0,0 +1,482 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_PMC_COMPONENT_
+#define _SAM3S_PMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Power Management Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S_PMC Power Management Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Pmc hardware registers */
+typedef struct {
+  WoReg PMC_SCER;      /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */
+  WoReg PMC_SCDR;      /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */
+  RoReg PMC_SCSR;      /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */
+  RoReg Reserved1[1];
+  WoReg PMC_PCER0;     /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */
+  WoReg PMC_PCDR0;     /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */
+  RoReg PMC_PCSR0;     /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */
+  RoReg Reserved2[1];
+  RwReg CKGR_MOR;      /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */
+  RoReg CKGR_MCFR;     /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */
+  RwReg CKGR_PLLAR;    /**< \brief (Pmc Offset: 0x0028) PLLA Register */
+  RwReg CKGR_PLLBR;    /**< \brief (Pmc Offset: 0x002C) PLLB Register */
+  RwReg PMC_MCKR;      /**< \brief (Pmc Offset: 0x0030) Master Clock Register */
+  RoReg Reserved3[1];
+  RwReg PMC_USB;       /**< \brief (Pmc Offset: 0x0038) USB Clock Register */
+  RoReg Reserved4[1];
+  RwReg PMC_PCK[3];    /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */
+  RoReg Reserved5[5];
+  WoReg PMC_IER;       /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */
+  WoReg PMC_IDR;       /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */
+  RoReg PMC_SR;        /**< \brief (Pmc Offset: 0x0068) Status Register */
+  RoReg PMC_IMR;       /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */
+  RwReg PMC_FSMR;      /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */
+  RwReg PMC_FSPR;      /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */
+  WoReg PMC_FOCR;      /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */
+  RoReg Reserved6[26];
+  RwReg PMC_WPMR;      /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */
+  RoReg PMC_WPSR;      /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */
+  RoReg Reserved7[5];
+  WoReg PMC_PCER1;     /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */
+  WoReg PMC_PCDR1;     /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */
+  RoReg PMC_PCSR1;     /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */
+  RoReg Reserved8[1];
+  RwReg PMC_OCR;       /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */
+} Pmc;
+#endif /* __ASSEMBLY__ */
+/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
+#define PMC_SCER_UDP (0x1u << 7) /**< \brief (PMC_SCER) USB Device Port Clock Enable */
+#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */
+#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */
+#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */
+/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
+#define PMC_SCDR_UDP (0x1u << 7) /**< \brief (PMC_SCDR) USB Device Port Clock Disable */
+#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */
+#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */
+#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */
+/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
+#define PMC_SCSR_UDP (0x1u << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */
+#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */
+#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */
+#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */
+/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
+#define PMC_PCER0_PID2 (0x1u << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */
+#define PMC_PCER0_PID3 (0x1u << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */
+#define PMC_PCER0_PID4 (0x1u << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */
+#define PMC_PCER0_PID5 (0x1u << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */
+#define PMC_PCER0_PID6 (0x1u << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */
+#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */
+#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */
+#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */
+#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */
+#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */
+#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */
+#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */
+#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */
+#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */
+#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */
+#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */
+#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */
+#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */
+#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */
+#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */
+#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */
+#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */
+#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */
+#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */
+#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */
+#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */
+#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */
+#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */
+#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */
+#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */
+/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
+#define PMC_PCDR0_PID2 (0x1u << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */
+#define PMC_PCDR0_PID3 (0x1u << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */
+#define PMC_PCDR0_PID4 (0x1u << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */
+#define PMC_PCDR0_PID5 (0x1u << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */
+#define PMC_PCDR0_PID6 (0x1u << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */
+#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */
+#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */
+#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */
+#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */
+#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */
+#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */
+#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */
+#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */
+#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */
+#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */
+#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */
+#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */
+#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */
+#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */
+#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */
+#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */
+#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */
+#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */
+#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */
+#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */
+#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */
+#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */
+#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */
+#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */
+#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */
+/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
+#define PMC_PCSR0_PID2 (0x1u << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */
+#define PMC_PCSR0_PID3 (0x1u << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */
+#define PMC_PCSR0_PID4 (0x1u << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */
+#define PMC_PCSR0_PID5 (0x1u << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */
+#define PMC_PCSR0_PID6 (0x1u << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */
+#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */
+#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */
+#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */
+#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */
+#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */
+#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */
+#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */
+#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */
+#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */
+#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */
+#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */
+#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */
+#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */
+#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */
+#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */
+#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */
+#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */
+#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */
+#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */
+#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */
+#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */
+#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */
+#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */
+#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */
+#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */
+/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
+#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */
+#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */
+#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */
+#define CKGR_MOR_MOSCRCF_Pos 4
+#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */
+#define   CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default) */
+#define   CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz */
+#define   CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz */
+#define CKGR_MOR_MOSCXTST_Pos 8
+#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */
+#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
+#define CKGR_MOR_KEY_Pos 16
+#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */
+#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
+#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */
+#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */
+/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
+#define CKGR_MCFR_MAINF_Pos 0
+#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */
+#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */
+/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
+#define CKGR_PLLAR_DIVA_Pos 0
+#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider */
+#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
+#define CKGR_PLLAR_PLLACOUNT_Pos 8
+#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */
+#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
+#define CKGR_PLLAR_MULA_Pos 16
+#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */
+#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
+#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */
+/* -------- CKGR_PLLBR : (PMC Offset: 0x002C) PLLB Register -------- */
+#define CKGR_PLLBR_DIVB_Pos 0
+#define CKGR_PLLBR_DIVB_Msk (0xffu << CKGR_PLLBR_DIVB_Pos) /**< \brief (CKGR_PLLBR) Divider */
+#define CKGR_PLLBR_DIVB(value) ((CKGR_PLLBR_DIVB_Msk & ((value) << CKGR_PLLBR_DIVB_Pos)))
+#define CKGR_PLLBR_PLLBCOUNT_Pos 8
+#define CKGR_PLLBR_PLLBCOUNT_Msk (0x3fu << CKGR_PLLBR_PLLBCOUNT_Pos) /**< \brief (CKGR_PLLBR) PLLB Counter */
+#define CKGR_PLLBR_PLLBCOUNT(value) ((CKGR_PLLBR_PLLBCOUNT_Msk & ((value) << CKGR_PLLBR_PLLBCOUNT_Pos)))
+#define CKGR_PLLBR_MULB_Pos 16
+#define CKGR_PLLBR_MULB_Msk (0x7ffu << CKGR_PLLBR_MULB_Pos) /**< \brief (CKGR_PLLBR) PLLB Multiplier */
+#define CKGR_PLLBR_MULB(value) ((CKGR_PLLBR_MULB_Msk & ((value) << CKGR_PLLBR_MULB_Pos)))
+/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
+#define PMC_MCKR_CSS_Pos 0
+#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */
+#define   PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */
+#define   PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */
+#define   PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */
+#define   PMC_MCKR_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_MCKR) PLLBClock is selected */
+#define PMC_MCKR_PRES_Pos 4
+#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */
+#define   PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */
+#define   PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */
+#define   PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */
+#define   PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */
+#define   PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */
+#define   PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */
+#define   PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */
+#define   PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */
+#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */
+#define PMC_MCKR_PLLBDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) PLLB Divisor by 2 */
+/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */
+#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */
+#define PMC_USB_USBDIV_Pos 8
+#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock. */
+#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))
+/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
+#define PMC_PCK_CSS_Pos 0
+#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */
+#define   PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */
+#define   PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */
+#define   PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */
+#define   PMC_PCK_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) PLLB Clock is selected */
+#define   PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */
+#define PMC_PCK_PRES_Pos 4
+#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */
+#define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos)))
+#define   PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */
+#define   PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */
+#define   PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */
+#define   PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */
+#define   PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */
+#define   PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */
+#define   PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */
+/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
+#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */
+#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */
+#define PMC_IER_LOCKB (0x1u << 2) /**< \brief (PMC_IER) PLLB Lock Interrupt Enable */
+#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */
+#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */
+#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */
+#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */
+#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */
+#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */
+#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */
+/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
+#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */
+#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */
+#define PMC_IDR_LOCKB (0x1u << 2) /**< \brief (PMC_IDR) PLLB Lock Interrupt Disable */
+#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */
+#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */
+#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */
+#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */
+#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */
+#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */
+#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */
+/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
+#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */
+#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */
+#define PMC_SR_LOCKB (0x1u << 2) /**< \brief (PMC_SR) PLLB Lock Status */
+#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */
+#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */
+#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */
+#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */
+#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */
+#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */
+#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */
+/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
+#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */
+#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */
+#define PMC_IMR_LOCKB (0x1u << 2) /**< \brief (PMC_IMR) PLLB Lock Interrupt Mask */
+#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */
+#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */
+#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */
+#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */
+#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */
+#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */
+#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */
+/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
+#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */
+#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */
+#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */
+#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */
+#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */
+#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */
+#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */
+#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */
+#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */
+#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */
+#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */
+#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */
+#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */
+#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */
+#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */
+#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */
+#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */
+#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */
+#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */
+#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low Power Mode */
+/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
+#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
+#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */
+/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */
+#define PMC_WPMR_WPKEY_Pos 8
+#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */
+#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
+/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */
+#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */
+#define PMC_WPSR_WPVSRC_Pos 8
+#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */
+/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */
+#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */
+#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */
+#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */
+#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */
+#define PMC_PCER1_PID36 (0x1u << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */
+#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */
+#define PMC_PCER1_PID38 (0x1u << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */
+#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */
+#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */
+#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */
+#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */
+#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */
+#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */
+#define PMC_PCER1_PID45 (0x1u << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */
+#define PMC_PCER1_PID46 (0x1u << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */
+#define PMC_PCER1_PID47 (0x1u << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */
+#define PMC_PCER1_PID48 (0x1u << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */
+#define PMC_PCER1_PID49 (0x1u << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */
+#define PMC_PCER1_PID50 (0x1u << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */
+#define PMC_PCER1_PID51 (0x1u << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */
+#define PMC_PCER1_PID52 (0x1u << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */
+#define PMC_PCER1_PID53 (0x1u << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */
+#define PMC_PCER1_PID54 (0x1u << 22) /**< \brief (PMC_PCER1) Peripheral Clock 54 Enable */
+#define PMC_PCER1_PID55 (0x1u << 23) /**< \brief (PMC_PCER1) Peripheral Clock 55 Enable */
+#define PMC_PCER1_PID56 (0x1u << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */
+#define PMC_PCER1_PID57 (0x1u << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */
+#define PMC_PCER1_PID58 (0x1u << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */
+#define PMC_PCER1_PID59 (0x1u << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */
+#define PMC_PCER1_PID60 (0x1u << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */
+#define PMC_PCER1_PID61 (0x1u << 29) /**< \brief (PMC_PCER1) Peripheral Clock 61 Enable */
+#define PMC_PCER1_PID62 (0x1u << 30) /**< \brief (PMC_PCER1) Peripheral Clock 62 Enable */
+#define PMC_PCER1_PID63 (0x1u << 31) /**< \brief (PMC_PCER1) Peripheral Clock 63 Enable */
+/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */
+#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */
+#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */
+#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */
+#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */
+#define PMC_PCDR1_PID36 (0x1u << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */
+#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */
+#define PMC_PCDR1_PID38 (0x1u << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */
+#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */
+#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */
+#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */
+#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */
+#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */
+#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */
+#define PMC_PCDR1_PID45 (0x1u << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */
+#define PMC_PCDR1_PID46 (0x1u << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */
+#define PMC_PCDR1_PID47 (0x1u << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */
+#define PMC_PCDR1_PID48 (0x1u << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */
+#define PMC_PCDR1_PID49 (0x1u << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */
+#define PMC_PCDR1_PID50 (0x1u << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */
+#define PMC_PCDR1_PID51 (0x1u << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */
+#define PMC_PCDR1_PID52 (0x1u << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */
+#define PMC_PCDR1_PID53 (0x1u << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */
+#define PMC_PCDR1_PID54 (0x1u << 22) /**< \brief (PMC_PCDR1) Peripheral Clock 54 Disable */
+#define PMC_PCDR1_PID55 (0x1u << 23) /**< \brief (PMC_PCDR1) Peripheral Clock 55 Disable */
+#define PMC_PCDR1_PID56 (0x1u << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */
+#define PMC_PCDR1_PID57 (0x1u << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */
+#define PMC_PCDR1_PID58 (0x1u << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */
+#define PMC_PCDR1_PID59 (0x1u << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */
+#define PMC_PCDR1_PID60 (0x1u << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */
+#define PMC_PCDR1_PID61 (0x1u << 29) /**< \brief (PMC_PCDR1) Peripheral Clock 61 Disable */
+#define PMC_PCDR1_PID62 (0x1u << 30) /**< \brief (PMC_PCDR1) Peripheral Clock 62 Disable */
+#define PMC_PCDR1_PID63 (0x1u << 31) /**< \brief (PMC_PCDR1) Peripheral Clock 63 Disable */
+/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */
+#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */
+#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */
+#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */
+#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */
+#define PMC_PCSR1_PID36 (0x1u << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */
+#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */
+#define PMC_PCSR1_PID38 (0x1u << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */
+#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */
+#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */
+#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */
+#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */
+#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */
+#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */
+#define PMC_PCSR1_PID45 (0x1u << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */
+#define PMC_PCSR1_PID46 (0x1u << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */
+#define PMC_PCSR1_PID47 (0x1u << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */
+#define PMC_PCSR1_PID48 (0x1u << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */
+#define PMC_PCSR1_PID49 (0x1u << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */
+#define PMC_PCSR1_PID50 (0x1u << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */
+#define PMC_PCSR1_PID51 (0x1u << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */
+#define PMC_PCSR1_PID52 (0x1u << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */
+#define PMC_PCSR1_PID53 (0x1u << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */
+#define PMC_PCSR1_PID54 (0x1u << 22) /**< \brief (PMC_PCSR1) Peripheral Clock 54 Status */
+#define PMC_PCSR1_PID55 (0x1u << 23) /**< \brief (PMC_PCSR1) Peripheral Clock 55 Status */
+#define PMC_PCSR1_PID56 (0x1u << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */
+#define PMC_PCSR1_PID57 (0x1u << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */
+#define PMC_PCSR1_PID58 (0x1u << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */
+#define PMC_PCSR1_PID59 (0x1u << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */
+#define PMC_PCSR1_PID60 (0x1u << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */
+#define PMC_PCSR1_PID61 (0x1u << 29) /**< \brief (PMC_PCSR1) Peripheral Clock 61 Status */
+#define PMC_PCSR1_PID62 (0x1u << 30) /**< \brief (PMC_PCSR1) Peripheral Clock 62 Status */
+#define PMC_PCSR1_PID63 (0x1u << 31) /**< \brief (PMC_PCSR1) Peripheral Clock 63 Status */
+/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */
+#define PMC_OCR_CAL4_Pos 0
+#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 Mhz */
+#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos)))
+#define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 Mhz */
+#define PMC_OCR_CAL8_Pos 8
+#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 Mhz */
+#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos)))
+#define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 Mhz */
+#define PMC_OCR_CAL12_Pos 16
+#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 Mhz */
+#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos)))
+#define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 Mhz */
+
+/*@}*/
+
+
+#endif /* _SAM3S_PMC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_pwm.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_pwm.h
new file mode 100644
index 000000000..788c14ab0
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_pwm.h
@@ -0,0 +1,564 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_PWM_COMPONENT_
+#define _SAM3S_PWM_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S_PWM Pulse Width Modulation Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief PwmCh_num hardware registers */
+typedef struct {
+  RwReg      PWM_CMR;       /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */
+  RwReg      PWM_CDTY;      /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */
+  RwReg      PWM_CDTYUPD;   /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */
+  RwReg      PWM_CPRD;      /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */
+  RwReg      PWM_CPRDUPD;   /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */
+  RwReg      PWM_CCNT;      /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */
+  RwReg      PWM_DT;        /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */
+  RwReg      PWM_DTUPD;     /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */
+} PwmCh_num;
+/** \brief PwmCmp hardware registers */
+typedef struct {
+  RwReg      PWM_CMPV;      /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */
+  RwReg      PWM_CMPVUPD;   /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */
+  RwReg      PWM_CMPM;      /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */
+  RwReg      PWM_CMPMUPD;   /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */
+} PwmCmp;
+/** \brief Pwm hardware registers */
+#define PWMCMP_NUMBER 8
+#define PWMCH_NUM_NUMBER 4
+typedef struct {
+  RwReg      PWM_CLK;       /**< \brief (Pwm Offset: 0x00) PWM Clock Register */
+  WoReg      PWM_ENA;       /**< \brief (Pwm Offset: 0x04) PWM Enable Register */
+  WoReg      PWM_DIS;       /**< \brief (Pwm Offset: 0x08) PWM Disable Register */
+  RoReg      PWM_SR;        /**< \brief (Pwm Offset: 0x0C) PWM Status Register */
+  WoReg      PWM_IER1;      /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */
+  WoReg      PWM_IDR1;      /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */
+  RoReg      PWM_IMR1;      /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */
+  RoReg      PWM_ISR1;      /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */
+  RwReg      PWM_SCM;       /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */
+  RoReg      Reserved1[1];
+  RwReg      PWM_SCUC;      /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */
+  RwReg      PWM_SCUP;      /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */
+  WoReg      PWM_SCUPUPD;   /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */
+  WoReg      PWM_IER2;      /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */
+  WoReg      PWM_IDR2;      /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */
+  RoReg      PWM_IMR2;      /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */
+  RoReg      PWM_ISR2;      /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */
+  RwReg      PWM_OOV;       /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */
+  RwReg      PWM_OS;        /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */
+  WoReg      PWM_OSS;       /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */
+  WoReg      PWM_OSC;       /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */
+  WoReg      PWM_OSSUPD;    /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */
+  WoReg      PWM_OSCUPD;    /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */
+  RwReg      PWM_FMR;       /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */
+  RoReg      PWM_FSR;       /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */
+  WoReg      PWM_FCR;       /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */
+  RwReg      PWM_FPV;       /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */
+  RwReg      PWM_FPE;       /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */
+  RoReg      Reserved2[3];
+  RwReg      PWM_ELMR[2];   /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */
+  RoReg      Reserved3[11];
+  RwReg      PWM_SMMR;      /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */
+  RoReg      Reserved4[12];
+  WoReg      PWM_WPCR;      /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */
+  RoReg      PWM_WPSR;      /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */
+  RoReg      Reserved5[5];
+  RwReg      PWM_RPR;       /**< \brief (Pwm Offset: 0x100) Receive Pointer Register */
+  RwReg      PWM_RCR;       /**< \brief (Pwm Offset: 0x104) Receive Counter Register */
+  RwReg      PWM_TPR;       /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */
+  RwReg      PWM_TCR;       /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */
+  RwReg      PWM_RNPR;      /**< \brief (Pwm Offset: 0x110) Receive Next Pointer Register */
+  RwReg      PWM_RNCR;      /**< \brief (Pwm Offset: 0x114) Receive Next Counter Register */
+  RwReg      PWM_TNPR;      /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */
+  RwReg      PWM_TNCR;      /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */
+  WoReg      PWM_PTCR;      /**< \brief (Pwm Offset: 0x120) Transfer Control Register */
+  RoReg      PWM_PTSR;      /**< \brief (Pwm Offset: 0x124) Transfer Status Register */
+  RoReg      Reserved6[2];
+  PwmCmp     PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */
+  RoReg      Reserved7[20];
+  PwmCh_num  PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */
+} Pwm;
+#endif /* __ASSEMBLY__ */
+/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */
+#define PWM_CLK_DIVA_Pos 0
+#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
+#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))
+#define PWM_CLK_PREA_Pos 8
+#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
+#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))
+#define PWM_CLK_DIVB_Pos 16
+#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
+#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))
+#define PWM_CLK_PREB_Pos 24
+#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
+#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))
+/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
+#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */
+/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
+#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */
+/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
+#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */
+/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */
+#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */
+#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */
+#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */
+#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */
+#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */
+#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */
+#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */
+#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */
+/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */
+#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */
+#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */
+#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */
+#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */
+#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */
+#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */
+#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */
+#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */
+/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */
+#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */
+#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */
+#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */
+#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */
+#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */
+#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */
+#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */
+#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */
+/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */
+#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */
+#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */
+#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */
+#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */
+#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */
+#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */
+#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */
+#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */
+/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */
+#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */
+#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */
+#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */
+#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */
+#define PWM_SCM_UPDM_Pos 16
+#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */
+#define   PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */
+#define   PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */
+#define   PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels */
+#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */
+#define PWM_SCM_PTRCS_Pos 21
+#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */
+#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))
+/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */
+#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */
+/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */
+#define PWM_SCUP_UPR_Pos 0
+#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */
+#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))
+#define PWM_SCUP_UPRCNT_Pos 4
+#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */
+#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))
+/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */
+#define PWM_SCUPUPD_UPRUPD_Pos 0
+#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */
+#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))
+/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */
+#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */
+#define PWM_IER2_ENDTX (0x1u << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */
+#define PWM_IER2_TXBUFE (0x1u << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */
+#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */
+#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */
+#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */
+#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */
+#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */
+#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */
+#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */
+#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */
+#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */
+#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */
+#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */
+#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */
+#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */
+#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */
+#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */
+#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */
+#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */
+/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */
+#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */
+#define PWM_IDR2_ENDTX (0x1u << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */
+#define PWM_IDR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */
+#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */
+#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */
+#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */
+#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */
+#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */
+#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */
+#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */
+#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */
+#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */
+#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */
+#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */
+#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */
+#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */
+#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */
+#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */
+#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */
+#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */
+/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */
+#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */
+#define PWM_IMR2_ENDTX (0x1u << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */
+#define PWM_IMR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */
+#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */
+#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */
+#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */
+#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */
+#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */
+#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */
+#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */
+#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */
+#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */
+#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */
+#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */
+#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */
+#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */
+#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */
+#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */
+#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */
+#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */
+/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */
+#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */
+#define PWM_ISR2_ENDTX (0x1u << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */
+#define PWM_ISR2_TXBUFE (0x1u << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */
+#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */
+#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */
+#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */
+#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */
+#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */
+#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */
+#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */
+#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */
+#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */
+#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */
+#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */
+#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */
+#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */
+#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */
+#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */
+#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */
+#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */
+/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */
+#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */
+#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */
+#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */
+#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */
+#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */
+#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */
+#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */
+#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */
+/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */
+#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */
+#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */
+#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */
+#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */
+#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */
+#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */
+#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */
+#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */
+/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */
+#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */
+#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */
+#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */
+#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */
+#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */
+#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */
+#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */
+#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */
+/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */
+#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */
+#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */
+#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */
+#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */
+#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */
+#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */
+#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */
+#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */
+/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */
+#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */
+#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */
+#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */
+#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */
+#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */
+#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */
+#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */
+#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */
+/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */
+#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */
+#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */
+#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */
+#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */
+#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */
+#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */
+#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */
+#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */
+/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */
+#define PWM_FMR_FPOL_Pos 0
+#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))
+#define PWM_FMR_FMOD_Pos 8
+#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))
+#define PWM_FMR_FFIL_Pos 16
+#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))
+/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */
+#define PWM_FSR_FIV_Pos 0
+#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value (fault input bit varies from 0 to 5) */
+#define PWM_FSR_FS_Pos 8
+#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status (fault input bit varies from 0 to 5) */
+/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */
+#define PWM_FCR_FCLR_Pos 0
+#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear (fault input bit varies from 0 to 5) */
+#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))
+/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */
+#define PWM_FPV_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */
+#define PWM_FPV_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */
+#define PWM_FPV_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */
+#define PWM_FPV_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */
+#define PWM_FPV_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */
+#define PWM_FPV_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */
+#define PWM_FPV_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */
+#define PWM_FPV_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */
+/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */
+#define PWM_FPE_FPE0_Pos 0
+#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) */
+#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)))
+#define PWM_FPE_FPE1_Pos 8
+#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) */
+#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)))
+#define PWM_FPE_FPE2_Pos 16
+#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) */
+#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)))
+#define PWM_FPE_FPE3_Pos 24
+#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) */
+#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)))
+/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */
+#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */
+#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */
+#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */
+#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */
+#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */
+#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */
+#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */
+#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */
+/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */
+#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */
+#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */
+/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */
+#define PWM_WPCR_WPCMD_Pos 0
+#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protect Command */
+#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))
+#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */
+#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */
+#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */
+#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */
+#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */
+#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */
+#define PWM_WPCR_WPKEY_Pos 8
+#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protect Key */
+#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))
+/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */
+#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */
+#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPVSRC_Pos 16
+#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */
+/* -------- PWM_RPR : (PWM Offset: 0x100) Receive Pointer Register -------- */
+#define PWM_RPR_RXPTR_Pos 0
+#define PWM_RPR_RXPTR_Msk (0xffffffffu << PWM_RPR_RXPTR_Pos) /**< \brief (PWM_RPR) Receive Pointer Register */
+#define PWM_RPR_RXPTR(value) ((PWM_RPR_RXPTR_Msk & ((value) << PWM_RPR_RXPTR_Pos)))
+/* -------- PWM_RCR : (PWM Offset: 0x104) Receive Counter Register -------- */
+#define PWM_RCR_RXCTR_Pos 0
+#define PWM_RCR_RXCTR_Msk (0xffffu << PWM_RCR_RXCTR_Pos) /**< \brief (PWM_RCR) Receive Counter Register */
+#define PWM_RCR_RXCTR(value) ((PWM_RCR_RXCTR_Msk & ((value) << PWM_RCR_RXCTR_Pos)))
+/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */
+#define PWM_TPR_TXPTR_Pos 0
+#define PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos) /**< \brief (PWM_TPR) Transmit Counter Register */
+#define PWM_TPR_TXPTR(value) ((PWM_TPR_TXPTR_Msk & ((value) << PWM_TPR_TXPTR_Pos)))
+/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */
+#define PWM_TCR_TXCTR_Pos 0
+#define PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos) /**< \brief (PWM_TCR) Transmit Counter Register */
+#define PWM_TCR_TXCTR(value) ((PWM_TCR_TXCTR_Msk & ((value) << PWM_TCR_TXCTR_Pos)))
+/* -------- PWM_RNPR : (PWM Offset: 0x110) Receive Next Pointer Register -------- */
+#define PWM_RNPR_RXNPTR_Pos 0
+#define PWM_RNPR_RXNPTR_Msk (0xffffffffu << PWM_RNPR_RXNPTR_Pos) /**< \brief (PWM_RNPR) Receive Next Pointer */
+#define PWM_RNPR_RXNPTR(value) ((PWM_RNPR_RXNPTR_Msk & ((value) << PWM_RNPR_RXNPTR_Pos)))
+/* -------- PWM_RNCR : (PWM Offset: 0x114) Receive Next Counter Register -------- */
+#define PWM_RNCR_RXNCTR_Pos 0
+#define PWM_RNCR_RXNCTR_Msk (0xffffu << PWM_RNCR_RXNCTR_Pos) /**< \brief (PWM_RNCR) Receive Next Counter */
+#define PWM_RNCR_RXNCTR(value) ((PWM_RNCR_RXNCTR_Msk & ((value) << PWM_RNCR_RXNCTR_Pos)))
+/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */
+#define PWM_TNPR_TXNPTR_Pos 0
+#define PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos) /**< \brief (PWM_TNPR) Transmit Next Pointer */
+#define PWM_TNPR_TXNPTR(value) ((PWM_TNPR_TXNPTR_Msk & ((value) << PWM_TNPR_TXNPTR_Pos)))
+/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */
+#define PWM_TNCR_TXNCTR_Pos 0
+#define PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos) /**< \brief (PWM_TNCR) Transmit Counter Next */
+#define PWM_TNCR_TXNCTR(value) ((PWM_TNCR_TXNCTR_Msk & ((value) << PWM_TNCR_TXNCTR_Pos)))
+/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */
+#define PWM_PTCR_RXTEN (0x1u << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */
+#define PWM_PTCR_RXTDIS (0x1u << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */
+#define PWM_PTCR_TXTEN (0x1u << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */
+#define PWM_PTCR_TXTDIS (0x1u << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */
+/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */
+#define PWM_PTSR_RXTEN (0x1u << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */
+#define PWM_PTSR_TXTEN (0x1u << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */
+/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */
+#define PWM_CMPV_CV_Pos 0
+#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */
+#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))
+#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */
+/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */
+#define PWM_CMPVUPD_CVUPD_Pos 0
+#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */
+#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))
+#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */
+/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */
+#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */
+#define PWM_CMPM_CTR_Pos 4
+#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */
+#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))
+#define PWM_CMPM_CPR_Pos 8
+#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */
+#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))
+#define PWM_CMPM_CPRCNT_Pos 12
+#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */
+#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))
+#define PWM_CMPM_CUPR_Pos 16
+#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */
+#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))
+#define PWM_CMPM_CUPRCNT_Pos 20
+#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */
+#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))
+/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */
+#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */
+#define PWM_CMPMUPD_CTRUPD_Pos 4
+#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */
+#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))
+#define PWM_CMPMUPD_CPRUPD_Pos 8
+#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */
+#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))
+#define PWM_CMPMUPD_CUPRUPD_Pos 16
+#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */
+#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))
+/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */
+#define PWM_CMR_CPRE_Pos 0
+#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */
+#define   PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master clock */
+#define   PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Master clock/2 */
+#define   PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Master clock/4 */
+#define   PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Master clock/8 */
+#define   PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Master clock/16 */
+#define   PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Master clock/32 */
+#define   PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Master clock/64 */
+#define   PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Master clock/128 */
+#define   PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Master clock/256 */
+#define   PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Master clock/512 */
+#define   PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Master clock/1024 */
+#define   PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */
+#define   PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */
+#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */
+#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */
+#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */
+#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */
+#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */
+#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */
+/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */
+#define PWM_CDTY_CDTY_Pos 0
+#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */
+#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))
+/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */
+#define PWM_CDTYUPD_CDTYUPD_Pos 0
+#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */
+#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))
+/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */
+#define PWM_CPRD_CPRD_Pos 0
+#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */
+#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))
+/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */
+#define PWM_CPRDUPD_CPRDUPD_Pos 0
+#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */
+#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))
+/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */
+#define PWM_CCNT_CNT_Pos 0
+#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */
+/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */
+#define PWM_DT_DTH_Pos 0
+#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */
+#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))
+#define PWM_DT_DTL_Pos 16
+#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */
+#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))
+/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */
+#define PWM_DTUPD_DTHUPD_Pos 0
+#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */
+#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))
+#define PWM_DTUPD_DTLUPD_Pos 16
+#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */
+#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3S_PWM_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_rstc.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_rstc.h
new file mode 100644
index 000000000..09cf75abe
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_rstc.h
@@ -0,0 +1,73 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_RSTC_COMPONENT_
+#define _SAM3S_RSTC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Reset Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S_RSTC Reset Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Rstc hardware registers */
+typedef struct {
+  WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
+  RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
+  RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
+} Rstc;
+#endif /* __ASSEMBLY__ */
+/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
+#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */
+#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */
+#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */
+#define RSTC_CR_KEY_Pos 24
+#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Password */
+#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
+/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
+#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */
+#define RSTC_SR_RSTTYP_Pos 8
+#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */
+#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
+#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
+/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
+#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */
+#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
+#define RSTC_MR_ERSTL_Pos 8
+#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */
+#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
+#define RSTC_MR_KEY_Pos 24
+#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */
+#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3S_RSTC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_rtc.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_rtc.h
new file mode 100644
index 000000000..598c8dc43
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_rtc.h
@@ -0,0 +1,161 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_RTC_COMPONENT_
+#define _SAM3S_RTC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Real-time Clock */
+/* ============================================================================= */
+/** \addtogroup SAM3S_RTC Real-time Clock */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Rtc hardware registers */
+typedef struct {
+  RwReg RTC_CR;     /**< \brief (Rtc Offset: 0x00) Control Register */
+  RwReg RTC_MR;     /**< \brief (Rtc Offset: 0x04) Mode Register */
+  RwReg RTC_TIMR;   /**< \brief (Rtc Offset: 0x08) Time Register */
+  RwReg RTC_CALR;   /**< \brief (Rtc Offset: 0x0C) Calendar Register */
+  RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */
+  RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */
+  RoReg RTC_SR;     /**< \brief (Rtc Offset: 0x18) Status Register */
+  WoReg RTC_SCCR;   /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */
+  WoReg RTC_IER;    /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */
+  WoReg RTC_IDR;    /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */
+  RoReg RTC_IMR;    /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */
+  RoReg RTC_VER;    /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */
+} Rtc;
+#endif /* __ASSEMBLY__ */
+/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
+#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */
+#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */
+#define RTC_CR_TIMEVSEL_Pos 8
+#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */
+#define   RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */
+#define   RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */
+#define   RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */
+#define   RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */
+#define RTC_CR_CALEVSEL_Pos 16
+#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */
+#define   RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */
+#define   RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */
+#define   RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */
+/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
+#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */
+/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
+#define RTC_TIMR_SEC_Pos 0
+#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */
+#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
+#define RTC_TIMR_MIN_Pos 8
+#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */
+#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
+#define RTC_TIMR_HOUR_Pos 16
+#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */
+#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
+#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */
+/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
+#define RTC_CALR_CENT_Pos 0
+#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */
+#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
+#define RTC_CALR_YEAR_Pos 8
+#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */
+#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
+#define RTC_CALR_MONTH_Pos 16
+#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */
+#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
+#define RTC_CALR_DAY_Pos 21
+#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */
+#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
+#define RTC_CALR_DATE_Pos 24
+#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */
+#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
+/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
+#define RTC_TIMALR_SEC_Pos 0
+#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */
+#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
+#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */
+#define RTC_TIMALR_MIN_Pos 8
+#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */
+#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
+#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */
+#define RTC_TIMALR_HOUR_Pos 16
+#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */
+#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
+#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */
+#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */
+/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
+#define RTC_CALALR_MONTH_Pos 16
+#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */
+#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
+#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */
+#define RTC_CALALR_DATE_Pos 24
+#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */
+#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
+#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */
+/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
+#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */
+#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */
+#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */
+#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */
+#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */
+/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
+#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */
+#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */
+#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */
+#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */
+#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */
+/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
+#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */
+#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */
+#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */
+#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */
+#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */
+/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
+#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */
+#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */
+#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */
+#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */
+#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */
+/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
+#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */
+#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */
+#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */
+#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */
+#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */
+/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
+#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */
+#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */
+#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */
+#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */
+
+/*@}*/
+
+
+#endif /* _SAM3S_RTC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_rtt.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_rtt.h
new file mode 100644
index 000000000..df096229b
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_rtt.h
@@ -0,0 +1,69 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_RTT_COMPONENT_
+#define _SAM3S_RTT_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Real-time Timer */
+/* ============================================================================= */
+/** \addtogroup SAM3S_RTT Real-time Timer */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Rtt hardware registers */
+typedef struct {
+  RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */
+  RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */
+  RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */
+  RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */
+} Rtt;
+#endif /* __ASSEMBLY__ */
+/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */
+#define RTT_MR_RTPRES_Pos 0
+#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */
+#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)))
+#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */
+#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */
+#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */
+/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */
+#define RTT_AR_ALMV_Pos 0
+#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */
+#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)))
+/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */
+#define RTT_VR_CRTV_Pos 0
+#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */
+/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */
+#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */
+#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */
+
+/*@}*/
+
+
+#endif /* _SAM3S_RTT_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_smc.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_smc.h
new file mode 100644
index 000000000..4797a6100
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_smc.h
@@ -0,0 +1,144 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_SMC_COMPONENT_
+#define _SAM3S_SMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Static Memory Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S_SMC Static Memory Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief SmcCs_number hardware registers */
+typedef struct {
+  RwReg         SMC_SETUP;        /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */
+  RwReg         SMC_PULSE;        /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */
+  RwReg         SMC_CYCLE;        /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */
+  RwReg         SMC_MODE;         /**< \brief (SmcCs_number Offset: 0xC) SMC Mode Register */
+} SmcCs_number;
+/** \brief Smc hardware registers */
+#define SMCCS_NUMBER_NUMBER 5
+typedef struct {
+  SmcCs_number  SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 4 */
+  RoReg         Reserved1[12];
+  RwReg         SMC_OCMS;         /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */
+  WoReg         SMC_KEY1;         /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */
+  WoReg         SMC_KEY2;         /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */
+  RoReg         Reserved2[22];
+  RwReg         SMC_WPMR;         /**< \brief (Smc Offset: 0xE4) SMC Write Protect Mode Register */
+  RoReg         SMC_WPSR;         /**< \brief (Smc Offset: 0xE8) SMC Write Protect Status Register */
+} Smc;
+#endif /* __ASSEMBLY__ */
+/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */
+#define SMC_SETUP_NWE_SETUP_Pos 0
+#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */
+#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))
+#define SMC_SETUP_NCS_WR_SETUP_Pos 8
+#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */
+#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))
+#define SMC_SETUP_NRD_SETUP_Pos 16
+#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */
+#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))
+#define SMC_SETUP_NCS_RD_SETUP_Pos 24
+#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */
+#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))
+/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */
+#define SMC_PULSE_NWE_PULSE_Pos 0
+#define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */
+#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))
+#define SMC_PULSE_NCS_WR_PULSE_Pos 8
+#define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */
+#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))
+#define SMC_PULSE_NRD_PULSE_Pos 16
+#define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */
+#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))
+#define SMC_PULSE_NCS_RD_PULSE_Pos 24
+#define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */
+#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))
+/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */
+#define SMC_CYCLE_NWE_CYCLE_Pos 0
+#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */
+#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))
+#define SMC_CYCLE_NRD_CYCLE_Pos 16
+#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */
+#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))
+/* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */
+#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE)  */
+#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE)  */
+#define SMC_MODE_EXNW_MODE_Pos 4
+#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */
+#define   SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */
+#define   SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */
+#define   SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */
+#define SMC_MODE_DBW_Pos 12
+#define SMC_MODE_DBW_Msk (0x3u << SMC_MODE_DBW_Pos) /**< \brief (SMC_MODE) Data Bus Width */
+#define   SMC_MODE_DBW_8_BIT (0x0u << 12) /**< \brief (SMC_MODE) 8-bit bus */
+#define   SMC_MODE_DBW_16_BIT (0x1u << 12) /**< \brief (SMC_MODE) 16-bit bus */
+#define   SMC_MODE_DBW_32_BIT (0x2u << 12) /**< \brief (SMC_MODE) 32-bit bus */
+#define SMC_MODE_TDF_CYCLES_Pos 16
+#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */
+#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))
+#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */
+#define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */
+#define SMC_MODE_PS_Pos 28
+#define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */
+#define   SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */
+#define   SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */
+#define   SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */
+#define   SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */
+/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */
+#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */
+#define SMC_OCMS_CS0SE (0x1u << 16) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
+#define SMC_OCMS_CS1SE (0x1u << 17) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
+#define SMC_OCMS_CS2SE (0x1u << 18) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
+#define SMC_OCMS_CS3SE (0x1u << 19) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
+/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */
+#define SMC_KEY1_KEY1_Pos 0
+#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */
+#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))
+/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */
+#define SMC_KEY2_KEY2_Pos 0
+#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */
+#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))
+/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protect Mode Register -------- */
+#define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */
+#define SMC_WPMR_WPKEY_Pos 8
+#define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protect KEY */
+#define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos)))
+/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protect Status Register -------- */
+#define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protect Enable */
+#define SMC_WPSR_WPVSRC_Pos 8
+#define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3S_SMC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_spi.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_spi.h
new file mode 100644
index 000000000..fed4db1c3
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_spi.h
@@ -0,0 +1,227 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_SPI_COMPONENT_
+#define _SAM3S_SPI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Serial Peripheral Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3S_SPI Serial Peripheral Interface */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Spi hardware registers */
+typedef struct {
+  WoReg SPI_CR;        /**< \brief (Spi Offset: 0x00) Control Register */
+  RwReg SPI_MR;        /**< \brief (Spi Offset: 0x04) Mode Register */
+  RoReg SPI_RDR;       /**< \brief (Spi Offset: 0x08) Receive Data Register */
+  WoReg SPI_TDR;       /**< \brief (Spi Offset: 0x0C) Transmit Data Register */
+  RoReg SPI_SR;        /**< \brief (Spi Offset: 0x10) Status Register */
+  WoReg SPI_IER;       /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */
+  WoReg SPI_IDR;       /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */
+  RoReg SPI_IMR;       /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */
+  RoReg Reserved1[4];
+  RwReg SPI_CSR[4];    /**< \brief (Spi Offset: 0x30) Chip Select Register */
+  RoReg Reserved2[41];
+  RwReg SPI_WPMR;      /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */
+  RoReg SPI_WPSR;      /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */
+  RoReg Reserved3[5];
+  RwReg SPI_RPR;       /**< \brief (Spi Offset: 0x100) Receive Pointer Register */
+  RwReg SPI_RCR;       /**< \brief (Spi Offset: 0x104) Receive Counter Register */
+  RwReg SPI_TPR;       /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */
+  RwReg SPI_TCR;       /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */
+  RwReg SPI_RNPR;      /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */
+  RwReg SPI_RNCR;      /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */
+  RwReg SPI_TNPR;      /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */
+  RwReg SPI_TNCR;      /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */
+  WoReg SPI_PTCR;      /**< \brief (Spi Offset: 0x120) Transfer Control Register */
+  RoReg SPI_PTSR;      /**< \brief (Spi Offset: 0x124) Transfer Status Register */
+} Spi;
+#endif /* __ASSEMBLY__ */
+/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
+#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */
+#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */
+#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */
+#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */
+/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
+#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */
+#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */
+#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */
+#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */
+#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */
+#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */
+#define SPI_MR_PCS_Pos 16
+#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */
+#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
+#define SPI_MR_DLYBCS_Pos 24
+#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */
+#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
+/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
+#define SPI_RDR_RD_Pos 0
+#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */
+#define SPI_RDR_PCS_Pos 16
+#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */
+/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
+#define SPI_TDR_TD_Pos 0
+#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */
+#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
+#define SPI_TDR_PCS_Pos 16
+#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */
+#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
+#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
+#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */
+#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */
+#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */
+#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */
+#define SPI_SR_ENDRX (0x1u << 4) /**< \brief (SPI_SR) End of RX buffer */
+#define SPI_SR_ENDTX (0x1u << 5) /**< \brief (SPI_SR) End of TX buffer */
+#define SPI_SR_RXBUFF (0x1u << 6) /**< \brief (SPI_SR) RX Buffer Full */
+#define SPI_SR_TXBUFE (0x1u << 7) /**< \brief (SPI_SR) TX Buffer Empty */
+#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */
+#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */
+#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */
+#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
+#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */
+#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */
+#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */
+#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */
+#define SPI_IER_ENDRX (0x1u << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */
+#define SPI_IER_ENDTX (0x1u << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */
+#define SPI_IER_RXBUFF (0x1u << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */
+#define SPI_IER_TXBUFE (0x1u << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */
+#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */
+#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */
+#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */
+#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */
+#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */
+#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */
+#define SPI_IDR_ENDRX (0x1u << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */
+#define SPI_IDR_ENDTX (0x1u << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */
+#define SPI_IDR_RXBUFF (0x1u << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */
+#define SPI_IDR_TXBUFE (0x1u << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */
+#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */
+#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */
+#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */
+/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
+#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */
+#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */
+#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */
+#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */
+#define SPI_IMR_ENDRX (0x1u << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */
+#define SPI_IMR_ENDTX (0x1u << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */
+#define SPI_IMR_RXBUFF (0x1u << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */
+#define SPI_IMR_TXBUFE (0x1u << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */
+#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */
+#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */
+#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */
+/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
+#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */
+#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */
+#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_BITS_Pos 4
+#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */
+#define   SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */
+#define   SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */
+#define   SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */
+#define   SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */
+#define   SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */
+#define   SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */
+#define   SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */
+#define   SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */
+#define   SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */
+#define SPI_CSR_SCBR_Pos 8
+#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */
+#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
+#define SPI_CSR_DLYBS_Pos 16
+#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */
+#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
+#define SPI_CSR_DLYBCT_Pos 24
+#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */
+#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
+/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */
+#define SPI_WPMR_SPIWPEN (0x1u << 0) /**< \brief (SPI_WPMR) SPI Write Protection Enable */
+#define SPI_WPMR_SPIWPKEY_Pos 8
+#define SPI_WPMR_SPIWPKEY_Msk (0xffffffu << SPI_WPMR_SPIWPKEY_Pos) /**< \brief (SPI_WPMR) SPI Write Protection Key Password */
+#define SPI_WPMR_SPIWPKEY(value) ((SPI_WPMR_SPIWPKEY_Msk & ((value) << SPI_WPMR_SPIWPKEY_Pos)))
+/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
+#define SPI_WPSR_SPIWPVS_Pos 0
+#define SPI_WPSR_SPIWPVS_Msk (0x7u << SPI_WPSR_SPIWPVS_Pos) /**< \brief (SPI_WPSR) SPI Write Protection Violation Status */
+#define SPI_WPSR_SPIWPVSRC_Pos 8
+#define SPI_WPSR_SPIWPVSRC_Msk (0xffu << SPI_WPSR_SPIWPVSRC_Pos) /**< \brief (SPI_WPSR) SPI Write Protection Violation Source */
+/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */
+#define SPI_RPR_RXPTR_Pos 0
+#define SPI_RPR_RXPTR_Msk (0xffffffffu << SPI_RPR_RXPTR_Pos) /**< \brief (SPI_RPR) Receive Pointer Register */
+#define SPI_RPR_RXPTR(value) ((SPI_RPR_RXPTR_Msk & ((value) << SPI_RPR_RXPTR_Pos)))
+/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */
+#define SPI_RCR_RXCTR_Pos 0
+#define SPI_RCR_RXCTR_Msk (0xffffu << SPI_RCR_RXCTR_Pos) /**< \brief (SPI_RCR) Receive Counter Register */
+#define SPI_RCR_RXCTR(value) ((SPI_RCR_RXCTR_Msk & ((value) << SPI_RCR_RXCTR_Pos)))
+/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */
+#define SPI_TPR_TXPTR_Pos 0
+#define SPI_TPR_TXPTR_Msk (0xffffffffu << SPI_TPR_TXPTR_Pos) /**< \brief (SPI_TPR) Transmit Counter Register */
+#define SPI_TPR_TXPTR(value) ((SPI_TPR_TXPTR_Msk & ((value) << SPI_TPR_TXPTR_Pos)))
+/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */
+#define SPI_TCR_TXCTR_Pos 0
+#define SPI_TCR_TXCTR_Msk (0xffffu << SPI_TCR_TXCTR_Pos) /**< \brief (SPI_TCR) Transmit Counter Register */
+#define SPI_TCR_TXCTR(value) ((SPI_TCR_TXCTR_Msk & ((value) << SPI_TCR_TXCTR_Pos)))
+/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */
+#define SPI_RNPR_RXNPTR_Pos 0
+#define SPI_RNPR_RXNPTR_Msk (0xffffffffu << SPI_RNPR_RXNPTR_Pos) /**< \brief (SPI_RNPR) Receive Next Pointer */
+#define SPI_RNPR_RXNPTR(value) ((SPI_RNPR_RXNPTR_Msk & ((value) << SPI_RNPR_RXNPTR_Pos)))
+/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */
+#define SPI_RNCR_RXNCTR_Pos 0
+#define SPI_RNCR_RXNCTR_Msk (0xffffu << SPI_RNCR_RXNCTR_Pos) /**< \brief (SPI_RNCR) Receive Next Counter */
+#define SPI_RNCR_RXNCTR(value) ((SPI_RNCR_RXNCTR_Msk & ((value) << SPI_RNCR_RXNCTR_Pos)))
+/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define SPI_TNPR_TXNPTR_Pos 0
+#define SPI_TNPR_TXNPTR_Msk (0xffffffffu << SPI_TNPR_TXNPTR_Pos) /**< \brief (SPI_TNPR) Transmit Next Pointer */
+#define SPI_TNPR_TXNPTR(value) ((SPI_TNPR_TXNPTR_Msk & ((value) << SPI_TNPR_TXNPTR_Pos)))
+/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define SPI_TNCR_TXNCTR_Pos 0
+#define SPI_TNCR_TXNCTR_Msk (0xffffu << SPI_TNCR_TXNCTR_Pos) /**< \brief (SPI_TNCR) Transmit Counter Next */
+#define SPI_TNCR_TXNCTR(value) ((SPI_TNCR_TXNCTR_Msk & ((value) << SPI_TNCR_TXNCTR_Pos)))
+/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */
+#define SPI_PTCR_RXTEN (0x1u << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */
+#define SPI_PTCR_RXTDIS (0x1u << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */
+#define SPI_PTCR_TXTEN (0x1u << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */
+#define SPI_PTCR_TXTDIS (0x1u << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */
+/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */
+#define SPI_PTSR_RXTEN (0x1u << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */
+#define SPI_PTSR_TXTEN (0x1u << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S_SPI_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_ssc.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_ssc.h
new file mode 100644
index 000000000..954006152
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_ssc.h
@@ -0,0 +1,337 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_SSC_COMPONENT_
+#define _SAM3S_SSC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Synchronous Serial Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S_SSC Synchronous Serial Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Ssc hardware registers */
+typedef struct {
+  WoReg SSC_CR;        /**< \brief (Ssc Offset: 0x0) Control Register */
+  RwReg SSC_CMR;       /**< \brief (Ssc Offset: 0x4) Clock Mode Register */
+  RoReg Reserved1[2];
+  RwReg SSC_RCMR;      /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */
+  RwReg SSC_RFMR;      /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */
+  RwReg SSC_TCMR;      /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */
+  RwReg SSC_TFMR;      /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */
+  RoReg SSC_RHR;       /**< \brief (Ssc Offset: 0x20) Receive Holding Register */
+  WoReg SSC_THR;       /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */
+  RoReg Reserved2[2];
+  RoReg SSC_RSHR;      /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */
+  RwReg SSC_TSHR;      /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */
+  RwReg SSC_RC0R;      /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */
+  RwReg SSC_RC1R;      /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */
+  RoReg SSC_SR;        /**< \brief (Ssc Offset: 0x40) Status Register */
+  WoReg SSC_IER;       /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */
+  WoReg SSC_IDR;       /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */
+  RoReg SSC_IMR;       /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */
+  RoReg Reserved3[37];
+  RwReg SSC_WPMR;      /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */
+  RoReg SSC_WPSR;      /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved4[5];
+  RwReg SSC_RPR;       /**< \brief (Ssc Offset: 0x100) Receive Pointer Register */
+  RwReg SSC_RCR;       /**< \brief (Ssc Offset: 0x104) Receive Counter Register */
+  RwReg SSC_TPR;       /**< \brief (Ssc Offset: 0x108) Transmit Pointer Register */
+  RwReg SSC_TCR;       /**< \brief (Ssc Offset: 0x10C) Transmit Counter Register */
+  RwReg SSC_RNPR;      /**< \brief (Ssc Offset: 0x110) Receive Next Pointer Register */
+  RwReg SSC_RNCR;      /**< \brief (Ssc Offset: 0x114) Receive Next Counter Register */
+  RwReg SSC_TNPR;      /**< \brief (Ssc Offset: 0x118) Transmit Next Pointer Register */
+  RwReg SSC_TNCR;      /**< \brief (Ssc Offset: 0x11C) Transmit Next Counter Register */
+  WoReg SSC_PTCR;      /**< \brief (Ssc Offset: 0x120) Transfer Control Register */
+  RoReg SSC_PTSR;      /**< \brief (Ssc Offset: 0x124) Transfer Status Register */
+} Ssc;
+#endif /* __ASSEMBLY__ */
+/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */
+#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */
+#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */
+#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */
+#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */
+#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */
+/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */
+#define SSC_CMR_DIV_Pos 0
+#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */
+#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))
+/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */
+#define SSC_RCMR_CKS_Pos 0
+#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */
+#define   SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */
+#define   SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */
+#define   SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */
+#define SSC_RCMR_CKO_Pos 2
+#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */
+#define   SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None */
+#define   SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock */
+#define   SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
+#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */
+#define SSC_RCMR_CKG_Pos 6
+#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */
+#define   SSC_RCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_RCMR) None */
+#define   SSC_RCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_RCMR) Continuous Receive Clock */
+#define   SSC_RCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
+#define SSC_RCMR_START_Pos 8
+#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */
+#define   SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
+#define   SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */
+#define   SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */
+#define   SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */
+#define   SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */
+#define   SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */
+#define   SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */
+#define   SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */
+#define   SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */
+#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */
+#define SSC_RCMR_STTDLY_Pos 16
+#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */
+#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))
+#define SSC_RCMR_PERIOD_Pos 24
+#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */
+#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))
+/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */
+#define SSC_RFMR_DATLEN_Pos 0
+#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */
+#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))
+#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */
+#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */
+#define SSC_RFMR_DATNB_Pos 8
+#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */
+#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))
+#define SSC_RFMR_FSLEN_Pos 16
+#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */
+#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))
+#define SSC_RFMR_FSOS_Pos 20
+#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */
+#define   SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None */
+#define   SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse */
+#define   SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse */
+#define   SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer */
+#define   SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer */
+#define   SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer */
+#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */
+#define   SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */
+#define   SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */
+#define SSC_RFMR_FSLEN_EXT_Pos 28
+#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */
+#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))
+/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */
+#define SSC_TCMR_CKS_Pos 0
+#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */
+#define   SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */
+#define   SSC_TCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_TCMR) TK Clock signal */
+#define   SSC_TCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_TCMR) RK pin */
+#define SSC_TCMR_CKO_Pos 2
+#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */
+#define   SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None */
+#define   SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Receive Clock */
+#define   SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers */
+#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */
+#define SSC_TCMR_CKG_Pos 6
+#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */
+#define   SSC_TCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_TCMR) None */
+#define   SSC_TCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */
+#define   SSC_TCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */
+#define SSC_TCMR_START_Pos 8
+#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */
+#define   SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. */
+#define   SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */
+#define   SSC_TCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */
+#define   SSC_TCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */
+#define   SSC_TCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */
+#define   SSC_TCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */
+#define   SSC_TCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */
+#define   SSC_TCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */
+#define   SSC_TCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_TCMR) Compare 0 */
+#define SSC_TCMR_STTDLY_Pos 16
+#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */
+#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))
+#define SSC_TCMR_PERIOD_Pos 24
+#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */
+#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))
+/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */
+#define SSC_TFMR_DATLEN_Pos 0
+#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */
+#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))
+#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */
+#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */
+#define SSC_TFMR_DATNB_Pos 8
+#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per frame */
+#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))
+#define SSC_TFMR_FSLEN_Pos 16
+#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */
+#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))
+#define SSC_TFMR_FSOS_Pos 20
+#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */
+#define   SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None */
+#define   SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse */
+#define   SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse */
+#define   SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */
+#define   SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */
+#define   SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */
+#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */
+#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */
+#define   SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */
+#define   SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */
+#define SSC_TFMR_FSLEN_EXT_Pos 28
+#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */
+#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))
+/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */
+#define SSC_RHR_RDAT_Pos 0
+#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */
+/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */
+#define SSC_THR_TDAT_Pos 0
+#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */
+#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))
+/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */
+#define SSC_RSHR_RSDAT_Pos 0
+#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */
+/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */
+#define SSC_TSHR_TSDAT_Pos 0
+#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */
+#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))
+/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */
+#define SSC_RC0R_CP0_Pos 0
+#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */
+#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))
+/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */
+#define SSC_RC1R_CP1_Pos 0
+#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */
+#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))
+/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */
+#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */
+#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */
+#define SSC_SR_ENDTX (0x1u << 2) /**< \brief (SSC_SR) End of Transmission */
+#define SSC_SR_TXBUFE (0x1u << 3) /**< \brief (SSC_SR) Transmit Buffer Empty */
+#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */
+#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */
+#define SSC_SR_ENDRX (0x1u << 6) /**< \brief (SSC_SR) End of Reception */
+#define SSC_SR_RXBUFF (0x1u << 7) /**< \brief (SSC_SR) Receive Buffer Full */
+#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */
+#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */
+#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */
+#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */
+#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */
+#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */
+/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */
+#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */
+#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */
+#define SSC_IER_ENDTX (0x1u << 2) /**< \brief (SSC_IER) End of Transmission Interrupt Enable */
+#define SSC_IER_TXBUFE (0x1u << 3) /**< \brief (SSC_IER) Transmit Buffer Empty Interrupt Enable */
+#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */
+#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */
+#define SSC_IER_ENDRX (0x1u << 6) /**< \brief (SSC_IER) End of Reception Interrupt Enable */
+#define SSC_IER_RXBUFF (0x1u << 7) /**< \brief (SSC_IER) Receive Buffer Full Interrupt Enable */
+#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */
+#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */
+#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */
+#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */
+/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */
+#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */
+#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */
+#define SSC_IDR_ENDTX (0x1u << 2) /**< \brief (SSC_IDR) End of Transmission Interrupt Disable */
+#define SSC_IDR_TXBUFE (0x1u << 3) /**< \brief (SSC_IDR) Transmit Buffer Empty Interrupt Disable */
+#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */
+#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */
+#define SSC_IDR_ENDRX (0x1u << 6) /**< \brief (SSC_IDR) End of Reception Interrupt Disable */
+#define SSC_IDR_RXBUFF (0x1u << 7) /**< \brief (SSC_IDR) Receive Buffer Full Interrupt Disable */
+#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */
+#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */
+#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */
+#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */
+/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */
+#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */
+#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */
+#define SSC_IMR_ENDTX (0x1u << 2) /**< \brief (SSC_IMR) End of Transmission Interrupt Mask */
+#define SSC_IMR_TXBUFE (0x1u << 3) /**< \brief (SSC_IMR) Transmit Buffer Empty Interrupt Mask */
+#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */
+#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */
+#define SSC_IMR_ENDRX (0x1u << 6) /**< \brief (SSC_IMR) End of Reception Interrupt Mask */
+#define SSC_IMR_RXBUFF (0x1u << 7) /**< \brief (SSC_IMR) Receive Buffer Full Interrupt Mask */
+#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */
+#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */
+#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */
+#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */
+/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */
+#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protect Enable */
+#define SSC_WPMR_WPKEY_Pos 8
+#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protect KEY */
+#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)))
+/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */
+#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */
+#define SSC_WPSR_WPVSRC_Pos 8
+#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */
+/* -------- SSC_RPR : (SSC Offset: 0x100) Receive Pointer Register -------- */
+#define SSC_RPR_RXPTR_Pos 0
+#define SSC_RPR_RXPTR_Msk (0xffffffffu << SSC_RPR_RXPTR_Pos) /**< \brief (SSC_RPR) Receive Pointer Register */
+#define SSC_RPR_RXPTR(value) ((SSC_RPR_RXPTR_Msk & ((value) << SSC_RPR_RXPTR_Pos)))
+/* -------- SSC_RCR : (SSC Offset: 0x104) Receive Counter Register -------- */
+#define SSC_RCR_RXCTR_Pos 0
+#define SSC_RCR_RXCTR_Msk (0xffffu << SSC_RCR_RXCTR_Pos) /**< \brief (SSC_RCR) Receive Counter Register */
+#define SSC_RCR_RXCTR(value) ((SSC_RCR_RXCTR_Msk & ((value) << SSC_RCR_RXCTR_Pos)))
+/* -------- SSC_TPR : (SSC Offset: 0x108) Transmit Pointer Register -------- */
+#define SSC_TPR_TXPTR_Pos 0
+#define SSC_TPR_TXPTR_Msk (0xffffffffu << SSC_TPR_TXPTR_Pos) /**< \brief (SSC_TPR) Transmit Counter Register */
+#define SSC_TPR_TXPTR(value) ((SSC_TPR_TXPTR_Msk & ((value) << SSC_TPR_TXPTR_Pos)))
+/* -------- SSC_TCR : (SSC Offset: 0x10C) Transmit Counter Register -------- */
+#define SSC_TCR_TXCTR_Pos 0
+#define SSC_TCR_TXCTR_Msk (0xffffu << SSC_TCR_TXCTR_Pos) /**< \brief (SSC_TCR) Transmit Counter Register */
+#define SSC_TCR_TXCTR(value) ((SSC_TCR_TXCTR_Msk & ((value) << SSC_TCR_TXCTR_Pos)))
+/* -------- SSC_RNPR : (SSC Offset: 0x110) Receive Next Pointer Register -------- */
+#define SSC_RNPR_RXNPTR_Pos 0
+#define SSC_RNPR_RXNPTR_Msk (0xffffffffu << SSC_RNPR_RXNPTR_Pos) /**< \brief (SSC_RNPR) Receive Next Pointer */
+#define SSC_RNPR_RXNPTR(value) ((SSC_RNPR_RXNPTR_Msk & ((value) << SSC_RNPR_RXNPTR_Pos)))
+/* -------- SSC_RNCR : (SSC Offset: 0x114) Receive Next Counter Register -------- */
+#define SSC_RNCR_RXNCTR_Pos 0
+#define SSC_RNCR_RXNCTR_Msk (0xffffu << SSC_RNCR_RXNCTR_Pos) /**< \brief (SSC_RNCR) Receive Next Counter */
+#define SSC_RNCR_RXNCTR(value) ((SSC_RNCR_RXNCTR_Msk & ((value) << SSC_RNCR_RXNCTR_Pos)))
+/* -------- SSC_TNPR : (SSC Offset: 0x118) Transmit Next Pointer Register -------- */
+#define SSC_TNPR_TXNPTR_Pos 0
+#define SSC_TNPR_TXNPTR_Msk (0xffffffffu << SSC_TNPR_TXNPTR_Pos) /**< \brief (SSC_TNPR) Transmit Next Pointer */
+#define SSC_TNPR_TXNPTR(value) ((SSC_TNPR_TXNPTR_Msk & ((value) << SSC_TNPR_TXNPTR_Pos)))
+/* -------- SSC_TNCR : (SSC Offset: 0x11C) Transmit Next Counter Register -------- */
+#define SSC_TNCR_TXNCTR_Pos 0
+#define SSC_TNCR_TXNCTR_Msk (0xffffu << SSC_TNCR_TXNCTR_Pos) /**< \brief (SSC_TNCR) Transmit Counter Next */
+#define SSC_TNCR_TXNCTR(value) ((SSC_TNCR_TXNCTR_Msk & ((value) << SSC_TNCR_TXNCTR_Pos)))
+/* -------- SSC_PTCR : (SSC Offset: 0x120) Transfer Control Register -------- */
+#define SSC_PTCR_RXTEN (0x1u << 0) /**< \brief (SSC_PTCR) Receiver Transfer Enable */
+#define SSC_PTCR_RXTDIS (0x1u << 1) /**< \brief (SSC_PTCR) Receiver Transfer Disable */
+#define SSC_PTCR_TXTEN (0x1u << 8) /**< \brief (SSC_PTCR) Transmitter Transfer Enable */
+#define SSC_PTCR_TXTDIS (0x1u << 9) /**< \brief (SSC_PTCR) Transmitter Transfer Disable */
+/* -------- SSC_PTSR : (SSC Offset: 0x124) Transfer Status Register -------- */
+#define SSC_PTSR_RXTEN (0x1u << 0) /**< \brief (SSC_PTSR) Receiver Transfer Enable */
+#define SSC_PTSR_TXTEN (0x1u << 8) /**< \brief (SSC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S_SSC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_supc.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_supc.h
new file mode 100644
index 000000000..4dbcb0402
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_supc.h
@@ -0,0 +1,297 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_SUPC_COMPONENT_
+#define _SAM3S_SUPC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Supply Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S_SUPC Supply Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Supc hardware registers */
+typedef struct {
+  WoReg SUPC_CR;   /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */
+  RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */
+  RwReg SUPC_MR;   /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */
+  RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */
+  RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */
+  RoReg SUPC_SR;   /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */
+} Supc;
+#endif /* __ASSEMBLY__ */
+/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */
+#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */
+#define   SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */
+#define   SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */
+#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */
+#define   SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */
+#define   SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */
+#define SUPC_CR_KEY_Pos 24
+#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */
+#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))
+/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */
+#define SUPC_SMMR_SMTH_Pos 0
+#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */
+#define   SUPC_SMMR_SMTH_1_9V (0x0u << 0) /**< \brief (SUPC_SMMR) 1.9 V */
+#define   SUPC_SMMR_SMTH_2_0V (0x1u << 0) /**< \brief (SUPC_SMMR) 2.0 V */
+#define   SUPC_SMMR_SMTH_2_1V (0x2u << 0) /**< \brief (SUPC_SMMR) 2.1 V */
+#define   SUPC_SMMR_SMTH_2_2V (0x3u << 0) /**< \brief (SUPC_SMMR) 2.2 V */
+#define   SUPC_SMMR_SMTH_2_3V (0x4u << 0) /**< \brief (SUPC_SMMR) 2.3 V */
+#define   SUPC_SMMR_SMTH_2_4V (0x5u << 0) /**< \brief (SUPC_SMMR) 2.4 V */
+#define   SUPC_SMMR_SMTH_2_5V (0x6u << 0) /**< \brief (SUPC_SMMR) 2.5 V */
+#define   SUPC_SMMR_SMTH_2_6V (0x7u << 0) /**< \brief (SUPC_SMMR) 2.6 V */
+#define   SUPC_SMMR_SMTH_2_7V (0x8u << 0) /**< \brief (SUPC_SMMR) 2.7 V */
+#define   SUPC_SMMR_SMTH_2_8V (0x9u << 0) /**< \brief (SUPC_SMMR) 2.8 V */
+#define   SUPC_SMMR_SMTH_2_9V (0xAu << 0) /**< \brief (SUPC_SMMR) 2.9 V */
+#define   SUPC_SMMR_SMTH_3_0V (0xBu << 0) /**< \brief (SUPC_SMMR) 3.0 V */
+#define   SUPC_SMMR_SMTH_3_1V (0xCu << 0) /**< \brief (SUPC_SMMR) 3.1 V */
+#define   SUPC_SMMR_SMTH_3_2V (0xDu << 0) /**< \brief (SUPC_SMMR) 3.2 V */
+#define   SUPC_SMMR_SMTH_3_3V (0xEu << 0) /**< \brief (SUPC_SMMR) 3.3 V */
+#define   SUPC_SMMR_SMTH_3_4V (0xFu << 0) /**< \brief (SUPC_SMMR) 3.4 V */
+#define SUPC_SMMR_SMSMPL_Pos 8
+#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */
+#define   SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */
+#define   SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */
+#define   SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */
+#define   SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */
+#define   SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */
+#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */
+#define   SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */
+#define   SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */
+#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */
+#define   SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */
+#define   SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */
+/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */
+#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */
+#define   SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */
+#define   SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */
+#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */
+#define   SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */
+#define   SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */
+#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */
+#define   SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Voltage Regulator is not used */
+#define   SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator is used */
+#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */
+#define   SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */
+#define   SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */
+#define SUPC_MR_KEY_Pos 24
+#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */
+#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))
+/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */
+#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */
+#define   SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */
+#define   SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */
+#define   SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */
+#define   SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */
+#define   SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */
+#define   SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_WKUPDBC_Pos 12
+#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer Period */
+#define   SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
+#define   SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */
+/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */
+#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */
+#define   SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */
+#define   SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */
+#define   SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */
+#define   SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */
+#define   SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */
+#define   SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */
+#define   SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */
+#define   SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */
+#define   SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */
+#define   SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */
+#define   SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */
+#define   SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */
+#define   SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */
+#define   SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */
+#define   SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */
+#define   SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */
+#define   SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */
+#define   SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */
+#define   SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */
+#define   SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */
+#define   SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */
+#define   SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */
+#define   SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */
+#define   SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */
+#define   SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */
+#define   SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */
+#define   SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */
+#define   SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */
+#define   SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */
+#define   SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */
+#define   SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */
+#define   SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */
+#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */
+#define   SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */
+#define   SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */
+#define   SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */
+#define   SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */
+#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */
+#define   SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define   SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */
+#define   SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */
+#define   SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */
+#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */
+#define   SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */
+#define   SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */
+#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */
+#define   SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */
+#define   SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */
+#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */
+#define   SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */
+#define   SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */
+#define   SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */
+#define   SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */
+#define   SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */
+#define   SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */
+#define   SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */
+#define   SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */
+#define   SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */
+#define   SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */
+#define   SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */
+#define   SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */
+#define   SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */
+#define   SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */
+#define   SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */
+#define   SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+
+/*@}*/
+
+
+#endif /* _SAM3S_SUPC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_tc.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_tc.h
new file mode 100644
index 000000000..531aab046
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_tc.h
@@ -0,0 +1,303 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_TC_COMPONENT_
+#define _SAM3S_TC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Timer Counter */
+/* ============================================================================= */
+/** \addtogroup SAM3S_TC Timer Counter */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief TcChannel hardware registers */
+typedef struct {
+  RwReg      TC_CCR;        /**< \brief (TcChannel Offset: 0x0) Channel Control Register */
+  RwReg      TC_CMR;        /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */
+  RwReg      TC_SMMR;       /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */
+  RoReg      Reserved1[1];
+  RwReg      TC_CV;         /**< \brief (TcChannel Offset: 0x10) Counter Value */
+  RwReg      TC_RA;         /**< \brief (TcChannel Offset: 0x14) Register A */
+  RwReg      TC_RB;         /**< \brief (TcChannel Offset: 0x18) Register B */
+  RwReg      TC_RC;         /**< \brief (TcChannel Offset: 0x1C) Register C */
+  RwReg      TC_SR;         /**< \brief (TcChannel Offset: 0x20) Status Register */
+  RwReg      TC_IER;        /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
+  RwReg      TC_IDR;        /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
+  RwReg      TC_IMR;        /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */
+  RoReg      Reserved2[4];
+} TcChannel;
+/** \brief Tc hardware registers */
+#define TCCHANNEL_NUMBER 3
+typedef struct {
+  TcChannel  TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */
+  WoReg      TC_BCR;        /**< \brief (Tc Offset: 0xC0) Block Control Register */
+  RwReg      TC_BMR;        /**< \brief (Tc Offset: 0xC4) Block Mode Register */
+  WoReg      TC_QIER;       /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */
+  WoReg      TC_QIDR;       /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */
+  RoReg      TC_QIMR;       /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */
+  RoReg      TC_QISR;       /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */
+  RwReg      TC_FMR;        /**< \brief (Tc Offset: 0xD8) Fault Mode Register */
+  RoReg      Reserved1[2];
+  RwReg      TC_WPMR;       /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */
+} Tc;
+#endif /* __ASSEMBLY__ */
+/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */
+#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */
+#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */
+#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */
+/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */
+#define TC_CMR_TCCLKS_Pos 0
+#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */
+#define   TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */
+#define   TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */
+#define   TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */
+#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */
+#define TC_CMR_BURST_Pos 4
+#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */
+#define   TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define   TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */
+#define   TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */
+#define   TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */
+#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */
+#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */
+#define TC_CMR_ETRGEDG_Pos 8
+#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */
+#define   TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define   TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define   TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define   TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */
+#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */
+#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */
+#define TC_CMR_LDRA_Pos 16
+#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */
+#define   TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define   TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define   TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define   TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_LDRB_Pos 18
+#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */
+#define   TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define   TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define   TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define   TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */
+#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */
+#define TC_CMR_EEVTEDG_Pos 8
+#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */
+#define   TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */
+#define   TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define   TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define   TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_EEVT_Pos 10
+#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */
+#define   TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */
+#define   TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */
+#define   TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */
+#define   TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */
+#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */
+#define TC_CMR_WAVSEL_Pos 13
+#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */
+#define   TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */
+#define TC_CMR_ACPA_Pos 16
+#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */
+#define   TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ACPC_Pos 18
+#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */
+#define   TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_AEEVT_Pos 20
+#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */
+#define   TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */
+#define   TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ASWTRG_Pos 22
+#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */
+#define   TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPB_Pos 24
+#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */
+#define   TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPC_Pos 26
+#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */
+#define   TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BEEVT_Pos 28
+#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */
+#define   TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BSWTRG_Pos 30
+#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */
+#define   TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */
+/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */
+#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */
+#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) DOWN Count */
+/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */
+#define TC_CV_CV_Pos 0
+#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */
+/* -------- TC_RA : (TC Offset: N/A) Register A -------- */
+#define TC_RA_RA_Pos 0
+#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */
+#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))
+/* -------- TC_RB : (TC Offset: N/A) Register B -------- */
+#define TC_RB_RB_Pos 0
+#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */
+#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))
+/* -------- TC_RC : (TC Offset: N/A) Register C -------- */
+#define TC_RC_RC_Pos 0
+#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */
+#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))
+/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */
+#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */
+#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */
+#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */
+#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */
+#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */
+#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */
+#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */
+#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */
+#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */
+#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */
+#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */
+/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */
+#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */
+#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */
+#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */
+#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */
+#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */
+#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */
+#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */
+#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */
+/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */
+#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */
+#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */
+#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */
+#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */
+#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */
+#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */
+#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */
+#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */
+/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */
+#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */
+#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */
+#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */
+#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */
+#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */
+#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */
+#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */
+#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */
+/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
+#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */
+/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
+#define TC_BMR_TC0XC0S_Pos 0
+#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */
+#define   TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */
+#define   TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */
+#define   TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */
+#define TC_BMR_TC1XC1S_Pos 2
+#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */
+#define   TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */
+#define   TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */
+#define   TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */
+#define TC_BMR_TC2XC2S_Pos 4
+#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */
+#define   TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */
+#define   TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */
+#define   TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */
+#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */
+#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */
+#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */
+#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */
+#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */
+#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */
+#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */
+#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */
+#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */
+#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */
+#define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR)  */
+#define TC_BMR_MAXFILT_Pos 20
+#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */
+#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))
+/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */
+#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */
+#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */
+#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */
+/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */
+#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */
+#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */
+#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */
+/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */
+#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */
+#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */
+#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */
+/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */
+#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */
+#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */
+#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */
+#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */
+/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */
+#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */
+#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */
+/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */
+#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protect Enable */
+#define TC_WPMR_WPKEY_Pos 8
+#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protect KEY */
+#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3S_TC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_twi.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_twi.h
new file mode 100644
index 000000000..f009592a6
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_twi.h
@@ -0,0 +1,217 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_TWI_COMPONENT_
+#define _SAM3S_TWI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Two-wire Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3S_TWI Two-wire Interface */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Twi hardware registers */
+typedef struct {
+  WoReg TWI_CR;        /**< \brief (Twi Offset: 0x00) Control Register */
+  RwReg TWI_MMR;       /**< \brief (Twi Offset: 0x04) Master Mode Register */
+  RwReg TWI_SMR;       /**< \brief (Twi Offset: 0x08) Slave Mode Register */
+  RwReg TWI_IADR;      /**< \brief (Twi Offset: 0x0C) Internal Address Register */
+  RwReg TWI_CWGR;      /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */
+  RoReg Reserved1[3];
+  RoReg TWI_SR;        /**< \brief (Twi Offset: 0x20) Status Register */
+  WoReg TWI_IER;       /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */
+  WoReg TWI_IDR;       /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */
+  RoReg TWI_IMR;       /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */
+  RoReg TWI_RHR;       /**< \brief (Twi Offset: 0x30) Receive Holding Register */
+  WoReg TWI_THR;       /**< \brief (Twi Offset: 0x34) Transmit Holding Register */
+  RoReg Reserved2[50];
+  RwReg TWI_RPR;       /**< \brief (Twi Offset: 0x100) Receive Pointer Register */
+  RwReg TWI_RCR;       /**< \brief (Twi Offset: 0x104) Receive Counter Register */
+  RwReg TWI_TPR;       /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */
+  RwReg TWI_TCR;       /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */
+  RwReg TWI_RNPR;      /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */
+  RwReg TWI_RNCR;      /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */
+  RwReg TWI_TNPR;      /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */
+  RwReg TWI_TNCR;      /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */
+  WoReg TWI_PTCR;      /**< \brief (Twi Offset: 0x120) Transfer Control Register */
+  RoReg TWI_PTSR;      /**< \brief (Twi Offset: 0x124) Transfer Status Register */
+} Twi;
+#endif /* __ASSEMBLY__ */
+/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */
+#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */
+#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */
+#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */
+#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */
+#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */
+#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */
+#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */
+#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */
+/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */
+#define TWI_MMR_IADRSZ_Pos 8
+#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */
+#define   TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */
+#define   TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */
+#define   TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */
+#define   TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */
+#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */
+#define TWI_MMR_DADR_Pos 16
+#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */
+#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))
+/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */
+#define TWI_SMR_SADR_Pos 16
+#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */
+#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))
+/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */
+#define TWI_IADR_IADR_Pos 0
+#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */
+#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))
+/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */
+#define TWI_CWGR_CLDIV_Pos 0
+#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */
+#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))
+#define TWI_CWGR_CHDIV_Pos 8
+#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */
+#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))
+#define TWI_CWGR_CKDIV_Pos 16
+#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */
+#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))
+/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */
+#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */
+#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */
+#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */
+#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */
+#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */
+#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */
+#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */
+#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */
+#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */
+#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */
+#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */
+#define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */
+#define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */
+#define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */
+#define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */
+/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */
+#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */
+#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */
+#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */
+#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */
+#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */
+#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */
+#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */
+#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */
+#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */
+#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */
+#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */
+#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */
+#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */
+#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */
+/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */
+#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */
+#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */
+#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */
+#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */
+#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */
+#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */
+#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */
+#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */
+#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */
+#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */
+#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */
+#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */
+#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */
+#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */
+/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */
+#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */
+#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */
+#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */
+#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */
+#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */
+#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */
+#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */
+#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */
+#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */
+#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */
+#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */
+#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */
+#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */
+#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */
+/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */
+#define TWI_RHR_RXDATA_Pos 0
+#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */
+/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */
+#define TWI_THR_TXDATA_Pos 0
+#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */
+#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))
+/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */
+#define TWI_RPR_RXPTR_Pos 0
+#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */
+#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos)))
+/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */
+#define TWI_RCR_RXCTR_Pos 0
+#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */
+#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos)))
+/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */
+#define TWI_TPR_TXPTR_Pos 0
+#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */
+#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos)))
+/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */
+#define TWI_TCR_TXCTR_Pos 0
+#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */
+#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos)))
+/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */
+#define TWI_RNPR_RXNPTR_Pos 0
+#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */
+#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos)))
+/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */
+#define TWI_RNCR_RXNCTR_Pos 0
+#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */
+#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos)))
+/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define TWI_TNPR_TXNPTR_Pos 0
+#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */
+#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos)))
+/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define TWI_TNCR_TXNCTR_Pos 0
+#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */
+#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos)))
+/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */
+#define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */
+#define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */
+#define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */
+#define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */
+/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */
+#define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */
+#define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S_TWI_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_uart.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_uart.h
new file mode 100644
index 000000000..9e0daefd6
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_uart.h
@@ -0,0 +1,185 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_UART_COMPONENT_
+#define _SAM3S_UART_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM3S_UART Universal Asynchronous Receiver Transmitter */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Uart hardware registers */
+typedef struct {
+  WoReg UART_CR;       /**< \brief (Uart Offset: 0x0000) Control Register */
+  RwReg UART_MR;       /**< \brief (Uart Offset: 0x0004) Mode Register */
+  WoReg UART_IER;      /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */
+  WoReg UART_IDR;      /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */
+  RoReg UART_IMR;      /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */
+  RoReg UART_SR;       /**< \brief (Uart Offset: 0x0014) Status Register */
+  RoReg UART_RHR;      /**< \brief (Uart Offset: 0x0018) Receive Holding Register */
+  WoReg UART_THR;      /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */
+  RwReg UART_BRGR;     /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */
+  RoReg Reserved1[55];
+  RwReg UART_RPR;      /**< \brief (Uart Offset: 0x100) Receive Pointer Register */
+  RwReg UART_RCR;      /**< \brief (Uart Offset: 0x104) Receive Counter Register */
+  RwReg UART_TPR;      /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */
+  RwReg UART_TCR;      /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */
+  RwReg UART_RNPR;     /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */
+  RwReg UART_RNCR;     /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */
+  RwReg UART_TNPR;     /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */
+  RwReg UART_TNCR;     /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */
+  WoReg UART_PTCR;     /**< \brief (Uart Offset: 0x120) Transfer Control Register */
+  RoReg UART_PTSR;     /**< \brief (Uart Offset: 0x124) Transfer Status Register */
+} Uart;
+#endif /* __ASSEMBLY__ */
+/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
+#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */
+#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */
+#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */
+#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */
+#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */
+#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */
+#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */
+/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
+#define UART_MR_PAR_Pos 9
+#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */
+#define   UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */
+#define   UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */
+#define   UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */
+#define   UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */
+#define   UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */
+#define UART_MR_CHMODE_Pos 14
+#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */
+#define   UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */
+#define   UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */
+#define   UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */
+#define   UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */
+/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
+#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */
+#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */
+#define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */
+#define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */
+#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */
+#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */
+#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */
+#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */
+#define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */
+#define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */
+/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
+#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */
+#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */
+#define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */
+#define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */
+#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */
+#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */
+#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */
+#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */
+#define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */
+#define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */
+/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
+#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */
+#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */
+#define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */
+#define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */
+#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */
+#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */
+#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */
+#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */
+#define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */
+#define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */
+/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
+#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */
+#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */
+#define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */
+#define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */
+#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */
+#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */
+#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */
+#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */
+#define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */
+#define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */
+/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
+#define UART_RHR_RXCHR_Pos 0
+#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */
+/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
+#define UART_THR_TXCHR_Pos 0
+#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */
+#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
+/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define UART_BRGR_CD_Pos 0
+#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */
+#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
+/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */
+#define UART_RPR_RXPTR_Pos 0
+#define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */
+#define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos)))
+/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */
+#define UART_RCR_RXCTR_Pos 0
+#define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */
+#define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos)))
+/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */
+#define UART_TPR_TXPTR_Pos 0
+#define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */
+#define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos)))
+/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */
+#define UART_TCR_TXCTR_Pos 0
+#define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */
+#define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos)))
+/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */
+#define UART_RNPR_RXNPTR_Pos 0
+#define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */
+#define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos)))
+/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */
+#define UART_RNCR_RXNCTR_Pos 0
+#define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */
+#define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos)))
+/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define UART_TNPR_TXNPTR_Pos 0
+#define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */
+#define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos)))
+/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define UART_TNCR_TXNCTR_Pos 0
+#define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */
+#define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos)))
+/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */
+#define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */
+#define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */
+#define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */
+#define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */
+/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */
+#define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */
+#define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S_UART_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_udp.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_udp.h
new file mode 100644
index 000000000..be2b7b5dc
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_udp.h
@@ -0,0 +1,185 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_UDP_COMPONENT_
+#define _SAM3S_UDP_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR USB Device Port */
+/* ============================================================================= */
+/** \addtogroup SAM3S_UDP USB Device Port */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Udp hardware registers */
+typedef struct {
+  RoReg UDP_FRM_NUM;  /**< \brief (Udp Offset: 0x000) Frame Number Register */
+  RwReg UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */
+  RwReg UDP_FADDR;    /**< \brief (Udp Offset: 0x008) Function Address Register */
+  RoReg Reserved1[1];
+  WoReg UDP_IER;      /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */
+  WoReg UDP_IDR;      /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */
+  RoReg UDP_IMR;      /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */
+  RoReg UDP_ISR;      /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */
+  WoReg UDP_ICR;      /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */
+  RoReg Reserved2[1];
+  RwReg UDP_RST_EP;   /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */
+  RoReg Reserved3[1];
+  RwReg UDP_CSR[8];   /**< \brief (Udp Offset: 0x030) Endpoint Control and Status Register */
+  RwReg UDP_FDR[8];   /**< \brief (Udp Offset: 0x050) Endpoint FIFO Data Register */
+  RoReg Reserved4[1];
+  RwReg UDP_TXVC;     /**< \brief (Udp Offset: 0x074) Transceiver Control Register */
+} Udp;
+#endif /* __ASSEMBLY__ */
+/* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */
+#define UDP_FRM_NUM_FRM_NUM_Pos 0
+#define UDP_FRM_NUM_FRM_NUM_Msk (0x7ffu << UDP_FRM_NUM_FRM_NUM_Pos) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */
+#define UDP_FRM_NUM_FRM_ERR (0x1u << 16) /**< \brief (UDP_FRM_NUM) Frame Error */
+#define UDP_FRM_NUM_FRM_OK (0x1u << 17) /**< \brief (UDP_FRM_NUM) Frame OK */
+/* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */
+#define UDP_GLB_STAT_FADDEN (0x1u << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */
+#define UDP_GLB_STAT_CONFG (0x1u << 1) /**< \brief (UDP_GLB_STAT) Configured */
+#define UDP_GLB_STAT_ESR (0x1u << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */
+#define UDP_GLB_STAT_RSMINPR (0x1u << 3) /**< \brief (UDP_GLB_STAT)  */
+#define UDP_GLB_STAT_RMWUPE (0x1u << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */
+/* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */
+#define UDP_FADDR_FADD_Pos 0
+#define UDP_FADDR_FADD_Msk (0x7fu << UDP_FADDR_FADD_Pos) /**< \brief (UDP_FADDR) Function Address Value */
+#define UDP_FADDR_FADD(value) ((UDP_FADDR_FADD_Msk & ((value) << UDP_FADDR_FADD_Pos)))
+#define UDP_FADDR_FEN (0x1u << 8) /**< \brief (UDP_FADDR) Function Enable */
+/* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */
+#define UDP_IER_EP0INT (0x1u << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */
+#define UDP_IER_EP1INT (0x1u << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */
+#define UDP_IER_EP2INT (0x1u << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */
+#define UDP_IER_EP3INT (0x1u << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */
+#define UDP_IER_EP4INT (0x1u << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */
+#define UDP_IER_EP5INT (0x1u << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */
+#define UDP_IER_EP6INT (0x1u << 6) /**< \brief (UDP_IER) Enable Endpoint 6 Interrupt */
+#define UDP_IER_EP7INT (0x1u << 7) /**< \brief (UDP_IER) Enable Endpoint 7 Interrupt */
+#define UDP_IER_RXSUSP (0x1u << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */
+#define UDP_IER_RXRSM (0x1u << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */
+#define UDP_IER_EXTRSM (0x1u << 10) /**< \brief (UDP_IER)  */
+#define UDP_IER_SOFINT (0x1u << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */
+#define UDP_IER_WAKEUP (0x1u << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */
+/* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */
+#define UDP_IDR_EP0INT (0x1u << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */
+#define UDP_IDR_EP1INT (0x1u << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */
+#define UDP_IDR_EP2INT (0x1u << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */
+#define UDP_IDR_EP3INT (0x1u << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */
+#define UDP_IDR_EP4INT (0x1u << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */
+#define UDP_IDR_EP5INT (0x1u << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */
+#define UDP_IDR_EP6INT (0x1u << 6) /**< \brief (UDP_IDR) Disable Endpoint 6 Interrupt */
+#define UDP_IDR_EP7INT (0x1u << 7) /**< \brief (UDP_IDR) Disable Endpoint 7 Interrupt */
+#define UDP_IDR_RXSUSP (0x1u << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */
+#define UDP_IDR_RXRSM (0x1u << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */
+#define UDP_IDR_EXTRSM (0x1u << 10) /**< \brief (UDP_IDR)  */
+#define UDP_IDR_SOFINT (0x1u << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */
+#define UDP_IDR_WAKEUP (0x1u << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */
+/* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */
+#define UDP_IMR_EP0INT (0x1u << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */
+#define UDP_IMR_EP1INT (0x1u << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */
+#define UDP_IMR_EP2INT (0x1u << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */
+#define UDP_IMR_EP3INT (0x1u << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */
+#define UDP_IMR_EP4INT (0x1u << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */
+#define UDP_IMR_EP5INT (0x1u << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */
+#define UDP_IMR_EP6INT (0x1u << 6) /**< \brief (UDP_IMR) Mask Endpoint 6 Interrupt */
+#define UDP_IMR_EP7INT (0x1u << 7) /**< \brief (UDP_IMR) Mask Endpoint 7 Interrupt */
+#define UDP_IMR_RXSUSP (0x1u << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */
+#define UDP_IMR_RXRSM (0x1u << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */
+#define UDP_IMR_EXTRSM (0x1u << 10) /**< \brief (UDP_IMR)  */
+#define UDP_IMR_SOFINT (0x1u << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */
+#define UDP_IMR_BIT12 (0x1u << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */
+#define UDP_IMR_WAKEUP (0x1u << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */
+/* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */
+#define UDP_ISR_EP0INT (0x1u << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */
+#define UDP_ISR_EP1INT (0x1u << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */
+#define UDP_ISR_EP2INT (0x1u << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */
+#define UDP_ISR_EP3INT (0x1u << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */
+#define UDP_ISR_EP4INT (0x1u << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */
+#define UDP_ISR_EP5INT (0x1u << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */
+#define UDP_ISR_EP6INT (0x1u << 6) /**< \brief (UDP_ISR) Endpoint 6 Interrupt Status */
+#define UDP_ISR_EP7INT (0x1u << 7) /**< \brief (UDP_ISR) Endpoint 7Interrupt Status */
+#define UDP_ISR_RXSUSP (0x1u << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */
+#define UDP_ISR_RXRSM (0x1u << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */
+#define UDP_ISR_EXTRSM (0x1u << 10) /**< \brief (UDP_ISR)  */
+#define UDP_ISR_SOFINT (0x1u << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */
+#define UDP_ISR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */
+#define UDP_ISR_WAKEUP (0x1u << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */
+/* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */
+#define UDP_ICR_RXSUSP (0x1u << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */
+#define UDP_ICR_RXRSM (0x1u << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */
+#define UDP_ICR_EXTRSM (0x1u << 10) /**< \brief (UDP_ICR)  */
+#define UDP_ICR_SOFINT (0x1u << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */
+#define UDP_ICR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */
+#define UDP_ICR_WAKEUP (0x1u << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */
+/* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */
+#define UDP_RST_EP_EP0 (0x1u << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */
+#define UDP_RST_EP_EP1 (0x1u << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */
+#define UDP_RST_EP_EP2 (0x1u << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */
+#define UDP_RST_EP_EP3 (0x1u << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */
+#define UDP_RST_EP_EP4 (0x1u << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */
+#define UDP_RST_EP_EP5 (0x1u << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */
+#define UDP_RST_EP_EP6 (0x1u << 6) /**< \brief (UDP_RST_EP) Reset Endpoint 6 */
+#define UDP_RST_EP_EP7 (0x1u << 7) /**< \brief (UDP_RST_EP) Reset Endpoint 7 */
+/* -------- UDP_CSR[8] : (UDP Offset: 0x030) Endpoint Control and Status Register -------- */
+#define UDP_CSR_TXCOMP (0x1u << 0) /**< \brief (UDP_CSR[8]) Generates an IN Packet with Data Previously Written in the DPR */
+#define UDP_CSR_RX_DATA_BK0 (0x1u << 1) /**< \brief (UDP_CSR[8]) Receive Data Bank 0 */
+#define UDP_CSR_RXSETUP (0x1u << 2) /**< \brief (UDP_CSR[8]) Received Setup */
+#define UDP_CSR_STALLSENT (0x1u << 3) /**< \brief (UDP_CSR[8]) Stall Sent (Control, Bulk Interrupt Endpoints)/ISOERROR (Isochronous Endpoints) */
+#define UDP_CSR_ISOERROR (0x1u << 3) /**< \brief (UDP_CSR[8]) Stall Sent (Control, Bulk Interrupt Endpoints)/ISOERROR (Isochronous Endpoints) */
+#define UDP_CSR_TXPKTRDY (0x1u << 4) /**< \brief (UDP_CSR[8]) Transmit Packet Ready */
+#define UDP_CSR_FORCESTALL (0x1u << 5) /**< \brief (UDP_CSR[8]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */
+#define UDP_CSR_RX_DATA_BK1 (0x1u << 6) /**< \brief (UDP_CSR[8]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */
+#define UDP_CSR_DIR (0x1u << 7) /**< \brief (UDP_CSR[8]) Transfer Direction (only available for control endpoints) */
+#define UDP_CSR_EPTYPE_Pos 8
+#define UDP_CSR_EPTYPE_Msk (0x7u << UDP_CSR_EPTYPE_Pos) /**< \brief (UDP_CSR[8]) Endpoint Type */
+#define   UDP_CSR_EPTYPE_CTRL (0x0u << 8) /**< \brief (UDP_CSR[8]) Control */
+#define   UDP_CSR_EPTYPE_ISO_OUT (0x1u << 8) /**< \brief (UDP_CSR[8]) Isochronous OUT */
+#define   UDP_CSR_EPTYPE_BULK_OUT (0x2u << 8) /**< \brief (UDP_CSR[8]) Bulk OUT */
+#define   UDP_CSR_EPTYPE_INT_OUT (0x3u << 8) /**< \brief (UDP_CSR[8]) Interrupt OUT */
+#define   UDP_CSR_EPTYPE_ISO_IN (0x5u << 8) /**< \brief (UDP_CSR[8]) Isochronous IN */
+#define   UDP_CSR_EPTYPE_BULK_IN (0x6u << 8) /**< \brief (UDP_CSR[8]) Bulk IN */
+#define   UDP_CSR_EPTYPE_INT_IN (0x7u << 8) /**< \brief (UDP_CSR[8]) Interrupt IN */
+#define UDP_CSR_DTGLE (0x1u << 11) /**< \brief (UDP_CSR[8]) Data Toggle */
+#define UDP_CSR_EPEDS (0x1u << 15) /**< \brief (UDP_CSR[8]) Endpoint Enable Disable */
+#define UDP_CSR_RXBYTECNT_Pos 16
+#define UDP_CSR_RXBYTECNT_Msk (0x7ffu << UDP_CSR_RXBYTECNT_Pos) /**< \brief (UDP_CSR[8]) Number of Bytes Available in the FIFO */
+#define UDP_CSR_RXBYTECNT(value) ((UDP_CSR_RXBYTECNT_Msk & ((value) << UDP_CSR_RXBYTECNT_Pos)))
+/* -------- UDP_FDR[8] : (UDP Offset: 0x050) Endpoint FIFO Data Register -------- */
+#define UDP_FDR_FIFO_DATA_Pos 0
+#define UDP_FDR_FIFO_DATA_Msk (0xffu << UDP_FDR_FIFO_DATA_Pos) /**< \brief (UDP_FDR[8]) FIFO Data Value */
+#define UDP_FDR_FIFO_DATA(value) ((UDP_FDR_FIFO_DATA_Msk & ((value) << UDP_FDR_FIFO_DATA_Pos)))
+/* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */
+#define UDP_TXVC_TXVDIS (0x1u << 8) /**< \brief (UDP_TXVC) Transceiver Disable */
+#define UDP_TXVC_PUON (0x1u << 9) /**< \brief (UDP_TXVC) Pullup On */
+
+/*@}*/
+
+
+#endif /* _SAM3S_UDP_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_usart.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_usart.h
new file mode 100644
index 000000000..83dd265d8
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_usart.h
@@ -0,0 +1,361 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_USART_COMPONENT_
+#define _SAM3S_USART_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM3S_USART Universal Synchronous Asynchronous Receiver Transmitter */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Usart hardware registers */
+typedef struct {
+  WoReg US_CR;         /**< \brief (Usart Offset: 0x0000) Control Register */
+  RwReg US_MR;         /**< \brief (Usart Offset: 0x0004) Mode Register */
+  WoReg US_IER;        /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */
+  WoReg US_IDR;        /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */
+  RoReg US_IMR;        /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */
+  RoReg US_CSR;        /**< \brief (Usart Offset: 0x0014) Channel Status Register */
+  RoReg US_RHR;        /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */
+  WoReg US_THR;        /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */
+  RwReg US_BRGR;       /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */
+  RwReg US_RTOR;       /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */
+  RwReg US_TTGR;       /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */
+  RoReg Reserved1[5];
+  RwReg US_FIDI;       /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */
+  RoReg US_NER;        /**< \brief (Usart Offset: 0x0044) Number of Errors Register */
+  RoReg Reserved2[1];
+  RwReg US_IF;         /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */
+  RwReg US_MAN;        /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */
+  RoReg Reserved3[36];
+  RwReg US_WPMR;       /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */
+  RoReg US_WPSR;       /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved4[4];
+  RoReg US_VERSION;    /**< \brief (Usart Offset: 0xFC) Version Register */
+  RwReg US_RPR;        /**< \brief (Usart Offset: 0x100) Receive Pointer Register */
+  RwReg US_RCR;        /**< \brief (Usart Offset: 0x104) Receive Counter Register */
+  RwReg US_TPR;        /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */
+  RwReg US_TCR;        /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */
+  RwReg US_RNPR;       /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */
+  RwReg US_RNCR;       /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */
+  RwReg US_TNPR;       /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */
+  RwReg US_TNCR;       /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */
+  WoReg US_PTCR;       /**< \brief (Usart Offset: 0x120) Transfer Control Register */
+  RoReg US_PTSR;       /**< \brief (Usart Offset: 0x124) Transfer Status Register */
+} Usart;
+#endif /* __ASSEMBLY__ */
+/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
+#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */
+#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */
+#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */
+#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */
+#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */
+#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */
+#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */
+#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */
+#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */
+#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */
+#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */
+#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */
+#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */
+#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */
+#define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */
+#define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */
+#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */
+#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */
+#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */
+#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */
+/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
+#define US_MR_USART_MODE_Pos 0
+#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR)  */
+#define   US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */
+#define   US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */
+#define   US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */
+#define   US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */
+#define   US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */
+#define   US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */
+#define   US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */
+#define   US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */
+#define   US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */
+#define US_MR_USCLKS_Pos 4
+#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */
+#define   US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */
+#define   US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */
+#define   US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */
+#define US_MR_CHRL_Pos 6
+#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */
+#define   US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */
+#define   US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */
+#define   US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */
+#define   US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */
+#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */
+#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */
+#define US_MR_PAR_Pos 9
+#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */
+#define   US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */
+#define   US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */
+#define   US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */
+#define   US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */
+#define   US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */
+#define   US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */
+#define US_MR_NBSTOP_Pos 12
+#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */
+#define   US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */
+#define   US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */
+#define   US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */
+#define US_MR_CHMODE_Pos 14
+#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */
+#define   US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */
+#define   US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */
+#define   US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */
+#define   US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */
+#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */
+#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */
+#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */
+#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */
+#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */
+#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */
+#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */
+#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */
+#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) INverted Data */
+#define US_MR_MAX_ITERATION_Pos 24
+#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR)  */
+#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))
+#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */
+#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */
+#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */
+#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */
+/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
+#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */
+#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */
+#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */
+#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */
+#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */
+#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */
+#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */
+#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */
+#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */
+#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */
+#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached */
+#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error */
+#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */
+#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */
+#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non AcknowledgeInterrupt Enable */
+#define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */
+#define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */
+#define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */
+#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
+#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */
+/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
+#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */
+#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */
+#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */
+#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */
+#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */
+#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */
+#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */
+#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */
+#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */
+#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */
+#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max number of Repetitions Reached Disable */
+#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Disable */
+#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */
+#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */
+#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non AcknowledgeInterrupt Disable */
+#define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */
+#define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */
+#define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */
+#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
+#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */
+/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
+#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */
+#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */
+#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */
+#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */
+#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */
+#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */
+#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */
+#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */
+#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */
+#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
+#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max number of Repetitions Reached Mask */
+#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Mask */
+#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */
+#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */
+#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non AcknowledgeInterrupt Mask */
+#define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */
+#define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */
+#define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */
+#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
+#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */
+/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
+#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */
+#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */
+#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */
+#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */
+#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */
+#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */
+#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */
+#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */
+#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */
+#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */
+#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max number of Repetitions Reached */
+#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) SPI Underrun Error */
+#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */
+#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */
+#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non AcknowledgeInterrupt */
+#define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */
+#define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */
+#define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */
+#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */
+#define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */
+#define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */
+#define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */
+#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */
+#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */
+/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */
+#define US_RHR_RXCHR_Pos 0
+#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */
+#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */
+/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */
+#define US_THR_TXCHR_Pos 0
+#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */
+#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
+#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be transmitted */
+/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define US_BRGR_CD_Pos 0
+#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */
+#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
+#define US_BRGR_FP_Pos 16
+#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */
+#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
+/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
+#define US_RTOR_TO_Pos 0
+#define US_RTOR_TO_Msk (0xffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */
+#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
+/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
+#define US_TTGR_TG_Pos 0
+#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */
+#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
+/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */
+#define US_FIDI_FI_DI_RATIO_Pos 0
+#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */
+#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))
+/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */
+#define US_NER_NB_ERRORS_Pos 0
+#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */
+/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */
+#define US_IF_IRDA_FILTER_Pos 0
+#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */
+#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))
+/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */
+#define US_MAN_TX_PL_Pos 0
+#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */
+#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))
+#define US_MAN_TX_PP_Pos 8
+#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */
+#define   US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */
+#define   US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */
+#define   US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */
+#define   US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */
+#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */
+#define US_MAN_RX_PL_Pos 16
+#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */
+#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))
+#define US_MAN_RX_PP_Pos 24
+#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */
+#define   US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */
+#define   US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */
+#define   US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */
+#define   US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */
+#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */
+#define US_MAN_STUCKTO1 (0x1u << 29) /**< \brief (US_MAN)  */
+#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift compensation */
+/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */
+#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */
+#define US_WPMR_WPKEY_Pos 8
+#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */
+#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))
+/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */
+#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */
+#define US_WPSR_WPVSRC_Pos 8
+#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */
+/* -------- US_VERSION : (USART Offset: 0xFC) Version Register -------- */
+#define US_VERSION_VERSION_Pos 0
+#define US_VERSION_VERSION_Msk (0xfffu << US_VERSION_VERSION_Pos) /**< \brief (US_VERSION)  */
+#define US_VERSION_MFN_Pos 16
+#define US_VERSION_MFN_Msk (0x7u << US_VERSION_MFN_Pos) /**< \brief (US_VERSION)  */
+/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */
+#define US_RPR_RXPTR_Pos 0
+#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */
+#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos)))
+/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */
+#define US_RCR_RXCTR_Pos 0
+#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */
+#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos)))
+/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */
+#define US_TPR_TXPTR_Pos 0
+#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */
+#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos)))
+/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */
+#define US_TCR_TXCTR_Pos 0
+#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */
+#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos)))
+/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */
+#define US_RNPR_RXNPTR_Pos 0
+#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */
+#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos)))
+/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */
+#define US_RNCR_RXNCTR_Pos 0
+#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */
+#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos)))
+/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define US_TNPR_TXNPTR_Pos 0
+#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */
+#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos)))
+/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define US_TNCR_TXNCTR_Pos 0
+#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */
+#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos)))
+/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */
+#define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */
+#define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */
+#define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */
+#define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */
+/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */
+#define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */
+#define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S_USART_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_wdt.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_wdt.h
new file mode 100644
index 000000000..842198ad8
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/component_wdt.h
@@ -0,0 +1,72 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_WDT_COMPONENT_
+#define _SAM3S_WDT_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Watchdog Timer */
+/* ============================================================================= */
+/** \addtogroup SAM3S_WDT Watchdog Timer */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Wdt hardware registers */
+typedef struct {
+  WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */
+  RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */
+  RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */
+} Wdt;
+#endif /* __ASSEMBLY__ */
+/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */
+#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */
+#define WDT_CR_KEY_Pos 24
+#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */
+#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))
+/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */
+#define WDT_MR_WDV_Pos 0
+#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */
+#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))
+#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */
+#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */
+#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */
+#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */
+#define WDT_MR_WDD_Pos 16
+#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */
+#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))
+#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */
+#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */
+/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */
+#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */
+#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */
+
+/*@}*/
+
+
+#endif /* _SAM3S_WDT_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_acc.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_acc.h
new file mode 100644
index 000000000..c8db6714f
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_acc.h
@@ -0,0 +1,56 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_ACC_INSTANCE_
+#define _SAM3S_ACC_INSTANCE_
+
+/* ========== Register definition for ACC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_ACC_CR            (0x40040000U) /**< \brief (ACC) Control Register */
+#define REG_ACC_MR            (0x40040004U) /**< \brief (ACC) Mode Register */
+#define REG_ACC_IER           (0x40040024U) /**< \brief (ACC) Interrupt Enable Register */
+#define REG_ACC_IDR           (0x40040028U) /**< \brief (ACC) Interrupt Disable Register */
+#define REG_ACC_IMR           (0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */
+#define REG_ACC_ISR           (0x40040030U) /**< \brief (ACC) Interrupt Status Register */
+#define REG_ACC_ACR           (0x40040094U) /**< \brief (ACC) Analog Control Register */
+#define REG_ACC_WPMR          (0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */
+#define REG_ACC_WPSR          (0x400400E8U) /**< \brief (ACC) Write Protect Status Register */
+#else
+#define REG_ACC_CR   (*(WoReg*)0x40040000U) /**< \brief (ACC) Control Register */
+#define REG_ACC_MR   (*(RwReg*)0x40040004U) /**< \brief (ACC) Mode Register */
+#define REG_ACC_IER  (*(WoReg*)0x40040024U) /**< \brief (ACC) Interrupt Enable Register */
+#define REG_ACC_IDR  (*(WoReg*)0x40040028U) /**< \brief (ACC) Interrupt Disable Register */
+#define REG_ACC_IMR  (*(RoReg*)0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */
+#define REG_ACC_ISR  (*(RoReg*)0x40040030U) /**< \brief (ACC) Interrupt Status Register */
+#define REG_ACC_ACR  (*(RwReg*)0x40040094U) /**< \brief (ACC) Analog Control Register */
+#define REG_ACC_WPMR (*(RwReg*)0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */
+#define REG_ACC_WPSR (*(RoReg*)0x400400E8U) /**< \brief (ACC) Write Protect Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_ACC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_adc.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_adc.h
new file mode 100644
index 000000000..763483e7e
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_adc.h
@@ -0,0 +1,100 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_ADC_INSTANCE_
+#define _SAM3S_ADC_INSTANCE_
+
+/* ========== Register definition for ADC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_ADC_CR               (0x40038000U) /**< \brief (ADC) Control Register */
+#define REG_ADC_MR               (0x40038004U) /**< \brief (ADC) Mode Register */
+#define REG_ADC_SEQR1            (0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */
+#define REG_ADC_SEQR2            (0x4003800CU) /**< \brief (ADC) Channel Sequence Register 2 */
+#define REG_ADC_CHER             (0x40038010U) /**< \brief (ADC) Channel Enable Register */
+#define REG_ADC_CHDR             (0x40038014U) /**< \brief (ADC) Channel Disable Register */
+#define REG_ADC_CHSR             (0x40038018U) /**< \brief (ADC) Channel Status Register */
+#define REG_ADC_LCDR             (0x40038020U) /**< \brief (ADC) Last Converted Data Register */
+#define REG_ADC_IER              (0x40038024U) /**< \brief (ADC) Interrupt Enable Register */
+#define REG_ADC_IDR              (0x40038028U) /**< \brief (ADC) Interrupt Disable Register */
+#define REG_ADC_IMR              (0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */
+#define REG_ADC_ISR              (0x40038030U) /**< \brief (ADC) Interrupt Status Register */
+#define REG_ADC_OVER             (0x4003803CU) /**< \brief (ADC) Overrun Status Register */
+#define REG_ADC_EMR              (0x40038040U) /**< \brief (ADC) Extended Mode Register */
+#define REG_ADC_CWR              (0x40038044U) /**< \brief (ADC) Compare Window Register */
+#define REG_ADC_CGR              (0x40038048U) /**< \brief (ADC) Channel Gain Register */
+#define REG_ADC_COR              (0x4003804CU) /**< \brief (ADC) Channel Offset Register */
+#define REG_ADC_CDR              (0x40038050U) /**< \brief (ADC) Channel Data Register */
+#define REG_ADC_ACR              (0x40038094U) /**< \brief (ADC) Analog Control Register */
+#define REG_ADC_WPMR             (0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */
+#define REG_ADC_WPSR             (0x400380E8U) /**< \brief (ADC) Write Protect Status Register */
+#define REG_ADC_RPR              (0x40038100U) /**< \brief (ADC) Receive Pointer Register */
+#define REG_ADC_RCR              (0x40038104U) /**< \brief (ADC) Receive Counter Register */
+#define REG_ADC_TPR              (0x40038108U) /**< \brief (ADC) Transmit Pointer Register */
+#define REG_ADC_TCR              (0x4003810CU) /**< \brief (ADC) Transmit Counter Register */
+#define REG_ADC_RNPR             (0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */
+#define REG_ADC_RNCR             (0x40038114U) /**< \brief (ADC) Receive Next Counter Register */
+#define REG_ADC_TNPR             (0x40038118U) /**< \brief (ADC) Transmit Next Pointer Register */
+#define REG_ADC_TNCR             (0x4003811CU) /**< \brief (ADC) Transmit Next Counter Register */
+#define REG_ADC_PTCR             (0x40038120U) /**< \brief (ADC) Transfer Control Register */
+#define REG_ADC_PTSR             (0x40038124U) /**< \brief (ADC) Transfer Status Register */
+#else
+#define REG_ADC_CR      (*(WoReg*)0x40038000U) /**< \brief (ADC) Control Register */
+#define REG_ADC_MR      (*(RwReg*)0x40038004U) /**< \brief (ADC) Mode Register */
+#define REG_ADC_SEQR1   (*(RwReg*)0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */
+#define REG_ADC_SEQR2   (*(RwReg*)0x4003800CU) /**< \brief (ADC) Channel Sequence Register 2 */
+#define REG_ADC_CHER    (*(WoReg*)0x40038010U) /**< \brief (ADC) Channel Enable Register */
+#define REG_ADC_CHDR    (*(WoReg*)0x40038014U) /**< \brief (ADC) Channel Disable Register */
+#define REG_ADC_CHSR    (*(RoReg*)0x40038018U) /**< \brief (ADC) Channel Status Register */
+#define REG_ADC_LCDR    (*(RoReg*)0x40038020U) /**< \brief (ADC) Last Converted Data Register */
+#define REG_ADC_IER     (*(WoReg*)0x40038024U) /**< \brief (ADC) Interrupt Enable Register */
+#define REG_ADC_IDR     (*(WoReg*)0x40038028U) /**< \brief (ADC) Interrupt Disable Register */
+#define REG_ADC_IMR     (*(RoReg*)0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */
+#define REG_ADC_ISR     (*(RoReg*)0x40038030U) /**< \brief (ADC) Interrupt Status Register */
+#define REG_ADC_OVER    (*(RoReg*)0x4003803CU) /**< \brief (ADC) Overrun Status Register */
+#define REG_ADC_EMR     (*(RwReg*)0x40038040U) /**< \brief (ADC) Extended Mode Register */
+#define REG_ADC_CWR     (*(RwReg*)0x40038044U) /**< \brief (ADC) Compare Window Register */
+#define REG_ADC_CGR     (*(RwReg*)0x40038048U) /**< \brief (ADC) Channel Gain Register */
+#define REG_ADC_COR     (*(RwReg*)0x4003804CU) /**< \brief (ADC) Channel Offset Register */
+#define REG_ADC_CDR     (*(RoReg*)0x40038050U) /**< \brief (ADC) Channel Data Register */
+#define REG_ADC_ACR     (*(RwReg*)0x40038094U) /**< \brief (ADC) Analog Control Register */
+#define REG_ADC_WPMR    (*(RwReg*)0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */
+#define REG_ADC_WPSR    (*(RoReg*)0x400380E8U) /**< \brief (ADC) Write Protect Status Register */
+#define REG_ADC_RPR     (*(RwReg*)0x40038100U) /**< \brief (ADC) Receive Pointer Register */
+#define REG_ADC_RCR     (*(RwReg*)0x40038104U) /**< \brief (ADC) Receive Counter Register */
+#define REG_ADC_TPR     (*(RwReg*)0x40038108U) /**< \brief (ADC) Transmit Pointer Register */
+#define REG_ADC_TCR     (*(RwReg*)0x4003810CU) /**< \brief (ADC) Transmit Counter Register */
+#define REG_ADC_RNPR    (*(RwReg*)0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */
+#define REG_ADC_RNCR    (*(RwReg*)0x40038114U) /**< \brief (ADC) Receive Next Counter Register */
+#define REG_ADC_TNPR    (*(RwReg*)0x40038118U) /**< \brief (ADC) Transmit Next Pointer Register */
+#define REG_ADC_TNCR    (*(RwReg*)0x4003811CU) /**< \brief (ADC) Transmit Next Counter Register */
+#define REG_ADC_PTCR    (*(WoReg*)0x40038120U) /**< \brief (ADC) Transfer Control Register */
+#define REG_ADC_PTSR    (*(RoReg*)0x40038124U) /**< \brief (ADC) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_ADC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_chipid.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_chipid.h
new file mode 100644
index 000000000..1954f13e8
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_chipid.h
@@ -0,0 +1,42 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_CHIPID_INSTANCE_
+#define _SAM3S_CHIPID_INSTANCE_
+
+/* ========== Register definition for CHIPID peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_CHIPID_CIDR          (0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
+#define REG_CHIPID_EXID          (0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
+#else
+#define REG_CHIPID_CIDR (*(RoReg*)0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
+#define REG_CHIPID_EXID (*(RoReg*)0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_CHIPID_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_crccu.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_crccu.h
new file mode 100644
index 000000000..f374c1e20
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_crccu.h
@@ -0,0 +1,68 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_CRCCU_INSTANCE_
+#define _SAM3S_CRCCU_INSTANCE_
+
+/* ========== Register definition for CRCCU peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_CRCCU_DSCR             (0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */
+#define REG_CRCCU_DMA_EN           (0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */
+#define REG_CRCCU_DMA_DIS          (0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */
+#define REG_CRCCU_DMA_SR           (0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */
+#define REG_CRCCU_DMA_IER          (0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */
+#define REG_CRCCU_DMA_IDR          (0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */
+#define REG_CRCCU_DMA_IMR          (0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */
+#define REG_CRCCU_DMA_ISR          (0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */
+#define REG_CRCCU_CR               (0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */
+#define REG_CRCCU_MR               (0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */
+#define REG_CRCCU_SR               (0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */
+#define REG_CRCCU_IER              (0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */
+#define REG_CRCCU_IDR              (0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */
+#define REG_CRCCU_IMR              (0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */
+#define REG_CRCCU_ISR              (0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */
+#else
+#define REG_CRCCU_DSCR    (*(RwReg*)0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */
+#define REG_CRCCU_DMA_EN  (*(WoReg*)0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */
+#define REG_CRCCU_DMA_DIS (*(WoReg*)0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */
+#define REG_CRCCU_DMA_SR  (*(RoReg*)0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */
+#define REG_CRCCU_DMA_IER (*(WoReg*)0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */
+#define REG_CRCCU_DMA_IDR (*(WoReg*)0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */
+#define REG_CRCCU_DMA_IMR (*(RoReg*)0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */
+#define REG_CRCCU_DMA_ISR (*(RoReg*)0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */
+#define REG_CRCCU_CR      (*(WoReg*)0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */
+#define REG_CRCCU_MR      (*(RwReg*)0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */
+#define REG_CRCCU_SR      (*(RoReg*)0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */
+#define REG_CRCCU_IER     (*(WoReg*)0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */
+#define REG_CRCCU_IDR     (*(WoReg*)0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */
+#define REG_CRCCU_IMR     (*(RoReg*)0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */
+#define REG_CRCCU_ISR     (*(RoReg*)0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_CRCCU_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_dacc.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_dacc.h
new file mode 100644
index 000000000..dc5581b94
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_dacc.h
@@ -0,0 +1,84 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_DACC_INSTANCE_
+#define _SAM3S_DACC_INSTANCE_
+
+/* ========== Register definition for DACC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_DACC_CR            (0x4003C000U) /**< \brief (DACC) Control Register */
+#define REG_DACC_MR            (0x4003C004U) /**< \brief (DACC) Mode Register */
+#define REG_DACC_CHER          (0x4003C010U) /**< \brief (DACC) Channel Enable Register */
+#define REG_DACC_CHDR          (0x4003C014U) /**< \brief (DACC) Channel Disable Register */
+#define REG_DACC_CHSR          (0x4003C018U) /**< \brief (DACC) Channel Status Register */
+#define REG_DACC_CDR           (0x4003C020U) /**< \brief (DACC) Conversion Data Register */
+#define REG_DACC_IER           (0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */
+#define REG_DACC_IDR           (0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */
+#define REG_DACC_IMR           (0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */
+#define REG_DACC_ISR           (0x4003C030U) /**< \brief (DACC) Interrupt Status Register */
+#define REG_DACC_ACR           (0x4003C094U) /**< \brief (DACC) Analog Current Register */
+#define REG_DACC_WPMR          (0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */
+#define REG_DACC_WPSR          (0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */
+#define REG_DACC_RPR           (0x4003C100U) /**< \brief (DACC) Receive Pointer Register */
+#define REG_DACC_RCR           (0x4003C104U) /**< \brief (DACC) Receive Counter Register */
+#define REG_DACC_TPR           (0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */
+#define REG_DACC_TCR           (0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */
+#define REG_DACC_RNPR          (0x4003C110U) /**< \brief (DACC) Receive Next Pointer Register */
+#define REG_DACC_RNCR          (0x4003C114U) /**< \brief (DACC) Receive Next Counter Register */
+#define REG_DACC_TNPR          (0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */
+#define REG_DACC_TNCR          (0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */
+#define REG_DACC_PTCR          (0x4003C120U) /**< \brief (DACC) Transfer Control Register */
+#define REG_DACC_PTSR          (0x4003C124U) /**< \brief (DACC) Transfer Status Register */
+#else
+#define REG_DACC_CR   (*(WoReg*)0x4003C000U) /**< \brief (DACC) Control Register */
+#define REG_DACC_MR   (*(RwReg*)0x4003C004U) /**< \brief (DACC) Mode Register */
+#define REG_DACC_CHER (*(WoReg*)0x4003C010U) /**< \brief (DACC) Channel Enable Register */
+#define REG_DACC_CHDR (*(WoReg*)0x4003C014U) /**< \brief (DACC) Channel Disable Register */
+#define REG_DACC_CHSR (*(RoReg*)0x4003C018U) /**< \brief (DACC) Channel Status Register */
+#define REG_DACC_CDR  (*(WoReg*)0x4003C020U) /**< \brief (DACC) Conversion Data Register */
+#define REG_DACC_IER  (*(WoReg*)0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */
+#define REG_DACC_IDR  (*(WoReg*)0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */
+#define REG_DACC_IMR  (*(RoReg*)0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */
+#define REG_DACC_ISR  (*(RoReg*)0x4003C030U) /**< \brief (DACC) Interrupt Status Register */
+#define REG_DACC_ACR  (*(RwReg*)0x4003C094U) /**< \brief (DACC) Analog Current Register */
+#define REG_DACC_WPMR (*(RwReg*)0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */
+#define REG_DACC_WPSR (*(RoReg*)0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */
+#define REG_DACC_RPR  (*(RwReg*)0x4003C100U) /**< \brief (DACC) Receive Pointer Register */
+#define REG_DACC_RCR  (*(RwReg*)0x4003C104U) /**< \brief (DACC) Receive Counter Register */
+#define REG_DACC_TPR  (*(RwReg*)0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */
+#define REG_DACC_TCR  (*(RwReg*)0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */
+#define REG_DACC_RNPR (*(RwReg*)0x4003C110U) /**< \brief (DACC) Receive Next Pointer Register */
+#define REG_DACC_RNCR (*(RwReg*)0x4003C114U) /**< \brief (DACC) Receive Next Counter Register */
+#define REG_DACC_TNPR (*(RwReg*)0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */
+#define REG_DACC_TNCR (*(RwReg*)0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */
+#define REG_DACC_PTCR (*(WoReg*)0x4003C120U) /**< \brief (DACC) Transfer Control Register */
+#define REG_DACC_PTSR (*(RoReg*)0x4003C124U) /**< \brief (DACC) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_DACC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_efc.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_efc.h
new file mode 100644
index 000000000..1348be6fe
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_efc.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_EFC_INSTANCE_
+#define _SAM3S_EFC_INSTANCE_
+
+/* ========== Register definition for EFC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_EFC_FMR           (0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */
+#define REG_EFC_FCR           (0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */
+#define REG_EFC_FSR           (0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */
+#define REG_EFC_FRR           (0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */
+#else
+#define REG_EFC_FMR  (*(RwReg*)0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */
+#define REG_EFC_FCR  (*(WoReg*)0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */
+#define REG_EFC_FSR  (*(RoReg*)0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */
+#define REG_EFC_FRR  (*(RoReg*)0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_EFC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_gpbr.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_gpbr.h
new file mode 100644
index 000000000..7f3aba1f5
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_gpbr.h
@@ -0,0 +1,40 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_GPBR_INSTANCE_
+#define _SAM3S_GPBR_INSTANCE_
+
+/* ========== Register definition for GPBR peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_GPBR_GPBR            (0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */
+#else
+#define REG_GPBR_GPBR   (*(RwReg*)0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_GPBR_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_hsmci.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_hsmci.h
new file mode 100644
index 000000000..b07b43c59
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_hsmci.h
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_HSMCI_INSTANCE_
+#define _SAM3S_HSMCI_INSTANCE_
+
+/* ========== Register definition for HSMCI peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_HSMCI_CR                 (0x40000000U) /**< \brief (HSMCI) Control Register */
+#define REG_HSMCI_MR                 (0x40000004U) /**< \brief (HSMCI) Mode Register */
+#define REG_HSMCI_DTOR               (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
+#define REG_HSMCI_SDCR               (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
+#define REG_HSMCI_ARGR               (0x40000010U) /**< \brief (HSMCI) Argument Register */
+#define REG_HSMCI_CMDR               (0x40000014U) /**< \brief (HSMCI) Command Register */
+#define REG_HSMCI_BLKR               (0x40000018U) /**< \brief (HSMCI) Block Register */
+#define REG_HSMCI_CSTOR              (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
+#define REG_HSMCI_RSPR               (0x40000020U) /**< \brief (HSMCI) Response Register */
+#define REG_HSMCI_RDR                (0x40000030U) /**< \brief (HSMCI) Receive Data Register */
+#define REG_HSMCI_TDR                (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
+#define REG_HSMCI_SR                 (0x40000040U) /**< \brief (HSMCI) Status Register */
+#define REG_HSMCI_IER                (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
+#define REG_HSMCI_IDR                (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
+#define REG_HSMCI_IMR                (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
+#define REG_HSMCI_CFG                (0x40000054U) /**< \brief (HSMCI) Configuration Register */
+#define REG_HSMCI_WPMR               (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
+#define REG_HSMCI_WPSR               (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
+#define REG_HSMCI_RPR                (0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */
+#define REG_HSMCI_RCR                (0x40000104U) /**< \brief (HSMCI) Receive Counter Register */
+#define REG_HSMCI_TPR                (0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */
+#define REG_HSMCI_TCR                (0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */
+#define REG_HSMCI_RNPR               (0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */
+#define REG_HSMCI_RNCR               (0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */
+#define REG_HSMCI_TNPR               (0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */
+#define REG_HSMCI_TNCR               (0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */
+#define REG_HSMCI_PTCR               (0x40000120U) /**< \brief (HSMCI) Transfer Control Register */
+#define REG_HSMCI_PTSR               (0x40000124U) /**< \brief (HSMCI) Transfer Status Register */
+#define REG_HSMCI_FIFO               (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
+#else
+#define REG_HSMCI_CR        (*(WoReg*)0x40000000U) /**< \brief (HSMCI) Control Register */
+#define REG_HSMCI_MR        (*(RwReg*)0x40000004U) /**< \brief (HSMCI) Mode Register */
+#define REG_HSMCI_DTOR      (*(RwReg*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
+#define REG_HSMCI_SDCR      (*(RwReg*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
+#define REG_HSMCI_ARGR      (*(RwReg*)0x40000010U) /**< \brief (HSMCI) Argument Register */
+#define REG_HSMCI_CMDR      (*(WoReg*)0x40000014U) /**< \brief (HSMCI) Command Register */
+#define REG_HSMCI_BLKR      (*(RwReg*)0x40000018U) /**< \brief (HSMCI) Block Register */
+#define REG_HSMCI_CSTOR     (*(RwReg*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
+#define REG_HSMCI_RSPR      (*(RoReg*)0x40000020U) /**< \brief (HSMCI) Response Register */
+#define REG_HSMCI_RDR       (*(RoReg*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */
+#define REG_HSMCI_TDR       (*(WoReg*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
+#define REG_HSMCI_SR        (*(RoReg*)0x40000040U) /**< \brief (HSMCI) Status Register */
+#define REG_HSMCI_IER       (*(WoReg*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
+#define REG_HSMCI_IDR       (*(WoReg*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
+#define REG_HSMCI_IMR       (*(RoReg*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
+#define REG_HSMCI_CFG       (*(RwReg*)0x40000054U) /**< \brief (HSMCI) Configuration Register */
+#define REG_HSMCI_WPMR      (*(RwReg*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
+#define REG_HSMCI_WPSR      (*(RoReg*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
+#define REG_HSMCI_RPR       (*(RwReg*)0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */
+#define REG_HSMCI_RCR       (*(RwReg*)0x40000104U) /**< \brief (HSMCI) Receive Counter Register */
+#define REG_HSMCI_TPR       (*(RwReg*)0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */
+#define REG_HSMCI_TCR       (*(RwReg*)0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */
+#define REG_HSMCI_RNPR      (*(RwReg*)0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */
+#define REG_HSMCI_RNCR      (*(RwReg*)0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */
+#define REG_HSMCI_TNPR      (*(RwReg*)0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */
+#define REG_HSMCI_TNCR      (*(RwReg*)0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */
+#define REG_HSMCI_PTCR      (*(WoReg*)0x40000120U) /**< \brief (HSMCI) Transfer Control Register */
+#define REG_HSMCI_PTSR      (*(RoReg*)0x40000124U) /**< \brief (HSMCI) Transfer Status Register */
+#define REG_HSMCI_FIFO      (*(RwReg*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_HSMCI_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_matrix.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_matrix.h
new file mode 100644
index 000000000..c5c34f77e
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_matrix.h
@@ -0,0 +1,60 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_MATRIX_INSTANCE_
+#define _SAM3S_MATRIX_INSTANCE_
+
+/* ========== Register definition for MATRIX peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_MATRIX_MCFG             (0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
+#define REG_MATRIX_SCFG             (0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
+#define REG_MATRIX_PRAS0            (0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
+#define REG_MATRIX_PRAS1            (0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
+#define REG_MATRIX_PRAS2            (0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
+#define REG_MATRIX_PRAS3            (0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
+#define REG_MATRIX_PRAS4            (0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
+#define REG_CCFG_SYSIO              (0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */
+#define REG_CCFG_SMCNFCS            (0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */
+#define REG_MATRIX_WPMR             (0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
+#define REG_MATRIX_WPSR             (0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
+#else
+#define REG_MATRIX_MCFG    (*(RwReg*)0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
+#define REG_MATRIX_SCFG    (*(RwReg*)0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
+#define REG_MATRIX_PRAS0   (*(RwReg*)0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
+#define REG_MATRIX_PRAS1   (*(RwReg*)0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
+#define REG_MATRIX_PRAS2   (*(RwReg*)0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
+#define REG_MATRIX_PRAS3   (*(RwReg*)0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
+#define REG_MATRIX_PRAS4   (*(RwReg*)0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
+#define REG_CCFG_SYSIO     (*(RwReg*)0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */
+#define REG_CCFG_SMCNFCS   (*(RwReg*)0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */
+#define REG_MATRIX_WPMR    (*(RwReg*)0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
+#define REG_MATRIX_WPSR    (*(RoReg*)0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_MATRIX_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_pioa.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_pioa.h
new file mode 100644
index 000000000..19c23f2d7
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_pioa.h
@@ -0,0 +1,164 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_PIOA_INSTANCE_
+#define _SAM3S_PIOA_INSTANCE_
+
+/* ========== Register definition for PIOA peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PIOA_PER                (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
+#define REG_PIOA_PDR                (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
+#define REG_PIOA_PSR                (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
+#define REG_PIOA_OER                (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
+#define REG_PIOA_ODR                (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
+#define REG_PIOA_OSR                (0x400E0E18U) /**< \brief (PIOA) Output Status Register */
+#define REG_PIOA_IFER               (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
+#define REG_PIOA_IFDR               (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
+#define REG_PIOA_IFSR               (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
+#define REG_PIOA_SODR               (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
+#define REG_PIOA_CODR               (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
+#define REG_PIOA_ODSR               (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
+#define REG_PIOA_PDSR               (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
+#define REG_PIOA_IER                (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
+#define REG_PIOA_IDR                (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
+#define REG_PIOA_IMR                (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
+#define REG_PIOA_ISR                (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
+#define REG_PIOA_MDER               (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
+#define REG_PIOA_MDDR               (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
+#define REG_PIOA_MDSR               (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
+#define REG_PIOA_PUDR               (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
+#define REG_PIOA_PUER               (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
+#define REG_PIOA_PUSR               (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
+#define REG_PIOA_ABCDSR             (0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
+#define REG_PIOA_IFSCDR             (0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
+#define REG_PIOA_IFSCER             (0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
+#define REG_PIOA_IFSCSR             (0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
+#define REG_PIOA_SCDR               (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
+#define REG_PIOA_PPDDR              (0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
+#define REG_PIOA_PPDER              (0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
+#define REG_PIOA_PPDSR              (0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
+#define REG_PIOA_OWER               (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
+#define REG_PIOA_OWDR               (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
+#define REG_PIOA_OWSR               (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
+#define REG_PIOA_AIMER              (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
+#define REG_PIOA_AIMDR              (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
+#define REG_PIOA_AIMMR              (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
+#define REG_PIOA_ESR                (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
+#define REG_PIOA_LSR                (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
+#define REG_PIOA_ELSR               (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
+#define REG_PIOA_FELLSR             (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
+#define REG_PIOA_REHLSR             (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
+#define REG_PIOA_FRLHSR             (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
+#define REG_PIOA_LOCKSR             (0x400E0EE0U) /**< \brief (PIOA) Lock Status */
+#define REG_PIOA_WPMR               (0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
+#define REG_PIOA_WPSR               (0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
+#define REG_PIOA_SCHMITT            (0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
+#define REG_PIOA_PCMR               (0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */
+#define REG_PIOA_PCIER              (0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */
+#define REG_PIOA_PCIDR              (0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */
+#define REG_PIOA_PCIMR              (0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */
+#define REG_PIOA_PCISR              (0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */
+#define REG_PIOA_PCRHR              (0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */
+#define REG_PIOA_RPR                (0x400E0F68U) /**< \brief (PIOA) Receive Pointer Register */
+#define REG_PIOA_RCR                (0x400E0F6CU) /**< \brief (PIOA) Receive Counter Register */
+#define REG_PIOA_TPR                (0x400E0F70U) /**< \brief (PIOA) Transmit Pointer Register */
+#define REG_PIOA_TCR                (0x400E0F74U) /**< \brief (PIOA) Transmit Counter Register */
+#define REG_PIOA_RNPR               (0x400E0F78U) /**< \brief (PIOA) Receive Next Pointer Register */
+#define REG_PIOA_RNCR               (0x400E0F7CU) /**< \brief (PIOA) Receive Next Counter Register */
+#define REG_PIOA_TNPR               (0x400E0F80U) /**< \brief (PIOA) Transmit Next Pointer Register */
+#define REG_PIOA_TNCR               (0x400E0F84U) /**< \brief (PIOA) Transmit Next Counter Register */
+#define REG_PIOA_PTCR               (0x400E0F88U) /**< \brief (PIOA) Transfer Control Register */
+#define REG_PIOA_PTSR               (0x400E0F8CU) /**< \brief (PIOA) Transfer Status Register */
+#else
+#define REG_PIOA_PER       (*(WoReg*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
+#define REG_PIOA_PDR       (*(WoReg*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
+#define REG_PIOA_PSR       (*(RoReg*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
+#define REG_PIOA_OER       (*(WoReg*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
+#define REG_PIOA_ODR       (*(WoReg*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
+#define REG_PIOA_OSR       (*(RoReg*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */
+#define REG_PIOA_IFER      (*(WoReg*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
+#define REG_PIOA_IFDR      (*(WoReg*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
+#define REG_PIOA_IFSR      (*(RoReg*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
+#define REG_PIOA_SODR      (*(WoReg*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
+#define REG_PIOA_CODR      (*(WoReg*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
+#define REG_PIOA_ODSR      (*(RwReg*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
+#define REG_PIOA_PDSR      (*(RoReg*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
+#define REG_PIOA_IER       (*(WoReg*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
+#define REG_PIOA_IDR       (*(WoReg*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
+#define REG_PIOA_IMR       (*(RoReg*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
+#define REG_PIOA_ISR       (*(RoReg*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
+#define REG_PIOA_MDER      (*(WoReg*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
+#define REG_PIOA_MDDR      (*(WoReg*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
+#define REG_PIOA_MDSR      (*(RoReg*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
+#define REG_PIOA_PUDR      (*(WoReg*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
+#define REG_PIOA_PUER      (*(WoReg*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
+#define REG_PIOA_PUSR      (*(RoReg*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
+#define REG_PIOA_ABCDSR    (*(RwReg*)0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
+#define REG_PIOA_IFSCDR    (*(WoReg*)0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
+#define REG_PIOA_IFSCER    (*(WoReg*)0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
+#define REG_PIOA_IFSCSR    (*(RoReg*)0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
+#define REG_PIOA_SCDR      (*(RwReg*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
+#define REG_PIOA_PPDDR     (*(WoReg*)0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
+#define REG_PIOA_PPDER     (*(WoReg*)0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
+#define REG_PIOA_PPDSR     (*(RoReg*)0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
+#define REG_PIOA_OWER      (*(WoReg*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
+#define REG_PIOA_OWDR      (*(WoReg*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
+#define REG_PIOA_OWSR      (*(RoReg*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
+#define REG_PIOA_AIMER     (*(WoReg*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
+#define REG_PIOA_AIMDR     (*(WoReg*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
+#define REG_PIOA_AIMMR     (*(RoReg*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
+#define REG_PIOA_ESR       (*(WoReg*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
+#define REG_PIOA_LSR       (*(WoReg*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
+#define REG_PIOA_ELSR      (*(RoReg*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
+#define REG_PIOA_FELLSR    (*(WoReg*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
+#define REG_PIOA_REHLSR    (*(WoReg*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
+#define REG_PIOA_FRLHSR    (*(RoReg*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
+#define REG_PIOA_LOCKSR    (*(RoReg*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */
+#define REG_PIOA_WPMR      (*(RwReg*)0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
+#define REG_PIOA_WPSR      (*(RoReg*)0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
+#define REG_PIOA_SCHMITT   (*(RwReg*)0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
+#define REG_PIOA_PCMR      (*(RwReg*)0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */
+#define REG_PIOA_PCIER     (*(WoReg*)0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */
+#define REG_PIOA_PCIDR     (*(WoReg*)0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */
+#define REG_PIOA_PCIMR     (*(RoReg*)0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */
+#define REG_PIOA_PCISR     (*(RoReg*)0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */
+#define REG_PIOA_PCRHR     (*(RoReg*)0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */
+#define REG_PIOA_RPR       (*(RwReg*)0x400E0F68U) /**< \brief (PIOA) Receive Pointer Register */
+#define REG_PIOA_RCR       (*(RwReg*)0x400E0F6CU) /**< \brief (PIOA) Receive Counter Register */
+#define REG_PIOA_TPR       (*(RwReg*)0x400E0F70U) /**< \brief (PIOA) Transmit Pointer Register */
+#define REG_PIOA_TCR       (*(RwReg*)0x400E0F74U) /**< \brief (PIOA) Transmit Counter Register */
+#define REG_PIOA_RNPR      (*(RwReg*)0x400E0F78U) /**< \brief (PIOA) Receive Next Pointer Register */
+#define REG_PIOA_RNCR      (*(RwReg*)0x400E0F7CU) /**< \brief (PIOA) Receive Next Counter Register */
+#define REG_PIOA_TNPR      (*(RwReg*)0x400E0F80U) /**< \brief (PIOA) Transmit Next Pointer Register */
+#define REG_PIOA_TNCR      (*(RwReg*)0x400E0F84U) /**< \brief (PIOA) Transmit Next Counter Register */
+#define REG_PIOA_PTCR      (*(WoReg*)0x400E0F88U) /**< \brief (PIOA) Transfer Control Register */
+#define REG_PIOA_PTSR      (*(RoReg*)0x400E0F8CU) /**< \brief (PIOA) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_PIOA_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_piob.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_piob.h
new file mode 100644
index 000000000..4858f39d6
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_piob.h
@@ -0,0 +1,144 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_PIOB_INSTANCE_
+#define _SAM3S_PIOB_INSTANCE_
+
+/* ========== Register definition for PIOB peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PIOB_PER                (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
+#define REG_PIOB_PDR                (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
+#define REG_PIOB_PSR                (0x400E1008U) /**< \brief (PIOB) PIO Status Register */
+#define REG_PIOB_OER                (0x400E1010U) /**< \brief (PIOB) Output Enable Register */
+#define REG_PIOB_ODR                (0x400E1014U) /**< \brief (PIOB) Output Disable Register */
+#define REG_PIOB_OSR                (0x400E1018U) /**< \brief (PIOB) Output Status Register */
+#define REG_PIOB_IFER               (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
+#define REG_PIOB_IFDR               (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
+#define REG_PIOB_IFSR               (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
+#define REG_PIOB_SODR               (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
+#define REG_PIOB_CODR               (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
+#define REG_PIOB_ODSR               (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
+#define REG_PIOB_PDSR               (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
+#define REG_PIOB_IER                (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
+#define REG_PIOB_IDR                (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
+#define REG_PIOB_IMR                (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
+#define REG_PIOB_ISR                (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
+#define REG_PIOB_MDER               (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
+#define REG_PIOB_MDDR               (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
+#define REG_PIOB_MDSR               (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
+#define REG_PIOB_PUDR               (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
+#define REG_PIOB_PUER               (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
+#define REG_PIOB_PUSR               (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
+#define REG_PIOB_ABCDSR             (0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */
+#define REG_PIOB_IFSCDR             (0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
+#define REG_PIOB_IFSCER             (0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
+#define REG_PIOB_IFSCSR             (0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
+#define REG_PIOB_SCDR               (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
+#define REG_PIOB_PPDDR              (0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */
+#define REG_PIOB_PPDER              (0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */
+#define REG_PIOB_PPDSR              (0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */
+#define REG_PIOB_OWER               (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
+#define REG_PIOB_OWDR               (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
+#define REG_PIOB_OWSR               (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
+#define REG_PIOB_AIMER              (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
+#define REG_PIOB_AIMDR              (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
+#define REG_PIOB_AIMMR              (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
+#define REG_PIOB_ESR                (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
+#define REG_PIOB_LSR                (0x400E10C4U) /**< \brief (PIOB) Level Select Register */
+#define REG_PIOB_ELSR               (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
+#define REG_PIOB_FELLSR             (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
+#define REG_PIOB_REHLSR             (0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
+#define REG_PIOB_FRLHSR             (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
+#define REG_PIOB_LOCKSR             (0x400E10E0U) /**< \brief (PIOB) Lock Status */
+#define REG_PIOB_WPMR               (0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
+#define REG_PIOB_WPSR               (0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
+#define REG_PIOB_SCHMITT            (0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */
+#define REG_PIOB_PCMR               (0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */
+#define REG_PIOB_PCIER              (0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */
+#define REG_PIOB_PCIDR              (0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */
+#define REG_PIOB_PCIMR              (0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */
+#define REG_PIOB_PCISR              (0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */
+#define REG_PIOB_PCRHR              (0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */
+#else
+#define REG_PIOB_PER       (*(WoReg*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
+#define REG_PIOB_PDR       (*(WoReg*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
+#define REG_PIOB_PSR       (*(RoReg*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */
+#define REG_PIOB_OER       (*(WoReg*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */
+#define REG_PIOB_ODR       (*(WoReg*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */
+#define REG_PIOB_OSR       (*(RoReg*)0x400E1018U) /**< \brief (PIOB) Output Status Register */
+#define REG_PIOB_IFER      (*(WoReg*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
+#define REG_PIOB_IFDR      (*(WoReg*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
+#define REG_PIOB_IFSR      (*(RoReg*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
+#define REG_PIOB_SODR      (*(WoReg*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
+#define REG_PIOB_CODR      (*(WoReg*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
+#define REG_PIOB_ODSR      (*(RwReg*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
+#define REG_PIOB_PDSR      (*(RoReg*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
+#define REG_PIOB_IER       (*(WoReg*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
+#define REG_PIOB_IDR       (*(WoReg*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
+#define REG_PIOB_IMR       (*(RoReg*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
+#define REG_PIOB_ISR       (*(RoReg*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
+#define REG_PIOB_MDER      (*(WoReg*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
+#define REG_PIOB_MDDR      (*(WoReg*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
+#define REG_PIOB_MDSR      (*(RoReg*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
+#define REG_PIOB_PUDR      (*(WoReg*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
+#define REG_PIOB_PUER      (*(WoReg*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
+#define REG_PIOB_PUSR      (*(RoReg*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
+#define REG_PIOB_ABCDSR    (*(RwReg*)0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */
+#define REG_PIOB_IFSCDR    (*(WoReg*)0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
+#define REG_PIOB_IFSCER    (*(WoReg*)0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
+#define REG_PIOB_IFSCSR    (*(RoReg*)0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
+#define REG_PIOB_SCDR      (*(RwReg*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
+#define REG_PIOB_PPDDR     (*(WoReg*)0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */
+#define REG_PIOB_PPDER     (*(WoReg*)0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */
+#define REG_PIOB_PPDSR     (*(RoReg*)0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */
+#define REG_PIOB_OWER      (*(WoReg*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
+#define REG_PIOB_OWDR      (*(WoReg*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
+#define REG_PIOB_OWSR      (*(RoReg*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
+#define REG_PIOB_AIMER     (*(WoReg*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
+#define REG_PIOB_AIMDR     (*(WoReg*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
+#define REG_PIOB_AIMMR     (*(RoReg*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
+#define REG_PIOB_ESR       (*(WoReg*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
+#define REG_PIOB_LSR       (*(WoReg*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */
+#define REG_PIOB_ELSR      (*(RoReg*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
+#define REG_PIOB_FELLSR    (*(WoReg*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
+#define REG_PIOB_REHLSR    (*(WoReg*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
+#define REG_PIOB_FRLHSR    (*(RoReg*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
+#define REG_PIOB_LOCKSR    (*(RoReg*)0x400E10E0U) /**< \brief (PIOB) Lock Status */
+#define REG_PIOB_WPMR      (*(RwReg*)0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
+#define REG_PIOB_WPSR      (*(RoReg*)0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
+#define REG_PIOB_SCHMITT   (*(RwReg*)0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */
+#define REG_PIOB_PCMR      (*(RwReg*)0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */
+#define REG_PIOB_PCIER     (*(WoReg*)0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */
+#define REG_PIOB_PCIDR     (*(WoReg*)0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */
+#define REG_PIOB_PCIMR     (*(RoReg*)0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */
+#define REG_PIOB_PCISR     (*(RoReg*)0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */
+#define REG_PIOB_PCRHR     (*(RoReg*)0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_PIOB_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_pioc.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_pioc.h
new file mode 100644
index 000000000..ebb15f158
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_pioc.h
@@ -0,0 +1,144 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_PIOC_INSTANCE_
+#define _SAM3S_PIOC_INSTANCE_
+
+/* ========== Register definition for PIOC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PIOC_PER                (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
+#define REG_PIOC_PDR                (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
+#define REG_PIOC_PSR                (0x400E1208U) /**< \brief (PIOC) PIO Status Register */
+#define REG_PIOC_OER                (0x400E1210U) /**< \brief (PIOC) Output Enable Register */
+#define REG_PIOC_ODR                (0x400E1214U) /**< \brief (PIOC) Output Disable Register */
+#define REG_PIOC_OSR                (0x400E1218U) /**< \brief (PIOC) Output Status Register */
+#define REG_PIOC_IFER               (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
+#define REG_PIOC_IFDR               (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
+#define REG_PIOC_IFSR               (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
+#define REG_PIOC_SODR               (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
+#define REG_PIOC_CODR               (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
+#define REG_PIOC_ODSR               (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
+#define REG_PIOC_PDSR               (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
+#define REG_PIOC_IER                (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
+#define REG_PIOC_IDR                (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
+#define REG_PIOC_IMR                (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
+#define REG_PIOC_ISR                (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
+#define REG_PIOC_MDER               (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
+#define REG_PIOC_MDDR               (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
+#define REG_PIOC_MDSR               (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
+#define REG_PIOC_PUDR               (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
+#define REG_PIOC_PUER               (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
+#define REG_PIOC_PUSR               (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
+#define REG_PIOC_ABCDSR             (0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */
+#define REG_PIOC_IFSCDR             (0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
+#define REG_PIOC_IFSCER             (0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
+#define REG_PIOC_IFSCSR             (0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
+#define REG_PIOC_SCDR               (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
+#define REG_PIOC_PPDDR              (0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */
+#define REG_PIOC_PPDER              (0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */
+#define REG_PIOC_PPDSR              (0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */
+#define REG_PIOC_OWER               (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
+#define REG_PIOC_OWDR               (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
+#define REG_PIOC_OWSR               (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
+#define REG_PIOC_AIMER              (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
+#define REG_PIOC_AIMDR              (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
+#define REG_PIOC_AIMMR              (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
+#define REG_PIOC_ESR                (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
+#define REG_PIOC_LSR                (0x400E12C4U) /**< \brief (PIOC) Level Select Register */
+#define REG_PIOC_ELSR               (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
+#define REG_PIOC_FELLSR             (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
+#define REG_PIOC_REHLSR             (0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
+#define REG_PIOC_FRLHSR             (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
+#define REG_PIOC_LOCKSR             (0x400E12E0U) /**< \brief (PIOC) Lock Status */
+#define REG_PIOC_WPMR               (0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
+#define REG_PIOC_WPSR               (0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
+#define REG_PIOC_SCHMITT            (0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */
+#define REG_PIOC_PCMR               (0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */
+#define REG_PIOC_PCIER              (0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */
+#define REG_PIOC_PCIDR              (0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */
+#define REG_PIOC_PCIMR              (0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */
+#define REG_PIOC_PCISR              (0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */
+#define REG_PIOC_PCRHR              (0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */
+#else
+#define REG_PIOC_PER       (*(WoReg*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
+#define REG_PIOC_PDR       (*(WoReg*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
+#define REG_PIOC_PSR       (*(RoReg*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */
+#define REG_PIOC_OER       (*(WoReg*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */
+#define REG_PIOC_ODR       (*(WoReg*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */
+#define REG_PIOC_OSR       (*(RoReg*)0x400E1218U) /**< \brief (PIOC) Output Status Register */
+#define REG_PIOC_IFER      (*(WoReg*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
+#define REG_PIOC_IFDR      (*(WoReg*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
+#define REG_PIOC_IFSR      (*(RoReg*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
+#define REG_PIOC_SODR      (*(WoReg*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
+#define REG_PIOC_CODR      (*(WoReg*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
+#define REG_PIOC_ODSR      (*(RwReg*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
+#define REG_PIOC_PDSR      (*(RoReg*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
+#define REG_PIOC_IER       (*(WoReg*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
+#define REG_PIOC_IDR       (*(WoReg*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
+#define REG_PIOC_IMR       (*(RoReg*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
+#define REG_PIOC_ISR       (*(RoReg*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
+#define REG_PIOC_MDER      (*(WoReg*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
+#define REG_PIOC_MDDR      (*(WoReg*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
+#define REG_PIOC_MDSR      (*(RoReg*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
+#define REG_PIOC_PUDR      (*(WoReg*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
+#define REG_PIOC_PUER      (*(WoReg*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
+#define REG_PIOC_PUSR      (*(RoReg*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
+#define REG_PIOC_ABCDSR    (*(RwReg*)0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */
+#define REG_PIOC_IFSCDR    (*(WoReg*)0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
+#define REG_PIOC_IFSCER    (*(WoReg*)0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
+#define REG_PIOC_IFSCSR    (*(RoReg*)0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
+#define REG_PIOC_SCDR      (*(RwReg*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
+#define REG_PIOC_PPDDR     (*(WoReg*)0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */
+#define REG_PIOC_PPDER     (*(WoReg*)0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */
+#define REG_PIOC_PPDSR     (*(RoReg*)0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */
+#define REG_PIOC_OWER      (*(WoReg*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
+#define REG_PIOC_OWDR      (*(WoReg*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
+#define REG_PIOC_OWSR      (*(RoReg*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
+#define REG_PIOC_AIMER     (*(WoReg*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
+#define REG_PIOC_AIMDR     (*(WoReg*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
+#define REG_PIOC_AIMMR     (*(RoReg*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
+#define REG_PIOC_ESR       (*(WoReg*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
+#define REG_PIOC_LSR       (*(WoReg*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */
+#define REG_PIOC_ELSR      (*(RoReg*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
+#define REG_PIOC_FELLSR    (*(WoReg*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
+#define REG_PIOC_REHLSR    (*(WoReg*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
+#define REG_PIOC_FRLHSR    (*(RoReg*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
+#define REG_PIOC_LOCKSR    (*(RoReg*)0x400E12E0U) /**< \brief (PIOC) Lock Status */
+#define REG_PIOC_WPMR      (*(RwReg*)0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
+#define REG_PIOC_WPSR      (*(RoReg*)0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
+#define REG_PIOC_SCHMITT   (*(RwReg*)0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */
+#define REG_PIOC_PCMR      (*(RwReg*)0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */
+#define REG_PIOC_PCIER     (*(WoReg*)0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */
+#define REG_PIOC_PCIDR     (*(WoReg*)0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */
+#define REG_PIOC_PCIMR     (*(RoReg*)0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */
+#define REG_PIOC_PCISR     (*(RoReg*)0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */
+#define REG_PIOC_PCRHR     (*(RoReg*)0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_PIOC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_pmc.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_pmc.h
new file mode 100644
index 000000000..7646f73c9
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_pmc.h
@@ -0,0 +1,90 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_PMC_INSTANCE_
+#define _SAM3S_PMC_INSTANCE_
+
+/* ========== Register definition for PMC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PMC_SCER            (0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
+#define REG_PMC_SCDR            (0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
+#define REG_PMC_SCSR            (0x400E0408U) /**< \brief (PMC) System Clock Status Register */
+#define REG_PMC_PCER0           (0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
+#define REG_PMC_PCDR0           (0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
+#define REG_PMC_PCSR0           (0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
+#define REG_CKGR_MOR            (0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
+#define REG_CKGR_MCFR           (0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
+#define REG_CKGR_PLLAR          (0x400E0428U) /**< \brief (PMC) PLLA Register */
+#define REG_CKGR_PLLBR          (0x400E042CU) /**< \brief (PMC) PLLB Register */
+#define REG_PMC_MCKR            (0x400E0430U) /**< \brief (PMC) Master Clock Register */
+#define REG_PMC_USB             (0x400E0438U) /**< \brief (PMC) USB Clock Register */
+#define REG_PMC_PCK             (0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
+#define REG_PMC_IER             (0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
+#define REG_PMC_IDR             (0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
+#define REG_PMC_SR              (0x400E0468U) /**< \brief (PMC) Status Register */
+#define REG_PMC_IMR             (0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
+#define REG_PMC_FSMR            (0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
+#define REG_PMC_FSPR            (0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
+#define REG_PMC_FOCR            (0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
+#define REG_PMC_WPMR            (0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
+#define REG_PMC_WPSR            (0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
+#define REG_PMC_PCER1           (0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
+#define REG_PMC_PCDR1           (0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
+#define REG_PMC_PCSR1           (0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
+#define REG_PMC_OCR             (0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */
+#else
+#define REG_PMC_SCER   (*(WoReg*)0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
+#define REG_PMC_SCDR   (*(WoReg*)0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
+#define REG_PMC_SCSR   (*(RoReg*)0x400E0408U) /**< \brief (PMC) System Clock Status Register */
+#define REG_PMC_PCER0  (*(WoReg*)0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
+#define REG_PMC_PCDR0  (*(WoReg*)0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
+#define REG_PMC_PCSR0  (*(RoReg*)0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
+#define REG_CKGR_MOR   (*(RwReg*)0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
+#define REG_CKGR_MCFR  (*(RoReg*)0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
+#define REG_CKGR_PLLAR (*(RwReg*)0x400E0428U) /**< \brief (PMC) PLLA Register */
+#define REG_CKGR_PLLBR (*(RwReg*)0x400E042CU) /**< \brief (PMC) PLLB Register */
+#define REG_PMC_MCKR   (*(RwReg*)0x400E0430U) /**< \brief (PMC) Master Clock Register */
+#define REG_PMC_USB    (*(RwReg*)0x400E0438U) /**< \brief (PMC) USB Clock Register */
+#define REG_PMC_PCK    (*(RwReg*)0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
+#define REG_PMC_IER    (*(WoReg*)0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
+#define REG_PMC_IDR    (*(WoReg*)0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
+#define REG_PMC_SR     (*(RoReg*)0x400E0468U) /**< \brief (PMC) Status Register */
+#define REG_PMC_IMR    (*(RoReg*)0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
+#define REG_PMC_FSMR   (*(RwReg*)0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
+#define REG_PMC_FSPR   (*(RwReg*)0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
+#define REG_PMC_FOCR   (*(WoReg*)0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
+#define REG_PMC_WPMR   (*(RwReg*)0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
+#define REG_PMC_WPSR   (*(RoReg*)0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
+#define REG_PMC_PCER1  (*(WoReg*)0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
+#define REG_PMC_PCDR1  (*(WoReg*)0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
+#define REG_PMC_PCSR1  (*(RoReg*)0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
+#define REG_PMC_OCR    (*(RwReg*)0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_PMC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_pwm.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_pwm.h
new file mode 100644
index 000000000..729709457
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_pwm.h
@@ -0,0 +1,248 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_PWM_INSTANCE_
+#define _SAM3S_PWM_INSTANCE_
+
+/* ========== Register definition for PWM peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PWM_CLK               (0x40020000U) /**< \brief (PWM) PWM Clock Register */
+#define REG_PWM_ENA               (0x40020004U) /**< \brief (PWM) PWM Enable Register */
+#define REG_PWM_DIS               (0x40020008U) /**< \brief (PWM) PWM Disable Register */
+#define REG_PWM_SR                (0x4002000CU) /**< \brief (PWM) PWM Status Register */
+#define REG_PWM_IER1              (0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
+#define REG_PWM_IDR1              (0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
+#define REG_PWM_IMR1              (0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
+#define REG_PWM_ISR1              (0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
+#define REG_PWM_SCM               (0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
+#define REG_PWM_SCUC              (0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
+#define REG_PWM_SCUP              (0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
+#define REG_PWM_SCUPUPD           (0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
+#define REG_PWM_IER2              (0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
+#define REG_PWM_IDR2              (0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
+#define REG_PWM_IMR2              (0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
+#define REG_PWM_ISR2              (0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
+#define REG_PWM_OOV               (0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */
+#define REG_PWM_OS                (0x40020048U) /**< \brief (PWM) PWM Output Selection Register */
+#define REG_PWM_OSS               (0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */
+#define REG_PWM_OSC               (0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */
+#define REG_PWM_OSSUPD            (0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
+#define REG_PWM_OSCUPD            (0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
+#define REG_PWM_FMR               (0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */
+#define REG_PWM_FSR               (0x40020060U) /**< \brief (PWM) PWM Fault Status Register */
+#define REG_PWM_FCR               (0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */
+#define REG_PWM_FPV               (0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */
+#define REG_PWM_FPE               (0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */
+#define REG_PWM_ELMR              (0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
+#define REG_PWM_SMMR              (0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */
+#define REG_PWM_WPCR              (0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */
+#define REG_PWM_WPSR              (0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */
+#define REG_PWM_RPR               (0x40020100U) /**< \brief (PWM) Receive Pointer Register */
+#define REG_PWM_RCR               (0x40020104U) /**< \brief (PWM) Receive Counter Register */
+#define REG_PWM_TPR               (0x40020108U) /**< \brief (PWM) Transmit Pointer Register */
+#define REG_PWM_TCR               (0x4002010CU) /**< \brief (PWM) Transmit Counter Register */
+#define REG_PWM_RNPR              (0x40020110U) /**< \brief (PWM) Receive Next Pointer Register */
+#define REG_PWM_RNCR              (0x40020114U) /**< \brief (PWM) Receive Next Counter Register */
+#define REG_PWM_TNPR              (0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */
+#define REG_PWM_TNCR              (0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */
+#define REG_PWM_PTCR              (0x40020120U) /**< \brief (PWM) Transfer Control Register */
+#define REG_PWM_PTSR              (0x40020124U) /**< \brief (PWM) Transfer Status Register */
+#define REG_PWM_CMPV0             (0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
+#define REG_PWM_CMPVUPD0          (0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
+#define REG_PWM_CMPM0             (0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
+#define REG_PWM_CMPMUPD0          (0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
+#define REG_PWM_CMPV1             (0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
+#define REG_PWM_CMPVUPD1          (0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
+#define REG_PWM_CMPM1             (0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
+#define REG_PWM_CMPMUPD1          (0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
+#define REG_PWM_CMPV2             (0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
+#define REG_PWM_CMPVUPD2          (0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
+#define REG_PWM_CMPM2             (0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
+#define REG_PWM_CMPMUPD2          (0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
+#define REG_PWM_CMPV3             (0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
+#define REG_PWM_CMPVUPD3          (0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
+#define REG_PWM_CMPM3             (0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
+#define REG_PWM_CMPMUPD3          (0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
+#define REG_PWM_CMPV4             (0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
+#define REG_PWM_CMPVUPD4          (0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
+#define REG_PWM_CMPM4             (0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
+#define REG_PWM_CMPMUPD4          (0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
+#define REG_PWM_CMPV5             (0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
+#define REG_PWM_CMPVUPD5          (0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
+#define REG_PWM_CMPM5             (0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
+#define REG_PWM_CMPMUPD5          (0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
+#define REG_PWM_CMPV6             (0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
+#define REG_PWM_CMPVUPD6          (0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
+#define REG_PWM_CMPM6             (0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
+#define REG_PWM_CMPMUPD6          (0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
+#define REG_PWM_CMPV7             (0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
+#define REG_PWM_CMPVUPD7          (0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
+#define REG_PWM_CMPM7             (0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
+#define REG_PWM_CMPMUPD7          (0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
+#define REG_PWM_CMR0              (0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
+#define REG_PWM_CDTY0             (0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
+#define REG_PWM_CDTYUPD0          (0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
+#define REG_PWM_CPRD0             (0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
+#define REG_PWM_CPRDUPD0          (0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
+#define REG_PWM_CCNT0             (0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
+#define REG_PWM_DT0               (0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
+#define REG_PWM_DTUPD0            (0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
+#define REG_PWM_CMR1              (0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
+#define REG_PWM_CDTY1             (0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
+#define REG_PWM_CDTYUPD1          (0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
+#define REG_PWM_CPRD1             (0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
+#define REG_PWM_CPRDUPD1          (0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
+#define REG_PWM_CCNT1             (0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
+#define REG_PWM_DT1               (0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
+#define REG_PWM_DTUPD1            (0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
+#define REG_PWM_CMR2              (0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
+#define REG_PWM_CDTY2             (0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
+#define REG_PWM_CDTYUPD2          (0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
+#define REG_PWM_CPRD2             (0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
+#define REG_PWM_CPRDUPD2          (0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
+#define REG_PWM_CCNT2             (0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
+#define REG_PWM_DT2               (0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
+#define REG_PWM_DTUPD2            (0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
+#define REG_PWM_CMR3              (0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
+#define REG_PWM_CDTY3             (0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
+#define REG_PWM_CDTYUPD3          (0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
+#define REG_PWM_CPRD3             (0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
+#define REG_PWM_CPRDUPD3          (0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
+#define REG_PWM_CCNT3             (0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
+#define REG_PWM_DT3               (0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
+#define REG_PWM_DTUPD3            (0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
+#else
+#define REG_PWM_CLK      (*(RwReg*)0x40020000U) /**< \brief (PWM) PWM Clock Register */
+#define REG_PWM_ENA      (*(WoReg*)0x40020004U) /**< \brief (PWM) PWM Enable Register */
+#define REG_PWM_DIS      (*(WoReg*)0x40020008U) /**< \brief (PWM) PWM Disable Register */
+#define REG_PWM_SR       (*(RoReg*)0x4002000CU) /**< \brief (PWM) PWM Status Register */
+#define REG_PWM_IER1     (*(WoReg*)0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
+#define REG_PWM_IDR1     (*(WoReg*)0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
+#define REG_PWM_IMR1     (*(RoReg*)0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
+#define REG_PWM_ISR1     (*(RoReg*)0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
+#define REG_PWM_SCM      (*(RwReg*)0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
+#define REG_PWM_SCUC     (*(RwReg*)0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
+#define REG_PWM_SCUP     (*(RwReg*)0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
+#define REG_PWM_SCUPUPD  (*(WoReg*)0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
+#define REG_PWM_IER2     (*(WoReg*)0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
+#define REG_PWM_IDR2     (*(WoReg*)0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
+#define REG_PWM_IMR2     (*(RoReg*)0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
+#define REG_PWM_ISR2     (*(RoReg*)0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
+#define REG_PWM_OOV      (*(RwReg*)0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */
+#define REG_PWM_OS       (*(RwReg*)0x40020048U) /**< \brief (PWM) PWM Output Selection Register */
+#define REG_PWM_OSS      (*(WoReg*)0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */
+#define REG_PWM_OSC      (*(WoReg*)0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */
+#define REG_PWM_OSSUPD   (*(WoReg*)0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
+#define REG_PWM_OSCUPD   (*(WoReg*)0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
+#define REG_PWM_FMR      (*(RwReg*)0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */
+#define REG_PWM_FSR      (*(RoReg*)0x40020060U) /**< \brief (PWM) PWM Fault Status Register */
+#define REG_PWM_FCR      (*(WoReg*)0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */
+#define REG_PWM_FPV      (*(RwReg*)0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */
+#define REG_PWM_FPE      (*(RwReg*)0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */
+#define REG_PWM_ELMR     (*(RwReg*)0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
+#define REG_PWM_SMMR     (*(RwReg*)0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */
+#define REG_PWM_WPCR     (*(WoReg*)0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */
+#define REG_PWM_WPSR     (*(RoReg*)0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */
+#define REG_PWM_RPR      (*(RwReg*)0x40020100U) /**< \brief (PWM) Receive Pointer Register */
+#define REG_PWM_RCR      (*(RwReg*)0x40020104U) /**< \brief (PWM) Receive Counter Register */
+#define REG_PWM_TPR      (*(RwReg*)0x40020108U) /**< \brief (PWM) Transmit Pointer Register */
+#define REG_PWM_TCR      (*(RwReg*)0x4002010CU) /**< \brief (PWM) Transmit Counter Register */
+#define REG_PWM_RNPR     (*(RwReg*)0x40020110U) /**< \brief (PWM) Receive Next Pointer Register */
+#define REG_PWM_RNCR     (*(RwReg*)0x40020114U) /**< \brief (PWM) Receive Next Counter Register */
+#define REG_PWM_TNPR     (*(RwReg*)0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */
+#define REG_PWM_TNCR     (*(RwReg*)0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */
+#define REG_PWM_PTCR     (*(WoReg*)0x40020120U) /**< \brief (PWM) Transfer Control Register */
+#define REG_PWM_PTSR     (*(RoReg*)0x40020124U) /**< \brief (PWM) Transfer Status Register */
+#define REG_PWM_CMPV0    (*(RwReg*)0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
+#define REG_PWM_CMPVUPD0 (*(WoReg*)0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
+#define REG_PWM_CMPM0    (*(RwReg*)0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
+#define REG_PWM_CMPMUPD0 (*(WoReg*)0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
+#define REG_PWM_CMPV1    (*(RwReg*)0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
+#define REG_PWM_CMPVUPD1 (*(WoReg*)0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
+#define REG_PWM_CMPM1    (*(RwReg*)0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
+#define REG_PWM_CMPMUPD1 (*(WoReg*)0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
+#define REG_PWM_CMPV2    (*(RwReg*)0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
+#define REG_PWM_CMPVUPD2 (*(WoReg*)0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
+#define REG_PWM_CMPM2    (*(RwReg*)0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
+#define REG_PWM_CMPMUPD2 (*(WoReg*)0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
+#define REG_PWM_CMPV3    (*(RwReg*)0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
+#define REG_PWM_CMPVUPD3 (*(WoReg*)0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
+#define REG_PWM_CMPM3    (*(RwReg*)0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
+#define REG_PWM_CMPMUPD3 (*(WoReg*)0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
+#define REG_PWM_CMPV4    (*(RwReg*)0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
+#define REG_PWM_CMPVUPD4 (*(WoReg*)0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
+#define REG_PWM_CMPM4    (*(RwReg*)0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
+#define REG_PWM_CMPMUPD4 (*(WoReg*)0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
+#define REG_PWM_CMPV5    (*(RwReg*)0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
+#define REG_PWM_CMPVUPD5 (*(WoReg*)0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
+#define REG_PWM_CMPM5    (*(RwReg*)0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
+#define REG_PWM_CMPMUPD5 (*(WoReg*)0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
+#define REG_PWM_CMPV6    (*(RwReg*)0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
+#define REG_PWM_CMPVUPD6 (*(WoReg*)0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
+#define REG_PWM_CMPM6    (*(RwReg*)0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
+#define REG_PWM_CMPMUPD6 (*(WoReg*)0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
+#define REG_PWM_CMPV7    (*(RwReg*)0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
+#define REG_PWM_CMPVUPD7 (*(WoReg*)0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
+#define REG_PWM_CMPM7    (*(RwReg*)0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
+#define REG_PWM_CMPMUPD7 (*(WoReg*)0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
+#define REG_PWM_CMR0     (*(RwReg*)0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
+#define REG_PWM_CDTY0    (*(RwReg*)0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
+#define REG_PWM_CDTYUPD0 (*(WoReg*)0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
+#define REG_PWM_CPRD0    (*(RwReg*)0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
+#define REG_PWM_CPRDUPD0 (*(WoReg*)0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
+#define REG_PWM_CCNT0    (*(RoReg*)0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
+#define REG_PWM_DT0      (*(RwReg*)0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
+#define REG_PWM_DTUPD0   (*(WoReg*)0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
+#define REG_PWM_CMR1     (*(RwReg*)0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
+#define REG_PWM_CDTY1    (*(RwReg*)0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
+#define REG_PWM_CDTYUPD1 (*(WoReg*)0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
+#define REG_PWM_CPRD1    (*(RwReg*)0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
+#define REG_PWM_CPRDUPD1 (*(WoReg*)0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
+#define REG_PWM_CCNT1    (*(RoReg*)0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
+#define REG_PWM_DT1      (*(RwReg*)0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
+#define REG_PWM_DTUPD1   (*(WoReg*)0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
+#define REG_PWM_CMR2     (*(RwReg*)0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
+#define REG_PWM_CDTY2    (*(RwReg*)0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
+#define REG_PWM_CDTYUPD2 (*(WoReg*)0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
+#define REG_PWM_CPRD2    (*(RwReg*)0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
+#define REG_PWM_CPRDUPD2 (*(WoReg*)0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
+#define REG_PWM_CCNT2    (*(RoReg*)0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
+#define REG_PWM_DT2      (*(RwReg*)0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
+#define REG_PWM_DTUPD2   (*(WoReg*)0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
+#define REG_PWM_CMR3     (*(RwReg*)0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
+#define REG_PWM_CDTY3    (*(RwReg*)0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
+#define REG_PWM_CDTYUPD3 (*(WoReg*)0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
+#define REG_PWM_CPRD3    (*(RwReg*)0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
+#define REG_PWM_CPRDUPD3 (*(WoReg*)0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
+#define REG_PWM_CCNT3    (*(RoReg*)0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
+#define REG_PWM_DT3      (*(RwReg*)0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
+#define REG_PWM_DTUPD3   (*(WoReg*)0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_PWM_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_rstc.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_rstc.h
new file mode 100644
index 000000000..85bc90e8a
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_rstc.h
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_RSTC_INSTANCE_
+#define _SAM3S_RSTC_INSTANCE_
+
+/* ========== Register definition for RSTC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_RSTC_CR          (0x400E1400U) /**< \brief (RSTC) Control Register */
+#define REG_RSTC_SR          (0x400E1404U) /**< \brief (RSTC) Status Register */
+#define REG_RSTC_MR          (0x400E1408U) /**< \brief (RSTC) Mode Register */
+#else
+#define REG_RSTC_CR (*(WoReg*)0x400E1400U) /**< \brief (RSTC) Control Register */
+#define REG_RSTC_SR (*(RoReg*)0x400E1404U) /**< \brief (RSTC) Status Register */
+#define REG_RSTC_MR (*(RwReg*)0x400E1408U) /**< \brief (RSTC) Mode Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_RSTC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_rtc.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_rtc.h
new file mode 100644
index 000000000..abe37184f
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_rtc.h
@@ -0,0 +1,62 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_RTC_INSTANCE_
+#define _SAM3S_RTC_INSTANCE_
+
+/* ========== Register definition for RTC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_RTC_CR              (0x400E1460U) /**< \brief (RTC) Control Register */
+#define REG_RTC_MR              (0x400E1464U) /**< \brief (RTC) Mode Register */
+#define REG_RTC_TIMR            (0x400E1468U) /**< \brief (RTC) Time Register */
+#define REG_RTC_CALR            (0x400E146CU) /**< \brief (RTC) Calendar Register */
+#define REG_RTC_TIMALR          (0x400E1470U) /**< \brief (RTC) Time Alarm Register */
+#define REG_RTC_CALALR          (0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */
+#define REG_RTC_SR              (0x400E1478U) /**< \brief (RTC) Status Register */
+#define REG_RTC_SCCR            (0x400E147CU) /**< \brief (RTC) Status Clear Command Register */
+#define REG_RTC_IER             (0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */
+#define REG_RTC_IDR             (0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */
+#define REG_RTC_IMR             (0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */
+#define REG_RTC_VER             (0x400E148CU) /**< \brief (RTC) Valid Entry Register */
+#else
+#define REG_RTC_CR     (*(RwReg*)0x400E1460U) /**< \brief (RTC) Control Register */
+#define REG_RTC_MR     (*(RwReg*)0x400E1464U) /**< \brief (RTC) Mode Register */
+#define REG_RTC_TIMR   (*(RwReg*)0x400E1468U) /**< \brief (RTC) Time Register */
+#define REG_RTC_CALR   (*(RwReg*)0x400E146CU) /**< \brief (RTC) Calendar Register */
+#define REG_RTC_TIMALR (*(RwReg*)0x400E1470U) /**< \brief (RTC) Time Alarm Register */
+#define REG_RTC_CALALR (*(RwReg*)0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */
+#define REG_RTC_SR     (*(RoReg*)0x400E1478U) /**< \brief (RTC) Status Register */
+#define REG_RTC_SCCR   (*(WoReg*)0x400E147CU) /**< \brief (RTC) Status Clear Command Register */
+#define REG_RTC_IER    (*(WoReg*)0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */
+#define REG_RTC_IDR    (*(WoReg*)0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */
+#define REG_RTC_IMR    (*(RoReg*)0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */
+#define REG_RTC_VER    (*(RoReg*)0x400E148CU) /**< \brief (RTC) Valid Entry Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_RTC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_rtt.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_rtt.h
new file mode 100644
index 000000000..87917ca6c
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_rtt.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_RTT_INSTANCE_
+#define _SAM3S_RTT_INSTANCE_
+
+/* ========== Register definition for RTT peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_RTT_MR          (0x400E1430U) /**< \brief (RTT) Mode Register */
+#define REG_RTT_AR          (0x400E1434U) /**< \brief (RTT) Alarm Register */
+#define REG_RTT_VR          (0x400E1438U) /**< \brief (RTT) Value Register */
+#define REG_RTT_SR          (0x400E143CU) /**< \brief (RTT) Status Register */
+#else
+#define REG_RTT_MR (*(RwReg*)0x400E1430U) /**< \brief (RTT) Mode Register */
+#define REG_RTT_AR (*(RwReg*)0x400E1434U) /**< \brief (RTT) Alarm Register */
+#define REG_RTT_VR (*(RoReg*)0x400E1438U) /**< \brief (RTT) Value Register */
+#define REG_RTT_SR (*(RoReg*)0x400E143CU) /**< \brief (RTT) Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_RTT_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_smc.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_smc.h
new file mode 100644
index 000000000..af0bcbc02
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_smc.h
@@ -0,0 +1,88 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_SMC_INSTANCE_
+#define _SAM3S_SMC_INSTANCE_
+
+/* ========== Register definition for SMC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_SMC_SETUP0          (0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
+#define REG_SMC_PULSE0          (0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
+#define REG_SMC_CYCLE0          (0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
+#define REG_SMC_MODE0           (0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
+#define REG_SMC_SETUP1          (0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
+#define REG_SMC_PULSE1          (0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
+#define REG_SMC_CYCLE1          (0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
+#define REG_SMC_MODE1           (0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
+#define REG_SMC_SETUP2          (0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
+#define REG_SMC_PULSE2          (0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
+#define REG_SMC_CYCLE2          (0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
+#define REG_SMC_MODE2           (0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
+#define REG_SMC_SETUP3          (0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
+#define REG_SMC_PULSE3          (0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
+#define REG_SMC_CYCLE3          (0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
+#define REG_SMC_MODE3           (0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
+#define REG_SMC_SETUP4          (0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */
+#define REG_SMC_PULSE4          (0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */
+#define REG_SMC_CYCLE4          (0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */
+#define REG_SMC_MODE4           (0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */
+#define REG_SMC_OCMS            (0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */
+#define REG_SMC_KEY1            (0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */
+#define REG_SMC_KEY2            (0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */
+#define REG_SMC_WPMR            (0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */
+#define REG_SMC_WPSR            (0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */
+#else
+#define REG_SMC_SETUP0 (*(RwReg*)0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
+#define REG_SMC_PULSE0 (*(RwReg*)0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
+#define REG_SMC_CYCLE0 (*(RwReg*)0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
+#define REG_SMC_MODE0  (*(RwReg*)0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
+#define REG_SMC_SETUP1 (*(RwReg*)0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
+#define REG_SMC_PULSE1 (*(RwReg*)0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
+#define REG_SMC_CYCLE1 (*(RwReg*)0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
+#define REG_SMC_MODE1  (*(RwReg*)0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
+#define REG_SMC_SETUP2 (*(RwReg*)0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
+#define REG_SMC_PULSE2 (*(RwReg*)0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
+#define REG_SMC_CYCLE2 (*(RwReg*)0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
+#define REG_SMC_MODE2  (*(RwReg*)0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
+#define REG_SMC_SETUP3 (*(RwReg*)0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
+#define REG_SMC_PULSE3 (*(RwReg*)0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
+#define REG_SMC_CYCLE3 (*(RwReg*)0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
+#define REG_SMC_MODE3  (*(RwReg*)0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
+#define REG_SMC_SETUP4 (*(RwReg*)0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */
+#define REG_SMC_PULSE4 (*(RwReg*)0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */
+#define REG_SMC_CYCLE4 (*(RwReg*)0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */
+#define REG_SMC_MODE4  (*(RwReg*)0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */
+#define REG_SMC_OCMS   (*(RwReg*)0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */
+#define REG_SMC_KEY1   (*(WoReg*)0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */
+#define REG_SMC_KEY2   (*(WoReg*)0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */
+#define REG_SMC_WPMR   (*(RwReg*)0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */
+#define REG_SMC_WPSR   (*(RoReg*)0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_SMC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_spi.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_spi.h
new file mode 100644
index 000000000..ee59a26ee
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_spi.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_SPI_INSTANCE_
+#define _SAM3S_SPI_INSTANCE_
+
+/* ========== Register definition for SPI peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_SPI_CR              (0x40008000U) /**< \brief (SPI) Control Register */
+#define REG_SPI_MR              (0x40008004U) /**< \brief (SPI) Mode Register */
+#define REG_SPI_RDR             (0x40008008U) /**< \brief (SPI) Receive Data Register */
+#define REG_SPI_TDR             (0x4000800CU) /**< \brief (SPI) Transmit Data Register */
+#define REG_SPI_SR              (0x40008010U) /**< \brief (SPI) Status Register */
+#define REG_SPI_IER             (0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
+#define REG_SPI_IDR             (0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
+#define REG_SPI_IMR             (0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
+#define REG_SPI_CSR             (0x40008030U) /**< \brief (SPI) Chip Select Register */
+#define REG_SPI_WPMR            (0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
+#define REG_SPI_WPSR            (0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
+#define REG_SPI_RPR             (0x40008100U) /**< \brief (SPI) Receive Pointer Register */
+#define REG_SPI_RCR             (0x40008104U) /**< \brief (SPI) Receive Counter Register */
+#define REG_SPI_TPR             (0x40008108U) /**< \brief (SPI) Transmit Pointer Register */
+#define REG_SPI_TCR             (0x4000810CU) /**< \brief (SPI) Transmit Counter Register */
+#define REG_SPI_RNPR            (0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */
+#define REG_SPI_RNCR            (0x40008114U) /**< \brief (SPI) Receive Next Counter Register */
+#define REG_SPI_TNPR            (0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */
+#define REG_SPI_TNCR            (0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */
+#define REG_SPI_PTCR            (0x40008120U) /**< \brief (SPI) Transfer Control Register */
+#define REG_SPI_PTSR            (0x40008124U) /**< \brief (SPI) Transfer Status Register */
+#else
+#define REG_SPI_CR     (*(WoReg*)0x40008000U) /**< \brief (SPI) Control Register */
+#define REG_SPI_MR     (*(RwReg*)0x40008004U) /**< \brief (SPI) Mode Register */
+#define REG_SPI_RDR    (*(RoReg*)0x40008008U) /**< \brief (SPI) Receive Data Register */
+#define REG_SPI_TDR    (*(WoReg*)0x4000800CU) /**< \brief (SPI) Transmit Data Register */
+#define REG_SPI_SR     (*(RoReg*)0x40008010U) /**< \brief (SPI) Status Register */
+#define REG_SPI_IER    (*(WoReg*)0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
+#define REG_SPI_IDR    (*(WoReg*)0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
+#define REG_SPI_IMR    (*(RoReg*)0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
+#define REG_SPI_CSR    (*(RwReg*)0x40008030U) /**< \brief (SPI) Chip Select Register */
+#define REG_SPI_WPMR   (*(RwReg*)0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
+#define REG_SPI_WPSR   (*(RoReg*)0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
+#define REG_SPI_RPR    (*(RwReg*)0x40008100U) /**< \brief (SPI) Receive Pointer Register */
+#define REG_SPI_RCR    (*(RwReg*)0x40008104U) /**< \brief (SPI) Receive Counter Register */
+#define REG_SPI_TPR    (*(RwReg*)0x40008108U) /**< \brief (SPI) Transmit Pointer Register */
+#define REG_SPI_TCR    (*(RwReg*)0x4000810CU) /**< \brief (SPI) Transmit Counter Register */
+#define REG_SPI_RNPR   (*(RwReg*)0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */
+#define REG_SPI_RNCR   (*(RwReg*)0x40008114U) /**< \brief (SPI) Receive Next Counter Register */
+#define REG_SPI_TNPR   (*(RwReg*)0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */
+#define REG_SPI_TNCR   (*(RwReg*)0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */
+#define REG_SPI_PTCR   (*(WoReg*)0x40008120U) /**< \brief (SPI) Transfer Control Register */
+#define REG_SPI_PTSR   (*(RoReg*)0x40008124U) /**< \brief (SPI) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_SPI_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_ssc.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_ssc.h
new file mode 100644
index 000000000..ce9623814
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_ssc.h
@@ -0,0 +1,94 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_SSC_INSTANCE_
+#define _SAM3S_SSC_INSTANCE_
+
+/* ========== Register definition for SSC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_SSC_CR            (0x40004000U) /**< \brief (SSC) Control Register */
+#define REG_SSC_CMR           (0x40004004U) /**< \brief (SSC) Clock Mode Register */
+#define REG_SSC_RCMR          (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
+#define REG_SSC_RFMR          (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
+#define REG_SSC_TCMR          (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
+#define REG_SSC_TFMR          (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
+#define REG_SSC_RHR           (0x40004020U) /**< \brief (SSC) Receive Holding Register */
+#define REG_SSC_THR           (0x40004024U) /**< \brief (SSC) Transmit Holding Register */
+#define REG_SSC_RSHR          (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
+#define REG_SSC_TSHR          (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
+#define REG_SSC_RC0R          (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
+#define REG_SSC_RC1R          (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
+#define REG_SSC_SR            (0x40004040U) /**< \brief (SSC) Status Register */
+#define REG_SSC_IER           (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
+#define REG_SSC_IDR           (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
+#define REG_SSC_IMR           (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
+#define REG_SSC_WPMR          (0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
+#define REG_SSC_WPSR          (0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
+#define REG_SSC_RPR           (0x40004100U) /**< \brief (SSC) Receive Pointer Register */
+#define REG_SSC_RCR           (0x40004104U) /**< \brief (SSC) Receive Counter Register */
+#define REG_SSC_TPR           (0x40004108U) /**< \brief (SSC) Transmit Pointer Register */
+#define REG_SSC_TCR           (0x4000410CU) /**< \brief (SSC) Transmit Counter Register */
+#define REG_SSC_RNPR          (0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */
+#define REG_SSC_RNCR          (0x40004114U) /**< \brief (SSC) Receive Next Counter Register */
+#define REG_SSC_TNPR          (0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */
+#define REG_SSC_TNCR          (0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */
+#define REG_SSC_PTCR          (0x40004120U) /**< \brief (SSC) Transfer Control Register */
+#define REG_SSC_PTSR          (0x40004124U) /**< \brief (SSC) Transfer Status Register */
+#else
+#define REG_SSC_CR   (*(WoReg*)0x40004000U) /**< \brief (SSC) Control Register */
+#define REG_SSC_CMR  (*(RwReg*)0x40004004U) /**< \brief (SSC) Clock Mode Register */
+#define REG_SSC_RCMR (*(RwReg*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
+#define REG_SSC_RFMR (*(RwReg*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
+#define REG_SSC_TCMR (*(RwReg*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
+#define REG_SSC_TFMR (*(RwReg*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
+#define REG_SSC_RHR  (*(RoReg*)0x40004020U) /**< \brief (SSC) Receive Holding Register */
+#define REG_SSC_THR  (*(WoReg*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */
+#define REG_SSC_RSHR (*(RoReg*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
+#define REG_SSC_TSHR (*(RwReg*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
+#define REG_SSC_RC0R (*(RwReg*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
+#define REG_SSC_RC1R (*(RwReg*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
+#define REG_SSC_SR   (*(RoReg*)0x40004040U) /**< \brief (SSC) Status Register */
+#define REG_SSC_IER  (*(WoReg*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
+#define REG_SSC_IDR  (*(WoReg*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
+#define REG_SSC_IMR  (*(RoReg*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
+#define REG_SSC_WPMR (*(RwReg*)0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
+#define REG_SSC_WPSR (*(RoReg*)0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
+#define REG_SSC_RPR  (*(RwReg*)0x40004100U) /**< \brief (SSC) Receive Pointer Register */
+#define REG_SSC_RCR  (*(RwReg*)0x40004104U) /**< \brief (SSC) Receive Counter Register */
+#define REG_SSC_TPR  (*(RwReg*)0x40004108U) /**< \brief (SSC) Transmit Pointer Register */
+#define REG_SSC_TCR  (*(RwReg*)0x4000410CU) /**< \brief (SSC) Transmit Counter Register */
+#define REG_SSC_RNPR (*(RwReg*)0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */
+#define REG_SSC_RNCR (*(RwReg*)0x40004114U) /**< \brief (SSC) Receive Next Counter Register */
+#define REG_SSC_TNPR (*(RwReg*)0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */
+#define REG_SSC_TNCR (*(RwReg*)0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */
+#define REG_SSC_PTCR (*(WoReg*)0x40004120U) /**< \brief (SSC) Transfer Control Register */
+#define REG_SSC_PTSR (*(RoReg*)0x40004124U) /**< \brief (SSC) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_SSC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_supc.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_supc.h
new file mode 100644
index 000000000..7a05575e3
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_supc.h
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_SUPC_INSTANCE_
+#define _SAM3S_SUPC_INSTANCE_
+
+/* ========== Register definition for SUPC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_SUPC_CR            (0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */
+#define REG_SUPC_SMMR          (0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
+#define REG_SUPC_MR            (0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */
+#define REG_SUPC_WUMR          (0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
+#define REG_SUPC_WUIR          (0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
+#define REG_SUPC_SR            (0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */
+#else
+#define REG_SUPC_CR   (*(WoReg*)0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */
+#define REG_SUPC_SMMR (*(RwReg*)0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
+#define REG_SUPC_MR   (*(RwReg*)0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */
+#define REG_SUPC_WUMR (*(RwReg*)0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
+#define REG_SUPC_WUIR (*(RwReg*)0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
+#define REG_SUPC_SR   (*(RoReg*)0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_SUPC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_tc0.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_tc0.h
new file mode 100644
index 000000000..24b829ad8
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_tc0.h
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_TC0_INSTANCE_
+#define _SAM3S_TC0_INSTANCE_
+
+/* ========== Register definition for TC0 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_TC0_CCR0           (0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
+#define REG_TC0_CMR0           (0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
+#define REG_TC0_SMMR0          (0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC0_CV0            (0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */
+#define REG_TC0_RA0            (0x40010014U) /**< \brief (TC0) Register A (channel = 0) */
+#define REG_TC0_RB0            (0x40010018U) /**< \brief (TC0) Register B (channel = 0) */
+#define REG_TC0_RC0            (0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */
+#define REG_TC0_SR0            (0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */
+#define REG_TC0_IER0           (0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
+#define REG_TC0_IDR0           (0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
+#define REG_TC0_IMR0           (0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
+#define REG_TC0_CCR1           (0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
+#define REG_TC0_CMR1           (0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
+#define REG_TC0_SMMR1          (0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC0_CV1            (0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */
+#define REG_TC0_RA1            (0x40010054U) /**< \brief (TC0) Register A (channel = 1) */
+#define REG_TC0_RB1            (0x40010058U) /**< \brief (TC0) Register B (channel = 1) */
+#define REG_TC0_RC1            (0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */
+#define REG_TC0_SR1            (0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */
+#define REG_TC0_IER1           (0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
+#define REG_TC0_IDR1           (0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
+#define REG_TC0_IMR1           (0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
+#define REG_TC0_CCR2           (0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
+#define REG_TC0_CMR2           (0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
+#define REG_TC0_SMMR2          (0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC0_CV2            (0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */
+#define REG_TC0_RA2            (0x40010094U) /**< \brief (TC0) Register A (channel = 2) */
+#define REG_TC0_RB2            (0x40010098U) /**< \brief (TC0) Register B (channel = 2) */
+#define REG_TC0_RC2            (0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */
+#define REG_TC0_SR2            (0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */
+#define REG_TC0_IER2           (0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
+#define REG_TC0_IDR2           (0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
+#define REG_TC0_IMR2           (0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
+#define REG_TC0_BCR            (0x400100C0U) /**< \brief (TC0) Block Control Register */
+#define REG_TC0_BMR            (0x400100C4U) /**< \brief (TC0) Block Mode Register */
+#define REG_TC0_QIER           (0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
+#define REG_TC0_QIDR           (0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
+#define REG_TC0_QIMR           (0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
+#define REG_TC0_QISR           (0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
+#define REG_TC0_FMR            (0x400100D8U) /**< \brief (TC0) Fault Mode Register */
+#define REG_TC0_WPMR           (0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */
+#else
+#define REG_TC0_CCR0  (*(WoReg*)0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
+#define REG_TC0_CMR0  (*(RwReg*)0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
+#define REG_TC0_SMMR0 (*(RwReg*)0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC0_CV0   (*(RoReg*)0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */
+#define REG_TC0_RA0   (*(RwReg*)0x40010014U) /**< \brief (TC0) Register A (channel = 0) */
+#define REG_TC0_RB0   (*(RwReg*)0x40010018U) /**< \brief (TC0) Register B (channel = 0) */
+#define REG_TC0_RC0   (*(RwReg*)0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */
+#define REG_TC0_SR0   (*(RoReg*)0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */
+#define REG_TC0_IER0  (*(WoReg*)0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
+#define REG_TC0_IDR0  (*(WoReg*)0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
+#define REG_TC0_IMR0  (*(RoReg*)0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
+#define REG_TC0_CCR1  (*(WoReg*)0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
+#define REG_TC0_CMR1  (*(RwReg*)0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
+#define REG_TC0_SMMR1 (*(RwReg*)0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC0_CV1   (*(RoReg*)0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */
+#define REG_TC0_RA1   (*(RwReg*)0x40010054U) /**< \brief (TC0) Register A (channel = 1) */
+#define REG_TC0_RB1   (*(RwReg*)0x40010058U) /**< \brief (TC0) Register B (channel = 1) */
+#define REG_TC0_RC1   (*(RwReg*)0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */
+#define REG_TC0_SR1   (*(RoReg*)0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */
+#define REG_TC0_IER1  (*(WoReg*)0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
+#define REG_TC0_IDR1  (*(WoReg*)0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
+#define REG_TC0_IMR1  (*(RoReg*)0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
+#define REG_TC0_CCR2  (*(WoReg*)0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
+#define REG_TC0_CMR2  (*(RwReg*)0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
+#define REG_TC0_SMMR2 (*(RwReg*)0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC0_CV2   (*(RoReg*)0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */
+#define REG_TC0_RA2   (*(RwReg*)0x40010094U) /**< \brief (TC0) Register A (channel = 2) */
+#define REG_TC0_RB2   (*(RwReg*)0x40010098U) /**< \brief (TC0) Register B (channel = 2) */
+#define REG_TC0_RC2   (*(RwReg*)0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */
+#define REG_TC0_SR2   (*(RoReg*)0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */
+#define REG_TC0_IER2  (*(WoReg*)0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
+#define REG_TC0_IDR2  (*(WoReg*)0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
+#define REG_TC0_IMR2  (*(RoReg*)0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
+#define REG_TC0_BCR   (*(WoReg*)0x400100C0U) /**< \brief (TC0) Block Control Register */
+#define REG_TC0_BMR   (*(RwReg*)0x400100C4U) /**< \brief (TC0) Block Mode Register */
+#define REG_TC0_QIER  (*(WoReg*)0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
+#define REG_TC0_QIDR  (*(WoReg*)0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
+#define REG_TC0_QIMR  (*(RoReg*)0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
+#define REG_TC0_QISR  (*(RoReg*)0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
+#define REG_TC0_FMR   (*(RwReg*)0x400100D8U) /**< \brief (TC0) Fault Mode Register */
+#define REG_TC0_WPMR  (*(RwReg*)0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_TC0_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_tc1.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_tc1.h
new file mode 100644
index 000000000..9a21a125f
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_tc1.h
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_TC1_INSTANCE_
+#define _SAM3S_TC1_INSTANCE_
+
+/* ========== Register definition for TC1 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_TC1_CCR0           (0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
+#define REG_TC1_CMR0           (0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
+#define REG_TC1_SMMR0          (0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC1_CV0            (0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */
+#define REG_TC1_RA0            (0x40014014U) /**< \brief (TC1) Register A (channel = 0) */
+#define REG_TC1_RB0            (0x40014018U) /**< \brief (TC1) Register B (channel = 0) */
+#define REG_TC1_RC0            (0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */
+#define REG_TC1_SR0            (0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */
+#define REG_TC1_IER0           (0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
+#define REG_TC1_IDR0           (0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
+#define REG_TC1_IMR0           (0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
+#define REG_TC1_CCR1           (0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
+#define REG_TC1_CMR1           (0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
+#define REG_TC1_SMMR1          (0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC1_CV1            (0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */
+#define REG_TC1_RA1            (0x40014054U) /**< \brief (TC1) Register A (channel = 1) */
+#define REG_TC1_RB1            (0x40014058U) /**< \brief (TC1) Register B (channel = 1) */
+#define REG_TC1_RC1            (0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */
+#define REG_TC1_SR1            (0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */
+#define REG_TC1_IER1           (0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
+#define REG_TC1_IDR1           (0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
+#define REG_TC1_IMR1           (0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
+#define REG_TC1_CCR2           (0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
+#define REG_TC1_CMR2           (0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
+#define REG_TC1_SMMR2          (0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC1_CV2            (0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */
+#define REG_TC1_RA2            (0x40014094U) /**< \brief (TC1) Register A (channel = 2) */
+#define REG_TC1_RB2            (0x40014098U) /**< \brief (TC1) Register B (channel = 2) */
+#define REG_TC1_RC2            (0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */
+#define REG_TC1_SR2            (0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */
+#define REG_TC1_IER2           (0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
+#define REG_TC1_IDR2           (0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
+#define REG_TC1_IMR2           (0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
+#define REG_TC1_BCR            (0x400140C0U) /**< \brief (TC1) Block Control Register */
+#define REG_TC1_BMR            (0x400140C4U) /**< \brief (TC1) Block Mode Register */
+#define REG_TC1_QIER           (0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
+#define REG_TC1_QIDR           (0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
+#define REG_TC1_QIMR           (0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
+#define REG_TC1_QISR           (0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
+#define REG_TC1_FMR            (0x400140D8U) /**< \brief (TC1) Fault Mode Register */
+#define REG_TC1_WPMR           (0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */
+#else
+#define REG_TC1_CCR0  (*(WoReg*)0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
+#define REG_TC1_CMR0  (*(RwReg*)0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
+#define REG_TC1_SMMR0 (*(RwReg*)0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC1_CV0   (*(RoReg*)0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */
+#define REG_TC1_RA0   (*(RwReg*)0x40014014U) /**< \brief (TC1) Register A (channel = 0) */
+#define REG_TC1_RB0   (*(RwReg*)0x40014018U) /**< \brief (TC1) Register B (channel = 0) */
+#define REG_TC1_RC0   (*(RwReg*)0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */
+#define REG_TC1_SR0   (*(RoReg*)0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */
+#define REG_TC1_IER0  (*(WoReg*)0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
+#define REG_TC1_IDR0  (*(WoReg*)0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
+#define REG_TC1_IMR0  (*(RoReg*)0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
+#define REG_TC1_CCR1  (*(WoReg*)0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
+#define REG_TC1_CMR1  (*(RwReg*)0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
+#define REG_TC1_SMMR1 (*(RwReg*)0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC1_CV1   (*(RoReg*)0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */
+#define REG_TC1_RA1   (*(RwReg*)0x40014054U) /**< \brief (TC1) Register A (channel = 1) */
+#define REG_TC1_RB1   (*(RwReg*)0x40014058U) /**< \brief (TC1) Register B (channel = 1) */
+#define REG_TC1_RC1   (*(RwReg*)0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */
+#define REG_TC1_SR1   (*(RoReg*)0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */
+#define REG_TC1_IER1  (*(WoReg*)0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
+#define REG_TC1_IDR1  (*(WoReg*)0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
+#define REG_TC1_IMR1  (*(RoReg*)0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
+#define REG_TC1_CCR2  (*(WoReg*)0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
+#define REG_TC1_CMR2  (*(RwReg*)0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
+#define REG_TC1_SMMR2 (*(RwReg*)0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC1_CV2   (*(RoReg*)0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */
+#define REG_TC1_RA2   (*(RwReg*)0x40014094U) /**< \brief (TC1) Register A (channel = 2) */
+#define REG_TC1_RB2   (*(RwReg*)0x40014098U) /**< \brief (TC1) Register B (channel = 2) */
+#define REG_TC1_RC2   (*(RwReg*)0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */
+#define REG_TC1_SR2   (*(RoReg*)0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */
+#define REG_TC1_IER2  (*(WoReg*)0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
+#define REG_TC1_IDR2  (*(WoReg*)0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
+#define REG_TC1_IMR2  (*(RoReg*)0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
+#define REG_TC1_BCR   (*(WoReg*)0x400140C0U) /**< \brief (TC1) Block Control Register */
+#define REG_TC1_BMR   (*(RwReg*)0x400140C4U) /**< \brief (TC1) Block Mode Register */
+#define REG_TC1_QIER  (*(WoReg*)0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
+#define REG_TC1_QIDR  (*(WoReg*)0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
+#define REG_TC1_QIMR  (*(RoReg*)0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
+#define REG_TC1_QISR  (*(RoReg*)0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
+#define REG_TC1_FMR   (*(RwReg*)0x400140D8U) /**< \brief (TC1) Fault Mode Register */
+#define REG_TC1_WPMR  (*(RwReg*)0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_TC1_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_twi0.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_twi0.h
new file mode 100644
index 000000000..cd8cb0a5b
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_twi0.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_TWI0_INSTANCE_
+#define _SAM3S_TWI0_INSTANCE_
+
+/* ========== Register definition for TWI0 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_TWI0_CR            (0x40018000U) /**< \brief (TWI0) Control Register */
+#define REG_TWI0_MMR           (0x40018004U) /**< \brief (TWI0) Master Mode Register */
+#define REG_TWI0_SMR           (0x40018008U) /**< \brief (TWI0) Slave Mode Register */
+#define REG_TWI0_IADR          (0x4001800CU) /**< \brief (TWI0) Internal Address Register */
+#define REG_TWI0_CWGR          (0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */
+#define REG_TWI0_SR            (0x40018020U) /**< \brief (TWI0) Status Register */
+#define REG_TWI0_IER           (0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */
+#define REG_TWI0_IDR           (0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */
+#define REG_TWI0_IMR           (0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */
+#define REG_TWI0_RHR           (0x40018030U) /**< \brief (TWI0) Receive Holding Register */
+#define REG_TWI0_THR           (0x40018034U) /**< \brief (TWI0) Transmit Holding Register */
+#define REG_TWI0_RPR           (0x40018100U) /**< \brief (TWI0) Receive Pointer Register */
+#define REG_TWI0_RCR           (0x40018104U) /**< \brief (TWI0) Receive Counter Register */
+#define REG_TWI0_TPR           (0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */
+#define REG_TWI0_TCR           (0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */
+#define REG_TWI0_RNPR          (0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */
+#define REG_TWI0_RNCR          (0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */
+#define REG_TWI0_TNPR          (0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */
+#define REG_TWI0_TNCR          (0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */
+#define REG_TWI0_PTCR          (0x40018120U) /**< \brief (TWI0) Transfer Control Register */
+#define REG_TWI0_PTSR          (0x40018124U) /**< \brief (TWI0) Transfer Status Register */
+#else
+#define REG_TWI0_CR   (*(WoReg*)0x40018000U) /**< \brief (TWI0) Control Register */
+#define REG_TWI0_MMR  (*(RwReg*)0x40018004U) /**< \brief (TWI0) Master Mode Register */
+#define REG_TWI0_SMR  (*(RwReg*)0x40018008U) /**< \brief (TWI0) Slave Mode Register */
+#define REG_TWI0_IADR (*(RwReg*)0x4001800CU) /**< \brief (TWI0) Internal Address Register */
+#define REG_TWI0_CWGR (*(RwReg*)0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */
+#define REG_TWI0_SR   (*(RoReg*)0x40018020U) /**< \brief (TWI0) Status Register */
+#define REG_TWI0_IER  (*(WoReg*)0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */
+#define REG_TWI0_IDR  (*(WoReg*)0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */
+#define REG_TWI0_IMR  (*(RoReg*)0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */
+#define REG_TWI0_RHR  (*(RoReg*)0x40018030U) /**< \brief (TWI0) Receive Holding Register */
+#define REG_TWI0_THR  (*(WoReg*)0x40018034U) /**< \brief (TWI0) Transmit Holding Register */
+#define REG_TWI0_RPR  (*(RwReg*)0x40018100U) /**< \brief (TWI0) Receive Pointer Register */
+#define REG_TWI0_RCR  (*(RwReg*)0x40018104U) /**< \brief (TWI0) Receive Counter Register */
+#define REG_TWI0_TPR  (*(RwReg*)0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */
+#define REG_TWI0_TCR  (*(RwReg*)0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */
+#define REG_TWI0_RNPR (*(RwReg*)0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */
+#define REG_TWI0_RNCR (*(RwReg*)0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */
+#define REG_TWI0_TNPR (*(RwReg*)0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */
+#define REG_TWI0_TNCR (*(RwReg*)0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */
+#define REG_TWI0_PTCR (*(WoReg*)0x40018120U) /**< \brief (TWI0) Transfer Control Register */
+#define REG_TWI0_PTSR (*(RoReg*)0x40018124U) /**< \brief (TWI0) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_TWI0_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_twi1.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_twi1.h
new file mode 100644
index 000000000..8a64ec1a3
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_twi1.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_TWI1_INSTANCE_
+#define _SAM3S_TWI1_INSTANCE_
+
+/* ========== Register definition for TWI1 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_TWI1_CR            (0x4001C000U) /**< \brief (TWI1) Control Register */
+#define REG_TWI1_MMR           (0x4001C004U) /**< \brief (TWI1) Master Mode Register */
+#define REG_TWI1_SMR           (0x4001C008U) /**< \brief (TWI1) Slave Mode Register */
+#define REG_TWI1_IADR          (0x4001C00CU) /**< \brief (TWI1) Internal Address Register */
+#define REG_TWI1_CWGR          (0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */
+#define REG_TWI1_SR            (0x4001C020U) /**< \brief (TWI1) Status Register */
+#define REG_TWI1_IER           (0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */
+#define REG_TWI1_IDR           (0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */
+#define REG_TWI1_IMR           (0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */
+#define REG_TWI1_RHR           (0x4001C030U) /**< \brief (TWI1) Receive Holding Register */
+#define REG_TWI1_THR           (0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */
+#define REG_TWI1_RPR           (0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */
+#define REG_TWI1_RCR           (0x4001C104U) /**< \brief (TWI1) Receive Counter Register */
+#define REG_TWI1_TPR           (0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */
+#define REG_TWI1_TCR           (0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */
+#define REG_TWI1_RNPR          (0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */
+#define REG_TWI1_RNCR          (0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */
+#define REG_TWI1_TNPR          (0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */
+#define REG_TWI1_TNCR          (0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */
+#define REG_TWI1_PTCR          (0x4001C120U) /**< \brief (TWI1) Transfer Control Register */
+#define REG_TWI1_PTSR          (0x4001C124U) /**< \brief (TWI1) Transfer Status Register */
+#else
+#define REG_TWI1_CR   (*(WoReg*)0x4001C000U) /**< \brief (TWI1) Control Register */
+#define REG_TWI1_MMR  (*(RwReg*)0x4001C004U) /**< \brief (TWI1) Master Mode Register */
+#define REG_TWI1_SMR  (*(RwReg*)0x4001C008U) /**< \brief (TWI1) Slave Mode Register */
+#define REG_TWI1_IADR (*(RwReg*)0x4001C00CU) /**< \brief (TWI1) Internal Address Register */
+#define REG_TWI1_CWGR (*(RwReg*)0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */
+#define REG_TWI1_SR   (*(RoReg*)0x4001C020U) /**< \brief (TWI1) Status Register */
+#define REG_TWI1_IER  (*(WoReg*)0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */
+#define REG_TWI1_IDR  (*(WoReg*)0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */
+#define REG_TWI1_IMR  (*(RoReg*)0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */
+#define REG_TWI1_RHR  (*(RoReg*)0x4001C030U) /**< \brief (TWI1) Receive Holding Register */
+#define REG_TWI1_THR  (*(WoReg*)0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */
+#define REG_TWI1_RPR  (*(RwReg*)0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */
+#define REG_TWI1_RCR  (*(RwReg*)0x4001C104U) /**< \brief (TWI1) Receive Counter Register */
+#define REG_TWI1_TPR  (*(RwReg*)0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */
+#define REG_TWI1_TCR  (*(RwReg*)0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */
+#define REG_TWI1_RNPR (*(RwReg*)0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */
+#define REG_TWI1_RNCR (*(RwReg*)0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */
+#define REG_TWI1_TNPR (*(RwReg*)0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */
+#define REG_TWI1_TNCR (*(RwReg*)0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */
+#define REG_TWI1_PTCR (*(WoReg*)0x4001C120U) /**< \brief (TWI1) Transfer Control Register */
+#define REG_TWI1_PTSR (*(RoReg*)0x4001C124U) /**< \brief (TWI1) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_TWI1_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_uart0.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_uart0.h
new file mode 100644
index 000000000..ae95c8d37
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_uart0.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_UART0_INSTANCE_
+#define _SAM3S_UART0_INSTANCE_
+
+/* ========== Register definition for UART0 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_UART0_CR            (0x400E0600U) /**< \brief (UART0) Control Register */
+#define REG_UART0_MR            (0x400E0604U) /**< \brief (UART0) Mode Register */
+#define REG_UART0_IER           (0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */
+#define REG_UART0_IDR           (0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */
+#define REG_UART0_IMR           (0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */
+#define REG_UART0_SR            (0x400E0614U) /**< \brief (UART0) Status Register */
+#define REG_UART0_RHR           (0x400E0618U) /**< \brief (UART0) Receive Holding Register */
+#define REG_UART0_THR           (0x400E061CU) /**< \brief (UART0) Transmit Holding Register */
+#define REG_UART0_BRGR          (0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */
+#define REG_UART0_RPR           (0x400E0700U) /**< \brief (UART0) Receive Pointer Register */
+#define REG_UART0_RCR           (0x400E0704U) /**< \brief (UART0) Receive Counter Register */
+#define REG_UART0_TPR           (0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */
+#define REG_UART0_TCR           (0x400E070CU) /**< \brief (UART0) Transmit Counter Register */
+#define REG_UART0_RNPR          (0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */
+#define REG_UART0_RNCR          (0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */
+#define REG_UART0_TNPR          (0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */
+#define REG_UART0_TNCR          (0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */
+#define REG_UART0_PTCR          (0x400E0720U) /**< \brief (UART0) Transfer Control Register */
+#define REG_UART0_PTSR          (0x400E0724U) /**< \brief (UART0) Transfer Status Register */
+#else
+#define REG_UART0_CR   (*(WoReg*)0x400E0600U) /**< \brief (UART0) Control Register */
+#define REG_UART0_MR   (*(RwReg*)0x400E0604U) /**< \brief (UART0) Mode Register */
+#define REG_UART0_IER  (*(WoReg*)0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */
+#define REG_UART0_IDR  (*(WoReg*)0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */
+#define REG_UART0_IMR  (*(RoReg*)0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */
+#define REG_UART0_SR   (*(RoReg*)0x400E0614U) /**< \brief (UART0) Status Register */
+#define REG_UART0_RHR  (*(RoReg*)0x400E0618U) /**< \brief (UART0) Receive Holding Register */
+#define REG_UART0_THR  (*(WoReg*)0x400E061CU) /**< \brief (UART0) Transmit Holding Register */
+#define REG_UART0_BRGR (*(RwReg*)0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */
+#define REG_UART0_RPR  (*(RwReg*)0x400E0700U) /**< \brief (UART0) Receive Pointer Register */
+#define REG_UART0_RCR  (*(RwReg*)0x400E0704U) /**< \brief (UART0) Receive Counter Register */
+#define REG_UART0_TPR  (*(RwReg*)0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */
+#define REG_UART0_TCR  (*(RwReg*)0x400E070CU) /**< \brief (UART0) Transmit Counter Register */
+#define REG_UART0_RNPR (*(RwReg*)0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */
+#define REG_UART0_RNCR (*(RwReg*)0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */
+#define REG_UART0_TNPR (*(RwReg*)0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */
+#define REG_UART0_TNCR (*(RwReg*)0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */
+#define REG_UART0_PTCR (*(WoReg*)0x400E0720U) /**< \brief (UART0) Transfer Control Register */
+#define REG_UART0_PTSR (*(RoReg*)0x400E0724U) /**< \brief (UART0) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_UART0_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_uart1.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_uart1.h
new file mode 100644
index 000000000..9a9a844ac
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_uart1.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_UART1_INSTANCE_
+#define _SAM3S_UART1_INSTANCE_
+
+/* ========== Register definition for UART1 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_UART1_CR            (0x400E0800U) /**< \brief (UART1) Control Register */
+#define REG_UART1_MR            (0x400E0804U) /**< \brief (UART1) Mode Register */
+#define REG_UART1_IER           (0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */
+#define REG_UART1_IDR           (0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */
+#define REG_UART1_IMR           (0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */
+#define REG_UART1_SR            (0x400E0814U) /**< \brief (UART1) Status Register */
+#define REG_UART1_RHR           (0x400E0818U) /**< \brief (UART1) Receive Holding Register */
+#define REG_UART1_THR           (0x400E081CU) /**< \brief (UART1) Transmit Holding Register */
+#define REG_UART1_BRGR          (0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */
+#define REG_UART1_RPR           (0x400E0900U) /**< \brief (UART1) Receive Pointer Register */
+#define REG_UART1_RCR           (0x400E0904U) /**< \brief (UART1) Receive Counter Register */
+#define REG_UART1_TPR           (0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */
+#define REG_UART1_TCR           (0x400E090CU) /**< \brief (UART1) Transmit Counter Register */
+#define REG_UART1_RNPR          (0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */
+#define REG_UART1_RNCR          (0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */
+#define REG_UART1_TNPR          (0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */
+#define REG_UART1_TNCR          (0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */
+#define REG_UART1_PTCR          (0x400E0920U) /**< \brief (UART1) Transfer Control Register */
+#define REG_UART1_PTSR          (0x400E0924U) /**< \brief (UART1) Transfer Status Register */
+#else
+#define REG_UART1_CR   (*(WoReg*)0x400E0800U) /**< \brief (UART1) Control Register */
+#define REG_UART1_MR   (*(RwReg*)0x400E0804U) /**< \brief (UART1) Mode Register */
+#define REG_UART1_IER  (*(WoReg*)0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */
+#define REG_UART1_IDR  (*(WoReg*)0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */
+#define REG_UART1_IMR  (*(RoReg*)0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */
+#define REG_UART1_SR   (*(RoReg*)0x400E0814U) /**< \brief (UART1) Status Register */
+#define REG_UART1_RHR  (*(RoReg*)0x400E0818U) /**< \brief (UART1) Receive Holding Register */
+#define REG_UART1_THR  (*(WoReg*)0x400E081CU) /**< \brief (UART1) Transmit Holding Register */
+#define REG_UART1_BRGR (*(RwReg*)0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */
+#define REG_UART1_RPR  (*(RwReg*)0x400E0900U) /**< \brief (UART1) Receive Pointer Register */
+#define REG_UART1_RCR  (*(RwReg*)0x400E0904U) /**< \brief (UART1) Receive Counter Register */
+#define REG_UART1_TPR  (*(RwReg*)0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */
+#define REG_UART1_TCR  (*(RwReg*)0x400E090CU) /**< \brief (UART1) Transmit Counter Register */
+#define REG_UART1_RNPR (*(RwReg*)0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */
+#define REG_UART1_RNCR (*(RwReg*)0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */
+#define REG_UART1_TNPR (*(RwReg*)0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */
+#define REG_UART1_TNCR (*(RwReg*)0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */
+#define REG_UART1_PTCR (*(WoReg*)0x400E0920U) /**< \brief (UART1) Transfer Control Register */
+#define REG_UART1_PTSR (*(RoReg*)0x400E0924U) /**< \brief (UART1) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_UART1_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_udp.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_udp.h
new file mode 100644
index 000000000..431799182
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_udp.h
@@ -0,0 +1,62 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_UDP_INSTANCE_
+#define _SAM3S_UDP_INSTANCE_
+
+/* ========== Register definition for UDP peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_UDP_FRM_NUM           (0x40034000U) /**< \brief (UDP) Frame Number Register */
+#define REG_UDP_GLB_STAT          (0x40034004U) /**< \brief (UDP) Global State Register */
+#define REG_UDP_FADDR             (0x40034008U) /**< \brief (UDP) Function Address Register */
+#define REG_UDP_IER               (0x40034010U) /**< \brief (UDP) Interrupt Enable Register */
+#define REG_UDP_IDR               (0x40034014U) /**< \brief (UDP) Interrupt Disable Register */
+#define REG_UDP_IMR               (0x40034018U) /**< \brief (UDP) Interrupt Mask Register */
+#define REG_UDP_ISR               (0x4003401CU) /**< \brief (UDP) Interrupt Status Register */
+#define REG_UDP_ICR               (0x40034020U) /**< \brief (UDP) Interrupt Clear Register */
+#define REG_UDP_RST_EP            (0x40034028U) /**< \brief (UDP) Reset Endpoint Register */
+#define REG_UDP_CSR               (0x40034030U) /**< \brief (UDP) Endpoint Control and Status Register */
+#define REG_UDP_FDR               (0x40034050U) /**< \brief (UDP) Endpoint FIFO Data Register */
+#define REG_UDP_TXVC              (0x40034074U) /**< \brief (UDP) Transceiver Control Register */
+#else
+#define REG_UDP_FRM_NUM  (*(RoReg*)0x40034000U) /**< \brief (UDP) Frame Number Register */
+#define REG_UDP_GLB_STAT (*(RwReg*)0x40034004U) /**< \brief (UDP) Global State Register */
+#define REG_UDP_FADDR    (*(RwReg*)0x40034008U) /**< \brief (UDP) Function Address Register */
+#define REG_UDP_IER      (*(WoReg*)0x40034010U) /**< \brief (UDP) Interrupt Enable Register */
+#define REG_UDP_IDR      (*(WoReg*)0x40034014U) /**< \brief (UDP) Interrupt Disable Register */
+#define REG_UDP_IMR      (*(RoReg*)0x40034018U) /**< \brief (UDP) Interrupt Mask Register */
+#define REG_UDP_ISR      (*(RoReg*)0x4003401CU) /**< \brief (UDP) Interrupt Status Register */
+#define REG_UDP_ICR      (*(WoReg*)0x40034020U) /**< \brief (UDP) Interrupt Clear Register */
+#define REG_UDP_RST_EP   (*(RwReg*)0x40034028U) /**< \brief (UDP) Reset Endpoint Register */
+#define REG_UDP_CSR      (*(RwReg*)0x40034030U) /**< \brief (UDP) Endpoint Control and Status Register */
+#define REG_UDP_FDR      (*(RwReg*)0x40034050U) /**< \brief (UDP) Endpoint FIFO Data Register */
+#define REG_UDP_TXVC     (*(RwReg*)0x40034074U) /**< \brief (UDP) Transceiver Control Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_UDP_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_usart0.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_usart0.h
new file mode 100644
index 000000000..85a80872e
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_usart0.h
@@ -0,0 +1,94 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_USART0_INSTANCE_
+#define _SAM3S_USART0_INSTANCE_
+
+/* ========== Register definition for USART0 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_USART0_CR            (0x40024000U) /**< \brief (USART0) Control Register */
+#define REG_USART0_MR            (0x40024004U) /**< \brief (USART0) Mode Register */
+#define REG_USART0_IER           (0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
+#define REG_USART0_IDR           (0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
+#define REG_USART0_IMR           (0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
+#define REG_USART0_CSR           (0x40024014U) /**< \brief (USART0) Channel Status Register */
+#define REG_USART0_RHR           (0x40024018U) /**< \brief (USART0) Receiver Holding Register */
+#define REG_USART0_THR           (0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */
+#define REG_USART0_BRGR          (0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
+#define REG_USART0_RTOR          (0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
+#define REG_USART0_TTGR          (0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
+#define REG_USART0_FIDI          (0x40024040U) /**< \brief (USART0) FI DI Ratio Register */
+#define REG_USART0_NER           (0x40024044U) /**< \brief (USART0) Number of Errors Register */
+#define REG_USART0_IF            (0x4002404CU) /**< \brief (USART0) IrDA Filter Register */
+#define REG_USART0_MAN           (0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
+#define REG_USART0_WPMR          (0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */
+#define REG_USART0_WPSR          (0x400240E8U) /**< \brief (USART0) Write Protect Status Register */
+#define REG_USART0_VERSION          (0x400240FCU) /**< \brief (USART0) Version Register */
+#define REG_USART0_RPR           (0x40024100U) /**< \brief (USART0) Receive Pointer Register */
+#define REG_USART0_RCR           (0x40024104U) /**< \brief (USART0) Receive Counter Register */
+#define REG_USART0_TPR           (0x40024108U) /**< \brief (USART0) Transmit Pointer Register */
+#define REG_USART0_TCR           (0x4002410CU) /**< \brief (USART0) Transmit Counter Register */
+#define REG_USART0_RNPR          (0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */
+#define REG_USART0_RNCR          (0x40024114U) /**< \brief (USART0) Receive Next Counter Register */
+#define REG_USART0_TNPR          (0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */
+#define REG_USART0_TNCR          (0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */
+#define REG_USART0_PTCR          (0x40024120U) /**< \brief (USART0) Transfer Control Register */
+#define REG_USART0_PTSR          (0x40024124U) /**< \brief (USART0) Transfer Status Register */
+#else
+#define REG_USART0_CR   (*(WoReg*)0x40024000U) /**< \brief (USART0) Control Register */
+#define REG_USART0_MR   (*(RwReg*)0x40024004U) /**< \brief (USART0) Mode Register */
+#define REG_USART0_IER  (*(WoReg*)0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
+#define REG_USART0_IDR  (*(WoReg*)0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
+#define REG_USART0_IMR  (*(RoReg*)0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
+#define REG_USART0_CSR  (*(RoReg*)0x40024014U) /**< \brief (USART0) Channel Status Register */
+#define REG_USART0_RHR  (*(RoReg*)0x40024018U) /**< \brief (USART0) Receiver Holding Register */
+#define REG_USART0_THR  (*(WoReg*)0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */
+#define REG_USART0_BRGR (*(RwReg*)0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
+#define REG_USART0_RTOR (*(RwReg*)0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
+#define REG_USART0_TTGR (*(RwReg*)0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
+#define REG_USART0_FIDI (*(RwReg*)0x40024040U) /**< \brief (USART0) FI DI Ratio Register */
+#define REG_USART0_NER  (*(RoReg*)0x40024044U) /**< \brief (USART0) Number of Errors Register */
+#define REG_USART0_IF   (*(RwReg*)0x4002404CU) /**< \brief (USART0) IrDA Filter Register */
+#define REG_USART0_MAN  (*(RwReg*)0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
+#define REG_USART0_WPMR (*(RwReg*)0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */
+#define REG_USART0_WPSR (*(RoReg*)0x400240E8U) /**< \brief (USART0) Write Protect Status Register */
+#define REG_USART0_VERSION (*(RoReg*)0x400240FCU) /**< \brief (USART0) Version Register */
+#define REG_USART0_RPR  (*(RwReg*)0x40024100U) /**< \brief (USART0) Receive Pointer Register */
+#define REG_USART0_RCR  (*(RwReg*)0x40024104U) /**< \brief (USART0) Receive Counter Register */
+#define REG_USART0_TPR  (*(RwReg*)0x40024108U) /**< \brief (USART0) Transmit Pointer Register */
+#define REG_USART0_TCR  (*(RwReg*)0x4002410CU) /**< \brief (USART0) Transmit Counter Register */
+#define REG_USART0_RNPR (*(RwReg*)0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */
+#define REG_USART0_RNCR (*(RwReg*)0x40024114U) /**< \brief (USART0) Receive Next Counter Register */
+#define REG_USART0_TNPR (*(RwReg*)0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */
+#define REG_USART0_TNCR (*(RwReg*)0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */
+#define REG_USART0_PTCR (*(WoReg*)0x40024120U) /**< \brief (USART0) Transfer Control Register */
+#define REG_USART0_PTSR (*(RoReg*)0x40024124U) /**< \brief (USART0) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_USART0_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_usart1.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_usart1.h
new file mode 100644
index 000000000..380eb086f
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_usart1.h
@@ -0,0 +1,94 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_USART1_INSTANCE_
+#define _SAM3S_USART1_INSTANCE_
+
+/* ========== Register definition for USART1 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_USART1_CR            (0x40028000U) /**< \brief (USART1) Control Register */
+#define REG_USART1_MR            (0x40028004U) /**< \brief (USART1) Mode Register */
+#define REG_USART1_IER           (0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
+#define REG_USART1_IDR           (0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
+#define REG_USART1_IMR           (0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
+#define REG_USART1_CSR           (0x40028014U) /**< \brief (USART1) Channel Status Register */
+#define REG_USART1_RHR           (0x40028018U) /**< \brief (USART1) Receiver Holding Register */
+#define REG_USART1_THR           (0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */
+#define REG_USART1_BRGR          (0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
+#define REG_USART1_RTOR          (0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
+#define REG_USART1_TTGR          (0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
+#define REG_USART1_FIDI          (0x40028040U) /**< \brief (USART1) FI DI Ratio Register */
+#define REG_USART1_NER           (0x40028044U) /**< \brief (USART1) Number of Errors Register */
+#define REG_USART1_IF            (0x4002804CU) /**< \brief (USART1) IrDA Filter Register */
+#define REG_USART1_MAN           (0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
+#define REG_USART1_WPMR          (0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */
+#define REG_USART1_WPSR          (0x400280E8U) /**< \brief (USART1) Write Protect Status Register */
+#define REG_USART1_VERSION          (0x400280FCU) /**< \brief (USART1) Version Register */
+#define REG_USART1_RPR           (0x40028100U) /**< \brief (USART1) Receive Pointer Register */
+#define REG_USART1_RCR           (0x40028104U) /**< \brief (USART1) Receive Counter Register */
+#define REG_USART1_TPR           (0x40028108U) /**< \brief (USART1) Transmit Pointer Register */
+#define REG_USART1_TCR           (0x4002810CU) /**< \brief (USART1) Transmit Counter Register */
+#define REG_USART1_RNPR          (0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */
+#define REG_USART1_RNCR          (0x40028114U) /**< \brief (USART1) Receive Next Counter Register */
+#define REG_USART1_TNPR          (0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */
+#define REG_USART1_TNCR          (0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */
+#define REG_USART1_PTCR          (0x40028120U) /**< \brief (USART1) Transfer Control Register */
+#define REG_USART1_PTSR          (0x40028124U) /**< \brief (USART1) Transfer Status Register */
+#else
+#define REG_USART1_CR   (*(WoReg*)0x40028000U) /**< \brief (USART1) Control Register */
+#define REG_USART1_MR   (*(RwReg*)0x40028004U) /**< \brief (USART1) Mode Register */
+#define REG_USART1_IER  (*(WoReg*)0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
+#define REG_USART1_IDR  (*(WoReg*)0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
+#define REG_USART1_IMR  (*(RoReg*)0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
+#define REG_USART1_CSR  (*(RoReg*)0x40028014U) /**< \brief (USART1) Channel Status Register */
+#define REG_USART1_RHR  (*(RoReg*)0x40028018U) /**< \brief (USART1) Receiver Holding Register */
+#define REG_USART1_THR  (*(WoReg*)0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */
+#define REG_USART1_BRGR (*(RwReg*)0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
+#define REG_USART1_RTOR (*(RwReg*)0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
+#define REG_USART1_TTGR (*(RwReg*)0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
+#define REG_USART1_FIDI (*(RwReg*)0x40028040U) /**< \brief (USART1) FI DI Ratio Register */
+#define REG_USART1_NER  (*(RoReg*)0x40028044U) /**< \brief (USART1) Number of Errors Register */
+#define REG_USART1_IF   (*(RwReg*)0x4002804CU) /**< \brief (USART1) IrDA Filter Register */
+#define REG_USART1_MAN  (*(RwReg*)0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
+#define REG_USART1_WPMR (*(RwReg*)0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */
+#define REG_USART1_WPSR (*(RoReg*)0x400280E8U) /**< \brief (USART1) Write Protect Status Register */
+#define REG_USART1_VERSION (*(RoReg*)0x400280FCU) /**< \brief (USART1) Version Register */
+#define REG_USART1_RPR  (*(RwReg*)0x40028100U) /**< \brief (USART1) Receive Pointer Register */
+#define REG_USART1_RCR  (*(RwReg*)0x40028104U) /**< \brief (USART1) Receive Counter Register */
+#define REG_USART1_TPR  (*(RwReg*)0x40028108U) /**< \brief (USART1) Transmit Pointer Register */
+#define REG_USART1_TCR  (*(RwReg*)0x4002810CU) /**< \brief (USART1) Transmit Counter Register */
+#define REG_USART1_RNPR (*(RwReg*)0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */
+#define REG_USART1_RNCR (*(RwReg*)0x40028114U) /**< \brief (USART1) Receive Next Counter Register */
+#define REG_USART1_TNPR (*(RwReg*)0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */
+#define REG_USART1_TNCR (*(RwReg*)0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */
+#define REG_USART1_PTCR (*(WoReg*)0x40028120U) /**< \brief (USART1) Transfer Control Register */
+#define REG_USART1_PTSR (*(RoReg*)0x40028124U) /**< \brief (USART1) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_USART1_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_wdt.h b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_wdt.h
new file mode 100644
index 000000000..42d37576c
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/instance/instance_wdt.h
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_WDT_INSTANCE_
+#define _SAM3S_WDT_INSTANCE_
+
+/* ========== Register definition for WDT peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_WDT_CR          (0x400E1450U) /**< \brief (WDT) Control Register */
+#define REG_WDT_MR          (0x400E1454U) /**< \brief (WDT) Mode Register */
+#define REG_WDT_SR          (0x400E1458U) /**< \brief (WDT) Status Register */
+#else
+#define REG_WDT_CR (*(WoReg*)0x400E1450U) /**< \brief (WDT) Control Register */
+#define REG_WDT_MR (*(RwReg*)0x400E1454U) /**< \brief (WDT) Mode Register */
+#define REG_WDT_SR (*(RoReg*)0x400E1458U) /**< \brief (WDT) Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S_WDT_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s1a.h b/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s1a.h
new file mode 100644
index 000000000..f17c79fa4
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s1a.h
@@ -0,0 +1,230 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S1A_PIO_
+#define _SAM3S1A_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+
+#endif /* _SAM3S1A_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s1b.h b/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s1b.h
new file mode 100644
index 000000000..60b1f207b
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s1b.h
@@ -0,0 +1,277 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S1B_PIO_
+#define _SAM3S1B_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21           (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22           (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23           (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24           (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25           (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26           (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27           (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28           (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29           (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30           (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31           (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13           (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14           (1u << 14) /**< \brief Pin Controlled by PB14 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0    (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PB14X1_DAC1    (1u << 14) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA2C_DATRG     (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA28C_MCCDA    (1u << 28) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA29C_MCCK     (1u << 29) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA30C_MCDA0    (1u << 30) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA31C_MCDA1    (1u << 31) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA26C_MCDA2    (1u << 26) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA27C_MCDA3    (1u << 27) /**< \brief Hsmci signal: MCDA3 */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1     (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA26A_DCD1     (1u << 26) /**< \brief Usart1 signal: DCD1 */
+#define PIO_PA28A_DSR1     (1u << 28) /**< \brief Usart1 signal: DSR1 */
+#define PIO_PA27A_DTR1     (1u << 27) /**< \brief Usart1 signal: DTR1 */
+#define PIO_PA29A_RI1      (1u << 29) /**< \brief Usart1 signal: RI1 */
+#define PIO_PA24A_RTS1     (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1     (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1     (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1     (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PA21_IDX       21
+#define PIO_PA22_IDX       22
+#define PIO_PA23_IDX       23
+#define PIO_PA24_IDX       24
+#define PIO_PA25_IDX       25
+#define PIO_PA26_IDX       26
+#define PIO_PA27_IDX       27
+#define PIO_PA28_IDX       28
+#define PIO_PA29_IDX       29
+#define PIO_PA30_IDX       30
+#define PIO_PA31_IDX       31
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+#define PIO_PB13_IDX       45
+#define PIO_PB14_IDX       46
+
+#endif /* _SAM3S1B_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s1c.h b/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s1c.h
new file mode 100644
index 000000000..10c6b06ef
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s1c.h
@@ -0,0 +1,395 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S1C_PIO_
+#define _SAM3S1C_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21           (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22           (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23           (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24           (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25           (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26           (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27           (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28           (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29           (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30           (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31           (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13           (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14           (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PC0            (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1            (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2            (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3            (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4            (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5            (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6            (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7            (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8            (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9            (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10           (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11           (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12           (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13           (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14           (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15           (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16           (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17           (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18           (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19           (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20           (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21           (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22           (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23           (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24           (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25           (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26           (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27           (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28           (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29           (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30           (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31           (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0    (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PB14X1_DAC1    (1u << 14) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA2C_DATRG     (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PC18A_A0       (1u << 18) /**< \brief Ebi signal: A0 */
+#define PIO_PC19A_A1       (1u << 19) /**< \brief Ebi signal: A1 */
+#define PIO_PC28A_A10      (1u << 28) /**< \brief Ebi signal: A10 */
+#define PIO_PC29A_A11      (1u << 29) /**< \brief Ebi signal: A11 */
+#define PIO_PC30A_A12      (1u << 30) /**< \brief Ebi signal: A12 */
+#define PIO_PC31A_A13      (1u << 31) /**< \brief Ebi signal: A13 */
+#define PIO_PA18C_A14      (1u << 18) /**< \brief Ebi signal: A14 */
+#define PIO_PA19C_A15      (1u << 19) /**< \brief Ebi signal: A15 */
+#define PIO_PA20C_A16      (1u << 20) /**< \brief Ebi signal: A16 */
+#define PIO_PA0C_A17       (1u << 0)  /**< \brief Ebi signal: A17 */
+#define PIO_PA1C_A18       (1u << 1)  /**< \brief Ebi signal: A18 */
+#define PIO_PA23C_A19      (1u << 23) /**< \brief Ebi signal: A19 */
+#define PIO_PC20A_A2       (1u << 20) /**< \brief Ebi signal: A2 */
+#define PIO_PA24C_A20      (1u << 24) /**< \brief Ebi signal: A20 */
+#define PIO_PC16A_A21      (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PC16A_NANDALE  (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PC17A_A22      (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PC17A_NANDCLE  (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PA25C_A23      (1u << 25) /**< \brief Ebi signal: A23 */
+#define PIO_PC21A_A3       (1u << 21) /**< \brief Ebi signal: A3 */
+#define PIO_PC22A_A4       (1u << 22) /**< \brief Ebi signal: A4 */
+#define PIO_PC23A_A5       (1u << 23) /**< \brief Ebi signal: A5 */
+#define PIO_PC24A_A6       (1u << 24) /**< \brief Ebi signal: A6 */
+#define PIO_PC25A_A7       (1u << 25) /**< \brief Ebi signal: A7 */
+#define PIO_PC26A_A8       (1u << 26) /**< \brief Ebi signal: A8 */
+#define PIO_PC27A_A9       (1u << 27) /**< \brief Ebi signal: A9 */
+#define PIO_PC0A_D0        (1u << 0)  /**< \brief Ebi signal: D0 */
+#define PIO_PC1A_D1        (1u << 1)  /**< \brief Ebi signal: D1 */
+#define PIO_PC2A_D2        (1u << 2)  /**< \brief Ebi signal: D2 */
+#define PIO_PC3A_D3        (1u << 3)  /**< \brief Ebi signal: D3 */
+#define PIO_PC4A_D4        (1u << 4)  /**< \brief Ebi signal: D4 */
+#define PIO_PC5A_D5        (1u << 5)  /**< \brief Ebi signal: D5 */
+#define PIO_PC6A_D6        (1u << 6)  /**< \brief Ebi signal: D6 */
+#define PIO_PC7A_D7        (1u << 7)  /**< \brief Ebi signal: D7 */
+#define PIO_PC9A_NANDOE    (1u << 9)  /**< \brief Ebi signal: NANDOE */
+#define PIO_PC10A_NANDWE   (1u << 10) /**< \brief Ebi signal: NANDWE */
+#define PIO_PC14A_NCS0     (1u << 14) /**< \brief Ebi signal: NCS0 */
+#define PIO_PC15A_NCS1     (1u << 15) /**< \brief Ebi signal: NCS1 */
+#define PIO_PA22C_NCS2     (1u << 22) /**< \brief Ebi signal: NCS2 */
+#define PIO_PC12A_NCS3     (1u << 12) /**< \brief Ebi signal: NCS3 */
+#define PIO_PC11A_NRD      (1u << 11) /**< \brief Ebi signal: NRD */
+#define PIO_PC13A_NWAIT    (1u << 13) /**< \brief Ebi signal: NWAIT */
+#define PIO_PC8A_NWE       (1u << 8)  /**< \brief Ebi signal: NWE */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA28C_MCCDA    (1u << 28) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA29C_MCCK     (1u << 29) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA30C_MCDA0    (1u << 30) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA31C_MCDA1    (1u << 31) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA26C_MCDA2    (1u << 26) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA27C_MCDA3    (1u << 27) /**< \brief Hsmci signal: MCDA3 */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PC25B_TCLK3    (1u << 25) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PC28B_TCLK4    (1u << 28) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PC31B_TCLK5    (1u << 31) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PC23B_TIOA3    (1u << 23) /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PC26B_TIOA4    (1u << 26) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PC29B_TIOA5    (1u << 29) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PC24B_TIOB3    (1u << 24) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PC27B_TIOB4    (1u << 27) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PC30B_TIOB5    (1u << 30) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1     (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA26A_DCD1     (1u << 26) /**< \brief Usart1 signal: DCD1 */
+#define PIO_PA28A_DSR1     (1u << 28) /**< \brief Usart1 signal: DSR1 */
+#define PIO_PA27A_DTR1     (1u << 27) /**< \brief Usart1 signal: DTR1 */
+#define PIO_PA29A_RI1      (1u << 29) /**< \brief Usart1 signal: RI1 */
+#define PIO_PA24A_RTS1     (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1     (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1     (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1     (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PA21_IDX       21
+#define PIO_PA22_IDX       22
+#define PIO_PA23_IDX       23
+#define PIO_PA24_IDX       24
+#define PIO_PA25_IDX       25
+#define PIO_PA26_IDX       26
+#define PIO_PA27_IDX       27
+#define PIO_PA28_IDX       28
+#define PIO_PA29_IDX       29
+#define PIO_PA30_IDX       30
+#define PIO_PA31_IDX       31
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+#define PIO_PB13_IDX       45
+#define PIO_PB14_IDX       46
+#define PIO_PC0_IDX        64
+#define PIO_PC1_IDX        65
+#define PIO_PC2_IDX        66
+#define PIO_PC3_IDX        67
+#define PIO_PC4_IDX        68
+#define PIO_PC5_IDX        69
+#define PIO_PC6_IDX        70
+#define PIO_PC7_IDX        71
+#define PIO_PC8_IDX        72
+#define PIO_PC9_IDX        73
+#define PIO_PC10_IDX       74
+#define PIO_PC11_IDX       75
+#define PIO_PC12_IDX       76
+#define PIO_PC13_IDX       77
+#define PIO_PC14_IDX       78
+#define PIO_PC15_IDX       79
+#define PIO_PC16_IDX       80
+#define PIO_PC17_IDX       81
+#define PIO_PC18_IDX       82
+#define PIO_PC19_IDX       83
+#define PIO_PC20_IDX       84
+#define PIO_PC21_IDX       85
+#define PIO_PC22_IDX       86
+#define PIO_PC23_IDX       87
+#define PIO_PC24_IDX       88
+#define PIO_PC25_IDX       89
+#define PIO_PC26_IDX       90
+#define PIO_PC27_IDX       91
+#define PIO_PC28_IDX       92
+#define PIO_PC29_IDX       93
+#define PIO_PC30_IDX       94
+#define PIO_PC31_IDX       95
+
+#endif /* _SAM3S1C_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s2a.h b/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s2a.h
new file mode 100644
index 000000000..7c195be1c
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s2a.h
@@ -0,0 +1,230 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S2A_PIO_
+#define _SAM3S2A_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+
+#endif /* _SAM3S2A_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s2b.h b/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s2b.h
new file mode 100644
index 000000000..21483f577
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s2b.h
@@ -0,0 +1,277 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S2B_PIO_
+#define _SAM3S2B_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21           (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22           (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23           (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24           (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25           (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26           (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27           (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28           (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29           (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30           (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31           (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13           (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14           (1u << 14) /**< \brief Pin Controlled by PB14 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0    (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PB14X1_DAC1    (1u << 14) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA2C_DATRG     (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA28C_MCCDA    (1u << 28) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA29C_MCCK     (1u << 29) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA30C_MCDA0    (1u << 30) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA31C_MCDA1    (1u << 31) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA26C_MCDA2    (1u << 26) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA27C_MCDA3    (1u << 27) /**< \brief Hsmci signal: MCDA3 */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1     (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA26A_DCD1     (1u << 26) /**< \brief Usart1 signal: DCD1 */
+#define PIO_PA28A_DSR1     (1u << 28) /**< \brief Usart1 signal: DSR1 */
+#define PIO_PA27A_DTR1     (1u << 27) /**< \brief Usart1 signal: DTR1 */
+#define PIO_PA29A_RI1      (1u << 29) /**< \brief Usart1 signal: RI1 */
+#define PIO_PA24A_RTS1     (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1     (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1     (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1     (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PA21_IDX       21
+#define PIO_PA22_IDX       22
+#define PIO_PA23_IDX       23
+#define PIO_PA24_IDX       24
+#define PIO_PA25_IDX       25
+#define PIO_PA26_IDX       26
+#define PIO_PA27_IDX       27
+#define PIO_PA28_IDX       28
+#define PIO_PA29_IDX       29
+#define PIO_PA30_IDX       30
+#define PIO_PA31_IDX       31
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+#define PIO_PB13_IDX       45
+#define PIO_PB14_IDX       46
+
+#endif /* _SAM3S2B_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s2c.h b/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s2c.h
new file mode 100644
index 000000000..42b5d82f8
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s2c.h
@@ -0,0 +1,395 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S2C_PIO_
+#define _SAM3S2C_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21           (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22           (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23           (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24           (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25           (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26           (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27           (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28           (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29           (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30           (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31           (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13           (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14           (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PC0            (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1            (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2            (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3            (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4            (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5            (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6            (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7            (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8            (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9            (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10           (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11           (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12           (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13           (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14           (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15           (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16           (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17           (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18           (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19           (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20           (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21           (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22           (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23           (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24           (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25           (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26           (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27           (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28           (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29           (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30           (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31           (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0    (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PB14X1_DAC1    (1u << 14) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA2C_DATRG     (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PC18A_A0       (1u << 18) /**< \brief Ebi signal: A0 */
+#define PIO_PC19A_A1       (1u << 19) /**< \brief Ebi signal: A1 */
+#define PIO_PC28A_A10      (1u << 28) /**< \brief Ebi signal: A10 */
+#define PIO_PC29A_A11      (1u << 29) /**< \brief Ebi signal: A11 */
+#define PIO_PC30A_A12      (1u << 30) /**< \brief Ebi signal: A12 */
+#define PIO_PC31A_A13      (1u << 31) /**< \brief Ebi signal: A13 */
+#define PIO_PA18C_A14      (1u << 18) /**< \brief Ebi signal: A14 */
+#define PIO_PA19C_A15      (1u << 19) /**< \brief Ebi signal: A15 */
+#define PIO_PA20C_A16      (1u << 20) /**< \brief Ebi signal: A16 */
+#define PIO_PA0C_A17       (1u << 0)  /**< \brief Ebi signal: A17 */
+#define PIO_PA1C_A18       (1u << 1)  /**< \brief Ebi signal: A18 */
+#define PIO_PA23C_A19      (1u << 23) /**< \brief Ebi signal: A19 */
+#define PIO_PC20A_A2       (1u << 20) /**< \brief Ebi signal: A2 */
+#define PIO_PA24C_A20      (1u << 24) /**< \brief Ebi signal: A20 */
+#define PIO_PC16A_A21      (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PC16A_NANDALE  (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PC17A_A22      (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PC17A_NANDCLE  (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PA25C_A23      (1u << 25) /**< \brief Ebi signal: A23 */
+#define PIO_PC21A_A3       (1u << 21) /**< \brief Ebi signal: A3 */
+#define PIO_PC22A_A4       (1u << 22) /**< \brief Ebi signal: A4 */
+#define PIO_PC23A_A5       (1u << 23) /**< \brief Ebi signal: A5 */
+#define PIO_PC24A_A6       (1u << 24) /**< \brief Ebi signal: A6 */
+#define PIO_PC25A_A7       (1u << 25) /**< \brief Ebi signal: A7 */
+#define PIO_PC26A_A8       (1u << 26) /**< \brief Ebi signal: A8 */
+#define PIO_PC27A_A9       (1u << 27) /**< \brief Ebi signal: A9 */
+#define PIO_PC0A_D0        (1u << 0)  /**< \brief Ebi signal: D0 */
+#define PIO_PC1A_D1        (1u << 1)  /**< \brief Ebi signal: D1 */
+#define PIO_PC2A_D2        (1u << 2)  /**< \brief Ebi signal: D2 */
+#define PIO_PC3A_D3        (1u << 3)  /**< \brief Ebi signal: D3 */
+#define PIO_PC4A_D4        (1u << 4)  /**< \brief Ebi signal: D4 */
+#define PIO_PC5A_D5        (1u << 5)  /**< \brief Ebi signal: D5 */
+#define PIO_PC6A_D6        (1u << 6)  /**< \brief Ebi signal: D6 */
+#define PIO_PC7A_D7        (1u << 7)  /**< \brief Ebi signal: D7 */
+#define PIO_PC9A_NANDOE    (1u << 9)  /**< \brief Ebi signal: NANDOE */
+#define PIO_PC10A_NANDWE   (1u << 10) /**< \brief Ebi signal: NANDWE */
+#define PIO_PC14A_NCS0     (1u << 14) /**< \brief Ebi signal: NCS0 */
+#define PIO_PC15A_NCS1     (1u << 15) /**< \brief Ebi signal: NCS1 */
+#define PIO_PA22C_NCS2     (1u << 22) /**< \brief Ebi signal: NCS2 */
+#define PIO_PC12A_NCS3     (1u << 12) /**< \brief Ebi signal: NCS3 */
+#define PIO_PC11A_NRD      (1u << 11) /**< \brief Ebi signal: NRD */
+#define PIO_PC13A_NWAIT    (1u << 13) /**< \brief Ebi signal: NWAIT */
+#define PIO_PC8A_NWE       (1u << 8)  /**< \brief Ebi signal: NWE */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA28C_MCCDA    (1u << 28) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA29C_MCCK     (1u << 29) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA30C_MCDA0    (1u << 30) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA31C_MCDA1    (1u << 31) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA26C_MCDA2    (1u << 26) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA27C_MCDA3    (1u << 27) /**< \brief Hsmci signal: MCDA3 */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PC25B_TCLK3    (1u << 25) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PC28B_TCLK4    (1u << 28) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PC31B_TCLK5    (1u << 31) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PC23B_TIOA3    (1u << 23) /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PC26B_TIOA4    (1u << 26) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PC29B_TIOA5    (1u << 29) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PC24B_TIOB3    (1u << 24) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PC27B_TIOB4    (1u << 27) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PC30B_TIOB5    (1u << 30) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1     (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA26A_DCD1     (1u << 26) /**< \brief Usart1 signal: DCD1 */
+#define PIO_PA28A_DSR1     (1u << 28) /**< \brief Usart1 signal: DSR1 */
+#define PIO_PA27A_DTR1     (1u << 27) /**< \brief Usart1 signal: DTR1 */
+#define PIO_PA29A_RI1      (1u << 29) /**< \brief Usart1 signal: RI1 */
+#define PIO_PA24A_RTS1     (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1     (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1     (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1     (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PA21_IDX       21
+#define PIO_PA22_IDX       22
+#define PIO_PA23_IDX       23
+#define PIO_PA24_IDX       24
+#define PIO_PA25_IDX       25
+#define PIO_PA26_IDX       26
+#define PIO_PA27_IDX       27
+#define PIO_PA28_IDX       28
+#define PIO_PA29_IDX       29
+#define PIO_PA30_IDX       30
+#define PIO_PA31_IDX       31
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+#define PIO_PB13_IDX       45
+#define PIO_PB14_IDX       46
+#define PIO_PC0_IDX        64
+#define PIO_PC1_IDX        65
+#define PIO_PC2_IDX        66
+#define PIO_PC3_IDX        67
+#define PIO_PC4_IDX        68
+#define PIO_PC5_IDX        69
+#define PIO_PC6_IDX        70
+#define PIO_PC7_IDX        71
+#define PIO_PC8_IDX        72
+#define PIO_PC9_IDX        73
+#define PIO_PC10_IDX       74
+#define PIO_PC11_IDX       75
+#define PIO_PC12_IDX       76
+#define PIO_PC13_IDX       77
+#define PIO_PC14_IDX       78
+#define PIO_PC15_IDX       79
+#define PIO_PC16_IDX       80
+#define PIO_PC17_IDX       81
+#define PIO_PC18_IDX       82
+#define PIO_PC19_IDX       83
+#define PIO_PC20_IDX       84
+#define PIO_PC21_IDX       85
+#define PIO_PC22_IDX       86
+#define PIO_PC23_IDX       87
+#define PIO_PC24_IDX       88
+#define PIO_PC25_IDX       89
+#define PIO_PC26_IDX       90
+#define PIO_PC27_IDX       91
+#define PIO_PC28_IDX       92
+#define PIO_PC29_IDX       93
+#define PIO_PC30_IDX       94
+#define PIO_PC31_IDX       95
+
+#endif /* _SAM3S2C_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s4a.h b/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s4a.h
new file mode 100644
index 000000000..d73ff2705
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s4a.h
@@ -0,0 +1,230 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S4A_PIO_
+#define _SAM3S4A_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+
+#endif /* _SAM3S4A_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s4b.h b/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s4b.h
new file mode 100644
index 000000000..2d27ee5bc
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s4b.h
@@ -0,0 +1,277 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S4B_PIO_
+#define _SAM3S4B_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21           (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22           (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23           (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24           (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25           (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26           (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27           (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28           (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29           (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30           (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31           (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13           (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14           (1u << 14) /**< \brief Pin Controlled by PB14 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0    (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PB14X1_DAC1    (1u << 14) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA2C_DATRG     (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA28C_MCCDA    (1u << 28) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA29C_MCCK     (1u << 29) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA30C_MCDA0    (1u << 30) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA31C_MCDA1    (1u << 31) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA26C_MCDA2    (1u << 26) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA27C_MCDA3    (1u << 27) /**< \brief Hsmci signal: MCDA3 */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1     (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA26A_DCD1     (1u << 26) /**< \brief Usart1 signal: DCD1 */
+#define PIO_PA28A_DSR1     (1u << 28) /**< \brief Usart1 signal: DSR1 */
+#define PIO_PA27A_DTR1     (1u << 27) /**< \brief Usart1 signal: DTR1 */
+#define PIO_PA29A_RI1      (1u << 29) /**< \brief Usart1 signal: RI1 */
+#define PIO_PA24A_RTS1     (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1     (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1     (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1     (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PA21_IDX       21
+#define PIO_PA22_IDX       22
+#define PIO_PA23_IDX       23
+#define PIO_PA24_IDX       24
+#define PIO_PA25_IDX       25
+#define PIO_PA26_IDX       26
+#define PIO_PA27_IDX       27
+#define PIO_PA28_IDX       28
+#define PIO_PA29_IDX       29
+#define PIO_PA30_IDX       30
+#define PIO_PA31_IDX       31
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+#define PIO_PB13_IDX       45
+#define PIO_PB14_IDX       46
+
+#endif /* _SAM3S4B_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s4c.h b/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s4c.h
new file mode 100644
index 000000000..f9e512892
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/pio/pio_sam3s4c.h
@@ -0,0 +1,395 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S4C_PIO_
+#define _SAM3S4C_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21           (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22           (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23           (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24           (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25           (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26           (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27           (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28           (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29           (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30           (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31           (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13           (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14           (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PC0            (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1            (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2            (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3            (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4            (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5            (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6            (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7            (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8            (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9            (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10           (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11           (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12           (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13           (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14           (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15           (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16           (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17           (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18           (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19           (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20           (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21           (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22           (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23           (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24           (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25           (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26           (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27           (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28           (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29           (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30           (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31           (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0    (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PB14X1_DAC1    (1u << 14) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA2C_DATRG     (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PC18A_A0       (1u << 18) /**< \brief Ebi signal: A0 */
+#define PIO_PC19A_A1       (1u << 19) /**< \brief Ebi signal: A1 */
+#define PIO_PC28A_A10      (1u << 28) /**< \brief Ebi signal: A10 */
+#define PIO_PC29A_A11      (1u << 29) /**< \brief Ebi signal: A11 */
+#define PIO_PC30A_A12      (1u << 30) /**< \brief Ebi signal: A12 */
+#define PIO_PC31A_A13      (1u << 31) /**< \brief Ebi signal: A13 */
+#define PIO_PA18C_A14      (1u << 18) /**< \brief Ebi signal: A14 */
+#define PIO_PA19C_A15      (1u << 19) /**< \brief Ebi signal: A15 */
+#define PIO_PA20C_A16      (1u << 20) /**< \brief Ebi signal: A16 */
+#define PIO_PA0C_A17       (1u << 0)  /**< \brief Ebi signal: A17 */
+#define PIO_PA1C_A18       (1u << 1)  /**< \brief Ebi signal: A18 */
+#define PIO_PA23C_A19      (1u << 23) /**< \brief Ebi signal: A19 */
+#define PIO_PC20A_A2       (1u << 20) /**< \brief Ebi signal: A2 */
+#define PIO_PA24C_A20      (1u << 24) /**< \brief Ebi signal: A20 */
+#define PIO_PC16A_A21      (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PC16A_NANDALE  (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PC17A_A22      (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PC17A_NANDCLE  (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PA25C_A23      (1u << 25) /**< \brief Ebi signal: A23 */
+#define PIO_PC21A_A3       (1u << 21) /**< \brief Ebi signal: A3 */
+#define PIO_PC22A_A4       (1u << 22) /**< \brief Ebi signal: A4 */
+#define PIO_PC23A_A5       (1u << 23) /**< \brief Ebi signal: A5 */
+#define PIO_PC24A_A6       (1u << 24) /**< \brief Ebi signal: A6 */
+#define PIO_PC25A_A7       (1u << 25) /**< \brief Ebi signal: A7 */
+#define PIO_PC26A_A8       (1u << 26) /**< \brief Ebi signal: A8 */
+#define PIO_PC27A_A9       (1u << 27) /**< \brief Ebi signal: A9 */
+#define PIO_PC0A_D0        (1u << 0)  /**< \brief Ebi signal: D0 */
+#define PIO_PC1A_D1        (1u << 1)  /**< \brief Ebi signal: D1 */
+#define PIO_PC2A_D2        (1u << 2)  /**< \brief Ebi signal: D2 */
+#define PIO_PC3A_D3        (1u << 3)  /**< \brief Ebi signal: D3 */
+#define PIO_PC4A_D4        (1u << 4)  /**< \brief Ebi signal: D4 */
+#define PIO_PC5A_D5        (1u << 5)  /**< \brief Ebi signal: D5 */
+#define PIO_PC6A_D6        (1u << 6)  /**< \brief Ebi signal: D6 */
+#define PIO_PC7A_D7        (1u << 7)  /**< \brief Ebi signal: D7 */
+#define PIO_PC9A_NANDOE    (1u << 9)  /**< \brief Ebi signal: NANDOE */
+#define PIO_PC10A_NANDWE   (1u << 10) /**< \brief Ebi signal: NANDWE */
+#define PIO_PC14A_NCS0     (1u << 14) /**< \brief Ebi signal: NCS0 */
+#define PIO_PC15A_NCS1     (1u << 15) /**< \brief Ebi signal: NCS1 */
+#define PIO_PA22C_NCS2     (1u << 22) /**< \brief Ebi signal: NCS2 */
+#define PIO_PC12A_NCS3     (1u << 12) /**< \brief Ebi signal: NCS3 */
+#define PIO_PC11A_NRD      (1u << 11) /**< \brief Ebi signal: NRD */
+#define PIO_PC13A_NWAIT    (1u << 13) /**< \brief Ebi signal: NWAIT */
+#define PIO_PC8A_NWE       (1u << 8)  /**< \brief Ebi signal: NWE */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA28C_MCCDA    (1u << 28) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA29C_MCCK     (1u << 29) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA30C_MCDA0    (1u << 30) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA31C_MCDA1    (1u << 31) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA26C_MCDA2    (1u << 26) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA27C_MCDA3    (1u << 27) /**< \brief Hsmci signal: MCDA3 */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PC25B_TCLK3    (1u << 25) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PC28B_TCLK4    (1u << 28) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PC31B_TCLK5    (1u << 31) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PC23B_TIOA3    (1u << 23) /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PC26B_TIOA4    (1u << 26) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PC29B_TIOA5    (1u << 29) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PC24B_TIOB3    (1u << 24) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PC27B_TIOB4    (1u << 27) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PC30B_TIOB5    (1u << 30) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1     (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA26A_DCD1     (1u << 26) /**< \brief Usart1 signal: DCD1 */
+#define PIO_PA28A_DSR1     (1u << 28) /**< \brief Usart1 signal: DSR1 */
+#define PIO_PA27A_DTR1     (1u << 27) /**< \brief Usart1 signal: DTR1 */
+#define PIO_PA29A_RI1      (1u << 29) /**< \brief Usart1 signal: RI1 */
+#define PIO_PA24A_RTS1     (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1     (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1     (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1     (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PA21_IDX       21
+#define PIO_PA22_IDX       22
+#define PIO_PA23_IDX       23
+#define PIO_PA24_IDX       24
+#define PIO_PA25_IDX       25
+#define PIO_PA26_IDX       26
+#define PIO_PA27_IDX       27
+#define PIO_PA28_IDX       28
+#define PIO_PA29_IDX       29
+#define PIO_PA30_IDX       30
+#define PIO_PA31_IDX       31
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+#define PIO_PB13_IDX       45
+#define PIO_PB14_IDX       46
+#define PIO_PC0_IDX        64
+#define PIO_PC1_IDX        65
+#define PIO_PC2_IDX        66
+#define PIO_PC3_IDX        67
+#define PIO_PC4_IDX        68
+#define PIO_PC5_IDX        69
+#define PIO_PC6_IDX        70
+#define PIO_PC7_IDX        71
+#define PIO_PC8_IDX        72
+#define PIO_PC9_IDX        73
+#define PIO_PC10_IDX       74
+#define PIO_PC11_IDX       75
+#define PIO_PC12_IDX       76
+#define PIO_PC13_IDX       77
+#define PIO_PC14_IDX       78
+#define PIO_PC15_IDX       79
+#define PIO_PC16_IDX       80
+#define PIO_PC17_IDX       81
+#define PIO_PC18_IDX       82
+#define PIO_PC19_IDX       83
+#define PIO_PC20_IDX       84
+#define PIO_PC21_IDX       85
+#define PIO_PC22_IDX       86
+#define PIO_PC23_IDX       87
+#define PIO_PC24_IDX       88
+#define PIO_PC25_IDX       89
+#define PIO_PC26_IDX       90
+#define PIO_PC27_IDX       91
+#define PIO_PC28_IDX       92
+#define PIO_PC29_IDX       93
+#define PIO_PC30_IDX       94
+#define PIO_PC31_IDX       95
+
+#endif /* _SAM3S4C_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s.h b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s.h
new file mode 100644
index 000000000..f5627c0df
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s.h
@@ -0,0 +1,55 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_
+#define _SAM3S_
+
+#if defined __SAM3S1A__
+  #include "sam3s1a.h"
+#elif defined __SAM3S1B__
+  #include "sam3s1b.h"
+#elif defined __SAM3S1C__
+  #include "sam3s1c.h"
+#elif defined __SAM3S2A__
+  #include "sam3s2a.h"
+#elif defined __SAM3S2B__
+  #include "sam3s2b.h"
+#elif defined __SAM3S2C__
+  #include "sam3s2c.h"
+#elif defined __SAM3S4A__
+  #include "sam3s4a.h"
+#elif defined __SAM3S4B__
+  #include "sam3s4b.h"
+#elif defined __SAM3S4C__
+  #include "sam3s4c.h"
+#else
+  #error Library does not support the specified device.
+#endif
+
+#endif /* _SAM3S_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s1a.h b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s1a.h
new file mode 100644
index 000000000..bc8623a7b
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s1a.h
@@ -0,0 +1,346 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S1A_
+#define _SAM3S1A_
+
+/** \addtogroup SAM3S1A_definitions SAM3S1A definitions
+  This file defines all structures and symbols for SAM3S1A:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3S1A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1A_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3S1A specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3S1A Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3S1A Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3S1A Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3S1A Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3S1A Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3S1A Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3S1A Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3S1A UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3S1A UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3S1A Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3S1A Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3S1A USART 0 (USART0) */
+  TWI0_IRQn            = 19, /**< 19 SAM3S1A Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3S1A Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3S1A Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3S1A Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3S1A Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3S1A Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3S1A Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3S1A Analog To Digital Converter (ADC) */
+  PWM_IRQn             = 31, /**< 31 SAM3S1A Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3S1A CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3S1A Analog Comparator (ACC) */
+  UDP_IRQn             = 34  /**< 34 SAM3S1A USB Device Port (UDP) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3S1A core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S1A does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S1A uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S1A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1A_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3S1A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3S1A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1A_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3S1A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3S1A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1A_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3s1a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3S1A */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x10000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (256u)
+#define IFLASH_NB_OF_LOCK_BITS  (4u)
+#define IRAM_SIZE               (0x4000u)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3S1A */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (64000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3S1A_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s1b.h b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s1b.h
new file mode 100644
index 000000000..f9b011d70
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s1b.h
@@ -0,0 +1,369 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S1B_
+#define _SAM3S1B_
+
+/** \addtogroup SAM3S1B_definitions SAM3S1B definitions
+  This file defines all structures and symbols for SAM3S1B:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3S1B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1B_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3S1B specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3S1B Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3S1B Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3S1B Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3S1B Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3S1B Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3S1B Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3S1B Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3S1B UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3S1B UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3S1B Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3S1B Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3S1B USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3S1B USART 1 (USART1) */
+  HSMCI_IRQn           = 18, /**< 18 SAM3S1B Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 19, /**< 19 SAM3S1B Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3S1B Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3S1B Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3S1B Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3S1B Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3S1B Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3S1B Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3S1B Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3S1B Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3S1B Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3S1B CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3S1B Analog Comparator (ACC) */
+  UDP_IRQn             = 34  /**< 34 SAM3S1B USB Device Port (UDP) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3S1B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S1B does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S1B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S1B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1B_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3S1B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3S1B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1B_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3S1B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  ((Pdc    *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3S1B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1B_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3s1b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3S1B */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x10000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (256u)
+#define IFLASH_NB_OF_LOCK_BITS  (4u)
+#define IRAM_SIZE               (0x4000u)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3S1B */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (64000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3S1B_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s1c.h b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s1c.h
new file mode 100644
index 000000000..c849b07c8
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s1c.h
@@ -0,0 +1,389 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S1C_
+#define _SAM3S1C_
+
+/** \addtogroup SAM3S1C_definitions SAM3S1C definitions
+  This file defines all structures and symbols for SAM3S1C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3S1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3S1C specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3S1C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3S1C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3S1C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3S1C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3S1C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3S1C Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3S1C Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3S1C UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3S1C UART 1 (UART1) */
+  SMC_IRQn             = 10, /**< 10 SAM3S1C Static Memory Controller (SMC) */
+  PIOA_IRQn            = 11, /**< 11 SAM3S1C Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3S1C Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM3S1C Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 14, /**< 14 SAM3S1C USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3S1C USART 1 (USART1) */
+  HSMCI_IRQn           = 18, /**< 18 SAM3S1C Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 19, /**< 19 SAM3S1C Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3S1C Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3S1C Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3S1C Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3S1C Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3S1C Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3S1C Timer/Counter 2 (TC2) */
+  TC3_IRQn             = 26, /**< 26 SAM3S1C Timer/Counter 3 (TC3) */
+  TC4_IRQn             = 27, /**< 27 SAM3S1C Timer/Counter 4 (TC4) */
+  TC5_IRQn             = 28, /**< 28 SAM3S1C Timer/Counter 5 (TC5) */
+  ADC_IRQn             = 29, /**< 29 SAM3S1C Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3S1C Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3S1C Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3S1C CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3S1C Analog Comparator (ACC) */
+  UDP_IRQn             = 34  /**< 34 SAM3S1C USB Device Port (UDP) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3S1C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S1C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S1C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3S1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3S1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_SMC    (10) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_TC3    (26) /**< \brief Timer/Counter 3 (TC3) */
+#define ID_TC4    (27) /**< \brief Timer/Counter 4 (TC4) */
+#define ID_TC5    (28) /**< \brief Timer/Counter 5 (TC5) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3S1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  ((Pdc    *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3S1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3s1c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3S1C */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x10000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (256u)
+#define IFLASH_NB_OF_LOCK_BITS  (4u)
+#define IRAM_SIZE               (0x4000u)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3S1C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (64000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3S1C_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s2a.h b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s2a.h
new file mode 100644
index 000000000..5d21cc47a
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s2a.h
@@ -0,0 +1,346 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S2A_
+#define _SAM3S2A_
+
+/** \addtogroup SAM3S2A_definitions SAM3S2A definitions
+  This file defines all structures and symbols for SAM3S2A:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3S2A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2A_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3S2A specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3S2A Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3S2A Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3S2A Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3S2A Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3S2A Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3S2A Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3S2A Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3S2A UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3S2A UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3S2A Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3S2A Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3S2A USART 0 (USART0) */
+  TWI0_IRQn            = 19, /**< 19 SAM3S2A Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3S2A Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3S2A Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3S2A Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3S2A Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3S2A Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3S2A Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3S2A Analog To Digital Converter (ADC) */
+  PWM_IRQn             = 31, /**< 31 SAM3S2A Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3S2A CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3S2A Analog Comparator (ACC) */
+  UDP_IRQn             = 34  /**< 34 SAM3S2A USB Device Port (UDP) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3S2A core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S2A does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S2A uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S2A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2A_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3S2A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3S2A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2A_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3S2A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3S2A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2A_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3s2a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3S2A */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x20000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (512u)
+#define IFLASH_NB_OF_LOCK_BITS  (8u)
+#define IRAM_SIZE               (0x8000u)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3S2A */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (64000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3S2A_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s2b.h b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s2b.h
new file mode 100644
index 000000000..859c3cbc3
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s2b.h
@@ -0,0 +1,369 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S2B_
+#define _SAM3S2B_
+
+/** \addtogroup SAM3S2B_definitions SAM3S2B definitions
+  This file defines all structures and symbols for SAM3S2B:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3S2B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2B_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3S2B specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3S2B Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3S2B Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3S2B Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3S2B Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3S2B Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3S2B Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3S2B Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3S2B UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3S2B UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3S2B Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3S2B Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3S2B USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3S2B USART 1 (USART1) */
+  HSMCI_IRQn           = 18, /**< 18 SAM3S2B Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 19, /**< 19 SAM3S2B Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3S2B Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3S2B Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3S2B Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3S2B Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3S2B Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3S2B Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3S2B Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3S2B Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3S2B Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3S2B CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3S2B Analog Comparator (ACC) */
+  UDP_IRQn             = 34  /**< 34 SAM3S2B USB Device Port (UDP) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3S2B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S2B does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S2B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S2B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2B_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3S2B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3S2B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2B_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3S2B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  ((Pdc    *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3S2B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2B_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3s2b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3S2B */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x20000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (512u)
+#define IFLASH_NB_OF_LOCK_BITS  (8u)
+#define IRAM_SIZE               (0x8000u)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3S2B */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (64000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3S2B_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s2c.h b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s2c.h
new file mode 100644
index 000000000..26956ca4f
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s2c.h
@@ -0,0 +1,389 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S2C_
+#define _SAM3S2C_
+
+/** \addtogroup SAM3S2C_definitions SAM3S2C definitions
+  This file defines all structures and symbols for SAM3S2C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3S2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3S2C specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3S2C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3S2C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3S2C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3S2C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3S2C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3S2C Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3S2C Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3S2C UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3S2C UART 1 (UART1) */
+  SMC_IRQn             = 10, /**< 10 SAM3S2C Static Memory Controller (SMC) */
+  PIOA_IRQn            = 11, /**< 11 SAM3S2C Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3S2C Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM3S2C Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 14, /**< 14 SAM3S2C USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3S2C USART 1 (USART1) */
+  HSMCI_IRQn           = 18, /**< 18 SAM3S2C Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 19, /**< 19 SAM3S2C Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3S2C Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3S2C Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3S2C Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3S2C Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3S2C Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3S2C Timer/Counter 2 (TC2) */
+  TC3_IRQn             = 26, /**< 26 SAM3S2C Timer/Counter 3 (TC3) */
+  TC4_IRQn             = 27, /**< 27 SAM3S2C Timer/Counter 4 (TC4) */
+  TC5_IRQn             = 28, /**< 28 SAM3S2C Timer/Counter 5 (TC5) */
+  ADC_IRQn             = 29, /**< 29 SAM3S2C Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3S2C Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3S2C Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3S2C CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3S2C Analog Comparator (ACC) */
+  UDP_IRQn             = 34  /**< 34 SAM3S2C USB Device Port (UDP) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3S2C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S2C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S2C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3S2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3S2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_SMC    (10) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_TC3    (26) /**< \brief Timer/Counter 3 (TC3) */
+#define ID_TC4    (27) /**< \brief Timer/Counter 4 (TC4) */
+#define ID_TC5    (28) /**< \brief Timer/Counter 5 (TC5) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3S2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  ((Pdc    *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3S2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3s2c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3S2C */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x20000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (512u)
+#define IFLASH_NB_OF_LOCK_BITS  (8u)
+#define IRAM_SIZE               (0x8000u)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3S2C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (64000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3S2C_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s4a.h b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s4a.h
new file mode 100644
index 000000000..9e8974820
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s4a.h
@@ -0,0 +1,346 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S4A_
+#define _SAM3S4A_
+
+/** \addtogroup SAM3S4A_definitions SAM3S4A definitions
+  This file defines all structures and symbols for SAM3S4A:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3S4A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4A_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3S4A specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3S4A Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3S4A Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3S4A Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3S4A Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3S4A Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3S4A Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3S4A Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3S4A UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3S4A UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3S4A Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3S4A Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3S4A USART 0 (USART0) */
+  TWI0_IRQn            = 19, /**< 19 SAM3S4A Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3S4A Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3S4A Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3S4A Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3S4A Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3S4A Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3S4A Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3S4A Analog To Digital Converter (ADC) */
+  PWM_IRQn             = 31, /**< 31 SAM3S4A Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3S4A CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3S4A Analog Comparator (ACC) */
+  UDP_IRQn             = 34  /**< 34 SAM3S4A USB Device Port (UDP) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3S4A core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S4A does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S4A uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S4A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4A_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3S4A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3S4A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4A_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3S4A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3S4A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4A_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3s4a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3S4A */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x40000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (1024u)
+#define IFLASH_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE               (0xC000u)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3S4A */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (64000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3S4A_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s4b.h b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s4b.h
new file mode 100644
index 000000000..c4f695e5d
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s4b.h
@@ -0,0 +1,369 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S4B_
+#define _SAM3S4B_
+
+/** \addtogroup SAM3S4B_definitions SAM3S4B definitions
+  This file defines all structures and symbols for SAM3S4B:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3S4B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4B_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3S4B specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3S4B Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3S4B Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3S4B Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3S4B Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3S4B Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3S4B Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3S4B Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3S4B UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3S4B UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3S4B Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3S4B Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3S4B USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3S4B USART 1 (USART1) */
+  HSMCI_IRQn           = 18, /**< 18 SAM3S4B Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 19, /**< 19 SAM3S4B Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3S4B Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3S4B Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3S4B Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3S4B Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3S4B Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3S4B Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3S4B Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3S4B Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3S4B Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3S4B CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3S4B Analog Comparator (ACC) */
+  UDP_IRQn             = 34  /**< 34 SAM3S4B USB Device Port (UDP) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3S4B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S4B does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S4B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S4B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4B_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3S4B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3S4B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4B_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3S4B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  ((Pdc    *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3S4B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4B_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3s4b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3S4B */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x40000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (1024u)
+#define IFLASH_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE               (0xC000u)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3S4B */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (64000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3S4B_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s4c.h b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s4c.h
new file mode 100644
index 000000000..f20237359
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s4c.h
@@ -0,0 +1,389 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S4C_
+#define _SAM3S4C_
+
+/** \addtogroup SAM3S4C_definitions SAM3S4C definitions
+  This file defines all structures and symbols for SAM3S4C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3S4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3S4C specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3S4C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3S4C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3S4C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3S4C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3S4C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3S4C Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3S4C Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3S4C UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3S4C UART 1 (UART1) */
+  SMC_IRQn             = 10, /**< 10 SAM3S4C Static Memory Controller (SMC) */
+  PIOA_IRQn            = 11, /**< 11 SAM3S4C Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3S4C Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM3S4C Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 14, /**< 14 SAM3S4C USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3S4C USART 1 (USART1) */
+  HSMCI_IRQn           = 18, /**< 18 SAM3S4C Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 19, /**< 19 SAM3S4C Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3S4C Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3S4C Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3S4C Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3S4C Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3S4C Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3S4C Timer/Counter 2 (TC2) */
+  TC3_IRQn             = 26, /**< 26 SAM3S4C Timer/Counter 3 (TC3) */
+  TC4_IRQn             = 27, /**< 27 SAM3S4C Timer/Counter 4 (TC4) */
+  TC5_IRQn             = 28, /**< 28 SAM3S4C Timer/Counter 5 (TC5) */
+  ADC_IRQn             = 29, /**< 29 SAM3S4C Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3S4C Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3S4C Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3S4C CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3S4C Analog Comparator (ACC) */
+  UDP_IRQn             = 34  /**< 34 SAM3S4C USB Device Port (UDP) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3S4C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S4C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S4C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3S4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3S4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_SMC    (10) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_TC3    (26) /**< \brief Timer/Counter 3 (TC3) */
+#define ID_TC4    (27) /**< \brief Timer/Counter 4 (TC4) */
+#define ID_TC5    (28) /**< \brief Timer/Counter 5 (TC5) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3S4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  ((Pdc    *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3S4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3s4c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3S4C */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x40000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (1024u)
+#define IFLASH_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE               (0xC000u)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3S4C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (64000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3S4C_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/source/templates/exceptions.c b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/exceptions.c
new file mode 100644
index 000000000..a7c89fcf9
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/exceptions.c
@@ -0,0 +1,143 @@
+/*! \file *********************************************************************
+ *
+ * \brief This file contains the default exception handlers.
+ *
+ * $asf_license$
+ *
+ * \par Purpose
+ *
+ * This file provides basic support for Cortex-M processor based
+ * microcontrollers.
+ *
+ * \note
+ * The exception handler has weak aliases.
+ * As they are weak aliases, any function with the same name will override
+ * this definition.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+#include "exceptions.h"
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#ifdef __GNUC__
+/* Cortex-M3 core handlers */
+//void Reset_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
+void NMI_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
+//void HardFault_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
+void MemManage_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
+void BusFault_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
+void UsageFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void ACC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void ADC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void CRCCU_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void DAC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void EEFC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void MCI_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOA_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PWM_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SMC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SSC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SUPC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void USBD_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* __GNUC__ */
+
+#ifdef __ICCARM__
+/* Cortex-M3 core handlers */
+//#pragma weak Reset_Handler=Dummy_Handler
+#pragma weak NMI_Handler=Dummy_Handler
+//#pragma weak HardFault_Handler=Dummy_Handler
+#pragma weak MemManage_Handler=Dummy_Handler
+#pragma weak BusFault_Handler=Dummy_Handler
+#pragma weak UsageFault_Handler=Dummy_Handler
+#pragma weak SVC_Handler=Dummy_Handler
+#pragma weak DebugMon_Handler=Dummy_Handler
+#pragma weak PendSV_Handler=Dummy_Handler
+#pragma weak SysTick_Handler=Dummy_Handler
+
+/* Peripherals handlers */
+#pragma weak ACC_IrqHandler=Dummy_Handler
+#pragma weak ADC_IrqHandler=Dummy_Handler
+#pragma weak CRCCU_IrqHandler=Dummy_Handler
+#pragma weak DAC_IrqHandler=Dummy_Handler
+#pragma weak EEFC_IrqHandler=Dummy_Handler
+#pragma weak MCI_IrqHandler=Dummy_Handler
+#pragma weak PIOA_IrqHandler=Dummy_Handler
+#pragma weak PIOB_IrqHandler=Dummy_Handler
+#pragma weak PIOC_IrqHandler=Dummy_Handler
+#pragma weak PMC_IrqHandler=Dummy_Handler
+#pragma weak PWM_IrqHandler=Dummy_Handler
+#pragma weak RSTC_IrqHandler=Dummy_Handler
+#pragma weak RTC_IrqHandler=Dummy_Handler
+#pragma weak RTT_IrqHandler=Dummy_Handler
+#pragma weak SMC_IrqHandler=Dummy_Handler
+#pragma weak SPI_IrqHandler=Dummy_Handler
+#pragma weak SSC_IrqHandler=Dummy_Handler
+#pragma weak SUPC_IrqHandler=Dummy_Handler
+#pragma weak TC0_IrqHandler=Dummy_Handler
+#pragma weak TC1_IrqHandler=Dummy_Handler
+#pragma weak TC2_IrqHandler=Dummy_Handler
+#pragma weak TC3_IrqHandler=Dummy_Handler
+#pragma weak TC4_IrqHandler=Dummy_Handler
+#pragma weak TC5_IrqHandler=Dummy_Handler
+#pragma weak TWI0_IrqHandler=Dummy_Handler
+#pragma weak TWI1_IrqHandler=Dummy_Handler
+#pragma weak UART0_IrqHandler=Dummy_Handler
+#pragma weak UART1_IrqHandler=Dummy_Handler
+#pragma weak USART0_IrqHandler=Dummy_Handler
+#pragma weak USART1_IrqHandler=Dummy_Handler
+#pragma weak USBD_IrqHandler=Dummy_Handler
+#pragma weak WDT_IrqHandler=Dummy_Handler
+#endif /* __ICCARM__ */
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/source/templates/exceptions.h b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/exceptions.h
new file mode 100644
index 000000000..9fe540757
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/exceptions.h
@@ -0,0 +1,88 @@
+/*! \file *********************************************************************
+ *
+ * \brief This file contains the interface for default exception handlers.
+ *
+ * $asf_license$
+ *
+ * \par Purpose
+ *
+ * This file provides basic support for Cortex-M processor based 
+ * microcontrollers.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+#ifndef EXCEPTIONS_H_INCLUDED
+#define EXCEPTIONS_H_INCLUDED
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+/* Function prototype for exception table items (interrupt handler). */
+typedef void (*IntFunc) (void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+void Reset_Handler(void);
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+
+/* Peripherals handlers */
+void ACC_IrqHandler(void);
+void ADC_IrqHandler(void);
+void CRCCU_IrqHandler(void);
+void DAC_IrqHandler(void);
+void EEFC_IrqHandler(void);
+void MCI_IrqHandler(void);
+void PIOA_IrqHandler(void);
+void PIOB_IrqHandler(void);
+void PIOC_IrqHandler(void);
+void PMC_IrqHandler(void);
+void PWM_IrqHandler(void);
+void RSTC_IrqHandler(void);
+void RTC_IrqHandler(void);
+void RTT_IrqHandler(void);
+void SMC_IrqHandler(void);
+void SPI_IrqHandler(void);
+void SSC_IrqHandler(void);
+void SUPC_IrqHandler(void);
+void TC0_IrqHandler(void);
+void TC1_IrqHandler(void);
+void TC2_IrqHandler(void);
+void TC3_IrqHandler(void);
+void TC4_IrqHandler(void);
+void TC5_IrqHandler(void);
+void TWI0_IrqHandler(void);
+void TWI1_IrqHandler(void);
+void UART0_IrqHandler(void);
+void UART1_IrqHandler(void);
+void USART0_IrqHandler(void);
+void USART1_IrqHandler(void);
+void USBD_IrqHandler(void);
+void WDT_IrqHandler(void);
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#endif /* EXCEPTIONS_H_INCLUDED */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/source/templates/gcc/startup_sam3s.c b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/gcc/startup_sam3s.c
new file mode 100644
index 000000000..93d837d10
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/gcc/startup_sam3s.c
@@ -0,0 +1,137 @@
+/*! \file *********************************************************************
+ *
+ * \brief Startup file for SAM3S.
+ *
+ * $asf_license$
+ *
+ * This file defines common SAM series.
+ *
+ * - Compiler:           ARMGCC
+ * - Supported devices:  All SAM3S devices can be used.
+ * - AppNote:
+ *
+ ******************************************************************************/
+
+#include "../exceptions.h"
+#include "sam3.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+IntFunc exception_table[] = {
+
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(IntFunc) (&_estack),
+	Reset_Handler,
+
+	NMI_Handler,
+	HardFault_Handler,
+	MemManage_Handler,
+	BusFault_Handler,
+	UsageFault_Handler,
+	0, 0, 0, 0,        /* Reserved */
+	SVC_Handler,
+	DebugMon_Handler,
+	0,                 /* Reserved  */
+	PendSV_Handler,
+	SysTick_Handler,
+
+	/* Configurable interrupts  */
+	SUPC_IrqHandler,   /* 0  Supply Controller */
+	RSTC_IrqHandler,   /* 1  Reset Controller */
+	RTC_IrqHandler,    /* 2  Real Time Clock */
+	RTT_IrqHandler,    /* 3  Real Time Timer */
+	WDT_IrqHandler,    /* 4  Watchdog Timer */
+	PMC_IrqHandler,    /* 5  PMC */
+	EEFC_IrqHandler,   /* 6  EEFC */
+	Dummy_Handler,     /* 7  Reserved */
+	UART0_IrqHandler,  /* 8  UART0 */
+	UART1_IrqHandler,  /* 9  UART1 */
+	SMC_IrqHandler,    /* 10 SMC */
+	PIOA_IrqHandler,   /* 11 Parallel IO Controller A */
+	PIOB_IrqHandler,   /* 12 Parallel IO Controller B */
+	PIOC_IrqHandler,   /* 13 Parallel IO Controller C */
+	USART0_IrqHandler, /* 14 USART 0 */
+	USART1_IrqHandler, /* 15 USART 1 */
+	Dummy_Handler,     /* 16 Reserved */
+	Dummy_Handler,     /* 17 Reserved */
+	MCI_IrqHandler,    /* 18 MCI */
+	TWI0_IrqHandler,   /* 19 TWI 0 */
+	TWI1_IrqHandler,   /* 20 TWI 1 */
+	SPI_IrqHandler,    /* 21 SPI */
+	SSC_IrqHandler,    /* 22 SSC */
+	TC0_IrqHandler,    /* 23 Timer Counter 0 */
+	TC1_IrqHandler,    /* 24 Timer Counter 1 */
+	TC2_IrqHandler,    /* 25 Timer Counter 2 */
+	TC3_IrqHandler,    /* 26 Timer Counter 3 */
+	TC4_IrqHandler,    /* 27 Timer Counter 4 */
+	TC5_IrqHandler,    /* 28 Timer Counter 5 */
+	ADC_IrqHandler,    /* 29 ADC controller */
+	DAC_IrqHandler,    /* 30 DAC controller */
+	PWM_IrqHandler,    /* 31 PWM */
+	CRCCU_IrqHandler,  /* 32 CRC Calculation Unit */
+	ACC_IrqHandler,    /* 33 Analog Comparator */
+	USBD_IrqHandler,   /* 34 USB Device Port */
+	Dummy_Handler      /* 35 not used */
+};
+
+/* TEMPORARY PATCH FOR SCB */
+#define SCB_VTOR_TBLBASE_Pos               29                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/source/templates/iar/startup_sam3s.c b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/iar/startup_sam3s.c
new file mode 100644
index 000000000..73a55087b
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/iar/startup_sam3s.c
@@ -0,0 +1,113 @@
+/*! \file *********************************************************************
+ *
+ * \brief Startup file for SAM3S.
+ *
+ * $asf_license$
+ *
+ * This file defines common SAM series.
+ *
+ * - Compiler:           IAR EWARM
+ * - Supported devices:  All SAM3S devices can be used.
+ * - AppNote:
+ *
+ ******************************************************************************/
+
+#include "../exceptions.h"
+#include "sam3.h"
+
+typedef void (*intfunc) (void);
+typedef union { intfunc __fun; void * __ptr; } intvec_elem;
+
+void __iar_program_start(void);
+int __low_level_init(void);
+
+/* Exception Table */
+#pragma language=extended
+#pragma segment="CSTACK"
+
+/* The name "__vector_table" has special meaning for C-SPY: */
+/* it is where the SP start value is found, and the NVIC vector */
+/* table register (VTOR) is initialized to this address if != 0 */
+
+#pragma section = ".intvec"
+#pragma location = ".intvec"
+const intvec_elem __vector_table[] = {
+	{.__ptr = __sfe("CSTACK")},
+	{Reset_Handler},
+
+	{NMI_Handler},
+	{HardFault_Handler},
+	{MemManage_Handler},
+	{BusFault_Handler},
+	{UsageFault_Handler},
+	{0}, {0}, {0}, {0},   /*  Reserved */
+	{SVC_Handler},
+	{DebugMon_Handler},
+	{0},                   /*  Reserved */
+	{PendSV_Handler},
+	{SysTick_Handler},
+
+	/* Configurable interrupts */
+	{SUPC_IrqHandler},     /* 0  Supply Controller */
+	{RSTC_IrqHandler},     /* 1  Reset Controller */
+	{RTC_IrqHandler},      /* 2  Real Time Clock */
+	{RTT_IrqHandler},      /* 3  Real Time Timer */
+	{WDT_IrqHandler},      /* 4  Watchdog Timer */
+	{PMC_IrqHandler},      /* 5  PMC */
+	{EEFC_IrqHandler},     /* 6  EEFC */
+	{Dummy_Handler},       /* 7  Reserved */
+	{UART0_IrqHandler},    /* 8  UART0 */
+	{UART1_IrqHandler},    /* 9  UART1 */
+	{SMC_IrqHandler},      /* 10 SMC */
+	{PIOA_IrqHandler},     /* 11 Parallel IO Controller A */
+	{PIOB_IrqHandler},     /* 12 Parallel IO Controller B */
+	{PIOC_IrqHandler},     /* 13 Parallel IO Controller C */
+	{USART0_IrqHandler},   /* 14 USART 0 */
+	{USART1_IrqHandler},   /* 15 USART 1 */
+	{Dummy_Handler},       /* 16 Reserved */
+	{Dummy_Handler},       /* 17 Reserved */
+	{MCI_IrqHandler},      /* 18 MCI */
+	{TWI0_IrqHandler},     /* 19 TWI 0 */
+	{TWI1_IrqHandler},     /* 20 TWI 1 */
+	{SPI_IrqHandler},      /* 21 SPI */
+	{SSC_IrqHandler},      /* 22 SSC */
+	{TC0_IrqHandler},      /* 23 Timer Counter 0 */
+	{TC1_IrqHandler},      /* 24 Timer Counter 1 */
+	{TC2_IrqHandler},      /* 25 Timer Counter 2 */
+	{TC3_IrqHandler},      /* 26 Timer Counter 3 */
+	{TC4_IrqHandler},      /* 27 Timer Counter 4 */
+	{TC5_IrqHandler},      /* 28 Timer Counter 5 */
+	{ADC_IrqHandler},      /* 29 ADC controller */
+	{DAC_IrqHandler},      /* 30 DAC controller */
+	{PWM_IrqHandler},      /* 31 PWM */
+	{CRCCU_IrqHandler},	   /* 32 CRC Calculation Unit */
+	{ACC_IrqHandler},      /* 33 Analog Comparator */
+	{USBD_IrqHandler},     /* 34 USB Device Port */
+	{Dummy_Handler}        /* 35 not used */
+};
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+int __low_level_init(void)
+{
+	uint32_t *pSrc = __section_begin(".intvec");
+
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < (uint32_t) IRAM_ADDR + (uint32_t) IRAM_SIZE)) {
+		SCB->VTOR |= (uint32_t) (1 << SCB_VTOR_TBLBASE_Pos);
+	}
+
+	return 1; /* if return 0, the data sections will not be initialized */
+}
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+	__iar_program_start();
+}
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/source/templates/system_sam3s.c b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/system_sam3s.c
new file mode 100644
index 000000000..6219a6437
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/system_sam3s.c
@@ -0,0 +1,197 @@
+/*! \file *********************************************************************
+ *
+ * \brief Provides the low-level initialization functions that called 
+ * on chip startup.
+ *
+ * $asf_license$
+ *
+ * \par Purpose
+ *
+ * This file provides basic support for Cortex-M processor based 
+ * microcontrollers.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+#include "sam3.h"
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+/* Clock Settings (64MHz) */
+#define SYS_BOARD_OSCOUNT   (CKGR_MOR_MOSCXTST(0x8U))
+#define SYS_BOARD_PLLAR     (CKGR_PLLAR_ONE \
+							| CKGR_PLLAR_MULA(0xfU) \
+							| CKGR_PLLAR_PLLACOUNT(0x3fU) \
+							| CKGR_PLLAR_DIVA(0x3U))
+#define SYS_BOARD_MCKR      (PMC_MCKR_PRES_CLK_1 | PMC_MCKR_CSS_PLLA_CLK)
+
+/* Clock Definitions */
+#define SYS_FREQ_XTAL_32K      	(32768UL)		/* External 32K crystal frequency */
+#define SYS_FREQ_XTAL_XTAL12M	(12000000UL)	/* External 12M crystal frequency */
+
+#define SYS_FREQ_FWS_0	(17000000UL)	/* Maximum operating frequency when FWS is 0 */
+#define SYS_FREQ_FWS_1	(30000000UL)	/* Maximum operating frequency when FWS is 1 */
+#define SYS_FREQ_FWS_2	(54000000UL)	/* Maximum operating frequency when FWS is 2 */
+
+#define SYS_CKGR_MOR_KEY_VALUE	CKGR_MOR_KEY(0x37) /* Key to unlock MOR register */
+
+/* FIXME: should be generated by sock */
+uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+/**
+ * \brief Setup the microcontroller system.
+ * Initialize the System and update the SystemFrequency variable.
+ */
+void SystemInit(void)
+{
+	/* Set 3 FWS for Embedded Flash Access */
+	EFC->EEFC_FMR = EEFC_FMR_FWS(CHIP_FLASH_WAIT_STATE);
+
+	/* Initialize main oscillator */
+	if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {
+		PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | 
+			                     CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
+		while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
+		}
+	}
+
+	/* Switch to 3-20MHz Xtal oscillator */
+	PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | 
+	                           CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
+
+	while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
+	}
+		PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | 
+			                    PMC_MCKR_CSS_MAIN_CLK;
+		while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	/* Initialize PLLA */
+	PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
+	while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
+	}
+
+	/* Switch to main clock */
+	PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	/* Switch to PLLA */
+	PMC->PMC_MCKR = SYS_BOARD_MCKR;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	SystemCoreClock = CHIP_FREQ_CPU_MAX;
+}
+
+void SystemCoreClockUpdate(void)
+{
+	/* Determine clock frequency according to clock register values */
+	switch (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) {
+	case PMC_MCKR_CSS_SLOW_CLK:	/* Slow clock */
+		if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
+			SystemCoreClock = SYS_FREQ_XTAL_32K;
+		} else {
+			SystemCoreClock = CHIP_FREQ_SLCK_RC;
+		}
+		break;
+	case PMC_MCKR_CSS_MAIN_CLK:	/* Main clock */
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
+			SystemCoreClock = SYS_FREQ_XTAL_XTAL12M;
+		} else {
+			SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+			switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
+			case CKGR_MOR_MOSCRCF_4_MHz:
+				break;
+			case CKGR_MOR_MOSCRCF_8_MHz:
+				SystemCoreClock *= 2U;
+				break;
+			case CKGR_MOR_MOSCRCF_12_MHz:
+				SystemCoreClock *= 3U;
+				break;
+			default:
+				break;
+			}
+		}
+		break;
+	case PMC_MCKR_CSS_PLLA_CLK:	/* PLLA clock */
+	case PMC_MCKR_CSS_PLLB_CLK:	/* PLLB clock */
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
+			SystemCoreClock = SYS_FREQ_XTAL_XTAL12M;
+		} else {
+			SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+			switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
+			case CKGR_MOR_MOSCRCF_4_MHz:
+				break;
+			case CKGR_MOR_MOSCRCF_8_MHz:
+				SystemCoreClock *= 2U;
+				break;
+			case CKGR_MOR_MOSCRCF_12_MHz:
+				SystemCoreClock *= 3U;
+				break;
+			default:
+				break;
+			}
+		}
+		if ((uint32_t) (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {
+			SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> 
+				                          CKGR_PLLAR_MULA_Pos) + 1U);
+			SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >> 
+				                          CKGR_PLLAR_DIVA_Pos));
+		} else {
+			SystemCoreClock *= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_MULB_Msk) >> 
+				                           CKGR_PLLBR_MULB_Pos) + 1U);
+			SystemCoreClock /= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_DIVB_Msk) >> 
+				                               CKGR_PLLBR_DIVB_Pos));
+		}
+		break;
+	default:
+		break;
+	}
+
+	if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
+		SystemCoreClock /= 3U;
+	} else {
+		SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);
+	}
+}
+
+/** 
+ * Initialize flash and watchdog.
+ */
+void system_init_flash_and_watchdog(uint32_t dw_clk)
+{
+	/* Set FWS for embedded Flash access according to operating frequency */
+	if (dw_clk < SYS_FREQ_FWS_0) {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(0);
+	} else if (dw_clk < SYS_FREQ_FWS_1) {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(1);
+	} else if (dw_clk < SYS_FREQ_FWS_2) {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(2);
+	} else {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(3);
+	}
+	
+#ifndef CONFIG_KEEP_WATCHDOG_AFTER_INIT 
+	/* Disable the watchdog */
+	WDT->WDT_MR = WDT_MR_WDDIS;
+#endif
+}
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/source/templates/system_sam3s.h b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/system_sam3s.h
new file mode 100644
index 000000000..e5c32e9c4
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/system_sam3s.h
@@ -0,0 +1,58 @@
+/*! \file *********************************************************************
+ *
+ * \brief CMSIS Cortex-M# Device Peripheral Access Layer Header File
+ *           for SAM3 devices.
+ *
+ * $asf_license$
+ *
+ * \par Purpose
+ *
+ * This file provides basic support for Cortex-M processor based 
+ * microcontrollers.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+#ifndef SYSTEM_SAM3S_H_INCLUDED
+#define SYSTEM_SAM3S_H_INCLUDED
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#include 
+
+extern uint32_t SystemCoreClock;	/* System Clock Frequency (Core Clock) */
+
+/**
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+void SystemInit(void);
+
+/**
+ * @brief Updates the SystemCoreClock with current core Clock 
+ * retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void);
+
+/** 
+ * Initialize flash and watchdog.
+ */
+void system_init_flash_and_watchdog(uint32_t dw_clk);
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#endif /* SYSTEM_SAM3S_H_INCLUDED */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_acc.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_acc.h
new file mode 100644
index 000000000..f4d28244a
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_acc.h
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_ACC_COMPONENT_
+#define _SAM3S8_ACC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Analog Comparator Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_ACC Analog Comparator Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Acc hardware registers */
+typedef struct {
+  WoReg ACC_CR;        /**< \brief (Acc Offset: 0x00) Control Register */
+  RwReg ACC_MR;        /**< \brief (Acc Offset: 0x04) Mode Register */
+  RoReg Reserved1[7];
+  WoReg ACC_IER;       /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */
+  WoReg ACC_IDR;       /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */
+  RoReg ACC_IMR;       /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */
+  RoReg ACC_ISR;       /**< \brief (Acc Offset: 0x30) Interrupt Status Register */
+  RoReg Reserved2[24];
+  RwReg ACC_ACR;       /**< \brief (Acc Offset: 0x94) Analog Control Register */
+  RoReg Reserved3[19];
+  RwReg ACC_WPMR;      /**< \brief (Acc Offset: 0xE4) Write Protect Mode Register */
+  RoReg ACC_WPSR;      /**< \brief (Acc Offset: 0xE8) Write Protect Status Register */
+} Acc;
+#endif /* __ASSEMBLY__ */
+/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */
+#define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) SoftWare ReSeT */
+/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */
+#define ACC_MR_SELMINUS_Pos 0
+#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) SELection for MINUS comparator input */
+#define   ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) SelectTS */
+#define   ACC_MR_SELMINUS_ADVREF (0x1u << 0) /**< \brief (ACC_MR) Select ADVREF */
+#define   ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */
+#define   ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */
+#define   ACC_MR_SELMINUS_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AD0 */
+#define   ACC_MR_SELMINUS_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AD1 */
+#define   ACC_MR_SELMINUS_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AD2 */
+#define   ACC_MR_SELMINUS_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AD3 */
+#define ACC_MR_SELPLUS_Pos 4
+#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) SELection for PLUS comparator input */
+#define   ACC_MR_SELPLUS_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AD0 */
+#define   ACC_MR_SELPLUS_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AD1 */
+#define   ACC_MR_SELPLUS_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AD2 */
+#define   ACC_MR_SELPLUS_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AD3 */
+#define   ACC_MR_SELPLUS_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AD4 */
+#define   ACC_MR_SELPLUS_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AD5 */
+#define   ACC_MR_SELPLUS_AD6 (0x6u << 4) /**< \brief (ACC_MR) Select AD6 */
+#define   ACC_MR_SELPLUS_AD7 (0x7u << 4) /**< \brief (ACC_MR) Select AD7 */
+#define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator ENable */
+#define   ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog Comparator Disabled. */
+#define   ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enabled. */
+#define ACC_MR_EDGETYP_Pos 9
+#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) EDGE TYPe */
+#define   ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) only rising edge of comparator output */
+#define   ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) falling edge of comparator output */
+#define   ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) any edge of comparator output */
+#define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) INVert comparator output */
+#define   ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog Comparator output is directly processed. */
+#define   ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog Comparator output is inverted prior to being processed. */
+#define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) SELection of Fault Source */
+#define   ACC_MR_SELFS_CF (0x0u << 13) /**< \brief (ACC_MR) the CF flag is used to drive the FAULT output. */
+#define   ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) the output of the Analog Comparator flag is used to drive the FAULT output. */
+#define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */
+#define   ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) the FAULT output is tied to 0. */
+#define   ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) the FAULT output is driven by the signal defined by SELFS. */
+/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */
+#define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */
+/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */
+#define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */
+/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */
+#define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */
+/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */
+#define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge */
+#define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */
+#define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR)  */
+/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */
+#define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current SELection */
+#define   ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) low power option. */
+#define   ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) high speed option. */
+#define ACC_ACR_HYST_Pos 1
+#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) HYSTeresis selection */
+#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos)))
+/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protect Mode Register -------- */
+#define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protect Enable */
+#define ACC_WPMR_WPKEY_Pos 8
+#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protect KEY */
+#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos)))
+/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protect Status Register -------- */
+#define ACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (ACC_WPSR) Write PROTection ERRor */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_ACC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_adc.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_adc.h
new file mode 100644
index 000000000..ea035adce
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_adc.h
@@ -0,0 +1,527 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_ADC_COMPONENT_
+#define _SAM3S8_ADC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Analog-to-digital Converter */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_ADC Analog-to-digital Converter */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Adc hardware registers */
+typedef struct {
+  WoReg ADC_CR;        /**< \brief (Adc Offset: 0x00) Control Register */
+  RwReg ADC_MR;        /**< \brief (Adc Offset: 0x04) Mode Register */
+  RwReg ADC_SEQR1;     /**< \brief (Adc Offset: 0x08) Channel Sequence Register 1 */
+  RwReg ADC_SEQR2;     /**< \brief (Adc Offset: 0x0C) Channel Sequence Register 2 */
+  WoReg ADC_CHER;      /**< \brief (Adc Offset: 0x10) Channel Enable Register */
+  WoReg ADC_CHDR;      /**< \brief (Adc Offset: 0x14) Channel Disable Register */
+  RoReg ADC_CHSR;      /**< \brief (Adc Offset: 0x18) Channel Status Register */
+  RoReg Reserved1[1];
+  RoReg ADC_LCDR;      /**< \brief (Adc Offset: 0x20) Last Converted Data Register */
+  WoReg ADC_IER;       /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */
+  WoReg ADC_IDR;       /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */
+  RoReg ADC_IMR;       /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */
+  RoReg ADC_ISR;       /**< \brief (Adc Offset: 0x30) Interrupt Status Register */
+  RoReg Reserved2[2];
+  RoReg ADC_OVER;      /**< \brief (Adc Offset: 0x3C) Overrun Status Register */
+  RwReg ADC_EMR;       /**< \brief (Adc Offset: 0x40) Extended Mode Register */
+  RwReg ADC_CWR;       /**< \brief (Adc Offset: 0x44) Compare Window Register */
+  RwReg ADC_CGR;       /**< \brief (Adc Offset: 0x48) Channel Gain Register */
+  RwReg ADC_COR;       /**< \brief (Adc Offset: 0x4C) Channel Offset Register */
+  RoReg ADC_CDR[15];   /**< \brief (Adc Offset: 0x50) Channel Data Register */
+  RoReg Reserved3[2];
+  RwReg ADC_ACR;       /**< \brief (Adc Offset: 0x94) Analog Control Register */
+  RoReg Reserved4[19];
+  RwReg ADC_WPMR;      /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */
+  RoReg ADC_WPSR;      /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved5[5];
+  RwReg ADC_RPR;       /**< \brief (Adc Offset: 0x100) Receive Pointer Register */
+  RwReg ADC_RCR;       /**< \brief (Adc Offset: 0x104) Receive Counter Register */
+  RwReg ADC_TPR;       /**< \brief (Adc Offset: 0x108) Transmit Pointer Register */
+  RwReg ADC_TCR;       /**< \brief (Adc Offset: 0x10C) Transmit Counter Register */
+  RwReg ADC_RNPR;      /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */
+  RwReg ADC_RNCR;      /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */
+  RwReg ADC_TNPR;      /**< \brief (Adc Offset: 0x118) Transmit Next Pointer Register */
+  RwReg ADC_TNCR;      /**< \brief (Adc Offset: 0x11C) Transmit Next Counter Register */
+  WoReg ADC_PTCR;      /**< \brief (Adc Offset: 0x120) Transfer Control Register */
+  RoReg ADC_PTSR;      /**< \brief (Adc Offset: 0x124) Transfer Status Register */
+} Adc;
+#endif /* __ASSEMBLY__ */
+/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */
+#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */
+#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */
+#define ADC_CR_AUTOCAL (0x1u << 3) /**< \brief (ADC_CR) Automatic Calibration of ADC */
+/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */
+#define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */
+#define   ADC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */
+#define   ADC_MR_TRGEN_EN (0x1u << 0) /**< \brief (ADC_MR) Hardware trigger selected by TRGSEL field is enabled. */
+#define ADC_MR_TRGSEL_Pos 1
+#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */
+#define   ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC_MR) External trigger */
+#define   ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 0 */
+#define   ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 1 */
+#define   ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 2 */
+#define   ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) /**< \brief (ADC_MR) PWM Event Line 0 */
+#define   ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) /**< \brief (ADC_MR) PWM Event Line 1 */
+#define ADC_MR_LOWRES (0x1u << 4) /**< \brief (ADC_MR) Resolution */
+#define   ADC_MR_LOWRES_BITS_12 (0x0u << 4) /**< \brief (ADC_MR) 12-bit resolution */
+#define   ADC_MR_LOWRES_BITS_10 (0x1u << 4) /**< \brief (ADC_MR) 10-bit resolution */
+#define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */
+#define   ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions */
+#define   ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions */
+#define ADC_MR_FWUP (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up */
+#define   ADC_MR_FWUP_OFF (0x0u << 6) /**< \brief (ADC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit */
+#define   ADC_MR_FWUP_ON (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF */
+#define ADC_MR_FREERUN (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode */
+#define   ADC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (ADC_MR) Normal Mode */
+#define   ADC_MR_FREERUN_ON (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode: Never wait for any trigger. */
+#define ADC_MR_PRESCAL_Pos 8
+#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */
+#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos)))
+#define ADC_MR_STARTUP_Pos 16
+#define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */
+#define   ADC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (ADC_MR) 0 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (ADC_MR) 8 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (ADC_MR) 16 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (ADC_MR) 24 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (ADC_MR) 64 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (ADC_MR) 80 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (ADC_MR) 96 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (ADC_MR) 112 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (ADC_MR) 512 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (ADC_MR) 576 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (ADC_MR) 640 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (ADC_MR) 704 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (ADC_MR) 768 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (ADC_MR) 832 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (ADC_MR) 896 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (ADC_MR) 960 periods of ADCClock */
+#define ADC_MR_SETTLING_Pos 20
+#define ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos) /**< \brief (ADC_MR) Analog Settling Time */
+#define   ADC_MR_SETTLING_AST3 (0x0u << 20) /**< \brief (ADC_MR) 3 periods of ADCClock */
+#define   ADC_MR_SETTLING_AST5 (0x1u << 20) /**< \brief (ADC_MR) 5 periods of ADCClock */
+#define   ADC_MR_SETTLING_AST9 (0x2u << 20) /**< \brief (ADC_MR) 9 periods of ADCClock */
+#define   ADC_MR_SETTLING_AST17 (0x3u << 20) /**< \brief (ADC_MR) 17 periods of ADCClock */
+#define ADC_MR_ANACH (0x1u << 23) /**< \brief (ADC_MR) Analog Change */
+#define   ADC_MR_ANACH_NONE (0x0u << 23) /**< \brief (ADC_MR) No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels */
+#define   ADC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (ADC_MR) Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers */
+#define ADC_MR_TRACKTIM_Pos 24
+#define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) /**< \brief (ADC_MR) Tracking Time */
+#define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos)))
+#define ADC_MR_TRANSFER_Pos 28
+#define ADC_MR_TRANSFER_Msk (0x3u << ADC_MR_TRANSFER_Pos) /**< \brief (ADC_MR) Transfer Period */
+#define ADC_MR_TRANSFER(value) ((ADC_MR_TRANSFER_Msk & ((value) << ADC_MR_TRANSFER_Pos)))
+#define ADC_MR_USEQ (0x1u << 31) /**< \brief (ADC_MR) Use Sequence Enable */
+#define   ADC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (ADC_MR) Normal Mode: The controller converts channels in a simple numeric order. */
+#define   ADC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers. */
+/* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */
+#define ADC_SEQR1_USCH1_Pos 0
+#define ADC_SEQR1_USCH1_Msk (0x7u << ADC_SEQR1_USCH1_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 1 */
+#define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos)))
+#define ADC_SEQR1_USCH2_Pos 4
+#define ADC_SEQR1_USCH2_Msk (0x7u << ADC_SEQR1_USCH2_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 2 */
+#define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos)))
+#define ADC_SEQR1_USCH3_Pos 8
+#define ADC_SEQR1_USCH3_Msk (0x7u << ADC_SEQR1_USCH3_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 3 */
+#define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos)))
+#define ADC_SEQR1_USCH4_Pos 12
+#define ADC_SEQR1_USCH4_Msk (0x7u << ADC_SEQR1_USCH4_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 4 */
+#define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos)))
+#define ADC_SEQR1_USCH5_Pos 16
+#define ADC_SEQR1_USCH5_Msk (0x7u << ADC_SEQR1_USCH5_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 5 */
+#define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos)))
+#define ADC_SEQR1_USCH6_Pos 20
+#define ADC_SEQR1_USCH6_Msk (0x7u << ADC_SEQR1_USCH6_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 6 */
+#define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos)))
+#define ADC_SEQR1_USCH7_Pos 24
+#define ADC_SEQR1_USCH7_Msk (0x7u << ADC_SEQR1_USCH7_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 7 */
+#define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos)))
+#define ADC_SEQR1_USCH8_Pos 28
+#define ADC_SEQR1_USCH8_Msk (0x7u << ADC_SEQR1_USCH8_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 8 */
+#define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos)))
+/* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */
+#define ADC_SEQR2_USCH9_Pos 0
+#define ADC_SEQR2_USCH9_Msk (0x7u << ADC_SEQR2_USCH9_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 9 */
+#define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos)))
+#define ADC_SEQR2_USCH10_Pos 4
+#define ADC_SEQR2_USCH10_Msk (0x7u << ADC_SEQR2_USCH10_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 10 */
+#define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos)))
+#define ADC_SEQR2_USCH11_Pos 8
+#define ADC_SEQR2_USCH11_Msk (0x7u << ADC_SEQR2_USCH11_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 11 */
+#define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos)))
+#define ADC_SEQR2_USCH12_Pos 12
+#define ADC_SEQR2_USCH12_Msk (0x7u << ADC_SEQR2_USCH12_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 12 */
+#define ADC_SEQR2_USCH12(value) ((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos)))
+#define ADC_SEQR2_USCH13_Pos 16
+#define ADC_SEQR2_USCH13_Msk (0x7u << ADC_SEQR2_USCH13_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 13 */
+#define ADC_SEQR2_USCH13(value) ((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos)))
+#define ADC_SEQR2_USCH14_Pos 20
+#define ADC_SEQR2_USCH14_Msk (0x7u << ADC_SEQR2_USCH14_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 14 */
+#define ADC_SEQR2_USCH14(value) ((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos)))
+#define ADC_SEQR2_USCH15_Pos 24
+#define ADC_SEQR2_USCH15_Msk (0x7u << ADC_SEQR2_USCH15_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 15 */
+#define ADC_SEQR2_USCH15(value) ((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos)))
+#define ADC_SEQR2_USCH16_Pos 28
+#define ADC_SEQR2_USCH16_Msk (0x7u << ADC_SEQR2_USCH16_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 16 */
+#define ADC_SEQR2_USCH16(value) ((ADC_SEQR2_USCH16_Msk & ((value) << ADC_SEQR2_USCH16_Pos)))
+/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */
+#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */
+#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */
+#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */
+#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */
+#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */
+#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */
+#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */
+#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */
+#define ADC_CHER_CH8 (0x1u << 8) /**< \brief (ADC_CHER) Channel 8 Enable */
+#define ADC_CHER_CH9 (0x1u << 9) /**< \brief (ADC_CHER) Channel 9 Enable */
+#define ADC_CHER_CH10 (0x1u << 10) /**< \brief (ADC_CHER) Channel 10 Enable */
+#define ADC_CHER_CH11 (0x1u << 11) /**< \brief (ADC_CHER) Channel 11 Enable */
+#define ADC_CHER_CH12 (0x1u << 12) /**< \brief (ADC_CHER) Channel 12 Enable */
+#define ADC_CHER_CH13 (0x1u << 13) /**< \brief (ADC_CHER) Channel 13 Enable */
+#define ADC_CHER_CH14 (0x1u << 14) /**< \brief (ADC_CHER) Channel 14 Enable */
+#define ADC_CHER_CH15 (0x1u << 15) /**< \brief (ADC_CHER) Channel 15 Enable */
+/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */
+#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */
+#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */
+#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */
+#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */
+#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */
+#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */
+#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */
+#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */
+#define ADC_CHDR_CH8 (0x1u << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */
+#define ADC_CHDR_CH9 (0x1u << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */
+#define ADC_CHDR_CH10 (0x1u << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */
+#define ADC_CHDR_CH11 (0x1u << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */
+#define ADC_CHDR_CH12 (0x1u << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */
+#define ADC_CHDR_CH13 (0x1u << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */
+#define ADC_CHDR_CH14 (0x1u << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */
+#define ADC_CHDR_CH15 (0x1u << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */
+/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */
+#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */
+#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */
+#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */
+#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */
+#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */
+#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */
+#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */
+#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */
+#define ADC_CHSR_CH8 (0x1u << 8) /**< \brief (ADC_CHSR) Channel 8 Status */
+#define ADC_CHSR_CH9 (0x1u << 9) /**< \brief (ADC_CHSR) Channel 9 Status */
+#define ADC_CHSR_CH10 (0x1u << 10) /**< \brief (ADC_CHSR) Channel 10 Status */
+#define ADC_CHSR_CH11 (0x1u << 11) /**< \brief (ADC_CHSR) Channel 11 Status */
+#define ADC_CHSR_CH12 (0x1u << 12) /**< \brief (ADC_CHSR) Channel 12 Status */
+#define ADC_CHSR_CH13 (0x1u << 13) /**< \brief (ADC_CHSR) Channel 13 Status */
+#define ADC_CHSR_CH14 (0x1u << 14) /**< \brief (ADC_CHSR) Channel 14 Status */
+#define ADC_CHSR_CH15 (0x1u << 15) /**< \brief (ADC_CHSR) Channel 15 Status */
+/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */
+#define ADC_LCDR_LDATA_Pos 0
+#define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */
+#define ADC_LCDR_CHNB_Pos 12
+#define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) /**< \brief (ADC_LCDR) Channel Number */
+/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */
+#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */
+#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */
+#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */
+#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */
+#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */
+#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */
+#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */
+#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */
+#define ADC_IER_EOC8 (0x1u << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */
+#define ADC_IER_EOC9 (0x1u << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */
+#define ADC_IER_EOC10 (0x1u << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */
+#define ADC_IER_EOC11 (0x1u << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */
+#define ADC_IER_EOC12 (0x1u << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */
+#define ADC_IER_EOC13 (0x1u << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */
+#define ADC_IER_EOC14 (0x1u << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */
+#define ADC_IER_EOC15 (0x1u << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */
+#define ADC_IER_EOCAL (0x1u << 23) /**< \brief (ADC_IER) End of Calibration Sequence */
+#define ADC_IER_DRDY (0x1u << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */
+#define ADC_IER_GOVRE (0x1u << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */
+#define ADC_IER_COMPE (0x1u << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */
+#define ADC_IER_ENDRX (0x1u << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */
+#define ADC_IER_RXBUFF (0x1u << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */
+/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */
+#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */
+#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */
+#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */
+#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */
+#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */
+#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */
+#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */
+#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */
+#define ADC_IDR_EOC8 (0x1u << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */
+#define ADC_IDR_EOC9 (0x1u << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */
+#define ADC_IDR_EOC10 (0x1u << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */
+#define ADC_IDR_EOC11 (0x1u << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */
+#define ADC_IDR_EOC12 (0x1u << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */
+#define ADC_IDR_EOC13 (0x1u << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */
+#define ADC_IDR_EOC14 (0x1u << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */
+#define ADC_IDR_EOC15 (0x1u << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */
+#define ADC_IDR_EOCAL (0x1u << 23) /**< \brief (ADC_IDR) End of Calibration Sequence */
+#define ADC_IDR_DRDY (0x1u << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */
+#define ADC_IDR_GOVRE (0x1u << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */
+#define ADC_IDR_COMPE (0x1u << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */
+#define ADC_IDR_ENDRX (0x1u << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */
+#define ADC_IDR_RXBUFF (0x1u << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */
+/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */
+#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */
+#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */
+#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */
+#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */
+#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */
+#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */
+#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */
+#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */
+#define ADC_IMR_EOC8 (0x1u << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */
+#define ADC_IMR_EOC9 (0x1u << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */
+#define ADC_IMR_EOC10 (0x1u << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */
+#define ADC_IMR_EOC11 (0x1u << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */
+#define ADC_IMR_EOC12 (0x1u << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */
+#define ADC_IMR_EOC13 (0x1u << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */
+#define ADC_IMR_EOC14 (0x1u << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */
+#define ADC_IMR_EOC15 (0x1u << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */
+#define ADC_IMR_EOCAL (0x1u << 23) /**< \brief (ADC_IMR) End of Calibration Sequence */
+#define ADC_IMR_DRDY (0x1u << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */
+#define ADC_IMR_GOVRE (0x1u << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */
+#define ADC_IMR_COMPE (0x1u << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */
+#define ADC_IMR_ENDRX (0x1u << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */
+#define ADC_IMR_RXBUFF (0x1u << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */
+/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */
+#define ADC_ISR_EOC0 (0x1u << 0) /**< \brief (ADC_ISR) End of Conversion 0 */
+#define ADC_ISR_EOC1 (0x1u << 1) /**< \brief (ADC_ISR) End of Conversion 1 */
+#define ADC_ISR_EOC2 (0x1u << 2) /**< \brief (ADC_ISR) End of Conversion 2 */
+#define ADC_ISR_EOC3 (0x1u << 3) /**< \brief (ADC_ISR) End of Conversion 3 */
+#define ADC_ISR_EOC4 (0x1u << 4) /**< \brief (ADC_ISR) End of Conversion 4 */
+#define ADC_ISR_EOC5 (0x1u << 5) /**< \brief (ADC_ISR) End of Conversion 5 */
+#define ADC_ISR_EOC6 (0x1u << 6) /**< \brief (ADC_ISR) End of Conversion 6 */
+#define ADC_ISR_EOC7 (0x1u << 7) /**< \brief (ADC_ISR) End of Conversion 7 */
+#define ADC_ISR_EOC8 (0x1u << 8) /**< \brief (ADC_ISR) End of Conversion 8 */
+#define ADC_ISR_EOC9 (0x1u << 9) /**< \brief (ADC_ISR) End of Conversion 9 */
+#define ADC_ISR_EOC10 (0x1u << 10) /**< \brief (ADC_ISR) End of Conversion 10 */
+#define ADC_ISR_EOC11 (0x1u << 11) /**< \brief (ADC_ISR) End of Conversion 11 */
+#define ADC_ISR_EOC12 (0x1u << 12) /**< \brief (ADC_ISR) End of Conversion 12 */
+#define ADC_ISR_EOC13 (0x1u << 13) /**< \brief (ADC_ISR) End of Conversion 13 */
+#define ADC_ISR_EOC14 (0x1u << 14) /**< \brief (ADC_ISR) End of Conversion 14 */
+#define ADC_ISR_EOC15 (0x1u << 15) /**< \brief (ADC_ISR) End of Conversion 15 */
+#define ADC_ISR_EOCAL (0x1u << 23) /**< \brief (ADC_ISR) End of Calibration Sequence */
+#define ADC_ISR_DRDY (0x1u << 24) /**< \brief (ADC_ISR) Data Ready */
+#define ADC_ISR_GOVRE (0x1u << 25) /**< \brief (ADC_ISR) General Overrun Error */
+#define ADC_ISR_COMPE (0x1u << 26) /**< \brief (ADC_ISR) Comparison Error */
+#define ADC_ISR_ENDRX (0x1u << 27) /**< \brief (ADC_ISR) End of RX Buffer */
+#define ADC_ISR_RXBUFF (0x1u << 28) /**< \brief (ADC_ISR) RX Buffer Full */
+/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */
+#define ADC_OVER_OVRE0 (0x1u << 0) /**< \brief (ADC_OVER) Overrun Error 0 */
+#define ADC_OVER_OVRE1 (0x1u << 1) /**< \brief (ADC_OVER) Overrun Error 1 */
+#define ADC_OVER_OVRE2 (0x1u << 2) /**< \brief (ADC_OVER) Overrun Error 2 */
+#define ADC_OVER_OVRE3 (0x1u << 3) /**< \brief (ADC_OVER) Overrun Error 3 */
+#define ADC_OVER_OVRE4 (0x1u << 4) /**< \brief (ADC_OVER) Overrun Error 4 */
+#define ADC_OVER_OVRE5 (0x1u << 5) /**< \brief (ADC_OVER) Overrun Error 5 */
+#define ADC_OVER_OVRE6 (0x1u << 6) /**< \brief (ADC_OVER) Overrun Error 6 */
+#define ADC_OVER_OVRE7 (0x1u << 7) /**< \brief (ADC_OVER) Overrun Error 7 */
+#define ADC_OVER_OVRE8 (0x1u << 8) /**< \brief (ADC_OVER) Overrun Error 8 */
+#define ADC_OVER_OVRE9 (0x1u << 9) /**< \brief (ADC_OVER) Overrun Error 9 */
+#define ADC_OVER_OVRE10 (0x1u << 10) /**< \brief (ADC_OVER) Overrun Error 10 */
+#define ADC_OVER_OVRE11 (0x1u << 11) /**< \brief (ADC_OVER) Overrun Error 11 */
+#define ADC_OVER_OVRE12 (0x1u << 12) /**< \brief (ADC_OVER) Overrun Error 12 */
+#define ADC_OVER_OVRE13 (0x1u << 13) /**< \brief (ADC_OVER) Overrun Error 13 */
+#define ADC_OVER_OVRE14 (0x1u << 14) /**< \brief (ADC_OVER) Overrun Error 14 */
+#define ADC_OVER_OVRE15 (0x1u << 15) /**< \brief (ADC_OVER) Overrun Error 15 */
+/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */
+#define ADC_EMR_CMPMODE_Pos 0
+#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /**< \brief (ADC_EMR) Comparison Mode */
+#define   ADC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */
+#define   ADC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */
+#define   ADC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is in the comparison window. */
+#define   ADC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is out of the comparison window. */
+#define ADC_EMR_CMPSEL_Pos 4
+#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /**< \brief (ADC_EMR) Comparison Selected Channel */
+#define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos)))
+#define ADC_EMR_CMPALL (0x1u << 9) /**< \brief (ADC_EMR) Compare All Channels */
+#define ADC_EMR_CMPFILTER_Pos 12
+#define ADC_EMR_CMPFILTER_Msk (0x3u << ADC_EMR_CMPFILTER_Pos) /**< \brief (ADC_EMR) Compare Event Filtering */
+#define ADC_EMR_CMPFILTER(value) ((ADC_EMR_CMPFILTER_Msk & ((value) << ADC_EMR_CMPFILTER_Pos)))
+#define ADC_EMR_TAG (0x1u << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */
+/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */
+#define ADC_CWR_LOWTHRES_Pos 0
+#define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) /**< \brief (ADC_CWR) Low Threshold */
+#define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos)))
+#define ADC_CWR_HIGHTHRES_Pos 16
+#define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) /**< \brief (ADC_CWR) High Threshold */
+#define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos)))
+/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */
+#define ADC_CGR_GAIN0_Pos 0
+#define ADC_CGR_GAIN0_Msk (0x3u << ADC_CGR_GAIN0_Pos) /**< \brief (ADC_CGR) Gain for channel 0 */
+#define ADC_CGR_GAIN0(value) ((ADC_CGR_GAIN0_Msk & ((value) << ADC_CGR_GAIN0_Pos)))
+#define ADC_CGR_GAIN1_Pos 2
+#define ADC_CGR_GAIN1_Msk (0x3u << ADC_CGR_GAIN1_Pos) /**< \brief (ADC_CGR) Gain for channel 1 */
+#define ADC_CGR_GAIN1(value) ((ADC_CGR_GAIN1_Msk & ((value) << ADC_CGR_GAIN1_Pos)))
+#define ADC_CGR_GAIN2_Pos 4
+#define ADC_CGR_GAIN2_Msk (0x3u << ADC_CGR_GAIN2_Pos) /**< \brief (ADC_CGR) Gain for channel 2 */
+#define ADC_CGR_GAIN2(value) ((ADC_CGR_GAIN2_Msk & ((value) << ADC_CGR_GAIN2_Pos)))
+#define ADC_CGR_GAIN3_Pos 6
+#define ADC_CGR_GAIN3_Msk (0x3u << ADC_CGR_GAIN3_Pos) /**< \brief (ADC_CGR) Gain for channel 3 */
+#define ADC_CGR_GAIN3(value) ((ADC_CGR_GAIN3_Msk & ((value) << ADC_CGR_GAIN3_Pos)))
+#define ADC_CGR_GAIN4_Pos 8
+#define ADC_CGR_GAIN4_Msk (0x3u << ADC_CGR_GAIN4_Pos) /**< \brief (ADC_CGR) Gain for channel 4 */
+#define ADC_CGR_GAIN4(value) ((ADC_CGR_GAIN4_Msk & ((value) << ADC_CGR_GAIN4_Pos)))
+#define ADC_CGR_GAIN5_Pos 10
+#define ADC_CGR_GAIN5_Msk (0x3u << ADC_CGR_GAIN5_Pos) /**< \brief (ADC_CGR) Gain for channel 5 */
+#define ADC_CGR_GAIN5(value) ((ADC_CGR_GAIN5_Msk & ((value) << ADC_CGR_GAIN5_Pos)))
+#define ADC_CGR_GAIN6_Pos 12
+#define ADC_CGR_GAIN6_Msk (0x3u << ADC_CGR_GAIN6_Pos) /**< \brief (ADC_CGR) Gain for channel 6 */
+#define ADC_CGR_GAIN6(value) ((ADC_CGR_GAIN6_Msk & ((value) << ADC_CGR_GAIN6_Pos)))
+#define ADC_CGR_GAIN7_Pos 14
+#define ADC_CGR_GAIN7_Msk (0x3u << ADC_CGR_GAIN7_Pos) /**< \brief (ADC_CGR) Gain for channel 7 */
+#define ADC_CGR_GAIN7(value) ((ADC_CGR_GAIN7_Msk & ((value) << ADC_CGR_GAIN7_Pos)))
+#define ADC_CGR_GAIN8_Pos 16
+#define ADC_CGR_GAIN8_Msk (0x3u << ADC_CGR_GAIN8_Pos) /**< \brief (ADC_CGR) Gain for channel 8 */
+#define ADC_CGR_GAIN8(value) ((ADC_CGR_GAIN8_Msk & ((value) << ADC_CGR_GAIN8_Pos)))
+#define ADC_CGR_GAIN9_Pos 18
+#define ADC_CGR_GAIN9_Msk (0x3u << ADC_CGR_GAIN9_Pos) /**< \brief (ADC_CGR) Gain for channel 9 */
+#define ADC_CGR_GAIN9(value) ((ADC_CGR_GAIN9_Msk & ((value) << ADC_CGR_GAIN9_Pos)))
+#define ADC_CGR_GAIN10_Pos 20
+#define ADC_CGR_GAIN10_Msk (0x3u << ADC_CGR_GAIN10_Pos) /**< \brief (ADC_CGR) Gain for channel 10 */
+#define ADC_CGR_GAIN10(value) ((ADC_CGR_GAIN10_Msk & ((value) << ADC_CGR_GAIN10_Pos)))
+#define ADC_CGR_GAIN11_Pos 22
+#define ADC_CGR_GAIN11_Msk (0x3u << ADC_CGR_GAIN11_Pos) /**< \brief (ADC_CGR) Gain for channel 11 */
+#define ADC_CGR_GAIN11(value) ((ADC_CGR_GAIN11_Msk & ((value) << ADC_CGR_GAIN11_Pos)))
+#define ADC_CGR_GAIN12_Pos 24
+#define ADC_CGR_GAIN12_Msk (0x3u << ADC_CGR_GAIN12_Pos) /**< \brief (ADC_CGR) Gain for channel 12 */
+#define ADC_CGR_GAIN12(value) ((ADC_CGR_GAIN12_Msk & ((value) << ADC_CGR_GAIN12_Pos)))
+#define ADC_CGR_GAIN13_Pos 26
+#define ADC_CGR_GAIN13_Msk (0x3u << ADC_CGR_GAIN13_Pos) /**< \brief (ADC_CGR) Gain for channel 13 */
+#define ADC_CGR_GAIN13(value) ((ADC_CGR_GAIN13_Msk & ((value) << ADC_CGR_GAIN13_Pos)))
+#define ADC_CGR_GAIN14_Pos 28
+#define ADC_CGR_GAIN14_Msk (0x3u << ADC_CGR_GAIN14_Pos) /**< \brief (ADC_CGR) Gain for channel 14 */
+#define ADC_CGR_GAIN14(value) ((ADC_CGR_GAIN14_Msk & ((value) << ADC_CGR_GAIN14_Pos)))
+#define ADC_CGR_GAIN15_Pos 30
+#define ADC_CGR_GAIN15_Msk (0x3u << ADC_CGR_GAIN15_Pos) /**< \brief (ADC_CGR) Gain for channel 15 */
+#define ADC_CGR_GAIN15(value) ((ADC_CGR_GAIN15_Msk & ((value) << ADC_CGR_GAIN15_Pos)))
+/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */
+#define ADC_COR_OFF0 (0x1u << 0) /**< \brief (ADC_COR) Offset for channel 0 */
+#define ADC_COR_OFF1 (0x1u << 1) /**< \brief (ADC_COR) Offset for channel 1 */
+#define ADC_COR_OFF2 (0x1u << 2) /**< \brief (ADC_COR) Offset for channel 2 */
+#define ADC_COR_OFF3 (0x1u << 3) /**< \brief (ADC_COR) Offset for channel 3 */
+#define ADC_COR_OFF4 (0x1u << 4) /**< \brief (ADC_COR) Offset for channel 4 */
+#define ADC_COR_OFF5 (0x1u << 5) /**< \brief (ADC_COR) Offset for channel 5 */
+#define ADC_COR_OFF6 (0x1u << 6) /**< \brief (ADC_COR) Offset for channel 6 */
+#define ADC_COR_OFF7 (0x1u << 7) /**< \brief (ADC_COR) Offset for channel 7 */
+#define ADC_COR_OFF8 (0x1u << 8) /**< \brief (ADC_COR) Offset for channel 8 */
+#define ADC_COR_OFF9 (0x1u << 9) /**< \brief (ADC_COR) Offset for channel 9 */
+#define ADC_COR_OFF10 (0x1u << 10) /**< \brief (ADC_COR) Offset for channel 10 */
+#define ADC_COR_OFF11 (0x1u << 11) /**< \brief (ADC_COR) Offset for channel 11 */
+#define ADC_COR_OFF12 (0x1u << 12) /**< \brief (ADC_COR) Offset for channel 12 */
+#define ADC_COR_OFF13 (0x1u << 13) /**< \brief (ADC_COR) Offset for channel 13 */
+#define ADC_COR_OFF14 (0x1u << 14) /**< \brief (ADC_COR) Offset for channel 14 */
+#define ADC_COR_OFF15 (0x1u << 15) /**< \brief (ADC_COR) Offset for channel 15 */
+#define ADC_COR_DIFF0 (0x1u << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */
+#define ADC_COR_DIFF1 (0x1u << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */
+#define ADC_COR_DIFF2 (0x1u << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */
+#define ADC_COR_DIFF3 (0x1u << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */
+#define ADC_COR_DIFF4 (0x1u << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */
+#define ADC_COR_DIFF5 (0x1u << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */
+#define ADC_COR_DIFF6 (0x1u << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */
+#define ADC_COR_DIFF7 (0x1u << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */
+#define ADC_COR_DIFF8 (0x1u << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */
+#define ADC_COR_DIFF9 (0x1u << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */
+#define ADC_COR_DIFF10 (0x1u << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */
+#define ADC_COR_DIFF11 (0x1u << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */
+#define ADC_COR_DIFF12 (0x1u << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */
+#define ADC_COR_DIFF13 (0x1u << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */
+#define ADC_COR_DIFF14 (0x1u << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */
+#define ADC_COR_DIFF15 (0x1u << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */
+/* -------- ADC_CDR[15] : (ADC Offset: 0x50) Channel Data Register -------- */
+#define ADC_CDR_DATA_Pos 0
+#define ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[15]) Converted Data */
+/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */
+#define ADC_ACR_TSON (0x1u << 4) /**< \brief (ADC_ACR) Temperature Sensor On */
+#define ADC_ACR_IBCTL_Pos 8
+#define ADC_ACR_IBCTL_Msk (0x3u << ADC_ACR_IBCTL_Pos) /**< \brief (ADC_ACR) ADC Bias Current Control */
+#define ADC_ACR_IBCTL(value) ((ADC_ACR_IBCTL_Msk & ((value) << ADC_ACR_IBCTL_Pos)))
+/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */
+#define ADC_WPMR_WPEN (0x1u << 0) /**< \brief (ADC_WPMR) Write Protect Enable */
+#define ADC_WPMR_WPKEY_Pos 8
+#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /**< \brief (ADC_WPMR) Write Protect KEY */
+#define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos)))
+/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */
+#define ADC_WPSR_WPVS (0x1u << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */
+#define ADC_WPSR_WPVSRC_Pos 8
+#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /**< \brief (ADC_WPSR) Write Protect Violation Source */
+/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */
+#define ADC_RPR_RXPTR_Pos 0
+#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */
+#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos)))
+/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */
+#define ADC_RCR_RXCTR_Pos 0
+#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */
+#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos)))
+/* -------- ADC_TPR : (ADC Offset: 0x108) Transmit Pointer Register -------- */
+#define ADC_TPR_TXPTR_Pos 0
+#define ADC_TPR_TXPTR_Msk (0xffffffffu << ADC_TPR_TXPTR_Pos) /**< \brief (ADC_TPR) Transmit Counter Register */
+#define ADC_TPR_TXPTR(value) ((ADC_TPR_TXPTR_Msk & ((value) << ADC_TPR_TXPTR_Pos)))
+/* -------- ADC_TCR : (ADC Offset: 0x10C) Transmit Counter Register -------- */
+#define ADC_TCR_TXCTR_Pos 0
+#define ADC_TCR_TXCTR_Msk (0xffffu << ADC_TCR_TXCTR_Pos) /**< \brief (ADC_TCR) Transmit Counter Register */
+#define ADC_TCR_TXCTR(value) ((ADC_TCR_TXCTR_Msk & ((value) << ADC_TCR_TXCTR_Pos)))
+/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */
+#define ADC_RNPR_RXNPTR_Pos 0
+#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */
+#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos)))
+/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */
+#define ADC_RNCR_RXNCTR_Pos 0
+#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */
+#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos)))
+/* -------- ADC_TNPR : (ADC Offset: 0x118) Transmit Next Pointer Register -------- */
+#define ADC_TNPR_TXNPTR_Pos 0
+#define ADC_TNPR_TXNPTR_Msk (0xffffffffu << ADC_TNPR_TXNPTR_Pos) /**< \brief (ADC_TNPR) Transmit Next Pointer */
+#define ADC_TNPR_TXNPTR(value) ((ADC_TNPR_TXNPTR_Msk & ((value) << ADC_TNPR_TXNPTR_Pos)))
+/* -------- ADC_TNCR : (ADC Offset: 0x11C) Transmit Next Counter Register -------- */
+#define ADC_TNCR_TXNCTR_Pos 0
+#define ADC_TNCR_TXNCTR_Msk (0xffffu << ADC_TNCR_TXNCTR_Pos) /**< \brief (ADC_TNCR) Transmit Counter Next */
+#define ADC_TNCR_TXNCTR(value) ((ADC_TNCR_TXNCTR_Msk & ((value) << ADC_TNCR_TXNCTR_Pos)))
+/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */
+#define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */
+#define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */
+#define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */
+#define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */
+/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */
+#define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */
+#define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_ADC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_chipid.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_chipid.h
new file mode 100644
index 000000000..91839ba4f
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_chipid.h
@@ -0,0 +1,159 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_CHIPID_COMPONENT_
+#define _SAM3S8_CHIPID_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Chip Identifier */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_CHIPID Chip Identifier */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Chipid hardware registers */
+typedef struct {
+  RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */
+  RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */
+} Chipid;
+#endif /* __ASSEMBLY__ */
+/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */
+#define CHIPID_CIDR_VERSION_Pos 0
+#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */
+#define CHIPID_CIDR_EPROC_Pos 5
+#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */
+#define   CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */
+#define   CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */
+#define   CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */
+#define   CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */
+#define   CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */
+#define   CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */
+#define   CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */
+#define CHIPID_CIDR_NVPSIZ_Pos 8
+#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */
+#define   CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */
+#define   CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define   CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define   CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_NVPSIZ2_Pos 12
+#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */
+#define   CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */
+#define   CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_SRAMSIZ_Pos 16
+#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */
+#define   CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_1K (0x1u << 16) /**< \brief (CHIPID_CIDR) 1K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define CHIPID_CIDR_ARCH_Pos 20
+#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */
+#define   CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */
+#define   CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */
+#define   CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */
+#define   CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */
+#define   CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */
+#define   CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */
+#define   CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */
+#define   CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */
+#define   CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */
+#define   CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM4AxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM4XxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM4XxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxG Series (208/217-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM4XxG Series (208/217-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM3SxASeries (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM4SxA Series (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM3SxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM4SxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM3SxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM4SxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */
+#define   CHIPID_CIDR_ARCH_SAM3NxA (0x93u << 20) /**< \brief (CHIPID_CIDR) SAM3NxA Series (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3NxB (0x94u << 20) /**< \brief (CHIPID_CIDR) SAM3NxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3NxC (0x95u << 20) /**< \brief (CHIPID_CIDR) SAM3NxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */
+#define   CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */
+#define CHIPID_CIDR_NVPTYP_Pos 28
+#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */
+#define   CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */
+#define   CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */
+#define   CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */
+#define   CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size      NVPSIZ2 is Flash size */
+#define   CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */
+#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */
+/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */
+#define CHIPID_EXID_EXID_Pos 0
+#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_CHIPID_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_crccu.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_crccu.h
new file mode 100644
index 000000000..ad2e79be2
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_crccu.h
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_CRCCU_COMPONENT_
+#define _SAM3S8_CRCCU_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_CRCCU Cyclic Redundancy Check Calculation Unit */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Crccu hardware registers */
+typedef struct {
+  RwReg CRCCU_DSCR;    /**< \brief (Crccu Offset: 0x00000000) CRCCU Descriptor Base Register */
+  RoReg Reserved1[1];
+  WoReg CRCCU_DMA_EN;  /**< \brief (Crccu Offset: 0x00000008) CRCCU DMA Enable Register */
+  WoReg CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x0000000C) CRCCU DMA Disable Register */
+  RoReg CRCCU_DMA_SR;  /**< \brief (Crccu Offset: 0x00000010) CRCCU DMA Status Register */
+  WoReg CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x00000014) CRCCU DMA Interrupt Enable Register */
+  WoReg CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x00000018) CRCCU DMA Interrupt Disable Register */
+  RoReg CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register */
+  RoReg CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x00000020) CRCCU DMA Interrupt Status Register */
+  RoReg Reserved2[4];
+  WoReg CRCCU_CR;      /**< \brief (Crccu Offset: 0x00000034) CRCCU Control Register */
+  RwReg CRCCU_MR;      /**< \brief (Crccu Offset: 0x00000038) CRCCU Mode Register */
+  RoReg CRCCU_SR;      /**< \brief (Crccu Offset: 0x0000003C) CRCCU Status Register */
+  WoReg CRCCU_IER;     /**< \brief (Crccu Offset: 0x00000040) CRCCU Interrupt Enable Register */
+  WoReg CRCCU_IDR;     /**< \brief (Crccu Offset: 0x00000044) CRCCU Interrupt Disable Register */
+  RoReg CRCCU_IMR;     /**< \brief (Crccu Offset: 0x00000048) CRCCU Interrupt Mask Register */
+  RoReg CRCCU_ISR;     /**< \brief (Crccu Offset: 0x0000004C) CRCCU Interrupt Status Register */
+} Crccu;
+#endif /* __ASSEMBLY__ */
+/* -------- CRCCU_DSCR : (CRCCU Offset: 0x00000000) CRCCU Descriptor Base Register -------- */
+#define CRCCU_DSCR_DSCR_Pos 9
+#define CRCCU_DSCR_DSCR_Msk (0x7fffffu << CRCCU_DSCR_DSCR_Pos) /**< \brief (CRCCU_DSCR) Descriptor Base Address */
+#define CRCCU_DSCR_DSCR(value) ((CRCCU_DSCR_DSCR_Msk & ((value) << CRCCU_DSCR_DSCR_Pos)))
+/* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x00000008) CRCCU DMA Enable Register -------- */
+#define CRCCU_DMA_EN_DMAEN (0x1u << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable Register */
+/* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x0000000C) CRCCU DMA Disable Register -------- */
+#define CRCCU_DMA_DIS_DMADIS (0x1u << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable Register */
+/* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x00000010) CRCCU DMA Status Register -------- */
+#define CRCCU_DMA_SR_DMASR (0x1u << 0) /**< \brief (CRCCU_DMA_SR) DMA Status Register */
+/* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x00000014) CRCCU DMA Interrupt Enable Register -------- */
+#define CRCCU_DMA_IER_DMAIER (0x1u << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable register */
+/* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x00000018) CRCCU DMA Interrupt Disable Register -------- */
+#define CRCCU_DMA_IDR_DMAIDR (0x1u << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable register */
+/* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register -------- */
+#define CRCCU_DMA_IMR_DMAIMR (0x1u << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask Register */
+/* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x00000020) CRCCU DMA Interrupt Status Register -------- */
+#define CRCCU_DMA_ISR_DMAISR (0x1u << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status register */
+/* -------- CRCCU_CR : (CRCCU Offset: 0x00000034) CRCCU Control Register -------- */
+#define CRCCU_CR_RESET (0x1u << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */
+/* -------- CRCCU_MR : (CRCCU Offset: 0x00000038) CRCCU Mode Register -------- */
+#define CRCCU_MR_ENABLE (0x1u << 0) /**< \brief (CRCCU_MR) CRC Enable */
+#define CRCCU_MR_COMPARE (0x1u << 1) /**< \brief (CRCCU_MR) CRC Compare */
+#define CRCCU_MR_PTYPE_Pos 2
+#define CRCCU_MR_PTYPE_Msk (0x3u << CRCCU_MR_PTYPE_Pos) /**< \brief (CRCCU_MR) Primitive Polynomial */
+#define   CRCCU_MR_PTYPE_CCITT8023 (0x0u << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */
+#define   CRCCU_MR_PTYPE_CASTAGNOLI (0x1u << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */
+#define   CRCCU_MR_PTYPE_CCITT16 (0x2u << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */
+#define CRCCU_MR_DIVIDER_Pos 4
+#define CRCCU_MR_DIVIDER_Msk (0xfu << CRCCU_MR_DIVIDER_Pos) /**< \brief (CRCCU_MR) Request Divider */
+#define CRCCU_MR_DIVIDER(value) ((CRCCU_MR_DIVIDER_Msk & ((value) << CRCCU_MR_DIVIDER_Pos)))
+/* -------- CRCCU_SR : (CRCCU Offset: 0x0000003C) CRCCU Status Register -------- */
+#define CRCCU_SR_CRC_Pos 0
+#define CRCCU_SR_CRC_Msk (0xffffffffu << CRCCU_SR_CRC_Pos) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */
+/* -------- CRCCU_IER : (CRCCU Offset: 0x00000040) CRCCU Interrupt Enable Register -------- */
+#define CRCCU_IER_ERRIER (0x1u << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */
+/* -------- CRCCU_IDR : (CRCCU Offset: 0x00000044) CRCCU Interrupt Disable Register -------- */
+#define CRCCU_IDR_ERRIDR (0x1u << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */
+/* -------- CRCCU_IMR : (CRCCU Offset: 0x00000048) CRCCU Interrupt Mask Register -------- */
+#define CRCCU_IMR_ERRIMR (0x1u << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */
+/* -------- CRCCU_ISR : (CRCCU Offset: 0x0000004C) CRCCU Interrupt Status Register -------- */
+#define CRCCU_ISR_ERRISR (0x1u << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_CRCCU_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_dacc.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_dacc.h
new file mode 100644
index 000000000..e82e25965
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_dacc.h
@@ -0,0 +1,227 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_DACC_COMPONENT_
+#define _SAM3S8_DACC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_DACC Digital-to-Analog Converter Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Dacc hardware registers */
+typedef struct {
+  WoReg DACC_CR;       /**< \brief (Dacc Offset: 0x00) Control Register */
+  RwReg DACC_MR;       /**< \brief (Dacc Offset: 0x04) Mode Register */
+  RoReg Reserved1[2];
+  WoReg DACC_CHER;     /**< \brief (Dacc Offset: 0x10) Channel Enable Register */
+  WoReg DACC_CHDR;     /**< \brief (Dacc Offset: 0x14) Channel Disable Register */
+  RoReg DACC_CHSR;     /**< \brief (Dacc Offset: 0x18) Channel Status Register */
+  RoReg Reserved2[1];
+  WoReg DACC_CDR;      /**< \brief (Dacc Offset: 0x20) Conversion Data Register */
+  WoReg DACC_IER;      /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */
+  WoReg DACC_IDR;      /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */
+  RoReg DACC_IMR;      /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */
+  RoReg DACC_ISR;      /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */
+  RoReg Reserved3[24];
+  RwReg DACC_ACR;      /**< \brief (Dacc Offset: 0x94) Analog Current Register */
+  RoReg Reserved4[19];
+  RwReg DACC_WPMR;     /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */
+  RoReg DACC_WPSR;     /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */
+  RoReg Reserved5[5];
+  RwReg DACC_RPR;      /**< \brief (Dacc Offset: 0x100) Receive Pointer Register */
+  RwReg DACC_RCR;      /**< \brief (Dacc Offset: 0x104) Receive Counter Register */
+  RwReg DACC_TPR;      /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */
+  RwReg DACC_TCR;      /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */
+  RwReg DACC_RNPR;     /**< \brief (Dacc Offset: 0x110) Receive Next Pointer Register */
+  RwReg DACC_RNCR;     /**< \brief (Dacc Offset: 0x114) Receive Next Counter Register */
+  RwReg DACC_TNPR;     /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */
+  RwReg DACC_TNCR;     /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */
+  WoReg DACC_PTCR;     /**< \brief (Dacc Offset: 0x120) Transfer Control Register */
+  RoReg DACC_PTSR;     /**< \brief (Dacc Offset: 0x124) Transfer Status Register */
+} Dacc;
+#endif /* __ASSEMBLY__ */
+/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */
+#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */
+/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */
+#define DACC_MR_TRGEN (0x1u << 0) /**< \brief (DACC_MR) Trigger Enable */
+#define   DACC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (DACC_MR) External trigger mode disabled. DACC in free running mode. */
+#define   DACC_MR_TRGEN_EN (0x1u << 0) /**< \brief (DACC_MR) External trigger mode enabled. */
+#define DACC_MR_TRGSEL_Pos 1
+#define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) /**< \brief (DACC_MR) Trigger Selection */
+#define DACC_MR_TRGSEL(value) ((DACC_MR_TRGSEL_Msk & ((value) << DACC_MR_TRGSEL_Pos)))
+#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */
+#define   DACC_MR_WORD_HALF (0x0u << 4) /**< \brief (DACC_MR) Half-Word transfer */
+#define   DACC_MR_WORD_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */
+#define DACC_MR_SLEEP (0x1u << 5) /**< \brief (DACC_MR) Sleep Mode */
+#define DACC_MR_FASTWKUP (0x1u << 6) /**< \brief (DACC_MR) Fast Wake up Mode */
+#define DACC_MR_REFRESH_Pos 8
+#define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */
+#define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos)))
+#define DACC_MR_USER_SEL_Pos 16
+#define DACC_MR_USER_SEL_Msk (0x3u << DACC_MR_USER_SEL_Pos) /**< \brief (DACC_MR) User Channel Selection */
+#define   DACC_MR_USER_SEL_CHANNEL0 (0x0u << 16) /**< \brief (DACC_MR) Channel 0 */
+#define   DACC_MR_USER_SEL_CHANNEL1 (0x1u << 16) /**< \brief (DACC_MR) Channel 1 */
+#define DACC_MR_TAG (0x1u << 20) /**< \brief (DACC_MR) Tag Selection Mode */
+#define   DACC_MR_TAG_DIS (0x0u << 20) /**< \brief (DACC_MR) Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. */
+#define   DACC_MR_TAG_EN (0x1u << 20) /**< \brief (DACC_MR) Tag selection mode enabled */
+#define DACC_MR_MAXS (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode */
+#define DACC_MR_STARTUP_Pos 24
+#define DACC_MR_STARTUP_Msk (0x3fu << DACC_MR_STARTUP_Pos) /**< \brief (DACC_MR) Startup Time Selection */
+#define   DACC_MR_STARTUP_0 (0x0u << 24) /**< \brief (DACC_MR) 0 periods of DACClock */
+#define   DACC_MR_STARTUP_8 (0x1u << 24) /**< \brief (DACC_MR) 8 periods of DACClock */
+#define   DACC_MR_STARTUP_16 (0x2u << 24) /**< \brief (DACC_MR) 16 periods of DACClock */
+#define   DACC_MR_STARTUP_24 (0x3u << 24) /**< \brief (DACC_MR) 24 periods of DACClock */
+#define   DACC_MR_STARTUP_64 (0x4u << 24) /**< \brief (DACC_MR) 64 periods of DACClock */
+#define   DACC_MR_STARTUP_80 (0x5u << 24) /**< \brief (DACC_MR) 80 periods of DACClock */
+#define   DACC_MR_STARTUP_96 (0x6u << 24) /**< \brief (DACC_MR) 96 periods of DACClock */
+#define   DACC_MR_STARTUP_112 (0x7u << 24) /**< \brief (DACC_MR) 112 periods of DACClock */
+#define   DACC_MR_STARTUP_512 (0x8u << 24) /**< \brief (DACC_MR) 512 periods of DACClock */
+#define   DACC_MR_STARTUP_576 (0x9u << 24) /**< \brief (DACC_MR) 576 periods of DACClock */
+#define   DACC_MR_STARTUP_640 (0xAu << 24) /**< \brief (DACC_MR) 640 periods of DACClock */
+#define   DACC_MR_STARTUP_704 (0xBu << 24) /**< \brief (DACC_MR) 704 periods of DACClock */
+#define   DACC_MR_STARTUP_768 (0xCu << 24) /**< \brief (DACC_MR) 768 periods of DACClock */
+#define   DACC_MR_STARTUP_832 (0xDu << 24) /**< \brief (DACC_MR) 832 periods of DACClock */
+#define   DACC_MR_STARTUP_896 (0xEu << 24) /**< \brief (DACC_MR) 896 periods of DACClock */
+#define   DACC_MR_STARTUP_960 (0xFu << 24) /**< \brief (DACC_MR) 960 periods of DACClock */
+#define   DACC_MR_STARTUP_1024 (0x10u << 24) /**< \brief (DACC_MR) 1024 periods of DACClock */
+#define   DACC_MR_STARTUP_1088 (0x11u << 24) /**< \brief (DACC_MR) 1088 periods of DACClock */
+#define   DACC_MR_STARTUP_1152 (0x12u << 24) /**< \brief (DACC_MR) 1152 periods of DACClock */
+#define   DACC_MR_STARTUP_1216 (0x13u << 24) /**< \brief (DACC_MR) 1216 periods of DACClock */
+#define   DACC_MR_STARTUP_1280 (0x14u << 24) /**< \brief (DACC_MR) 1280 periods of DACClock */
+#define   DACC_MR_STARTUP_1344 (0x15u << 24) /**< \brief (DACC_MR) 1344 periods of DACClock */
+#define   DACC_MR_STARTUP_1408 (0x16u << 24) /**< \brief (DACC_MR) 1408 periods of DACClock */
+#define   DACC_MR_STARTUP_1472 (0x17u << 24) /**< \brief (DACC_MR) 1472 periods of DACClock */
+#define   DACC_MR_STARTUP_1536 (0x18u << 24) /**< \brief (DACC_MR) 1536 periods of DACClock */
+#define   DACC_MR_STARTUP_1600 (0x19u << 24) /**< \brief (DACC_MR) 1600 periods of DACClock */
+#define   DACC_MR_STARTUP_1664 (0x1Au << 24) /**< \brief (DACC_MR) 1664 periods of DACClock */
+#define   DACC_MR_STARTUP_1728 (0x1Bu << 24) /**< \brief (DACC_MR) 1728 periods of DACClock */
+#define   DACC_MR_STARTUP_1792 (0x1Cu << 24) /**< \brief (DACC_MR) 1792 periods of DACClock */
+#define   DACC_MR_STARTUP_1856 (0x1Du << 24) /**< \brief (DACC_MR) 1856 periods of DACClock */
+#define   DACC_MR_STARTUP_1920 (0x1Eu << 24) /**< \brief (DACC_MR) 1920 periods of DACClock */
+#define   DACC_MR_STARTUP_1984 (0x1Fu << 24) /**< \brief (DACC_MR) 1984 periods of DACClock */
+/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */
+#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */
+#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */
+/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */
+#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */
+#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */
+/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */
+#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */
+#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */
+/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */
+#define DACC_CDR_DATA_Pos 0
+#define DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos) /**< \brief (DACC_CDR) Data to Convert */
+#define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos)))
+/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */
+#define DACC_IER_TXRDY (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */
+#define DACC_IER_EOC (0x1u << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */
+#define DACC_IER_ENDTX (0x1u << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */
+#define DACC_IER_TXBUFE (0x1u << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */
+/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */
+#define DACC_IDR_TXRDY (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */
+#define DACC_IDR_EOC (0x1u << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */
+#define DACC_IDR_ENDTX (0x1u << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */
+#define DACC_IDR_TXBUFE (0x1u << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */
+/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */
+#define DACC_IMR_TXRDY (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */
+#define DACC_IMR_EOC (0x1u << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */
+#define DACC_IMR_ENDTX (0x1u << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */
+#define DACC_IMR_TXBUFE (0x1u << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */
+/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */
+#define DACC_ISR_TXRDY (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */
+#define DACC_ISR_EOC (0x1u << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */
+#define DACC_ISR_ENDTX (0x1u << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */
+#define DACC_ISR_TXBUFE (0x1u << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */
+/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */
+#define DACC_ACR_IBCTLCH0_Pos 0
+#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */
+#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)))
+#define DACC_ACR_IBCTLCH1_Pos 2
+#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */
+#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)))
+#define DACC_ACR_IBCTLDACCORE_Pos 8
+#define DACC_ACR_IBCTLDACCORE_Msk (0x3u << DACC_ACR_IBCTLDACCORE_Pos) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */
+#define DACC_ACR_IBCTLDACCORE(value) ((DACC_ACR_IBCTLDACCORE_Msk & ((value) << DACC_ACR_IBCTLDACCORE_Pos)))
+/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */
+#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protect Enable */
+#define DACC_WPMR_WPKEY_Pos 8
+#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect KEY */
+#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))
+/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */
+#define DACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (DACC_WPSR) Write protection error */
+#define DACC_WPSR_WPROTADDR_Pos 8
+#define DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos) /**< \brief (DACC_WPSR) Write protection error address */
+/* -------- DACC_RPR : (DACC Offset: 0x100) Receive Pointer Register -------- */
+#define DACC_RPR_RXPTR_Pos 0
+#define DACC_RPR_RXPTR_Msk (0xffffffffu << DACC_RPR_RXPTR_Pos) /**< \brief (DACC_RPR) Receive Pointer Register */
+#define DACC_RPR_RXPTR(value) ((DACC_RPR_RXPTR_Msk & ((value) << DACC_RPR_RXPTR_Pos)))
+/* -------- DACC_RCR : (DACC Offset: 0x104) Receive Counter Register -------- */
+#define DACC_RCR_RXCTR_Pos 0
+#define DACC_RCR_RXCTR_Msk (0xffffu << DACC_RCR_RXCTR_Pos) /**< \brief (DACC_RCR) Receive Counter Register */
+#define DACC_RCR_RXCTR(value) ((DACC_RCR_RXCTR_Msk & ((value) << DACC_RCR_RXCTR_Pos)))
+/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */
+#define DACC_TPR_TXPTR_Pos 0
+#define DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos) /**< \brief (DACC_TPR) Transmit Counter Register */
+#define DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos)))
+/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */
+#define DACC_TCR_TXCTR_Pos 0
+#define DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos) /**< \brief (DACC_TCR) Transmit Counter Register */
+#define DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos)))
+/* -------- DACC_RNPR : (DACC Offset: 0x110) Receive Next Pointer Register -------- */
+#define DACC_RNPR_RXNPTR_Pos 0
+#define DACC_RNPR_RXNPTR_Msk (0xffffffffu << DACC_RNPR_RXNPTR_Pos) /**< \brief (DACC_RNPR) Receive Next Pointer */
+#define DACC_RNPR_RXNPTR(value) ((DACC_RNPR_RXNPTR_Msk & ((value) << DACC_RNPR_RXNPTR_Pos)))
+/* -------- DACC_RNCR : (DACC Offset: 0x114) Receive Next Counter Register -------- */
+#define DACC_RNCR_RXNCTR_Pos 0
+#define DACC_RNCR_RXNCTR_Msk (0xffffu << DACC_RNCR_RXNCTR_Pos) /**< \brief (DACC_RNCR) Receive Next Counter */
+#define DACC_RNCR_RXNCTR(value) ((DACC_RNCR_RXNCTR_Msk & ((value) << DACC_RNCR_RXNCTR_Pos)))
+/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */
+#define DACC_TNPR_TXNPTR_Pos 0
+#define DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos) /**< \brief (DACC_TNPR) Transmit Next Pointer */
+#define DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos)))
+/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */
+#define DACC_TNCR_TXNCTR_Pos 0
+#define DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos) /**< \brief (DACC_TNCR) Transmit Counter Next */
+#define DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos)))
+/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */
+#define DACC_PTCR_RXTEN (0x1u << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */
+#define DACC_PTCR_RXTDIS (0x1u << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */
+#define DACC_PTCR_TXTEN (0x1u << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */
+#define DACC_PTCR_TXTDIS (0x1u << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */
+/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */
+#define DACC_PTSR_RXTEN (0x1u << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */
+#define DACC_PTSR_TXTEN (0x1u << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_DACC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_efc.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_efc.h
new file mode 100644
index 000000000..ac672a709
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_efc.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_EFC_COMPONENT_
+#define _SAM3S8_EFC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Embedded Flash Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_EFC Embedded Flash Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Efc hardware registers */
+typedef struct {
+  RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */
+  WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */
+  RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */
+  RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */
+} Efc;
+#endif /* __ASSEMBLY__ */
+/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
+#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */
+#define EEFC_FMR_FWS_Pos 8
+#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */
+#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))
+#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */
+#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */
+/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
+#define EEFC_FCR_FCMD_Pos 0
+#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */
+#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))
+#define EEFC_FCR_FARG_Pos 8
+#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */
+#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))
+#define EEFC_FCR_FKEY_Pos 24
+#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */
+#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)))
+/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
+#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */
+#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */
+#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */
+/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
+#define EEFC_FRR_FVALUE_Pos 0
+#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_EFC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_gpbr.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_gpbr.h
new file mode 100644
index 000000000..489b77c82
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_gpbr.h
@@ -0,0 +1,53 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_GPBR_COMPONENT_
+#define _SAM3S8_GPBR_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR General Purpose Backup Register */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_GPBR General Purpose Backup Register */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Gpbr hardware registers */
+typedef struct {
+  RwReg SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */
+} Gpbr;
+#endif /* __ASSEMBLY__ */
+/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */
+#define SYS_GPBR_GPBR_VALUE_Pos 0
+#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */
+#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3S8_GPBR_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_hsmci.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_hsmci.h
new file mode 100644
index 000000000..4132a460b
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_hsmci.h
@@ -0,0 +1,384 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_HSMCI_COMPONENT_
+#define _SAM3S8_HSMCI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_HSMCI High Speed MultiMedia Card Interface */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Hsmci hardware registers */
+typedef struct {
+  WoReg HSMCI_CR;        /**< \brief (Hsmci Offset: 0x00) Control Register */
+  RwReg HSMCI_MR;        /**< \brief (Hsmci Offset: 0x04) Mode Register */
+  RwReg HSMCI_DTOR;      /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */
+  RwReg HSMCI_SDCR;      /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */
+  RwReg HSMCI_ARGR;      /**< \brief (Hsmci Offset: 0x10) Argument Register */
+  WoReg HSMCI_CMDR;      /**< \brief (Hsmci Offset: 0x14) Command Register */
+  RwReg HSMCI_BLKR;      /**< \brief (Hsmci Offset: 0x18) Block Register */
+  RwReg HSMCI_CSTOR;     /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */
+  RoReg HSMCI_RSPR[4];   /**< \brief (Hsmci Offset: 0x20) Response Register */
+  RoReg HSMCI_RDR;       /**< \brief (Hsmci Offset: 0x30) Receive Data Register */
+  WoReg HSMCI_TDR;       /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */
+  RoReg Reserved1[2];
+  RoReg HSMCI_SR;        /**< \brief (Hsmci Offset: 0x40) Status Register */
+  WoReg HSMCI_IER;       /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */
+  WoReg HSMCI_IDR;       /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */
+  RoReg HSMCI_IMR;       /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */
+  RoReg Reserved2[1];
+  RwReg HSMCI_CFG;       /**< \brief (Hsmci Offset: 0x54) Configuration Register */
+  RoReg Reserved3[35];
+  RwReg HSMCI_WPMR;      /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */
+  RoReg HSMCI_WPSR;      /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */
+  RoReg Reserved4[5];
+  RwReg HSMCI_RPR;       /**< \brief (Hsmci Offset: 0x100) Receive Pointer Register */
+  RwReg HSMCI_RCR;       /**< \brief (Hsmci Offset: 0x104) Receive Counter Register */
+  RwReg HSMCI_TPR;       /**< \brief (Hsmci Offset: 0x108) Transmit Pointer Register */
+  RwReg HSMCI_TCR;       /**< \brief (Hsmci Offset: 0x10C) Transmit Counter Register */
+  RwReg HSMCI_RNPR;      /**< \brief (Hsmci Offset: 0x110) Receive Next Pointer Register */
+  RwReg HSMCI_RNCR;      /**< \brief (Hsmci Offset: 0x114) Receive Next Counter Register */
+  RwReg HSMCI_TNPR;      /**< \brief (Hsmci Offset: 0x118) Transmit Next Pointer Register */
+  RwReg HSMCI_TNCR;      /**< \brief (Hsmci Offset: 0x11C) Transmit Next Counter Register */
+  WoReg HSMCI_PTCR;      /**< \brief (Hsmci Offset: 0x120) Transfer Control Register */
+  RoReg HSMCI_PTSR;      /**< \brief (Hsmci Offset: 0x124) Transfer Status Register */
+  RoReg Reserved5[54];
+  RwReg HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */
+} Hsmci;
+#endif /* __ASSEMBLY__ */
+/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */
+#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */
+#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */
+#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */
+#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */
+#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */
+/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */
+#define HSMCI_MR_CLKDIV_Pos 0
+#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */
+#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))
+#define HSMCI_MR_PWSDIV_Pos 8
+#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */
+#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))
+#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR)  */
+#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR)  */
+#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */
+#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */
+#define HSMCI_MR_PDCMODE (0x1u << 15) /**< \brief (HSMCI_MR) PDC-oriented Mode */
+/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */
+#define HSMCI_DTOR_DTOCYC_Pos 0
+#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */
+#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))
+#define HSMCI_DTOR_DTOMUL_Pos 4
+#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */
+#define   HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */
+#define   HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */
+#define   HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */
+#define   HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */
+#define   HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */
+#define   HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */
+#define   HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */
+#define   HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */
+/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */
+#define HSMCI_SDCR_SDCSEL_Pos 0
+#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */
+#define   HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */
+#define   HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) - */
+#define   HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */
+#define   HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */
+#define HSMCI_SDCR_SDCBUS_Pos 6
+#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */
+#define   HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */
+#define   HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */
+#define   HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */
+/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */
+#define HSMCI_ARGR_ARG_Pos 0
+#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */
+#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))
+/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */
+#define HSMCI_CMDR_CMDNB_Pos 0
+#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */
+#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))
+#define HSMCI_CMDR_RSPTYP_Pos 6
+#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */
+#define   HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */
+#define   HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */
+#define   HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */
+#define   HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */
+#define HSMCI_CMDR_SPCMD_Pos 8
+#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */
+#define   HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */
+#define   HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */
+#define   HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */
+#define   HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */
+#define   HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */
+#define   HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */
+#define   HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */
+#define   HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */
+#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */
+#define   HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */
+#define   HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */
+#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */
+#define   HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */
+#define   HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */
+#define HSMCI_CMDR_TRCMD_Pos 16
+#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */
+#define   HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */
+#define   HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */
+#define   HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */
+#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */
+#define   HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */
+#define   HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */
+#define HSMCI_CMDR_TRTYP_Pos 19
+#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */
+#define   HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */
+#define   HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */
+#define   HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */
+#define   HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */
+#define   HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */
+#define HSMCI_CMDR_IOSPCMD_Pos 24
+#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */
+#define   HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */
+#define   HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */
+#define   HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */
+#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */
+#define   HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */
+#define   HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */
+#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */
+/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */
+#define HSMCI_BLKR_BCNT_Pos 0
+#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */
+#define   HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. */
+#define   HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */
+#define   HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */
+#define HSMCI_BLKR_BLKLEN_Pos 16
+#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */
+#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))
+/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */
+#define HSMCI_CSTOR_CSTOCYC_Pos 0
+#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */
+#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))
+#define HSMCI_CSTOR_CSTOMUL_Pos 4
+#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */
+#define   HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */
+#define   HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */
+#define   HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */
+#define   HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */
+#define   HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */
+#define   HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */
+#define   HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */
+#define   HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */
+/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */
+#define HSMCI_RSPR_RSP_Pos 0
+#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */
+/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */
+#define HSMCI_RDR_DATA_Pos 0
+#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */
+/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */
+#define HSMCI_TDR_DATA_Pos 0
+#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */
+#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))
+/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */
+#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */
+#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */
+#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */
+#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */
+#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */
+#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */
+#define HSMCI_SR_ENDRX (0x1u << 6) /**< \brief (HSMCI_SR) End of RX Buffer */
+#define HSMCI_SR_ENDTX (0x1u << 7) /**< \brief (HSMCI_SR) End of TX Buffer */
+#define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */
+#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */
+#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */
+#define HSMCI_SR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_SR) RX Buffer Full */
+#define HSMCI_SR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_SR) TX Buffer Empty */
+#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */
+#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */
+#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */
+#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */
+#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */
+#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */
+#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */
+#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */
+#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */
+#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */
+#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */
+#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */
+#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */
+#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */
+/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */
+#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */
+#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */
+#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */
+#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */
+#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */
+#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */
+#define HSMCI_IER_ENDRX (0x1u << 6) /**< \brief (HSMCI_IER) End of Receive Buffer Interrupt Enable */
+#define HSMCI_IER_ENDTX (0x1u << 7) /**< \brief (HSMCI_IER) End of Transmit Buffer Interrupt Enable */
+#define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */
+#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */
+#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */
+#define HSMCI_IER_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IER) Receive Buffer Full Interrupt Enable */
+#define HSMCI_IER_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IER) Transmit Buffer Empty Interrupt Enable */
+#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */
+#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */
+#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */
+#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */
+#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */
+#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */
+#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */
+#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */
+#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */
+#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */
+#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */
+#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */
+#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */
+#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */
+/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */
+#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */
+#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */
+#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */
+#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */
+#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */
+#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */
+#define HSMCI_IDR_ENDRX (0x1u << 6) /**< \brief (HSMCI_IDR) End of Receive Buffer Interrupt Disable */
+#define HSMCI_IDR_ENDTX (0x1u << 7) /**< \brief (HSMCI_IDR) End of Transmit Buffer Interrupt Disable */
+#define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */
+#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */
+#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */
+#define HSMCI_IDR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IDR) Receive Buffer Full Interrupt Disable */
+#define HSMCI_IDR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IDR) Transmit Buffer Empty Interrupt Disable */
+#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */
+#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */
+#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */
+#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */
+#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */
+#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */
+#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */
+#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */
+#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */
+#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */
+#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */
+#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */
+#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */
+#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */
+/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */
+#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */
+#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */
+#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */
+#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */
+#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */
+#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */
+#define HSMCI_IMR_ENDRX (0x1u << 6) /**< \brief (HSMCI_IMR) End of Receive Buffer Interrupt Mask */
+#define HSMCI_IMR_ENDTX (0x1u << 7) /**< \brief (HSMCI_IMR) End of Transmit Buffer Interrupt Mask */
+#define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */
+#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */
+#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */
+#define HSMCI_IMR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IMR) Receive Buffer Full Interrupt Mask */
+#define HSMCI_IMR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IMR) Transmit Buffer Empty Interrupt Mask */
+#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */
+#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */
+#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */
+#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */
+#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */
+#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */
+#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */
+#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */
+#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */
+#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */
+#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */
+#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */
+#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */
+#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */
+/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */
+#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */
+#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */
+#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */
+#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */
+/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */
+#define HSMCI_WPMR_WP_EN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */
+#define HSMCI_WPMR_WP_KEY_Pos 8
+#define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) /**< \brief (HSMCI_WPMR) Write Protection Key password */
+#define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos)))
+/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */
+#define HSMCI_WPSR_WP_VS_Pos 0
+#define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */
+#define   HSMCI_WPSR_WP_VS_NONE (0x0u << 0) /**< \brief (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) */
+#define   HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) */
+#define   HSMCI_WPSR_WP_VS_RESET (0x2u << 0) /**< \brief (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). */
+#define   HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) /**< \brief (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. */
+#define HSMCI_WPSR_WP_VSRC_Pos 8
+#define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */
+/* -------- HSMCI_RPR : (HSMCI Offset: 0x100) Receive Pointer Register -------- */
+#define HSMCI_RPR_RXPTR_Pos 0
+#define HSMCI_RPR_RXPTR_Msk (0xffffffffu << HSMCI_RPR_RXPTR_Pos) /**< \brief (HSMCI_RPR) Receive Pointer Register */
+#define HSMCI_RPR_RXPTR(value) ((HSMCI_RPR_RXPTR_Msk & ((value) << HSMCI_RPR_RXPTR_Pos)))
+/* -------- HSMCI_RCR : (HSMCI Offset: 0x104) Receive Counter Register -------- */
+#define HSMCI_RCR_RXCTR_Pos 0
+#define HSMCI_RCR_RXCTR_Msk (0xffffu << HSMCI_RCR_RXCTR_Pos) /**< \brief (HSMCI_RCR) Receive Counter Register */
+#define HSMCI_RCR_RXCTR(value) ((HSMCI_RCR_RXCTR_Msk & ((value) << HSMCI_RCR_RXCTR_Pos)))
+/* -------- HSMCI_TPR : (HSMCI Offset: 0x108) Transmit Pointer Register -------- */
+#define HSMCI_TPR_TXPTR_Pos 0
+#define HSMCI_TPR_TXPTR_Msk (0xffffffffu << HSMCI_TPR_TXPTR_Pos) /**< \brief (HSMCI_TPR) Transmit Counter Register */
+#define HSMCI_TPR_TXPTR(value) ((HSMCI_TPR_TXPTR_Msk & ((value) << HSMCI_TPR_TXPTR_Pos)))
+/* -------- HSMCI_TCR : (HSMCI Offset: 0x10C) Transmit Counter Register -------- */
+#define HSMCI_TCR_TXCTR_Pos 0
+#define HSMCI_TCR_TXCTR_Msk (0xffffu << HSMCI_TCR_TXCTR_Pos) /**< \brief (HSMCI_TCR) Transmit Counter Register */
+#define HSMCI_TCR_TXCTR(value) ((HSMCI_TCR_TXCTR_Msk & ((value) << HSMCI_TCR_TXCTR_Pos)))
+/* -------- HSMCI_RNPR : (HSMCI Offset: 0x110) Receive Next Pointer Register -------- */
+#define HSMCI_RNPR_RXNPTR_Pos 0
+#define HSMCI_RNPR_RXNPTR_Msk (0xffffffffu << HSMCI_RNPR_RXNPTR_Pos) /**< \brief (HSMCI_RNPR) Receive Next Pointer */
+#define HSMCI_RNPR_RXNPTR(value) ((HSMCI_RNPR_RXNPTR_Msk & ((value) << HSMCI_RNPR_RXNPTR_Pos)))
+/* -------- HSMCI_RNCR : (HSMCI Offset: 0x114) Receive Next Counter Register -------- */
+#define HSMCI_RNCR_RXNCTR_Pos 0
+#define HSMCI_RNCR_RXNCTR_Msk (0xffffu << HSMCI_RNCR_RXNCTR_Pos) /**< \brief (HSMCI_RNCR) Receive Next Counter */
+#define HSMCI_RNCR_RXNCTR(value) ((HSMCI_RNCR_RXNCTR_Msk & ((value) << HSMCI_RNCR_RXNCTR_Pos)))
+/* -------- HSMCI_TNPR : (HSMCI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define HSMCI_TNPR_TXNPTR_Pos 0
+#define HSMCI_TNPR_TXNPTR_Msk (0xffffffffu << HSMCI_TNPR_TXNPTR_Pos) /**< \brief (HSMCI_TNPR) Transmit Next Pointer */
+#define HSMCI_TNPR_TXNPTR(value) ((HSMCI_TNPR_TXNPTR_Msk & ((value) << HSMCI_TNPR_TXNPTR_Pos)))
+/* -------- HSMCI_TNCR : (HSMCI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define HSMCI_TNCR_TXNCTR_Pos 0
+#define HSMCI_TNCR_TXNCTR_Msk (0xffffu << HSMCI_TNCR_TXNCTR_Pos) /**< \brief (HSMCI_TNCR) Transmit Counter Next */
+#define HSMCI_TNCR_TXNCTR(value) ((HSMCI_TNCR_TXNCTR_Msk & ((value) << HSMCI_TNCR_TXNCTR_Pos)))
+/* -------- HSMCI_PTCR : (HSMCI Offset: 0x120) Transfer Control Register -------- */
+#define HSMCI_PTCR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTCR) Receiver Transfer Enable */
+#define HSMCI_PTCR_RXTDIS (0x1u << 1) /**< \brief (HSMCI_PTCR) Receiver Transfer Disable */
+#define HSMCI_PTCR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTCR) Transmitter Transfer Enable */
+#define HSMCI_PTCR_TXTDIS (0x1u << 9) /**< \brief (HSMCI_PTCR) Transmitter Transfer Disable */
+/* -------- HSMCI_PTSR : (HSMCI Offset: 0x124) Transfer Status Register -------- */
+#define HSMCI_PTSR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTSR) Receiver Transfer Enable */
+#define HSMCI_PTSR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_HSMCI_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_matrix.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_matrix.h
new file mode 100644
index 000000000..053917d80
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_matrix.h
@@ -0,0 +1,188 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_MATRIX_COMPONENT_
+#define _SAM3S8_MATRIX_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR AHB Bus Matrix */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_MATRIX AHB Bus Matrix */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Matrix hardware registers */
+typedef struct {
+  RwReg MATRIX_MCFG[4]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */
+  RoReg Reserved1[12];
+  RwReg MATRIX_SCFG[5]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */
+  RoReg Reserved2[11];
+  RwReg MATRIX_PRAS0;   /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */
+  RoReg Reserved3[1];
+  RwReg MATRIX_PRAS1;   /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */
+  RoReg Reserved4[1];
+  RwReg MATRIX_PRAS2;   /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */
+  RoReg Reserved5[1];
+  RwReg MATRIX_PRAS3;   /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */
+  RoReg Reserved6[1];
+  RwReg MATRIX_PRAS4;   /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */
+  RoReg Reserved7[1];
+  RoReg Reserved8[27];
+  RwReg CCFG_SYSIO;     /**< \brief (Matrix Offset: 0x0114) System I/O Configuration register */
+  RoReg Reserved9[1];
+  RwReg CCFG_SMCNFCS;   /**< \brief (Matrix Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register */
+  RoReg Reserved10[49];
+  RwReg MATRIX_WPMR;    /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */
+  RoReg MATRIX_WPSR;    /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */
+} Matrix;
+#endif /* __ASSEMBLY__ */
+/* -------- MATRIX_MCFG[4] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */
+#define MATRIX_MCFG_ULBT_Pos 0
+#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[4]) Undefined Length Burst Type */
+#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))
+/* -------- MATRIX_SCFG[5] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
+#define MATRIX_SCFG_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[5]) Maximum Number of Allowed Cycles for a Burst */
+#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[5]) Default Master Type */
+#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
+#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[5]) Fixed Default Master */
+#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
+#define MATRIX_SCFG_ARBT_Pos 24
+#define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[5]) Arbitration Type */
+#define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos)))
+/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */
+#define MATRIX_PRAS0_M0PR_Pos 0
+#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */
+#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))
+#define MATRIX_PRAS0_M1PR_Pos 4
+#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */
+#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))
+#define MATRIX_PRAS0_M2PR_Pos 8
+#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */
+#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))
+#define MATRIX_PRAS0_M3PR_Pos 12
+#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */
+#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))
+#define MATRIX_PRAS0_M4PR_Pos 16
+#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */
+#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos)))
+/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */
+#define MATRIX_PRAS1_M0PR_Pos 0
+#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */
+#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))
+#define MATRIX_PRAS1_M1PR_Pos 4
+#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */
+#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))
+#define MATRIX_PRAS1_M2PR_Pos 8
+#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */
+#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))
+#define MATRIX_PRAS1_M3PR_Pos 12
+#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */
+#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))
+#define MATRIX_PRAS1_M4PR_Pos 16
+#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */
+#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos)))
+/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */
+#define MATRIX_PRAS2_M0PR_Pos 0
+#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */
+#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))
+#define MATRIX_PRAS2_M1PR_Pos 4
+#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */
+#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))
+#define MATRIX_PRAS2_M2PR_Pos 8
+#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */
+#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))
+#define MATRIX_PRAS2_M3PR_Pos 12
+#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */
+#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))
+#define MATRIX_PRAS2_M4PR_Pos 16
+#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */
+#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos)))
+/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */
+#define MATRIX_PRAS3_M0PR_Pos 0
+#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */
+#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))
+#define MATRIX_PRAS3_M1PR_Pos 4
+#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */
+#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))
+#define MATRIX_PRAS3_M2PR_Pos 8
+#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */
+#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))
+#define MATRIX_PRAS3_M3PR_Pos 12
+#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */
+#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))
+#define MATRIX_PRAS3_M4PR_Pos 16
+#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */
+#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos)))
+/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */
+#define MATRIX_PRAS4_M0PR_Pos 0
+#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */
+#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos)))
+#define MATRIX_PRAS4_M1PR_Pos 4
+#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */
+#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos)))
+#define MATRIX_PRAS4_M2PR_Pos 8
+#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */
+#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos)))
+#define MATRIX_PRAS4_M3PR_Pos 12
+#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */
+#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos)))
+#define MATRIX_PRAS4_M4PR_Pos 16
+#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */
+#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos)))
+/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration register -------- */
+#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */
+#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */
+#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */
+#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */
+#define CCFG_SYSIO_SYSIO10 (0x1u << 10) /**< \brief (CCFG_SYSIO) PB10 or DDM Assignment */
+#define CCFG_SYSIO_SYSIO11 (0x1u << 11) /**< \brief (CCFG_SYSIO) PB11 or DDP Assignment */
+#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */
+/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register -------- */
+#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */
+#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */
+#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */
+#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */
+/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */
+#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */
+#define MATRIX_WPMR_WPKEY_Pos 8
+#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */
+#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
+/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */
+#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */
+#define MATRIX_WPSR_WPVSRC_Pos 8
+#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_MATRIX_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_pdc.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_pdc.h
new file mode 100644
index 000000000..770a44746
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_pdc.h
@@ -0,0 +1,98 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_PDC_COMPONENT_
+#define _SAM3S8_PDC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_PDC Peripheral DMA Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Pdc hardware registers */
+typedef struct {
+  RwReg PERIPH_RPR;  /**< \brief (Pdc Offset: 0x0) Receive Pointer Register */
+  RwReg PERIPH_RCR;  /**< \brief (Pdc Offset: 0x4) Receive Counter Register */
+  RwReg PERIPH_TPR;  /**< \brief (Pdc Offset: 0x8) Transmit Pointer Register */
+  RwReg PERIPH_TCR;  /**< \brief (Pdc Offset: 0xC) Transmit Counter Register */
+  RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */
+  RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */
+  RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */
+  RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */
+  WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */
+  RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */
+} Pdc;
+#endif /* __ASSEMBLY__ */
+/* -------- PERIPH_RPR : (PDC Offset: 0x0) Receive Pointer Register -------- */
+#define PERIPH_RPR_RXPTR_Pos 0
+#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */
+#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos)))
+/* -------- PERIPH_RCR : (PDC Offset: 0x4) Receive Counter Register -------- */
+#define PERIPH_RCR_RXCTR_Pos 0
+#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */
+#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos)))
+/* -------- PERIPH_TPR : (PDC Offset: 0x8) Transmit Pointer Register -------- */
+#define PERIPH_TPR_TXPTR_Pos 0
+#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */
+#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos)))
+/* -------- PERIPH_TCR : (PDC Offset: 0xC) Transmit Counter Register -------- */
+#define PERIPH_TCR_TXCTR_Pos 0
+#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */
+#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos)))
+/* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */
+#define PERIPH_RNPR_RXNPTR_Pos 0
+#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */
+#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos)))
+/* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */
+#define PERIPH_RNCR_RXNCTR_Pos 0
+#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */
+#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos)))
+/* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */
+#define PERIPH_TNPR_TXNPTR_Pos 0
+#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */
+#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos)))
+/* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */
+#define PERIPH_TNCR_TXNCTR_Pos 0
+#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */
+#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos)))
+/* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */
+#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */
+#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */
+#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */
+#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */
+/* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */
+#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */
+#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_PDC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_pio.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_pio.h
new file mode 100644
index 000000000..a519a3c51
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_pio.h
@@ -0,0 +1,1662 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_PIO_COMPONENT_
+#define _SAM3S8_PIO_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_PIO Parallel Input/Output Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Pio hardware registers */
+typedef struct {
+  WoReg PIO_PER;        /**< \brief (Pio Offset: 0x0000) PIO Enable Register */
+  WoReg PIO_PDR;        /**< \brief (Pio Offset: 0x0004) PIO Disable Register */
+  RoReg PIO_PSR;        /**< \brief (Pio Offset: 0x0008) PIO Status Register */
+  RoReg Reserved1[1];
+  WoReg PIO_OER;        /**< \brief (Pio Offset: 0x0010) Output Enable Register */
+  WoReg PIO_ODR;        /**< \brief (Pio Offset: 0x0014) Output Disable Register */
+  RoReg PIO_OSR;        /**< \brief (Pio Offset: 0x0018) Output Status Register */
+  RoReg Reserved2[1];
+  WoReg PIO_IFER;       /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */
+  WoReg PIO_IFDR;       /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */
+  RoReg PIO_IFSR;       /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */
+  RoReg Reserved3[1];
+  WoReg PIO_SODR;       /**< \brief (Pio Offset: 0x0030) Set Output Data Register */
+  WoReg PIO_CODR;       /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */
+  RwReg PIO_ODSR;       /**< \brief (Pio Offset: 0x0038) Output Data Status Register */
+  RoReg PIO_PDSR;       /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */
+  WoReg PIO_IER;        /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */
+  WoReg PIO_IDR;        /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */
+  RoReg PIO_IMR;        /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */
+  RoReg PIO_ISR;        /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */
+  WoReg PIO_MDER;       /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */
+  WoReg PIO_MDDR;       /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */
+  RoReg PIO_MDSR;       /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */
+  RoReg Reserved4[1];
+  WoReg PIO_PUDR;       /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */
+  WoReg PIO_PUER;       /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */
+  RoReg PIO_PUSR;       /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */
+  RoReg Reserved5[1];
+  RwReg PIO_ABCDSR[2];  /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */
+  RoReg Reserved6[2];
+  WoReg PIO_IFSCDR;     /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */
+  WoReg PIO_IFSCER;     /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */
+  RoReg PIO_IFSCSR;     /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */
+  RwReg PIO_SCDR;       /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */
+  WoReg PIO_PPDDR;      /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */
+  WoReg PIO_PPDER;      /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */
+  RoReg PIO_PPDSR;      /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */
+  RoReg Reserved7[1];
+  WoReg PIO_OWER;       /**< \brief (Pio Offset: 0x00A0) Output Write Enable */
+  WoReg PIO_OWDR;       /**< \brief (Pio Offset: 0x00A4) Output Write Disable */
+  RoReg PIO_OWSR;       /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */
+  RoReg Reserved8[1];
+  WoReg PIO_AIMER;      /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */
+  WoReg PIO_AIMDR;      /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */
+  RoReg PIO_AIMMR;      /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */
+  RoReg Reserved9[1];
+  WoReg PIO_ESR;        /**< \brief (Pio Offset: 0x00C0) Edge Select Register */
+  WoReg PIO_LSR;        /**< \brief (Pio Offset: 0x00C4) Level Select Register */
+  RoReg PIO_ELSR;       /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */
+  RoReg Reserved10[1];
+  WoReg PIO_FELLSR;     /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */
+  WoReg PIO_REHLSR;     /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */
+  RoReg PIO_FRLHSR;     /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */
+  RoReg Reserved11[1];
+  RoReg PIO_LOCKSR;     /**< \brief (Pio Offset: 0x00E0) Lock Status */
+  RwReg PIO_WPMR;       /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */
+  RoReg PIO_WPSR;       /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */
+  RoReg Reserved12[5];
+  RwReg PIO_SCHMITT;    /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */
+  RoReg Reserved13[19];
+  RwReg PIO_PCMR;       /**< \brief (Pio Offset: 0x150) Parallel Capture Mode Register */
+  WoReg PIO_PCIER;      /**< \brief (Pio Offset: 0x154) Parallel Capture Interrupt Enable Register */
+  WoReg PIO_PCIDR;      /**< \brief (Pio Offset: 0x158) Parallel Capture Interrupt Disable Register */
+  RoReg PIO_PCIMR;      /**< \brief (Pio Offset: 0x15C) Parallel Capture Interrupt Mask Register */
+  RoReg PIO_PCISR;      /**< \brief (Pio Offset: 0x160) Parallel Capture Interrupt Status Register */
+  RoReg PIO_PCRHR;      /**< \brief (Pio Offset: 0x164) Parallel Capture Reception Holding Register */
+  RwReg PIO_RPR;        /**< \brief (Pio Offset: 0x168) Receive Pointer Register */
+  RwReg PIO_RCR;        /**< \brief (Pio Offset: 0x16C) Receive Counter Register */
+  RwReg PIO_TPR;        /**< \brief (Pio Offset: 0x170) Transmit Pointer Register */
+  RwReg PIO_TCR;        /**< \brief (Pio Offset: 0x174) Transmit Counter Register */
+  RwReg PIO_RNPR;       /**< \brief (Pio Offset: 0x178) Receive Next Pointer Register */
+  RwReg PIO_RNCR;       /**< \brief (Pio Offset: 0x17C) Receive Next Counter Register */
+  RwReg PIO_TNPR;       /**< \brief (Pio Offset: 0x180) Transmit Next Pointer Register */
+  RwReg PIO_TNCR;       /**< \brief (Pio Offset: 0x184) Transmit Next Counter Register */
+  WoReg PIO_PTCR;       /**< \brief (Pio Offset: 0x188) Transfer Control Register */
+  RoReg PIO_PTSR;       /**< \brief (Pio Offset: 0x18C) Transfer Status Register */
+} Pio;
+#endif /* __ASSEMBLY__ */
+/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */
+#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */
+/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */
+#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */
+/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */
+#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */
+/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */
+#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */
+/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */
+#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */
+/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */
+#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */
+/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */
+#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */
+/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */
+#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */
+/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */
+#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */
+/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */
+#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */
+/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */
+#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */
+/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */
+#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */
+/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */
+#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */
+/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */
+#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */
+#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */
+#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */
+#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */
+#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */
+/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */
+#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */
+#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */
+/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */
+#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */
+/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */
+#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull Up Enable. */
+/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */
+#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull Up Status. */
+/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */
+#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */
+#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */
+#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */
+#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */
+#define PIO_SCDR_DIV_Pos 0
+#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR)  */
+#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)))
+/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */
+#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */
+#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */
+/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */
+#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */
+/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */
+#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable. */
+/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */
+#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable. */
+/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */
+#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status. */
+/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */
+#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */
+#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */
+#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */
+#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */
+#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */
+#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */
+#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */
+#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */
+#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */
+#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status. */
+/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protect Enable */
+#define PIO_WPMR_WPKEY_Pos 8
+#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protect KEY */
+#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)))
+/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */
+#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */
+#define PIO_WPSR_WPVSRC_Pos 8
+#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protect Violation Source */
+/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */
+#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT)  */
+/* -------- PIO_PCMR : (PIO Offset: 0x150) Parallel Capture Mode Register -------- */
+#define PIO_PCMR_PCEN (0x1u << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */
+#define PIO_PCMR_DSIZE_Pos 4
+#define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */
+#define   PIO_PCMR_DSIZE_BYTE (0x0u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR register is a BYTE (8-bit) */
+#define   PIO_PCMR_DSIZE_HALFWORD (0x1u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit) */
+#define   PIO_PCMR_DSIZE_WORD (0x2u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR register is a WORD (32-bit) */
+#define PIO_PCMR_ALWYS (0x1u << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */
+#define PIO_PCMR_HALFS (0x1u << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */
+#define PIO_PCMR_FRSTS (0x1u << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */
+/* -------- PIO_PCIER : (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register -------- */
+#define PIO_PCIER_DRDY (0x1u << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */
+#define PIO_PCIER_OVRE (0x1u << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */
+#define PIO_PCIER_ENDRX (0x1u << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */
+#define PIO_PCIER_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */
+/* -------- PIO_PCIDR : (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register -------- */
+#define PIO_PCIDR_DRDY (0x1u << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */
+#define PIO_PCIDR_OVRE (0x1u << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */
+#define PIO_PCIDR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */
+#define PIO_PCIDR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */
+/* -------- PIO_PCIMR : (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register -------- */
+#define PIO_PCIMR_DRDY (0x1u << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */
+#define PIO_PCIMR_OVRE (0x1u << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */
+#define PIO_PCIMR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */
+#define PIO_PCIMR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */
+/* -------- PIO_PCISR : (PIO Offset: 0x160) Parallel Capture Interrupt Status Register -------- */
+#define PIO_PCISR_DRDY (0x1u << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */
+#define PIO_PCISR_OVRE (0x1u << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error. */
+#define PIO_PCISR_ENDRX (0x1u << 2) /**< \brief (PIO_PCISR) End of Reception Transfer. */
+#define PIO_PCISR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCISR) Reception Buffer Full */
+/* -------- PIO_PCRHR : (PIO Offset: 0x164) Parallel Capture Reception Holding Register -------- */
+#define PIO_PCRHR_RDATA_Pos 0
+#define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data. */
+/* -------- PIO_RPR : (PIO Offset: 0x168) Receive Pointer Register -------- */
+#define PIO_RPR_RXPTR_Pos 0
+#define PIO_RPR_RXPTR_Msk (0xffffffffu << PIO_RPR_RXPTR_Pos) /**< \brief (PIO_RPR) Receive Pointer Register */
+#define PIO_RPR_RXPTR(value) ((PIO_RPR_RXPTR_Msk & ((value) << PIO_RPR_RXPTR_Pos)))
+/* -------- PIO_RCR : (PIO Offset: 0x16C) Receive Counter Register -------- */
+#define PIO_RCR_RXCTR_Pos 0
+#define PIO_RCR_RXCTR_Msk (0xffffu << PIO_RCR_RXCTR_Pos) /**< \brief (PIO_RCR) Receive Counter Register */
+#define PIO_RCR_RXCTR(value) ((PIO_RCR_RXCTR_Msk & ((value) << PIO_RCR_RXCTR_Pos)))
+/* -------- PIO_TPR : (PIO Offset: 0x170) Transmit Pointer Register -------- */
+#define PIO_TPR_TXPTR_Pos 0
+#define PIO_TPR_TXPTR_Msk (0xffffffffu << PIO_TPR_TXPTR_Pos) /**< \brief (PIO_TPR) Transmit Counter Register */
+#define PIO_TPR_TXPTR(value) ((PIO_TPR_TXPTR_Msk & ((value) << PIO_TPR_TXPTR_Pos)))
+/* -------- PIO_TCR : (PIO Offset: 0x174) Transmit Counter Register -------- */
+#define PIO_TCR_TXCTR_Pos 0
+#define PIO_TCR_TXCTR_Msk (0xffffu << PIO_TCR_TXCTR_Pos) /**< \brief (PIO_TCR) Transmit Counter Register */
+#define PIO_TCR_TXCTR(value) ((PIO_TCR_TXCTR_Msk & ((value) << PIO_TCR_TXCTR_Pos)))
+/* -------- PIO_RNPR : (PIO Offset: 0x178) Receive Next Pointer Register -------- */
+#define PIO_RNPR_RXNPTR_Pos 0
+#define PIO_RNPR_RXNPTR_Msk (0xffffffffu << PIO_RNPR_RXNPTR_Pos) /**< \brief (PIO_RNPR) Receive Next Pointer */
+#define PIO_RNPR_RXNPTR(value) ((PIO_RNPR_RXNPTR_Msk & ((value) << PIO_RNPR_RXNPTR_Pos)))
+/* -------- PIO_RNCR : (PIO Offset: 0x17C) Receive Next Counter Register -------- */
+#define PIO_RNCR_RXNCTR_Pos 0
+#define PIO_RNCR_RXNCTR_Msk (0xffffu << PIO_RNCR_RXNCTR_Pos) /**< \brief (PIO_RNCR) Receive Next Counter */
+#define PIO_RNCR_RXNCTR(value) ((PIO_RNCR_RXNCTR_Msk & ((value) << PIO_RNCR_RXNCTR_Pos)))
+/* -------- PIO_TNPR : (PIO Offset: 0x180) Transmit Next Pointer Register -------- */
+#define PIO_TNPR_TXNPTR_Pos 0
+#define PIO_TNPR_TXNPTR_Msk (0xffffffffu << PIO_TNPR_TXNPTR_Pos) /**< \brief (PIO_TNPR) Transmit Next Pointer */
+#define PIO_TNPR_TXNPTR(value) ((PIO_TNPR_TXNPTR_Msk & ((value) << PIO_TNPR_TXNPTR_Pos)))
+/* -------- PIO_TNCR : (PIO Offset: 0x184) Transmit Next Counter Register -------- */
+#define PIO_TNCR_TXNCTR_Pos 0
+#define PIO_TNCR_TXNCTR_Msk (0xffffu << PIO_TNCR_TXNCTR_Pos) /**< \brief (PIO_TNCR) Transmit Counter Next */
+#define PIO_TNCR_TXNCTR(value) ((PIO_TNCR_TXNCTR_Msk & ((value) << PIO_TNCR_TXNCTR_Pos)))
+/* -------- PIO_PTCR : (PIO Offset: 0x188) Transfer Control Register -------- */
+#define PIO_PTCR_RXTEN (0x1u << 0) /**< \brief (PIO_PTCR) Receiver Transfer Enable */
+#define PIO_PTCR_RXTDIS (0x1u << 1) /**< \brief (PIO_PTCR) Receiver Transfer Disable */
+#define PIO_PTCR_TXTEN (0x1u << 8) /**< \brief (PIO_PTCR) Transmitter Transfer Enable */
+#define PIO_PTCR_TXTDIS (0x1u << 9) /**< \brief (PIO_PTCR) Transmitter Transfer Disable */
+/* -------- PIO_PTSR : (PIO Offset: 0x18C) Transfer Status Register -------- */
+#define PIO_PTSR_RXTEN (0x1u << 0) /**< \brief (PIO_PTSR) Receiver Transfer Enable */
+#define PIO_PTSR_TXTEN (0x1u << 8) /**< \brief (PIO_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_PIO_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_pmc.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_pmc.h
new file mode 100644
index 000000000..47cca67d0
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_pmc.h
@@ -0,0 +1,394 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_PMC_COMPONENT_
+#define _SAM3S8_PMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Power Management Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_PMC Power Management Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Pmc hardware registers */
+typedef struct {
+  WoReg PMC_SCER;      /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */
+  WoReg PMC_SCDR;      /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */
+  RoReg PMC_SCSR;      /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */
+  RoReg Reserved1[1];
+  WoReg PMC_PCER0;     /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */
+  WoReg PMC_PCDR0;     /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */
+  RoReg PMC_PCSR0;     /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */
+  RoReg Reserved2[1];
+  RwReg CKGR_MOR;      /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */
+  RwReg CKGR_MCFR;     /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */
+  RwReg CKGR_PLLAR;    /**< \brief (Pmc Offset: 0x0028) PLLA Register */
+  RwReg CKGR_PLLBR;    /**< \brief (Pmc Offset: 0x002C) PLLB Register */
+  RwReg PMC_MCKR;      /**< \brief (Pmc Offset: 0x0030) Master Clock Register */
+  RoReg Reserved3[1];
+  RwReg PMC_USB;       /**< \brief (Pmc Offset: 0x0038) USB Clock Register */
+  RoReg Reserved4[1];
+  RwReg PMC_PCK[3];    /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */
+  RoReg Reserved5[5];
+  WoReg PMC_IER;       /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */
+  WoReg PMC_IDR;       /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */
+  RoReg PMC_SR;        /**< \brief (Pmc Offset: 0x0068) Status Register */
+  RoReg PMC_IMR;       /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */
+  RwReg PMC_FSMR;      /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */
+  RwReg PMC_FSPR;      /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */
+  WoReg PMC_FOCR;      /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */
+  RoReg Reserved6[26];
+  RwReg PMC_WPMR;      /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */
+  RoReg PMC_WPSR;      /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */
+  RoReg Reserved7[5];
+  WoReg PMC_PCER1;     /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */
+  WoReg PMC_PCDR1;     /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */
+  RoReg PMC_PCSR1;     /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */
+  RoReg Reserved8[1];
+  RwReg PMC_OCR;       /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */
+} Pmc;
+#endif /* __ASSEMBLY__ */
+/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
+#define PMC_SCER_UDP (0x1u << 7) /**< \brief (PMC_SCER) USB Device Port Clock Enable */
+#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */
+#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */
+#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */
+/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
+#define PMC_SCDR_UDP (0x1u << 7) /**< \brief (PMC_SCDR) USB Device Port Clock Disable */
+#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */
+#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */
+#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */
+/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
+#define PMC_SCSR_UDP (0x1u << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */
+#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */
+#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */
+#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */
+/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
+#define PMC_PCER0_PID2 (0x1u << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */
+#define PMC_PCER0_PID3 (0x1u << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */
+#define PMC_PCER0_PID4 (0x1u << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */
+#define PMC_PCER0_PID5 (0x1u << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */
+#define PMC_PCER0_PID6 (0x1u << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */
+#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */
+#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */
+#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */
+#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */
+#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */
+#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */
+#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */
+#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */
+#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */
+#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */
+#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */
+#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */
+#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */
+#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */
+#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */
+#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */
+#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */
+#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */
+#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */
+#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */
+#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */
+#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */
+#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */
+#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */
+/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
+#define PMC_PCDR0_PID2 (0x1u << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */
+#define PMC_PCDR0_PID3 (0x1u << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */
+#define PMC_PCDR0_PID4 (0x1u << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */
+#define PMC_PCDR0_PID5 (0x1u << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */
+#define PMC_PCDR0_PID6 (0x1u << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */
+#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */
+#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */
+#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */
+#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */
+#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */
+#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */
+#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */
+#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */
+#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */
+#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */
+#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */
+#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */
+#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */
+#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */
+#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */
+#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */
+#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */
+#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */
+#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */
+#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */
+#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */
+#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */
+#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */
+#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */
+/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
+#define PMC_PCSR0_PID2 (0x1u << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */
+#define PMC_PCSR0_PID3 (0x1u << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */
+#define PMC_PCSR0_PID4 (0x1u << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */
+#define PMC_PCSR0_PID5 (0x1u << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */
+#define PMC_PCSR0_PID6 (0x1u << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */
+#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */
+#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */
+#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */
+#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */
+#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */
+#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */
+#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */
+#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */
+#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */
+#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */
+#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */
+#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */
+#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */
+#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */
+#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */
+#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */
+#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */
+#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */
+#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */
+#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */
+#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */
+#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */
+#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */
+#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */
+/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
+#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */
+#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */
+#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */
+#define CKGR_MOR_MOSCRCF_Pos 4
+#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */
+#define   CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default) */
+#define   CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz */
+#define   CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz */
+#define CKGR_MOR_MOSCXTST_Pos 8
+#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */
+#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
+#define CKGR_MOR_KEY_Pos 16
+#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */
+#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
+#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */
+#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */
+/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
+#define CKGR_MCFR_MAINF_Pos 0
+#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */
+#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos)))
+#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */
+#define CKGR_MCFR_RCMEAS (0x1u << 20) /**< \brief (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) */
+/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
+#define CKGR_PLLAR_DIVA_Pos 0
+#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider */
+#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
+#define CKGR_PLLAR_PLLACOUNT_Pos 8
+#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */
+#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
+#define CKGR_PLLAR_MULA_Pos 16
+#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */
+#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
+#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */
+/* -------- CKGR_PLLBR : (PMC Offset: 0x002C) PLLB Register -------- */
+#define CKGR_PLLBR_DIVB_Pos 0
+#define CKGR_PLLBR_DIVB_Msk (0xffu << CKGR_PLLBR_DIVB_Pos) /**< \brief (CKGR_PLLBR) Divider */
+#define CKGR_PLLBR_DIVB(value) ((CKGR_PLLBR_DIVB_Msk & ((value) << CKGR_PLLBR_DIVB_Pos)))
+#define CKGR_PLLBR_PLLBCOUNT_Pos 8
+#define CKGR_PLLBR_PLLBCOUNT_Msk (0x3fu << CKGR_PLLBR_PLLBCOUNT_Pos) /**< \brief (CKGR_PLLBR) PLLB Counter */
+#define CKGR_PLLBR_PLLBCOUNT(value) ((CKGR_PLLBR_PLLBCOUNT_Msk & ((value) << CKGR_PLLBR_PLLBCOUNT_Pos)))
+#define CKGR_PLLBR_MULB_Pos 16
+#define CKGR_PLLBR_MULB_Msk (0x7ffu << CKGR_PLLBR_MULB_Pos) /**< \brief (CKGR_PLLBR) PLLB Multiplier */
+#define CKGR_PLLBR_MULB(value) ((CKGR_PLLBR_MULB_Msk & ((value) << CKGR_PLLBR_MULB_Pos)))
+/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
+#define PMC_MCKR_CSS_Pos 0
+#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */
+#define   PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */
+#define   PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */
+#define   PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */
+#define   PMC_MCKR_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_MCKR) PLLBClock is selected */
+#define PMC_MCKR_PRES_Pos 4
+#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */
+#define   PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */
+#define   PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */
+#define   PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */
+#define   PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */
+#define   PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */
+#define   PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */
+#define   PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */
+#define   PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */
+#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */
+#define PMC_MCKR_PLLBDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) PLLB Divisor by 2 */
+/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */
+#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */
+#define PMC_USB_USBDIV_Pos 8
+#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock. */
+#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))
+/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
+#define PMC_PCK_CSS_Pos 0
+#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */
+#define   PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */
+#define   PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */
+#define   PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */
+#define   PMC_PCK_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) PLLB Clock is selected */
+#define   PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */
+#define PMC_PCK_PRES_Pos 4
+#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */
+#define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos)))
+#define   PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */
+#define   PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */
+#define   PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */
+#define   PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */
+#define   PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */
+#define   PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */
+#define   PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */
+/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
+#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */
+#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */
+#define PMC_IER_LOCKB (0x1u << 2) /**< \brief (PMC_IER) PLLB Lock Interrupt Enable */
+#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */
+#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */
+#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */
+#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */
+#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */
+#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */
+#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */
+/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
+#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */
+#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */
+#define PMC_IDR_LOCKB (0x1u << 2) /**< \brief (PMC_IDR) PLLB Lock Interrupt Disable */
+#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */
+#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */
+#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */
+#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */
+#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */
+#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */
+#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */
+/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
+#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */
+#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */
+#define PMC_SR_LOCKB (0x1u << 2) /**< \brief (PMC_SR) PLLB Lock Status */
+#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */
+#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */
+#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */
+#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */
+#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */
+#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */
+#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */
+/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
+#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */
+#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */
+#define PMC_IMR_LOCKB (0x1u << 2) /**< \brief (PMC_IMR) PLLB Lock Interrupt Mask */
+#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */
+#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */
+#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */
+#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */
+#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */
+#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */
+#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */
+/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
+#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */
+#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */
+#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */
+#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */
+#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */
+#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */
+#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */
+#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */
+#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */
+#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */
+#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */
+#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */
+#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */
+#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */
+#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */
+#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */
+#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */
+#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */
+#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */
+#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low Power Mode */
+/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
+#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
+#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */
+/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */
+#define PMC_WPMR_WPKEY_Pos 8
+#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */
+#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
+/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */
+#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */
+#define PMC_WPSR_WPVSRC_Pos 8
+#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */
+/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */
+#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */
+#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */
+#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */
+/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */
+#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */
+#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */
+#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */
+/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */
+#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */
+#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */
+#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */
+/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */
+#define PMC_OCR_CAL4_Pos 0
+#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 Mhz */
+#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos)))
+#define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 Mhz */
+#define PMC_OCR_CAL8_Pos 8
+#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 Mhz */
+#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos)))
+#define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 Mhz */
+#define PMC_OCR_CAL12_Pos 16
+#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 Mhz */
+#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos)))
+#define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 Mhz */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_PMC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_pwm.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_pwm.h
new file mode 100644
index 000000000..ad63587dc
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_pwm.h
@@ -0,0 +1,564 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_PWM_COMPONENT_
+#define _SAM3S8_PWM_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_PWM Pulse Width Modulation Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief PwmCh_num hardware registers */
+typedef struct {
+  RwReg      PWM_CMR;       /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */
+  RwReg      PWM_CDTY;      /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */
+  RwReg      PWM_CDTYUPD;   /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */
+  RwReg      PWM_CPRD;      /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */
+  RwReg      PWM_CPRDUPD;   /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */
+  RwReg      PWM_CCNT;      /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */
+  RwReg      PWM_DT;        /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */
+  RwReg      PWM_DTUPD;     /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */
+} PwmCh_num;
+/** \brief PwmCmp hardware registers */
+typedef struct {
+  RwReg      PWM_CMPV;      /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */
+  RwReg      PWM_CMPVUPD;   /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */
+  RwReg      PWM_CMPM;      /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */
+  RwReg      PWM_CMPMUPD;   /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */
+} PwmCmp;
+/** \brief Pwm hardware registers */
+#define PWMCMP_NUMBER 8
+#define PWMCH_NUM_NUMBER 4
+typedef struct {
+  RwReg      PWM_CLK;       /**< \brief (Pwm Offset: 0x00) PWM Clock Register */
+  WoReg      PWM_ENA;       /**< \brief (Pwm Offset: 0x04) PWM Enable Register */
+  WoReg      PWM_DIS;       /**< \brief (Pwm Offset: 0x08) PWM Disable Register */
+  RoReg      PWM_SR;        /**< \brief (Pwm Offset: 0x0C) PWM Status Register */
+  WoReg      PWM_IER1;      /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */
+  WoReg      PWM_IDR1;      /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */
+  RoReg      PWM_IMR1;      /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */
+  RoReg      PWM_ISR1;      /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */
+  RwReg      PWM_SCM;       /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */
+  RoReg      Reserved1[1];
+  RwReg      PWM_SCUC;      /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */
+  RwReg      PWM_SCUP;      /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */
+  WoReg      PWM_SCUPUPD;   /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */
+  WoReg      PWM_IER2;      /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */
+  WoReg      PWM_IDR2;      /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */
+  RoReg      PWM_IMR2;      /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */
+  RoReg      PWM_ISR2;      /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */
+  RwReg      PWM_OOV;       /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */
+  RwReg      PWM_OS;        /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */
+  WoReg      PWM_OSS;       /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */
+  WoReg      PWM_OSC;       /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */
+  WoReg      PWM_OSSUPD;    /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */
+  WoReg      PWM_OSCUPD;    /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */
+  RwReg      PWM_FMR;       /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */
+  RoReg      PWM_FSR;       /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */
+  WoReg      PWM_FCR;       /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */
+  RwReg      PWM_FPV;       /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */
+  RwReg      PWM_FPE;       /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */
+  RoReg      Reserved2[3];
+  RwReg      PWM_ELMR[2];   /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */
+  RoReg      Reserved3[11];
+  RwReg      PWM_SMMR;      /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */
+  RoReg      Reserved4[12];
+  WoReg      PWM_WPCR;      /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */
+  RoReg      PWM_WPSR;      /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */
+  RoReg      Reserved5[5];
+  RwReg      PWM_RPR;       /**< \brief (Pwm Offset: 0x100) Receive Pointer Register */
+  RwReg      PWM_RCR;       /**< \brief (Pwm Offset: 0x104) Receive Counter Register */
+  RwReg      PWM_TPR;       /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */
+  RwReg      PWM_TCR;       /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */
+  RwReg      PWM_RNPR;      /**< \brief (Pwm Offset: 0x110) Receive Next Pointer Register */
+  RwReg      PWM_RNCR;      /**< \brief (Pwm Offset: 0x114) Receive Next Counter Register */
+  RwReg      PWM_TNPR;      /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */
+  RwReg      PWM_TNCR;      /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */
+  WoReg      PWM_PTCR;      /**< \brief (Pwm Offset: 0x120) Transfer Control Register */
+  RoReg      PWM_PTSR;      /**< \brief (Pwm Offset: 0x124) Transfer Status Register */
+  RoReg      Reserved6[2];
+  PwmCmp     PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */
+  RoReg      Reserved7[20];
+  PwmCh_num  PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */
+} Pwm;
+#endif /* __ASSEMBLY__ */
+/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */
+#define PWM_CLK_DIVA_Pos 0
+#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
+#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))
+#define PWM_CLK_PREA_Pos 8
+#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
+#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))
+#define PWM_CLK_DIVB_Pos 16
+#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
+#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))
+#define PWM_CLK_PREB_Pos 24
+#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
+#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))
+/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
+#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */
+/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
+#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */
+/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
+#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */
+/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */
+#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */
+#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */
+#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */
+#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */
+#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */
+#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */
+#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */
+#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */
+/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */
+#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */
+#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */
+#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */
+#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */
+#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */
+#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */
+#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */
+#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */
+/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */
+#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */
+#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */
+#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */
+#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */
+#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */
+#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */
+#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */
+#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */
+/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */
+#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */
+#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */
+#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */
+#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */
+#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */
+#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */
+#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */
+#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */
+/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */
+#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */
+#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */
+#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */
+#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */
+#define PWM_SCM_UPDM_Pos 16
+#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */
+#define   PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */
+#define   PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */
+#define   PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels */
+#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */
+#define PWM_SCM_PTRCS_Pos 21
+#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */
+#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))
+/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */
+#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */
+/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */
+#define PWM_SCUP_UPR_Pos 0
+#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */
+#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))
+#define PWM_SCUP_UPRCNT_Pos 4
+#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */
+#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))
+/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */
+#define PWM_SCUPUPD_UPRUPD_Pos 0
+#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */
+#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))
+/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */
+#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */
+#define PWM_IER2_ENDTX (0x1u << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */
+#define PWM_IER2_TXBUFE (0x1u << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */
+#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */
+#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */
+#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */
+#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */
+#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */
+#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */
+#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */
+#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */
+#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */
+#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */
+#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */
+#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */
+#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */
+#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */
+#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */
+#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */
+#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */
+/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */
+#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */
+#define PWM_IDR2_ENDTX (0x1u << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */
+#define PWM_IDR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */
+#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */
+#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */
+#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */
+#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */
+#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */
+#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */
+#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */
+#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */
+#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */
+#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */
+#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */
+#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */
+#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */
+#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */
+#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */
+#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */
+#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */
+/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */
+#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */
+#define PWM_IMR2_ENDTX (0x1u << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */
+#define PWM_IMR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */
+#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */
+#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */
+#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */
+#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */
+#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */
+#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */
+#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */
+#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */
+#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */
+#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */
+#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */
+#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */
+#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */
+#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */
+#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */
+#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */
+#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */
+/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */
+#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */
+#define PWM_ISR2_ENDTX (0x1u << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */
+#define PWM_ISR2_TXBUFE (0x1u << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */
+#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */
+#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */
+#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */
+#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */
+#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */
+#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */
+#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */
+#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */
+#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */
+#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */
+#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */
+#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */
+#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */
+#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */
+#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */
+#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */
+#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */
+/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */
+#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */
+#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */
+#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */
+#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */
+#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */
+#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */
+#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */
+#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */
+/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */
+#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */
+#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */
+#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */
+#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */
+#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */
+#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */
+#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */
+#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */
+/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */
+#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */
+#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */
+#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */
+#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */
+#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */
+#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */
+#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */
+#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */
+/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */
+#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */
+#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */
+#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */
+#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */
+#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */
+#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */
+#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */
+#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */
+/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */
+#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */
+#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */
+#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */
+#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */
+#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */
+#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */
+#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */
+#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */
+/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */
+#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */
+#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */
+#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */
+#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */
+#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */
+#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */
+#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */
+#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */
+/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */
+#define PWM_FMR_FPOL_Pos 0
+#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))
+#define PWM_FMR_FMOD_Pos 8
+#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))
+#define PWM_FMR_FFIL_Pos 16
+#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))
+/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */
+#define PWM_FSR_FIV_Pos 0
+#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value (fault input bit varies from 0 to 5) */
+#define PWM_FSR_FS_Pos 8
+#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status (fault input bit varies from 0 to 5) */
+/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */
+#define PWM_FCR_FCLR_Pos 0
+#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear (fault input bit varies from 0 to 5) */
+#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))
+/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */
+#define PWM_FPV_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */
+#define PWM_FPV_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */
+#define PWM_FPV_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */
+#define PWM_FPV_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */
+#define PWM_FPV_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */
+#define PWM_FPV_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */
+#define PWM_FPV_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */
+#define PWM_FPV_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */
+/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */
+#define PWM_FPE_FPE0_Pos 0
+#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) */
+#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)))
+#define PWM_FPE_FPE1_Pos 8
+#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) */
+#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)))
+#define PWM_FPE_FPE2_Pos 16
+#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) */
+#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)))
+#define PWM_FPE_FPE3_Pos 24
+#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) */
+#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)))
+/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */
+#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */
+#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */
+#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */
+#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */
+#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */
+#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */
+#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */
+#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */
+/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */
+#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */
+#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */
+/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */
+#define PWM_WPCR_WPCMD_Pos 0
+#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protect Command */
+#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))
+#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */
+#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */
+#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */
+#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */
+#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */
+#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */
+#define PWM_WPCR_WPKEY_Pos 8
+#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protect Key */
+#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))
+/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */
+#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */
+#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPVSRC_Pos 16
+#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */
+/* -------- PWM_RPR : (PWM Offset: 0x100) Receive Pointer Register -------- */
+#define PWM_RPR_RXPTR_Pos 0
+#define PWM_RPR_RXPTR_Msk (0xffffffffu << PWM_RPR_RXPTR_Pos) /**< \brief (PWM_RPR) Receive Pointer Register */
+#define PWM_RPR_RXPTR(value) ((PWM_RPR_RXPTR_Msk & ((value) << PWM_RPR_RXPTR_Pos)))
+/* -------- PWM_RCR : (PWM Offset: 0x104) Receive Counter Register -------- */
+#define PWM_RCR_RXCTR_Pos 0
+#define PWM_RCR_RXCTR_Msk (0xffffu << PWM_RCR_RXCTR_Pos) /**< \brief (PWM_RCR) Receive Counter Register */
+#define PWM_RCR_RXCTR(value) ((PWM_RCR_RXCTR_Msk & ((value) << PWM_RCR_RXCTR_Pos)))
+/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */
+#define PWM_TPR_TXPTR_Pos 0
+#define PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos) /**< \brief (PWM_TPR) Transmit Counter Register */
+#define PWM_TPR_TXPTR(value) ((PWM_TPR_TXPTR_Msk & ((value) << PWM_TPR_TXPTR_Pos)))
+/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */
+#define PWM_TCR_TXCTR_Pos 0
+#define PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos) /**< \brief (PWM_TCR) Transmit Counter Register */
+#define PWM_TCR_TXCTR(value) ((PWM_TCR_TXCTR_Msk & ((value) << PWM_TCR_TXCTR_Pos)))
+/* -------- PWM_RNPR : (PWM Offset: 0x110) Receive Next Pointer Register -------- */
+#define PWM_RNPR_RXNPTR_Pos 0
+#define PWM_RNPR_RXNPTR_Msk (0xffffffffu << PWM_RNPR_RXNPTR_Pos) /**< \brief (PWM_RNPR) Receive Next Pointer */
+#define PWM_RNPR_RXNPTR(value) ((PWM_RNPR_RXNPTR_Msk & ((value) << PWM_RNPR_RXNPTR_Pos)))
+/* -------- PWM_RNCR : (PWM Offset: 0x114) Receive Next Counter Register -------- */
+#define PWM_RNCR_RXNCTR_Pos 0
+#define PWM_RNCR_RXNCTR_Msk (0xffffu << PWM_RNCR_RXNCTR_Pos) /**< \brief (PWM_RNCR) Receive Next Counter */
+#define PWM_RNCR_RXNCTR(value) ((PWM_RNCR_RXNCTR_Msk & ((value) << PWM_RNCR_RXNCTR_Pos)))
+/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */
+#define PWM_TNPR_TXNPTR_Pos 0
+#define PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos) /**< \brief (PWM_TNPR) Transmit Next Pointer */
+#define PWM_TNPR_TXNPTR(value) ((PWM_TNPR_TXNPTR_Msk & ((value) << PWM_TNPR_TXNPTR_Pos)))
+/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */
+#define PWM_TNCR_TXNCTR_Pos 0
+#define PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos) /**< \brief (PWM_TNCR) Transmit Counter Next */
+#define PWM_TNCR_TXNCTR(value) ((PWM_TNCR_TXNCTR_Msk & ((value) << PWM_TNCR_TXNCTR_Pos)))
+/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */
+#define PWM_PTCR_RXTEN (0x1u << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */
+#define PWM_PTCR_RXTDIS (0x1u << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */
+#define PWM_PTCR_TXTEN (0x1u << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */
+#define PWM_PTCR_TXTDIS (0x1u << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */
+/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */
+#define PWM_PTSR_RXTEN (0x1u << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */
+#define PWM_PTSR_TXTEN (0x1u << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */
+/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */
+#define PWM_CMPV_CV_Pos 0
+#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */
+#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))
+#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */
+/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */
+#define PWM_CMPVUPD_CVUPD_Pos 0
+#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */
+#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))
+#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */
+/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */
+#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */
+#define PWM_CMPM_CTR_Pos 4
+#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */
+#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))
+#define PWM_CMPM_CPR_Pos 8
+#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */
+#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))
+#define PWM_CMPM_CPRCNT_Pos 12
+#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */
+#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))
+#define PWM_CMPM_CUPR_Pos 16
+#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */
+#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))
+#define PWM_CMPM_CUPRCNT_Pos 20
+#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */
+#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))
+/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */
+#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */
+#define PWM_CMPMUPD_CTRUPD_Pos 4
+#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */
+#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))
+#define PWM_CMPMUPD_CPRUPD_Pos 8
+#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */
+#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))
+#define PWM_CMPMUPD_CUPRUPD_Pos 16
+#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */
+#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))
+/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */
+#define PWM_CMR_CPRE_Pos 0
+#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */
+#define   PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master clock */
+#define   PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Master clock/2 */
+#define   PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Master clock/4 */
+#define   PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Master clock/8 */
+#define   PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Master clock/16 */
+#define   PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Master clock/32 */
+#define   PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Master clock/64 */
+#define   PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Master clock/128 */
+#define   PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Master clock/256 */
+#define   PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Master clock/512 */
+#define   PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Master clock/1024 */
+#define   PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */
+#define   PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */
+#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */
+#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */
+#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */
+#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */
+#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */
+#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */
+/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */
+#define PWM_CDTY_CDTY_Pos 0
+#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */
+#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))
+/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */
+#define PWM_CDTYUPD_CDTYUPD_Pos 0
+#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */
+#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))
+/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */
+#define PWM_CPRD_CPRD_Pos 0
+#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */
+#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))
+/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */
+#define PWM_CPRDUPD_CPRDUPD_Pos 0
+#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */
+#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))
+/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */
+#define PWM_CCNT_CNT_Pos 0
+#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */
+/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */
+#define PWM_DT_DTH_Pos 0
+#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */
+#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))
+#define PWM_DT_DTL_Pos 16
+#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */
+#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))
+/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */
+#define PWM_DTUPD_DTHUPD_Pos 0
+#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */
+#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))
+#define PWM_DTUPD_DTLUPD_Pos 16
+#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */
+#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3S8_PWM_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_rstc.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_rstc.h
new file mode 100644
index 000000000..17af99e3e
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_rstc.h
@@ -0,0 +1,73 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_RSTC_COMPONENT_
+#define _SAM3S8_RSTC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Reset Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_RSTC Reset Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Rstc hardware registers */
+typedef struct {
+  WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
+  RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
+  RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
+} Rstc;
+#endif /* __ASSEMBLY__ */
+/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
+#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */
+#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */
+#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */
+#define RSTC_CR_KEY_Pos 24
+#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Password */
+#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
+/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
+#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */
+#define RSTC_SR_RSTTYP_Pos 8
+#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */
+#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
+#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
+/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
+#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */
+#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
+#define RSTC_MR_ERSTL_Pos 8
+#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */
+#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
+#define RSTC_MR_KEY_Pos 24
+#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */
+#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3S8_RSTC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_rtc.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_rtc.h
new file mode 100644
index 000000000..285d88cda
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_rtc.h
@@ -0,0 +1,203 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_RTC_COMPONENT_
+#define _SAM3S8_RTC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Real-time Clock */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_RTC Real-time Clock */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Rtc hardware registers */
+typedef struct {
+  RwReg RTC_CR;     /**< \brief (Rtc Offset: 0x00) Control Register */
+  RwReg RTC_MR;     /**< \brief (Rtc Offset: 0x04) Mode Register */
+  RwReg RTC_TIMR;   /**< \brief (Rtc Offset: 0x08) Time Register */
+  RwReg RTC_CALR;   /**< \brief (Rtc Offset: 0x0C) Calendar Register */
+  RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */
+  RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */
+  RoReg RTC_SR;     /**< \brief (Rtc Offset: 0x18) Status Register */
+  WoReg RTC_SCCR;   /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */
+  WoReg RTC_IER;    /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */
+  WoReg RTC_IDR;    /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */
+  RoReg RTC_IMR;    /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */
+  RoReg RTC_VER;    /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */
+} Rtc;
+#endif /* __ASSEMBLY__ */
+/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
+#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */
+#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */
+#define RTC_CR_TIMEVSEL_Pos 8
+#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */
+#define   RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */
+#define   RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */
+#define   RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */
+#define   RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */
+#define RTC_CR_CALEVSEL_Pos 16
+#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */
+#define   RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */
+#define   RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */
+#define   RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */
+/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
+#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */
+#define RTC_MR_PERSIAN (0x1u << 1) /**< \brief (RTC_MR) PERSIAN Calendar */
+#define RTC_MR_NEGPPM (0x1u << 4) /**< \brief (RTC_MR) NEGative PPM Correction */
+#define RTC_MR_CORRECTION_Pos 8
+#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos) /**< \brief (RTC_MR)  */
+#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos)))
+#define RTC_MR_HIGHPPM (0x1u << 15) /**< \brief (RTC_MR) HIGH PPM Correction */
+#define RTC_MR_OUT0_Pos 16
+#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos) /**< \brief (RTC_MR) RTCOUT0 Output Source Selection */
+#define   RTC_MR_OUT0_NO_WAVE (0x0u << 16) /**< \brief (RTC_MR) no waveform, stuck at '0' */
+#define   RTC_MR_OUT0_FREQ1HZ (0x1u << 16) /**< \brief (RTC_MR) 1 Hz square wave */
+#define   RTC_MR_OUT0_FREQ32HZ (0x2u << 16) /**< \brief (RTC_MR) 32 Hz square wave */
+#define   RTC_MR_OUT0_FREQ64HZ (0x3u << 16) /**< \brief (RTC_MR) 64 Hz square wave */
+#define   RTC_MR_OUT0_FREQ512HZ (0x4u << 16) /**< \brief (RTC_MR) 512 Hz square wave */
+#define   RTC_MR_OUT0_ALARM_TOGGLE (0x5u << 16) /**< \brief (RTC_MR) output toggles when alarm flag rises */
+#define   RTC_MR_OUT0_ALARM_FLAG (0x6u << 16) /**< \brief (RTC_MR) output is a copy of the alarm flag */
+#define   RTC_MR_OUT0_PROG_PULSE (0x7u << 16) /**< \brief (RTC_MR) duty cycle programmable pulse */
+#define RTC_MR_OUT1_Pos 20
+#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos) /**< \brief (RTC_MR) RTCOUT1 Output Source Selection */
+#define   RTC_MR_OUT1_NO_WAVE (0x0u << 20) /**< \brief (RTC_MR) no waveform, stuck at '0' */
+#define   RTC_MR_OUT1_FREQ1HZ (0x1u << 20) /**< \brief (RTC_MR) 1 Hz square wave */
+#define   RTC_MR_OUT1_FREQ32HZ (0x2u << 20) /**< \brief (RTC_MR) 32 Hz square wave */
+#define   RTC_MR_OUT1_FREQ64HZ (0x3u << 20) /**< \brief (RTC_MR) 64 Hz square wave */
+#define   RTC_MR_OUT1_FREQ512HZ (0x4u << 20) /**< \brief (RTC_MR) 512 Hz square wave */
+#define   RTC_MR_OUT1_ALARM_TOGGLE (0x5u << 20) /**< \brief (RTC_MR) output toggles when alarm flag rises */
+#define   RTC_MR_OUT1_ALARM_FLAG (0x6u << 20) /**< \brief (RTC_MR) output is a copy of the alarm flag */
+#define   RTC_MR_OUT1_PROG_PULSE (0x7u << 20) /**< \brief (RTC_MR) duty cycle programmable pulse */
+#define RTC_MR_THIGH_Pos 24
+#define RTC_MR_THIGH_Msk (0x7u << RTC_MR_THIGH_Pos) /**< \brief (RTC_MR) High Duration of the Output Pulse */
+#define   RTC_MR_THIGH_H_31MS (0x0u << 24) /**< \brief (RTC_MR) 31.2 ms */
+#define   RTC_MR_THIGH_H_16MS (0x1u << 24) /**< \brief (RTC_MR) 15.6 ms */
+#define   RTC_MR_THIGH_H_4MS (0x2u << 24) /**< \brief (RTC_MR) 3.91 ms */
+#define   RTC_MR_THIGH_H_967US (0x3u << 24) /**< \brief (RTC_MR) 967 \xb5 s */
+#define   RTC_MR_THIGH_H_488US (0x4u << 24) /**< \brief (RTC_MR) 488 \xb5 s */
+#define   RTC_MR_THIGH_H_122US (0x5u << 24) /**< \brief (RTC_MR) 122 \xb5 s */
+#define   RTC_MR_THIGH_H_30US (0x6u << 24) /**< \brief (RTC_MR) 30.5 \xb5 s */
+#define   RTC_MR_THIGH_H_15US (0x7u << 24) /**< \brief (RTC_MR) 15.2 \xb5 s */
+#define RTC_MR_TPERIOD_Pos 28
+#define RTC_MR_TPERIOD_Msk (0x3u << RTC_MR_TPERIOD_Pos) /**< \brief (RTC_MR) Period of the Output Pulse */
+#define   RTC_MR_TPERIOD_P_1S (0x0u << 28) /**< \brief (RTC_MR) 1 second */
+#define   RTC_MR_TPERIOD_P_500MS (0x1u << 28) /**< \brief (RTC_MR) 500 ms */
+#define   RTC_MR_TPERIOD_P_250MS (0x2u << 28) /**< \brief (RTC_MR) 250 ms */
+#define   RTC_MR_TPERIOD_P_125MS (0x3u << 28) /**< \brief (RTC_MR) 125 ms */
+/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
+#define RTC_TIMR_SEC_Pos 0
+#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */
+#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
+#define RTC_TIMR_MIN_Pos 8
+#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */
+#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
+#define RTC_TIMR_HOUR_Pos 16
+#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */
+#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
+#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */
+/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
+#define RTC_CALR_CENT_Pos 0
+#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */
+#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
+#define RTC_CALR_YEAR_Pos 8
+#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */
+#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
+#define RTC_CALR_MONTH_Pos 16
+#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */
+#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
+#define RTC_CALR_DAY_Pos 21
+#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */
+#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
+#define RTC_CALR_DATE_Pos 24
+#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */
+#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
+/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
+#define RTC_TIMALR_SEC_Pos 0
+#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */
+#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
+#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */
+#define RTC_TIMALR_MIN_Pos 8
+#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */
+#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
+#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */
+#define RTC_TIMALR_HOUR_Pos 16
+#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */
+#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
+#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */
+#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */
+/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
+#define RTC_CALALR_MONTH_Pos 16
+#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */
+#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
+#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */
+#define RTC_CALALR_DATE_Pos 24
+#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */
+#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
+#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */
+/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
+#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */
+#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */
+#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */
+#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */
+#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */
+/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
+#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */
+#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */
+#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */
+#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */
+#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */
+/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
+#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */
+#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */
+#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */
+#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */
+#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */
+/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
+#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */
+#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */
+#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */
+#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */
+#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */
+/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
+#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */
+#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */
+#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */
+#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */
+#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */
+/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
+#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */
+#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */
+#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */
+#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_RTC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_rtt.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_rtt.h
new file mode 100644
index 000000000..a9b965449
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_rtt.h
@@ -0,0 +1,71 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_RTT_COMPONENT_
+#define _SAM3S8_RTT_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Real-time Timer */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_RTT Real-time Timer */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Rtt hardware registers */
+typedef struct {
+  RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */
+  RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */
+  RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */
+  RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */
+} Rtt;
+#endif /* __ASSEMBLY__ */
+/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */
+#define RTT_MR_RTPRES_Pos 0
+#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */
+#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)))
+#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */
+#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */
+#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */
+#define RTT_MR_RTTDIS (0x1u << 20) /**< \brief (RTT_MR) Real-time Timer Disable */
+#define RTT_MR_RTC1HZ (0x1u << 24) /**< \brief (RTT_MR) Real-Time Clock 1Hz Clock Selection */
+/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */
+#define RTT_AR_ALMV_Pos 0
+#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */
+#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)))
+/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */
+#define RTT_VR_CRTV_Pos 0
+#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */
+/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */
+#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */
+#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_RTT_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_smc.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_smc.h
new file mode 100644
index 000000000..8c3050d9e
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_smc.h
@@ -0,0 +1,144 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_SMC_COMPONENT_
+#define _SAM3S8_SMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Static Memory Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_SMC Static Memory Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief SmcCs_number hardware registers */
+typedef struct {
+  RwReg         SMC_SETUP;        /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */
+  RwReg         SMC_PULSE;        /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */
+  RwReg         SMC_CYCLE;        /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */
+  RwReg         SMC_MODE;         /**< \brief (SmcCs_number Offset: 0xC) SMC Mode Register */
+} SmcCs_number;
+/** \brief Smc hardware registers */
+#define SMCCS_NUMBER_NUMBER 5
+typedef struct {
+  SmcCs_number  SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 4 */
+  RoReg         Reserved1[12];
+  RwReg         SMC_OCMS;         /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */
+  WoReg         SMC_KEY1;         /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */
+  WoReg         SMC_KEY2;         /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */
+  RoReg         Reserved2[22];
+  RwReg         SMC_WPMR;         /**< \brief (Smc Offset: 0xE4) SMC Write Protect Mode Register */
+  RoReg         SMC_WPSR;         /**< \brief (Smc Offset: 0xE8) SMC Write Protect Status Register */
+} Smc;
+#endif /* __ASSEMBLY__ */
+/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */
+#define SMC_SETUP_NWE_SETUP_Pos 0
+#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */
+#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))
+#define SMC_SETUP_NCS_WR_SETUP_Pos 8
+#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */
+#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))
+#define SMC_SETUP_NRD_SETUP_Pos 16
+#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */
+#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))
+#define SMC_SETUP_NCS_RD_SETUP_Pos 24
+#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */
+#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))
+/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */
+#define SMC_PULSE_NWE_PULSE_Pos 0
+#define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */
+#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))
+#define SMC_PULSE_NCS_WR_PULSE_Pos 8
+#define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */
+#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))
+#define SMC_PULSE_NRD_PULSE_Pos 16
+#define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */
+#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))
+#define SMC_PULSE_NCS_RD_PULSE_Pos 24
+#define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */
+#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))
+/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */
+#define SMC_CYCLE_NWE_CYCLE_Pos 0
+#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */
+#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))
+#define SMC_CYCLE_NRD_CYCLE_Pos 16
+#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */
+#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))
+/* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */
+#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE)  */
+#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE)  */
+#define SMC_MODE_EXNW_MODE_Pos 4
+#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */
+#define   SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */
+#define   SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */
+#define   SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */
+#define SMC_MODE_DBW_Pos 12
+#define SMC_MODE_DBW_Msk (0x3u << SMC_MODE_DBW_Pos) /**< \brief (SMC_MODE) Data Bus Width */
+#define   SMC_MODE_DBW_8_BIT (0x0u << 12) /**< \brief (SMC_MODE) 8-bit bus */
+#define   SMC_MODE_DBW_16_BIT (0x1u << 12) /**< \brief (SMC_MODE) 16-bit bus */
+#define   SMC_MODE_DBW_32_BIT (0x2u << 12) /**< \brief (SMC_MODE) 32-bit bus */
+#define SMC_MODE_TDF_CYCLES_Pos 16
+#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */
+#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))
+#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */
+#define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */
+#define SMC_MODE_PS_Pos 28
+#define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */
+#define   SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */
+#define   SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */
+#define   SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */
+#define   SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */
+/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */
+#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */
+#define SMC_OCMS_CS0SE (0x1u << 16) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
+#define SMC_OCMS_CS1SE (0x1u << 17) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
+#define SMC_OCMS_CS2SE (0x1u << 18) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
+#define SMC_OCMS_CS3SE (0x1u << 19) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
+/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */
+#define SMC_KEY1_KEY1_Pos 0
+#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */
+#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))
+/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */
+#define SMC_KEY2_KEY2_Pos 0
+#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */
+#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))
+/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protect Mode Register -------- */
+#define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */
+#define SMC_WPMR_WPKEY_Pos 8
+#define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protect KEY */
+#define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos)))
+/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protect Status Register -------- */
+#define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protect Enable */
+#define SMC_WPSR_WPVSRC_Pos 8
+#define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_SMC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_spi.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_spi.h
new file mode 100644
index 000000000..88153749e
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_spi.h
@@ -0,0 +1,227 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_SPI_COMPONENT_
+#define _SAM3S8_SPI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Serial Peripheral Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_SPI Serial Peripheral Interface */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Spi hardware registers */
+typedef struct {
+  WoReg SPI_CR;        /**< \brief (Spi Offset: 0x00) Control Register */
+  RwReg SPI_MR;        /**< \brief (Spi Offset: 0x04) Mode Register */
+  RoReg SPI_RDR;       /**< \brief (Spi Offset: 0x08) Receive Data Register */
+  WoReg SPI_TDR;       /**< \brief (Spi Offset: 0x0C) Transmit Data Register */
+  RoReg SPI_SR;        /**< \brief (Spi Offset: 0x10) Status Register */
+  WoReg SPI_IER;       /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */
+  WoReg SPI_IDR;       /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */
+  RoReg SPI_IMR;       /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */
+  RoReg Reserved1[4];
+  RwReg SPI_CSR[4];    /**< \brief (Spi Offset: 0x30) Chip Select Register */
+  RoReg Reserved2[41];
+  RwReg SPI_WPMR;      /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */
+  RoReg SPI_WPSR;      /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */
+  RoReg Reserved3[5];
+  RwReg SPI_RPR;       /**< \brief (Spi Offset: 0x100) Receive Pointer Register */
+  RwReg SPI_RCR;       /**< \brief (Spi Offset: 0x104) Receive Counter Register */
+  RwReg SPI_TPR;       /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */
+  RwReg SPI_TCR;       /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */
+  RwReg SPI_RNPR;      /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */
+  RwReg SPI_RNCR;      /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */
+  RwReg SPI_TNPR;      /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */
+  RwReg SPI_TNCR;      /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */
+  WoReg SPI_PTCR;      /**< \brief (Spi Offset: 0x120) Transfer Control Register */
+  RoReg SPI_PTSR;      /**< \brief (Spi Offset: 0x124) Transfer Status Register */
+} Spi;
+#endif /* __ASSEMBLY__ */
+/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
+#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */
+#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */
+#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */
+#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */
+/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
+#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */
+#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */
+#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */
+#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */
+#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */
+#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */
+#define SPI_MR_PCS_Pos 16
+#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */
+#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
+#define SPI_MR_DLYBCS_Pos 24
+#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */
+#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
+/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
+#define SPI_RDR_RD_Pos 0
+#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */
+#define SPI_RDR_PCS_Pos 16
+#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */
+/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
+#define SPI_TDR_TD_Pos 0
+#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */
+#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
+#define SPI_TDR_PCS_Pos 16
+#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */
+#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
+#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
+#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */
+#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */
+#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */
+#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */
+#define SPI_SR_ENDRX (0x1u << 4) /**< \brief (SPI_SR) End of RX buffer */
+#define SPI_SR_ENDTX (0x1u << 5) /**< \brief (SPI_SR) End of TX buffer */
+#define SPI_SR_RXBUFF (0x1u << 6) /**< \brief (SPI_SR) RX Buffer Full */
+#define SPI_SR_TXBUFE (0x1u << 7) /**< \brief (SPI_SR) TX Buffer Empty */
+#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */
+#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */
+#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */
+#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
+#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */
+#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */
+#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */
+#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */
+#define SPI_IER_ENDRX (0x1u << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */
+#define SPI_IER_ENDTX (0x1u << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */
+#define SPI_IER_RXBUFF (0x1u << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */
+#define SPI_IER_TXBUFE (0x1u << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */
+#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */
+#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */
+#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */
+#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */
+#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */
+#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */
+#define SPI_IDR_ENDRX (0x1u << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */
+#define SPI_IDR_ENDTX (0x1u << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */
+#define SPI_IDR_RXBUFF (0x1u << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */
+#define SPI_IDR_TXBUFE (0x1u << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */
+#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */
+#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */
+#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */
+/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
+#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */
+#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */
+#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */
+#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */
+#define SPI_IMR_ENDRX (0x1u << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */
+#define SPI_IMR_ENDTX (0x1u << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */
+#define SPI_IMR_RXBUFF (0x1u << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */
+#define SPI_IMR_TXBUFE (0x1u << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */
+#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */
+#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */
+#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */
+/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
+#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */
+#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */
+#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_BITS_Pos 4
+#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */
+#define   SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */
+#define   SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */
+#define   SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */
+#define   SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */
+#define   SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */
+#define   SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */
+#define   SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */
+#define   SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */
+#define   SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */
+#define SPI_CSR_SCBR_Pos 8
+#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */
+#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
+#define SPI_CSR_DLYBS_Pos 16
+#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */
+#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
+#define SPI_CSR_DLYBCT_Pos 24
+#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */
+#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
+/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */
+#define SPI_WPMR_SPIWPEN (0x1u << 0) /**< \brief (SPI_WPMR) SPI Write Protection Enable */
+#define SPI_WPMR_SPIWPKEY_Pos 8
+#define SPI_WPMR_SPIWPKEY_Msk (0xffffffu << SPI_WPMR_SPIWPKEY_Pos) /**< \brief (SPI_WPMR) SPI Write Protection Key Password */
+#define SPI_WPMR_SPIWPKEY(value) ((SPI_WPMR_SPIWPKEY_Msk & ((value) << SPI_WPMR_SPIWPKEY_Pos)))
+/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
+#define SPI_WPSR_SPIWPVS_Pos 0
+#define SPI_WPSR_SPIWPVS_Msk (0x7u << SPI_WPSR_SPIWPVS_Pos) /**< \brief (SPI_WPSR) SPI Write Protection Violation Status */
+#define SPI_WPSR_SPIWPVSRC_Pos 8
+#define SPI_WPSR_SPIWPVSRC_Msk (0xffu << SPI_WPSR_SPIWPVSRC_Pos) /**< \brief (SPI_WPSR) SPI Write Protection Violation Source */
+/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */
+#define SPI_RPR_RXPTR_Pos 0
+#define SPI_RPR_RXPTR_Msk (0xffffffffu << SPI_RPR_RXPTR_Pos) /**< \brief (SPI_RPR) Receive Pointer Register */
+#define SPI_RPR_RXPTR(value) ((SPI_RPR_RXPTR_Msk & ((value) << SPI_RPR_RXPTR_Pos)))
+/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */
+#define SPI_RCR_RXCTR_Pos 0
+#define SPI_RCR_RXCTR_Msk (0xffffu << SPI_RCR_RXCTR_Pos) /**< \brief (SPI_RCR) Receive Counter Register */
+#define SPI_RCR_RXCTR(value) ((SPI_RCR_RXCTR_Msk & ((value) << SPI_RCR_RXCTR_Pos)))
+/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */
+#define SPI_TPR_TXPTR_Pos 0
+#define SPI_TPR_TXPTR_Msk (0xffffffffu << SPI_TPR_TXPTR_Pos) /**< \brief (SPI_TPR) Transmit Counter Register */
+#define SPI_TPR_TXPTR(value) ((SPI_TPR_TXPTR_Msk & ((value) << SPI_TPR_TXPTR_Pos)))
+/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */
+#define SPI_TCR_TXCTR_Pos 0
+#define SPI_TCR_TXCTR_Msk (0xffffu << SPI_TCR_TXCTR_Pos) /**< \brief (SPI_TCR) Transmit Counter Register */
+#define SPI_TCR_TXCTR(value) ((SPI_TCR_TXCTR_Msk & ((value) << SPI_TCR_TXCTR_Pos)))
+/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */
+#define SPI_RNPR_RXNPTR_Pos 0
+#define SPI_RNPR_RXNPTR_Msk (0xffffffffu << SPI_RNPR_RXNPTR_Pos) /**< \brief (SPI_RNPR) Receive Next Pointer */
+#define SPI_RNPR_RXNPTR(value) ((SPI_RNPR_RXNPTR_Msk & ((value) << SPI_RNPR_RXNPTR_Pos)))
+/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */
+#define SPI_RNCR_RXNCTR_Pos 0
+#define SPI_RNCR_RXNCTR_Msk (0xffffu << SPI_RNCR_RXNCTR_Pos) /**< \brief (SPI_RNCR) Receive Next Counter */
+#define SPI_RNCR_RXNCTR(value) ((SPI_RNCR_RXNCTR_Msk & ((value) << SPI_RNCR_RXNCTR_Pos)))
+/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define SPI_TNPR_TXNPTR_Pos 0
+#define SPI_TNPR_TXNPTR_Msk (0xffffffffu << SPI_TNPR_TXNPTR_Pos) /**< \brief (SPI_TNPR) Transmit Next Pointer */
+#define SPI_TNPR_TXNPTR(value) ((SPI_TNPR_TXNPTR_Msk & ((value) << SPI_TNPR_TXNPTR_Pos)))
+/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define SPI_TNCR_TXNCTR_Pos 0
+#define SPI_TNCR_TXNCTR_Msk (0xffffu << SPI_TNCR_TXNCTR_Pos) /**< \brief (SPI_TNCR) Transmit Counter Next */
+#define SPI_TNCR_TXNCTR(value) ((SPI_TNCR_TXNCTR_Msk & ((value) << SPI_TNCR_TXNCTR_Pos)))
+/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */
+#define SPI_PTCR_RXTEN (0x1u << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */
+#define SPI_PTCR_RXTDIS (0x1u << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */
+#define SPI_PTCR_TXTEN (0x1u << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */
+#define SPI_PTCR_TXTDIS (0x1u << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */
+/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */
+#define SPI_PTSR_RXTEN (0x1u << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */
+#define SPI_PTSR_TXTEN (0x1u << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_SPI_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_ssc.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_ssc.h
new file mode 100644
index 000000000..ffaed3b56
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_ssc.h
@@ -0,0 +1,337 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_SSC_COMPONENT_
+#define _SAM3S8_SSC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Synchronous Serial Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_SSC Synchronous Serial Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Ssc hardware registers */
+typedef struct {
+  WoReg SSC_CR;        /**< \brief (Ssc Offset: 0x0) Control Register */
+  RwReg SSC_CMR;       /**< \brief (Ssc Offset: 0x4) Clock Mode Register */
+  RoReg Reserved1[2];
+  RwReg SSC_RCMR;      /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */
+  RwReg SSC_RFMR;      /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */
+  RwReg SSC_TCMR;      /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */
+  RwReg SSC_TFMR;      /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */
+  RoReg SSC_RHR;       /**< \brief (Ssc Offset: 0x20) Receive Holding Register */
+  WoReg SSC_THR;       /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */
+  RoReg Reserved2[2];
+  RoReg SSC_RSHR;      /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */
+  RwReg SSC_TSHR;      /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */
+  RwReg SSC_RC0R;      /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */
+  RwReg SSC_RC1R;      /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */
+  RoReg SSC_SR;        /**< \brief (Ssc Offset: 0x40) Status Register */
+  WoReg SSC_IER;       /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */
+  WoReg SSC_IDR;       /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */
+  RoReg SSC_IMR;       /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */
+  RoReg Reserved3[37];
+  RwReg SSC_WPMR;      /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */
+  RoReg SSC_WPSR;      /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved4[5];
+  RwReg SSC_RPR;       /**< \brief (Ssc Offset: 0x100) Receive Pointer Register */
+  RwReg SSC_RCR;       /**< \brief (Ssc Offset: 0x104) Receive Counter Register */
+  RwReg SSC_TPR;       /**< \brief (Ssc Offset: 0x108) Transmit Pointer Register */
+  RwReg SSC_TCR;       /**< \brief (Ssc Offset: 0x10C) Transmit Counter Register */
+  RwReg SSC_RNPR;      /**< \brief (Ssc Offset: 0x110) Receive Next Pointer Register */
+  RwReg SSC_RNCR;      /**< \brief (Ssc Offset: 0x114) Receive Next Counter Register */
+  RwReg SSC_TNPR;      /**< \brief (Ssc Offset: 0x118) Transmit Next Pointer Register */
+  RwReg SSC_TNCR;      /**< \brief (Ssc Offset: 0x11C) Transmit Next Counter Register */
+  WoReg SSC_PTCR;      /**< \brief (Ssc Offset: 0x120) Transfer Control Register */
+  RoReg SSC_PTSR;      /**< \brief (Ssc Offset: 0x124) Transfer Status Register */
+} Ssc;
+#endif /* __ASSEMBLY__ */
+/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */
+#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */
+#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */
+#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */
+#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */
+#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */
+/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */
+#define SSC_CMR_DIV_Pos 0
+#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */
+#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))
+/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */
+#define SSC_RCMR_CKS_Pos 0
+#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */
+#define   SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */
+#define   SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */
+#define   SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */
+#define SSC_RCMR_CKO_Pos 2
+#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */
+#define   SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None */
+#define   SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock */
+#define   SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
+#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */
+#define SSC_RCMR_CKG_Pos 6
+#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */
+#define   SSC_RCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_RCMR) None */
+#define   SSC_RCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_RCMR) Continuous Receive Clock */
+#define   SSC_RCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
+#define SSC_RCMR_START_Pos 8
+#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */
+#define   SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
+#define   SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */
+#define   SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */
+#define   SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */
+#define   SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */
+#define   SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */
+#define   SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */
+#define   SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */
+#define   SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */
+#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */
+#define SSC_RCMR_STTDLY_Pos 16
+#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */
+#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))
+#define SSC_RCMR_PERIOD_Pos 24
+#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */
+#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))
+/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */
+#define SSC_RFMR_DATLEN_Pos 0
+#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */
+#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))
+#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */
+#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */
+#define SSC_RFMR_DATNB_Pos 8
+#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */
+#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))
+#define SSC_RFMR_FSLEN_Pos 16
+#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */
+#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))
+#define SSC_RFMR_FSOS_Pos 20
+#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */
+#define   SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None */
+#define   SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse */
+#define   SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse */
+#define   SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer */
+#define   SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer */
+#define   SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer */
+#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */
+#define   SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */
+#define   SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */
+#define SSC_RFMR_FSLEN_EXT_Pos 28
+#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */
+#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))
+/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */
+#define SSC_TCMR_CKS_Pos 0
+#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */
+#define   SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */
+#define   SSC_TCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_TCMR) TK Clock signal */
+#define   SSC_TCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_TCMR) RK pin */
+#define SSC_TCMR_CKO_Pos 2
+#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */
+#define   SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None */
+#define   SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Receive Clock */
+#define   SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers */
+#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */
+#define SSC_TCMR_CKG_Pos 6
+#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */
+#define   SSC_TCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_TCMR) None */
+#define   SSC_TCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */
+#define   SSC_TCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */
+#define SSC_TCMR_START_Pos 8
+#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */
+#define   SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. */
+#define   SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */
+#define   SSC_TCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */
+#define   SSC_TCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */
+#define   SSC_TCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */
+#define   SSC_TCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */
+#define   SSC_TCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */
+#define   SSC_TCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */
+#define   SSC_TCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_TCMR) Compare 0 */
+#define SSC_TCMR_STTDLY_Pos 16
+#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */
+#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))
+#define SSC_TCMR_PERIOD_Pos 24
+#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */
+#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))
+/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */
+#define SSC_TFMR_DATLEN_Pos 0
+#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */
+#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))
+#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */
+#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */
+#define SSC_TFMR_DATNB_Pos 8
+#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per frame */
+#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))
+#define SSC_TFMR_FSLEN_Pos 16
+#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */
+#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))
+#define SSC_TFMR_FSOS_Pos 20
+#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */
+#define   SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None */
+#define   SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse */
+#define   SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse */
+#define   SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */
+#define   SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */
+#define   SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */
+#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */
+#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */
+#define   SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */
+#define   SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */
+#define SSC_TFMR_FSLEN_EXT_Pos 28
+#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */
+#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))
+/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */
+#define SSC_RHR_RDAT_Pos 0
+#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */
+/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */
+#define SSC_THR_TDAT_Pos 0
+#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */
+#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))
+/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */
+#define SSC_RSHR_RSDAT_Pos 0
+#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */
+/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */
+#define SSC_TSHR_TSDAT_Pos 0
+#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */
+#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))
+/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */
+#define SSC_RC0R_CP0_Pos 0
+#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */
+#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))
+/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */
+#define SSC_RC1R_CP1_Pos 0
+#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */
+#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))
+/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */
+#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */
+#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */
+#define SSC_SR_ENDTX (0x1u << 2) /**< \brief (SSC_SR) End of Transmission */
+#define SSC_SR_TXBUFE (0x1u << 3) /**< \brief (SSC_SR) Transmit Buffer Empty */
+#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */
+#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */
+#define SSC_SR_ENDRX (0x1u << 6) /**< \brief (SSC_SR) End of Reception */
+#define SSC_SR_RXBUFF (0x1u << 7) /**< \brief (SSC_SR) Receive Buffer Full */
+#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */
+#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */
+#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */
+#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */
+#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */
+#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */
+/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */
+#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */
+#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */
+#define SSC_IER_ENDTX (0x1u << 2) /**< \brief (SSC_IER) End of Transmission Interrupt Enable */
+#define SSC_IER_TXBUFE (0x1u << 3) /**< \brief (SSC_IER) Transmit Buffer Empty Interrupt Enable */
+#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */
+#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */
+#define SSC_IER_ENDRX (0x1u << 6) /**< \brief (SSC_IER) End of Reception Interrupt Enable */
+#define SSC_IER_RXBUFF (0x1u << 7) /**< \brief (SSC_IER) Receive Buffer Full Interrupt Enable */
+#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */
+#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */
+#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */
+#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */
+/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */
+#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */
+#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */
+#define SSC_IDR_ENDTX (0x1u << 2) /**< \brief (SSC_IDR) End of Transmission Interrupt Disable */
+#define SSC_IDR_TXBUFE (0x1u << 3) /**< \brief (SSC_IDR) Transmit Buffer Empty Interrupt Disable */
+#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */
+#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */
+#define SSC_IDR_ENDRX (0x1u << 6) /**< \brief (SSC_IDR) End of Reception Interrupt Disable */
+#define SSC_IDR_RXBUFF (0x1u << 7) /**< \brief (SSC_IDR) Receive Buffer Full Interrupt Disable */
+#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */
+#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */
+#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */
+#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */
+/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */
+#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */
+#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */
+#define SSC_IMR_ENDTX (0x1u << 2) /**< \brief (SSC_IMR) End of Transmission Interrupt Mask */
+#define SSC_IMR_TXBUFE (0x1u << 3) /**< \brief (SSC_IMR) Transmit Buffer Empty Interrupt Mask */
+#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */
+#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */
+#define SSC_IMR_ENDRX (0x1u << 6) /**< \brief (SSC_IMR) End of Reception Interrupt Mask */
+#define SSC_IMR_RXBUFF (0x1u << 7) /**< \brief (SSC_IMR) Receive Buffer Full Interrupt Mask */
+#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */
+#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */
+#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */
+#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */
+/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */
+#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protect Enable */
+#define SSC_WPMR_WPKEY_Pos 8
+#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protect KEY */
+#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)))
+/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */
+#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */
+#define SSC_WPSR_WPVSRC_Pos 8
+#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */
+/* -------- SSC_RPR : (SSC Offset: 0x100) Receive Pointer Register -------- */
+#define SSC_RPR_RXPTR_Pos 0
+#define SSC_RPR_RXPTR_Msk (0xffffffffu << SSC_RPR_RXPTR_Pos) /**< \brief (SSC_RPR) Receive Pointer Register */
+#define SSC_RPR_RXPTR(value) ((SSC_RPR_RXPTR_Msk & ((value) << SSC_RPR_RXPTR_Pos)))
+/* -------- SSC_RCR : (SSC Offset: 0x104) Receive Counter Register -------- */
+#define SSC_RCR_RXCTR_Pos 0
+#define SSC_RCR_RXCTR_Msk (0xffffu << SSC_RCR_RXCTR_Pos) /**< \brief (SSC_RCR) Receive Counter Register */
+#define SSC_RCR_RXCTR(value) ((SSC_RCR_RXCTR_Msk & ((value) << SSC_RCR_RXCTR_Pos)))
+/* -------- SSC_TPR : (SSC Offset: 0x108) Transmit Pointer Register -------- */
+#define SSC_TPR_TXPTR_Pos 0
+#define SSC_TPR_TXPTR_Msk (0xffffffffu << SSC_TPR_TXPTR_Pos) /**< \brief (SSC_TPR) Transmit Counter Register */
+#define SSC_TPR_TXPTR(value) ((SSC_TPR_TXPTR_Msk & ((value) << SSC_TPR_TXPTR_Pos)))
+/* -------- SSC_TCR : (SSC Offset: 0x10C) Transmit Counter Register -------- */
+#define SSC_TCR_TXCTR_Pos 0
+#define SSC_TCR_TXCTR_Msk (0xffffu << SSC_TCR_TXCTR_Pos) /**< \brief (SSC_TCR) Transmit Counter Register */
+#define SSC_TCR_TXCTR(value) ((SSC_TCR_TXCTR_Msk & ((value) << SSC_TCR_TXCTR_Pos)))
+/* -------- SSC_RNPR : (SSC Offset: 0x110) Receive Next Pointer Register -------- */
+#define SSC_RNPR_RXNPTR_Pos 0
+#define SSC_RNPR_RXNPTR_Msk (0xffffffffu << SSC_RNPR_RXNPTR_Pos) /**< \brief (SSC_RNPR) Receive Next Pointer */
+#define SSC_RNPR_RXNPTR(value) ((SSC_RNPR_RXNPTR_Msk & ((value) << SSC_RNPR_RXNPTR_Pos)))
+/* -------- SSC_RNCR : (SSC Offset: 0x114) Receive Next Counter Register -------- */
+#define SSC_RNCR_RXNCTR_Pos 0
+#define SSC_RNCR_RXNCTR_Msk (0xffffu << SSC_RNCR_RXNCTR_Pos) /**< \brief (SSC_RNCR) Receive Next Counter */
+#define SSC_RNCR_RXNCTR(value) ((SSC_RNCR_RXNCTR_Msk & ((value) << SSC_RNCR_RXNCTR_Pos)))
+/* -------- SSC_TNPR : (SSC Offset: 0x118) Transmit Next Pointer Register -------- */
+#define SSC_TNPR_TXNPTR_Pos 0
+#define SSC_TNPR_TXNPTR_Msk (0xffffffffu << SSC_TNPR_TXNPTR_Pos) /**< \brief (SSC_TNPR) Transmit Next Pointer */
+#define SSC_TNPR_TXNPTR(value) ((SSC_TNPR_TXNPTR_Msk & ((value) << SSC_TNPR_TXNPTR_Pos)))
+/* -------- SSC_TNCR : (SSC Offset: 0x11C) Transmit Next Counter Register -------- */
+#define SSC_TNCR_TXNCTR_Pos 0
+#define SSC_TNCR_TXNCTR_Msk (0xffffu << SSC_TNCR_TXNCTR_Pos) /**< \brief (SSC_TNCR) Transmit Counter Next */
+#define SSC_TNCR_TXNCTR(value) ((SSC_TNCR_TXNCTR_Msk & ((value) << SSC_TNCR_TXNCTR_Pos)))
+/* -------- SSC_PTCR : (SSC Offset: 0x120) Transfer Control Register -------- */
+#define SSC_PTCR_RXTEN (0x1u << 0) /**< \brief (SSC_PTCR) Receiver Transfer Enable */
+#define SSC_PTCR_RXTDIS (0x1u << 1) /**< \brief (SSC_PTCR) Receiver Transfer Disable */
+#define SSC_PTCR_TXTEN (0x1u << 8) /**< \brief (SSC_PTCR) Transmitter Transfer Enable */
+#define SSC_PTCR_TXTDIS (0x1u << 9) /**< \brief (SSC_PTCR) Transmitter Transfer Disable */
+/* -------- SSC_PTSR : (SSC Offset: 0x124) Transfer Status Register -------- */
+#define SSC_PTSR_RXTEN (0x1u << 0) /**< \brief (SSC_PTSR) Receiver Transfer Enable */
+#define SSC_PTSR_TXTEN (0x1u << 8) /**< \brief (SSC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_SSC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_supc.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_supc.h
new file mode 100644
index 000000000..609e2bf4b
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_supc.h
@@ -0,0 +1,322 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_SUPC_COMPONENT_
+#define _SAM3S8_SUPC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Supply Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_SUPC Supply Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Supc hardware registers */
+typedef struct {
+  WoReg SUPC_CR;   /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */
+  RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */
+  RwReg SUPC_MR;   /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */
+  RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */
+  RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */
+  RoReg SUPC_SR;   /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */
+} Supc;
+#endif /* __ASSEMBLY__ */
+/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */
+#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */
+#define   SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */
+#define   SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */
+#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */
+#define   SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */
+#define   SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */
+#define SUPC_CR_KEY_Pos 24
+#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */
+#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))
+/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */
+#define SUPC_SMMR_SMTH_Pos 0
+#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */
+#define   SUPC_SMMR_SMTH_1_9V (0x0u << 0) /**< \brief (SUPC_SMMR) 1.9 V */
+#define   SUPC_SMMR_SMTH_2_0V (0x1u << 0) /**< \brief (SUPC_SMMR) 2.0 V */
+#define   SUPC_SMMR_SMTH_2_1V (0x2u << 0) /**< \brief (SUPC_SMMR) 2.1 V */
+#define   SUPC_SMMR_SMTH_2_2V (0x3u << 0) /**< \brief (SUPC_SMMR) 2.2 V */
+#define   SUPC_SMMR_SMTH_2_3V (0x4u << 0) /**< \brief (SUPC_SMMR) 2.3 V */
+#define   SUPC_SMMR_SMTH_2_4V (0x5u << 0) /**< \brief (SUPC_SMMR) 2.4 V */
+#define   SUPC_SMMR_SMTH_2_5V (0x6u << 0) /**< \brief (SUPC_SMMR) 2.5 V */
+#define   SUPC_SMMR_SMTH_2_6V (0x7u << 0) /**< \brief (SUPC_SMMR) 2.6 V */
+#define   SUPC_SMMR_SMTH_2_7V (0x8u << 0) /**< \brief (SUPC_SMMR) 2.7 V */
+#define   SUPC_SMMR_SMTH_2_8V (0x9u << 0) /**< \brief (SUPC_SMMR) 2.8 V */
+#define   SUPC_SMMR_SMTH_2_9V (0xAu << 0) /**< \brief (SUPC_SMMR) 2.9 V */
+#define   SUPC_SMMR_SMTH_3_0V (0xBu << 0) /**< \brief (SUPC_SMMR) 3.0 V */
+#define   SUPC_SMMR_SMTH_3_1V (0xCu << 0) /**< \brief (SUPC_SMMR) 3.1 V */
+#define   SUPC_SMMR_SMTH_3_2V (0xDu << 0) /**< \brief (SUPC_SMMR) 3.2 V */
+#define   SUPC_SMMR_SMTH_3_3V (0xEu << 0) /**< \brief (SUPC_SMMR) 3.3 V */
+#define   SUPC_SMMR_SMTH_3_4V (0xFu << 0) /**< \brief (SUPC_SMMR) 3.4 V */
+#define SUPC_SMMR_SMSMPL_Pos 8
+#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */
+#define   SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */
+#define   SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */
+#define   SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */
+#define   SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */
+#define   SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */
+#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */
+#define   SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */
+#define   SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */
+#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */
+#define   SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */
+#define   SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */
+/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */
+#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */
+#define   SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */
+#define   SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */
+#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */
+#define   SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */
+#define   SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */
+#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */
+#define   SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Voltage Regulator is not used */
+#define   SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator is used */
+#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */
+#define   SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */
+#define   SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */
+#define SUPC_MR_KEY_Pos 24
+#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */
+#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))
+/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */
+#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */
+#define   SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */
+#define   SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */
+#define   SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */
+#define   SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */
+#define   SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */
+#define   SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_LPDBCEN0 (0x1u << 5) /**< \brief (SUPC_WUMR) Low power Debouncer ENable WKUP0 */
+#define   SUPC_WUMR_LPDBCEN0_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUMR) the WKUP0 input pin is not connected with low power debouncer. */
+#define   SUPC_WUMR_LPDBCEN0_ENABLE (0x1u << 5) /**< \brief (SUPC_WUMR) the WKUP0 input pin is connected with low power debouncer and can force the a core wake up. */
+#define SUPC_WUMR_LPDBCEN1 (0x1u << 6) /**< \brief (SUPC_WUMR) Low power Debouncer ENable WKUP1 */
+#define   SUPC_WUMR_LPDBCEN1_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUMR) the WKUP1input pin is not connected with low power debouncer. */
+#define   SUPC_WUMR_LPDBCEN1_ENABLE (0x1u << 6) /**< \brief (SUPC_WUMR) the WKUP1 input pin is connected with low power debouncer and can force the a core wake up. */
+#define SUPC_WUMR_LPDBCCLR (0x1u << 7) /**< \brief (SUPC_WUMR) Low power Debouncer Clear */
+#define   SUPC_WUMR_LPDBCCLR_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUMR) a low power debounce event does not create an immediate clear on half GPBR registers. */
+#define   SUPC_WUMR_LPDBCCLR_ENABLE (0x1u << 7) /**< \brief (SUPC_WUMR) a low power debounce event on WKUP0 or WKUP1 generates an immediate clear on half GPBR registers. */
+#define SUPC_WUMR_WKUPDBC_Pos 12
+#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer Period */
+#define   SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
+#define   SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */
+#define SUPC_WUMR_LPDBC_Pos 16
+#define SUPC_WUMR_LPDBC_Msk (0x7u << SUPC_WUMR_LPDBC_Pos) /**< \brief (SUPC_WUMR) Low Power DeBounCer Period */
+#define   SUPC_WUMR_LPDBC_DISABLE (0x0u << 16) /**< \brief (SUPC_WUMR) Disable the low power debouncer. */
+#define   SUPC_WUMR_LPDBC_2_RTCOUT0 (0x1u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 2 RTCOUT0 periods */
+#define   SUPC_WUMR_LPDBC_3_RTCOUT0 (0x2u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 3 RTCOUT0 periods */
+#define   SUPC_WUMR_LPDBC_4_RTCOUT0 (0x3u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 4 RTCOUT0 periods */
+#define   SUPC_WUMR_LPDBC_5_RTCOUT0 (0x4u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 5 RTCOUT0 periods */
+#define   SUPC_WUMR_LPDBC_6_RTCOUT0 (0x5u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 6 RTCOUT0 periods */
+#define   SUPC_WUMR_LPDBC_7_RTCOUT0 (0x6u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 7 RTCOUT0 periods */
+#define   SUPC_WUMR_LPDBC_8_RTCOUT0 (0x7u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 8 RTCOUT0 periods */
+/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */
+#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */
+#define   SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */
+#define   SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */
+#define   SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */
+#define   SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */
+#define   SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */
+#define   SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */
+#define   SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */
+#define   SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */
+#define   SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */
+#define   SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */
+#define   SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */
+#define   SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */
+#define   SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */
+#define   SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */
+#define   SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */
+#define   SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */
+#define   SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */
+#define   SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */
+#define   SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */
+#define   SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */
+#define   SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */
+#define   SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */
+#define   SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */
+#define   SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */
+#define   SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */
+#define   SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */
+#define   SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */
+#define   SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */
+#define   SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */
+#define   SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */
+#define   SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */
+#define   SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */
+#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */
+#define   SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */
+#define   SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */
+#define   SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */
+#define   SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */
+#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */
+#define   SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define   SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */
+#define   SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */
+#define   SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */
+#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */
+#define   SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */
+#define   SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */
+#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */
+#define   SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */
+#define   SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */
+#define SUPC_SR_LPDBCS0 (0x1u << 13) /**< \brief (SUPC_SR) Low Power Debouncer Wake Up Status on WKUP0 */
+#define   SUPC_SR_LPDBCS0_NO (0x0u << 13) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_LPDBCS0_PRESENT (0x1u << 13) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_LPDBCS1 (0x1u << 14) /**< \brief (SUPC_SR) Low Power Debouncer Wake Up Status on WKUP1 */
+#define   SUPC_SR_LPDBCS1_NO (0x0u << 14) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_LPDBCS1_PRESENT (0x1u << 14) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */
+#define   SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */
+#define   SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */
+#define   SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */
+#define   SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */
+#define   SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */
+#define   SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */
+#define   SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */
+#define   SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */
+#define   SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */
+#define   SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */
+#define   SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */
+#define   SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */
+#define   SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */
+#define   SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */
+#define   SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */
+#define   SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_SUPC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_tc.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_tc.h
new file mode 100644
index 000000000..0a209e177
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_tc.h
@@ -0,0 +1,303 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_TC_COMPONENT_
+#define _SAM3S8_TC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Timer Counter */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_TC Timer Counter */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief TcChannel hardware registers */
+typedef struct {
+  RwReg      TC_CCR;        /**< \brief (TcChannel Offset: 0x0) Channel Control Register */
+  RwReg      TC_CMR;        /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */
+  RwReg      TC_SMMR;       /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */
+  RoReg      Reserved1[1];
+  RwReg      TC_CV;         /**< \brief (TcChannel Offset: 0x10) Counter Value */
+  RwReg      TC_RA;         /**< \brief (TcChannel Offset: 0x14) Register A */
+  RwReg      TC_RB;         /**< \brief (TcChannel Offset: 0x18) Register B */
+  RwReg      TC_RC;         /**< \brief (TcChannel Offset: 0x1C) Register C */
+  RwReg      TC_SR;         /**< \brief (TcChannel Offset: 0x20) Status Register */
+  RwReg      TC_IER;        /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
+  RwReg      TC_IDR;        /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
+  RwReg      TC_IMR;        /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */
+  RoReg      Reserved2[4];
+} TcChannel;
+/** \brief Tc hardware registers */
+#define TCCHANNEL_NUMBER 3
+typedef struct {
+  TcChannel  TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */
+  WoReg      TC_BCR;        /**< \brief (Tc Offset: 0xC0) Block Control Register */
+  RwReg      TC_BMR;        /**< \brief (Tc Offset: 0xC4) Block Mode Register */
+  WoReg      TC_QIER;       /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */
+  WoReg      TC_QIDR;       /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */
+  RoReg      TC_QIMR;       /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */
+  RoReg      TC_QISR;       /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */
+  RwReg      TC_FMR;        /**< \brief (Tc Offset: 0xD8) Fault Mode Register */
+  RoReg      Reserved1[2];
+  RwReg      TC_WPMR;       /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */
+} Tc;
+#endif /* __ASSEMBLY__ */
+/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */
+#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */
+#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */
+#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */
+/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */
+#define TC_CMR_TCCLKS_Pos 0
+#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */
+#define   TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */
+#define   TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */
+#define   TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */
+#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */
+#define TC_CMR_BURST_Pos 4
+#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */
+#define   TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define   TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */
+#define   TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */
+#define   TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */
+#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */
+#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */
+#define TC_CMR_ETRGEDG_Pos 8
+#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */
+#define   TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define   TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define   TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define   TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */
+#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */
+#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */
+#define TC_CMR_LDRA_Pos 16
+#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */
+#define   TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define   TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define   TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define   TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_LDRB_Pos 18
+#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */
+#define   TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define   TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define   TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define   TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */
+#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */
+#define TC_CMR_EEVTEDG_Pos 8
+#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */
+#define   TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */
+#define   TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define   TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define   TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_EEVT_Pos 10
+#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */
+#define   TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */
+#define   TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */
+#define   TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */
+#define   TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */
+#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */
+#define TC_CMR_WAVSEL_Pos 13
+#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */
+#define   TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */
+#define TC_CMR_ACPA_Pos 16
+#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */
+#define   TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ACPC_Pos 18
+#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */
+#define   TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_AEEVT_Pos 20
+#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */
+#define   TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */
+#define   TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ASWTRG_Pos 22
+#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */
+#define   TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPB_Pos 24
+#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */
+#define   TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPC_Pos 26
+#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */
+#define   TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BEEVT_Pos 28
+#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */
+#define   TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BSWTRG_Pos 30
+#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */
+#define   TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */
+/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */
+#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */
+#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) DOWN Count */
+/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */
+#define TC_CV_CV_Pos 0
+#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */
+/* -------- TC_RA : (TC Offset: N/A) Register A -------- */
+#define TC_RA_RA_Pos 0
+#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */
+#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))
+/* -------- TC_RB : (TC Offset: N/A) Register B -------- */
+#define TC_RB_RB_Pos 0
+#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */
+#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))
+/* -------- TC_RC : (TC Offset: N/A) Register C -------- */
+#define TC_RC_RC_Pos 0
+#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */
+#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))
+/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */
+#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */
+#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */
+#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */
+#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */
+#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */
+#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */
+#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */
+#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */
+#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */
+#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */
+#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */
+/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */
+#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */
+#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */
+#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */
+#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */
+#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */
+#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */
+#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */
+#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */
+/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */
+#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */
+#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */
+#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */
+#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */
+#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */
+#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */
+#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */
+#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */
+/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */
+#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */
+#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */
+#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */
+#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */
+#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */
+#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */
+#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */
+#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */
+/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
+#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */
+/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
+#define TC_BMR_TC0XC0S_Pos 0
+#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */
+#define   TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */
+#define   TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */
+#define   TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */
+#define TC_BMR_TC1XC1S_Pos 2
+#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */
+#define   TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */
+#define   TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */
+#define   TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */
+#define TC_BMR_TC2XC2S_Pos 4
+#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */
+#define   TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */
+#define   TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */
+#define   TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */
+#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */
+#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */
+#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */
+#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */
+#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */
+#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */
+#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */
+#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */
+#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */
+#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */
+#define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR)  */
+#define TC_BMR_MAXFILT_Pos 20
+#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */
+#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))
+/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */
+#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */
+#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */
+#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */
+/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */
+#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */
+#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */
+#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */
+/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */
+#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */
+#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */
+#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */
+/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */
+#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */
+#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */
+#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */
+#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */
+/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */
+#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */
+#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */
+/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */
+#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protect Enable */
+#define TC_WPMR_WPKEY_Pos 8
+#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protect KEY */
+#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3S8_TC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_twi.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_twi.h
new file mode 100644
index 000000000..cdcb2e4a0
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_twi.h
@@ -0,0 +1,217 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_TWI_COMPONENT_
+#define _SAM3S8_TWI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Two-wire Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_TWI Two-wire Interface */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Twi hardware registers */
+typedef struct {
+  WoReg TWI_CR;        /**< \brief (Twi Offset: 0x00) Control Register */
+  RwReg TWI_MMR;       /**< \brief (Twi Offset: 0x04) Master Mode Register */
+  RwReg TWI_SMR;       /**< \brief (Twi Offset: 0x08) Slave Mode Register */
+  RwReg TWI_IADR;      /**< \brief (Twi Offset: 0x0C) Internal Address Register */
+  RwReg TWI_CWGR;      /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */
+  RoReg Reserved1[3];
+  RoReg TWI_SR;        /**< \brief (Twi Offset: 0x20) Status Register */
+  WoReg TWI_IER;       /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */
+  WoReg TWI_IDR;       /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */
+  RoReg TWI_IMR;       /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */
+  RoReg TWI_RHR;       /**< \brief (Twi Offset: 0x30) Receive Holding Register */
+  WoReg TWI_THR;       /**< \brief (Twi Offset: 0x34) Transmit Holding Register */
+  RoReg Reserved2[50];
+  RwReg TWI_RPR;       /**< \brief (Twi Offset: 0x100) Receive Pointer Register */
+  RwReg TWI_RCR;       /**< \brief (Twi Offset: 0x104) Receive Counter Register */
+  RwReg TWI_TPR;       /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */
+  RwReg TWI_TCR;       /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */
+  RwReg TWI_RNPR;      /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */
+  RwReg TWI_RNCR;      /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */
+  RwReg TWI_TNPR;      /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */
+  RwReg TWI_TNCR;      /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */
+  WoReg TWI_PTCR;      /**< \brief (Twi Offset: 0x120) Transfer Control Register */
+  RoReg TWI_PTSR;      /**< \brief (Twi Offset: 0x124) Transfer Status Register */
+} Twi;
+#endif /* __ASSEMBLY__ */
+/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */
+#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */
+#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */
+#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */
+#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */
+#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */
+#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */
+#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */
+#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */
+/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */
+#define TWI_MMR_IADRSZ_Pos 8
+#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */
+#define   TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */
+#define   TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */
+#define   TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */
+#define   TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */
+#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */
+#define TWI_MMR_DADR_Pos 16
+#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */
+#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))
+/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */
+#define TWI_SMR_SADR_Pos 16
+#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */
+#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))
+/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */
+#define TWI_IADR_IADR_Pos 0
+#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */
+#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))
+/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */
+#define TWI_CWGR_CLDIV_Pos 0
+#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */
+#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))
+#define TWI_CWGR_CHDIV_Pos 8
+#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */
+#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))
+#define TWI_CWGR_CKDIV_Pos 16
+#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */
+#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))
+/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */
+#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */
+#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */
+#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */
+#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */
+#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */
+#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */
+#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */
+#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */
+#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */
+#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */
+#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */
+#define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */
+#define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */
+#define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */
+#define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */
+/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */
+#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */
+#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */
+#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */
+#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */
+#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */
+#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */
+#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */
+#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */
+#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */
+#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */
+#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */
+#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */
+#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */
+#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */
+/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */
+#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */
+#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */
+#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */
+#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */
+#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */
+#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */
+#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */
+#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */
+#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */
+#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */
+#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */
+#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */
+#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */
+#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */
+/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */
+#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */
+#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */
+#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */
+#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */
+#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */
+#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */
+#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */
+#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */
+#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */
+#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */
+#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */
+#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */
+#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */
+#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */
+/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */
+#define TWI_RHR_RXDATA_Pos 0
+#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */
+/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */
+#define TWI_THR_TXDATA_Pos 0
+#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */
+#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))
+/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */
+#define TWI_RPR_RXPTR_Pos 0
+#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */
+#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos)))
+/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */
+#define TWI_RCR_RXCTR_Pos 0
+#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */
+#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos)))
+/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */
+#define TWI_TPR_TXPTR_Pos 0
+#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */
+#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos)))
+/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */
+#define TWI_TCR_TXCTR_Pos 0
+#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */
+#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos)))
+/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */
+#define TWI_RNPR_RXNPTR_Pos 0
+#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */
+#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos)))
+/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */
+#define TWI_RNCR_RXNCTR_Pos 0
+#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */
+#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos)))
+/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define TWI_TNPR_TXNPTR_Pos 0
+#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */
+#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos)))
+/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define TWI_TNCR_TXNCTR_Pos 0
+#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */
+#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos)))
+/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */
+#define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */
+#define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */
+#define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */
+#define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */
+/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */
+#define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */
+#define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_TWI_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_uart.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_uart.h
new file mode 100644
index 000000000..4b74609fc
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_uart.h
@@ -0,0 +1,185 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_UART_COMPONENT_
+#define _SAM3S8_UART_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_UART Universal Asynchronous Receiver Transmitter */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Uart hardware registers */
+typedef struct {
+  WoReg UART_CR;       /**< \brief (Uart Offset: 0x0000) Control Register */
+  RwReg UART_MR;       /**< \brief (Uart Offset: 0x0004) Mode Register */
+  WoReg UART_IER;      /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */
+  WoReg UART_IDR;      /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */
+  RoReg UART_IMR;      /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */
+  RoReg UART_SR;       /**< \brief (Uart Offset: 0x0014) Status Register */
+  RoReg UART_RHR;      /**< \brief (Uart Offset: 0x0018) Receive Holding Register */
+  WoReg UART_THR;      /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */
+  RwReg UART_BRGR;     /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */
+  RoReg Reserved1[55];
+  RwReg UART_RPR;      /**< \brief (Uart Offset: 0x100) Receive Pointer Register */
+  RwReg UART_RCR;      /**< \brief (Uart Offset: 0x104) Receive Counter Register */
+  RwReg UART_TPR;      /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */
+  RwReg UART_TCR;      /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */
+  RwReg UART_RNPR;     /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */
+  RwReg UART_RNCR;     /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */
+  RwReg UART_TNPR;     /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */
+  RwReg UART_TNCR;     /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */
+  WoReg UART_PTCR;     /**< \brief (Uart Offset: 0x120) Transfer Control Register */
+  RoReg UART_PTSR;     /**< \brief (Uart Offset: 0x124) Transfer Status Register */
+} Uart;
+#endif /* __ASSEMBLY__ */
+/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
+#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */
+#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */
+#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */
+#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */
+#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */
+#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */
+#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */
+/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
+#define UART_MR_PAR_Pos 9
+#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */
+#define   UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */
+#define   UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */
+#define   UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */
+#define   UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */
+#define   UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */
+#define UART_MR_CHMODE_Pos 14
+#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */
+#define   UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */
+#define   UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */
+#define   UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */
+#define   UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */
+/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
+#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */
+#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */
+#define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */
+#define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */
+#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */
+#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */
+#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */
+#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */
+#define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */
+#define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */
+/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
+#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */
+#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */
+#define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */
+#define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */
+#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */
+#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */
+#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */
+#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */
+#define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */
+#define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */
+/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
+#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */
+#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */
+#define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */
+#define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */
+#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */
+#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */
+#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */
+#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */
+#define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */
+#define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */
+/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
+#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */
+#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */
+#define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */
+#define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */
+#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */
+#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */
+#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */
+#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */
+#define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */
+#define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */
+/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
+#define UART_RHR_RXCHR_Pos 0
+#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */
+/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
+#define UART_THR_TXCHR_Pos 0
+#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */
+#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
+/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define UART_BRGR_CD_Pos 0
+#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */
+#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
+/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */
+#define UART_RPR_RXPTR_Pos 0
+#define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */
+#define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos)))
+/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */
+#define UART_RCR_RXCTR_Pos 0
+#define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */
+#define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos)))
+/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */
+#define UART_TPR_TXPTR_Pos 0
+#define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */
+#define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos)))
+/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */
+#define UART_TCR_TXCTR_Pos 0
+#define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */
+#define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos)))
+/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */
+#define UART_RNPR_RXNPTR_Pos 0
+#define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */
+#define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos)))
+/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */
+#define UART_RNCR_RXNCTR_Pos 0
+#define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */
+#define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos)))
+/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define UART_TNPR_TXNPTR_Pos 0
+#define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */
+#define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos)))
+/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define UART_TNCR_TXNCTR_Pos 0
+#define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */
+#define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos)))
+/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */
+#define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */
+#define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */
+#define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */
+#define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */
+/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */
+#define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */
+#define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_UART_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_udp.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_udp.h
new file mode 100644
index 000000000..6de4d8b1f
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_udp.h
@@ -0,0 +1,185 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_UDP_COMPONENT_
+#define _SAM3S8_UDP_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR USB Device Port */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_UDP USB Device Port */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Udp hardware registers */
+typedef struct {
+  RoReg UDP_FRM_NUM;  /**< \brief (Udp Offset: 0x000) Frame Number Register */
+  RwReg UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */
+  RwReg UDP_FADDR;    /**< \brief (Udp Offset: 0x008) Function Address Register */
+  RoReg Reserved1[1];
+  WoReg UDP_IER;      /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */
+  WoReg UDP_IDR;      /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */
+  RoReg UDP_IMR;      /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */
+  RoReg UDP_ISR;      /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */
+  WoReg UDP_ICR;      /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */
+  RoReg Reserved2[1];
+  RwReg UDP_RST_EP;   /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */
+  RoReg Reserved3[1];
+  RwReg UDP_CSR[8];   /**< \brief (Udp Offset: 0x030) Endpoint Control and Status Register */
+  RwReg UDP_FDR[8];   /**< \brief (Udp Offset: 0x050) Endpoint FIFO Data Register */
+  RoReg Reserved4[1];
+  RwReg UDP_TXVC;     /**< \brief (Udp Offset: 0x074) Transceiver Control Register */
+} Udp;
+#endif /* __ASSEMBLY__ */
+/* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */
+#define UDP_FRM_NUM_FRM_NUM_Pos 0
+#define UDP_FRM_NUM_FRM_NUM_Msk (0x7ffu << UDP_FRM_NUM_FRM_NUM_Pos) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */
+#define UDP_FRM_NUM_FRM_ERR (0x1u << 16) /**< \brief (UDP_FRM_NUM) Frame Error */
+#define UDP_FRM_NUM_FRM_OK (0x1u << 17) /**< \brief (UDP_FRM_NUM) Frame OK */
+/* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */
+#define UDP_GLB_STAT_FADDEN (0x1u << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */
+#define UDP_GLB_STAT_CONFG (0x1u << 1) /**< \brief (UDP_GLB_STAT) Configured */
+#define UDP_GLB_STAT_ESR (0x1u << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */
+#define UDP_GLB_STAT_RSMINPR (0x1u << 3) /**< \brief (UDP_GLB_STAT)  */
+#define UDP_GLB_STAT_RMWUPE (0x1u << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */
+/* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */
+#define UDP_FADDR_FADD_Pos 0
+#define UDP_FADDR_FADD_Msk (0x7fu << UDP_FADDR_FADD_Pos) /**< \brief (UDP_FADDR) Function Address Value */
+#define UDP_FADDR_FADD(value) ((UDP_FADDR_FADD_Msk & ((value) << UDP_FADDR_FADD_Pos)))
+#define UDP_FADDR_FEN (0x1u << 8) /**< \brief (UDP_FADDR) Function Enable */
+/* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */
+#define UDP_IER_EP0INT (0x1u << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */
+#define UDP_IER_EP1INT (0x1u << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */
+#define UDP_IER_EP2INT (0x1u << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */
+#define UDP_IER_EP3INT (0x1u << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */
+#define UDP_IER_EP4INT (0x1u << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */
+#define UDP_IER_EP5INT (0x1u << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */
+#define UDP_IER_EP6INT (0x1u << 6) /**< \brief (UDP_IER) Enable Endpoint 6 Interrupt */
+#define UDP_IER_EP7INT (0x1u << 7) /**< \brief (UDP_IER) Enable Endpoint 7 Interrupt */
+#define UDP_IER_RXSUSP (0x1u << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */
+#define UDP_IER_RXRSM (0x1u << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */
+#define UDP_IER_EXTRSM (0x1u << 10) /**< \brief (UDP_IER)  */
+#define UDP_IER_SOFINT (0x1u << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */
+#define UDP_IER_WAKEUP (0x1u << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */
+/* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */
+#define UDP_IDR_EP0INT (0x1u << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */
+#define UDP_IDR_EP1INT (0x1u << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */
+#define UDP_IDR_EP2INT (0x1u << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */
+#define UDP_IDR_EP3INT (0x1u << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */
+#define UDP_IDR_EP4INT (0x1u << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */
+#define UDP_IDR_EP5INT (0x1u << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */
+#define UDP_IDR_EP6INT (0x1u << 6) /**< \brief (UDP_IDR) Disable Endpoint 6 Interrupt */
+#define UDP_IDR_EP7INT (0x1u << 7) /**< \brief (UDP_IDR) Disable Endpoint 7 Interrupt */
+#define UDP_IDR_RXSUSP (0x1u << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */
+#define UDP_IDR_RXRSM (0x1u << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */
+#define UDP_IDR_EXTRSM (0x1u << 10) /**< \brief (UDP_IDR)  */
+#define UDP_IDR_SOFINT (0x1u << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */
+#define UDP_IDR_WAKEUP (0x1u << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */
+/* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */
+#define UDP_IMR_EP0INT (0x1u << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */
+#define UDP_IMR_EP1INT (0x1u << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */
+#define UDP_IMR_EP2INT (0x1u << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */
+#define UDP_IMR_EP3INT (0x1u << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */
+#define UDP_IMR_EP4INT (0x1u << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */
+#define UDP_IMR_EP5INT (0x1u << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */
+#define UDP_IMR_EP6INT (0x1u << 6) /**< \brief (UDP_IMR) Mask Endpoint 6 Interrupt */
+#define UDP_IMR_EP7INT (0x1u << 7) /**< \brief (UDP_IMR) Mask Endpoint 7 Interrupt */
+#define UDP_IMR_RXSUSP (0x1u << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */
+#define UDP_IMR_RXRSM (0x1u << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */
+#define UDP_IMR_EXTRSM (0x1u << 10) /**< \brief (UDP_IMR)  */
+#define UDP_IMR_SOFINT (0x1u << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */
+#define UDP_IMR_BIT12 (0x1u << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */
+#define UDP_IMR_WAKEUP (0x1u << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */
+/* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */
+#define UDP_ISR_EP0INT (0x1u << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */
+#define UDP_ISR_EP1INT (0x1u << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */
+#define UDP_ISR_EP2INT (0x1u << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */
+#define UDP_ISR_EP3INT (0x1u << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */
+#define UDP_ISR_EP4INT (0x1u << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */
+#define UDP_ISR_EP5INT (0x1u << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */
+#define UDP_ISR_EP6INT (0x1u << 6) /**< \brief (UDP_ISR) Endpoint 6 Interrupt Status */
+#define UDP_ISR_EP7INT (0x1u << 7) /**< \brief (UDP_ISR) Endpoint 7Interrupt Status */
+#define UDP_ISR_RXSUSP (0x1u << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */
+#define UDP_ISR_RXRSM (0x1u << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */
+#define UDP_ISR_EXTRSM (0x1u << 10) /**< \brief (UDP_ISR)  */
+#define UDP_ISR_SOFINT (0x1u << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */
+#define UDP_ISR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */
+#define UDP_ISR_WAKEUP (0x1u << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */
+/* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */
+#define UDP_ICR_RXSUSP (0x1u << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */
+#define UDP_ICR_RXRSM (0x1u << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */
+#define UDP_ICR_EXTRSM (0x1u << 10) /**< \brief (UDP_ICR)  */
+#define UDP_ICR_SOFINT (0x1u << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */
+#define UDP_ICR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */
+#define UDP_ICR_WAKEUP (0x1u << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */
+/* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */
+#define UDP_RST_EP_EP0 (0x1u << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */
+#define UDP_RST_EP_EP1 (0x1u << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */
+#define UDP_RST_EP_EP2 (0x1u << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */
+#define UDP_RST_EP_EP3 (0x1u << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */
+#define UDP_RST_EP_EP4 (0x1u << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */
+#define UDP_RST_EP_EP5 (0x1u << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */
+#define UDP_RST_EP_EP6 (0x1u << 6) /**< \brief (UDP_RST_EP) Reset Endpoint 6 */
+#define UDP_RST_EP_EP7 (0x1u << 7) /**< \brief (UDP_RST_EP) Reset Endpoint 7 */
+/* -------- UDP_CSR[8] : (UDP Offset: 0x030) Endpoint Control and Status Register -------- */
+#define UDP_CSR_TXCOMP (0x1u << 0) /**< \brief (UDP_CSR[8]) Generates an IN Packet with Data Previously Written in the DPR */
+#define UDP_CSR_RX_DATA_BK0 (0x1u << 1) /**< \brief (UDP_CSR[8]) Receive Data Bank 0 */
+#define UDP_CSR_RXSETUP (0x1u << 2) /**< \brief (UDP_CSR[8]) Received Setup */
+#define UDP_CSR_STALLSENT (0x1u << 3) /**< \brief (UDP_CSR[8]) Stall Sent (Control, Bulk Interrupt Endpoints)/ISOERROR (Isochronous Endpoints) */
+#define UDP_CSR_ISOERROR (0x1u << 3) /**< \brief (UDP_CSR[8]) Stall Sent (Control, Bulk Interrupt Endpoints)/ISOERROR (Isochronous Endpoints) */
+#define UDP_CSR_TXPKTRDY (0x1u << 4) /**< \brief (UDP_CSR[8]) Transmit Packet Ready */
+#define UDP_CSR_FORCESTALL (0x1u << 5) /**< \brief (UDP_CSR[8]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */
+#define UDP_CSR_RX_DATA_BK1 (0x1u << 6) /**< \brief (UDP_CSR[8]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */
+#define UDP_CSR_DIR (0x1u << 7) /**< \brief (UDP_CSR[8]) Transfer Direction (only available for control endpoints) */
+#define UDP_CSR_EPTYPE_Pos 8
+#define UDP_CSR_EPTYPE_Msk (0x7u << UDP_CSR_EPTYPE_Pos) /**< \brief (UDP_CSR[8]) Endpoint Type */
+#define   UDP_CSR_EPTYPE_CTRL (0x0u << 8) /**< \brief (UDP_CSR[8]) Control */
+#define   UDP_CSR_EPTYPE_ISO_OUT (0x1u << 8) /**< \brief (UDP_CSR[8]) Isochronous OUT */
+#define   UDP_CSR_EPTYPE_BULK_OUT (0x2u << 8) /**< \brief (UDP_CSR[8]) Bulk OUT */
+#define   UDP_CSR_EPTYPE_INT_OUT (0x3u << 8) /**< \brief (UDP_CSR[8]) Interrupt OUT */
+#define   UDP_CSR_EPTYPE_ISO_IN (0x5u << 8) /**< \brief (UDP_CSR[8]) Isochronous IN */
+#define   UDP_CSR_EPTYPE_BULK_IN (0x6u << 8) /**< \brief (UDP_CSR[8]) Bulk IN */
+#define   UDP_CSR_EPTYPE_INT_IN (0x7u << 8) /**< \brief (UDP_CSR[8]) Interrupt IN */
+#define UDP_CSR_DTGLE (0x1u << 11) /**< \brief (UDP_CSR[8]) Data Toggle */
+#define UDP_CSR_EPEDS (0x1u << 15) /**< \brief (UDP_CSR[8]) Endpoint Enable Disable */
+#define UDP_CSR_RXBYTECNT_Pos 16
+#define UDP_CSR_RXBYTECNT_Msk (0x7ffu << UDP_CSR_RXBYTECNT_Pos) /**< \brief (UDP_CSR[8]) Number of Bytes Available in the FIFO */
+#define UDP_CSR_RXBYTECNT(value) ((UDP_CSR_RXBYTECNT_Msk & ((value) << UDP_CSR_RXBYTECNT_Pos)))
+/* -------- UDP_FDR[8] : (UDP Offset: 0x050) Endpoint FIFO Data Register -------- */
+#define UDP_FDR_FIFO_DATA_Pos 0
+#define UDP_FDR_FIFO_DATA_Msk (0xffu << UDP_FDR_FIFO_DATA_Pos) /**< \brief (UDP_FDR[8]) FIFO Data Value */
+#define UDP_FDR_FIFO_DATA(value) ((UDP_FDR_FIFO_DATA_Msk & ((value) << UDP_FDR_FIFO_DATA_Pos)))
+/* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */
+#define UDP_TXVC_TXVDIS (0x1u << 8) /**< \brief (UDP_TXVC) Transceiver Disable */
+#define UDP_TXVC_PUON (0x1u << 9) /**< \brief (UDP_TXVC) Pullup On */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_UDP_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_usart.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_usart.h
new file mode 100644
index 000000000..664fdd27c
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_usart.h
@@ -0,0 +1,361 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_USART_COMPONENT_
+#define _SAM3S8_USART_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_USART Universal Synchronous Asynchronous Receiver Transmitter */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Usart hardware registers */
+typedef struct {
+  WoReg US_CR;         /**< \brief (Usart Offset: 0x0000) Control Register */
+  RwReg US_MR;         /**< \brief (Usart Offset: 0x0004) Mode Register */
+  WoReg US_IER;        /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */
+  WoReg US_IDR;        /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */
+  RoReg US_IMR;        /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */
+  RoReg US_CSR;        /**< \brief (Usart Offset: 0x0014) Channel Status Register */
+  RoReg US_RHR;        /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */
+  WoReg US_THR;        /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */
+  RwReg US_BRGR;       /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */
+  RwReg US_RTOR;       /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */
+  RwReg US_TTGR;       /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */
+  RoReg Reserved1[5];
+  RwReg US_FIDI;       /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */
+  RoReg US_NER;        /**< \brief (Usart Offset: 0x0044) Number of Errors Register */
+  RoReg Reserved2[1];
+  RwReg US_IF;         /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */
+  RwReg US_MAN;        /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */
+  RoReg Reserved3[36];
+  RwReg US_WPMR;       /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */
+  RoReg US_WPSR;       /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved4[4];
+  RoReg US_VERSION;    /**< \brief (Usart Offset: 0xFC) Version Register */
+  RwReg US_RPR;        /**< \brief (Usart Offset: 0x100) Receive Pointer Register */
+  RwReg US_RCR;        /**< \brief (Usart Offset: 0x104) Receive Counter Register */
+  RwReg US_TPR;        /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */
+  RwReg US_TCR;        /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */
+  RwReg US_RNPR;       /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */
+  RwReg US_RNCR;       /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */
+  RwReg US_TNPR;       /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */
+  RwReg US_TNCR;       /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */
+  WoReg US_PTCR;       /**< \brief (Usart Offset: 0x120) Transfer Control Register */
+  RoReg US_PTSR;       /**< \brief (Usart Offset: 0x124) Transfer Status Register */
+} Usart;
+#endif /* __ASSEMBLY__ */
+/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
+#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */
+#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */
+#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */
+#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */
+#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */
+#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */
+#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */
+#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */
+#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */
+#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */
+#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */
+#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */
+#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */
+#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */
+#define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */
+#define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */
+#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */
+#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */
+#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */
+#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */
+/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
+#define US_MR_USART_MODE_Pos 0
+#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR)  */
+#define   US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */
+#define   US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */
+#define   US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */
+#define   US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */
+#define   US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */
+#define   US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */
+#define   US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */
+#define   US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */
+#define   US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */
+#define US_MR_USCLKS_Pos 4
+#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */
+#define   US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */
+#define   US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */
+#define   US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */
+#define US_MR_CHRL_Pos 6
+#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */
+#define   US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */
+#define   US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */
+#define   US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */
+#define   US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */
+#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */
+#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */
+#define US_MR_PAR_Pos 9
+#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */
+#define   US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */
+#define   US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */
+#define   US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */
+#define   US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */
+#define   US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */
+#define   US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */
+#define US_MR_NBSTOP_Pos 12
+#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */
+#define   US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */
+#define   US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */
+#define   US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */
+#define US_MR_CHMODE_Pos 14
+#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */
+#define   US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */
+#define   US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */
+#define   US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */
+#define   US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */
+#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */
+#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */
+#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */
+#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */
+#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */
+#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */
+#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */
+#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */
+#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) INverted Data */
+#define US_MR_MAX_ITERATION_Pos 24
+#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR)  */
+#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))
+#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */
+#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */
+#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */
+#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */
+/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
+#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */
+#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */
+#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */
+#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */
+#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */
+#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */
+#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */
+#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */
+#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */
+#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */
+#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached */
+#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error */
+#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */
+#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */
+#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non AcknowledgeInterrupt Enable */
+#define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */
+#define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */
+#define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */
+#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
+#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */
+/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
+#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */
+#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */
+#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */
+#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */
+#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */
+#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */
+#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */
+#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */
+#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */
+#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */
+#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max number of Repetitions Reached Disable */
+#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Disable */
+#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */
+#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */
+#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non AcknowledgeInterrupt Disable */
+#define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */
+#define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */
+#define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */
+#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
+#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */
+/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
+#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */
+#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */
+#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */
+#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */
+#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */
+#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */
+#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */
+#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */
+#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */
+#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
+#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max number of Repetitions Reached Mask */
+#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Mask */
+#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */
+#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */
+#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non AcknowledgeInterrupt Mask */
+#define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */
+#define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */
+#define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */
+#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
+#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */
+/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
+#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */
+#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */
+#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */
+#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */
+#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */
+#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */
+#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */
+#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */
+#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */
+#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */
+#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max number of Repetitions Reached */
+#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) SPI Underrun Error */
+#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */
+#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */
+#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non AcknowledgeInterrupt */
+#define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */
+#define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */
+#define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */
+#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */
+#define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */
+#define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */
+#define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */
+#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */
+#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */
+/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */
+#define US_RHR_RXCHR_Pos 0
+#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */
+#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */
+/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */
+#define US_THR_TXCHR_Pos 0
+#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */
+#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
+#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be transmitted */
+/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define US_BRGR_CD_Pos 0
+#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */
+#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
+#define US_BRGR_FP_Pos 16
+#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */
+#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
+/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
+#define US_RTOR_TO_Pos 0
+#define US_RTOR_TO_Msk (0xffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */
+#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
+/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
+#define US_TTGR_TG_Pos 0
+#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */
+#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
+/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */
+#define US_FIDI_FI_DI_RATIO_Pos 0
+#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */
+#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))
+/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */
+#define US_NER_NB_ERRORS_Pos 0
+#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */
+/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */
+#define US_IF_IRDA_FILTER_Pos 0
+#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */
+#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))
+/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */
+#define US_MAN_TX_PL_Pos 0
+#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */
+#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))
+#define US_MAN_TX_PP_Pos 8
+#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */
+#define   US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */
+#define   US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */
+#define   US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */
+#define   US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */
+#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */
+#define US_MAN_RX_PL_Pos 16
+#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */
+#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))
+#define US_MAN_RX_PP_Pos 24
+#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */
+#define   US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */
+#define   US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */
+#define   US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */
+#define   US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */
+#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */
+#define US_MAN_STUCKTO1 (0x1u << 29) /**< \brief (US_MAN)  */
+#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift compensation */
+/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */
+#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */
+#define US_WPMR_WPKEY_Pos 8
+#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */
+#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))
+/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */
+#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */
+#define US_WPSR_WPVSRC_Pos 8
+#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */
+/* -------- US_VERSION : (USART Offset: 0xFC) Version Register -------- */
+#define US_VERSION_VERSION_Pos 0
+#define US_VERSION_VERSION_Msk (0xfffu << US_VERSION_VERSION_Pos) /**< \brief (US_VERSION)  */
+#define US_VERSION_MFN_Pos 16
+#define US_VERSION_MFN_Msk (0x7u << US_VERSION_MFN_Pos) /**< \brief (US_VERSION)  */
+/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */
+#define US_RPR_RXPTR_Pos 0
+#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */
+#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos)))
+/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */
+#define US_RCR_RXCTR_Pos 0
+#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */
+#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos)))
+/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */
+#define US_TPR_TXPTR_Pos 0
+#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */
+#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos)))
+/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */
+#define US_TCR_TXCTR_Pos 0
+#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */
+#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos)))
+/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */
+#define US_RNPR_RXNPTR_Pos 0
+#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */
+#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos)))
+/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */
+#define US_RNCR_RXNCTR_Pos 0
+#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */
+#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos)))
+/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define US_TNPR_TXNPTR_Pos 0
+#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */
+#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos)))
+/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define US_TNCR_TXNCTR_Pos 0
+#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */
+#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos)))
+/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */
+#define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */
+#define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */
+#define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */
+#define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */
+/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */
+#define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */
+#define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_USART_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_wdt.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_wdt.h
new file mode 100644
index 000000000..228e31be5
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/component/component_wdt.h
@@ -0,0 +1,72 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_WDT_COMPONENT_
+#define _SAM3S8_WDT_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Watchdog Timer */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_WDT Watchdog Timer */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Wdt hardware registers */
+typedef struct {
+  WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */
+  RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */
+  RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */
+} Wdt;
+#endif /* __ASSEMBLY__ */
+/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */
+#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */
+#define WDT_CR_KEY_Pos 24
+#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */
+#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))
+/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */
+#define WDT_MR_WDV_Pos 0
+#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */
+#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))
+#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */
+#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */
+#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */
+#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */
+#define WDT_MR_WDD_Pos 16
+#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */
+#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))
+#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */
+#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */
+/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */
+#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */
+#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_WDT_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_acc.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_acc.h
new file mode 100644
index 000000000..3a644c14d
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_acc.h
@@ -0,0 +1,56 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_ACC_INSTANCE_
+#define _SAM3S8_ACC_INSTANCE_
+
+/* ========== Register definition for ACC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_ACC_CR            (0x40040000U) /**< \brief (ACC) Control Register */
+#define REG_ACC_MR            (0x40040004U) /**< \brief (ACC) Mode Register */
+#define REG_ACC_IER           (0x40040024U) /**< \brief (ACC) Interrupt Enable Register */
+#define REG_ACC_IDR           (0x40040028U) /**< \brief (ACC) Interrupt Disable Register */
+#define REG_ACC_IMR           (0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */
+#define REG_ACC_ISR           (0x40040030U) /**< \brief (ACC) Interrupt Status Register */
+#define REG_ACC_ACR           (0x40040094U) /**< \brief (ACC) Analog Control Register */
+#define REG_ACC_WPMR          (0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */
+#define REG_ACC_WPSR          (0x400400E8U) /**< \brief (ACC) Write Protect Status Register */
+#else
+#define REG_ACC_CR   (*(WoReg*)0x40040000U) /**< \brief (ACC) Control Register */
+#define REG_ACC_MR   (*(RwReg*)0x40040004U) /**< \brief (ACC) Mode Register */
+#define REG_ACC_IER  (*(WoReg*)0x40040024U) /**< \brief (ACC) Interrupt Enable Register */
+#define REG_ACC_IDR  (*(WoReg*)0x40040028U) /**< \brief (ACC) Interrupt Disable Register */
+#define REG_ACC_IMR  (*(RoReg*)0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */
+#define REG_ACC_ISR  (*(RoReg*)0x40040030U) /**< \brief (ACC) Interrupt Status Register */
+#define REG_ACC_ACR  (*(RwReg*)0x40040094U) /**< \brief (ACC) Analog Control Register */
+#define REG_ACC_WPMR (*(RwReg*)0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */
+#define REG_ACC_WPSR (*(RoReg*)0x400400E8U) /**< \brief (ACC) Write Protect Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_ACC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_adc.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_adc.h
new file mode 100644
index 000000000..d6cc39f71
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_adc.h
@@ -0,0 +1,100 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_ADC_INSTANCE_
+#define _SAM3S8_ADC_INSTANCE_
+
+/* ========== Register definition for ADC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_ADC_CR               (0x40038000U) /**< \brief (ADC) Control Register */
+#define REG_ADC_MR               (0x40038004U) /**< \brief (ADC) Mode Register */
+#define REG_ADC_SEQR1            (0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */
+#define REG_ADC_SEQR2            (0x4003800CU) /**< \brief (ADC) Channel Sequence Register 2 */
+#define REG_ADC_CHER             (0x40038010U) /**< \brief (ADC) Channel Enable Register */
+#define REG_ADC_CHDR             (0x40038014U) /**< \brief (ADC) Channel Disable Register */
+#define REG_ADC_CHSR             (0x40038018U) /**< \brief (ADC) Channel Status Register */
+#define REG_ADC_LCDR             (0x40038020U) /**< \brief (ADC) Last Converted Data Register */
+#define REG_ADC_IER              (0x40038024U) /**< \brief (ADC) Interrupt Enable Register */
+#define REG_ADC_IDR              (0x40038028U) /**< \brief (ADC) Interrupt Disable Register */
+#define REG_ADC_IMR              (0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */
+#define REG_ADC_ISR              (0x40038030U) /**< \brief (ADC) Interrupt Status Register */
+#define REG_ADC_OVER             (0x4003803CU) /**< \brief (ADC) Overrun Status Register */
+#define REG_ADC_EMR              (0x40038040U) /**< \brief (ADC) Extended Mode Register */
+#define REG_ADC_CWR              (0x40038044U) /**< \brief (ADC) Compare Window Register */
+#define REG_ADC_CGR              (0x40038048U) /**< \brief (ADC) Channel Gain Register */
+#define REG_ADC_COR              (0x4003804CU) /**< \brief (ADC) Channel Offset Register */
+#define REG_ADC_CDR              (0x40038050U) /**< \brief (ADC) Channel Data Register */
+#define REG_ADC_ACR              (0x40038094U) /**< \brief (ADC) Analog Control Register */
+#define REG_ADC_WPMR             (0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */
+#define REG_ADC_WPSR             (0x400380E8U) /**< \brief (ADC) Write Protect Status Register */
+#define REG_ADC_RPR              (0x40038100U) /**< \brief (ADC) Receive Pointer Register */
+#define REG_ADC_RCR              (0x40038104U) /**< \brief (ADC) Receive Counter Register */
+#define REG_ADC_TPR              (0x40038108U) /**< \brief (ADC) Transmit Pointer Register */
+#define REG_ADC_TCR              (0x4003810CU) /**< \brief (ADC) Transmit Counter Register */
+#define REG_ADC_RNPR             (0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */
+#define REG_ADC_RNCR             (0x40038114U) /**< \brief (ADC) Receive Next Counter Register */
+#define REG_ADC_TNPR             (0x40038118U) /**< \brief (ADC) Transmit Next Pointer Register */
+#define REG_ADC_TNCR             (0x4003811CU) /**< \brief (ADC) Transmit Next Counter Register */
+#define REG_ADC_PTCR             (0x40038120U) /**< \brief (ADC) Transfer Control Register */
+#define REG_ADC_PTSR             (0x40038124U) /**< \brief (ADC) Transfer Status Register */
+#else
+#define REG_ADC_CR      (*(WoReg*)0x40038000U) /**< \brief (ADC) Control Register */
+#define REG_ADC_MR      (*(RwReg*)0x40038004U) /**< \brief (ADC) Mode Register */
+#define REG_ADC_SEQR1   (*(RwReg*)0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */
+#define REG_ADC_SEQR2   (*(RwReg*)0x4003800CU) /**< \brief (ADC) Channel Sequence Register 2 */
+#define REG_ADC_CHER    (*(WoReg*)0x40038010U) /**< \brief (ADC) Channel Enable Register */
+#define REG_ADC_CHDR    (*(WoReg*)0x40038014U) /**< \brief (ADC) Channel Disable Register */
+#define REG_ADC_CHSR    (*(RoReg*)0x40038018U) /**< \brief (ADC) Channel Status Register */
+#define REG_ADC_LCDR    (*(RoReg*)0x40038020U) /**< \brief (ADC) Last Converted Data Register */
+#define REG_ADC_IER     (*(WoReg*)0x40038024U) /**< \brief (ADC) Interrupt Enable Register */
+#define REG_ADC_IDR     (*(WoReg*)0x40038028U) /**< \brief (ADC) Interrupt Disable Register */
+#define REG_ADC_IMR     (*(RoReg*)0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */
+#define REG_ADC_ISR     (*(RoReg*)0x40038030U) /**< \brief (ADC) Interrupt Status Register */
+#define REG_ADC_OVER    (*(RoReg*)0x4003803CU) /**< \brief (ADC) Overrun Status Register */
+#define REG_ADC_EMR     (*(RwReg*)0x40038040U) /**< \brief (ADC) Extended Mode Register */
+#define REG_ADC_CWR     (*(RwReg*)0x40038044U) /**< \brief (ADC) Compare Window Register */
+#define REG_ADC_CGR     (*(RwReg*)0x40038048U) /**< \brief (ADC) Channel Gain Register */
+#define REG_ADC_COR     (*(RwReg*)0x4003804CU) /**< \brief (ADC) Channel Offset Register */
+#define REG_ADC_CDR     (*(RoReg*)0x40038050U) /**< \brief (ADC) Channel Data Register */
+#define REG_ADC_ACR     (*(RwReg*)0x40038094U) /**< \brief (ADC) Analog Control Register */
+#define REG_ADC_WPMR    (*(RwReg*)0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */
+#define REG_ADC_WPSR    (*(RoReg*)0x400380E8U) /**< \brief (ADC) Write Protect Status Register */
+#define REG_ADC_RPR     (*(RwReg*)0x40038100U) /**< \brief (ADC) Receive Pointer Register */
+#define REG_ADC_RCR     (*(RwReg*)0x40038104U) /**< \brief (ADC) Receive Counter Register */
+#define REG_ADC_TPR     (*(RwReg*)0x40038108U) /**< \brief (ADC) Transmit Pointer Register */
+#define REG_ADC_TCR     (*(RwReg*)0x4003810CU) /**< \brief (ADC) Transmit Counter Register */
+#define REG_ADC_RNPR    (*(RwReg*)0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */
+#define REG_ADC_RNCR    (*(RwReg*)0x40038114U) /**< \brief (ADC) Receive Next Counter Register */
+#define REG_ADC_TNPR    (*(RwReg*)0x40038118U) /**< \brief (ADC) Transmit Next Pointer Register */
+#define REG_ADC_TNCR    (*(RwReg*)0x4003811CU) /**< \brief (ADC) Transmit Next Counter Register */
+#define REG_ADC_PTCR    (*(WoReg*)0x40038120U) /**< \brief (ADC) Transfer Control Register */
+#define REG_ADC_PTSR    (*(RoReg*)0x40038124U) /**< \brief (ADC) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_ADC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_chipid.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_chipid.h
new file mode 100644
index 000000000..eeeeeae9b
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_chipid.h
@@ -0,0 +1,42 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_CHIPID_INSTANCE_
+#define _SAM3S8_CHIPID_INSTANCE_
+
+/* ========== Register definition for CHIPID peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_CHIPID_CIDR          (0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
+#define REG_CHIPID_EXID          (0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
+#else
+#define REG_CHIPID_CIDR (*(RoReg*)0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
+#define REG_CHIPID_EXID (*(RoReg*)0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_CHIPID_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_crccu.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_crccu.h
new file mode 100644
index 000000000..d37627396
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_crccu.h
@@ -0,0 +1,68 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_CRCCU_INSTANCE_
+#define _SAM3S8_CRCCU_INSTANCE_
+
+/* ========== Register definition for CRCCU peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_CRCCU_DSCR             (0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */
+#define REG_CRCCU_DMA_EN           (0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */
+#define REG_CRCCU_DMA_DIS          (0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */
+#define REG_CRCCU_DMA_SR           (0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */
+#define REG_CRCCU_DMA_IER          (0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */
+#define REG_CRCCU_DMA_IDR          (0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */
+#define REG_CRCCU_DMA_IMR          (0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */
+#define REG_CRCCU_DMA_ISR          (0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */
+#define REG_CRCCU_CR               (0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */
+#define REG_CRCCU_MR               (0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */
+#define REG_CRCCU_SR               (0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */
+#define REG_CRCCU_IER              (0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */
+#define REG_CRCCU_IDR              (0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */
+#define REG_CRCCU_IMR              (0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */
+#define REG_CRCCU_ISR              (0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */
+#else
+#define REG_CRCCU_DSCR    (*(RwReg*)0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */
+#define REG_CRCCU_DMA_EN  (*(WoReg*)0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */
+#define REG_CRCCU_DMA_DIS (*(WoReg*)0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */
+#define REG_CRCCU_DMA_SR  (*(RoReg*)0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */
+#define REG_CRCCU_DMA_IER (*(WoReg*)0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */
+#define REG_CRCCU_DMA_IDR (*(WoReg*)0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */
+#define REG_CRCCU_DMA_IMR (*(RoReg*)0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */
+#define REG_CRCCU_DMA_ISR (*(RoReg*)0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */
+#define REG_CRCCU_CR      (*(WoReg*)0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */
+#define REG_CRCCU_MR      (*(RwReg*)0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */
+#define REG_CRCCU_SR      (*(RoReg*)0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */
+#define REG_CRCCU_IER     (*(WoReg*)0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */
+#define REG_CRCCU_IDR     (*(WoReg*)0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */
+#define REG_CRCCU_IMR     (*(RoReg*)0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */
+#define REG_CRCCU_ISR     (*(RoReg*)0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_CRCCU_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_dacc.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_dacc.h
new file mode 100644
index 000000000..582ed9396
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_dacc.h
@@ -0,0 +1,84 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_DACC_INSTANCE_
+#define _SAM3S8_DACC_INSTANCE_
+
+/* ========== Register definition for DACC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_DACC_CR            (0x4003C000U) /**< \brief (DACC) Control Register */
+#define REG_DACC_MR            (0x4003C004U) /**< \brief (DACC) Mode Register */
+#define REG_DACC_CHER          (0x4003C010U) /**< \brief (DACC) Channel Enable Register */
+#define REG_DACC_CHDR          (0x4003C014U) /**< \brief (DACC) Channel Disable Register */
+#define REG_DACC_CHSR          (0x4003C018U) /**< \brief (DACC) Channel Status Register */
+#define REG_DACC_CDR           (0x4003C020U) /**< \brief (DACC) Conversion Data Register */
+#define REG_DACC_IER           (0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */
+#define REG_DACC_IDR           (0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */
+#define REG_DACC_IMR           (0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */
+#define REG_DACC_ISR           (0x4003C030U) /**< \brief (DACC) Interrupt Status Register */
+#define REG_DACC_ACR           (0x4003C094U) /**< \brief (DACC) Analog Current Register */
+#define REG_DACC_WPMR          (0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */
+#define REG_DACC_WPSR          (0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */
+#define REG_DACC_RPR           (0x4003C100U) /**< \brief (DACC) Receive Pointer Register */
+#define REG_DACC_RCR           (0x4003C104U) /**< \brief (DACC) Receive Counter Register */
+#define REG_DACC_TPR           (0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */
+#define REG_DACC_TCR           (0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */
+#define REG_DACC_RNPR          (0x4003C110U) /**< \brief (DACC) Receive Next Pointer Register */
+#define REG_DACC_RNCR          (0x4003C114U) /**< \brief (DACC) Receive Next Counter Register */
+#define REG_DACC_TNPR          (0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */
+#define REG_DACC_TNCR          (0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */
+#define REG_DACC_PTCR          (0x4003C120U) /**< \brief (DACC) Transfer Control Register */
+#define REG_DACC_PTSR          (0x4003C124U) /**< \brief (DACC) Transfer Status Register */
+#else
+#define REG_DACC_CR   (*(WoReg*)0x4003C000U) /**< \brief (DACC) Control Register */
+#define REG_DACC_MR   (*(RwReg*)0x4003C004U) /**< \brief (DACC) Mode Register */
+#define REG_DACC_CHER (*(WoReg*)0x4003C010U) /**< \brief (DACC) Channel Enable Register */
+#define REG_DACC_CHDR (*(WoReg*)0x4003C014U) /**< \brief (DACC) Channel Disable Register */
+#define REG_DACC_CHSR (*(RoReg*)0x4003C018U) /**< \brief (DACC) Channel Status Register */
+#define REG_DACC_CDR  (*(WoReg*)0x4003C020U) /**< \brief (DACC) Conversion Data Register */
+#define REG_DACC_IER  (*(WoReg*)0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */
+#define REG_DACC_IDR  (*(WoReg*)0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */
+#define REG_DACC_IMR  (*(RoReg*)0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */
+#define REG_DACC_ISR  (*(RoReg*)0x4003C030U) /**< \brief (DACC) Interrupt Status Register */
+#define REG_DACC_ACR  (*(RwReg*)0x4003C094U) /**< \brief (DACC) Analog Current Register */
+#define REG_DACC_WPMR (*(RwReg*)0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */
+#define REG_DACC_WPSR (*(RoReg*)0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */
+#define REG_DACC_RPR  (*(RwReg*)0x4003C100U) /**< \brief (DACC) Receive Pointer Register */
+#define REG_DACC_RCR  (*(RwReg*)0x4003C104U) /**< \brief (DACC) Receive Counter Register */
+#define REG_DACC_TPR  (*(RwReg*)0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */
+#define REG_DACC_TCR  (*(RwReg*)0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */
+#define REG_DACC_RNPR (*(RwReg*)0x4003C110U) /**< \brief (DACC) Receive Next Pointer Register */
+#define REG_DACC_RNCR (*(RwReg*)0x4003C114U) /**< \brief (DACC) Receive Next Counter Register */
+#define REG_DACC_TNPR (*(RwReg*)0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */
+#define REG_DACC_TNCR (*(RwReg*)0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */
+#define REG_DACC_PTCR (*(WoReg*)0x4003C120U) /**< \brief (DACC) Transfer Control Register */
+#define REG_DACC_PTSR (*(RoReg*)0x4003C124U) /**< \brief (DACC) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_DACC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_efc.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_efc.h
new file mode 100644
index 000000000..7d1b09910
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_efc.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_EFC_INSTANCE_
+#define _SAM3S8_EFC_INSTANCE_
+
+/* ========== Register definition for EFC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_EFC_FMR           (0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */
+#define REG_EFC_FCR           (0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */
+#define REG_EFC_FSR           (0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */
+#define REG_EFC_FRR           (0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */
+#else
+#define REG_EFC_FMR  (*(RwReg*)0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */
+#define REG_EFC_FCR  (*(WoReg*)0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */
+#define REG_EFC_FSR  (*(RoReg*)0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */
+#define REG_EFC_FRR  (*(RoReg*)0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_EFC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_gpbr.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_gpbr.h
new file mode 100644
index 000000000..b0a6fa782
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_gpbr.h
@@ -0,0 +1,40 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_GPBR_INSTANCE_
+#define _SAM3S8_GPBR_INSTANCE_
+
+/* ========== Register definition for GPBR peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_GPBR_GPBR            (0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */
+#else
+#define REG_GPBR_GPBR   (*(RwReg*)0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_GPBR_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_hsmci.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_hsmci.h
new file mode 100644
index 000000000..9efebbebc
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_hsmci.h
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_HSMCI_INSTANCE_
+#define _SAM3S8_HSMCI_INSTANCE_
+
+/* ========== Register definition for HSMCI peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_HSMCI_CR                 (0x40000000U) /**< \brief (HSMCI) Control Register */
+#define REG_HSMCI_MR                 (0x40000004U) /**< \brief (HSMCI) Mode Register */
+#define REG_HSMCI_DTOR               (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
+#define REG_HSMCI_SDCR               (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
+#define REG_HSMCI_ARGR               (0x40000010U) /**< \brief (HSMCI) Argument Register */
+#define REG_HSMCI_CMDR               (0x40000014U) /**< \brief (HSMCI) Command Register */
+#define REG_HSMCI_BLKR               (0x40000018U) /**< \brief (HSMCI) Block Register */
+#define REG_HSMCI_CSTOR              (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
+#define REG_HSMCI_RSPR               (0x40000020U) /**< \brief (HSMCI) Response Register */
+#define REG_HSMCI_RDR                (0x40000030U) /**< \brief (HSMCI) Receive Data Register */
+#define REG_HSMCI_TDR                (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
+#define REG_HSMCI_SR                 (0x40000040U) /**< \brief (HSMCI) Status Register */
+#define REG_HSMCI_IER                (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
+#define REG_HSMCI_IDR                (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
+#define REG_HSMCI_IMR                (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
+#define REG_HSMCI_CFG                (0x40000054U) /**< \brief (HSMCI) Configuration Register */
+#define REG_HSMCI_WPMR               (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
+#define REG_HSMCI_WPSR               (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
+#define REG_HSMCI_RPR                (0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */
+#define REG_HSMCI_RCR                (0x40000104U) /**< \brief (HSMCI) Receive Counter Register */
+#define REG_HSMCI_TPR                (0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */
+#define REG_HSMCI_TCR                (0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */
+#define REG_HSMCI_RNPR               (0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */
+#define REG_HSMCI_RNCR               (0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */
+#define REG_HSMCI_TNPR               (0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */
+#define REG_HSMCI_TNCR               (0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */
+#define REG_HSMCI_PTCR               (0x40000120U) /**< \brief (HSMCI) Transfer Control Register */
+#define REG_HSMCI_PTSR               (0x40000124U) /**< \brief (HSMCI) Transfer Status Register */
+#define REG_HSMCI_FIFO               (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
+#else
+#define REG_HSMCI_CR        (*(WoReg*)0x40000000U) /**< \brief (HSMCI) Control Register */
+#define REG_HSMCI_MR        (*(RwReg*)0x40000004U) /**< \brief (HSMCI) Mode Register */
+#define REG_HSMCI_DTOR      (*(RwReg*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
+#define REG_HSMCI_SDCR      (*(RwReg*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
+#define REG_HSMCI_ARGR      (*(RwReg*)0x40000010U) /**< \brief (HSMCI) Argument Register */
+#define REG_HSMCI_CMDR      (*(WoReg*)0x40000014U) /**< \brief (HSMCI) Command Register */
+#define REG_HSMCI_BLKR      (*(RwReg*)0x40000018U) /**< \brief (HSMCI) Block Register */
+#define REG_HSMCI_CSTOR     (*(RwReg*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
+#define REG_HSMCI_RSPR      (*(RoReg*)0x40000020U) /**< \brief (HSMCI) Response Register */
+#define REG_HSMCI_RDR       (*(RoReg*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */
+#define REG_HSMCI_TDR       (*(WoReg*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
+#define REG_HSMCI_SR        (*(RoReg*)0x40000040U) /**< \brief (HSMCI) Status Register */
+#define REG_HSMCI_IER       (*(WoReg*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
+#define REG_HSMCI_IDR       (*(WoReg*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
+#define REG_HSMCI_IMR       (*(RoReg*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
+#define REG_HSMCI_CFG       (*(RwReg*)0x40000054U) /**< \brief (HSMCI) Configuration Register */
+#define REG_HSMCI_WPMR      (*(RwReg*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
+#define REG_HSMCI_WPSR      (*(RoReg*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
+#define REG_HSMCI_RPR       (*(RwReg*)0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */
+#define REG_HSMCI_RCR       (*(RwReg*)0x40000104U) /**< \brief (HSMCI) Receive Counter Register */
+#define REG_HSMCI_TPR       (*(RwReg*)0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */
+#define REG_HSMCI_TCR       (*(RwReg*)0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */
+#define REG_HSMCI_RNPR      (*(RwReg*)0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */
+#define REG_HSMCI_RNCR      (*(RwReg*)0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */
+#define REG_HSMCI_TNPR      (*(RwReg*)0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */
+#define REG_HSMCI_TNCR      (*(RwReg*)0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */
+#define REG_HSMCI_PTCR      (*(WoReg*)0x40000120U) /**< \brief (HSMCI) Transfer Control Register */
+#define REG_HSMCI_PTSR      (*(RoReg*)0x40000124U) /**< \brief (HSMCI) Transfer Status Register */
+#define REG_HSMCI_FIFO      (*(RwReg*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_HSMCI_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_matrix.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_matrix.h
new file mode 100644
index 000000000..b11f4e12e
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_matrix.h
@@ -0,0 +1,60 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_MATRIX_INSTANCE_
+#define _SAM3S8_MATRIX_INSTANCE_
+
+/* ========== Register definition for MATRIX peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_MATRIX_MCFG             (0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
+#define REG_MATRIX_SCFG             (0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
+#define REG_MATRIX_PRAS0            (0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
+#define REG_MATRIX_PRAS1            (0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
+#define REG_MATRIX_PRAS2            (0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
+#define REG_MATRIX_PRAS3            (0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
+#define REG_MATRIX_PRAS4            (0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
+#define REG_CCFG_SYSIO              (0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */
+#define REG_CCFG_SMCNFCS            (0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */
+#define REG_MATRIX_WPMR             (0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
+#define REG_MATRIX_WPSR             (0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
+#else
+#define REG_MATRIX_MCFG    (*(RwReg*)0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
+#define REG_MATRIX_SCFG    (*(RwReg*)0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
+#define REG_MATRIX_PRAS0   (*(RwReg*)0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
+#define REG_MATRIX_PRAS1   (*(RwReg*)0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
+#define REG_MATRIX_PRAS2   (*(RwReg*)0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
+#define REG_MATRIX_PRAS3   (*(RwReg*)0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
+#define REG_MATRIX_PRAS4   (*(RwReg*)0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
+#define REG_CCFG_SYSIO     (*(RwReg*)0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */
+#define REG_CCFG_SMCNFCS   (*(RwReg*)0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */
+#define REG_MATRIX_WPMR    (*(RwReg*)0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
+#define REG_MATRIX_WPSR    (*(RoReg*)0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_MATRIX_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_pioa.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_pioa.h
new file mode 100644
index 000000000..1545f891a
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_pioa.h
@@ -0,0 +1,164 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_PIOA_INSTANCE_
+#define _SAM3S8_PIOA_INSTANCE_
+
+/* ========== Register definition for PIOA peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PIOA_PER                (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
+#define REG_PIOA_PDR                (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
+#define REG_PIOA_PSR                (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
+#define REG_PIOA_OER                (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
+#define REG_PIOA_ODR                (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
+#define REG_PIOA_OSR                (0x400E0E18U) /**< \brief (PIOA) Output Status Register */
+#define REG_PIOA_IFER               (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
+#define REG_PIOA_IFDR               (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
+#define REG_PIOA_IFSR               (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
+#define REG_PIOA_SODR               (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
+#define REG_PIOA_CODR               (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
+#define REG_PIOA_ODSR               (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
+#define REG_PIOA_PDSR               (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
+#define REG_PIOA_IER                (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
+#define REG_PIOA_IDR                (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
+#define REG_PIOA_IMR                (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
+#define REG_PIOA_ISR                (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
+#define REG_PIOA_MDER               (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
+#define REG_PIOA_MDDR               (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
+#define REG_PIOA_MDSR               (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
+#define REG_PIOA_PUDR               (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
+#define REG_PIOA_PUER               (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
+#define REG_PIOA_PUSR               (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
+#define REG_PIOA_ABCDSR             (0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
+#define REG_PIOA_IFSCDR             (0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
+#define REG_PIOA_IFSCER             (0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
+#define REG_PIOA_IFSCSR             (0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
+#define REG_PIOA_SCDR               (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
+#define REG_PIOA_PPDDR              (0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
+#define REG_PIOA_PPDER              (0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
+#define REG_PIOA_PPDSR              (0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
+#define REG_PIOA_OWER               (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
+#define REG_PIOA_OWDR               (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
+#define REG_PIOA_OWSR               (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
+#define REG_PIOA_AIMER              (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
+#define REG_PIOA_AIMDR              (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
+#define REG_PIOA_AIMMR              (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
+#define REG_PIOA_ESR                (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
+#define REG_PIOA_LSR                (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
+#define REG_PIOA_ELSR               (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
+#define REG_PIOA_FELLSR             (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
+#define REG_PIOA_REHLSR             (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
+#define REG_PIOA_FRLHSR             (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
+#define REG_PIOA_LOCKSR             (0x400E0EE0U) /**< \brief (PIOA) Lock Status */
+#define REG_PIOA_WPMR               (0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
+#define REG_PIOA_WPSR               (0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
+#define REG_PIOA_SCHMITT            (0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
+#define REG_PIOA_PCMR               (0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */
+#define REG_PIOA_PCIER              (0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */
+#define REG_PIOA_PCIDR              (0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */
+#define REG_PIOA_PCIMR              (0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */
+#define REG_PIOA_PCISR              (0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */
+#define REG_PIOA_PCRHR              (0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */
+#define REG_PIOA_RPR                (0x400E0F68U) /**< \brief (PIOA) Receive Pointer Register */
+#define REG_PIOA_RCR                (0x400E0F6CU) /**< \brief (PIOA) Receive Counter Register */
+#define REG_PIOA_TPR                (0x400E0F70U) /**< \brief (PIOA) Transmit Pointer Register */
+#define REG_PIOA_TCR                (0x400E0F74U) /**< \brief (PIOA) Transmit Counter Register */
+#define REG_PIOA_RNPR               (0x400E0F78U) /**< \brief (PIOA) Receive Next Pointer Register */
+#define REG_PIOA_RNCR               (0x400E0F7CU) /**< \brief (PIOA) Receive Next Counter Register */
+#define REG_PIOA_TNPR               (0x400E0F80U) /**< \brief (PIOA) Transmit Next Pointer Register */
+#define REG_PIOA_TNCR               (0x400E0F84U) /**< \brief (PIOA) Transmit Next Counter Register */
+#define REG_PIOA_PTCR               (0x400E0F88U) /**< \brief (PIOA) Transfer Control Register */
+#define REG_PIOA_PTSR               (0x400E0F8CU) /**< \brief (PIOA) Transfer Status Register */
+#else
+#define REG_PIOA_PER       (*(WoReg*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
+#define REG_PIOA_PDR       (*(WoReg*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
+#define REG_PIOA_PSR       (*(RoReg*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
+#define REG_PIOA_OER       (*(WoReg*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
+#define REG_PIOA_ODR       (*(WoReg*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
+#define REG_PIOA_OSR       (*(RoReg*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */
+#define REG_PIOA_IFER      (*(WoReg*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
+#define REG_PIOA_IFDR      (*(WoReg*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
+#define REG_PIOA_IFSR      (*(RoReg*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
+#define REG_PIOA_SODR      (*(WoReg*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
+#define REG_PIOA_CODR      (*(WoReg*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
+#define REG_PIOA_ODSR      (*(RwReg*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
+#define REG_PIOA_PDSR      (*(RoReg*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
+#define REG_PIOA_IER       (*(WoReg*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
+#define REG_PIOA_IDR       (*(WoReg*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
+#define REG_PIOA_IMR       (*(RoReg*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
+#define REG_PIOA_ISR       (*(RoReg*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
+#define REG_PIOA_MDER      (*(WoReg*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
+#define REG_PIOA_MDDR      (*(WoReg*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
+#define REG_PIOA_MDSR      (*(RoReg*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
+#define REG_PIOA_PUDR      (*(WoReg*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
+#define REG_PIOA_PUER      (*(WoReg*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
+#define REG_PIOA_PUSR      (*(RoReg*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
+#define REG_PIOA_ABCDSR    (*(RwReg*)0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
+#define REG_PIOA_IFSCDR    (*(WoReg*)0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
+#define REG_PIOA_IFSCER    (*(WoReg*)0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
+#define REG_PIOA_IFSCSR    (*(RoReg*)0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
+#define REG_PIOA_SCDR      (*(RwReg*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
+#define REG_PIOA_PPDDR     (*(WoReg*)0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
+#define REG_PIOA_PPDER     (*(WoReg*)0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
+#define REG_PIOA_PPDSR     (*(RoReg*)0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
+#define REG_PIOA_OWER      (*(WoReg*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
+#define REG_PIOA_OWDR      (*(WoReg*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
+#define REG_PIOA_OWSR      (*(RoReg*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
+#define REG_PIOA_AIMER     (*(WoReg*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
+#define REG_PIOA_AIMDR     (*(WoReg*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
+#define REG_PIOA_AIMMR     (*(RoReg*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
+#define REG_PIOA_ESR       (*(WoReg*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
+#define REG_PIOA_LSR       (*(WoReg*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
+#define REG_PIOA_ELSR      (*(RoReg*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
+#define REG_PIOA_FELLSR    (*(WoReg*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
+#define REG_PIOA_REHLSR    (*(WoReg*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
+#define REG_PIOA_FRLHSR    (*(RoReg*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
+#define REG_PIOA_LOCKSR    (*(RoReg*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */
+#define REG_PIOA_WPMR      (*(RwReg*)0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
+#define REG_PIOA_WPSR      (*(RoReg*)0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
+#define REG_PIOA_SCHMITT   (*(RwReg*)0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
+#define REG_PIOA_PCMR      (*(RwReg*)0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */
+#define REG_PIOA_PCIER     (*(WoReg*)0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */
+#define REG_PIOA_PCIDR     (*(WoReg*)0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */
+#define REG_PIOA_PCIMR     (*(RoReg*)0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */
+#define REG_PIOA_PCISR     (*(RoReg*)0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */
+#define REG_PIOA_PCRHR     (*(RoReg*)0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */
+#define REG_PIOA_RPR       (*(RwReg*)0x400E0F68U) /**< \brief (PIOA) Receive Pointer Register */
+#define REG_PIOA_RCR       (*(RwReg*)0x400E0F6CU) /**< \brief (PIOA) Receive Counter Register */
+#define REG_PIOA_TPR       (*(RwReg*)0x400E0F70U) /**< \brief (PIOA) Transmit Pointer Register */
+#define REG_PIOA_TCR       (*(RwReg*)0x400E0F74U) /**< \brief (PIOA) Transmit Counter Register */
+#define REG_PIOA_RNPR      (*(RwReg*)0x400E0F78U) /**< \brief (PIOA) Receive Next Pointer Register */
+#define REG_PIOA_RNCR      (*(RwReg*)0x400E0F7CU) /**< \brief (PIOA) Receive Next Counter Register */
+#define REG_PIOA_TNPR      (*(RwReg*)0x400E0F80U) /**< \brief (PIOA) Transmit Next Pointer Register */
+#define REG_PIOA_TNCR      (*(RwReg*)0x400E0F84U) /**< \brief (PIOA) Transmit Next Counter Register */
+#define REG_PIOA_PTCR      (*(WoReg*)0x400E0F88U) /**< \brief (PIOA) Transfer Control Register */
+#define REG_PIOA_PTSR      (*(RoReg*)0x400E0F8CU) /**< \brief (PIOA) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_PIOA_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_piob.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_piob.h
new file mode 100644
index 000000000..0ab9b1b1f
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_piob.h
@@ -0,0 +1,144 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_PIOB_INSTANCE_
+#define _SAM3S8_PIOB_INSTANCE_
+
+/* ========== Register definition for PIOB peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PIOB_PER                (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
+#define REG_PIOB_PDR                (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
+#define REG_PIOB_PSR                (0x400E1008U) /**< \brief (PIOB) PIO Status Register */
+#define REG_PIOB_OER                (0x400E1010U) /**< \brief (PIOB) Output Enable Register */
+#define REG_PIOB_ODR                (0x400E1014U) /**< \brief (PIOB) Output Disable Register */
+#define REG_PIOB_OSR                (0x400E1018U) /**< \brief (PIOB) Output Status Register */
+#define REG_PIOB_IFER               (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
+#define REG_PIOB_IFDR               (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
+#define REG_PIOB_IFSR               (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
+#define REG_PIOB_SODR               (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
+#define REG_PIOB_CODR               (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
+#define REG_PIOB_ODSR               (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
+#define REG_PIOB_PDSR               (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
+#define REG_PIOB_IER                (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
+#define REG_PIOB_IDR                (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
+#define REG_PIOB_IMR                (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
+#define REG_PIOB_ISR                (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
+#define REG_PIOB_MDER               (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
+#define REG_PIOB_MDDR               (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
+#define REG_PIOB_MDSR               (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
+#define REG_PIOB_PUDR               (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
+#define REG_PIOB_PUER               (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
+#define REG_PIOB_PUSR               (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
+#define REG_PIOB_ABCDSR             (0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */
+#define REG_PIOB_IFSCDR             (0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
+#define REG_PIOB_IFSCER             (0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
+#define REG_PIOB_IFSCSR             (0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
+#define REG_PIOB_SCDR               (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
+#define REG_PIOB_PPDDR              (0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */
+#define REG_PIOB_PPDER              (0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */
+#define REG_PIOB_PPDSR              (0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */
+#define REG_PIOB_OWER               (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
+#define REG_PIOB_OWDR               (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
+#define REG_PIOB_OWSR               (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
+#define REG_PIOB_AIMER              (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
+#define REG_PIOB_AIMDR              (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
+#define REG_PIOB_AIMMR              (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
+#define REG_PIOB_ESR                (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
+#define REG_PIOB_LSR                (0x400E10C4U) /**< \brief (PIOB) Level Select Register */
+#define REG_PIOB_ELSR               (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
+#define REG_PIOB_FELLSR             (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
+#define REG_PIOB_REHLSR             (0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
+#define REG_PIOB_FRLHSR             (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
+#define REG_PIOB_LOCKSR             (0x400E10E0U) /**< \brief (PIOB) Lock Status */
+#define REG_PIOB_WPMR               (0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
+#define REG_PIOB_WPSR               (0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
+#define REG_PIOB_SCHMITT            (0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */
+#define REG_PIOB_PCMR               (0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */
+#define REG_PIOB_PCIER              (0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */
+#define REG_PIOB_PCIDR              (0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */
+#define REG_PIOB_PCIMR              (0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */
+#define REG_PIOB_PCISR              (0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */
+#define REG_PIOB_PCRHR              (0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */
+#else
+#define REG_PIOB_PER       (*(WoReg*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
+#define REG_PIOB_PDR       (*(WoReg*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
+#define REG_PIOB_PSR       (*(RoReg*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */
+#define REG_PIOB_OER       (*(WoReg*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */
+#define REG_PIOB_ODR       (*(WoReg*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */
+#define REG_PIOB_OSR       (*(RoReg*)0x400E1018U) /**< \brief (PIOB) Output Status Register */
+#define REG_PIOB_IFER      (*(WoReg*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
+#define REG_PIOB_IFDR      (*(WoReg*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
+#define REG_PIOB_IFSR      (*(RoReg*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
+#define REG_PIOB_SODR      (*(WoReg*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
+#define REG_PIOB_CODR      (*(WoReg*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
+#define REG_PIOB_ODSR      (*(RwReg*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
+#define REG_PIOB_PDSR      (*(RoReg*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
+#define REG_PIOB_IER       (*(WoReg*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
+#define REG_PIOB_IDR       (*(WoReg*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
+#define REG_PIOB_IMR       (*(RoReg*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
+#define REG_PIOB_ISR       (*(RoReg*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
+#define REG_PIOB_MDER      (*(WoReg*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
+#define REG_PIOB_MDDR      (*(WoReg*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
+#define REG_PIOB_MDSR      (*(RoReg*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
+#define REG_PIOB_PUDR      (*(WoReg*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
+#define REG_PIOB_PUER      (*(WoReg*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
+#define REG_PIOB_PUSR      (*(RoReg*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
+#define REG_PIOB_ABCDSR    (*(RwReg*)0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */
+#define REG_PIOB_IFSCDR    (*(WoReg*)0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
+#define REG_PIOB_IFSCER    (*(WoReg*)0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
+#define REG_PIOB_IFSCSR    (*(RoReg*)0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
+#define REG_PIOB_SCDR      (*(RwReg*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
+#define REG_PIOB_PPDDR     (*(WoReg*)0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */
+#define REG_PIOB_PPDER     (*(WoReg*)0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */
+#define REG_PIOB_PPDSR     (*(RoReg*)0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */
+#define REG_PIOB_OWER      (*(WoReg*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
+#define REG_PIOB_OWDR      (*(WoReg*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
+#define REG_PIOB_OWSR      (*(RoReg*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
+#define REG_PIOB_AIMER     (*(WoReg*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
+#define REG_PIOB_AIMDR     (*(WoReg*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
+#define REG_PIOB_AIMMR     (*(RoReg*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
+#define REG_PIOB_ESR       (*(WoReg*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
+#define REG_PIOB_LSR       (*(WoReg*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */
+#define REG_PIOB_ELSR      (*(RoReg*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
+#define REG_PIOB_FELLSR    (*(WoReg*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
+#define REG_PIOB_REHLSR    (*(WoReg*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
+#define REG_PIOB_FRLHSR    (*(RoReg*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
+#define REG_PIOB_LOCKSR    (*(RoReg*)0x400E10E0U) /**< \brief (PIOB) Lock Status */
+#define REG_PIOB_WPMR      (*(RwReg*)0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
+#define REG_PIOB_WPSR      (*(RoReg*)0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
+#define REG_PIOB_SCHMITT   (*(RwReg*)0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */
+#define REG_PIOB_PCMR      (*(RwReg*)0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */
+#define REG_PIOB_PCIER     (*(WoReg*)0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */
+#define REG_PIOB_PCIDR     (*(WoReg*)0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */
+#define REG_PIOB_PCIMR     (*(RoReg*)0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */
+#define REG_PIOB_PCISR     (*(RoReg*)0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */
+#define REG_PIOB_PCRHR     (*(RoReg*)0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_PIOB_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_pioc.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_pioc.h
new file mode 100644
index 000000000..1d2de8a8b
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_pioc.h
@@ -0,0 +1,144 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_PIOC_INSTANCE_
+#define _SAM3S8_PIOC_INSTANCE_
+
+/* ========== Register definition for PIOC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PIOC_PER                (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
+#define REG_PIOC_PDR                (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
+#define REG_PIOC_PSR                (0x400E1208U) /**< \brief (PIOC) PIO Status Register */
+#define REG_PIOC_OER                (0x400E1210U) /**< \brief (PIOC) Output Enable Register */
+#define REG_PIOC_ODR                (0x400E1214U) /**< \brief (PIOC) Output Disable Register */
+#define REG_PIOC_OSR                (0x400E1218U) /**< \brief (PIOC) Output Status Register */
+#define REG_PIOC_IFER               (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
+#define REG_PIOC_IFDR               (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
+#define REG_PIOC_IFSR               (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
+#define REG_PIOC_SODR               (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
+#define REG_PIOC_CODR               (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
+#define REG_PIOC_ODSR               (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
+#define REG_PIOC_PDSR               (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
+#define REG_PIOC_IER                (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
+#define REG_PIOC_IDR                (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
+#define REG_PIOC_IMR                (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
+#define REG_PIOC_ISR                (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
+#define REG_PIOC_MDER               (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
+#define REG_PIOC_MDDR               (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
+#define REG_PIOC_MDSR               (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
+#define REG_PIOC_PUDR               (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
+#define REG_PIOC_PUER               (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
+#define REG_PIOC_PUSR               (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
+#define REG_PIOC_ABCDSR             (0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */
+#define REG_PIOC_IFSCDR             (0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
+#define REG_PIOC_IFSCER             (0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
+#define REG_PIOC_IFSCSR             (0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
+#define REG_PIOC_SCDR               (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
+#define REG_PIOC_PPDDR              (0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */
+#define REG_PIOC_PPDER              (0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */
+#define REG_PIOC_PPDSR              (0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */
+#define REG_PIOC_OWER               (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
+#define REG_PIOC_OWDR               (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
+#define REG_PIOC_OWSR               (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
+#define REG_PIOC_AIMER              (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
+#define REG_PIOC_AIMDR              (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
+#define REG_PIOC_AIMMR              (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
+#define REG_PIOC_ESR                (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
+#define REG_PIOC_LSR                (0x400E12C4U) /**< \brief (PIOC) Level Select Register */
+#define REG_PIOC_ELSR               (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
+#define REG_PIOC_FELLSR             (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
+#define REG_PIOC_REHLSR             (0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
+#define REG_PIOC_FRLHSR             (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
+#define REG_PIOC_LOCKSR             (0x400E12E0U) /**< \brief (PIOC) Lock Status */
+#define REG_PIOC_WPMR               (0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
+#define REG_PIOC_WPSR               (0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
+#define REG_PIOC_SCHMITT            (0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */
+#define REG_PIOC_PCMR               (0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */
+#define REG_PIOC_PCIER              (0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */
+#define REG_PIOC_PCIDR              (0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */
+#define REG_PIOC_PCIMR              (0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */
+#define REG_PIOC_PCISR              (0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */
+#define REG_PIOC_PCRHR              (0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */
+#else
+#define REG_PIOC_PER       (*(WoReg*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
+#define REG_PIOC_PDR       (*(WoReg*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
+#define REG_PIOC_PSR       (*(RoReg*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */
+#define REG_PIOC_OER       (*(WoReg*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */
+#define REG_PIOC_ODR       (*(WoReg*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */
+#define REG_PIOC_OSR       (*(RoReg*)0x400E1218U) /**< \brief (PIOC) Output Status Register */
+#define REG_PIOC_IFER      (*(WoReg*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
+#define REG_PIOC_IFDR      (*(WoReg*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
+#define REG_PIOC_IFSR      (*(RoReg*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
+#define REG_PIOC_SODR      (*(WoReg*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
+#define REG_PIOC_CODR      (*(WoReg*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
+#define REG_PIOC_ODSR      (*(RwReg*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
+#define REG_PIOC_PDSR      (*(RoReg*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
+#define REG_PIOC_IER       (*(WoReg*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
+#define REG_PIOC_IDR       (*(WoReg*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
+#define REG_PIOC_IMR       (*(RoReg*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
+#define REG_PIOC_ISR       (*(RoReg*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
+#define REG_PIOC_MDER      (*(WoReg*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
+#define REG_PIOC_MDDR      (*(WoReg*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
+#define REG_PIOC_MDSR      (*(RoReg*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
+#define REG_PIOC_PUDR      (*(WoReg*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
+#define REG_PIOC_PUER      (*(WoReg*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
+#define REG_PIOC_PUSR      (*(RoReg*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
+#define REG_PIOC_ABCDSR    (*(RwReg*)0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */
+#define REG_PIOC_IFSCDR    (*(WoReg*)0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
+#define REG_PIOC_IFSCER    (*(WoReg*)0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
+#define REG_PIOC_IFSCSR    (*(RoReg*)0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
+#define REG_PIOC_SCDR      (*(RwReg*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
+#define REG_PIOC_PPDDR     (*(WoReg*)0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */
+#define REG_PIOC_PPDER     (*(WoReg*)0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */
+#define REG_PIOC_PPDSR     (*(RoReg*)0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */
+#define REG_PIOC_OWER      (*(WoReg*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
+#define REG_PIOC_OWDR      (*(WoReg*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
+#define REG_PIOC_OWSR      (*(RoReg*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
+#define REG_PIOC_AIMER     (*(WoReg*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
+#define REG_PIOC_AIMDR     (*(WoReg*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
+#define REG_PIOC_AIMMR     (*(RoReg*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
+#define REG_PIOC_ESR       (*(WoReg*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
+#define REG_PIOC_LSR       (*(WoReg*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */
+#define REG_PIOC_ELSR      (*(RoReg*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
+#define REG_PIOC_FELLSR    (*(WoReg*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
+#define REG_PIOC_REHLSR    (*(WoReg*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
+#define REG_PIOC_FRLHSR    (*(RoReg*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
+#define REG_PIOC_LOCKSR    (*(RoReg*)0x400E12E0U) /**< \brief (PIOC) Lock Status */
+#define REG_PIOC_WPMR      (*(RwReg*)0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
+#define REG_PIOC_WPSR      (*(RoReg*)0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
+#define REG_PIOC_SCHMITT   (*(RwReg*)0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */
+#define REG_PIOC_PCMR      (*(RwReg*)0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */
+#define REG_PIOC_PCIER     (*(WoReg*)0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */
+#define REG_PIOC_PCIDR     (*(WoReg*)0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */
+#define REG_PIOC_PCIMR     (*(RoReg*)0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */
+#define REG_PIOC_PCISR     (*(RoReg*)0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */
+#define REG_PIOC_PCRHR     (*(RoReg*)0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_PIOC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_pmc.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_pmc.h
new file mode 100644
index 000000000..b4b0d05a7
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_pmc.h
@@ -0,0 +1,90 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_PMC_INSTANCE_
+#define _SAM3S8_PMC_INSTANCE_
+
+/* ========== Register definition for PMC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PMC_SCER            (0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
+#define REG_PMC_SCDR            (0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
+#define REG_PMC_SCSR            (0x400E0408U) /**< \brief (PMC) System Clock Status Register */
+#define REG_PMC_PCER0           (0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
+#define REG_PMC_PCDR0           (0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
+#define REG_PMC_PCSR0           (0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
+#define REG_CKGR_MOR            (0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
+#define REG_CKGR_MCFR           (0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
+#define REG_CKGR_PLLAR          (0x400E0428U) /**< \brief (PMC) PLLA Register */
+#define REG_CKGR_PLLBR          (0x400E042CU) /**< \brief (PMC) PLLB Register */
+#define REG_PMC_MCKR            (0x400E0430U) /**< \brief (PMC) Master Clock Register */
+#define REG_PMC_USB             (0x400E0438U) /**< \brief (PMC) USB Clock Register */
+#define REG_PMC_PCK             (0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
+#define REG_PMC_IER             (0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
+#define REG_PMC_IDR             (0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
+#define REG_PMC_SR              (0x400E0468U) /**< \brief (PMC) Status Register */
+#define REG_PMC_IMR             (0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
+#define REG_PMC_FSMR            (0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
+#define REG_PMC_FSPR            (0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
+#define REG_PMC_FOCR            (0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
+#define REG_PMC_WPMR            (0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
+#define REG_PMC_WPSR            (0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
+#define REG_PMC_PCER1           (0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
+#define REG_PMC_PCDR1           (0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
+#define REG_PMC_PCSR1           (0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
+#define REG_PMC_OCR             (0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */
+#else
+#define REG_PMC_SCER   (*(WoReg*)0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
+#define REG_PMC_SCDR   (*(WoReg*)0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
+#define REG_PMC_SCSR   (*(RoReg*)0x400E0408U) /**< \brief (PMC) System Clock Status Register */
+#define REG_PMC_PCER0  (*(WoReg*)0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
+#define REG_PMC_PCDR0  (*(WoReg*)0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
+#define REG_PMC_PCSR0  (*(RoReg*)0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
+#define REG_CKGR_MOR   (*(RwReg*)0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
+#define REG_CKGR_MCFR  (*(RwReg*)0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
+#define REG_CKGR_PLLAR (*(RwReg*)0x400E0428U) /**< \brief (PMC) PLLA Register */
+#define REG_CKGR_PLLBR (*(RwReg*)0x400E042CU) /**< \brief (PMC) PLLB Register */
+#define REG_PMC_MCKR   (*(RwReg*)0x400E0430U) /**< \brief (PMC) Master Clock Register */
+#define REG_PMC_USB    (*(RwReg*)0x400E0438U) /**< \brief (PMC) USB Clock Register */
+#define REG_PMC_PCK    (*(RwReg*)0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
+#define REG_PMC_IER    (*(WoReg*)0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
+#define REG_PMC_IDR    (*(WoReg*)0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
+#define REG_PMC_SR     (*(RoReg*)0x400E0468U) /**< \brief (PMC) Status Register */
+#define REG_PMC_IMR    (*(RoReg*)0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
+#define REG_PMC_FSMR   (*(RwReg*)0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
+#define REG_PMC_FSPR   (*(RwReg*)0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
+#define REG_PMC_FOCR   (*(WoReg*)0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
+#define REG_PMC_WPMR   (*(RwReg*)0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
+#define REG_PMC_WPSR   (*(RoReg*)0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
+#define REG_PMC_PCER1  (*(WoReg*)0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
+#define REG_PMC_PCDR1  (*(WoReg*)0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
+#define REG_PMC_PCSR1  (*(RoReg*)0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
+#define REG_PMC_OCR    (*(RwReg*)0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_PMC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_pwm.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_pwm.h
new file mode 100644
index 000000000..033a0fd5e
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_pwm.h
@@ -0,0 +1,248 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_PWM_INSTANCE_
+#define _SAM3S8_PWM_INSTANCE_
+
+/* ========== Register definition for PWM peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PWM_CLK               (0x40020000U) /**< \brief (PWM) PWM Clock Register */
+#define REG_PWM_ENA               (0x40020004U) /**< \brief (PWM) PWM Enable Register */
+#define REG_PWM_DIS               (0x40020008U) /**< \brief (PWM) PWM Disable Register */
+#define REG_PWM_SR                (0x4002000CU) /**< \brief (PWM) PWM Status Register */
+#define REG_PWM_IER1              (0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
+#define REG_PWM_IDR1              (0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
+#define REG_PWM_IMR1              (0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
+#define REG_PWM_ISR1              (0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
+#define REG_PWM_SCM               (0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
+#define REG_PWM_SCUC              (0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
+#define REG_PWM_SCUP              (0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
+#define REG_PWM_SCUPUPD           (0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
+#define REG_PWM_IER2              (0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
+#define REG_PWM_IDR2              (0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
+#define REG_PWM_IMR2              (0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
+#define REG_PWM_ISR2              (0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
+#define REG_PWM_OOV               (0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */
+#define REG_PWM_OS                (0x40020048U) /**< \brief (PWM) PWM Output Selection Register */
+#define REG_PWM_OSS               (0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */
+#define REG_PWM_OSC               (0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */
+#define REG_PWM_OSSUPD            (0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
+#define REG_PWM_OSCUPD            (0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
+#define REG_PWM_FMR               (0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */
+#define REG_PWM_FSR               (0x40020060U) /**< \brief (PWM) PWM Fault Status Register */
+#define REG_PWM_FCR               (0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */
+#define REG_PWM_FPV               (0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */
+#define REG_PWM_FPE               (0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */
+#define REG_PWM_ELMR              (0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
+#define REG_PWM_SMMR              (0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */
+#define REG_PWM_WPCR              (0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */
+#define REG_PWM_WPSR              (0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */
+#define REG_PWM_RPR               (0x40020100U) /**< \brief (PWM) Receive Pointer Register */
+#define REG_PWM_RCR               (0x40020104U) /**< \brief (PWM) Receive Counter Register */
+#define REG_PWM_TPR               (0x40020108U) /**< \brief (PWM) Transmit Pointer Register */
+#define REG_PWM_TCR               (0x4002010CU) /**< \brief (PWM) Transmit Counter Register */
+#define REG_PWM_RNPR              (0x40020110U) /**< \brief (PWM) Receive Next Pointer Register */
+#define REG_PWM_RNCR              (0x40020114U) /**< \brief (PWM) Receive Next Counter Register */
+#define REG_PWM_TNPR              (0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */
+#define REG_PWM_TNCR              (0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */
+#define REG_PWM_PTCR              (0x40020120U) /**< \brief (PWM) Transfer Control Register */
+#define REG_PWM_PTSR              (0x40020124U) /**< \brief (PWM) Transfer Status Register */
+#define REG_PWM_CMPV0             (0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
+#define REG_PWM_CMPVUPD0          (0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
+#define REG_PWM_CMPM0             (0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
+#define REG_PWM_CMPMUPD0          (0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
+#define REG_PWM_CMPV1             (0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
+#define REG_PWM_CMPVUPD1          (0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
+#define REG_PWM_CMPM1             (0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
+#define REG_PWM_CMPMUPD1          (0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
+#define REG_PWM_CMPV2             (0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
+#define REG_PWM_CMPVUPD2          (0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
+#define REG_PWM_CMPM2             (0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
+#define REG_PWM_CMPMUPD2          (0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
+#define REG_PWM_CMPV3             (0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
+#define REG_PWM_CMPVUPD3          (0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
+#define REG_PWM_CMPM3             (0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
+#define REG_PWM_CMPMUPD3          (0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
+#define REG_PWM_CMPV4             (0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
+#define REG_PWM_CMPVUPD4          (0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
+#define REG_PWM_CMPM4             (0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
+#define REG_PWM_CMPMUPD4          (0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
+#define REG_PWM_CMPV5             (0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
+#define REG_PWM_CMPVUPD5          (0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
+#define REG_PWM_CMPM5             (0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
+#define REG_PWM_CMPMUPD5          (0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
+#define REG_PWM_CMPV6             (0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
+#define REG_PWM_CMPVUPD6          (0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
+#define REG_PWM_CMPM6             (0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
+#define REG_PWM_CMPMUPD6          (0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
+#define REG_PWM_CMPV7             (0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
+#define REG_PWM_CMPVUPD7          (0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
+#define REG_PWM_CMPM7             (0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
+#define REG_PWM_CMPMUPD7          (0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
+#define REG_PWM_CMR0              (0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
+#define REG_PWM_CDTY0             (0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
+#define REG_PWM_CDTYUPD0          (0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
+#define REG_PWM_CPRD0             (0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
+#define REG_PWM_CPRDUPD0          (0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
+#define REG_PWM_CCNT0             (0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
+#define REG_PWM_DT0               (0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
+#define REG_PWM_DTUPD0            (0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
+#define REG_PWM_CMR1              (0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
+#define REG_PWM_CDTY1             (0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
+#define REG_PWM_CDTYUPD1          (0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
+#define REG_PWM_CPRD1             (0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
+#define REG_PWM_CPRDUPD1          (0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
+#define REG_PWM_CCNT1             (0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
+#define REG_PWM_DT1               (0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
+#define REG_PWM_DTUPD1            (0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
+#define REG_PWM_CMR2              (0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
+#define REG_PWM_CDTY2             (0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
+#define REG_PWM_CDTYUPD2          (0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
+#define REG_PWM_CPRD2             (0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
+#define REG_PWM_CPRDUPD2          (0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
+#define REG_PWM_CCNT2             (0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
+#define REG_PWM_DT2               (0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
+#define REG_PWM_DTUPD2            (0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
+#define REG_PWM_CMR3              (0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
+#define REG_PWM_CDTY3             (0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
+#define REG_PWM_CDTYUPD3          (0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
+#define REG_PWM_CPRD3             (0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
+#define REG_PWM_CPRDUPD3          (0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
+#define REG_PWM_CCNT3             (0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
+#define REG_PWM_DT3               (0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
+#define REG_PWM_DTUPD3            (0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
+#else
+#define REG_PWM_CLK      (*(RwReg*)0x40020000U) /**< \brief (PWM) PWM Clock Register */
+#define REG_PWM_ENA      (*(WoReg*)0x40020004U) /**< \brief (PWM) PWM Enable Register */
+#define REG_PWM_DIS      (*(WoReg*)0x40020008U) /**< \brief (PWM) PWM Disable Register */
+#define REG_PWM_SR       (*(RoReg*)0x4002000CU) /**< \brief (PWM) PWM Status Register */
+#define REG_PWM_IER1     (*(WoReg*)0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
+#define REG_PWM_IDR1     (*(WoReg*)0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
+#define REG_PWM_IMR1     (*(RoReg*)0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
+#define REG_PWM_ISR1     (*(RoReg*)0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
+#define REG_PWM_SCM      (*(RwReg*)0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
+#define REG_PWM_SCUC     (*(RwReg*)0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
+#define REG_PWM_SCUP     (*(RwReg*)0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
+#define REG_PWM_SCUPUPD  (*(WoReg*)0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
+#define REG_PWM_IER2     (*(WoReg*)0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
+#define REG_PWM_IDR2     (*(WoReg*)0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
+#define REG_PWM_IMR2     (*(RoReg*)0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
+#define REG_PWM_ISR2     (*(RoReg*)0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
+#define REG_PWM_OOV      (*(RwReg*)0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */
+#define REG_PWM_OS       (*(RwReg*)0x40020048U) /**< \brief (PWM) PWM Output Selection Register */
+#define REG_PWM_OSS      (*(WoReg*)0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */
+#define REG_PWM_OSC      (*(WoReg*)0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */
+#define REG_PWM_OSSUPD   (*(WoReg*)0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
+#define REG_PWM_OSCUPD   (*(WoReg*)0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
+#define REG_PWM_FMR      (*(RwReg*)0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */
+#define REG_PWM_FSR      (*(RoReg*)0x40020060U) /**< \brief (PWM) PWM Fault Status Register */
+#define REG_PWM_FCR      (*(WoReg*)0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */
+#define REG_PWM_FPV      (*(RwReg*)0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */
+#define REG_PWM_FPE      (*(RwReg*)0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */
+#define REG_PWM_ELMR     (*(RwReg*)0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
+#define REG_PWM_SMMR     (*(RwReg*)0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */
+#define REG_PWM_WPCR     (*(WoReg*)0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */
+#define REG_PWM_WPSR     (*(RoReg*)0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */
+#define REG_PWM_RPR      (*(RwReg*)0x40020100U) /**< \brief (PWM) Receive Pointer Register */
+#define REG_PWM_RCR      (*(RwReg*)0x40020104U) /**< \brief (PWM) Receive Counter Register */
+#define REG_PWM_TPR      (*(RwReg*)0x40020108U) /**< \brief (PWM) Transmit Pointer Register */
+#define REG_PWM_TCR      (*(RwReg*)0x4002010CU) /**< \brief (PWM) Transmit Counter Register */
+#define REG_PWM_RNPR     (*(RwReg*)0x40020110U) /**< \brief (PWM) Receive Next Pointer Register */
+#define REG_PWM_RNCR     (*(RwReg*)0x40020114U) /**< \brief (PWM) Receive Next Counter Register */
+#define REG_PWM_TNPR     (*(RwReg*)0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */
+#define REG_PWM_TNCR     (*(RwReg*)0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */
+#define REG_PWM_PTCR     (*(WoReg*)0x40020120U) /**< \brief (PWM) Transfer Control Register */
+#define REG_PWM_PTSR     (*(RoReg*)0x40020124U) /**< \brief (PWM) Transfer Status Register */
+#define REG_PWM_CMPV0    (*(RwReg*)0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
+#define REG_PWM_CMPVUPD0 (*(WoReg*)0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
+#define REG_PWM_CMPM0    (*(RwReg*)0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
+#define REG_PWM_CMPMUPD0 (*(WoReg*)0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
+#define REG_PWM_CMPV1    (*(RwReg*)0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
+#define REG_PWM_CMPVUPD1 (*(WoReg*)0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
+#define REG_PWM_CMPM1    (*(RwReg*)0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
+#define REG_PWM_CMPMUPD1 (*(WoReg*)0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
+#define REG_PWM_CMPV2    (*(RwReg*)0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
+#define REG_PWM_CMPVUPD2 (*(WoReg*)0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
+#define REG_PWM_CMPM2    (*(RwReg*)0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
+#define REG_PWM_CMPMUPD2 (*(WoReg*)0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
+#define REG_PWM_CMPV3    (*(RwReg*)0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
+#define REG_PWM_CMPVUPD3 (*(WoReg*)0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
+#define REG_PWM_CMPM3    (*(RwReg*)0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
+#define REG_PWM_CMPMUPD3 (*(WoReg*)0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
+#define REG_PWM_CMPV4    (*(RwReg*)0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
+#define REG_PWM_CMPVUPD4 (*(WoReg*)0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
+#define REG_PWM_CMPM4    (*(RwReg*)0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
+#define REG_PWM_CMPMUPD4 (*(WoReg*)0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
+#define REG_PWM_CMPV5    (*(RwReg*)0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
+#define REG_PWM_CMPVUPD5 (*(WoReg*)0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
+#define REG_PWM_CMPM5    (*(RwReg*)0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
+#define REG_PWM_CMPMUPD5 (*(WoReg*)0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
+#define REG_PWM_CMPV6    (*(RwReg*)0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
+#define REG_PWM_CMPVUPD6 (*(WoReg*)0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
+#define REG_PWM_CMPM6    (*(RwReg*)0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
+#define REG_PWM_CMPMUPD6 (*(WoReg*)0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
+#define REG_PWM_CMPV7    (*(RwReg*)0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
+#define REG_PWM_CMPVUPD7 (*(WoReg*)0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
+#define REG_PWM_CMPM7    (*(RwReg*)0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
+#define REG_PWM_CMPMUPD7 (*(WoReg*)0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
+#define REG_PWM_CMR0     (*(RwReg*)0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
+#define REG_PWM_CDTY0    (*(RwReg*)0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
+#define REG_PWM_CDTYUPD0 (*(WoReg*)0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
+#define REG_PWM_CPRD0    (*(RwReg*)0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
+#define REG_PWM_CPRDUPD0 (*(WoReg*)0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
+#define REG_PWM_CCNT0    (*(RoReg*)0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
+#define REG_PWM_DT0      (*(RwReg*)0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
+#define REG_PWM_DTUPD0   (*(WoReg*)0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
+#define REG_PWM_CMR1     (*(RwReg*)0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
+#define REG_PWM_CDTY1    (*(RwReg*)0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
+#define REG_PWM_CDTYUPD1 (*(WoReg*)0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
+#define REG_PWM_CPRD1    (*(RwReg*)0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
+#define REG_PWM_CPRDUPD1 (*(WoReg*)0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
+#define REG_PWM_CCNT1    (*(RoReg*)0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
+#define REG_PWM_DT1      (*(RwReg*)0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
+#define REG_PWM_DTUPD1   (*(WoReg*)0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
+#define REG_PWM_CMR2     (*(RwReg*)0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
+#define REG_PWM_CDTY2    (*(RwReg*)0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
+#define REG_PWM_CDTYUPD2 (*(WoReg*)0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
+#define REG_PWM_CPRD2    (*(RwReg*)0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
+#define REG_PWM_CPRDUPD2 (*(WoReg*)0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
+#define REG_PWM_CCNT2    (*(RoReg*)0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
+#define REG_PWM_DT2      (*(RwReg*)0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
+#define REG_PWM_DTUPD2   (*(WoReg*)0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
+#define REG_PWM_CMR3     (*(RwReg*)0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
+#define REG_PWM_CDTY3    (*(RwReg*)0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
+#define REG_PWM_CDTYUPD3 (*(WoReg*)0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
+#define REG_PWM_CPRD3    (*(RwReg*)0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
+#define REG_PWM_CPRDUPD3 (*(WoReg*)0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
+#define REG_PWM_CCNT3    (*(RoReg*)0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
+#define REG_PWM_DT3      (*(RwReg*)0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
+#define REG_PWM_DTUPD3   (*(WoReg*)0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_PWM_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_rstc.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_rstc.h
new file mode 100644
index 000000000..a4460f498
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_rstc.h
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_RSTC_INSTANCE_
+#define _SAM3S8_RSTC_INSTANCE_
+
+/* ========== Register definition for RSTC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_RSTC_CR          (0x400E1400U) /**< \brief (RSTC) Control Register */
+#define REG_RSTC_SR          (0x400E1404U) /**< \brief (RSTC) Status Register */
+#define REG_RSTC_MR          (0x400E1408U) /**< \brief (RSTC) Mode Register */
+#else
+#define REG_RSTC_CR (*(WoReg*)0x400E1400U) /**< \brief (RSTC) Control Register */
+#define REG_RSTC_SR (*(RoReg*)0x400E1404U) /**< \brief (RSTC) Status Register */
+#define REG_RSTC_MR (*(RwReg*)0x400E1408U) /**< \brief (RSTC) Mode Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_RSTC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_rtc.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_rtc.h
new file mode 100644
index 000000000..1579d422c
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_rtc.h
@@ -0,0 +1,62 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_RTC_INSTANCE_
+#define _SAM3S8_RTC_INSTANCE_
+
+/* ========== Register definition for RTC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_RTC_CR              (0x400E1460U) /**< \brief (RTC) Control Register */
+#define REG_RTC_MR              (0x400E1464U) /**< \brief (RTC) Mode Register */
+#define REG_RTC_TIMR            (0x400E1468U) /**< \brief (RTC) Time Register */
+#define REG_RTC_CALR            (0x400E146CU) /**< \brief (RTC) Calendar Register */
+#define REG_RTC_TIMALR          (0x400E1470U) /**< \brief (RTC) Time Alarm Register */
+#define REG_RTC_CALALR          (0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */
+#define REG_RTC_SR              (0x400E1478U) /**< \brief (RTC) Status Register */
+#define REG_RTC_SCCR            (0x400E147CU) /**< \brief (RTC) Status Clear Command Register */
+#define REG_RTC_IER             (0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */
+#define REG_RTC_IDR             (0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */
+#define REG_RTC_IMR             (0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */
+#define REG_RTC_VER             (0x400E148CU) /**< \brief (RTC) Valid Entry Register */
+#else
+#define REG_RTC_CR     (*(RwReg*)0x400E1460U) /**< \brief (RTC) Control Register */
+#define REG_RTC_MR     (*(RwReg*)0x400E1464U) /**< \brief (RTC) Mode Register */
+#define REG_RTC_TIMR   (*(RwReg*)0x400E1468U) /**< \brief (RTC) Time Register */
+#define REG_RTC_CALR   (*(RwReg*)0x400E146CU) /**< \brief (RTC) Calendar Register */
+#define REG_RTC_TIMALR (*(RwReg*)0x400E1470U) /**< \brief (RTC) Time Alarm Register */
+#define REG_RTC_CALALR (*(RwReg*)0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */
+#define REG_RTC_SR     (*(RoReg*)0x400E1478U) /**< \brief (RTC) Status Register */
+#define REG_RTC_SCCR   (*(WoReg*)0x400E147CU) /**< \brief (RTC) Status Clear Command Register */
+#define REG_RTC_IER    (*(WoReg*)0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */
+#define REG_RTC_IDR    (*(WoReg*)0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */
+#define REG_RTC_IMR    (*(RoReg*)0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */
+#define REG_RTC_VER    (*(RoReg*)0x400E148CU) /**< \brief (RTC) Valid Entry Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_RTC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_rtt.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_rtt.h
new file mode 100644
index 000000000..47fc384be
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_rtt.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_RTT_INSTANCE_
+#define _SAM3S8_RTT_INSTANCE_
+
+/* ========== Register definition for RTT peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_RTT_MR          (0x400E1430U) /**< \brief (RTT) Mode Register */
+#define REG_RTT_AR          (0x400E1434U) /**< \brief (RTT) Alarm Register */
+#define REG_RTT_VR          (0x400E1438U) /**< \brief (RTT) Value Register */
+#define REG_RTT_SR          (0x400E143CU) /**< \brief (RTT) Status Register */
+#else
+#define REG_RTT_MR (*(RwReg*)0x400E1430U) /**< \brief (RTT) Mode Register */
+#define REG_RTT_AR (*(RwReg*)0x400E1434U) /**< \brief (RTT) Alarm Register */
+#define REG_RTT_VR (*(RoReg*)0x400E1438U) /**< \brief (RTT) Value Register */
+#define REG_RTT_SR (*(RoReg*)0x400E143CU) /**< \brief (RTT) Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_RTT_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_smc.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_smc.h
new file mode 100644
index 000000000..43da6421e
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_smc.h
@@ -0,0 +1,88 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_SMC_INSTANCE_
+#define _SAM3S8_SMC_INSTANCE_
+
+/* ========== Register definition for SMC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_SMC_SETUP0          (0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
+#define REG_SMC_PULSE0          (0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
+#define REG_SMC_CYCLE0          (0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
+#define REG_SMC_MODE0           (0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
+#define REG_SMC_SETUP1          (0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
+#define REG_SMC_PULSE1          (0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
+#define REG_SMC_CYCLE1          (0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
+#define REG_SMC_MODE1           (0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
+#define REG_SMC_SETUP2          (0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
+#define REG_SMC_PULSE2          (0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
+#define REG_SMC_CYCLE2          (0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
+#define REG_SMC_MODE2           (0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
+#define REG_SMC_SETUP3          (0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
+#define REG_SMC_PULSE3          (0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
+#define REG_SMC_CYCLE3          (0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
+#define REG_SMC_MODE3           (0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
+#define REG_SMC_SETUP4          (0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */
+#define REG_SMC_PULSE4          (0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */
+#define REG_SMC_CYCLE4          (0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */
+#define REG_SMC_MODE4           (0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */
+#define REG_SMC_OCMS            (0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */
+#define REG_SMC_KEY1            (0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */
+#define REG_SMC_KEY2            (0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */
+#define REG_SMC_WPMR            (0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */
+#define REG_SMC_WPSR            (0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */
+#else
+#define REG_SMC_SETUP0 (*(RwReg*)0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
+#define REG_SMC_PULSE0 (*(RwReg*)0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
+#define REG_SMC_CYCLE0 (*(RwReg*)0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
+#define REG_SMC_MODE0  (*(RwReg*)0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
+#define REG_SMC_SETUP1 (*(RwReg*)0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
+#define REG_SMC_PULSE1 (*(RwReg*)0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
+#define REG_SMC_CYCLE1 (*(RwReg*)0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
+#define REG_SMC_MODE1  (*(RwReg*)0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
+#define REG_SMC_SETUP2 (*(RwReg*)0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
+#define REG_SMC_PULSE2 (*(RwReg*)0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
+#define REG_SMC_CYCLE2 (*(RwReg*)0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
+#define REG_SMC_MODE2  (*(RwReg*)0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
+#define REG_SMC_SETUP3 (*(RwReg*)0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
+#define REG_SMC_PULSE3 (*(RwReg*)0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
+#define REG_SMC_CYCLE3 (*(RwReg*)0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
+#define REG_SMC_MODE3  (*(RwReg*)0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
+#define REG_SMC_SETUP4 (*(RwReg*)0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */
+#define REG_SMC_PULSE4 (*(RwReg*)0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */
+#define REG_SMC_CYCLE4 (*(RwReg*)0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */
+#define REG_SMC_MODE4  (*(RwReg*)0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */
+#define REG_SMC_OCMS   (*(RwReg*)0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */
+#define REG_SMC_KEY1   (*(WoReg*)0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */
+#define REG_SMC_KEY2   (*(WoReg*)0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */
+#define REG_SMC_WPMR   (*(RwReg*)0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */
+#define REG_SMC_WPSR   (*(RoReg*)0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_SMC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_spi.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_spi.h
new file mode 100644
index 000000000..f35286dd6
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_spi.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_SPI_INSTANCE_
+#define _SAM3S8_SPI_INSTANCE_
+
+/* ========== Register definition for SPI peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_SPI_CR              (0x40008000U) /**< \brief (SPI) Control Register */
+#define REG_SPI_MR              (0x40008004U) /**< \brief (SPI) Mode Register */
+#define REG_SPI_RDR             (0x40008008U) /**< \brief (SPI) Receive Data Register */
+#define REG_SPI_TDR             (0x4000800CU) /**< \brief (SPI) Transmit Data Register */
+#define REG_SPI_SR              (0x40008010U) /**< \brief (SPI) Status Register */
+#define REG_SPI_IER             (0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
+#define REG_SPI_IDR             (0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
+#define REG_SPI_IMR             (0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
+#define REG_SPI_CSR             (0x40008030U) /**< \brief (SPI) Chip Select Register */
+#define REG_SPI_WPMR            (0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
+#define REG_SPI_WPSR            (0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
+#define REG_SPI_RPR             (0x40008100U) /**< \brief (SPI) Receive Pointer Register */
+#define REG_SPI_RCR             (0x40008104U) /**< \brief (SPI) Receive Counter Register */
+#define REG_SPI_TPR             (0x40008108U) /**< \brief (SPI) Transmit Pointer Register */
+#define REG_SPI_TCR             (0x4000810CU) /**< \brief (SPI) Transmit Counter Register */
+#define REG_SPI_RNPR            (0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */
+#define REG_SPI_RNCR            (0x40008114U) /**< \brief (SPI) Receive Next Counter Register */
+#define REG_SPI_TNPR            (0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */
+#define REG_SPI_TNCR            (0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */
+#define REG_SPI_PTCR            (0x40008120U) /**< \brief (SPI) Transfer Control Register */
+#define REG_SPI_PTSR            (0x40008124U) /**< \brief (SPI) Transfer Status Register */
+#else
+#define REG_SPI_CR     (*(WoReg*)0x40008000U) /**< \brief (SPI) Control Register */
+#define REG_SPI_MR     (*(RwReg*)0x40008004U) /**< \brief (SPI) Mode Register */
+#define REG_SPI_RDR    (*(RoReg*)0x40008008U) /**< \brief (SPI) Receive Data Register */
+#define REG_SPI_TDR    (*(WoReg*)0x4000800CU) /**< \brief (SPI) Transmit Data Register */
+#define REG_SPI_SR     (*(RoReg*)0x40008010U) /**< \brief (SPI) Status Register */
+#define REG_SPI_IER    (*(WoReg*)0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
+#define REG_SPI_IDR    (*(WoReg*)0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
+#define REG_SPI_IMR    (*(RoReg*)0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
+#define REG_SPI_CSR    (*(RwReg*)0x40008030U) /**< \brief (SPI) Chip Select Register */
+#define REG_SPI_WPMR   (*(RwReg*)0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
+#define REG_SPI_WPSR   (*(RoReg*)0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
+#define REG_SPI_RPR    (*(RwReg*)0x40008100U) /**< \brief (SPI) Receive Pointer Register */
+#define REG_SPI_RCR    (*(RwReg*)0x40008104U) /**< \brief (SPI) Receive Counter Register */
+#define REG_SPI_TPR    (*(RwReg*)0x40008108U) /**< \brief (SPI) Transmit Pointer Register */
+#define REG_SPI_TCR    (*(RwReg*)0x4000810CU) /**< \brief (SPI) Transmit Counter Register */
+#define REG_SPI_RNPR   (*(RwReg*)0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */
+#define REG_SPI_RNCR   (*(RwReg*)0x40008114U) /**< \brief (SPI) Receive Next Counter Register */
+#define REG_SPI_TNPR   (*(RwReg*)0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */
+#define REG_SPI_TNCR   (*(RwReg*)0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */
+#define REG_SPI_PTCR   (*(WoReg*)0x40008120U) /**< \brief (SPI) Transfer Control Register */
+#define REG_SPI_PTSR   (*(RoReg*)0x40008124U) /**< \brief (SPI) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_SPI_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_ssc.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_ssc.h
new file mode 100644
index 000000000..c5f9f00a0
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_ssc.h
@@ -0,0 +1,94 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_SSC_INSTANCE_
+#define _SAM3S8_SSC_INSTANCE_
+
+/* ========== Register definition for SSC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_SSC_CR            (0x40004000U) /**< \brief (SSC) Control Register */
+#define REG_SSC_CMR           (0x40004004U) /**< \brief (SSC) Clock Mode Register */
+#define REG_SSC_RCMR          (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
+#define REG_SSC_RFMR          (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
+#define REG_SSC_TCMR          (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
+#define REG_SSC_TFMR          (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
+#define REG_SSC_RHR           (0x40004020U) /**< \brief (SSC) Receive Holding Register */
+#define REG_SSC_THR           (0x40004024U) /**< \brief (SSC) Transmit Holding Register */
+#define REG_SSC_RSHR          (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
+#define REG_SSC_TSHR          (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
+#define REG_SSC_RC0R          (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
+#define REG_SSC_RC1R          (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
+#define REG_SSC_SR            (0x40004040U) /**< \brief (SSC) Status Register */
+#define REG_SSC_IER           (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
+#define REG_SSC_IDR           (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
+#define REG_SSC_IMR           (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
+#define REG_SSC_WPMR          (0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
+#define REG_SSC_WPSR          (0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
+#define REG_SSC_RPR           (0x40004100U) /**< \brief (SSC) Receive Pointer Register */
+#define REG_SSC_RCR           (0x40004104U) /**< \brief (SSC) Receive Counter Register */
+#define REG_SSC_TPR           (0x40004108U) /**< \brief (SSC) Transmit Pointer Register */
+#define REG_SSC_TCR           (0x4000410CU) /**< \brief (SSC) Transmit Counter Register */
+#define REG_SSC_RNPR          (0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */
+#define REG_SSC_RNCR          (0x40004114U) /**< \brief (SSC) Receive Next Counter Register */
+#define REG_SSC_TNPR          (0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */
+#define REG_SSC_TNCR          (0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */
+#define REG_SSC_PTCR          (0x40004120U) /**< \brief (SSC) Transfer Control Register */
+#define REG_SSC_PTSR          (0x40004124U) /**< \brief (SSC) Transfer Status Register */
+#else
+#define REG_SSC_CR   (*(WoReg*)0x40004000U) /**< \brief (SSC) Control Register */
+#define REG_SSC_CMR  (*(RwReg*)0x40004004U) /**< \brief (SSC) Clock Mode Register */
+#define REG_SSC_RCMR (*(RwReg*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
+#define REG_SSC_RFMR (*(RwReg*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
+#define REG_SSC_TCMR (*(RwReg*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
+#define REG_SSC_TFMR (*(RwReg*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
+#define REG_SSC_RHR  (*(RoReg*)0x40004020U) /**< \brief (SSC) Receive Holding Register */
+#define REG_SSC_THR  (*(WoReg*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */
+#define REG_SSC_RSHR (*(RoReg*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
+#define REG_SSC_TSHR (*(RwReg*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
+#define REG_SSC_RC0R (*(RwReg*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
+#define REG_SSC_RC1R (*(RwReg*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
+#define REG_SSC_SR   (*(RoReg*)0x40004040U) /**< \brief (SSC) Status Register */
+#define REG_SSC_IER  (*(WoReg*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
+#define REG_SSC_IDR  (*(WoReg*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
+#define REG_SSC_IMR  (*(RoReg*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
+#define REG_SSC_WPMR (*(RwReg*)0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
+#define REG_SSC_WPSR (*(RoReg*)0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
+#define REG_SSC_RPR  (*(RwReg*)0x40004100U) /**< \brief (SSC) Receive Pointer Register */
+#define REG_SSC_RCR  (*(RwReg*)0x40004104U) /**< \brief (SSC) Receive Counter Register */
+#define REG_SSC_TPR  (*(RwReg*)0x40004108U) /**< \brief (SSC) Transmit Pointer Register */
+#define REG_SSC_TCR  (*(RwReg*)0x4000410CU) /**< \brief (SSC) Transmit Counter Register */
+#define REG_SSC_RNPR (*(RwReg*)0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */
+#define REG_SSC_RNCR (*(RwReg*)0x40004114U) /**< \brief (SSC) Receive Next Counter Register */
+#define REG_SSC_TNPR (*(RwReg*)0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */
+#define REG_SSC_TNCR (*(RwReg*)0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */
+#define REG_SSC_PTCR (*(WoReg*)0x40004120U) /**< \brief (SSC) Transfer Control Register */
+#define REG_SSC_PTSR (*(RoReg*)0x40004124U) /**< \brief (SSC) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_SSC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_supc.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_supc.h
new file mode 100644
index 000000000..29dd98385
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_supc.h
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_SUPC_INSTANCE_
+#define _SAM3S8_SUPC_INSTANCE_
+
+/* ========== Register definition for SUPC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_SUPC_CR            (0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */
+#define REG_SUPC_SMMR          (0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
+#define REG_SUPC_MR            (0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */
+#define REG_SUPC_WUMR          (0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
+#define REG_SUPC_WUIR          (0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
+#define REG_SUPC_SR            (0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */
+#else
+#define REG_SUPC_CR   (*(WoReg*)0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */
+#define REG_SUPC_SMMR (*(RwReg*)0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
+#define REG_SUPC_MR   (*(RwReg*)0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */
+#define REG_SUPC_WUMR (*(RwReg*)0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
+#define REG_SUPC_WUIR (*(RwReg*)0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
+#define REG_SUPC_SR   (*(RoReg*)0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_SUPC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_tc0.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_tc0.h
new file mode 100644
index 000000000..44c6787d1
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_tc0.h
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_TC0_INSTANCE_
+#define _SAM3S8_TC0_INSTANCE_
+
+/* ========== Register definition for TC0 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_TC0_CCR0           (0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
+#define REG_TC0_CMR0           (0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
+#define REG_TC0_SMMR0          (0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC0_CV0            (0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */
+#define REG_TC0_RA0            (0x40010014U) /**< \brief (TC0) Register A (channel = 0) */
+#define REG_TC0_RB0            (0x40010018U) /**< \brief (TC0) Register B (channel = 0) */
+#define REG_TC0_RC0            (0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */
+#define REG_TC0_SR0            (0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */
+#define REG_TC0_IER0           (0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
+#define REG_TC0_IDR0           (0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
+#define REG_TC0_IMR0           (0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
+#define REG_TC0_CCR1           (0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
+#define REG_TC0_CMR1           (0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
+#define REG_TC0_SMMR1          (0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC0_CV1            (0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */
+#define REG_TC0_RA1            (0x40010054U) /**< \brief (TC0) Register A (channel = 1) */
+#define REG_TC0_RB1            (0x40010058U) /**< \brief (TC0) Register B (channel = 1) */
+#define REG_TC0_RC1            (0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */
+#define REG_TC0_SR1            (0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */
+#define REG_TC0_IER1           (0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
+#define REG_TC0_IDR1           (0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
+#define REG_TC0_IMR1           (0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
+#define REG_TC0_CCR2           (0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
+#define REG_TC0_CMR2           (0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
+#define REG_TC0_SMMR2          (0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC0_CV2            (0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */
+#define REG_TC0_RA2            (0x40010094U) /**< \brief (TC0) Register A (channel = 2) */
+#define REG_TC0_RB2            (0x40010098U) /**< \brief (TC0) Register B (channel = 2) */
+#define REG_TC0_RC2            (0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */
+#define REG_TC0_SR2            (0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */
+#define REG_TC0_IER2           (0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
+#define REG_TC0_IDR2           (0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
+#define REG_TC0_IMR2           (0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
+#define REG_TC0_BCR            (0x400100C0U) /**< \brief (TC0) Block Control Register */
+#define REG_TC0_BMR            (0x400100C4U) /**< \brief (TC0) Block Mode Register */
+#define REG_TC0_QIER           (0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
+#define REG_TC0_QIDR           (0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
+#define REG_TC0_QIMR           (0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
+#define REG_TC0_QISR           (0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
+#define REG_TC0_FMR            (0x400100D8U) /**< \brief (TC0) Fault Mode Register */
+#define REG_TC0_WPMR           (0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */
+#else
+#define REG_TC0_CCR0  (*(WoReg*)0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
+#define REG_TC0_CMR0  (*(RwReg*)0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
+#define REG_TC0_SMMR0 (*(RwReg*)0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC0_CV0   (*(RoReg*)0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */
+#define REG_TC0_RA0   (*(RwReg*)0x40010014U) /**< \brief (TC0) Register A (channel = 0) */
+#define REG_TC0_RB0   (*(RwReg*)0x40010018U) /**< \brief (TC0) Register B (channel = 0) */
+#define REG_TC0_RC0   (*(RwReg*)0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */
+#define REG_TC0_SR0   (*(RoReg*)0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */
+#define REG_TC0_IER0  (*(WoReg*)0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
+#define REG_TC0_IDR0  (*(WoReg*)0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
+#define REG_TC0_IMR0  (*(RoReg*)0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
+#define REG_TC0_CCR1  (*(WoReg*)0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
+#define REG_TC0_CMR1  (*(RwReg*)0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
+#define REG_TC0_SMMR1 (*(RwReg*)0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC0_CV1   (*(RoReg*)0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */
+#define REG_TC0_RA1   (*(RwReg*)0x40010054U) /**< \brief (TC0) Register A (channel = 1) */
+#define REG_TC0_RB1   (*(RwReg*)0x40010058U) /**< \brief (TC0) Register B (channel = 1) */
+#define REG_TC0_RC1   (*(RwReg*)0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */
+#define REG_TC0_SR1   (*(RoReg*)0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */
+#define REG_TC0_IER1  (*(WoReg*)0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
+#define REG_TC0_IDR1  (*(WoReg*)0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
+#define REG_TC0_IMR1  (*(RoReg*)0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
+#define REG_TC0_CCR2  (*(WoReg*)0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
+#define REG_TC0_CMR2  (*(RwReg*)0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
+#define REG_TC0_SMMR2 (*(RwReg*)0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC0_CV2   (*(RoReg*)0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */
+#define REG_TC0_RA2   (*(RwReg*)0x40010094U) /**< \brief (TC0) Register A (channel = 2) */
+#define REG_TC0_RB2   (*(RwReg*)0x40010098U) /**< \brief (TC0) Register B (channel = 2) */
+#define REG_TC0_RC2   (*(RwReg*)0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */
+#define REG_TC0_SR2   (*(RoReg*)0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */
+#define REG_TC0_IER2  (*(WoReg*)0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
+#define REG_TC0_IDR2  (*(WoReg*)0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
+#define REG_TC0_IMR2  (*(RoReg*)0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
+#define REG_TC0_BCR   (*(WoReg*)0x400100C0U) /**< \brief (TC0) Block Control Register */
+#define REG_TC0_BMR   (*(RwReg*)0x400100C4U) /**< \brief (TC0) Block Mode Register */
+#define REG_TC0_QIER  (*(WoReg*)0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
+#define REG_TC0_QIDR  (*(WoReg*)0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
+#define REG_TC0_QIMR  (*(RoReg*)0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
+#define REG_TC0_QISR  (*(RoReg*)0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
+#define REG_TC0_FMR   (*(RwReg*)0x400100D8U) /**< \brief (TC0) Fault Mode Register */
+#define REG_TC0_WPMR  (*(RwReg*)0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_TC0_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_tc1.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_tc1.h
new file mode 100644
index 000000000..1cda78bef
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_tc1.h
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_TC1_INSTANCE_
+#define _SAM3S8_TC1_INSTANCE_
+
+/* ========== Register definition for TC1 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_TC1_CCR0           (0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
+#define REG_TC1_CMR0           (0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
+#define REG_TC1_SMMR0          (0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC1_CV0            (0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */
+#define REG_TC1_RA0            (0x40014014U) /**< \brief (TC1) Register A (channel = 0) */
+#define REG_TC1_RB0            (0x40014018U) /**< \brief (TC1) Register B (channel = 0) */
+#define REG_TC1_RC0            (0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */
+#define REG_TC1_SR0            (0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */
+#define REG_TC1_IER0           (0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
+#define REG_TC1_IDR0           (0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
+#define REG_TC1_IMR0           (0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
+#define REG_TC1_CCR1           (0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
+#define REG_TC1_CMR1           (0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
+#define REG_TC1_SMMR1          (0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC1_CV1            (0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */
+#define REG_TC1_RA1            (0x40014054U) /**< \brief (TC1) Register A (channel = 1) */
+#define REG_TC1_RB1            (0x40014058U) /**< \brief (TC1) Register B (channel = 1) */
+#define REG_TC1_RC1            (0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */
+#define REG_TC1_SR1            (0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */
+#define REG_TC1_IER1           (0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
+#define REG_TC1_IDR1           (0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
+#define REG_TC1_IMR1           (0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
+#define REG_TC1_CCR2           (0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
+#define REG_TC1_CMR2           (0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
+#define REG_TC1_SMMR2          (0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC1_CV2            (0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */
+#define REG_TC1_RA2            (0x40014094U) /**< \brief (TC1) Register A (channel = 2) */
+#define REG_TC1_RB2            (0x40014098U) /**< \brief (TC1) Register B (channel = 2) */
+#define REG_TC1_RC2            (0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */
+#define REG_TC1_SR2            (0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */
+#define REG_TC1_IER2           (0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
+#define REG_TC1_IDR2           (0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
+#define REG_TC1_IMR2           (0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
+#define REG_TC1_BCR            (0x400140C0U) /**< \brief (TC1) Block Control Register */
+#define REG_TC1_BMR            (0x400140C4U) /**< \brief (TC1) Block Mode Register */
+#define REG_TC1_QIER           (0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
+#define REG_TC1_QIDR           (0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
+#define REG_TC1_QIMR           (0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
+#define REG_TC1_QISR           (0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
+#define REG_TC1_FMR            (0x400140D8U) /**< \brief (TC1) Fault Mode Register */
+#define REG_TC1_WPMR           (0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */
+#else
+#define REG_TC1_CCR0  (*(WoReg*)0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
+#define REG_TC1_CMR0  (*(RwReg*)0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
+#define REG_TC1_SMMR0 (*(RwReg*)0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC1_CV0   (*(RoReg*)0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */
+#define REG_TC1_RA0   (*(RwReg*)0x40014014U) /**< \brief (TC1) Register A (channel = 0) */
+#define REG_TC1_RB0   (*(RwReg*)0x40014018U) /**< \brief (TC1) Register B (channel = 0) */
+#define REG_TC1_RC0   (*(RwReg*)0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */
+#define REG_TC1_SR0   (*(RoReg*)0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */
+#define REG_TC1_IER0  (*(WoReg*)0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
+#define REG_TC1_IDR0  (*(WoReg*)0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
+#define REG_TC1_IMR0  (*(RoReg*)0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
+#define REG_TC1_CCR1  (*(WoReg*)0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
+#define REG_TC1_CMR1  (*(RwReg*)0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
+#define REG_TC1_SMMR1 (*(RwReg*)0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC1_CV1   (*(RoReg*)0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */
+#define REG_TC1_RA1   (*(RwReg*)0x40014054U) /**< \brief (TC1) Register A (channel = 1) */
+#define REG_TC1_RB1   (*(RwReg*)0x40014058U) /**< \brief (TC1) Register B (channel = 1) */
+#define REG_TC1_RC1   (*(RwReg*)0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */
+#define REG_TC1_SR1   (*(RoReg*)0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */
+#define REG_TC1_IER1  (*(WoReg*)0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
+#define REG_TC1_IDR1  (*(WoReg*)0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
+#define REG_TC1_IMR1  (*(RoReg*)0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
+#define REG_TC1_CCR2  (*(WoReg*)0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
+#define REG_TC1_CMR2  (*(RwReg*)0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
+#define REG_TC1_SMMR2 (*(RwReg*)0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC1_CV2   (*(RoReg*)0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */
+#define REG_TC1_RA2   (*(RwReg*)0x40014094U) /**< \brief (TC1) Register A (channel = 2) */
+#define REG_TC1_RB2   (*(RwReg*)0x40014098U) /**< \brief (TC1) Register B (channel = 2) */
+#define REG_TC1_RC2   (*(RwReg*)0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */
+#define REG_TC1_SR2   (*(RoReg*)0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */
+#define REG_TC1_IER2  (*(WoReg*)0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
+#define REG_TC1_IDR2  (*(WoReg*)0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
+#define REG_TC1_IMR2  (*(RoReg*)0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
+#define REG_TC1_BCR   (*(WoReg*)0x400140C0U) /**< \brief (TC1) Block Control Register */
+#define REG_TC1_BMR   (*(RwReg*)0x400140C4U) /**< \brief (TC1) Block Mode Register */
+#define REG_TC1_QIER  (*(WoReg*)0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
+#define REG_TC1_QIDR  (*(WoReg*)0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
+#define REG_TC1_QIMR  (*(RoReg*)0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
+#define REG_TC1_QISR  (*(RoReg*)0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
+#define REG_TC1_FMR   (*(RwReg*)0x400140D8U) /**< \brief (TC1) Fault Mode Register */
+#define REG_TC1_WPMR  (*(RwReg*)0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_TC1_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_twi0.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_twi0.h
new file mode 100644
index 000000000..ac6a6e852
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_twi0.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_TWI0_INSTANCE_
+#define _SAM3S8_TWI0_INSTANCE_
+
+/* ========== Register definition for TWI0 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_TWI0_CR            (0x40018000U) /**< \brief (TWI0) Control Register */
+#define REG_TWI0_MMR           (0x40018004U) /**< \brief (TWI0) Master Mode Register */
+#define REG_TWI0_SMR           (0x40018008U) /**< \brief (TWI0) Slave Mode Register */
+#define REG_TWI0_IADR          (0x4001800CU) /**< \brief (TWI0) Internal Address Register */
+#define REG_TWI0_CWGR          (0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */
+#define REG_TWI0_SR            (0x40018020U) /**< \brief (TWI0) Status Register */
+#define REG_TWI0_IER           (0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */
+#define REG_TWI0_IDR           (0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */
+#define REG_TWI0_IMR           (0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */
+#define REG_TWI0_RHR           (0x40018030U) /**< \brief (TWI0) Receive Holding Register */
+#define REG_TWI0_THR           (0x40018034U) /**< \brief (TWI0) Transmit Holding Register */
+#define REG_TWI0_RPR           (0x40018100U) /**< \brief (TWI0) Receive Pointer Register */
+#define REG_TWI0_RCR           (0x40018104U) /**< \brief (TWI0) Receive Counter Register */
+#define REG_TWI0_TPR           (0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */
+#define REG_TWI0_TCR           (0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */
+#define REG_TWI0_RNPR          (0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */
+#define REG_TWI0_RNCR          (0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */
+#define REG_TWI0_TNPR          (0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */
+#define REG_TWI0_TNCR          (0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */
+#define REG_TWI0_PTCR          (0x40018120U) /**< \brief (TWI0) Transfer Control Register */
+#define REG_TWI0_PTSR          (0x40018124U) /**< \brief (TWI0) Transfer Status Register */
+#else
+#define REG_TWI0_CR   (*(WoReg*)0x40018000U) /**< \brief (TWI0) Control Register */
+#define REG_TWI0_MMR  (*(RwReg*)0x40018004U) /**< \brief (TWI0) Master Mode Register */
+#define REG_TWI0_SMR  (*(RwReg*)0x40018008U) /**< \brief (TWI0) Slave Mode Register */
+#define REG_TWI0_IADR (*(RwReg*)0x4001800CU) /**< \brief (TWI0) Internal Address Register */
+#define REG_TWI0_CWGR (*(RwReg*)0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */
+#define REG_TWI0_SR   (*(RoReg*)0x40018020U) /**< \brief (TWI0) Status Register */
+#define REG_TWI0_IER  (*(WoReg*)0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */
+#define REG_TWI0_IDR  (*(WoReg*)0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */
+#define REG_TWI0_IMR  (*(RoReg*)0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */
+#define REG_TWI0_RHR  (*(RoReg*)0x40018030U) /**< \brief (TWI0) Receive Holding Register */
+#define REG_TWI0_THR  (*(WoReg*)0x40018034U) /**< \brief (TWI0) Transmit Holding Register */
+#define REG_TWI0_RPR  (*(RwReg*)0x40018100U) /**< \brief (TWI0) Receive Pointer Register */
+#define REG_TWI0_RCR  (*(RwReg*)0x40018104U) /**< \brief (TWI0) Receive Counter Register */
+#define REG_TWI0_TPR  (*(RwReg*)0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */
+#define REG_TWI0_TCR  (*(RwReg*)0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */
+#define REG_TWI0_RNPR (*(RwReg*)0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */
+#define REG_TWI0_RNCR (*(RwReg*)0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */
+#define REG_TWI0_TNPR (*(RwReg*)0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */
+#define REG_TWI0_TNCR (*(RwReg*)0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */
+#define REG_TWI0_PTCR (*(WoReg*)0x40018120U) /**< \brief (TWI0) Transfer Control Register */
+#define REG_TWI0_PTSR (*(RoReg*)0x40018124U) /**< \brief (TWI0) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_TWI0_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_twi1.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_twi1.h
new file mode 100644
index 000000000..f4bdeb96c
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_twi1.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_TWI1_INSTANCE_
+#define _SAM3S8_TWI1_INSTANCE_
+
+/* ========== Register definition for TWI1 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_TWI1_CR            (0x4001C000U) /**< \brief (TWI1) Control Register */
+#define REG_TWI1_MMR           (0x4001C004U) /**< \brief (TWI1) Master Mode Register */
+#define REG_TWI1_SMR           (0x4001C008U) /**< \brief (TWI1) Slave Mode Register */
+#define REG_TWI1_IADR          (0x4001C00CU) /**< \brief (TWI1) Internal Address Register */
+#define REG_TWI1_CWGR          (0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */
+#define REG_TWI1_SR            (0x4001C020U) /**< \brief (TWI1) Status Register */
+#define REG_TWI1_IER           (0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */
+#define REG_TWI1_IDR           (0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */
+#define REG_TWI1_IMR           (0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */
+#define REG_TWI1_RHR           (0x4001C030U) /**< \brief (TWI1) Receive Holding Register */
+#define REG_TWI1_THR           (0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */
+#define REG_TWI1_RPR           (0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */
+#define REG_TWI1_RCR           (0x4001C104U) /**< \brief (TWI1) Receive Counter Register */
+#define REG_TWI1_TPR           (0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */
+#define REG_TWI1_TCR           (0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */
+#define REG_TWI1_RNPR          (0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */
+#define REG_TWI1_RNCR          (0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */
+#define REG_TWI1_TNPR          (0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */
+#define REG_TWI1_TNCR          (0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */
+#define REG_TWI1_PTCR          (0x4001C120U) /**< \brief (TWI1) Transfer Control Register */
+#define REG_TWI1_PTSR          (0x4001C124U) /**< \brief (TWI1) Transfer Status Register */
+#else
+#define REG_TWI1_CR   (*(WoReg*)0x4001C000U) /**< \brief (TWI1) Control Register */
+#define REG_TWI1_MMR  (*(RwReg*)0x4001C004U) /**< \brief (TWI1) Master Mode Register */
+#define REG_TWI1_SMR  (*(RwReg*)0x4001C008U) /**< \brief (TWI1) Slave Mode Register */
+#define REG_TWI1_IADR (*(RwReg*)0x4001C00CU) /**< \brief (TWI1) Internal Address Register */
+#define REG_TWI1_CWGR (*(RwReg*)0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */
+#define REG_TWI1_SR   (*(RoReg*)0x4001C020U) /**< \brief (TWI1) Status Register */
+#define REG_TWI1_IER  (*(WoReg*)0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */
+#define REG_TWI1_IDR  (*(WoReg*)0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */
+#define REG_TWI1_IMR  (*(RoReg*)0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */
+#define REG_TWI1_RHR  (*(RoReg*)0x4001C030U) /**< \brief (TWI1) Receive Holding Register */
+#define REG_TWI1_THR  (*(WoReg*)0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */
+#define REG_TWI1_RPR  (*(RwReg*)0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */
+#define REG_TWI1_RCR  (*(RwReg*)0x4001C104U) /**< \brief (TWI1) Receive Counter Register */
+#define REG_TWI1_TPR  (*(RwReg*)0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */
+#define REG_TWI1_TCR  (*(RwReg*)0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */
+#define REG_TWI1_RNPR (*(RwReg*)0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */
+#define REG_TWI1_RNCR (*(RwReg*)0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */
+#define REG_TWI1_TNPR (*(RwReg*)0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */
+#define REG_TWI1_TNCR (*(RwReg*)0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */
+#define REG_TWI1_PTCR (*(WoReg*)0x4001C120U) /**< \brief (TWI1) Transfer Control Register */
+#define REG_TWI1_PTSR (*(RoReg*)0x4001C124U) /**< \brief (TWI1) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_TWI1_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_uart0.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_uart0.h
new file mode 100644
index 000000000..09ada8544
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_uart0.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_UART0_INSTANCE_
+#define _SAM3S8_UART0_INSTANCE_
+
+/* ========== Register definition for UART0 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_UART0_CR            (0x400E0600U) /**< \brief (UART0) Control Register */
+#define REG_UART0_MR            (0x400E0604U) /**< \brief (UART0) Mode Register */
+#define REG_UART0_IER           (0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */
+#define REG_UART0_IDR           (0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */
+#define REG_UART0_IMR           (0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */
+#define REG_UART0_SR            (0x400E0614U) /**< \brief (UART0) Status Register */
+#define REG_UART0_RHR           (0x400E0618U) /**< \brief (UART0) Receive Holding Register */
+#define REG_UART0_THR           (0x400E061CU) /**< \brief (UART0) Transmit Holding Register */
+#define REG_UART0_BRGR          (0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */
+#define REG_UART0_RPR           (0x400E0700U) /**< \brief (UART0) Receive Pointer Register */
+#define REG_UART0_RCR           (0x400E0704U) /**< \brief (UART0) Receive Counter Register */
+#define REG_UART0_TPR           (0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */
+#define REG_UART0_TCR           (0x400E070CU) /**< \brief (UART0) Transmit Counter Register */
+#define REG_UART0_RNPR          (0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */
+#define REG_UART0_RNCR          (0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */
+#define REG_UART0_TNPR          (0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */
+#define REG_UART0_TNCR          (0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */
+#define REG_UART0_PTCR          (0x400E0720U) /**< \brief (UART0) Transfer Control Register */
+#define REG_UART0_PTSR          (0x400E0724U) /**< \brief (UART0) Transfer Status Register */
+#else
+#define REG_UART0_CR   (*(WoReg*)0x400E0600U) /**< \brief (UART0) Control Register */
+#define REG_UART0_MR   (*(RwReg*)0x400E0604U) /**< \brief (UART0) Mode Register */
+#define REG_UART0_IER  (*(WoReg*)0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */
+#define REG_UART0_IDR  (*(WoReg*)0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */
+#define REG_UART0_IMR  (*(RoReg*)0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */
+#define REG_UART0_SR   (*(RoReg*)0x400E0614U) /**< \brief (UART0) Status Register */
+#define REG_UART0_RHR  (*(RoReg*)0x400E0618U) /**< \brief (UART0) Receive Holding Register */
+#define REG_UART0_THR  (*(WoReg*)0x400E061CU) /**< \brief (UART0) Transmit Holding Register */
+#define REG_UART0_BRGR (*(RwReg*)0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */
+#define REG_UART0_RPR  (*(RwReg*)0x400E0700U) /**< \brief (UART0) Receive Pointer Register */
+#define REG_UART0_RCR  (*(RwReg*)0x400E0704U) /**< \brief (UART0) Receive Counter Register */
+#define REG_UART0_TPR  (*(RwReg*)0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */
+#define REG_UART0_TCR  (*(RwReg*)0x400E070CU) /**< \brief (UART0) Transmit Counter Register */
+#define REG_UART0_RNPR (*(RwReg*)0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */
+#define REG_UART0_RNCR (*(RwReg*)0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */
+#define REG_UART0_TNPR (*(RwReg*)0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */
+#define REG_UART0_TNCR (*(RwReg*)0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */
+#define REG_UART0_PTCR (*(WoReg*)0x400E0720U) /**< \brief (UART0) Transfer Control Register */
+#define REG_UART0_PTSR (*(RoReg*)0x400E0724U) /**< \brief (UART0) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_UART0_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_uart1.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_uart1.h
new file mode 100644
index 000000000..d8d328665
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_uart1.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_UART1_INSTANCE_
+#define _SAM3S8_UART1_INSTANCE_
+
+/* ========== Register definition for UART1 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_UART1_CR            (0x400E0800U) /**< \brief (UART1) Control Register */
+#define REG_UART1_MR            (0x400E0804U) /**< \brief (UART1) Mode Register */
+#define REG_UART1_IER           (0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */
+#define REG_UART1_IDR           (0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */
+#define REG_UART1_IMR           (0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */
+#define REG_UART1_SR            (0x400E0814U) /**< \brief (UART1) Status Register */
+#define REG_UART1_RHR           (0x400E0818U) /**< \brief (UART1) Receive Holding Register */
+#define REG_UART1_THR           (0x400E081CU) /**< \brief (UART1) Transmit Holding Register */
+#define REG_UART1_BRGR          (0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */
+#define REG_UART1_RPR           (0x400E0900U) /**< \brief (UART1) Receive Pointer Register */
+#define REG_UART1_RCR           (0x400E0904U) /**< \brief (UART1) Receive Counter Register */
+#define REG_UART1_TPR           (0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */
+#define REG_UART1_TCR           (0x400E090CU) /**< \brief (UART1) Transmit Counter Register */
+#define REG_UART1_RNPR          (0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */
+#define REG_UART1_RNCR          (0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */
+#define REG_UART1_TNPR          (0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */
+#define REG_UART1_TNCR          (0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */
+#define REG_UART1_PTCR          (0x400E0920U) /**< \brief (UART1) Transfer Control Register */
+#define REG_UART1_PTSR          (0x400E0924U) /**< \brief (UART1) Transfer Status Register */
+#else
+#define REG_UART1_CR   (*(WoReg*)0x400E0800U) /**< \brief (UART1) Control Register */
+#define REG_UART1_MR   (*(RwReg*)0x400E0804U) /**< \brief (UART1) Mode Register */
+#define REG_UART1_IER  (*(WoReg*)0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */
+#define REG_UART1_IDR  (*(WoReg*)0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */
+#define REG_UART1_IMR  (*(RoReg*)0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */
+#define REG_UART1_SR   (*(RoReg*)0x400E0814U) /**< \brief (UART1) Status Register */
+#define REG_UART1_RHR  (*(RoReg*)0x400E0818U) /**< \brief (UART1) Receive Holding Register */
+#define REG_UART1_THR  (*(WoReg*)0x400E081CU) /**< \brief (UART1) Transmit Holding Register */
+#define REG_UART1_BRGR (*(RwReg*)0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */
+#define REG_UART1_RPR  (*(RwReg*)0x400E0900U) /**< \brief (UART1) Receive Pointer Register */
+#define REG_UART1_RCR  (*(RwReg*)0x400E0904U) /**< \brief (UART1) Receive Counter Register */
+#define REG_UART1_TPR  (*(RwReg*)0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */
+#define REG_UART1_TCR  (*(RwReg*)0x400E090CU) /**< \brief (UART1) Transmit Counter Register */
+#define REG_UART1_RNPR (*(RwReg*)0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */
+#define REG_UART1_RNCR (*(RwReg*)0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */
+#define REG_UART1_TNPR (*(RwReg*)0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */
+#define REG_UART1_TNCR (*(RwReg*)0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */
+#define REG_UART1_PTCR (*(WoReg*)0x400E0920U) /**< \brief (UART1) Transfer Control Register */
+#define REG_UART1_PTSR (*(RoReg*)0x400E0924U) /**< \brief (UART1) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_UART1_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_udp.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_udp.h
new file mode 100644
index 000000000..ff4ada3dc
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_udp.h
@@ -0,0 +1,62 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_UDP_INSTANCE_
+#define _SAM3S8_UDP_INSTANCE_
+
+/* ========== Register definition for UDP peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_UDP_FRM_NUM           (0x40034000U) /**< \brief (UDP) Frame Number Register */
+#define REG_UDP_GLB_STAT          (0x40034004U) /**< \brief (UDP) Global State Register */
+#define REG_UDP_FADDR             (0x40034008U) /**< \brief (UDP) Function Address Register */
+#define REG_UDP_IER               (0x40034010U) /**< \brief (UDP) Interrupt Enable Register */
+#define REG_UDP_IDR               (0x40034014U) /**< \brief (UDP) Interrupt Disable Register */
+#define REG_UDP_IMR               (0x40034018U) /**< \brief (UDP) Interrupt Mask Register */
+#define REG_UDP_ISR               (0x4003401CU) /**< \brief (UDP) Interrupt Status Register */
+#define REG_UDP_ICR               (0x40034020U) /**< \brief (UDP) Interrupt Clear Register */
+#define REG_UDP_RST_EP            (0x40034028U) /**< \brief (UDP) Reset Endpoint Register */
+#define REG_UDP_CSR               (0x40034030U) /**< \brief (UDP) Endpoint Control and Status Register */
+#define REG_UDP_FDR               (0x40034050U) /**< \brief (UDP) Endpoint FIFO Data Register */
+#define REG_UDP_TXVC              (0x40034074U) /**< \brief (UDP) Transceiver Control Register */
+#else
+#define REG_UDP_FRM_NUM  (*(RoReg*)0x40034000U) /**< \brief (UDP) Frame Number Register */
+#define REG_UDP_GLB_STAT (*(RwReg*)0x40034004U) /**< \brief (UDP) Global State Register */
+#define REG_UDP_FADDR    (*(RwReg*)0x40034008U) /**< \brief (UDP) Function Address Register */
+#define REG_UDP_IER      (*(WoReg*)0x40034010U) /**< \brief (UDP) Interrupt Enable Register */
+#define REG_UDP_IDR      (*(WoReg*)0x40034014U) /**< \brief (UDP) Interrupt Disable Register */
+#define REG_UDP_IMR      (*(RoReg*)0x40034018U) /**< \brief (UDP) Interrupt Mask Register */
+#define REG_UDP_ISR      (*(RoReg*)0x4003401CU) /**< \brief (UDP) Interrupt Status Register */
+#define REG_UDP_ICR      (*(WoReg*)0x40034020U) /**< \brief (UDP) Interrupt Clear Register */
+#define REG_UDP_RST_EP   (*(RwReg*)0x40034028U) /**< \brief (UDP) Reset Endpoint Register */
+#define REG_UDP_CSR      (*(RwReg*)0x40034030U) /**< \brief (UDP) Endpoint Control and Status Register */
+#define REG_UDP_FDR      (*(RwReg*)0x40034050U) /**< \brief (UDP) Endpoint FIFO Data Register */
+#define REG_UDP_TXVC     (*(RwReg*)0x40034074U) /**< \brief (UDP) Transceiver Control Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_UDP_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_usart0.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_usart0.h
new file mode 100644
index 000000000..04ee15c8e
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_usart0.h
@@ -0,0 +1,94 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_USART0_INSTANCE_
+#define _SAM3S8_USART0_INSTANCE_
+
+/* ========== Register definition for USART0 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_USART0_CR            (0x40024000U) /**< \brief (USART0) Control Register */
+#define REG_USART0_MR            (0x40024004U) /**< \brief (USART0) Mode Register */
+#define REG_USART0_IER           (0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
+#define REG_USART0_IDR           (0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
+#define REG_USART0_IMR           (0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
+#define REG_USART0_CSR           (0x40024014U) /**< \brief (USART0) Channel Status Register */
+#define REG_USART0_RHR           (0x40024018U) /**< \brief (USART0) Receiver Holding Register */
+#define REG_USART0_THR           (0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */
+#define REG_USART0_BRGR          (0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
+#define REG_USART0_RTOR          (0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
+#define REG_USART0_TTGR          (0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
+#define REG_USART0_FIDI          (0x40024040U) /**< \brief (USART0) FI DI Ratio Register */
+#define REG_USART0_NER           (0x40024044U) /**< \brief (USART0) Number of Errors Register */
+#define REG_USART0_IF            (0x4002404CU) /**< \brief (USART0) IrDA Filter Register */
+#define REG_USART0_MAN           (0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
+#define REG_USART0_WPMR          (0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */
+#define REG_USART0_WPSR          (0x400240E8U) /**< \brief (USART0) Write Protect Status Register */
+#define REG_USART0_VERSION          (0x400240FCU) /**< \brief (USART0) Version Register */
+#define REG_USART0_RPR           (0x40024100U) /**< \brief (USART0) Receive Pointer Register */
+#define REG_USART0_RCR           (0x40024104U) /**< \brief (USART0) Receive Counter Register */
+#define REG_USART0_TPR           (0x40024108U) /**< \brief (USART0) Transmit Pointer Register */
+#define REG_USART0_TCR           (0x4002410CU) /**< \brief (USART0) Transmit Counter Register */
+#define REG_USART0_RNPR          (0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */
+#define REG_USART0_RNCR          (0x40024114U) /**< \brief (USART0) Receive Next Counter Register */
+#define REG_USART0_TNPR          (0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */
+#define REG_USART0_TNCR          (0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */
+#define REG_USART0_PTCR          (0x40024120U) /**< \brief (USART0) Transfer Control Register */
+#define REG_USART0_PTSR          (0x40024124U) /**< \brief (USART0) Transfer Status Register */
+#else
+#define REG_USART0_CR   (*(WoReg*)0x40024000U) /**< \brief (USART0) Control Register */
+#define REG_USART0_MR   (*(RwReg*)0x40024004U) /**< \brief (USART0) Mode Register */
+#define REG_USART0_IER  (*(WoReg*)0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
+#define REG_USART0_IDR  (*(WoReg*)0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
+#define REG_USART0_IMR  (*(RoReg*)0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
+#define REG_USART0_CSR  (*(RoReg*)0x40024014U) /**< \brief (USART0) Channel Status Register */
+#define REG_USART0_RHR  (*(RoReg*)0x40024018U) /**< \brief (USART0) Receiver Holding Register */
+#define REG_USART0_THR  (*(WoReg*)0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */
+#define REG_USART0_BRGR (*(RwReg*)0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
+#define REG_USART0_RTOR (*(RwReg*)0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
+#define REG_USART0_TTGR (*(RwReg*)0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
+#define REG_USART0_FIDI (*(RwReg*)0x40024040U) /**< \brief (USART0) FI DI Ratio Register */
+#define REG_USART0_NER  (*(RoReg*)0x40024044U) /**< \brief (USART0) Number of Errors Register */
+#define REG_USART0_IF   (*(RwReg*)0x4002404CU) /**< \brief (USART0) IrDA Filter Register */
+#define REG_USART0_MAN  (*(RwReg*)0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
+#define REG_USART0_WPMR (*(RwReg*)0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */
+#define REG_USART0_WPSR (*(RoReg*)0x400240E8U) /**< \brief (USART0) Write Protect Status Register */
+#define REG_USART0_VERSION (*(RoReg*)0x400240FCU) /**< \brief (USART0) Version Register */
+#define REG_USART0_RPR  (*(RwReg*)0x40024100U) /**< \brief (USART0) Receive Pointer Register */
+#define REG_USART0_RCR  (*(RwReg*)0x40024104U) /**< \brief (USART0) Receive Counter Register */
+#define REG_USART0_TPR  (*(RwReg*)0x40024108U) /**< \brief (USART0) Transmit Pointer Register */
+#define REG_USART0_TCR  (*(RwReg*)0x4002410CU) /**< \brief (USART0) Transmit Counter Register */
+#define REG_USART0_RNPR (*(RwReg*)0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */
+#define REG_USART0_RNCR (*(RwReg*)0x40024114U) /**< \brief (USART0) Receive Next Counter Register */
+#define REG_USART0_TNPR (*(RwReg*)0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */
+#define REG_USART0_TNCR (*(RwReg*)0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */
+#define REG_USART0_PTCR (*(WoReg*)0x40024120U) /**< \brief (USART0) Transfer Control Register */
+#define REG_USART0_PTSR (*(RoReg*)0x40024124U) /**< \brief (USART0) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_USART0_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_usart1.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_usart1.h
new file mode 100644
index 000000000..1d83320ba
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_usart1.h
@@ -0,0 +1,94 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_USART1_INSTANCE_
+#define _SAM3S8_USART1_INSTANCE_
+
+/* ========== Register definition for USART1 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_USART1_CR            (0x40028000U) /**< \brief (USART1) Control Register */
+#define REG_USART1_MR            (0x40028004U) /**< \brief (USART1) Mode Register */
+#define REG_USART1_IER           (0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
+#define REG_USART1_IDR           (0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
+#define REG_USART1_IMR           (0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
+#define REG_USART1_CSR           (0x40028014U) /**< \brief (USART1) Channel Status Register */
+#define REG_USART1_RHR           (0x40028018U) /**< \brief (USART1) Receiver Holding Register */
+#define REG_USART1_THR           (0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */
+#define REG_USART1_BRGR          (0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
+#define REG_USART1_RTOR          (0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
+#define REG_USART1_TTGR          (0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
+#define REG_USART1_FIDI          (0x40028040U) /**< \brief (USART1) FI DI Ratio Register */
+#define REG_USART1_NER           (0x40028044U) /**< \brief (USART1) Number of Errors Register */
+#define REG_USART1_IF            (0x4002804CU) /**< \brief (USART1) IrDA Filter Register */
+#define REG_USART1_MAN           (0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
+#define REG_USART1_WPMR          (0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */
+#define REG_USART1_WPSR          (0x400280E8U) /**< \brief (USART1) Write Protect Status Register */
+#define REG_USART1_VERSION          (0x400280FCU) /**< \brief (USART1) Version Register */
+#define REG_USART1_RPR           (0x40028100U) /**< \brief (USART1) Receive Pointer Register */
+#define REG_USART1_RCR           (0x40028104U) /**< \brief (USART1) Receive Counter Register */
+#define REG_USART1_TPR           (0x40028108U) /**< \brief (USART1) Transmit Pointer Register */
+#define REG_USART1_TCR           (0x4002810CU) /**< \brief (USART1) Transmit Counter Register */
+#define REG_USART1_RNPR          (0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */
+#define REG_USART1_RNCR          (0x40028114U) /**< \brief (USART1) Receive Next Counter Register */
+#define REG_USART1_TNPR          (0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */
+#define REG_USART1_TNCR          (0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */
+#define REG_USART1_PTCR          (0x40028120U) /**< \brief (USART1) Transfer Control Register */
+#define REG_USART1_PTSR          (0x40028124U) /**< \brief (USART1) Transfer Status Register */
+#else
+#define REG_USART1_CR   (*(WoReg*)0x40028000U) /**< \brief (USART1) Control Register */
+#define REG_USART1_MR   (*(RwReg*)0x40028004U) /**< \brief (USART1) Mode Register */
+#define REG_USART1_IER  (*(WoReg*)0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
+#define REG_USART1_IDR  (*(WoReg*)0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
+#define REG_USART1_IMR  (*(RoReg*)0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
+#define REG_USART1_CSR  (*(RoReg*)0x40028014U) /**< \brief (USART1) Channel Status Register */
+#define REG_USART1_RHR  (*(RoReg*)0x40028018U) /**< \brief (USART1) Receiver Holding Register */
+#define REG_USART1_THR  (*(WoReg*)0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */
+#define REG_USART1_BRGR (*(RwReg*)0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
+#define REG_USART1_RTOR (*(RwReg*)0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
+#define REG_USART1_TTGR (*(RwReg*)0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
+#define REG_USART1_FIDI (*(RwReg*)0x40028040U) /**< \brief (USART1) FI DI Ratio Register */
+#define REG_USART1_NER  (*(RoReg*)0x40028044U) /**< \brief (USART1) Number of Errors Register */
+#define REG_USART1_IF   (*(RwReg*)0x4002804CU) /**< \brief (USART1) IrDA Filter Register */
+#define REG_USART1_MAN  (*(RwReg*)0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
+#define REG_USART1_WPMR (*(RwReg*)0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */
+#define REG_USART1_WPSR (*(RoReg*)0x400280E8U) /**< \brief (USART1) Write Protect Status Register */
+#define REG_USART1_VERSION (*(RoReg*)0x400280FCU) /**< \brief (USART1) Version Register */
+#define REG_USART1_RPR  (*(RwReg*)0x40028100U) /**< \brief (USART1) Receive Pointer Register */
+#define REG_USART1_RCR  (*(RwReg*)0x40028104U) /**< \brief (USART1) Receive Counter Register */
+#define REG_USART1_TPR  (*(RwReg*)0x40028108U) /**< \brief (USART1) Transmit Pointer Register */
+#define REG_USART1_TCR  (*(RwReg*)0x4002810CU) /**< \brief (USART1) Transmit Counter Register */
+#define REG_USART1_RNPR (*(RwReg*)0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */
+#define REG_USART1_RNCR (*(RwReg*)0x40028114U) /**< \brief (USART1) Receive Next Counter Register */
+#define REG_USART1_TNPR (*(RwReg*)0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */
+#define REG_USART1_TNCR (*(RwReg*)0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */
+#define REG_USART1_PTCR (*(WoReg*)0x40028120U) /**< \brief (USART1) Transfer Control Register */
+#define REG_USART1_PTSR (*(RoReg*)0x40028124U) /**< \brief (USART1) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_USART1_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_usart2.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_usart2.h
new file mode 100644
index 000000000..cc909ce68
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_usart2.h
@@ -0,0 +1,94 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_USART2_INSTANCE_
+#define _SAM3S8_USART2_INSTANCE_
+
+/* ========== Register definition for USART2 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_USART2_CR            (0x4002C000U) /**< \brief (USART2) Control Register */
+#define REG_USART2_MR            (0x4002C004U) /**< \brief (USART2) Mode Register */
+#define REG_USART2_IER           (0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */
+#define REG_USART2_IDR           (0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */
+#define REG_USART2_IMR           (0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */
+#define REG_USART2_CSR           (0x4002C014U) /**< \brief (USART2) Channel Status Register */
+#define REG_USART2_RHR           (0x4002C018U) /**< \brief (USART2) Receiver Holding Register */
+#define REG_USART2_THR           (0x4002C01CU) /**< \brief (USART2) Transmitter Holding Register */
+#define REG_USART2_BRGR          (0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */
+#define REG_USART2_RTOR          (0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */
+#define REG_USART2_TTGR          (0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */
+#define REG_USART2_FIDI          (0x4002C040U) /**< \brief (USART2) FI DI Ratio Register */
+#define REG_USART2_NER           (0x4002C044U) /**< \brief (USART2) Number of Errors Register */
+#define REG_USART2_IF            (0x4002C04CU) /**< \brief (USART2) IrDA Filter Register */
+#define REG_USART2_MAN           (0x4002C050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
+#define REG_USART2_WPMR          (0x4002C0E4U) /**< \brief (USART2) Write Protect Mode Register */
+#define REG_USART2_WPSR          (0x4002C0E8U) /**< \brief (USART2) Write Protect Status Register */
+#define REG_USART2_VERSION          (0x4002C0FCU) /**< \brief (USART2) Version Register */
+#define REG_USART2_RPR           (0x4002C100U) /**< \brief (USART2) Receive Pointer Register */
+#define REG_USART2_RCR           (0x4002C104U) /**< \brief (USART2) Receive Counter Register */
+#define REG_USART2_TPR           (0x4002C108U) /**< \brief (USART2) Transmit Pointer Register */
+#define REG_USART2_TCR           (0x4002C10CU) /**< \brief (USART2) Transmit Counter Register */
+#define REG_USART2_RNPR          (0x4002C110U) /**< \brief (USART2) Receive Next Pointer Register */
+#define REG_USART2_RNCR          (0x4002C114U) /**< \brief (USART2) Receive Next Counter Register */
+#define REG_USART2_TNPR          (0x4002C118U) /**< \brief (USART2) Transmit Next Pointer Register */
+#define REG_USART2_TNCR          (0x4002C11CU) /**< \brief (USART2) Transmit Next Counter Register */
+#define REG_USART2_PTCR          (0x4002C120U) /**< \brief (USART2) Transfer Control Register */
+#define REG_USART2_PTSR          (0x4002C124U) /**< \brief (USART2) Transfer Status Register */
+#else
+#define REG_USART2_CR   (*(WoReg*)0x4002C000U) /**< \brief (USART2) Control Register */
+#define REG_USART2_MR   (*(RwReg*)0x4002C004U) /**< \brief (USART2) Mode Register */
+#define REG_USART2_IER  (*(WoReg*)0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */
+#define REG_USART2_IDR  (*(WoReg*)0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */
+#define REG_USART2_IMR  (*(RoReg*)0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */
+#define REG_USART2_CSR  (*(RoReg*)0x4002C014U) /**< \brief (USART2) Channel Status Register */
+#define REG_USART2_RHR  (*(RoReg*)0x4002C018U) /**< \brief (USART2) Receiver Holding Register */
+#define REG_USART2_THR  (*(WoReg*)0x4002C01CU) /**< \brief (USART2) Transmitter Holding Register */
+#define REG_USART2_BRGR (*(RwReg*)0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */
+#define REG_USART2_RTOR (*(RwReg*)0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */
+#define REG_USART2_TTGR (*(RwReg*)0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */
+#define REG_USART2_FIDI (*(RwReg*)0x4002C040U) /**< \brief (USART2) FI DI Ratio Register */
+#define REG_USART2_NER  (*(RoReg*)0x4002C044U) /**< \brief (USART2) Number of Errors Register */
+#define REG_USART2_IF   (*(RwReg*)0x4002C04CU) /**< \brief (USART2) IrDA Filter Register */
+#define REG_USART2_MAN  (*(RwReg*)0x4002C050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
+#define REG_USART2_WPMR (*(RwReg*)0x4002C0E4U) /**< \brief (USART2) Write Protect Mode Register */
+#define REG_USART2_WPSR (*(RoReg*)0x4002C0E8U) /**< \brief (USART2) Write Protect Status Register */
+#define REG_USART2_VERSION (*(RoReg*)0x4002C0FCU) /**< \brief (USART2) Version Register */
+#define REG_USART2_RPR  (*(RwReg*)0x4002C100U) /**< \brief (USART2) Receive Pointer Register */
+#define REG_USART2_RCR  (*(RwReg*)0x4002C104U) /**< \brief (USART2) Receive Counter Register */
+#define REG_USART2_TPR  (*(RwReg*)0x4002C108U) /**< \brief (USART2) Transmit Pointer Register */
+#define REG_USART2_TCR  (*(RwReg*)0x4002C10CU) /**< \brief (USART2) Transmit Counter Register */
+#define REG_USART2_RNPR (*(RwReg*)0x4002C110U) /**< \brief (USART2) Receive Next Pointer Register */
+#define REG_USART2_RNCR (*(RwReg*)0x4002C114U) /**< \brief (USART2) Receive Next Counter Register */
+#define REG_USART2_TNPR (*(RwReg*)0x4002C118U) /**< \brief (USART2) Transmit Next Pointer Register */
+#define REG_USART2_TNCR (*(RwReg*)0x4002C11CU) /**< \brief (USART2) Transmit Next Counter Register */
+#define REG_USART2_PTCR (*(WoReg*)0x4002C120U) /**< \brief (USART2) Transfer Control Register */
+#define REG_USART2_PTSR (*(RoReg*)0x4002C124U) /**< \brief (USART2) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_USART2_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_wdt.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_wdt.h
new file mode 100644
index 000000000..6d89ffbb3
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/instance/instance_wdt.h
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_WDT_INSTANCE_
+#define _SAM3S8_WDT_INSTANCE_
+
+/* ========== Register definition for WDT peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_WDT_CR          (0x400E1450U) /**< \brief (WDT) Control Register */
+#define REG_WDT_MR          (0x400E1454U) /**< \brief (WDT) Mode Register */
+#define REG_WDT_SR          (0x400E1458U) /**< \brief (WDT) Status Register */
+#else
+#define REG_WDT_CR (*(WoReg*)0x400E1450U) /**< \brief (WDT) Control Register */
+#define REG_WDT_MR (*(RwReg*)0x400E1454U) /**< \brief (WDT) Mode Register */
+#define REG_WDT_SR (*(RoReg*)0x400E1458U) /**< \brief (WDT) Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3S8_WDT_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/pio/pio_sam3s8a.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/pio/pio_sam3s8a.h
new file mode 100644
index 000000000..26850a101
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/pio/pio_sam3s8a.h
@@ -0,0 +1,236 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8A_PIO_
+#define _SAM3S8A_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB0X1_RTCOUT0  (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB1X1_RTCOUT1  (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0    (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PB14X1_DAC1    (1u << 14) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA2C_DATRG     (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+
+#endif /* _SAM3S8A_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/pio/pio_sam3s8b.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/pio/pio_sam3s8b.h
new file mode 100644
index 000000000..9f942a976
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/pio/pio_sam3s8b.h
@@ -0,0 +1,279 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8B_PIO_
+#define _SAM3S8B_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21           (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22           (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23           (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24           (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25           (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26           (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27           (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28           (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29           (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30           (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31           (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13           (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14           (1u << 14) /**< \brief Pin Controlled by PB14 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB0X1_RTCOUT0  (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB1X1_RTCOUT1  (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0    (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PB14X1_DAC1    (1u << 14) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA2C_DATRG     (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA28C_MCCDA    (1u << 28) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA29C_MCCK     (1u << 29) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA30C_MCDA0    (1u << 30) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA31C_MCDA1    (1u << 31) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA26C_MCDA2    (1u << 26) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA27C_MCDA3    (1u << 27) /**< \brief Hsmci signal: MCDA3 */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1     (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA26A_DCD1     (1u << 26) /**< \brief Usart1 signal: DCD1 */
+#define PIO_PA28A_DSR1     (1u << 28) /**< \brief Usart1 signal: DSR1 */
+#define PIO_PA27A_DTR1     (1u << 27) /**< \brief Usart1 signal: DTR1 */
+#define PIO_PA29A_RI1      (1u << 29) /**< \brief Usart1 signal: RI1 */
+#define PIO_PA24A_RTS1     (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1     (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1     (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1     (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PA21_IDX       21
+#define PIO_PA22_IDX       22
+#define PIO_PA23_IDX       23
+#define PIO_PA24_IDX       24
+#define PIO_PA25_IDX       25
+#define PIO_PA26_IDX       26
+#define PIO_PA27_IDX       27
+#define PIO_PA28_IDX       28
+#define PIO_PA29_IDX       29
+#define PIO_PA30_IDX       30
+#define PIO_PA31_IDX       31
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+#define PIO_PB13_IDX       45
+#define PIO_PB14_IDX       46
+
+#endif /* _SAM3S8B_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/pio/pio_sam3s8c.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/pio/pio_sam3s8c.h
new file mode 100644
index 000000000..0d8a5ab44
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/pio/pio_sam3s8c.h
@@ -0,0 +1,403 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8C_PIO_
+#define _SAM3S8C_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21           (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22           (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23           (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24           (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25           (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26           (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27           (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28           (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29           (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30           (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31           (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13           (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14           (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PC0            (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1            (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2            (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3            (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4            (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5            (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6            (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7            (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8            (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9            (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10           (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11           (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12           (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13           (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14           (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15           (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16           (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17           (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18           (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19           (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20           (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21           (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22           (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23           (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24           (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25           (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26           (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27           (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28           (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29           (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30           (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31           (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB0X1_RTCOUT0  (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB1X1_RTCOUT1  (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0    (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PB14X1_DAC1    (1u << 14) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA2C_DATRG     (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PC18A_A0       (1u << 18) /**< \brief Ebi signal: A0 */
+#define PIO_PC19A_A1       (1u << 19) /**< \brief Ebi signal: A1 */
+#define PIO_PC28A_A10      (1u << 28) /**< \brief Ebi signal: A10 */
+#define PIO_PC29A_A11      (1u << 29) /**< \brief Ebi signal: A11 */
+#define PIO_PC30A_A12      (1u << 30) /**< \brief Ebi signal: A12 */
+#define PIO_PC31A_A13      (1u << 31) /**< \brief Ebi signal: A13 */
+#define PIO_PA18C_A14      (1u << 18) /**< \brief Ebi signal: A14 */
+#define PIO_PA19C_A15      (1u << 19) /**< \brief Ebi signal: A15 */
+#define PIO_PA20C_A16      (1u << 20) /**< \brief Ebi signal: A16 */
+#define PIO_PA0C_A17       (1u << 0)  /**< \brief Ebi signal: A17 */
+#define PIO_PA1C_A18       (1u << 1)  /**< \brief Ebi signal: A18 */
+#define PIO_PA23C_A19      (1u << 23) /**< \brief Ebi signal: A19 */
+#define PIO_PC20A_A2       (1u << 20) /**< \brief Ebi signal: A2 */
+#define PIO_PA24C_A20      (1u << 24) /**< \brief Ebi signal: A20 */
+#define PIO_PC16A_A21      (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PC16A_NANDALE  (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PC17A_A22      (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PC17A_NANDCLE  (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PA25C_A23      (1u << 25) /**< \brief Ebi signal: A23 */
+#define PIO_PC21A_A3       (1u << 21) /**< \brief Ebi signal: A3 */
+#define PIO_PC22A_A4       (1u << 22) /**< \brief Ebi signal: A4 */
+#define PIO_PC23A_A5       (1u << 23) /**< \brief Ebi signal: A5 */
+#define PIO_PC24A_A6       (1u << 24) /**< \brief Ebi signal: A6 */
+#define PIO_PC25A_A7       (1u << 25) /**< \brief Ebi signal: A7 */
+#define PIO_PC26A_A8       (1u << 26) /**< \brief Ebi signal: A8 */
+#define PIO_PC27A_A9       (1u << 27) /**< \brief Ebi signal: A9 */
+#define PIO_PC0A_D0        (1u << 0)  /**< \brief Ebi signal: D0 */
+#define PIO_PC1A_D1        (1u << 1)  /**< \brief Ebi signal: D1 */
+#define PIO_PC2A_D2        (1u << 2)  /**< \brief Ebi signal: D2 */
+#define PIO_PC3A_D3        (1u << 3)  /**< \brief Ebi signal: D3 */
+#define PIO_PC4A_D4        (1u << 4)  /**< \brief Ebi signal: D4 */
+#define PIO_PC5A_D5        (1u << 5)  /**< \brief Ebi signal: D5 */
+#define PIO_PC6A_D6        (1u << 6)  /**< \brief Ebi signal: D6 */
+#define PIO_PC7A_D7        (1u << 7)  /**< \brief Ebi signal: D7 */
+#define PIO_PC9A_NANDOE    (1u << 9)  /**< \brief Ebi signal: NANDOE */
+#define PIO_PC10A_NANDWE   (1u << 10) /**< \brief Ebi signal: NANDWE */
+#define PIO_PC14A_NCS0     (1u << 14) /**< \brief Ebi signal: NCS0 */
+#define PIO_PC15A_NCS1     (1u << 15) /**< \brief Ebi signal: NCS1 */
+#define PIO_PA22C_NCS2     (1u << 22) /**< \brief Ebi signal: NCS2 */
+#define PIO_PC12A_NCS3     (1u << 12) /**< \brief Ebi signal: NCS3 */
+#define PIO_PC11A_NRD      (1u << 11) /**< \brief Ebi signal: NRD */
+#define PIO_PC13A_NWAIT    (1u << 13) /**< \brief Ebi signal: NWAIT */
+#define PIO_PC8A_NWE       (1u << 8)  /**< \brief Ebi signal: NWE */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA28C_MCCDA    (1u << 28) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA29C_MCCK     (1u << 29) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA30C_MCDA0    (1u << 30) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA31C_MCDA1    (1u << 31) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA26C_MCDA2    (1u << 26) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA27C_MCDA3    (1u << 27) /**< \brief Hsmci signal: MCDA3 */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PC25B_TCLK3    (1u << 25) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PC28B_TCLK4    (1u << 28) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PC31B_TCLK5    (1u << 31) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PC23B_TIOA3    (1u << 23) /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PC26B_TIOA4    (1u << 26) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PC29B_TIOA5    (1u << 29) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PC24B_TIOB3    (1u << 24) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PC27B_TIOB4    (1u << 27) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PC30B_TIOB5    (1u << 30) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1     (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA26A_DCD1     (1u << 26) /**< \brief Usart1 signal: DCD1 */
+#define PIO_PA28A_DSR1     (1u << 28) /**< \brief Usart1 signal: DSR1 */
+#define PIO_PA27A_DTR1     (1u << 27) /**< \brief Usart1 signal: DTR1 */
+#define PIO_PA29A_RI1      (1u << 29) /**< \brief Usart1 signal: RI1 */
+#define PIO_PA24A_RTS1     (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1     (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1     (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1     (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PC17B_CTS2     (1u << 17) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PC16B_RTS2     (1u << 16) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PC9B_RXD2      (1u << 9)  /**< \brief Usart2 signal: RXD2 */
+#define PIO_PC14B_SCK2     (1u << 14) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PC10B_TXD2     (1u << 10) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PA21_IDX       21
+#define PIO_PA22_IDX       22
+#define PIO_PA23_IDX       23
+#define PIO_PA24_IDX       24
+#define PIO_PA25_IDX       25
+#define PIO_PA26_IDX       26
+#define PIO_PA27_IDX       27
+#define PIO_PA28_IDX       28
+#define PIO_PA29_IDX       29
+#define PIO_PA30_IDX       30
+#define PIO_PA31_IDX       31
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+#define PIO_PB13_IDX       45
+#define PIO_PB14_IDX       46
+#define PIO_PC0_IDX        64
+#define PIO_PC1_IDX        65
+#define PIO_PC2_IDX        66
+#define PIO_PC3_IDX        67
+#define PIO_PC4_IDX        68
+#define PIO_PC5_IDX        69
+#define PIO_PC6_IDX        70
+#define PIO_PC7_IDX        71
+#define PIO_PC8_IDX        72
+#define PIO_PC9_IDX        73
+#define PIO_PC10_IDX       74
+#define PIO_PC11_IDX       75
+#define PIO_PC12_IDX       76
+#define PIO_PC13_IDX       77
+#define PIO_PC14_IDX       78
+#define PIO_PC15_IDX       79
+#define PIO_PC16_IDX       80
+#define PIO_PC17_IDX       81
+#define PIO_PC18_IDX       82
+#define PIO_PC19_IDX       83
+#define PIO_PC20_IDX       84
+#define PIO_PC21_IDX       85
+#define PIO_PC22_IDX       86
+#define PIO_PC23_IDX       87
+#define PIO_PC24_IDX       88
+#define PIO_PC25_IDX       89
+#define PIO_PC26_IDX       90
+#define PIO_PC27_IDX       91
+#define PIO_PC28_IDX       92
+#define PIO_PC29_IDX       93
+#define PIO_PC30_IDX       94
+#define PIO_PC31_IDX       95
+
+#endif /* _SAM3S8C_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/pio/pio_sam3sd8a.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/pio/pio_sam3sd8a.h
new file mode 100644
index 000000000..189f4c3dd
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/pio/pio_sam3sd8a.h
@@ -0,0 +1,236 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3SD8A_PIO_
+#define _SAM3SD8A_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB0X1_RTCOUT0  (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB1X1_RTCOUT1  (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0    (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PB14X1_DAC1    (1u << 14) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA2C_DATRG     (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+
+#endif /* _SAM3SD8A_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/pio/pio_sam3sd8b.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/pio/pio_sam3sd8b.h
new file mode 100644
index 000000000..37c7658c2
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/pio/pio_sam3sd8b.h
@@ -0,0 +1,279 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3SD8B_PIO_
+#define _SAM3SD8B_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21           (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22           (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23           (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24           (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25           (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26           (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27           (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28           (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29           (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30           (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31           (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13           (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14           (1u << 14) /**< \brief Pin Controlled by PB14 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB0X1_RTCOUT0  (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB1X1_RTCOUT1  (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0    (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PB14X1_DAC1    (1u << 14) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA2C_DATRG     (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA28C_MCCDA    (1u << 28) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA29C_MCCK     (1u << 29) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA30C_MCDA0    (1u << 30) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA31C_MCDA1    (1u << 31) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA26C_MCDA2    (1u << 26) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA27C_MCDA3    (1u << 27) /**< \brief Hsmci signal: MCDA3 */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1     (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA26A_DCD1     (1u << 26) /**< \brief Usart1 signal: DCD1 */
+#define PIO_PA28A_DSR1     (1u << 28) /**< \brief Usart1 signal: DSR1 */
+#define PIO_PA27A_DTR1     (1u << 27) /**< \brief Usart1 signal: DTR1 */
+#define PIO_PA29A_RI1      (1u << 29) /**< \brief Usart1 signal: RI1 */
+#define PIO_PA24A_RTS1     (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1     (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1     (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1     (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PA21_IDX       21
+#define PIO_PA22_IDX       22
+#define PIO_PA23_IDX       23
+#define PIO_PA24_IDX       24
+#define PIO_PA25_IDX       25
+#define PIO_PA26_IDX       26
+#define PIO_PA27_IDX       27
+#define PIO_PA28_IDX       28
+#define PIO_PA29_IDX       29
+#define PIO_PA30_IDX       30
+#define PIO_PA31_IDX       31
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+#define PIO_PB13_IDX       45
+#define PIO_PB14_IDX       46
+
+#endif /* _SAM3SD8B_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/pio/pio_sam3sd8c.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/pio/pio_sam3sd8c.h
new file mode 100644
index 000000000..8c186e14c
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/pio/pio_sam3sd8c.h
@@ -0,0 +1,403 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3SD8C_PIO_
+#define _SAM3SD8C_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21           (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22           (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23           (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24           (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25           (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26           (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27           (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28           (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29           (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30           (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31           (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13           (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14           (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PC0            (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1            (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2            (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3            (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4            (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5            (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6            (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7            (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8            (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9            (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10           (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11           (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12           (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13           (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14           (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15           (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16           (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17           (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18           (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19           (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20           (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21           (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22           (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23           (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24           (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25           (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26           (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27           (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28           (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29           (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30           (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31           (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB0X1_RTCOUT0  (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB1X1_RTCOUT1  (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0    (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PB14X1_DAC1    (1u << 14) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA2C_DATRG     (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PC18A_A0       (1u << 18) /**< \brief Ebi signal: A0 */
+#define PIO_PC19A_A1       (1u << 19) /**< \brief Ebi signal: A1 */
+#define PIO_PC28A_A10      (1u << 28) /**< \brief Ebi signal: A10 */
+#define PIO_PC29A_A11      (1u << 29) /**< \brief Ebi signal: A11 */
+#define PIO_PC30A_A12      (1u << 30) /**< \brief Ebi signal: A12 */
+#define PIO_PC31A_A13      (1u << 31) /**< \brief Ebi signal: A13 */
+#define PIO_PA18C_A14      (1u << 18) /**< \brief Ebi signal: A14 */
+#define PIO_PA19C_A15      (1u << 19) /**< \brief Ebi signal: A15 */
+#define PIO_PA20C_A16      (1u << 20) /**< \brief Ebi signal: A16 */
+#define PIO_PA0C_A17       (1u << 0)  /**< \brief Ebi signal: A17 */
+#define PIO_PA1C_A18       (1u << 1)  /**< \brief Ebi signal: A18 */
+#define PIO_PA23C_A19      (1u << 23) /**< \brief Ebi signal: A19 */
+#define PIO_PC20A_A2       (1u << 20) /**< \brief Ebi signal: A2 */
+#define PIO_PA24C_A20      (1u << 24) /**< \brief Ebi signal: A20 */
+#define PIO_PC16A_A21      (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PC16A_NANDALE  (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PC17A_A22      (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PC17A_NANDCLE  (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PA25C_A23      (1u << 25) /**< \brief Ebi signal: A23 */
+#define PIO_PC21A_A3       (1u << 21) /**< \brief Ebi signal: A3 */
+#define PIO_PC22A_A4       (1u << 22) /**< \brief Ebi signal: A4 */
+#define PIO_PC23A_A5       (1u << 23) /**< \brief Ebi signal: A5 */
+#define PIO_PC24A_A6       (1u << 24) /**< \brief Ebi signal: A6 */
+#define PIO_PC25A_A7       (1u << 25) /**< \brief Ebi signal: A7 */
+#define PIO_PC26A_A8       (1u << 26) /**< \brief Ebi signal: A8 */
+#define PIO_PC27A_A9       (1u << 27) /**< \brief Ebi signal: A9 */
+#define PIO_PC0A_D0        (1u << 0)  /**< \brief Ebi signal: D0 */
+#define PIO_PC1A_D1        (1u << 1)  /**< \brief Ebi signal: D1 */
+#define PIO_PC2A_D2        (1u << 2)  /**< \brief Ebi signal: D2 */
+#define PIO_PC3A_D3        (1u << 3)  /**< \brief Ebi signal: D3 */
+#define PIO_PC4A_D4        (1u << 4)  /**< \brief Ebi signal: D4 */
+#define PIO_PC5A_D5        (1u << 5)  /**< \brief Ebi signal: D5 */
+#define PIO_PC6A_D6        (1u << 6)  /**< \brief Ebi signal: D6 */
+#define PIO_PC7A_D7        (1u << 7)  /**< \brief Ebi signal: D7 */
+#define PIO_PC9A_NANDOE    (1u << 9)  /**< \brief Ebi signal: NANDOE */
+#define PIO_PC10A_NANDWE   (1u << 10) /**< \brief Ebi signal: NANDWE */
+#define PIO_PC14A_NCS0     (1u << 14) /**< \brief Ebi signal: NCS0 */
+#define PIO_PC15A_NCS1     (1u << 15) /**< \brief Ebi signal: NCS1 */
+#define PIO_PA22C_NCS2     (1u << 22) /**< \brief Ebi signal: NCS2 */
+#define PIO_PC12A_NCS3     (1u << 12) /**< \brief Ebi signal: NCS3 */
+#define PIO_PC11A_NRD      (1u << 11) /**< \brief Ebi signal: NRD */
+#define PIO_PC13A_NWAIT    (1u << 13) /**< \brief Ebi signal: NWAIT */
+#define PIO_PC8A_NWE       (1u << 8)  /**< \brief Ebi signal: NWE */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA28C_MCCDA    (1u << 28) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA29C_MCCK     (1u << 29) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA30C_MCDA0    (1u << 30) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA31C_MCDA1    (1u << 31) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA26C_MCDA2    (1u << 26) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA27C_MCDA3    (1u << 27) /**< \brief Hsmci signal: MCDA3 */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PC25B_TCLK3    (1u << 25) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PC28B_TCLK4    (1u << 28) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PC31B_TCLK5    (1u << 31) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PC23B_TIOA3    (1u << 23) /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PC26B_TIOA4    (1u << 26) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PC29B_TIOA5    (1u << 29) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PC24B_TIOB3    (1u << 24) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PC27B_TIOB4    (1u << 27) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PC30B_TIOB5    (1u << 30) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1     (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA26A_DCD1     (1u << 26) /**< \brief Usart1 signal: DCD1 */
+#define PIO_PA28A_DSR1     (1u << 28) /**< \brief Usart1 signal: DSR1 */
+#define PIO_PA27A_DTR1     (1u << 27) /**< \brief Usart1 signal: DTR1 */
+#define PIO_PA29A_RI1      (1u << 29) /**< \brief Usart1 signal: RI1 */
+#define PIO_PA24A_RTS1     (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1     (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1     (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1     (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PC17B_CTS2     (1u << 17) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PC16B_RTS2     (1u << 16) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PC9B_RXD2      (1u << 9)  /**< \brief Usart2 signal: RXD2 */
+#define PIO_PC14B_SCK2     (1u << 14) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PC10B_TXD2     (1u << 10) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PA21_IDX       21
+#define PIO_PA22_IDX       22
+#define PIO_PA23_IDX       23
+#define PIO_PA24_IDX       24
+#define PIO_PA25_IDX       25
+#define PIO_PA26_IDX       26
+#define PIO_PA27_IDX       27
+#define PIO_PA28_IDX       28
+#define PIO_PA29_IDX       29
+#define PIO_PA30_IDX       30
+#define PIO_PA31_IDX       31
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+#define PIO_PB13_IDX       45
+#define PIO_PB14_IDX       46
+#define PIO_PC0_IDX        64
+#define PIO_PC1_IDX        65
+#define PIO_PC2_IDX        66
+#define PIO_PC3_IDX        67
+#define PIO_PC4_IDX        68
+#define PIO_PC5_IDX        69
+#define PIO_PC6_IDX        70
+#define PIO_PC7_IDX        71
+#define PIO_PC8_IDX        72
+#define PIO_PC9_IDX        73
+#define PIO_PC10_IDX       74
+#define PIO_PC11_IDX       75
+#define PIO_PC12_IDX       76
+#define PIO_PC13_IDX       77
+#define PIO_PC14_IDX       78
+#define PIO_PC15_IDX       79
+#define PIO_PC16_IDX       80
+#define PIO_PC17_IDX       81
+#define PIO_PC18_IDX       82
+#define PIO_PC19_IDX       83
+#define PIO_PC20_IDX       84
+#define PIO_PC21_IDX       85
+#define PIO_PC22_IDX       86
+#define PIO_PC23_IDX       87
+#define PIO_PC24_IDX       88
+#define PIO_PC25_IDX       89
+#define PIO_PC26_IDX       90
+#define PIO_PC27_IDX       91
+#define PIO_PC28_IDX       92
+#define PIO_PC29_IDX       93
+#define PIO_PC30_IDX       94
+#define PIO_PC31_IDX       95
+
+#endif /* _SAM3SD8C_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/sam3s8.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/sam3s8.h
new file mode 100644
index 000000000..0550476b3
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/sam3s8.h
@@ -0,0 +1,49 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_
+#define _SAM3S8_
+
+#if defined __SAM3SD8A__
+  #include "sam3sd8a.h"
+#elif defined __SAM3SD8B__
+  #include "sam3sd8b.h"
+#elif defined __SAM3SD8C__
+  #include "sam3sd8c.h"
+#elif defined __SAM3S8A__
+  #include "sam3s8a.h"
+#elif defined __SAM3S8B__
+  #include "sam3s8b.h"
+#elif defined __SAM3S8C__
+  #include "sam3s8c.h"
+#else
+  #error Library does not support the specified device.
+#endif
+
+#endif /* _SAM3S8_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/sam3s8a.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/sam3s8a.h
new file mode 100644
index 000000000..abcf69d0a
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/sam3s8a.h
@@ -0,0 +1,358 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8A_
+#define _SAM3S8A_
+
+/** \addtogroup SAM3S8A_definitions SAM3S8A definitions
+  This file defines all structures and symbols for SAM3S8A:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3S8A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8A_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3S8A specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3S8A Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3S8A Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3S8A Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3S8A Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3S8A Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3S8A Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3S8A Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3S8A UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3S8A UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3S8A Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3S8A Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3S8A USART 0 (USART0) */
+  TWI0_IRQn            = 19, /**< 19 SAM3S8A Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3S8A Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3S8A Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3S8A Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3S8A Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3S8A Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3S8A Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3S8A Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3S8A Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3S8A Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3S8A CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3S8A Analog Comparator (ACC) */
+  UDP_IRQn             = 34  /**< 34 SAM3S8A USB Device Port (UDP) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3S8A core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S8A does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S8A uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S8A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8A_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3S8A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3S8A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8A_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3S8A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3S8A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8A_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3s8a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3S8A */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x80000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (2048u)
+#define IFLASH_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE               (0x10000u)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3S8A */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (64000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3S8A_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/sam3s8b.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/sam3s8b.h
new file mode 100644
index 000000000..a4d517ef4
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/sam3s8b.h
@@ -0,0 +1,373 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8B_
+#define _SAM3S8B_
+
+/** \addtogroup SAM3S8B_definitions SAM3S8B definitions
+  This file defines all structures and symbols for SAM3S8B:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3S8B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8B_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3S8B specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3S8B Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3S8B Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3S8B Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3S8B Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3S8B Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3S8B Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3S8B Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3S8B UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3S8B UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3S8B Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3S8B Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3S8B USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3S8B USART 1 (USART1) */
+  HSMCI_IRQn           = 18, /**< 18 SAM3S8B Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 19, /**< 19 SAM3S8B Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3S8B Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3S8B Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3S8B Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3S8B Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3S8B Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3S8B Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3S8B Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3S8B Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3S8B Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3S8B CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3S8B Analog Comparator (ACC) */
+  UDP_IRQn             = 34  /**< 34 SAM3S8B USB Device Port (UDP) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3S8B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S8B does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S8B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S8B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8B_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3S8B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3S8B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8B_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3S8B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  ((Pdc    *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3S8B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8B_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3s8b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3S8B */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x80000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (2048u)
+#define IFLASH_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE               (0x10000u)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3S8B */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (64000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3S8B_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/sam3s8c.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/sam3s8c.h
new file mode 100644
index 000000000..d1bf39f60
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/sam3s8c.h
@@ -0,0 +1,400 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8C_
+#define _SAM3S8C_
+
+/** \addtogroup SAM3S8C_definitions SAM3S8C definitions
+  This file defines all structures and symbols for SAM3S8C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3S8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3S8C specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3S8C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3S8C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3S8C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3S8C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3S8C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3S8C Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3S8C Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3S8C UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3S8C UART 1 (UART1) */
+  SMC_IRQn             = 10, /**< 10 SAM3S8C Static Memory Controller (SMC) */
+  PIOA_IRQn            = 11, /**< 11 SAM3S8C Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3S8C Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM3S8C Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 14, /**< 14 SAM3S8C USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3S8C USART 1 (USART1) */
+  USART2_IRQn          = 16, /**< 16 SAM3S8C USART 2 (SAM3SD8 100 pins only) (USART2) */
+  HSMCI_IRQn           = 18, /**< 18 SAM3S8C Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 19, /**< 19 SAM3S8C Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3S8C Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3S8C Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3S8C Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3S8C Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3S8C Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3S8C Timer/Counter 2 (TC2) */
+  TC3_IRQn             = 26, /**< 26 SAM3S8C Timer/Counter 3 (TC3) */
+  TC4_IRQn             = 27, /**< 27 SAM3S8C Timer/Counter 4 (TC4) */
+  TC5_IRQn             = 28, /**< 28 SAM3S8C Timer/Counter 5 (TC5) */
+  ADC_IRQn             = 29, /**< 29 SAM3S8C Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3S8C Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3S8C Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3S8C CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3S8C Analog Comparator (ACC) */
+  UDP_IRQn             = 34  /**< 34 SAM3S8C USB Device Port (UDP) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3S8C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S8C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S8C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3S8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3S8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_SMC    (10) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (16) /**< \brief USART 2 (SAM3SD8 100 pins only) (USART2) */
+#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_TC3    (26) /**< \brief Timer/Counter 3 (TC3) */
+#define ID_TC4    (27) /**< \brief Timer/Counter 4 (TC4) */
+#define ID_TC5    (28) /**< \brief Timer/Counter 5 (TC5) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3S8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x4002C000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x4002C100U) /**< \brief (PDC_USART2) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  ((Pdc    *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x4002C000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x4002C100U) /**< \brief (PDC_USART2) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3S8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3s8c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3S8C */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x80000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (2048u)
+#define IFLASH_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE               (0x10000u)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3S8C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (64000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3S8C_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/sam3sd8a.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/sam3sd8a.h
new file mode 100644
index 000000000..d118aae17
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/sam3sd8a.h
@@ -0,0 +1,364 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3SD8A_
+#define _SAM3SD8A_
+
+/** \addtogroup SAM3SD8A_definitions SAM3SD8A definitions
+  This file defines all structures and symbols for SAM3SD8A:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3SD8A */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8A_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3SD8A specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3SD8A Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3SD8A Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3SD8A Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3SD8A Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3SD8A Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3SD8A Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3SD8A Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3SD8A UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3SD8A UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3SD8A Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3SD8A Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3SD8A USART 0 (USART0) */
+  TWI0_IRQn            = 19, /**< 19 SAM3SD8A Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3SD8A Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3SD8A Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3SD8A Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3SD8A Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3SD8A Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3SD8A Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3SD8A Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3SD8A Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3SD8A Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3SD8A CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3SD8A Analog Comparator (ACC) */
+  UDP_IRQn             = 34  /**< 34 SAM3SD8A USB Device Port (UDP) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3SD8A core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3SD8A does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3SD8A uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3SD8A */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8A_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3SD8A */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3SD8A */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8A_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3SD8A */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3SD8A */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8A_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3sd8a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3SD8A */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x40000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (1024u)
+#define IFLASH0_NB_OF_LOCK_BITS  (16u)
+#define IFLASH1_SIZE             (0x40000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (1024u)
+#define IFLASH1_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE                (0x10000u)
+#define IFLASH_SIZE              (0x80000u)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3SD8A */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (64000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3SD8A_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/sam3sd8b.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/sam3sd8b.h
new file mode 100644
index 000000000..bfab73420
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/sam3sd8b.h
@@ -0,0 +1,379 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3SD8B_
+#define _SAM3SD8B_
+
+/** \addtogroup SAM3SD8B_definitions SAM3SD8B definitions
+  This file defines all structures and symbols for SAM3SD8B:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3SD8B */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8B_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3SD8B specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3SD8B Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3SD8B Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3SD8B Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3SD8B Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3SD8B Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3SD8B Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3SD8B Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3SD8B UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3SD8B UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3SD8B Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3SD8B Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3SD8B USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3SD8B USART 1 (USART1) */
+  HSMCI_IRQn           = 18, /**< 18 SAM3SD8B Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 19, /**< 19 SAM3SD8B Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3SD8B Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3SD8B Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3SD8B Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3SD8B Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3SD8B Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3SD8B Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3SD8B Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3SD8B Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3SD8B Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3SD8B CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3SD8B Analog Comparator (ACC) */
+  UDP_IRQn             = 34  /**< 34 SAM3SD8B USB Device Port (UDP) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3SD8B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3SD8B does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3SD8B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3SD8B */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8B_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3SD8B */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3SD8B */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8B_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3SD8B */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  ((Pdc    *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3SD8B */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8B_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3sd8b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3SD8B */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x40000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (1024u)
+#define IFLASH0_NB_OF_LOCK_BITS  (16u)
+#define IFLASH1_SIZE             (0x40000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (1024u)
+#define IFLASH1_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE                (0x10000u)
+#define IFLASH_SIZE              (0x80000u)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3SD8B */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (64000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3SD8B_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/include/sam3sd8c.h b/hardware/sam/system/libsam/cmsis/sam3sd8/include/sam3sd8c.h
new file mode 100644
index 000000000..08ddfcb68
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/include/sam3sd8c.h
@@ -0,0 +1,406 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3SD8C_
+#define _SAM3SD8C_
+
+/** \addtogroup SAM3SD8C_definitions SAM3SD8C definitions
+  This file defines all structures and symbols for SAM3SD8C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3SD8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3SD8C specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3SD8C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3SD8C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3SD8C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3SD8C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3SD8C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3SD8C Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3SD8C Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3SD8C UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3SD8C UART 1 (UART1) */
+  SMC_IRQn             = 10, /**< 10 SAM3SD8C Static Memory Controller (SMC) */
+  PIOA_IRQn            = 11, /**< 11 SAM3SD8C Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3SD8C Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM3SD8C Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 14, /**< 14 SAM3SD8C USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3SD8C USART 1 (USART1) */
+  USART2_IRQn          = 16, /**< 16 SAM3SD8C USART 2 (SAM3SD8 100 pins only) (USART2) */
+  HSMCI_IRQn           = 18, /**< 18 SAM3SD8C Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 19, /**< 19 SAM3SD8C Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3SD8C Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3SD8C Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3SD8C Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3SD8C Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3SD8C Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3SD8C Timer/Counter 2 (TC2) */
+  TC3_IRQn             = 26, /**< 26 SAM3SD8C Timer/Counter 3 (TC3) */
+  TC4_IRQn             = 27, /**< 27 SAM3SD8C Timer/Counter 4 (TC4) */
+  TC5_IRQn             = 28, /**< 28 SAM3SD8C Timer/Counter 5 (TC5) */
+  ADC_IRQn             = 29, /**< 29 SAM3SD8C Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3SD8C Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3SD8C Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3SD8C CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3SD8C Analog Comparator (ACC) */
+  UDP_IRQn             = 34  /**< 34 SAM3SD8C USB Device Port (UDP) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3SD8C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3SD8C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3SD8C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3SD8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3SD8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3SD8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_SMC    (10) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (16) /**< \brief USART 2 (SAM3SD8 100 pins only) (USART2) */
+#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_TC3    (26) /**< \brief Timer/Counter 3 (TC3) */
+#define ID_TC4    (27) /**< \brief Timer/Counter 4 (TC4) */
+#define ID_TC5    (28) /**< \brief Timer/Counter 5 (TC5) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3SD8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x4002C000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x4002C100U) /**< \brief (PDC_USART2) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  ((Pdc    *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x4002C000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x4002C100U) /**< \brief (PDC_USART2) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3SD8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3sd8c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3SD8C */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x40000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (1024u)
+#define IFLASH0_NB_OF_LOCK_BITS  (16u)
+#define IFLASH1_SIZE             (0x40000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (1024u)
+#define IFLASH1_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE                (0x10000u)
+#define IFLASH_SIZE              (0x80000u)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3SD8C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (64000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3SD8C_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/exceptions.c b/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/exceptions.c
new file mode 100644
index 000000000..f67d1b6a3
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/exceptions.c
@@ -0,0 +1,143 @@
+/*! \file *********************************************************************
+ *
+ * \brief This file contains the default exception handlers.
+ *
+ * $asf_license$
+ *
+ * \par Purpose
+ *
+ * This file provides basic support for Cortex-M processor based 
+ * microcontrollers.
+ *
+ * \note
+ * The exception handler has weak aliases.
+ * As they are weak aliases, any function with the same name will override
+ * this definition.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+#include "exceptions.h"
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#ifdef __GNUC__
+/* Cortex-M3 core handlers */
+void Reset_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void NMI_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void ACC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void ADC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void CRCCU_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void DAC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void EEFC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void MCI_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOA_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PWM_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SMC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SSC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SUPC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void USBD_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* __GNUC__ */
+
+#ifdef __ICCARM__
+/* Cortex-M3 core handlers */
+#pragma weak Reset_Handler=Dummy_Handler
+#pragma weak NMI_Handler=Dummy_Handler
+#pragma weak HardFault_Handler=Dummy_Handler
+#pragma weak MemManage_Handler=Dummy_Handler
+#pragma weak BusFault_Handler=Dummy_Handler
+#pragma weak UsageFault_Handler=Dummy_Handler
+#pragma weak SVC_Handler=Dummy_Handler
+#pragma weak DebugMon_Handler=Dummy_Handler
+#pragma weak PendSV_Handler=Dummy_Handler
+#pragma weak SysTick_Handler=Dummy_Handler
+
+/* Peripherals handlers */
+#pragma weak ACC_IrqHandler=Dummy_Handler
+#pragma weak ADC_IrqHandler=Dummy_Handler
+#pragma weak CRCCU_IrqHandler=Dummy_Handler
+#pragma weak DAC_IrqHandler=Dummy_Handler
+#pragma weak EEFC_IrqHandler=Dummy_Handler
+#pragma weak MCI_IrqHandler=Dummy_Handler
+#pragma weak PIOA_IrqHandler=Dummy_Handler
+#pragma weak PIOB_IrqHandler=Dummy_Handler
+#pragma weak PIOC_IrqHandler=Dummy_Handler
+#pragma weak PMC_IrqHandler=Dummy_Handler
+#pragma weak PWM_IrqHandler=Dummy_Handler
+#pragma weak RSTC_IrqHandler=Dummy_Handler
+#pragma weak RTC_IrqHandler=Dummy_Handler
+#pragma weak RTT_IrqHandler=Dummy_Handler
+#pragma weak SMC_IrqHandler=Dummy_Handler
+#pragma weak SPI_IrqHandler=Dummy_Handler
+#pragma weak SSC_IrqHandler=Dummy_Handler
+#pragma weak SUPC_IrqHandler=Dummy_Handler
+#pragma weak TC0_IrqHandler=Dummy_Handler
+#pragma weak TC1_IrqHandler=Dummy_Handler
+#pragma weak TC2_IrqHandler=Dummy_Handler
+#pragma weak TC3_IrqHandler=Dummy_Handler
+#pragma weak TC4_IrqHandler=Dummy_Handler
+#pragma weak TC5_IrqHandler=Dummy_Handler
+#pragma weak TWI0_IrqHandler=Dummy_Handler
+#pragma weak TWI1_IrqHandler=Dummy_Handler
+#pragma weak UART0_IrqHandler=Dummy_Handler
+#pragma weak UART1_IrqHandler=Dummy_Handler
+#pragma weak USART0_IrqHandler=Dummy_Handler
+#pragma weak USART1_IrqHandler=Dummy_Handler
+#pragma weak USBD_IrqHandler=Dummy_Handler
+#pragma weak WDT_IrqHandler=Dummy_Handler
+#endif /* __ICCARM__ */
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/exceptions.h b/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/exceptions.h
new file mode 100644
index 000000000..9fe540757
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/exceptions.h
@@ -0,0 +1,88 @@
+/*! \file *********************************************************************
+ *
+ * \brief This file contains the interface for default exception handlers.
+ *
+ * $asf_license$
+ *
+ * \par Purpose
+ *
+ * This file provides basic support for Cortex-M processor based 
+ * microcontrollers.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+#ifndef EXCEPTIONS_H_INCLUDED
+#define EXCEPTIONS_H_INCLUDED
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+/* Function prototype for exception table items (interrupt handler). */
+typedef void (*IntFunc) (void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+void Reset_Handler(void);
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+
+/* Peripherals handlers */
+void ACC_IrqHandler(void);
+void ADC_IrqHandler(void);
+void CRCCU_IrqHandler(void);
+void DAC_IrqHandler(void);
+void EEFC_IrqHandler(void);
+void MCI_IrqHandler(void);
+void PIOA_IrqHandler(void);
+void PIOB_IrqHandler(void);
+void PIOC_IrqHandler(void);
+void PMC_IrqHandler(void);
+void PWM_IrqHandler(void);
+void RSTC_IrqHandler(void);
+void RTC_IrqHandler(void);
+void RTT_IrqHandler(void);
+void SMC_IrqHandler(void);
+void SPI_IrqHandler(void);
+void SSC_IrqHandler(void);
+void SUPC_IrqHandler(void);
+void TC0_IrqHandler(void);
+void TC1_IrqHandler(void);
+void TC2_IrqHandler(void);
+void TC3_IrqHandler(void);
+void TC4_IrqHandler(void);
+void TC5_IrqHandler(void);
+void TWI0_IrqHandler(void);
+void TWI1_IrqHandler(void);
+void UART0_IrqHandler(void);
+void UART1_IrqHandler(void);
+void USART0_IrqHandler(void);
+void USART1_IrqHandler(void);
+void USBD_IrqHandler(void);
+void WDT_IrqHandler(void);
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#endif /* EXCEPTIONS_H_INCLUDED */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/gcc/startup_sam3sd8.c b/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/gcc/startup_sam3sd8.c
new file mode 100644
index 000000000..67c3d62b4
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/gcc/startup_sam3sd8.c
@@ -0,0 +1,137 @@
+/*! \file *********************************************************************
+ *
+ * \brief Startup file for SAM3S8/SAM3SD.
+ *
+ * $asf_license$
+ *
+ * This file defines common SAM series.
+ *
+ * - Compiler:           ARMGCC
+ * - Supported devices:  All SAM3S8/SAM3SD devices can be used.
+ * - AppNote:
+ *
+ ******************************************************************************/
+
+#include "../exceptions.h"
+#include "sam3.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+IntFunc exception_table[] = {
+
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(IntFunc) (&_estack),
+	Reset_Handler,
+
+	NMI_Handler,
+	HardFault_Handler,
+	MemManage_Handler,
+	BusFault_Handler,
+	UsageFault_Handler,
+	0, 0, 0, 0,         /*  Reserved */
+	SVC_Handler,
+	DebugMon_Handler,
+	0,                  /*  Reserved */
+	PendSV_Handler,
+	SysTick_Handler,
+
+	/* Configurable interrupts */
+	SUPC_IrqHandler,    /* 0  Supply Controller */
+	RSTC_IrqHandler,    /* 1  Reset Controller */
+	RTC_IrqHandler,     /* 2  Real Time Clock */
+	RTT_IrqHandler,     /* 3  Real Time Timer */
+	WDT_IrqHandler,     /* 4  Watchdog Timer */
+	PMC_IrqHandler,     /* 5  PMC */
+	EEFC_IrqHandler,	/* 6  EEFC */
+	Dummy_Handler,      /* 7  Reserved */
+	UART0_IrqHandler,   /* 8  UART0 */
+	UART1_IrqHandler,   /* 9  UART1 */
+	SMC_IrqHandler,     /* 10 SMC */
+	PIOA_IrqHandler,    /* 11 Parallel IO Controller A */
+	PIOB_IrqHandler,    /* 12 Parallel IO Controller B */
+	PIOC_IrqHandler,    /* 13 Parallel IO Controller C */
+	USART0_IrqHandler,  /* 14 USART 0 */
+	USART1_IrqHandler,  /* 15 USART 1 */
+	Dummy_Handler,      /* 16 Reserved */
+	Dummy_Handler,      /* 17 Reserved */
+	MCI_IrqHandler,     /* 18 MCI */
+	TWI0_IrqHandler,    /* 19 TWI 0 */
+	TWI1_IrqHandler,    /* 20 TWI 1 */
+	SPI_IrqHandler,     /* 21 SPI */
+	SSC_IrqHandler,     /* 22 SSC */
+	TC0_IrqHandler,     /* 23 Timer Counter 0 */
+	TC1_IrqHandler,     /* 24 Timer Counter 1 */
+	TC2_IrqHandler,     /* 25 Timer Counter 2 */
+	TC3_IrqHandler,     /* 26 Timer Counter 3 */
+	TC4_IrqHandler,     /* 27 Timer Counter 4 */
+	TC5_IrqHandler,     /* 28 Timer Counter 5 */
+	ADC_IrqHandler,     /* 29 ADC controller */
+	DAC_IrqHandler,     /* 30 DAC controller */
+	PWM_IrqHandler,     /* 31 PWM */
+	CRCCU_IrqHandler,   /* 32 CRC Calculation Unit */
+	ACC_IrqHandler,     /* 33 Analog Comparator */
+	USBD_IrqHandler,    /* 34 USB Device Port */
+	Dummy_Handler       /* 35 not used */
+};
+
+/* TEMPORARY PATCH FOR SCB */
+#define SCB_VTOR_TBLBASE_Pos               29                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/iar/startup_sam3sd8.c b/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/iar/startup_sam3sd8.c
new file mode 100644
index 000000000..4e025ce4f
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/iar/startup_sam3sd8.c
@@ -0,0 +1,113 @@
+/*! \file *********************************************************************
+ *
+ * \brief Startup file for SAM3S8/SAM3SD.
+ *
+ * $asf_license$
+ *
+ * This file defines common SAM series.
+ *
+ * - Compiler:           IAR EWARM
+ * - Supported devices:  All SAM3S8/SAM3SD devices can be used.
+ * - AppNote:
+ *
+ ******************************************************************************/
+
+#include "../exceptions.h"
+#include "sam3.h"
+
+typedef void (*intfunc) (void);
+typedef union { intfunc __fun; void * __ptr; } intvec_elem;
+
+void __iar_program_start(void);
+int __low_level_init(void);
+
+/* Exception Table */
+#pragma language=extended
+#pragma segment="CSTACK"
+
+/* The name "__vector_table" has special meaning for C-SPY: */
+/* it is where the SP start value is found, and the NVIC vector */
+/* table register (VTOR) is initialized to this address if != 0 */
+
+#pragma section = ".intvec"
+#pragma location = ".intvec"
+const intvec_elem __vector_table[] = {
+	{.__ptr = __sfe("CSTACK")},
+	Reset_Handler,
+
+	NMI_Handler,
+	HardFault_Handler,
+	MemManage_Handler,
+	BusFault_Handler,
+	UsageFault_Handler,
+	0, 0, 0, 0,         /*  Reserved */
+	SVC_Handler,
+	DebugMon_Handler,
+	0,                  /*  Reserved */
+	PendSV_Handler,
+	SysTick_Handler,
+
+	/* Configurable interrupts */
+	SUPC_IrqHandler,    /* 0  Supply Controller */
+	RSTC_IrqHandler,    /* 1  Reset Controller */
+	RTC_IrqHandler,     /* 2  Real Time Clock */
+	RTT_IrqHandler,     /* 3  Real Time Timer */
+	WDT_IrqHandler,     /* 4  Watchdog Timer */
+	PMC_IrqHandler,     /* 5  PMC */
+	EEFC_IrqHandler,	/* 6  EEFC */
+	Dummy_Handler,      /* 7  Reserved */
+	UART0_IrqHandler,   /* 8  UART0 */
+	UART1_IrqHandler,   /* 9  UART1 */
+	SMC_IrqHandler,     /* 10 SMC */
+	PIOA_IrqHandler,    /* 11 Parallel IO Controller A */
+	PIOB_IrqHandler,    /* 12 Parallel IO Controller B */
+	PIOC_IrqHandler,    /* 13 Parallel IO Controller C */
+	USART0_IrqHandler,  /* 14 USART 0 */
+	USART1_IrqHandler,  /* 15 USART 1 */
+	Dummy_Handler,      /* 16 Reserved */
+	Dummy_Handler,      /* 17 Reserved */
+	MCI_IrqHandler,     /* 18 MCI */
+	TWI0_IrqHandler,    /* 19 TWI 0 */
+	TWI1_IrqHandler,    /* 20 TWI 1 */
+	SPI_IrqHandler,     /* 21 SPI */
+	SSC_IrqHandler,     /* 22 SSC */
+	TC0_IrqHandler,     /* 23 Timer Counter 0 */
+	TC1_IrqHandler,     /* 24 Timer Counter 1 */
+	TC2_IrqHandler,     /* 25 Timer Counter 2 */
+	TC3_IrqHandler,     /* 26 Timer Counter 3 */
+	TC4_IrqHandler,     /* 27 Timer Counter 4 */
+	TC5_IrqHandler,     /* 28 Timer Counter 5 */
+	ADC_IrqHandler,     /* 29 ADC controller */
+	DAC_IrqHandler,     /* 30 DAC controller */
+	PWM_IrqHandler,     /* 31 PWM */
+	CRCCU_IrqHandler,   /* 32 CRC Calculation Unit */
+	ACC_IrqHandler,     /* 33 Analog Comparator */
+	USBD_IrqHandler,    /* 34 USB Device Port */
+	Dummy_Handler       /* 35 not used */
+};
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+int __low_level_init(void)
+{
+	uint32_t *pSrc = __section_begin(".intvec");
+
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	return 1; /* if return 0, the data sections will not be initialized */
+}
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+	__iar_program_start();
+}
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/system_sam3sd8.c b/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/system_sam3sd8.c
new file mode 100644
index 000000000..507f74499
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/system_sam3sd8.c
@@ -0,0 +1,196 @@
+/*! \file *********************************************************************
+ *
+ * \brief Provides the low-level initialization functions that called 
+ * on chip startup.
+ *
+ * $asf_license$
+ *
+ * \par Purpose
+ *
+ * This file provides basic support for Cortex-M processor based 
+ * microcontrollers.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+#include "system_sam3sd8.h"
+#include "sam3s8.h"
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+/* Clock settings (64MHz) */
+#define SYS_BOARD_OSCOUNT   (CKGR_MOR_MOSCXTST(0x8))
+#define SYS_BOARD_PLLAR     (CKGR_PLLAR_ONE \
+							| CKGR_PLLAR_MULA(0xf) \
+							| CKGR_PLLAR_PLLACOUNT(0x3f) \
+							| CKGR_PLLAR_DIVA(0x3))
+#define SYS_BOARD_MCKR      (PMC_MCKR_PRES_CLK_1 | PMC_MCKR_CSS_PLLA_CLK)
+
+/* Clock Definitions */
+#define SYS_FREQ_XTAL_32K      	(32768UL)		/* External 32K crystal frequency */
+#define SYS_FREQ_XTAL_XTAL12M	(12000000UL)	/* External 12M crystal frequency */
+
+#define SYS_FREQ_FWS_0	(21000000UL)	/* Maximum operating frequency when FWS is 0 */
+#define SYS_FREQ_FWS_1	(35000000UL)	/* Maximum operating frequency when FWS is 1 */
+#define SYS_FREQ_FWS_2	(60000000UL)	/* Maximum operating frequency when FWS is 2 */
+
+#define SYS_CKGR_MOR_KEY_VALUE	CKGR_MOR_KEY(0x37) /* Key to unlock MOR register */
+
+/* FIXME: should be generated by sock */
+uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+/**
+ * \brief Setup the microcontroller system.
+ * Initialize the System and update the SystemFrequency variable.
+ */
+void SystemInit(void)
+{
+	/* Set 3 FWS for Embedded Flash Access */
+	EFC->EEFC_FMR = EEFC_FMR_FWS(CHIP_FLASH_WAIT_STATE);
+
+	/* Initialize main oscillator */
+	if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {
+		PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |
+			                     CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
+		while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
+		}
+	}
+
+	/* Switch to 3-20MHz Xtal oscillator */
+	PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | 
+	                           CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
+
+	while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
+	}
+	PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	/* Initialize PLLA */
+	PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
+	while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
+	}
+
+	/* Switch to main clock */
+	PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	/* Switch to PLLA */
+	PMC->PMC_MCKR = SYS_BOARD_MCKR;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	SystemCoreClock = CHIP_FREQ_CPU_MAX;
+}
+
+void SystemCoreClockUpdate(void)
+{
+	/* Determine clock frequency according to clock register values */
+	switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {
+	case PMC_MCKR_CSS_SLOW_CLK:	/* Slow clock */
+		if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
+			SystemCoreClock = SYS_FREQ_XTAL_32K;
+		} else {
+			SystemCoreClock = CHIP_FREQ_SLCK_RC;
+		}
+		break;
+	case PMC_MCKR_CSS_MAIN_CLK:	/* Main clock */
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
+			SystemCoreClock = SYS_FREQ_XTAL_XTAL12M;
+		} else {
+			SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+			switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
+			case CKGR_MOR_MOSCRCF_4_MHz:
+				break;
+			case CKGR_MOR_MOSCRCF_8_MHz:
+				SystemCoreClock *= 2U;
+				break;
+			case CKGR_MOR_MOSCRCF_12_MHz:
+				SystemCoreClock *= 3U;
+				break;
+			default:
+				break;
+			}
+		}
+		break;
+	case PMC_MCKR_CSS_PLLA_CLK:	/* PLLA clock */
+	case PMC_MCKR_CSS_PLLB_CLK:	/* PLLB clock */
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
+			SystemCoreClock = SYS_FREQ_XTAL_XTAL12M;
+		} else {
+			SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+			switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
+			case CKGR_MOR_MOSCRCF_4_MHz:
+				break;
+			case CKGR_MOR_MOSCRCF_8_MHz:
+				SystemCoreClock *= 2U;
+				break;
+			case CKGR_MOR_MOSCRCF_12_MHz:
+				SystemCoreClock *= 3U;
+				break;
+			default:
+				break;
+			}
+		}
+		if ((PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {
+			SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> 
+				                         CKGR_PLLAR_MULA_Pos) + 1U);
+			SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >> 
+				                          CKGR_PLLAR_DIVA_Pos));
+		} else {
+			SystemCoreClock *= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_MULB_Msk) >>
+				                         CKGR_PLLBR_MULB_Pos) + 1U);
+			SystemCoreClock /= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_DIVB_Msk) >> 
+				                           CKGR_PLLBR_DIVB_Pos));
+		}
+		break;
+	}
+
+	if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
+		SystemCoreClock /= 3U;
+	} else {
+		SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> 
+			                           PMC_MCKR_PRES_Pos);
+	}
+}
+
+/** 
+ * Initialize flash and watchdog.
+ */
+void system_init_flash_and_watchdog(uint32_t dw_clk)
+{
+	/* Set FWS for embedded Flash access according to operating frequency */
+	if (dw_clk < SYS_FREQ_FWS_0) {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(0);
+	} else if (dw_clk < SYS_FREQ_FWS_1) {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(1);
+	} else if (dw_clk < SYS_FREQ_FWS_2) {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(2);
+	} else {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(3);
+	}
+	
+#ifndef CONFIG_KEEP_WATCHDOG_AFTER_INIT 
+	/* Disable the watchdog */
+	WDT->WDT_MR = WDT_MR_WDDIS;
+#endif
+}
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
diff --git a/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/system_sam3sd8.h b/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/system_sam3sd8.h
new file mode 100644
index 000000000..b40962425
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3sd8/source/templates/system_sam3sd8.h
@@ -0,0 +1,58 @@
+/*! \file *********************************************************************
+ *
+ * \brief CMSIS Cortex-M# Device Peripheral Access Layer Header File
+ *           for SAM3 devices.
+ *
+ * $asf_license$
+ *
+ * \par Purpose
+ *
+ * This file provides basic support for Cortex-M processor based 
+ * microcontrollers.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+#ifndef SYSTEM_SAM3SD8_H_INCLUDED
+#define SYSTEM_SAM3SD8_H_INCLUDED
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#include 
+
+extern uint32_t SystemCoreClock;	/* System Clock Frequency (Core Clock) */
+
+/**
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+void SystemInit(void);
+
+/**
+ * @brief Updates the SystemCoreClock with current core Clock 
+ * retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void);
+
+/** 
+ * Initialize flash and watchdog.
+ */
+void system_init_flash_and_watchdog(uint32_t dw_clk);
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#endif /* SYSTEM_SAM3SD8_H_INCLUDED */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_adc.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_adc.h
new file mode 100644
index 000000000..d83700636
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_adc.h
@@ -0,0 +1,263 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_ADC_COMPONENT_
+#define _SAM3U_ADC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Analog-to-digital Converter */
+/* ============================================================================= */
+/** \addtogroup SAM3U_ADC Analog-to-digital Converter */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Adc hardware registers */
+typedef struct {
+  WoReg ADC_CR;        /**< \brief (Adc Offset: 0x00) Control Register */
+  RwReg ADC_MR;        /**< \brief (Adc Offset: 0x04) Mode Register */
+  RoReg Reserved1[2];
+  WoReg ADC_CHER;      /**< \brief (Adc Offset: 0x10) Channel Enable Register */
+  WoReg ADC_CHDR;      /**< \brief (Adc Offset: 0x14) Channel Disable Register */
+  RoReg ADC_CHSR;      /**< \brief (Adc Offset: 0x18) Channel Status Register */
+  RoReg ADC_SR;        /**< \brief (Adc Offset: 0x1C) Status Register */
+  RoReg ADC_LCDR;      /**< \brief (Adc Offset: 0x20) Last Converted Data Register */
+  WoReg ADC_IER;       /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */
+  WoReg ADC_IDR;       /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */
+  RoReg ADC_IMR;       /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */
+  RoReg ADC_CDR[8];    /**< \brief (Adc Offset: 0x30) Channel Data Register */
+  RoReg Reserved2[44];
+  RwReg ADC_RPR;       /**< \brief (Adc Offset: 0x100) Receive Pointer Register */
+  RwReg ADC_RCR;       /**< \brief (Adc Offset: 0x104) Receive Counter Register */
+  RwReg ADC_TPR;       /**< \brief (Adc Offset: 0x108) Transmit Pointer Register */
+  RwReg ADC_TCR;       /**< \brief (Adc Offset: 0x10C) Transmit Counter Register */
+  RwReg ADC_RNPR;      /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */
+  RwReg ADC_RNCR;      /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */
+  RwReg ADC_TNPR;      /**< \brief (Adc Offset: 0x118) Transmit Next Pointer Register */
+  RwReg ADC_TNCR;      /**< \brief (Adc Offset: 0x11C) Transmit Next Counter Register */
+  WoReg ADC_PTCR;      /**< \brief (Adc Offset: 0x120) Transfer Control Register */
+  RoReg ADC_PTSR;      /**< \brief (Adc Offset: 0x124) Transfer Status Register */
+} Adc;
+#endif /* __ASSEMBLY__ */
+/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */
+#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */
+#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */
+/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */
+#define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */
+#define   ADC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */
+#define   ADC_MR_TRGEN_EN (0x1u << 0) /**< \brief (ADC_MR) Hardware trigger selected by TRGSEL field is enabled. */
+#define ADC_MR_TRGSEL_Pos 1
+#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */
+#define ADC_MR_TRGSEL(value) ((ADC_MR_TRGSEL_Msk & ((value) << ADC_MR_TRGSEL_Pos)))
+#define   ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC_MR) External trigger */
+#define   ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 0 */
+#define   ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 1 */
+#define   ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 2 */
+#define   ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) /**< \brief (ADC_MR) PWM Event Line 0 */
+#define   ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) /**< \brief (ADC_MR) PWM Event Line 1 */
+#define ADC_MR_LOWRES (0x1u << 4) /**< \brief (ADC_MR) Resolution */
+#define   ADC_MR_LOWRES_BITS_10 (0x0u << 4) /**< \brief (ADC_MR) 10-bit resolution */
+#define   ADC_MR_LOWRES_BITS_8 (0x1u << 4) /**< \brief (ADC_MR) 8-bit resolution */
+#define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */
+#define   ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions */
+#define   ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions */
+#define ADC_MR_PRESCAL_Pos 8
+#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */
+#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos)))
+#define ADC_MR_STARTUP_Pos 16
+#define ADC_MR_STARTUP_Msk (0x7fu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */
+#define ADC_MR_STARTUP(value) ((ADC_MR_STARTUP_Msk & ((value) << ADC_MR_STARTUP_Pos)))
+#define ADC_MR_SHTIM_Pos 24
+#define ADC_MR_SHTIM_Msk (0xfu << ADC_MR_SHTIM_Pos) /**< \brief (ADC_MR) Sample & Hold Time */
+#define ADC_MR_SHTIM(value) ((ADC_MR_SHTIM_Msk & ((value) << ADC_MR_SHTIM_Pos)))
+/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */
+#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */
+#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */
+#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */
+#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */
+#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */
+#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */
+#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */
+#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */
+/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */
+#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */
+#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */
+#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */
+#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */
+#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */
+#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */
+#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */
+#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */
+/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */
+#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */
+#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */
+#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */
+#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */
+#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */
+#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */
+#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */
+#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */
+/* -------- ADC_SR : (ADC Offset: 0x1C) Status Register -------- */
+#define ADC_SR_EOC0 (0x1u << 0) /**< \brief (ADC_SR) End of Conversion 0 */
+#define ADC_SR_EOC1 (0x1u << 1) /**< \brief (ADC_SR) End of Conversion 1 */
+#define ADC_SR_EOC2 (0x1u << 2) /**< \brief (ADC_SR) End of Conversion 2 */
+#define ADC_SR_EOC3 (0x1u << 3) /**< \brief (ADC_SR) End of Conversion 3 */
+#define ADC_SR_EOC4 (0x1u << 4) /**< \brief (ADC_SR) End of Conversion 4 */
+#define ADC_SR_EOC5 (0x1u << 5) /**< \brief (ADC_SR) End of Conversion 5 */
+#define ADC_SR_EOC6 (0x1u << 6) /**< \brief (ADC_SR) End of Conversion 6 */
+#define ADC_SR_EOC7 (0x1u << 7) /**< \brief (ADC_SR) End of Conversion 7 */
+#define ADC_SR_OVRE0 (0x1u << 8) /**< \brief (ADC_SR) Overrun Error 0 */
+#define ADC_SR_OVRE1 (0x1u << 9) /**< \brief (ADC_SR) Overrun Error 1 */
+#define ADC_SR_OVRE2 (0x1u << 10) /**< \brief (ADC_SR) Overrun Error 2 */
+#define ADC_SR_OVRE3 (0x1u << 11) /**< \brief (ADC_SR) Overrun Error 3 */
+#define ADC_SR_OVRE4 (0x1u << 12) /**< \brief (ADC_SR) Overrun Error 4 */
+#define ADC_SR_OVRE5 (0x1u << 13) /**< \brief (ADC_SR) Overrun Error 5 */
+#define ADC_SR_OVRE6 (0x1u << 14) /**< \brief (ADC_SR) Overrun Error 6 */
+#define ADC_SR_OVRE7 (0x1u << 15) /**< \brief (ADC_SR) Overrun Error 7 */
+#define ADC_SR_DRDY (0x1u << 16) /**< \brief (ADC_SR) Data Ready */
+#define ADC_SR_GOVRE (0x1u << 17) /**< \brief (ADC_SR) General Overrun Error */
+#define ADC_SR_ENDRX (0x1u << 18) /**< \brief (ADC_SR) End of RX Buffer */
+#define ADC_SR_RXBUFF (0x1u << 19) /**< \brief (ADC_SR) RX Buffer Full */
+/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */
+#define ADC_LCDR_LDATA_Pos 0
+#define ADC_LCDR_LDATA_Msk (0x3ffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */
+/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */
+#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */
+#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */
+#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */
+#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */
+#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */
+#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */
+#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */
+#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */
+#define ADC_IER_OVRE0 (0x1u << 8) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 0 */
+#define ADC_IER_OVRE1 (0x1u << 9) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 1 */
+#define ADC_IER_OVRE2 (0x1u << 10) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 2 */
+#define ADC_IER_OVRE3 (0x1u << 11) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 3 */
+#define ADC_IER_OVRE4 (0x1u << 12) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 4 */
+#define ADC_IER_OVRE5 (0x1u << 13) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 5 */
+#define ADC_IER_OVRE6 (0x1u << 14) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 6 */
+#define ADC_IER_OVRE7 (0x1u << 15) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 7 */
+#define ADC_IER_DRDY (0x1u << 16) /**< \brief (ADC_IER) Data Ready Interrupt Enable */
+#define ADC_IER_GOVRE (0x1u << 17) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */
+#define ADC_IER_ENDRX (0x1u << 18) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */
+#define ADC_IER_RXBUFF (0x1u << 19) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */
+/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */
+#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */
+#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */
+#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */
+#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */
+#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */
+#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */
+#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */
+#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */
+#define ADC_IDR_OVRE0 (0x1u << 8) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 0 */
+#define ADC_IDR_OVRE1 (0x1u << 9) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 1 */
+#define ADC_IDR_OVRE2 (0x1u << 10) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 2 */
+#define ADC_IDR_OVRE3 (0x1u << 11) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 3 */
+#define ADC_IDR_OVRE4 (0x1u << 12) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 4 */
+#define ADC_IDR_OVRE5 (0x1u << 13) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 5 */
+#define ADC_IDR_OVRE6 (0x1u << 14) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 6 */
+#define ADC_IDR_OVRE7 (0x1u << 15) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 7 */
+#define ADC_IDR_DRDY (0x1u << 16) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */
+#define ADC_IDR_GOVRE (0x1u << 17) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */
+#define ADC_IDR_ENDRX (0x1u << 18) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */
+#define ADC_IDR_RXBUFF (0x1u << 19) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */
+/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */
+#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */
+#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */
+#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */
+#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */
+#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */
+#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */
+#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */
+#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */
+#define ADC_IMR_OVRE0 (0x1u << 8) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 0 */
+#define ADC_IMR_OVRE1 (0x1u << 9) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 1 */
+#define ADC_IMR_OVRE2 (0x1u << 10) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 2 */
+#define ADC_IMR_OVRE3 (0x1u << 11) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 3 */
+#define ADC_IMR_OVRE4 (0x1u << 12) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 4 */
+#define ADC_IMR_OVRE5 (0x1u << 13) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 5 */
+#define ADC_IMR_OVRE6 (0x1u << 14) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 6 */
+#define ADC_IMR_OVRE7 (0x1u << 15) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 7 */
+#define ADC_IMR_DRDY (0x1u << 16) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */
+#define ADC_IMR_GOVRE (0x1u << 17) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */
+#define ADC_IMR_ENDRX (0x1u << 18) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */
+#define ADC_IMR_RXBUFF (0x1u << 19) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */
+/* -------- ADC_CDR[8] : (ADC Offset: 0x30) Channel Data Register -------- */
+#define ADC_CDR_DATA_Pos 0
+#define ADC_CDR_DATA_Msk (0x3ffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[8]) Converted Data */
+/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */
+#define ADC_ACR_IBCTL_Pos 8
+#define ADC_ACR_IBCTL_Msk (0x3u << ADC_ACR_IBCTL_Pos) /**< \brief (ADC_ACR) ADC Bias Current Control */
+#define ADC_ACR_IBCTL(value) ((ADC_ACR_IBCTL_Msk & ((value) << ADC_ACR_IBCTL_Pos)))
+/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */
+#define ADC_RPR_RXPTR_Pos 0
+#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */
+#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos)))
+/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */
+#define ADC_RCR_RXCTR_Pos 0
+#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */
+#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos)))
+/* -------- ADC_TPR : (ADC Offset: 0x108) Transmit Pointer Register -------- */
+#define ADC_TPR_TXPTR_Pos 0
+#define ADC_TPR_TXPTR_Msk (0xffffffffu << ADC_TPR_TXPTR_Pos) /**< \brief (ADC_TPR) Transmit Counter Register */
+#define ADC_TPR_TXPTR(value) ((ADC_TPR_TXPTR_Msk & ((value) << ADC_TPR_TXPTR_Pos)))
+/* -------- ADC_TCR : (ADC Offset: 0x10C) Transmit Counter Register -------- */
+#define ADC_TCR_TXCTR_Pos 0
+#define ADC_TCR_TXCTR_Msk (0xffffu << ADC_TCR_TXCTR_Pos) /**< \brief (ADC_TCR) Transmit Counter Register */
+#define ADC_TCR_TXCTR(value) ((ADC_TCR_TXCTR_Msk & ((value) << ADC_TCR_TXCTR_Pos)))
+/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */
+#define ADC_RNPR_RXNPTR_Pos 0
+#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */
+#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos)))
+/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */
+#define ADC_RNCR_RXNCTR_Pos 0
+#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */
+#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos)))
+/* -------- ADC_TNPR : (ADC Offset: 0x118) Transmit Next Pointer Register -------- */
+#define ADC_TNPR_TXNPTR_Pos 0
+#define ADC_TNPR_TXNPTR_Msk (0xffffffffu << ADC_TNPR_TXNPTR_Pos) /**< \brief (ADC_TNPR) Transmit Next Pointer */
+#define ADC_TNPR_TXNPTR(value) ((ADC_TNPR_TXNPTR_Msk & ((value) << ADC_TNPR_TXNPTR_Pos)))
+/* -------- ADC_TNCR : (ADC Offset: 0x11C) Transmit Next Counter Register -------- */
+#define ADC_TNCR_TXNCTR_Pos 0
+#define ADC_TNCR_TXNCTR_Msk (0xffffu << ADC_TNCR_TXNCTR_Pos) /**< \brief (ADC_TNCR) Transmit Counter Next */
+#define ADC_TNCR_TXNCTR(value) ((ADC_TNCR_TXNCTR_Msk & ((value) << ADC_TNCR_TXNCTR_Pos)))
+/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */
+#define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */
+#define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */
+#define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */
+#define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */
+/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */
+#define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */
+#define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3U_ADC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_adc12b.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_adc12b.h
new file mode 100644
index 000000000..21f72a1d8
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_adc12b.h
@@ -0,0 +1,266 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_ADC12B_COMPONENT_
+#define _SAM3U_ADC12B_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Analog-to-Digital-Converter 12bits */
+/* ============================================================================= */
+/** \addtogroup SAM3U_ADC12B Analog-to-Digital-Converter 12bits */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Adc12b hardware registers */
+typedef struct {
+  WoReg ADC12B_CR;     /**< \brief (Adc12b Offset: 0x00) Control Register */
+  RwReg ADC12B_MR;     /**< \brief (Adc12b Offset: 0x04) Mode Register */
+  RoReg Reserved1[2];
+  WoReg ADC12B_CHER;   /**< \brief (Adc12b Offset: 0x10) Channel Enable Register */
+  WoReg ADC12B_CHDR;   /**< \brief (Adc12b Offset: 0x14) Channel Disable Register */
+  RoReg ADC12B_CHSR;   /**< \brief (Adc12b Offset: 0x18) Channel Status Register */
+  RoReg ADC12B_SR;     /**< \brief (Adc12b Offset: 0x1C) Status Register */
+  RoReg ADC12B_LCDR;   /**< \brief (Adc12b Offset: 0x20) Last Converted Data Register */
+  WoReg ADC12B_IER;    /**< \brief (Adc12b Offset: 0x24) Interrupt Enable Register */
+  WoReg ADC12B_IDR;    /**< \brief (Adc12b Offset: 0x28) Interrupt Disable Register */
+  RoReg ADC12B_IMR;    /**< \brief (Adc12b Offset: 0x2C) Interrupt Mask Register */
+  RoReg ADC12B_CDR[8]; /**< \brief (Adc12b Offset: 0x30) Channel Data Register */
+  RoReg Reserved2[5];
+  RwReg ADC12B_ACR;    /**< \brief (Adc12b Offset: 0x64) Analog Control Register */
+  RwReg ADC12B_EMR;    /**< \brief (Adc12b Offset: 0x68) Extended Mode Register */
+  RoReg Reserved3[37];
+  RwReg ADC12B_RPR;    /**< \brief (Adc12b Offset: 0x100) Receive Pointer Register */
+  RwReg ADC12B_RCR;    /**< \brief (Adc12b Offset: 0x104) Receive Counter Register */
+  RwReg ADC12B_TPR;    /**< \brief (Adc12b Offset: 0x108) Transmit Pointer Register */
+  RwReg ADC12B_TCR;    /**< \brief (Adc12b Offset: 0x10C) Transmit Counter Register */
+  RwReg ADC12B_RNPR;   /**< \brief (Adc12b Offset: 0x110) Receive Next Pointer Register */
+  RwReg ADC12B_RNCR;   /**< \brief (Adc12b Offset: 0x114) Receive Next Counter Register */
+  RwReg ADC12B_TNPR;   /**< \brief (Adc12b Offset: 0x118) Transmit Next Pointer Register */
+  RwReg ADC12B_TNCR;   /**< \brief (Adc12b Offset: 0x11C) Transmit Next Counter Register */
+  WoReg ADC12B_PTCR;   /**< \brief (Adc12b Offset: 0x120) Transfer Control Register */
+  RoReg ADC12B_PTSR;   /**< \brief (Adc12b Offset: 0x124) Transfer Status Register */
+} Adc12b;
+#endif /* __ASSEMBLY__ */
+/* -------- ADC12B_CR : (ADC12B Offset: 0x00) Control Register -------- */
+#define ADC12B_CR_SWRST (0x1u << 0) /**< \brief (ADC12B_CR) Software Reset */
+#define ADC12B_CR_START (0x1u << 1) /**< \brief (ADC12B_CR) Start Conversion */
+/* -------- ADC12B_MR : (ADC12B Offset: 0x04) Mode Register -------- */
+#define ADC12B_MR_TRGEN (0x1u << 0) /**< \brief (ADC12B_MR) Trigger Enable */
+#define ADC12B_MR_TRGSEL_Pos 1
+#define ADC12B_MR_TRGSEL_Msk (0x7u << ADC12B_MR_TRGSEL_Pos) /**< \brief (ADC12B_MR) Trigger Selection */
+#define ADC12B_MR_TRGSEL(value) ((ADC12B_MR_TRGSEL_Msk & ((value) << ADC12B_MR_TRGSEL_Pos)))
+#define ADC12B_MR_LOWRES (0x1u << 4) /**< \brief (ADC12B_MR) Resolution */
+#define   ADC12B_MR_LOWRES_BITS_12 (0x0u << 4) /**< \brief (ADC12B_MR) 10-bit resolution */
+#define   ADC12B_MR_LOWRES_BITS_10 (0x1u << 4) /**< \brief (ADC12B_MR) 8-bit resolution */
+#define ADC12B_MR_SLEEP (0x1u << 5) /**< \brief (ADC12B_MR) Sleep Mode */
+#define ADC12B_MR_PRESCAL_Pos 8
+#define ADC12B_MR_PRESCAL_Msk (0xffu << ADC12B_MR_PRESCAL_Pos) /**< \brief (ADC12B_MR) Prescaler Rate Selection */
+#define ADC12B_MR_PRESCAL(value) ((ADC12B_MR_PRESCAL_Msk & ((value) << ADC12B_MR_PRESCAL_Pos)))
+#define ADC12B_MR_STARTUP_Pos 16
+#define ADC12B_MR_STARTUP_Msk (0xffu << ADC12B_MR_STARTUP_Pos) /**< \brief (ADC12B_MR) Start Up Time */
+#define ADC12B_MR_STARTUP(value) ((ADC12B_MR_STARTUP_Msk & ((value) << ADC12B_MR_STARTUP_Pos)))
+#define ADC12B_MR_SHTIM_Pos 24
+#define ADC12B_MR_SHTIM_Msk (0xfu << ADC12B_MR_SHTIM_Pos) /**< \brief (ADC12B_MR) Sample & Hold Time */
+#define ADC12B_MR_SHTIM(value) ((ADC12B_MR_SHTIM_Msk & ((value) << ADC12B_MR_SHTIM_Pos)))
+/* -------- ADC12B_CHER : (ADC12B Offset: 0x10) Channel Enable Register -------- */
+#define ADC12B_CHER_CH0 (0x1u << 0) /**< \brief (ADC12B_CHER) Channel 0 Enable */
+#define ADC12B_CHER_CH1 (0x1u << 1) /**< \brief (ADC12B_CHER) Channel 1 Enable */
+#define ADC12B_CHER_CH2 (0x1u << 2) /**< \brief (ADC12B_CHER) Channel 2 Enable */
+#define ADC12B_CHER_CH3 (0x1u << 3) /**< \brief (ADC12B_CHER) Channel 3 Enable */
+#define ADC12B_CHER_CH4 (0x1u << 4) /**< \brief (ADC12B_CHER) Channel 4 Enable */
+#define ADC12B_CHER_CH5 (0x1u << 5) /**< \brief (ADC12B_CHER) Channel 5 Enable */
+#define ADC12B_CHER_CH6 (0x1u << 6) /**< \brief (ADC12B_CHER) Channel 6 Enable */
+#define ADC12B_CHER_CH7 (0x1u << 7) /**< \brief (ADC12B_CHER) Channel 7 Enable */
+/* -------- ADC12B_CHDR : (ADC12B Offset: 0x14) Channel Disable Register -------- */
+#define ADC12B_CHDR_CH0 (0x1u << 0) /**< \brief (ADC12B_CHDR)  */
+#define ADC12B_CHDR_CH1 (0x1u << 1) /**< \brief (ADC12B_CHDR)  */
+#define ADC12B_CHDR_CH2 (0x1u << 2) /**< \brief (ADC12B_CHDR)  */
+#define ADC12B_CHDR_CH3 (0x1u << 3) /**< \brief (ADC12B_CHDR)  */
+#define ADC12B_CHDR_CH4 (0x1u << 4) /**< \brief (ADC12B_CHDR)  */
+#define ADC12B_CHDR_CH5 (0x1u << 5) /**< \brief (ADC12B_CHDR)  */
+#define ADC12B_CHDR_CH6 (0x1u << 6) /**< \brief (ADC12B_CHDR)  */
+#define ADC12B_CHDR_CH7 (0x1u << 7) /**< \brief (ADC12B_CHDR)  */
+/* -------- ADC12B_CHSR : (ADC12B Offset: 0x18) Channel Status Register -------- */
+#define ADC12B_CHSR_CH0 (0x1u << 0) /**< \brief (ADC12B_CHSR) Channel 0 Status */
+#define ADC12B_CHSR_CH1 (0x1u << 1) /**< \brief (ADC12B_CHSR) Channel 1 Status */
+#define ADC12B_CHSR_CH2 (0x1u << 2) /**< \brief (ADC12B_CHSR) Channel 2 Status */
+#define ADC12B_CHSR_CH3 (0x1u << 3) /**< \brief (ADC12B_CHSR) Channel 3 Status */
+#define ADC12B_CHSR_CH4 (0x1u << 4) /**< \brief (ADC12B_CHSR) Channel 4 Status */
+#define ADC12B_CHSR_CH5 (0x1u << 5) /**< \brief (ADC12B_CHSR) Channel 5 Status */
+#define ADC12B_CHSR_CH6 (0x1u << 6) /**< \brief (ADC12B_CHSR) Channel 6 Status */
+#define ADC12B_CHSR_CH7 (0x1u << 7) /**< \brief (ADC12B_CHSR) Channel 7 Status */
+/* -------- ADC12B_SR : (ADC12B Offset: 0x1C) Status Register -------- */
+#define ADC12B_SR_EOC0 (0x1u << 0) /**< \brief (ADC12B_SR) End of Conversion 0 */
+#define ADC12B_SR_EOC1 (0x1u << 1) /**< \brief (ADC12B_SR) End of Conversion 1 */
+#define ADC12B_SR_EOC2 (0x1u << 2) /**< \brief (ADC12B_SR) End of Conversion 2 */
+#define ADC12B_SR_EOC3 (0x1u << 3) /**< \brief (ADC12B_SR) End of Conversion 3 */
+#define ADC12B_SR_EOC4 (0x1u << 4) /**< \brief (ADC12B_SR) End of Conversion 4 */
+#define ADC12B_SR_EOC5 (0x1u << 5) /**< \brief (ADC12B_SR) End of Conversion 5 */
+#define ADC12B_SR_EOC6 (0x1u << 6) /**< \brief (ADC12B_SR) End of Conversion 6 */
+#define ADC12B_SR_EOC7 (0x1u << 7) /**< \brief (ADC12B_SR) End of Conversion 7 */
+#define ADC12B_SR_OVRE0 (0x1u << 8) /**< \brief (ADC12B_SR) Overrun Error 0 */
+#define ADC12B_SR_OVRE1 (0x1u << 9) /**< \brief (ADC12B_SR) Overrun Error 1 */
+#define ADC12B_SR_OVRE2 (0x1u << 10) /**< \brief (ADC12B_SR) Overrun Error 2 */
+#define ADC12B_SR_OVRE3 (0x1u << 11) /**< \brief (ADC12B_SR) Overrun Error 3 */
+#define ADC12B_SR_OVRE4 (0x1u << 12) /**< \brief (ADC12B_SR) Overrun Error 4 */
+#define ADC12B_SR_OVRE5 (0x1u << 13) /**< \brief (ADC12B_SR) Overrun Error 5 */
+#define ADC12B_SR_OVRE6 (0x1u << 14) /**< \brief (ADC12B_SR) Overrun Error 6 */
+#define ADC12B_SR_OVRE7 (0x1u << 15) /**< \brief (ADC12B_SR) Overrun Error 7 */
+#define ADC12B_SR_DRDY (0x1u << 16) /**< \brief (ADC12B_SR) Data Ready */
+#define ADC12B_SR_GOVRE (0x1u << 17) /**< \brief (ADC12B_SR) General Overrun Error */
+#define ADC12B_SR_ENDRX (0x1u << 18) /**< \brief (ADC12B_SR) End of RX Buffer */
+#define ADC12B_SR_RXBUFF (0x1u << 19) /**< \brief (ADC12B_SR) RX Buffer Full */
+/* -------- ADC12B_LCDR : (ADC12B Offset: 0x20) Last Converted Data Register -------- */
+#define ADC12B_LCDR_LDATA_Pos 0
+#define ADC12B_LCDR_LDATA_Msk (0xfffu << ADC12B_LCDR_LDATA_Pos) /**< \brief (ADC12B_LCDR) Last Data Converted */
+/* -------- ADC12B_IER : (ADC12B Offset: 0x24) Interrupt Enable Register -------- */
+#define ADC12B_IER_EOC0 (0x1u << 0) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 0 */
+#define ADC12B_IER_EOC1 (0x1u << 1) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 1 */
+#define ADC12B_IER_EOC2 (0x1u << 2) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 2 */
+#define ADC12B_IER_EOC3 (0x1u << 3) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 3 */
+#define ADC12B_IER_EOC4 (0x1u << 4) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 4 */
+#define ADC12B_IER_EOC5 (0x1u << 5) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 5 */
+#define ADC12B_IER_EOC6 (0x1u << 6) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 6 */
+#define ADC12B_IER_EOC7 (0x1u << 7) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 7 */
+#define ADC12B_IER_OVRE0 (0x1u << 8) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 0 */
+#define ADC12B_IER_OVRE1 (0x1u << 9) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 1 */
+#define ADC12B_IER_OVRE2 (0x1u << 10) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 2 */
+#define ADC12B_IER_OVRE3 (0x1u << 11) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 3 */
+#define ADC12B_IER_OVRE4 (0x1u << 12) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 4 */
+#define ADC12B_IER_OVRE5 (0x1u << 13) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 5 */
+#define ADC12B_IER_OVRE6 (0x1u << 14) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 6 */
+#define ADC12B_IER_OVRE7 (0x1u << 15) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 7 */
+#define ADC12B_IER_DRDY (0x1u << 16) /**< \brief (ADC12B_IER) Data Ready Interrupt Enable */
+#define ADC12B_IER_GOVRE (0x1u << 17) /**< \brief (ADC12B_IER) General Overrun Error Interrupt Enable */
+#define ADC12B_IER_ENDRX (0x1u << 18) /**< \brief (ADC12B_IER) End of Receive Buffer Interrupt Enable */
+#define ADC12B_IER_RXBUFF (0x1u << 19) /**< \brief (ADC12B_IER) Receive Buffer Full Interrupt Enable */
+/* -------- ADC12B_IDR : (ADC12B Offset: 0x28) Interrupt Disable Register -------- */
+#define ADC12B_IDR_EOC0 (0x1u << 0) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 0 */
+#define ADC12B_IDR_EOC1 (0x1u << 1) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 1 */
+#define ADC12B_IDR_EOC2 (0x1u << 2) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 2 */
+#define ADC12B_IDR_EOC3 (0x1u << 3) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 3 */
+#define ADC12B_IDR_EOC4 (0x1u << 4) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 4 */
+#define ADC12B_IDR_EOC5 (0x1u << 5) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 5 */
+#define ADC12B_IDR_EOC6 (0x1u << 6) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 6 */
+#define ADC12B_IDR_EOC7 (0x1u << 7) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 7 */
+#define ADC12B_IDR_OVRE0 (0x1u << 8) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 0 */
+#define ADC12B_IDR_OVRE1 (0x1u << 9) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 1 */
+#define ADC12B_IDR_OVRE2 (0x1u << 10) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 2 */
+#define ADC12B_IDR_OVRE3 (0x1u << 11) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 3 */
+#define ADC12B_IDR_OVRE4 (0x1u << 12) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 4 */
+#define ADC12B_IDR_OVRE5 (0x1u << 13) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 5 */
+#define ADC12B_IDR_OVRE6 (0x1u << 14) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 6 */
+#define ADC12B_IDR_OVRE7 (0x1u << 15) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 7 */
+#define ADC12B_IDR_DRDY (0x1u << 16) /**< \brief (ADC12B_IDR) Data Ready Interrupt Disable */
+#define ADC12B_IDR_GOVRE (0x1u << 17) /**< \brief (ADC12B_IDR) General Overrun Error Interrupt Disable */
+#define ADC12B_IDR_ENDRX (0x1u << 18) /**< \brief (ADC12B_IDR) End of Receive Buffer Interrupt Disable */
+#define ADC12B_IDR_RXBUFF (0x1u << 19) /**< \brief (ADC12B_IDR) Receive Buffer Full Interrupt Disable */
+/* -------- ADC12B_IMR : (ADC12B Offset: 0x2C) Interrupt Mask Register -------- */
+#define ADC12B_IMR_EOC0 (0x1u << 0) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 0 */
+#define ADC12B_IMR_EOC1 (0x1u << 1) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 1 */
+#define ADC12B_IMR_EOC2 (0x1u << 2) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 2 */
+#define ADC12B_IMR_EOC3 (0x1u << 3) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 3 */
+#define ADC12B_IMR_EOC4 (0x1u << 4) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 4 */
+#define ADC12B_IMR_EOC5 (0x1u << 5) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 5 */
+#define ADC12B_IMR_EOC6 (0x1u << 6) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 6 */
+#define ADC12B_IMR_EOC7 (0x1u << 7) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 7 */
+#define ADC12B_IMR_OVRE0 (0x1u << 8) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 0 */
+#define ADC12B_IMR_OVRE1 (0x1u << 9) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 1 */
+#define ADC12B_IMR_OVRE2 (0x1u << 10) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 2 */
+#define ADC12B_IMR_OVRE3 (0x1u << 11) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 3 */
+#define ADC12B_IMR_OVRE4 (0x1u << 12) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 4 */
+#define ADC12B_IMR_OVRE5 (0x1u << 13) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 5 */
+#define ADC12B_IMR_OVRE6 (0x1u << 14) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 6 */
+#define ADC12B_IMR_OVRE7 (0x1u << 15) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 7 */
+#define ADC12B_IMR_DRDY (0x1u << 16) /**< \brief (ADC12B_IMR) Data Ready Interrupt Mask */
+#define ADC12B_IMR_GOVRE (0x1u << 17) /**< \brief (ADC12B_IMR) General Overrun Error Interrupt Mask */
+#define ADC12B_IMR_ENDRX (0x1u << 18) /**< \brief (ADC12B_IMR) End of Receive Buffer Interrupt Mask */
+#define ADC12B_IMR_RXBUFF (0x1u << 19) /**< \brief (ADC12B_IMR) Receive Buffer Full Interrupt Mask */
+/* -------- ADC12B_CDR[8] : (ADC12B Offset: 0x30) Channel Data Register -------- */
+#define ADC12B_CDR_DATA_Pos 0
+#define ADC12B_CDR_DATA_Msk (0xfffu << ADC12B_CDR_DATA_Pos) /**< \brief (ADC12B_CDR[8]) Converted Data */
+/* -------- ADC12B_ACR : (ADC12B Offset: 0x64) Analog Control Register -------- */
+#define ADC12B_ACR_GAIN_Pos 0
+#define ADC12B_ACR_GAIN_Msk (0x3u << ADC12B_ACR_GAIN_Pos) /**< \brief (ADC12B_ACR) Input Gain */
+#define ADC12B_ACR_GAIN(value) ((ADC12B_ACR_GAIN_Msk & ((value) << ADC12B_ACR_GAIN_Pos)))
+#define ADC12B_ACR_IBCTL_Pos 8
+#define ADC12B_ACR_IBCTL_Msk (0x3u << ADC12B_ACR_IBCTL_Pos) /**< \brief (ADC12B_ACR) Bias Current Control */
+#define ADC12B_ACR_IBCTL(value) ((ADC12B_ACR_IBCTL_Msk & ((value) << ADC12B_ACR_IBCTL_Pos)))
+#define ADC12B_ACR_DIFF (0x1u << 16) /**< \brief (ADC12B_ACR) Differential Mode */
+#define ADC12B_ACR_OFFSET (0x1u << 17) /**< \brief (ADC12B_ACR) Input OFFSET */
+/* -------- ADC12B_EMR : (ADC12B Offset: 0x68) Extended Mode Register -------- */
+#define ADC12B_EMR_OFFMODES (0x1u << 0) /**< \brief (ADC12B_EMR) Off Mode if Sleep Bit (ADC12B_MR) = 1 */
+#define ADC12B_EMR_OFF_MODE_STARTUP_TIME_Pos 16
+#define ADC12B_EMR_OFF_MODE_STARTUP_TIME_Msk (0xffu << ADC12B_EMR_OFF_MODE_STARTUP_TIME_Pos) /**< \brief (ADC12B_EMR) Startup Time */
+#define ADC12B_EMR_OFF_MODE_STARTUP_TIME(value) ((ADC12B_EMR_OFF_MODE_STARTUP_TIME_Msk & ((value) << ADC12B_EMR_OFF_MODE_STARTUP_TIME_Pos)))
+/* -------- ADC12B_RPR : (ADC12B Offset: 0x100) Receive Pointer Register -------- */
+#define ADC12B_RPR_RXPTR_Pos 0
+#define ADC12B_RPR_RXPTR_Msk (0xffffffffu << ADC12B_RPR_RXPTR_Pos) /**< \brief (ADC12B_RPR) Receive Pointer Register */
+#define ADC12B_RPR_RXPTR(value) ((ADC12B_RPR_RXPTR_Msk & ((value) << ADC12B_RPR_RXPTR_Pos)))
+/* -------- ADC12B_RCR : (ADC12B Offset: 0x104) Receive Counter Register -------- */
+#define ADC12B_RCR_RXCTR_Pos 0
+#define ADC12B_RCR_RXCTR_Msk (0xffffu << ADC12B_RCR_RXCTR_Pos) /**< \brief (ADC12B_RCR) Receive Counter Register */
+#define ADC12B_RCR_RXCTR(value) ((ADC12B_RCR_RXCTR_Msk & ((value) << ADC12B_RCR_RXCTR_Pos)))
+/* -------- ADC12B_TPR : (ADC12B Offset: 0x108) Transmit Pointer Register -------- */
+#define ADC12B_TPR_TXPTR_Pos 0
+#define ADC12B_TPR_TXPTR_Msk (0xffffffffu << ADC12B_TPR_TXPTR_Pos) /**< \brief (ADC12B_TPR) Transmit Counter Register */
+#define ADC12B_TPR_TXPTR(value) ((ADC12B_TPR_TXPTR_Msk & ((value) << ADC12B_TPR_TXPTR_Pos)))
+/* -------- ADC12B_TCR : (ADC12B Offset: 0x10C) Transmit Counter Register -------- */
+#define ADC12B_TCR_TXCTR_Pos 0
+#define ADC12B_TCR_TXCTR_Msk (0xffffu << ADC12B_TCR_TXCTR_Pos) /**< \brief (ADC12B_TCR) Transmit Counter Register */
+#define ADC12B_TCR_TXCTR(value) ((ADC12B_TCR_TXCTR_Msk & ((value) << ADC12B_TCR_TXCTR_Pos)))
+/* -------- ADC12B_RNPR : (ADC12B Offset: 0x110) Receive Next Pointer Register -------- */
+#define ADC12B_RNPR_RXNPTR_Pos 0
+#define ADC12B_RNPR_RXNPTR_Msk (0xffffffffu << ADC12B_RNPR_RXNPTR_Pos) /**< \brief (ADC12B_RNPR) Receive Next Pointer */
+#define ADC12B_RNPR_RXNPTR(value) ((ADC12B_RNPR_RXNPTR_Msk & ((value) << ADC12B_RNPR_RXNPTR_Pos)))
+/* -------- ADC12B_RNCR : (ADC12B Offset: 0x114) Receive Next Counter Register -------- */
+#define ADC12B_RNCR_RXNCTR_Pos 0
+#define ADC12B_RNCR_RXNCTR_Msk (0xffffu << ADC12B_RNCR_RXNCTR_Pos) /**< \brief (ADC12B_RNCR) Receive Next Counter */
+#define ADC12B_RNCR_RXNCTR(value) ((ADC12B_RNCR_RXNCTR_Msk & ((value) << ADC12B_RNCR_RXNCTR_Pos)))
+/* -------- ADC12B_TNPR : (ADC12B Offset: 0x118) Transmit Next Pointer Register -------- */
+#define ADC12B_TNPR_TXNPTR_Pos 0
+#define ADC12B_TNPR_TXNPTR_Msk (0xffffffffu << ADC12B_TNPR_TXNPTR_Pos) /**< \brief (ADC12B_TNPR) Transmit Next Pointer */
+#define ADC12B_TNPR_TXNPTR(value) ((ADC12B_TNPR_TXNPTR_Msk & ((value) << ADC12B_TNPR_TXNPTR_Pos)))
+/* -------- ADC12B_TNCR : (ADC12B Offset: 0x11C) Transmit Next Counter Register -------- */
+#define ADC12B_TNCR_TXNCTR_Pos 0
+#define ADC12B_TNCR_TXNCTR_Msk (0xffffu << ADC12B_TNCR_TXNCTR_Pos) /**< \brief (ADC12B_TNCR) Transmit Counter Next */
+#define ADC12B_TNCR_TXNCTR(value) ((ADC12B_TNCR_TXNCTR_Msk & ((value) << ADC12B_TNCR_TXNCTR_Pos)))
+/* -------- ADC12B_PTCR : (ADC12B Offset: 0x120) Transfer Control Register -------- */
+#define ADC12B_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC12B_PTCR) Receiver Transfer Enable */
+#define ADC12B_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC12B_PTCR) Receiver Transfer Disable */
+#define ADC12B_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC12B_PTCR) Transmitter Transfer Enable */
+#define ADC12B_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC12B_PTCR) Transmitter Transfer Disable */
+/* -------- ADC12B_PTSR : (ADC12B Offset: 0x124) Transfer Status Register -------- */
+#define ADC12B_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC12B_PTSR) Receiver Transfer Enable */
+#define ADC12B_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC12B_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3U_ADC12B_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_chipid.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_chipid.h
new file mode 100644
index 000000000..19949240b
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_chipid.h
@@ -0,0 +1,159 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_CHIPID_COMPONENT_
+#define _SAM3U_CHIPID_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Chip Identifier */
+/* ============================================================================= */
+/** \addtogroup SAM3U_CHIPID Chip Identifier */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Chipid hardware registers */
+typedef struct {
+  RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */
+  RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */
+} Chipid;
+#endif /* __ASSEMBLY__ */
+/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */
+#define CHIPID_CIDR_VERSION_Pos 0
+#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */
+#define CHIPID_CIDR_EPROC_Pos 5
+#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */
+#define   CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */
+#define   CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */
+#define   CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */
+#define   CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */
+#define   CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */
+#define   CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */
+#define   CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */
+#define CHIPID_CIDR_NVPSIZ_Pos 8
+#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */
+#define   CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */
+#define   CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define   CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define   CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_NVPSIZ2_Pos 12
+#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */
+#define   CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */
+#define   CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_SRAMSIZ_Pos 16
+#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */
+#define   CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_1K (0x1u << 16) /**< \brief (CHIPID_CIDR) 1K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define CHIPID_CIDR_ARCH_Pos 20
+#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */
+#define   CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */
+#define   CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */
+#define   CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */
+#define   CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */
+#define   CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */
+#define   CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */
+#define   CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */
+#define   CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */
+#define   CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */
+#define   CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM4AxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM4XxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM4XxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxG Series (208/217-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM4XxG Series (208/217-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM3SxASeries (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM4SxA Series (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM3SxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM4SxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM3SxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM4SxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */
+#define   CHIPID_CIDR_ARCH_SAM3NxA (0x93u << 20) /**< \brief (CHIPID_CIDR) SAM3NxA Series (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3NxB (0x94u << 20) /**< \brief (CHIPID_CIDR) SAM3NxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3NxC (0x95u << 20) /**< \brief (CHIPID_CIDR) SAM3NxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */
+#define   CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */
+#define CHIPID_CIDR_NVPTYP_Pos 28
+#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */
+#define   CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */
+#define   CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */
+#define   CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */
+#define   CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size      NVPSIZ2 is Flash size */
+#define   CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */
+#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */
+/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */
+#define CHIPID_EXID_EXID_Pos 0
+#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */
+
+/*@}*/
+
+
+#endif /* _SAM3U_CHIPID_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_dmac.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_dmac.h
new file mode 100644
index 000000000..c15eafe73
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_dmac.h
@@ -0,0 +1,249 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_DMAC_COMPONENT_
+#define _SAM3U_DMAC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR DMA Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_DMAC DMA Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief DmacCh_num hardware registers */
+typedef struct {
+  RwReg       DMAC_SADDR;     /**< \brief (DmacCh_num Offset: 0x0) DMAC Channel Source Address Register */
+  RwReg       DMAC_DADDR;     /**< \brief (DmacCh_num Offset: 0x4) DMAC Channel Destination Address Register */
+  RwReg       DMAC_DSCR;      /**< \brief (DmacCh_num Offset: 0x8) DMAC Channel Descriptor Address Register */
+  RwReg       DMAC_CTRLA;     /**< \brief (DmacCh_num Offset: 0xC) DMAC Channel Control A Register */
+  RwReg       DMAC_CTRLB;     /**< \brief (DmacCh_num Offset: 0x10) DMAC Channel Control B Register */
+  RwReg       DMAC_CFG;       /**< \brief (DmacCh_num Offset: 0x14) DMAC Channel Configuration Register */
+  RoReg       Reserved1[4];
+} DmacCh_num;
+/** \brief Dmac hardware registers */
+#define DMACCH_NUM_NUMBER 4
+typedef struct {
+  RwReg       DMAC_GCFG;      /**< \brief (Dmac Offset: 0x000) DMAC Global Configuration Register */
+  RwReg       DMAC_EN;        /**< \brief (Dmac Offset: 0x004) DMAC Enable Register */
+  RwReg       DMAC_SREQ;      /**< \brief (Dmac Offset: 0x008) DMAC Software Single Request Register */
+  RwReg       DMAC_CREQ;      /**< \brief (Dmac Offset: 0x00C) DMAC Software Chunk Transfer Request Register */
+  RwReg       DMAC_LAST;      /**< \brief (Dmac Offset: 0x010) DMAC Software Last Transfer Flag Register */
+  RoReg       Reserved1[1];
+  WoReg       DMAC_EBCIER;    /**< \brief (Dmac Offset: 0x018) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register. */
+  WoReg       DMAC_EBCIDR;    /**< \brief (Dmac Offset: 0x01C) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register. */
+  RoReg       DMAC_EBCIMR;    /**< \brief (Dmac Offset: 0x020) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register. */
+  RoReg       DMAC_EBCISR;    /**< \brief (Dmac Offset: 0x024) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Status Register. */
+  WoReg       DMAC_CHER;      /**< \brief (Dmac Offset: 0x028) DMAC Channel Handler Enable Register */
+  WoReg       DMAC_CHDR;      /**< \brief (Dmac Offset: 0x02C) DMAC Channel Handler Disable Register */
+  RoReg       DMAC_CHSR;      /**< \brief (Dmac Offset: 0x030) DMAC Channel Handler Status Register */
+  RoReg       Reserved2[2];
+  DmacCh_num  DMAC_CH_NUM[DMACCH_NUM_NUMBER]; /**< \brief (Dmac Offset: 0x3C) ch_num = 0 .. 3 */
+} Dmac;
+#endif /* __ASSEMBLY__ */
+/* -------- DMAC_GCFG : (DMAC Offset: 0x000) DMAC Global Configuration Register -------- */
+#define DMAC_GCFG_ARB_CFG (0x1u << 4) /**< \brief (DMAC_GCFG)  */
+/* -------- DMAC_EN : (DMAC Offset: 0x004) DMAC Enable Register -------- */
+#define DMAC_EN_ENABLE (0x1u << 0) /**< \brief (DMAC_EN)  */
+/* -------- DMAC_SREQ : (DMAC Offset: 0x008) DMAC Software Single Request Register -------- */
+#define DMAC_SREQ_SSREQ0 (0x1u << 0) /**< \brief (DMAC_SREQ)  */
+#define DMAC_SREQ_DSREQ0 (0x1u << 1) /**< \brief (DMAC_SREQ)  */
+#define DMAC_SREQ_SSREQ1 (0x1u << 2) /**< \brief (DMAC_SREQ)  */
+#define DMAC_SREQ_DSREQ1 (0x1u << 3) /**< \brief (DMAC_SREQ)  */
+#define DMAC_SREQ_SSREQ3 (0x1u << 6) /**< \brief (DMAC_SREQ)  */
+#define DMAC_SREQ_DSREQ3 (0x1u << 7) /**< \brief (DMAC_SREQ)  */
+/* -------- DMAC_CREQ : (DMAC Offset: 0x00C) DMAC Software Chunk Transfer Request Register -------- */
+#define DMAC_CREQ_SCREQ0 (0x1u << 0) /**< \brief (DMAC_CREQ)  */
+#define DMAC_CREQ_DCREQ0 (0x1u << 1) /**< \brief (DMAC_CREQ)  */
+#define DMAC_CREQ_SCREQ1 (0x1u << 2) /**< \brief (DMAC_CREQ)  */
+#define DMAC_CREQ_DCREQ1 (0x1u << 3) /**< \brief (DMAC_CREQ)  */
+#define DMAC_CREQ_SCREQ3 (0x1u << 6) /**< \brief (DMAC_CREQ)  */
+#define DMAC_CREQ_DCREQ3 (0x1u << 7) /**< \brief (DMAC_CREQ)  */
+/* -------- DMAC_LAST : (DMAC Offset: 0x010) DMAC Software Last Transfer Flag Register -------- */
+#define DMAC_LAST_SLAST0 (0x1u << 0) /**< \brief (DMAC_LAST)  */
+#define DMAC_LAST_DLAST0 (0x1u << 1) /**< \brief (DMAC_LAST)  */
+#define DMAC_LAST_SLAST1 (0x1u << 2) /**< \brief (DMAC_LAST)  */
+#define DMAC_LAST_DLAST1 (0x1u << 3) /**< \brief (DMAC_LAST)  */
+#define DMAC_LAST_SLAST2 (0x1u << 4) /**< \brief (DMAC_LAST)  */
+#define DMAC_LAST_DLAST2 (0x1u << 5) /**< \brief (DMAC_LAST)  */
+#define DMAC_LAST_SLAST3 (0x1u << 6) /**< \brief (DMAC_LAST)  */
+#define DMAC_LAST_DLAST3 (0x1u << 7) /**< \brief (DMAC_LAST)  */
+/* -------- DMAC_EBCIER : (DMAC Offset: 0x018) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register. -------- */
+#define DMAC_EBCIER_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIER)  */
+#define DMAC_EBCIER_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIER)  */
+#define DMAC_EBCIER_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIER)  */
+#define DMAC_EBCIER_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIER)  */
+#define DMAC_EBCIER_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIER)  */
+#define DMAC_EBCIER_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIER)  */
+#define DMAC_EBCIER_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIER)  */
+#define DMAC_EBCIER_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIER)  */
+#define DMAC_EBCIER_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIER)  */
+#define DMAC_EBCIER_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIER)  */
+#define DMAC_EBCIER_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIER)  */
+#define DMAC_EBCIER_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIER)  */
+/* -------- DMAC_EBCIDR : (DMAC Offset: 0x01C) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register. -------- */
+#define DMAC_EBCIDR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIDR)  */
+#define DMAC_EBCIDR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIDR)  */
+#define DMAC_EBCIDR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIDR)  */
+#define DMAC_EBCIDR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIDR)  */
+#define DMAC_EBCIDR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIDR)  */
+#define DMAC_EBCIDR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIDR)  */
+#define DMAC_EBCIDR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIDR)  */
+#define DMAC_EBCIDR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIDR)  */
+#define DMAC_EBCIDR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIDR)  */
+#define DMAC_EBCIDR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIDR)  */
+#define DMAC_EBCIDR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIDR)  */
+#define DMAC_EBCIDR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIDR)  */
+/* -------- DMAC_EBCIMR : (DMAC Offset: 0x020) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register. -------- */
+#define DMAC_EBCIMR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIMR)  */
+#define DMAC_EBCIMR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIMR)  */
+#define DMAC_EBCIMR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIMR)  */
+#define DMAC_EBCIMR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIMR)  */
+#define DMAC_EBCIMR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIMR)  */
+#define DMAC_EBCIMR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIMR)  */
+#define DMAC_EBCIMR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIMR)  */
+#define DMAC_EBCIMR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIMR)  */
+#define DMAC_EBCIMR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIMR)  */
+#define DMAC_EBCIMR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIMR)  */
+#define DMAC_EBCIMR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIMR)  */
+#define DMAC_EBCIMR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIMR)  */
+/* -------- DMAC_EBCISR : (DMAC Offset: 0x024) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Status Register. -------- */
+#define DMAC_EBCISR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCISR)  */
+#define DMAC_EBCISR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCISR)  */
+#define DMAC_EBCISR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCISR)  */
+#define DMAC_EBCISR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCISR)  */
+#define DMAC_EBCISR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCISR)  */
+#define DMAC_EBCISR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCISR)  */
+#define DMAC_EBCISR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCISR)  */
+#define DMAC_EBCISR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCISR)  */
+#define DMAC_EBCISR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCISR)  */
+#define DMAC_EBCISR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCISR)  */
+#define DMAC_EBCISR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCISR)  */
+#define DMAC_EBCISR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCISR)  */
+/* -------- DMAC_CHER : (DMAC Offset: 0x028) DMAC Channel Handler Enable Register -------- */
+#define DMAC_CHER_ENA0 (0x1u << 0) /**< \brief (DMAC_CHER)  */
+#define DMAC_CHER_ENA1 (0x1u << 1) /**< \brief (DMAC_CHER)  */
+#define DMAC_CHER_ENA2 (0x1u << 2) /**< \brief (DMAC_CHER)  */
+#define DMAC_CHER_ENA3 (0x1u << 3) /**< \brief (DMAC_CHER)  */
+#define DMAC_CHER_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHER)  */
+#define DMAC_CHER_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHER)  */
+#define DMAC_CHER_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHER)  */
+#define DMAC_CHER_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHER)  */
+#define DMAC_CHER_KEEP0 (0x1u << 24) /**< \brief (DMAC_CHER)  */
+#define DMAC_CHER_KEEP1 (0x1u << 25) /**< \brief (DMAC_CHER)  */
+#define DMAC_CHER_KEEP2 (0x1u << 26) /**< \brief (DMAC_CHER)  */
+#define DMAC_CHER_KEEP3 (0x1u << 27) /**< \brief (DMAC_CHER)  */
+/* -------- DMAC_CHDR : (DMAC Offset: 0x02C) DMAC Channel Handler Disable Register -------- */
+#define DMAC_CHDR_DIS0 (0x1u << 0) /**< \brief (DMAC_CHDR)  */
+#define DMAC_CHDR_DIS1 (0x1u << 1) /**< \brief (DMAC_CHDR)  */
+#define DMAC_CHDR_DIS2 (0x1u << 2) /**< \brief (DMAC_CHDR)  */
+#define DMAC_CHDR_DIS3 (0x1u << 3) /**< \brief (DMAC_CHDR)  */
+#define DMAC_CHDR_RES0 (0x1u << 8) /**< \brief (DMAC_CHDR)  */
+#define DMAC_CHDR_RES1 (0x1u << 9) /**< \brief (DMAC_CHDR)  */
+#define DMAC_CHDR_RES2 (0x1u << 10) /**< \brief (DMAC_CHDR)  */
+#define DMAC_CHDR_RES3 (0x1u << 11) /**< \brief (DMAC_CHDR)  */
+/* -------- DMAC_CHSR : (DMAC Offset: 0x030) DMAC Channel Handler Status Register -------- */
+#define DMAC_CHSR_ENA0 (0x1u << 0) /**< \brief (DMAC_CHSR)  */
+#define DMAC_CHSR_ENA1 (0x1u << 1) /**< \brief (DMAC_CHSR)  */
+#define DMAC_CHSR_ENA2 (0x1u << 2) /**< \brief (DMAC_CHSR)  */
+#define DMAC_CHSR_ENA3 (0x1u << 3) /**< \brief (DMAC_CHSR)  */
+#define DMAC_CHSR_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHSR)  */
+#define DMAC_CHSR_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHSR)  */
+#define DMAC_CHSR_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHSR)  */
+#define DMAC_CHSR_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHSR)  */
+#define DMAC_CHSR_EMPT0 (0x1u << 16) /**< \brief (DMAC_CHSR)  */
+#define DMAC_CHSR_EMPT1 (0x1u << 17) /**< \brief (DMAC_CHSR)  */
+#define DMAC_CHSR_EMPT2 (0x1u << 18) /**< \brief (DMAC_CHSR)  */
+#define DMAC_CHSR_EMPT3 (0x1u << 19) /**< \brief (DMAC_CHSR)  */
+#define DMAC_CHSR_STAL0 (0x1u << 24) /**< \brief (DMAC_CHSR)  */
+#define DMAC_CHSR_STAL1 (0x1u << 25) /**< \brief (DMAC_CHSR)  */
+#define DMAC_CHSR_STAL2 (0x1u << 26) /**< \brief (DMAC_CHSR)  */
+#define DMAC_CHSR_STAL3 (0x1u << 27) /**< \brief (DMAC_CHSR)  */
+/* -------- DMAC_SADDR : (DMAC Offset: N/A) DMAC Channel Source Address Register -------- */
+#define DMAC_SADDR_SADDRx_Pos 0
+#define DMAC_SADDR_SADDRx_Msk (0xffffffffu << DMAC_SADDR_SADDRx_Pos) /**< \brief (DMAC_SADDR)  */
+#define DMAC_SADDR_SADDRx(value) ((DMAC_SADDR_SADDRx_Msk & ((value) << DMAC_SADDR_SADDRx_Pos)))
+/* -------- DMAC_DADDR : (DMAC Offset: N/A) DMAC Channel Destination Address Register -------- */
+#define DMAC_DADDR_DADDRx_Pos 0
+#define DMAC_DADDR_DADDRx_Msk (0xffffffffu << DMAC_DADDR_DADDRx_Pos) /**< \brief (DMAC_DADDR)  */
+#define DMAC_DADDR_DADDRx(value) ((DMAC_DADDR_DADDRx_Msk & ((value) << DMAC_DADDR_DADDRx_Pos)))
+/* -------- DMAC_DSCR : (DMAC Offset: N/A) DMAC Channel Descriptor Address Register -------- */
+#define DMAC_DSCR_DSCRx_Pos 2
+#define DMAC_DSCR_DSCRx_Msk (0x3fffffffu << DMAC_DSCR_DSCRx_Pos) /**< \brief (DMAC_DSCR)  */
+#define DMAC_DSCR_DSCRx(value) ((DMAC_DSCR_DSCRx_Msk & ((value) << DMAC_DSCR_DSCRx_Pos)))
+/* -------- DMAC_CTRLA : (DMAC Offset: N/A) DMAC Channel Control A Register -------- */
+#define DMAC_CTRLA_BTSIZE_Pos 0
+#define DMAC_CTRLA_BTSIZE_Msk (0xfffu << DMAC_CTRLA_BTSIZE_Pos) /**< \brief (DMAC_CTRLA)  */
+#define DMAC_CTRLA_BTSIZE(value) ((DMAC_CTRLA_BTSIZE_Msk & ((value) << DMAC_CTRLA_BTSIZE_Pos)))
+#define DMAC_CTRLA_SCSIZE (0x1u << 16) /**< \brief (DMAC_CTRLA)  */
+#define DMAC_CTRLA_DCSIZE (0x1u << 20) /**< \brief (DMAC_CTRLA)  */
+#define DMAC_CTRLA_SRC_WIDTH_Pos 24
+#define DMAC_CTRLA_SRC_WIDTH_Msk (0x3u << DMAC_CTRLA_SRC_WIDTH_Pos) /**< \brief (DMAC_CTRLA)  */
+#define DMAC_CTRLA_SRC_WIDTH(value) ((DMAC_CTRLA_SRC_WIDTH_Msk & ((value) << DMAC_CTRLA_SRC_WIDTH_Pos)))
+#define DMAC_CTRLA_DST_WIDTH_Pos 28
+#define DMAC_CTRLA_DST_WIDTH_Msk (0x3u << DMAC_CTRLA_DST_WIDTH_Pos) /**< \brief (DMAC_CTRLA)  */
+#define DMAC_CTRLA_DST_WIDTH(value) ((DMAC_CTRLA_DST_WIDTH_Msk & ((value) << DMAC_CTRLA_DST_WIDTH_Pos)))
+#define DMAC_CTRLA_DONE (0x1u << 31) /**< \brief (DMAC_CTRLA)  */
+/* -------- DMAC_CTRLB : (DMAC Offset: N/A) DMAC Channel Control B Register -------- */
+#define DMAC_CTRLB_SRC_DSCR (0x1u << 16) /**< \brief (DMAC_CTRLB)  */
+#define DMAC_CTRLB_DST_DSCR (0x1u << 20) /**< \brief (DMAC_CTRLB)  */
+#define DMAC_CTRLB_FC_Pos 21
+#define DMAC_CTRLB_FC_Msk (0x3u << DMAC_CTRLB_FC_Pos) /**< \brief (DMAC_CTRLB)  */
+#define DMAC_CTRLB_FC(value) ((DMAC_CTRLB_FC_Msk & ((value) << DMAC_CTRLB_FC_Pos)))
+#define DMAC_CTRLB_SRC_INCR_Pos 24
+#define DMAC_CTRLB_SRC_INCR_Msk (0x3u << DMAC_CTRLB_SRC_INCR_Pos) /**< \brief (DMAC_CTRLB)  */
+#define DMAC_CTRLB_SRC_INCR(value) ((DMAC_CTRLB_SRC_INCR_Msk & ((value) << DMAC_CTRLB_SRC_INCR_Pos)))
+#define DMAC_CTRLB_DST_INCR_Pos 28
+#define DMAC_CTRLB_DST_INCR_Msk (0x3u << DMAC_CTRLB_DST_INCR_Pos) /**< \brief (DMAC_CTRLB)  */
+#define DMAC_CTRLB_DST_INCR(value) ((DMAC_CTRLB_DST_INCR_Msk & ((value) << DMAC_CTRLB_DST_INCR_Pos)))
+#define DMAC_CTRLB_IEN (0x1u << 30) /**< \brief (DMAC_CTRLB)  */
+/* -------- DMAC_CFG : (DMAC Offset: N/A) DMAC Channel Configuration Register -------- */
+#define DMAC_CFG_SRC_PER_Pos 0
+#define DMAC_CFG_SRC_PER_Msk (0xfu << DMAC_CFG_SRC_PER_Pos) /**< \brief (DMAC_CFG)  */
+#define DMAC_CFG_SRC_PER(value) ((DMAC_CFG_SRC_PER_Msk & ((value) << DMAC_CFG_SRC_PER_Pos)))
+#define DMAC_CFG_DST_PER_Pos 4
+#define DMAC_CFG_DST_PER_Msk (0xfu << DMAC_CFG_DST_PER_Pos) /**< \brief (DMAC_CFG)  */
+#define DMAC_CFG_DST_PER(value) ((DMAC_CFG_DST_PER_Msk & ((value) << DMAC_CFG_DST_PER_Pos)))
+#define DMAC_CFG_SRC_H2SEL (0x1u << 9) /**< \brief (DMAC_CFG)  */
+#define DMAC_CFG_DST_H2SEL (0x1u << 13) /**< \brief (DMAC_CFG)  */
+#define DMAC_CFG_SOD (0x1u << 16) /**< \brief (DMAC_CFG)  */
+#define DMAC_CFG_LOCK_IF (0x1u << 20) /**< \brief (DMAC_CFG)  */
+#define DMAC_CFG_LOCK_B (0x1u << 21) /**< \brief (DMAC_CFG)  */
+#define DMAC_CFG_LOCK_IF_L (0x1u << 22) /**< \brief (DMAC_CFG)  */
+#define DMAC_CFG_AHB_PROT_Pos 24
+#define DMAC_CFG_AHB_PROT_Msk (0x7u << DMAC_CFG_AHB_PROT_Pos) /**< \brief (DMAC_CFG)  */
+#define DMAC_CFG_AHB_PROT(value) ((DMAC_CFG_AHB_PROT_Msk & ((value) << DMAC_CFG_AHB_PROT_Pos)))
+#define DMAC_CFG_FIFOCFG_Pos 28
+#define DMAC_CFG_FIFOCFG_Msk (0x3u << DMAC_CFG_FIFOCFG_Pos) /**< \brief (DMAC_CFG)  */
+#define DMAC_CFG_FIFOCFG(value) ((DMAC_CFG_FIFOCFG_Msk & ((value) << DMAC_CFG_FIFOCFG_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3U_DMAC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_efc.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_efc.h
new file mode 100644
index 000000000..03ecd9d1d
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_efc.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_EFC_COMPONENT_
+#define _SAM3U_EFC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Embedded Flash Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_EFC Embedded Flash Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Efc hardware registers */
+typedef struct {
+  RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */
+  WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */
+  RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */
+  RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */
+} Efc;
+#endif /* __ASSEMBLY__ */
+/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
+#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */
+#define EEFC_FMR_FWS_Pos 8
+#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */
+#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))
+#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */
+#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */
+/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
+#define EEFC_FCR_FCMD_Pos 0
+#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */
+#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))
+#define EEFC_FCR_FARG_Pos 8
+#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */
+#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))
+#define EEFC_FCR_FKEY_Pos 24
+#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */
+#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)))
+/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
+#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */
+#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */
+#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */
+/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
+#define EEFC_FRR_FVALUE_Pos 0
+#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */
+
+/*@}*/
+
+
+#endif /* _SAM3U_EFC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_gpbr.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_gpbr.h
new file mode 100644
index 000000000..03449f32f
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_gpbr.h
@@ -0,0 +1,53 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_GPBR_COMPONENT_
+#define _SAM3U_GPBR_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR General Purpose Backup Register */
+/* ============================================================================= */
+/** \addtogroup SAM3U_GPBR General Purpose Backup Register */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Gpbr hardware registers */
+typedef struct {
+  RwReg SYS_GPBR[4]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */
+} Gpbr;
+#endif /* __ASSEMBLY__ */
+/* -------- SYS_GPBR[4] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */
+#define SYS_GPBR_GPBR_VALUE_Pos 0
+#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[4]) Value of GPBR x */
+#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3U_GPBR_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_hsmci.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_hsmci.h
new file mode 100644
index 000000000..7f6afe5ba
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_hsmci.h
@@ -0,0 +1,337 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_HSMCI_COMPONENT_
+#define _SAM3U_HSMCI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3U_HSMCI High Speed MultiMedia Card Interface */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Hsmci hardware registers */
+typedef struct {
+  WoReg HSMCI_CR;        /**< \brief (Hsmci Offset: 0x00) Control Register */
+  RwReg HSMCI_MR;        /**< \brief (Hsmci Offset: 0x04) Mode Register */
+  RwReg HSMCI_DTOR;      /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */
+  RwReg HSMCI_SDCR;      /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */
+  RwReg HSMCI_ARGR;      /**< \brief (Hsmci Offset: 0x10) Argument Register */
+  WoReg HSMCI_CMDR;      /**< \brief (Hsmci Offset: 0x14) Command Register */
+  RwReg HSMCI_BLKR;      /**< \brief (Hsmci Offset: 0x18) Block Register */
+  RwReg HSMCI_CSTOR;     /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */
+  RoReg HSMCI_RSPR[4];   /**< \brief (Hsmci Offset: 0x20) Response Register */
+  RoReg HSMCI_RDR;       /**< \brief (Hsmci Offset: 0x30) Receive Data Register */
+  WoReg HSMCI_TDR;       /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */
+  RoReg Reserved1[2];
+  RoReg HSMCI_SR;        /**< \brief (Hsmci Offset: 0x40) Status Register */
+  WoReg HSMCI_IER;       /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */
+  WoReg HSMCI_IDR;       /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */
+  RoReg HSMCI_IMR;       /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */
+  RwReg HSMCI_DMA;       /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */
+  RwReg HSMCI_CFG;       /**< \brief (Hsmci Offset: 0x54) Configuration Register */
+  RoReg Reserved2[35];
+  RwReg HSMCI_WPMR;      /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */
+  RoReg HSMCI_WPSR;      /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */
+  RoReg Reserved3[69];
+  RwReg HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */
+} Hsmci;
+#endif /* __ASSEMBLY__ */
+/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */
+#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */
+#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */
+#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */
+#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */
+#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */
+/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */
+#define HSMCI_MR_CLKDIV_Pos 0
+#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */
+#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))
+#define HSMCI_MR_PWSDIV_Pos 8
+#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */
+#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))
+#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR)  */
+#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR)  */
+#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */
+#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */
+/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */
+#define HSMCI_DTOR_DTOCYC_Pos 0
+#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */
+#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))
+#define HSMCI_DTOR_DTOMUL_Pos 4
+#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */
+#define   HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */
+#define   HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */
+#define   HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */
+#define   HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */
+#define   HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */
+#define   HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */
+#define   HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */
+#define   HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */
+/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */
+#define HSMCI_SDCR_SDCSEL_Pos 0
+#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */
+#define   HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */
+#define   HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) - */
+#define   HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */
+#define   HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */
+#define HSMCI_SDCR_SDCBUS_Pos 6
+#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */
+#define   HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */
+#define   HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */
+#define   HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */
+/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */
+#define HSMCI_ARGR_ARG_Pos 0
+#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */
+#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))
+/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */
+#define HSMCI_CMDR_CMDNB_Pos 0
+#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */
+#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))
+#define HSMCI_CMDR_RSPTYP_Pos 6
+#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */
+#define   HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */
+#define   HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */
+#define   HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */
+#define   HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */
+#define HSMCI_CMDR_SPCMD_Pos 8
+#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */
+#define   HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */
+#define   HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */
+#define   HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */
+#define   HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */
+#define   HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */
+#define   HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */
+#define   HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */
+#define   HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */
+#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */
+#define   HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */
+#define   HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */
+#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */
+#define   HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */
+#define   HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */
+#define HSMCI_CMDR_TRCMD_Pos 16
+#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */
+#define   HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */
+#define   HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */
+#define   HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */
+#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */
+#define   HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */
+#define   HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */
+#define HSMCI_CMDR_TRTYP_Pos 19
+#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */
+#define   HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */
+#define   HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */
+#define   HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */
+#define   HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */
+#define   HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */
+#define HSMCI_CMDR_IOSPCMD_Pos 24
+#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */
+#define   HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */
+#define   HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */
+#define   HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */
+#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */
+#define   HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */
+#define   HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */
+#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */
+/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */
+#define HSMCI_BLKR_BCNT_Pos 0
+#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */
+#define   HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. */
+#define   HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */
+#define   HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */
+#define HSMCI_BLKR_BLKLEN_Pos 16
+#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */
+#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))
+/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */
+#define HSMCI_CSTOR_CSTOCYC_Pos 0
+#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */
+#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))
+#define HSMCI_CSTOR_CSTOMUL_Pos 4
+#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */
+#define   HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */
+#define   HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */
+#define   HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */
+#define   HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */
+#define   HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */
+#define   HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */
+#define   HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */
+#define   HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */
+/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */
+#define HSMCI_RSPR_RSP_Pos 0
+#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */
+/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */
+#define HSMCI_RDR_DATA_Pos 0
+#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */
+/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */
+#define HSMCI_TDR_DATA_Pos 0
+#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */
+#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))
+/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */
+#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */
+#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */
+#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */
+#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */
+#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */
+#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */
+#define HSMCI_SR_MCI_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR)  */
+#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */
+#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */
+#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */
+#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */
+#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */
+#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */
+#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */
+#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */
+#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */
+#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */
+#define HSMCI_SR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error */
+#define HSMCI_SR_DMADONE (0x1u << 25) /**< \brief (HSMCI_SR) DMA Transfer done */
+#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */
+#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */
+#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */
+#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */
+#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */
+#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */
+/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */
+#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */
+#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */
+#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */
+#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */
+#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */
+#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */
+#define HSMCI_IER_MCI_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER)  */
+#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */
+#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */
+#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */
+#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */
+#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */
+#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */
+#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */
+#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */
+#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */
+#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */
+#define HSMCI_IER_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */
+#define HSMCI_IER_DMADONE (0x1u << 25) /**< \brief (HSMCI_IER) DMA Transfer completed Interrupt Enable */
+#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */
+#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */
+#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */
+#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */
+#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */
+#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */
+/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */
+#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */
+#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */
+#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */
+#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */
+#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */
+#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */
+#define HSMCI_IDR_MCI_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR)  */
+#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */
+#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */
+#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */
+#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */
+#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */
+#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */
+#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */
+#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */
+#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */
+#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */
+#define HSMCI_IDR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */
+#define HSMCI_IDR_DMADONE (0x1u << 25) /**< \brief (HSMCI_IDR) DMA Transfer completed Interrupt Disable */
+#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */
+#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */
+#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */
+#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */
+#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */
+#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */
+/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */
+#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */
+#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */
+#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */
+#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */
+#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */
+#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */
+#define HSMCI_IMR_MCI_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR)  */
+#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */
+#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */
+#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */
+#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */
+#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */
+#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */
+#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */
+#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */
+#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */
+#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */
+#define HSMCI_IMR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */
+#define HSMCI_IMR_DMADONE (0x1u << 25) /**< \brief (HSMCI_IMR) DMA Transfer Completed Interrupt Mask */
+#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */
+#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */
+#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */
+#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */
+#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */
+#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */
+/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */
+#define HSMCI_DMA_OFFSET_Pos 0
+#define HSMCI_DMA_OFFSET_Msk (0x3u << HSMCI_DMA_OFFSET_Pos) /**< \brief (HSMCI_DMA) DMA Write Buffer Offset */
+#define HSMCI_DMA_OFFSET(value) ((HSMCI_DMA_OFFSET_Msk & ((value) << HSMCI_DMA_OFFSET_Pos)))
+#define HSMCI_DMA_CHKSIZE (0x1u << 4) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */
+#define   HSMCI_DMA_CHKSIZE_1 (0x0u << 4) /**< \brief (HSMCI_DMA) 1 data available */
+#define   HSMCI_DMA_CHKSIZE_4 (0x1u << 4) /**< \brief (HSMCI_DMA) 4 data available */
+#define HSMCI_DMA_DMAEN (0x1u << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */
+#define HSMCI_DMA_ROPT (0x1u << 12) /**< \brief (HSMCI_DMA) Read Optimization with padding */
+/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */
+#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */
+#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */
+#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */
+#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */
+/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */
+#define HSMCI_WPMR_WP_EN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */
+#define HSMCI_WPMR_WP_KEY_Pos 8
+#define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) /**< \brief (HSMCI_WPMR) Write Protection Key password */
+#define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos)))
+/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */
+#define HSMCI_WPSR_WP_VS_Pos 0
+#define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */
+#define   HSMCI_WPSR_WP_VS_NONE (0x0u << 0) /**< \brief (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) */
+#define   HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) */
+#define   HSMCI_WPSR_WP_VS_RESET (0x2u << 0) /**< \brief (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). */
+#define   HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) /**< \brief (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. */
+#define HSMCI_WPSR_WP_VSRC_Pos 8
+#define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */
+/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */
+#define HSMCI_FIFO_DATA_Pos 0
+#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */
+#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3U_HSMCI_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_matrix.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_matrix.h
new file mode 100644
index 000000000..5d4c5616b
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_matrix.h
@@ -0,0 +1,269 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_MATRIX_COMPONENT_
+#define _SAM3U_MATRIX_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR AHB Bus Matrix */
+/* ============================================================================= */
+/** \addtogroup SAM3U_MATRIX AHB Bus Matrix */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Matrix hardware registers */
+typedef struct {
+  RwReg MATRIX_MCFG[5];  /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */
+  RoReg Reserved1[11];
+  RwReg MATRIX_SCFG[10]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */
+  RoReg Reserved2[6];
+  RwReg MATRIX_PRAS0;    /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */
+  RoReg Reserved3[1];
+  RwReg MATRIX_PRAS1;    /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */
+  RoReg Reserved4[1];
+  RwReg MATRIX_PRAS2;    /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */
+  RoReg Reserved5[1];
+  RwReg MATRIX_PRAS3;    /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */
+  RoReg Reserved6[1];
+  RwReg MATRIX_PRAS4;    /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */
+  RoReg Reserved7[1];
+  RwReg MATRIX_PRAS5;    /**< \brief (Matrix Offset: 0x00A8) Priority Register A for Slave 5 */
+  RoReg Reserved8[1];
+  RwReg MATRIX_PRAS6;    /**< \brief (Matrix Offset: 0x00B0) Priority Register A for Slave 6 */
+  RoReg Reserved9[1];
+  RwReg MATRIX_PRAS7;    /**< \brief (Matrix Offset: 0x00B8) Priority Register A for Slave 7 */
+  RoReg Reserved10[1];
+  RwReg MATRIX_PRAS8;    /**< \brief (Matrix Offset: 0x00C0) Priority Register A for Slave 8 */
+  RoReg Reserved11[1];
+  RwReg MATRIX_PRAS9;    /**< \brief (Matrix Offset: 0x00C8) Priority Register A for Slave 9 */
+  RoReg Reserved12[1];
+  RoReg Reserved13[12];
+  RwReg MATRIX_MRCR;     /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */
+  RoReg Reserved14[56];
+  RwReg MATRIX_WPMR;     /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */
+  RoReg MATRIX_WPSR;     /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */
+} Matrix;
+#endif /* __ASSEMBLY__ */
+/* -------- MATRIX_MCFG[5] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */
+#define MATRIX_MCFG_ULBT_Pos 0
+#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[5]) Undefined Length Burst Type */
+#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))
+/* -------- MATRIX_SCFG[10] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
+#define MATRIX_SCFG_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[10]) Maximum Number of Allowed Cycles for a Burst */
+#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[10]) Default Master Type */
+#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
+#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[10]) Fixed Default Master */
+#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
+#define MATRIX_SCFG_ARBT_Pos 24
+#define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[10]) Arbitration Type */
+#define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos)))
+/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */
+#define MATRIX_PRAS0_M0PR_Pos 0
+#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */
+#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))
+#define MATRIX_PRAS0_M1PR_Pos 4
+#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */
+#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))
+#define MATRIX_PRAS0_M2PR_Pos 8
+#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */
+#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))
+#define MATRIX_PRAS0_M3PR_Pos 12
+#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */
+#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))
+#define MATRIX_PRAS0_M4PR_Pos 16
+#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */
+#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos)))
+/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */
+#define MATRIX_PRAS1_M0PR_Pos 0
+#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */
+#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))
+#define MATRIX_PRAS1_M1PR_Pos 4
+#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */
+#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))
+#define MATRIX_PRAS1_M2PR_Pos 8
+#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */
+#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))
+#define MATRIX_PRAS1_M3PR_Pos 12
+#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */
+#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))
+#define MATRIX_PRAS1_M4PR_Pos 16
+#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */
+#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos)))
+/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */
+#define MATRIX_PRAS2_M0PR_Pos 0
+#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */
+#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))
+#define MATRIX_PRAS2_M1PR_Pos 4
+#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */
+#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))
+#define MATRIX_PRAS2_M2PR_Pos 8
+#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */
+#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))
+#define MATRIX_PRAS2_M3PR_Pos 12
+#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */
+#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))
+#define MATRIX_PRAS2_M4PR_Pos 16
+#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */
+#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos)))
+/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */
+#define MATRIX_PRAS3_M0PR_Pos 0
+#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */
+#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))
+#define MATRIX_PRAS3_M1PR_Pos 4
+#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */
+#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))
+#define MATRIX_PRAS3_M2PR_Pos 8
+#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */
+#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))
+#define MATRIX_PRAS3_M3PR_Pos 12
+#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */
+#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))
+#define MATRIX_PRAS3_M4PR_Pos 16
+#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */
+#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos)))
+/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */
+#define MATRIX_PRAS4_M0PR_Pos 0
+#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */
+#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos)))
+#define MATRIX_PRAS4_M1PR_Pos 4
+#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */
+#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos)))
+#define MATRIX_PRAS4_M2PR_Pos 8
+#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */
+#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos)))
+#define MATRIX_PRAS4_M3PR_Pos 12
+#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */
+#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos)))
+#define MATRIX_PRAS4_M4PR_Pos 16
+#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */
+#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos)))
+/* -------- MATRIX_PRAS5 : (MATRIX Offset: 0x00A8) Priority Register A for Slave 5 -------- */
+#define MATRIX_PRAS5_M0PR_Pos 0
+#define MATRIX_PRAS5_M0PR_Msk (0x3u << MATRIX_PRAS5_M0PR_Pos) /**< \brief (MATRIX_PRAS5) Master 0 Priority */
+#define MATRIX_PRAS5_M0PR(value) ((MATRIX_PRAS5_M0PR_Msk & ((value) << MATRIX_PRAS5_M0PR_Pos)))
+#define MATRIX_PRAS5_M1PR_Pos 4
+#define MATRIX_PRAS5_M1PR_Msk (0x3u << MATRIX_PRAS5_M1PR_Pos) /**< \brief (MATRIX_PRAS5) Master 1 Priority */
+#define MATRIX_PRAS5_M1PR(value) ((MATRIX_PRAS5_M1PR_Msk & ((value) << MATRIX_PRAS5_M1PR_Pos)))
+#define MATRIX_PRAS5_M2PR_Pos 8
+#define MATRIX_PRAS5_M2PR_Msk (0x3u << MATRIX_PRAS5_M2PR_Pos) /**< \brief (MATRIX_PRAS5) Master 2 Priority */
+#define MATRIX_PRAS5_M2PR(value) ((MATRIX_PRAS5_M2PR_Msk & ((value) << MATRIX_PRAS5_M2PR_Pos)))
+#define MATRIX_PRAS5_M3PR_Pos 12
+#define MATRIX_PRAS5_M3PR_Msk (0x3u << MATRIX_PRAS5_M3PR_Pos) /**< \brief (MATRIX_PRAS5) Master 3 Priority */
+#define MATRIX_PRAS5_M3PR(value) ((MATRIX_PRAS5_M3PR_Msk & ((value) << MATRIX_PRAS5_M3PR_Pos)))
+#define MATRIX_PRAS5_M4PR_Pos 16
+#define MATRIX_PRAS5_M4PR_Msk (0x3u << MATRIX_PRAS5_M4PR_Pos) /**< \brief (MATRIX_PRAS5) Master 4 Priority */
+#define MATRIX_PRAS5_M4PR(value) ((MATRIX_PRAS5_M4PR_Msk & ((value) << MATRIX_PRAS5_M4PR_Pos)))
+/* -------- MATRIX_PRAS6 : (MATRIX Offset: 0x00B0) Priority Register A for Slave 6 -------- */
+#define MATRIX_PRAS6_M0PR_Pos 0
+#define MATRIX_PRAS6_M0PR_Msk (0x3u << MATRIX_PRAS6_M0PR_Pos) /**< \brief (MATRIX_PRAS6) Master 0 Priority */
+#define MATRIX_PRAS6_M0PR(value) ((MATRIX_PRAS6_M0PR_Msk & ((value) << MATRIX_PRAS6_M0PR_Pos)))
+#define MATRIX_PRAS6_M1PR_Pos 4
+#define MATRIX_PRAS6_M1PR_Msk (0x3u << MATRIX_PRAS6_M1PR_Pos) /**< \brief (MATRIX_PRAS6) Master 1 Priority */
+#define MATRIX_PRAS6_M1PR(value) ((MATRIX_PRAS6_M1PR_Msk & ((value) << MATRIX_PRAS6_M1PR_Pos)))
+#define MATRIX_PRAS6_M2PR_Pos 8
+#define MATRIX_PRAS6_M2PR_Msk (0x3u << MATRIX_PRAS6_M2PR_Pos) /**< \brief (MATRIX_PRAS6) Master 2 Priority */
+#define MATRIX_PRAS6_M2PR(value) ((MATRIX_PRAS6_M2PR_Msk & ((value) << MATRIX_PRAS6_M2PR_Pos)))
+#define MATRIX_PRAS6_M3PR_Pos 12
+#define MATRIX_PRAS6_M3PR_Msk (0x3u << MATRIX_PRAS6_M3PR_Pos) /**< \brief (MATRIX_PRAS6) Master 3 Priority */
+#define MATRIX_PRAS6_M3PR(value) ((MATRIX_PRAS6_M3PR_Msk & ((value) << MATRIX_PRAS6_M3PR_Pos)))
+#define MATRIX_PRAS6_M4PR_Pos 16
+#define MATRIX_PRAS6_M4PR_Msk (0x3u << MATRIX_PRAS6_M4PR_Pos) /**< \brief (MATRIX_PRAS6) Master 4 Priority */
+#define MATRIX_PRAS6_M4PR(value) ((MATRIX_PRAS6_M4PR_Msk & ((value) << MATRIX_PRAS6_M4PR_Pos)))
+/* -------- MATRIX_PRAS7 : (MATRIX Offset: 0x00B8) Priority Register A for Slave 7 -------- */
+#define MATRIX_PRAS7_M0PR_Pos 0
+#define MATRIX_PRAS7_M0PR_Msk (0x3u << MATRIX_PRAS7_M0PR_Pos) /**< \brief (MATRIX_PRAS7) Master 0 Priority */
+#define MATRIX_PRAS7_M0PR(value) ((MATRIX_PRAS7_M0PR_Msk & ((value) << MATRIX_PRAS7_M0PR_Pos)))
+#define MATRIX_PRAS7_M1PR_Pos 4
+#define MATRIX_PRAS7_M1PR_Msk (0x3u << MATRIX_PRAS7_M1PR_Pos) /**< \brief (MATRIX_PRAS7) Master 1 Priority */
+#define MATRIX_PRAS7_M1PR(value) ((MATRIX_PRAS7_M1PR_Msk & ((value) << MATRIX_PRAS7_M1PR_Pos)))
+#define MATRIX_PRAS7_M2PR_Pos 8
+#define MATRIX_PRAS7_M2PR_Msk (0x3u << MATRIX_PRAS7_M2PR_Pos) /**< \brief (MATRIX_PRAS7) Master 2 Priority */
+#define MATRIX_PRAS7_M2PR(value) ((MATRIX_PRAS7_M2PR_Msk & ((value) << MATRIX_PRAS7_M2PR_Pos)))
+#define MATRIX_PRAS7_M3PR_Pos 12
+#define MATRIX_PRAS7_M3PR_Msk (0x3u << MATRIX_PRAS7_M3PR_Pos) /**< \brief (MATRIX_PRAS7) Master 3 Priority */
+#define MATRIX_PRAS7_M3PR(value) ((MATRIX_PRAS7_M3PR_Msk & ((value) << MATRIX_PRAS7_M3PR_Pos)))
+#define MATRIX_PRAS7_M4PR_Pos 16
+#define MATRIX_PRAS7_M4PR_Msk (0x3u << MATRIX_PRAS7_M4PR_Pos) /**< \brief (MATRIX_PRAS7) Master 4 Priority */
+#define MATRIX_PRAS7_M4PR(value) ((MATRIX_PRAS7_M4PR_Msk & ((value) << MATRIX_PRAS7_M4PR_Pos)))
+/* -------- MATRIX_PRAS8 : (MATRIX Offset: 0x00C0) Priority Register A for Slave 8 -------- */
+#define MATRIX_PRAS8_M0PR_Pos 0
+#define MATRIX_PRAS8_M0PR_Msk (0x3u << MATRIX_PRAS8_M0PR_Pos) /**< \brief (MATRIX_PRAS8) Master 0 Priority */
+#define MATRIX_PRAS8_M0PR(value) ((MATRIX_PRAS8_M0PR_Msk & ((value) << MATRIX_PRAS8_M0PR_Pos)))
+#define MATRIX_PRAS8_M1PR_Pos 4
+#define MATRIX_PRAS8_M1PR_Msk (0x3u << MATRIX_PRAS8_M1PR_Pos) /**< \brief (MATRIX_PRAS8) Master 1 Priority */
+#define MATRIX_PRAS8_M1PR(value) ((MATRIX_PRAS8_M1PR_Msk & ((value) << MATRIX_PRAS8_M1PR_Pos)))
+#define MATRIX_PRAS8_M2PR_Pos 8
+#define MATRIX_PRAS8_M2PR_Msk (0x3u << MATRIX_PRAS8_M2PR_Pos) /**< \brief (MATRIX_PRAS8) Master 2 Priority */
+#define MATRIX_PRAS8_M2PR(value) ((MATRIX_PRAS8_M2PR_Msk & ((value) << MATRIX_PRAS8_M2PR_Pos)))
+#define MATRIX_PRAS8_M3PR_Pos 12
+#define MATRIX_PRAS8_M3PR_Msk (0x3u << MATRIX_PRAS8_M3PR_Pos) /**< \brief (MATRIX_PRAS8) Master 3 Priority */
+#define MATRIX_PRAS8_M3PR(value) ((MATRIX_PRAS8_M3PR_Msk & ((value) << MATRIX_PRAS8_M3PR_Pos)))
+#define MATRIX_PRAS8_M4PR_Pos 16
+#define MATRIX_PRAS8_M4PR_Msk (0x3u << MATRIX_PRAS8_M4PR_Pos) /**< \brief (MATRIX_PRAS8) Master 4 Priority */
+#define MATRIX_PRAS8_M4PR(value) ((MATRIX_PRAS8_M4PR_Msk & ((value) << MATRIX_PRAS8_M4PR_Pos)))
+/* -------- MATRIX_PRAS9 : (MATRIX Offset: 0x00C8) Priority Register A for Slave 9 -------- */
+#define MATRIX_PRAS9_M0PR_Pos 0
+#define MATRIX_PRAS9_M0PR_Msk (0x3u << MATRIX_PRAS9_M0PR_Pos) /**< \brief (MATRIX_PRAS9) Master 0 Priority */
+#define MATRIX_PRAS9_M0PR(value) ((MATRIX_PRAS9_M0PR_Msk & ((value) << MATRIX_PRAS9_M0PR_Pos)))
+#define MATRIX_PRAS9_M1PR_Pos 4
+#define MATRIX_PRAS9_M1PR_Msk (0x3u << MATRIX_PRAS9_M1PR_Pos) /**< \brief (MATRIX_PRAS9) Master 1 Priority */
+#define MATRIX_PRAS9_M1PR(value) ((MATRIX_PRAS9_M1PR_Msk & ((value) << MATRIX_PRAS9_M1PR_Pos)))
+#define MATRIX_PRAS9_M2PR_Pos 8
+#define MATRIX_PRAS9_M2PR_Msk (0x3u << MATRIX_PRAS9_M2PR_Pos) /**< \brief (MATRIX_PRAS9) Master 2 Priority */
+#define MATRIX_PRAS9_M2PR(value) ((MATRIX_PRAS9_M2PR_Msk & ((value) << MATRIX_PRAS9_M2PR_Pos)))
+#define MATRIX_PRAS9_M3PR_Pos 12
+#define MATRIX_PRAS9_M3PR_Msk (0x3u << MATRIX_PRAS9_M3PR_Pos) /**< \brief (MATRIX_PRAS9) Master 3 Priority */
+#define MATRIX_PRAS9_M3PR(value) ((MATRIX_PRAS9_M3PR_Msk & ((value) << MATRIX_PRAS9_M3PR_Pos)))
+#define MATRIX_PRAS9_M4PR_Pos 16
+#define MATRIX_PRAS9_M4PR_Msk (0x3u << MATRIX_PRAS9_M4PR_Pos) /**< \brief (MATRIX_PRAS9) Master 4 Priority */
+#define MATRIX_PRAS9_M4PR(value) ((MATRIX_PRAS9_M4PR_Msk & ((value) << MATRIX_PRAS9_M4PR_Pos)))
+/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */
+#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 0 */
+#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 1 */
+#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 2 */
+#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 3 */
+#define MATRIX_MRCR_RCB4 (0x1u << 4) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 4 */
+/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */
+#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */
+#define MATRIX_WPMR_WPKEY_Pos 8
+#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */
+#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
+/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */
+#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */
+#define MATRIX_WPSR_WPVSRC_Pos 8
+#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3U_MATRIX_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_pdc.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_pdc.h
new file mode 100644
index 000000000..373accd4e
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_pdc.h
@@ -0,0 +1,98 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_PDC_COMPONENT_
+#define _SAM3U_PDC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_PDC Peripheral DMA Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Pdc hardware registers */
+typedef struct {
+  RwReg PERIPH_RPR;  /**< \brief (Pdc Offset: 0x0) Receive Pointer Register */
+  RwReg PERIPH_RCR;  /**< \brief (Pdc Offset: 0x4) Receive Counter Register */
+  RwReg PERIPH_TPR;  /**< \brief (Pdc Offset: 0x8) Transmit Pointer Register */
+  RwReg PERIPH_TCR;  /**< \brief (Pdc Offset: 0xC) Transmit Counter Register */
+  RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */
+  RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */
+  RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */
+  RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */
+  WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */
+  RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */
+} Pdc;
+#endif /* __ASSEMBLY__ */
+/* -------- PERIPH_RPR : (PDC Offset: 0x0) Receive Pointer Register -------- */
+#define PERIPH_RPR_RXPTR_Pos 0
+#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */
+#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos)))
+/* -------- PERIPH_RCR : (PDC Offset: 0x4) Receive Counter Register -------- */
+#define PERIPH_RCR_RXCTR_Pos 0
+#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */
+#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos)))
+/* -------- PERIPH_TPR : (PDC Offset: 0x8) Transmit Pointer Register -------- */
+#define PERIPH_TPR_TXPTR_Pos 0
+#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */
+#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos)))
+/* -------- PERIPH_TCR : (PDC Offset: 0xC) Transmit Counter Register -------- */
+#define PERIPH_TCR_TXCTR_Pos 0
+#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */
+#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos)))
+/* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */
+#define PERIPH_RNPR_RXNPTR_Pos 0
+#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */
+#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos)))
+/* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */
+#define PERIPH_RNCR_RXNCTR_Pos 0
+#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */
+#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos)))
+/* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */
+#define PERIPH_TNPR_TXNPTR_Pos 0
+#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */
+#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos)))
+/* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */
+#define PERIPH_TNCR_TXNCTR_Pos 0
+#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */
+#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos)))
+/* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */
+#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */
+#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */
+#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */
+#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */
+/* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */
+#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */
+#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3U_PDC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_pio.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_pio.h
new file mode 100644
index 000000000..8a65ee762
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_pio.h
@@ -0,0 +1,1435 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_PIO_COMPONENT_
+#define _SAM3U_PIO_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_PIO Parallel Input/Output Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Pio hardware registers */
+typedef struct {
+  WoReg PIO_PER;       /**< \brief (Pio Offset: 0x0000) PIO Enable Register */
+  WoReg PIO_PDR;       /**< \brief (Pio Offset: 0x0004) PIO Disable Register */
+  RoReg PIO_PSR;       /**< \brief (Pio Offset: 0x0008) PIO Status Register */
+  RoReg Reserved1[1];
+  WoReg PIO_OER;       /**< \brief (Pio Offset: 0x0010) Output Enable Register */
+  WoReg PIO_ODR;       /**< \brief (Pio Offset: 0x0014) Output Disable Register */
+  RoReg PIO_OSR;       /**< \brief (Pio Offset: 0x0018) Output Status Register */
+  RoReg Reserved2[1];
+  WoReg PIO_IFER;      /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */
+  WoReg PIO_IFDR;      /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */
+  RoReg PIO_IFSR;      /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */
+  RoReg Reserved3[1];
+  WoReg PIO_SODR;      /**< \brief (Pio Offset: 0x0030) Set Output Data Register */
+  WoReg PIO_CODR;      /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */
+  RwReg PIO_ODSR;      /**< \brief (Pio Offset: 0x0038) Output Data Status Register */
+  RoReg PIO_PDSR;      /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */
+  WoReg PIO_IER;       /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */
+  WoReg PIO_IDR;       /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */
+  RoReg PIO_IMR;       /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */
+  RoReg PIO_ISR;       /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */
+  WoReg PIO_MDER;      /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */
+  WoReg PIO_MDDR;      /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */
+  RoReg PIO_MDSR;      /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */
+  RoReg Reserved4[1];
+  WoReg PIO_PUDR;      /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */
+  WoReg PIO_PUER;      /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */
+  RoReg PIO_PUSR;      /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */
+  RoReg Reserved5[1];
+  RwReg PIO_ABSR;      /**< \brief (Pio Offset: 0x0070) Peripheral AB Select Register */
+  RoReg Reserved6[3];
+  WoReg PIO_SCIFSR;    /**< \brief (Pio Offset: 0x0080) System Clock Glitch Input Filter Select Register */
+  WoReg PIO_DIFSR;     /**< \brief (Pio Offset: 0x0084) Debouncing Input Filter Select Register */
+  RoReg PIO_IFDGSR;    /**< \brief (Pio Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register */
+  RwReg PIO_SCDR;      /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */
+  RoReg Reserved7[4];
+  WoReg PIO_OWER;      /**< \brief (Pio Offset: 0x00A0) Output Write Enable */
+  WoReg PIO_OWDR;      /**< \brief (Pio Offset: 0x00A4) Output Write Disable */
+  RoReg PIO_OWSR;      /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */
+  RoReg Reserved8[1];
+  WoReg PIO_AIMER;     /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */
+  WoReg PIO_AIMDR;     /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */
+  RoReg PIO_AIMMR;     /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */
+  RoReg Reserved9[1];
+  WoReg PIO_ESR;       /**< \brief (Pio Offset: 0x00C0) Edge Select Register */
+  WoReg PIO_LSR;       /**< \brief (Pio Offset: 0x00C4) Level Select Register */
+  RoReg PIO_ELSR;      /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */
+  RoReg Reserved10[1];
+  WoReg PIO_FELLSR;    /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */
+  WoReg PIO_REHLSR;    /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */
+  RoReg PIO_FRLHSR;    /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */
+  RoReg Reserved11[1];
+  RoReg PIO_LOCKSR;    /**< \brief (Pio Offset: 0x00E0) Lock Status */
+  RwReg PIO_WPMR;      /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */
+  RoReg PIO_WPSR;      /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */
+} Pio;
+#endif /* __ASSEMBLY__ */
+/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */
+#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */
+/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */
+#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */
+/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */
+#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */
+/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */
+#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */
+/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */
+#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */
+/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */
+#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */
+/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */
+#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */
+/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */
+#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */
+/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */
+#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */
+/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */
+#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */
+/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */
+#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */
+/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */
+#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */
+/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */
+#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */
+/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */
+#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */
+#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */
+#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */
+#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */
+#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */
+/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */
+#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */
+#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */
+/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */
+#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */
+/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */
+#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull Up Enable. */
+/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */
+#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull Up Status. */
+/* -------- PIO_ABSR : (PIO Offset: 0x0070) Peripheral AB Select Register -------- */
+#define PIO_ABSR_P0 (0x1u << 0) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P1 (0x1u << 1) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P2 (0x1u << 2) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P3 (0x1u << 3) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P4 (0x1u << 4) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P5 (0x1u << 5) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P6 (0x1u << 6) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P7 (0x1u << 7) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P8 (0x1u << 8) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P9 (0x1u << 9) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P10 (0x1u << 10) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P11 (0x1u << 11) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P12 (0x1u << 12) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P13 (0x1u << 13) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P14 (0x1u << 14) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P15 (0x1u << 15) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P16 (0x1u << 16) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P17 (0x1u << 17) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P18 (0x1u << 18) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P19 (0x1u << 19) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P20 (0x1u << 20) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P21 (0x1u << 21) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P22 (0x1u << 22) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P23 (0x1u << 23) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P24 (0x1u << 24) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P25 (0x1u << 25) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P26 (0x1u << 26) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P27 (0x1u << 27) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P28 (0x1u << 28) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P29 (0x1u << 29) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P30 (0x1u << 30) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P31 (0x1u << 31) /**< \brief (PIO_ABSR) Peripheral A Select. */
+/* -------- PIO_SCIFSR : (PIO Offset: 0x0080) System Clock Glitch Input Filter Select Register -------- */
+#define PIO_SCIFSR_P0 (0x1u << 0) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P1 (0x1u << 1) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P2 (0x1u << 2) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P3 (0x1u << 3) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P4 (0x1u << 4) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P5 (0x1u << 5) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P6 (0x1u << 6) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P7 (0x1u << 7) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P8 (0x1u << 8) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P9 (0x1u << 9) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P10 (0x1u << 10) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P11 (0x1u << 11) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P12 (0x1u << 12) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P13 (0x1u << 13) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P14 (0x1u << 14) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P15 (0x1u << 15) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P16 (0x1u << 16) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P17 (0x1u << 17) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P18 (0x1u << 18) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P19 (0x1u << 19) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P20 (0x1u << 20) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P21 (0x1u << 21) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P22 (0x1u << 22) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P23 (0x1u << 23) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P24 (0x1u << 24) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P25 (0x1u << 25) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P26 (0x1u << 26) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P27 (0x1u << 27) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P28 (0x1u << 28) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P29 (0x1u << 29) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P30 (0x1u << 30) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P31 (0x1u << 31) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+/* -------- PIO_DIFSR : (PIO Offset: 0x0084) Debouncing Input Filter Select Register -------- */
+#define PIO_DIFSR_P0 (0x1u << 0) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P1 (0x1u << 1) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P2 (0x1u << 2) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P3 (0x1u << 3) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P4 (0x1u << 4) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P5 (0x1u << 5) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P6 (0x1u << 6) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P7 (0x1u << 7) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P8 (0x1u << 8) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P9 (0x1u << 9) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P10 (0x1u << 10) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P11 (0x1u << 11) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P12 (0x1u << 12) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P13 (0x1u << 13) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P14 (0x1u << 14) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P15 (0x1u << 15) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P16 (0x1u << 16) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P17 (0x1u << 17) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P18 (0x1u << 18) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P19 (0x1u << 19) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P20 (0x1u << 20) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P21 (0x1u << 21) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P22 (0x1u << 22) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P23 (0x1u << 23) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P24 (0x1u << 24) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P25 (0x1u << 25) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P26 (0x1u << 26) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P27 (0x1u << 27) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P28 (0x1u << 28) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P29 (0x1u << 29) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P30 (0x1u << 30) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P31 (0x1u << 31) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+/* -------- PIO_IFDGSR : (PIO Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register -------- */
+#define PIO_IFDGSR_P0 (0x1u << 0) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P1 (0x1u << 1) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P2 (0x1u << 2) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P3 (0x1u << 3) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P4 (0x1u << 4) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P5 (0x1u << 5) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P6 (0x1u << 6) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P7 (0x1u << 7) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P8 (0x1u << 8) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P9 (0x1u << 9) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P10 (0x1u << 10) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P11 (0x1u << 11) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P12 (0x1u << 12) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P13 (0x1u << 13) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P14 (0x1u << 14) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P15 (0x1u << 15) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P16 (0x1u << 16) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P17 (0x1u << 17) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P18 (0x1u << 18) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P19 (0x1u << 19) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P20 (0x1u << 20) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P21 (0x1u << 21) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P22 (0x1u << 22) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P23 (0x1u << 23) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P24 (0x1u << 24) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P25 (0x1u << 25) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P26 (0x1u << 26) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P27 (0x1u << 27) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P28 (0x1u << 28) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P29 (0x1u << 29) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P30 (0x1u << 30) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P31 (0x1u << 31) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */
+#define PIO_SCDR_DIV_Pos 0
+#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */
+#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)))
+/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */
+#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable. */
+/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */
+#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable. */
+/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */
+#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status. */
+/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */
+#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */
+#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */
+#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */
+#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */
+#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */
+#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */
+#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */
+#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */
+#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */
+#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status. */
+/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protect Enable */
+#define PIO_WPMR_WPKEY_Pos 8
+#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protect KEY */
+#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)))
+/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */
+#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */
+#define PIO_WPSR_WPVSRC_Pos 8
+#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3U_PIO_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_pmc.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_pmc.h
new file mode 100644
index 000000000..6cd5dee7a
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_pmc.h
@@ -0,0 +1,342 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_PMC_COMPONENT_
+#define _SAM3U_PMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Power Management Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_PMC Power Management Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Pmc hardware registers */
+typedef struct {
+  WoReg PMC_SCER;      /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */
+  WoReg PMC_SCDR;      /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */
+  RoReg PMC_SCSR;      /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */
+  RoReg Reserved1[1];
+  WoReg PMC_PCER0;     /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */
+  WoReg PMC_PCDR0;     /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */
+  RoReg PMC_PCSR0;     /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */
+  RwReg CKGR_UCKR;     /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */
+  RwReg CKGR_MOR;      /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */
+  RoReg CKGR_MCFR;     /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */
+  RwReg CKGR_PLLAR;    /**< \brief (Pmc Offset: 0x0028) PLLA Register */
+  RoReg Reserved2[1];
+  RwReg PMC_MCKR;      /**< \brief (Pmc Offset: 0x0030) Master Clock Register */
+  RoReg Reserved3[3];
+  RwReg PMC_PCK[3];    /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */
+  RoReg Reserved4[5];
+  WoReg PMC_IER;       /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */
+  WoReg PMC_IDR;       /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */
+  RoReg PMC_SR;        /**< \brief (Pmc Offset: 0x0068) Status Register */
+  RoReg PMC_IMR;       /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */
+  RwReg PMC_FSMR;      /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */
+  RwReg PMC_FSPR;      /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */
+  WoReg PMC_FOCR;      /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */
+  RoReg Reserved5[26];
+  RwReg PMC_WPMR;      /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */
+  RoReg PMC_WPSR;      /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */
+} Pmc;
+#endif /* __ASSEMBLY__ */
+/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
+#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */
+#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */
+#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */
+/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
+#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */
+#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */
+#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */
+/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
+#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */
+#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */
+#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */
+/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
+#define PMC_PCER0_PID2 (0x1u << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */
+#define PMC_PCER0_PID3 (0x1u << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */
+#define PMC_PCER0_PID4 (0x1u << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */
+#define PMC_PCER0_PID5 (0x1u << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */
+#define PMC_PCER0_PID6 (0x1u << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */
+#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */
+#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */
+#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */
+#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */
+#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */
+#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */
+#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */
+#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */
+#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */
+#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */
+#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */
+#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */
+#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */
+#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */
+#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */
+#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */
+#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */
+#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */
+#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */
+#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */
+#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */
+#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */
+/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
+#define PMC_PCDR0_PID2 (0x1u << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */
+#define PMC_PCDR0_PID3 (0x1u << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */
+#define PMC_PCDR0_PID4 (0x1u << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */
+#define PMC_PCDR0_PID5 (0x1u << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */
+#define PMC_PCDR0_PID6 (0x1u << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */
+#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */
+#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */
+#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */
+#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */
+#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */
+#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */
+#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */
+#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */
+#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */
+#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */
+#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */
+#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */
+#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */
+#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */
+#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */
+#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */
+#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */
+#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */
+#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */
+#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */
+#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */
+#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */
+/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
+#define PMC_PCSR0_PID2 (0x1u << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */
+#define PMC_PCSR0_PID3 (0x1u << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */
+#define PMC_PCSR0_PID4 (0x1u << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */
+#define PMC_PCSR0_PID5 (0x1u << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */
+#define PMC_PCSR0_PID6 (0x1u << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */
+#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */
+#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */
+#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */
+#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */
+#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */
+#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */
+#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */
+#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */
+#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */
+#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */
+#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */
+#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */
+#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */
+#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */
+#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */
+#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */
+#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */
+#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */
+#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */
+#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */
+#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */
+#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */
+/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */
+#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */
+#define CKGR_UCKR_UPLLCOUNT_Pos 20
+#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */
+#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)))
+/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
+#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */
+#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */
+#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */
+#define CKGR_MOR_MOSCRCF_Pos 4
+#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */
+#define   CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default) */
+#define   CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz */
+#define   CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz */
+#define CKGR_MOR_MOSCRCF(value) ((CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos)))
+#define CKGR_MOR_MOSCXTST_Pos 8
+#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */
+#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
+#define CKGR_MOR_KEY_Pos 16
+#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */
+#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
+#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */
+#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */
+/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
+#define CKGR_MCFR_MAINF_Pos 0
+#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */
+#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */
+/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
+#define CKGR_PLLAR_DIVA_Pos 0
+#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider */
+#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
+#define CKGR_PLLAR_PLLACOUNT_Pos 8
+#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */
+#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
+#define CKGR_PLLAR_MULA_Pos 16
+#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */
+#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
+#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */
+/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
+#define PMC_MCKR_CSS_Pos 0
+#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */
+#define   PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */
+#define   PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */
+#define   PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */
+#define   PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) UPLLClock is selected */
+#define PMC_MCKR_CSS(value) ((PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos)))
+#define PMC_MCKR_PRES_Pos 4
+#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */
+#define   PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */
+#define   PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */
+#define   PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */
+#define   PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */
+#define   PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */
+#define   PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */
+#define   PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */
+#define   PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */
+#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */
+#define PMC_MCKR_UPLLDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) UPLL Divisor by 2 */
+/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
+#define PMC_PCK_CSS_Pos 0
+#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */
+#define   PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */
+#define   PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */
+#define   PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */
+#define   PMC_PCK_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) UPLL Clock is selected */
+#define   PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */
+#define PMC_PCK_PRES_Pos 4
+#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */
+#define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos)))
+#define   PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */
+#define   PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */
+#define   PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */
+#define   PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */
+#define   PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */
+#define   PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */
+#define   PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */
+/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
+#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */
+#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */
+#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */
+#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */
+#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */
+#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */
+#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */
+#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */
+#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */
+#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */
+/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
+#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */
+#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */
+#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */
+#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */
+#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */
+#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */
+#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */
+#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */
+#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */
+#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */
+/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
+#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */
+#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */
+#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */
+#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */
+#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */
+#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */
+#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */
+#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */
+#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */
+#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */
+/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
+#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */
+#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */
+#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */
+#define PMC_IMR_LOCKU (0x1u << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */
+#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */
+#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */
+#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */
+#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */
+#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */
+#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */
+/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
+#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */
+#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */
+#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */
+#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */
+#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */
+#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */
+#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */
+#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */
+#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */
+#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */
+#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */
+#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */
+#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */
+#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */
+#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */
+#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */
+#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */
+#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */
+#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */
+#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low Power Mode */
+/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
+#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
+#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */
+/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */
+#define PMC_WPMR_WPKEY_Pos 8
+#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */
+#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
+/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */
+#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */
+#define PMC_WPSR_WPVSRC_Pos 8
+#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3U_PMC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_pwm.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_pwm.h
new file mode 100644
index 000000000..887bb5dff
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_pwm.h
@@ -0,0 +1,557 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_PWM_COMPONENT_
+#define _SAM3U_PWM_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_PWM Pulse Width Modulation Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief PwmCh_num hardware registers */
+typedef struct {
+  RwReg      PWM_CMR;       /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */
+  RwReg      PWM_CDTY;      /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */
+  RwReg      PWM_CDTYUPD;   /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */
+  RwReg      PWM_CPRD;      /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */
+  RwReg      PWM_CPRDUPD;   /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */
+  RwReg      PWM_CCNT;      /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */
+  RwReg      PWM_DT;        /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */
+  RwReg      PWM_DTUPD;     /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */
+} PwmCh_num;
+/** \brief PwmCmp hardware registers */
+typedef struct {
+  RwReg      PWM_CMPV;      /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */
+  RwReg      PWM_CMPVUPD;   /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */
+  RwReg      PWM_CMPM;      /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */
+  RwReg      PWM_CMPMUPD;   /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */
+} PwmCmp;
+/** \brief Pwm hardware registers */
+#define PWMCMP_NUMBER 8
+#define PWMCH_NUM_NUMBER 4
+typedef struct {
+  RwReg      PWM_CLK;       /**< \brief (Pwm Offset: 0x00) PWM Clock Register */
+  WoReg      PWM_ENA;       /**< \brief (Pwm Offset: 0x04) PWM Enable Register */
+  WoReg      PWM_DIS;       /**< \brief (Pwm Offset: 0x08) PWM Disable Register */
+  RoReg      PWM_SR;        /**< \brief (Pwm Offset: 0x0C) PWM Status Register */
+  WoReg      PWM_IER1;      /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */
+  WoReg      PWM_IDR1;      /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */
+  RoReg      PWM_IMR1;      /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */
+  RoReg      PWM_ISR1;      /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */
+  RwReg      PWM_SCM;       /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */
+  RoReg      Reserved1[1];
+  RwReg      PWM_SCUC;      /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */
+  RwReg      PWM_SCUP;      /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */
+  WoReg      PWM_SCUPUPD;   /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */
+  WoReg      PWM_IER2;      /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */
+  WoReg      PWM_IDR2;      /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */
+  RoReg      PWM_IMR2;      /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */
+  RoReg      PWM_ISR2;      /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */
+  RwReg      PWM_OOV;       /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */
+  RwReg      PWM_OS;        /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */
+  WoReg      PWM_OSS;       /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */
+  WoReg      PWM_OSC;       /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */
+  WoReg      PWM_OSSUPD;    /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */
+  WoReg      PWM_OSCUPD;    /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */
+  RwReg      PWM_FMR;       /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */
+  RoReg      PWM_FSR;       /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */
+  WoReg      PWM_FCR;       /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */
+  RwReg      PWM_FPV;       /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */
+  RwReg      PWM_FPE;       /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */
+  RoReg      Reserved2[3];
+  RwReg      PWM_ELMR[2];   /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */
+  RoReg      Reserved3[24];
+  WoReg      PWM_WPCR;      /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */
+  RoReg      PWM_WPSR;      /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */
+  RoReg      Reserved4[5];
+  RwReg      PWM_RPR;       /**< \brief (Pwm Offset: 0x100) Receive Pointer Register */
+  RwReg      PWM_RCR;       /**< \brief (Pwm Offset: 0x104) Receive Counter Register */
+  RwReg      PWM_TPR;       /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */
+  RwReg      PWM_TCR;       /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */
+  RwReg      PWM_RNPR;      /**< \brief (Pwm Offset: 0x110) Receive Next Pointer Register */
+  RwReg      PWM_RNCR;      /**< \brief (Pwm Offset: 0x114) Receive Next Counter Register */
+  RwReg      PWM_TNPR;      /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */
+  RwReg      PWM_TNCR;      /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */
+  WoReg      PWM_PTCR;      /**< \brief (Pwm Offset: 0x120) Transfer Control Register */
+  RoReg      PWM_PTSR;      /**< \brief (Pwm Offset: 0x124) Transfer Status Register */
+  RoReg      Reserved5[2];
+  PwmCmp     PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */
+  RoReg      Reserved6[20];
+  PwmCh_num  PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */
+} Pwm;
+#endif /* __ASSEMBLY__ */
+/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */
+#define PWM_CLK_DIVA_Pos 0
+#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
+#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))
+#define PWM_CLK_PREA_Pos 8
+#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
+#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))
+#define PWM_CLK_DIVB_Pos 16
+#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
+#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))
+#define PWM_CLK_PREB_Pos 24
+#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
+#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))
+/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
+#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */
+/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
+#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */
+/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
+#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */
+/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */
+#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */
+#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */
+#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */
+#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */
+#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */
+#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */
+#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */
+#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */
+/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */
+#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */
+#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */
+#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */
+#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */
+#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */
+#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */
+#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */
+#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */
+/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */
+#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */
+#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */
+#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */
+#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */
+#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */
+#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */
+#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */
+#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */
+/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */
+#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */
+#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */
+#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */
+#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */
+#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */
+#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */
+#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */
+#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */
+/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */
+#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */
+#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */
+#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */
+#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */
+#define PWM_SCM_UPDM_Pos 16
+#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */
+#define   PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */
+#define   PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */
+#define   PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels */
+#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */
+#define PWM_SCM_PTRCS_Pos 21
+#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */
+#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))
+/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */
+#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */
+/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */
+#define PWM_SCUP_UPR_Pos 0
+#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */
+#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))
+#define PWM_SCUP_UPRCNT_Pos 4
+#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */
+#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))
+/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */
+#define PWM_SCUPUPD_UPRUPD_Pos 0
+#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */
+#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))
+/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */
+#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */
+#define PWM_IER2_ENDTX (0x1u << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */
+#define PWM_IER2_TXBUFE (0x1u << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */
+#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */
+#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */
+#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */
+#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */
+#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */
+#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */
+#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */
+#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */
+#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */
+#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */
+#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */
+#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */
+#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */
+#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */
+#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */
+#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */
+#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */
+/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */
+#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */
+#define PWM_IDR2_ENDTX (0x1u << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */
+#define PWM_IDR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */
+#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */
+#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */
+#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */
+#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */
+#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */
+#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */
+#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */
+#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */
+#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */
+#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */
+#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */
+#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */
+#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */
+#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */
+#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */
+#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */
+#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */
+/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */
+#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */
+#define PWM_IMR2_ENDTX (0x1u << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */
+#define PWM_IMR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */
+#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */
+#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */
+#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */
+#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */
+#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */
+#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */
+#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */
+#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */
+#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */
+#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */
+#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */
+#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */
+#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */
+#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */
+#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */
+#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */
+#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */
+/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */
+#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */
+#define PWM_ISR2_ENDTX (0x1u << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */
+#define PWM_ISR2_TXBUFE (0x1u << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */
+#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */
+#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */
+#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */
+#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */
+#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */
+#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */
+#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */
+#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */
+#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */
+#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */
+#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */
+#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */
+#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */
+#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */
+#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */
+#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */
+#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */
+/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */
+#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */
+#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */
+#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */
+#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */
+#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */
+#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */
+#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */
+#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */
+/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */
+#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */
+#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */
+#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */
+#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */
+#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */
+#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */
+#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */
+#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */
+/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */
+#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */
+#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */
+#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */
+#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */
+#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */
+#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */
+#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */
+#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */
+/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */
+#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */
+#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */
+#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */
+#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */
+#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */
+#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */
+#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */
+#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */
+/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */
+#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */
+#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */
+#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */
+#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */
+#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */
+#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */
+#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */
+#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */
+/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */
+#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */
+#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */
+#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */
+#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */
+#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */
+#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */
+#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */
+#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */
+/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */
+#define PWM_FMR_FPOL_Pos 0
+#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity (fault input bit varies from 0 to 3) */
+#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))
+#define PWM_FMR_FMOD_Pos 8
+#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode (fault input bit varies from 0 to 3) */
+#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))
+#define PWM_FMR_FFIL_Pos 16
+#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering (fault input bit varies from 0 to 3) */
+#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))
+/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */
+#define PWM_FSR_FIV_Pos 0
+#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value (fault input bit varies from 0 to 3) */
+#define PWM_FSR_FS_Pos 8
+#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status (fault input bit varies from 0 to 3) */
+/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */
+#define PWM_FCR_FCLR_Pos 0
+#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear (fault input bit varies from 0 to 3) */
+#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))
+/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */
+#define PWM_FPV_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */
+#define PWM_FPV_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */
+#define PWM_FPV_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */
+#define PWM_FPV_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */
+#define PWM_FPV_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */
+#define PWM_FPV_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */
+#define PWM_FPV_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */
+#define PWM_FPV_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */
+/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */
+#define PWM_FPE_FPE0_Pos 0
+#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 (fault input bit varies from 0 to 3) */
+#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)))
+#define PWM_FPE_FPE1_Pos 8
+#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 (fault input bit varies from 0 to 3) */
+#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)))
+#define PWM_FPE_FPE2_Pos 16
+#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 (fault input bit varies from 0 to 3) */
+#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)))
+#define PWM_FPE_FPE3_Pos 24
+#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 (fault input bit varies from 0 to 3) */
+#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)))
+/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */
+#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */
+#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */
+#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */
+#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */
+#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */
+#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */
+#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */
+#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */
+/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */
+#define PWM_WPCR_WPCMD_Pos 0
+#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protect Command */
+#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))
+#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */
+#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */
+#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */
+#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */
+#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */
+#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */
+#define PWM_WPCR_WPKEY_Pos 8
+#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protect Key */
+#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))
+/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */
+#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */
+#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPVSRC_Pos 16
+#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */
+/* -------- PWM_RPR : (PWM Offset: 0x100) Receive Pointer Register -------- */
+#define PWM_RPR_RXPTR_Pos 0
+#define PWM_RPR_RXPTR_Msk (0xffffffffu << PWM_RPR_RXPTR_Pos) /**< \brief (PWM_RPR) Receive Pointer Register */
+#define PWM_RPR_RXPTR(value) ((PWM_RPR_RXPTR_Msk & ((value) << PWM_RPR_RXPTR_Pos)))
+/* -------- PWM_RCR : (PWM Offset: 0x104) Receive Counter Register -------- */
+#define PWM_RCR_RXCTR_Pos 0
+#define PWM_RCR_RXCTR_Msk (0xffffu << PWM_RCR_RXCTR_Pos) /**< \brief (PWM_RCR) Receive Counter Register */
+#define PWM_RCR_RXCTR(value) ((PWM_RCR_RXCTR_Msk & ((value) << PWM_RCR_RXCTR_Pos)))
+/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */
+#define PWM_TPR_TXPTR_Pos 0
+#define PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos) /**< \brief (PWM_TPR) Transmit Counter Register */
+#define PWM_TPR_TXPTR(value) ((PWM_TPR_TXPTR_Msk & ((value) << PWM_TPR_TXPTR_Pos)))
+/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */
+#define PWM_TCR_TXCTR_Pos 0
+#define PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos) /**< \brief (PWM_TCR) Transmit Counter Register */
+#define PWM_TCR_TXCTR(value) ((PWM_TCR_TXCTR_Msk & ((value) << PWM_TCR_TXCTR_Pos)))
+/* -------- PWM_RNPR : (PWM Offset: 0x110) Receive Next Pointer Register -------- */
+#define PWM_RNPR_RXNPTR_Pos 0
+#define PWM_RNPR_RXNPTR_Msk (0xffffffffu << PWM_RNPR_RXNPTR_Pos) /**< \brief (PWM_RNPR) Receive Next Pointer */
+#define PWM_RNPR_RXNPTR(value) ((PWM_RNPR_RXNPTR_Msk & ((value) << PWM_RNPR_RXNPTR_Pos)))
+/* -------- PWM_RNCR : (PWM Offset: 0x114) Receive Next Counter Register -------- */
+#define PWM_RNCR_RXNCTR_Pos 0
+#define PWM_RNCR_RXNCTR_Msk (0xffffu << PWM_RNCR_RXNCTR_Pos) /**< \brief (PWM_RNCR) Receive Next Counter */
+#define PWM_RNCR_RXNCTR(value) ((PWM_RNCR_RXNCTR_Msk & ((value) << PWM_RNCR_RXNCTR_Pos)))
+/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */
+#define PWM_TNPR_TXNPTR_Pos 0
+#define PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos) /**< \brief (PWM_TNPR) Transmit Next Pointer */
+#define PWM_TNPR_TXNPTR(value) ((PWM_TNPR_TXNPTR_Msk & ((value) << PWM_TNPR_TXNPTR_Pos)))
+/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */
+#define PWM_TNCR_TXNCTR_Pos 0
+#define PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos) /**< \brief (PWM_TNCR) Transmit Counter Next */
+#define PWM_TNCR_TXNCTR(value) ((PWM_TNCR_TXNCTR_Msk & ((value) << PWM_TNCR_TXNCTR_Pos)))
+/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */
+#define PWM_PTCR_RXTEN (0x1u << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */
+#define PWM_PTCR_RXTDIS (0x1u << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */
+#define PWM_PTCR_TXTEN (0x1u << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */
+#define PWM_PTCR_TXTDIS (0x1u << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */
+/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */
+#define PWM_PTSR_RXTEN (0x1u << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */
+#define PWM_PTSR_TXTEN (0x1u << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */
+/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */
+#define PWM_CMPV_CV_Pos 0
+#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */
+#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))
+#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */
+/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */
+#define PWM_CMPVUPD_CVUPD_Pos 0
+#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */
+#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))
+#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */
+/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */
+#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */
+#define PWM_CMPM_CTR_Pos 4
+#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */
+#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))
+#define PWM_CMPM_CPR_Pos 8
+#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */
+#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))
+#define PWM_CMPM_CPRCNT_Pos 12
+#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */
+#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))
+#define PWM_CMPM_CUPR_Pos 16
+#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */
+#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))
+#define PWM_CMPM_CUPRCNT_Pos 20
+#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */
+#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))
+/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */
+#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */
+#define PWM_CMPMUPD_CTRUPD_Pos 4
+#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */
+#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))
+#define PWM_CMPMUPD_CPRUPD_Pos 8
+#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */
+#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))
+#define PWM_CMPMUPD_CUPRUPD_Pos 16
+#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */
+#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))
+/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */
+#define PWM_CMR_CPRE_Pos 0
+#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */
+#define   PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master clock */
+#define   PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Master clock/2 */
+#define   PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Master clock/4 */
+#define   PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Master clock/8 */
+#define   PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Master clock/16 */
+#define   PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Master clock/32 */
+#define   PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Master clock/64 */
+#define   PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Master clock/128 */
+#define   PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Master clock/256 */
+#define   PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Master clock/512 */
+#define   PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Master clock/1024 */
+#define   PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */
+#define   PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */
+#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */
+#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */
+#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */
+#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */
+#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */
+#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */
+/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */
+#define PWM_CDTY_CDTY_Pos 0
+#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */
+#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))
+/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */
+#define PWM_CDTYUPD_CDTYUPD_Pos 0
+#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */
+#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))
+/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */
+#define PWM_CPRD_CPRD_Pos 0
+#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */
+#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))
+/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */
+#define PWM_CPRDUPD_CPRDUPD_Pos 0
+#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */
+#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))
+/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */
+#define PWM_CCNT_CNT_Pos 0
+#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */
+/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */
+#define PWM_DT_DTH_Pos 0
+#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */
+#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))
+#define PWM_DT_DTL_Pos 16
+#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */
+#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))
+/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */
+#define PWM_DTUPD_DTHUPD_Pos 0
+#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */
+#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))
+#define PWM_DTUPD_DTLUPD_Pos 16
+#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */
+#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3U_PWM_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_rstc.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_rstc.h
new file mode 100644
index 000000000..f4800780f
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_rstc.h
@@ -0,0 +1,73 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_RSTC_COMPONENT_
+#define _SAM3U_RSTC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Reset Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_RSTC Reset Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Rstc hardware registers */
+typedef struct {
+  WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
+  RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
+  RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
+} Rstc;
+#endif /* __ASSEMBLY__ */
+/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
+#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */
+#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */
+#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */
+#define RSTC_CR_KEY_Pos 24
+#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Password */
+#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
+/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
+#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */
+#define RSTC_SR_RSTTYP_Pos 8
+#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */
+#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
+#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
+/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
+#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */
+#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
+#define RSTC_MR_ERSTL_Pos 8
+#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */
+#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
+#define RSTC_MR_KEY_Pos 24
+#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */
+#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3U_RSTC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_rtc.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_rtc.h
new file mode 100644
index 000000000..61c906158
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_rtc.h
@@ -0,0 +1,168 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_RTC_COMPONENT_
+#define _SAM3U_RTC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Real-time Clock */
+/* ============================================================================= */
+/** \addtogroup SAM3U_RTC Real-time Clock */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Rtc hardware registers */
+typedef struct {
+  RwReg RTC_CR;        /**< \brief (Rtc Offset: 0x00) Control Register */
+  RwReg RTC_MR;        /**< \brief (Rtc Offset: 0x04) Mode Register */
+  RwReg RTC_TIMR;      /**< \brief (Rtc Offset: 0x08) Time Register */
+  RwReg RTC_CALR;      /**< \brief (Rtc Offset: 0x0C) Calendar Register */
+  RwReg RTC_TIMALR;    /**< \brief (Rtc Offset: 0x10) Time Alarm Register */
+  RwReg RTC_CALALR;    /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */
+  RoReg RTC_SR;        /**< \brief (Rtc Offset: 0x18) Status Register */
+  WoReg RTC_SCCR;      /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */
+  WoReg RTC_IER;       /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */
+  WoReg RTC_IDR;       /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */
+  RoReg RTC_IMR;       /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */
+  RoReg RTC_VER;       /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */
+  RoReg Reserved1[45];
+  RwReg RTC_WPMR;      /**< \brief (Rtc Offset: 0xE4) Write Protect Mode Register */
+} Rtc;
+#endif /* __ASSEMBLY__ */
+/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
+#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */
+#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */
+#define RTC_CR_TIMEVSEL_Pos 8
+#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */
+#define   RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */
+#define   RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */
+#define   RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */
+#define   RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */
+#define RTC_CR_CALEVSEL_Pos 16
+#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */
+#define   RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */
+#define   RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */
+#define   RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */
+/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
+#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */
+/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
+#define RTC_TIMR_SEC_Pos 0
+#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */
+#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
+#define RTC_TIMR_MIN_Pos 8
+#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */
+#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
+#define RTC_TIMR_HOUR_Pos 16
+#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */
+#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
+#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */
+/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
+#define RTC_CALR_CENT_Pos 0
+#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */
+#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
+#define RTC_CALR_YEAR_Pos 8
+#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */
+#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
+#define RTC_CALR_MONTH_Pos 16
+#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */
+#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
+#define RTC_CALR_DAY_Pos 21
+#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */
+#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
+#define RTC_CALR_DATE_Pos 24
+#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */
+#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
+/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
+#define RTC_TIMALR_SEC_Pos 0
+#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */
+#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
+#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */
+#define RTC_TIMALR_MIN_Pos 8
+#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */
+#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
+#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */
+#define RTC_TIMALR_HOUR_Pos 16
+#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */
+#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
+#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */
+#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */
+/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
+#define RTC_CALALR_MONTH_Pos 16
+#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */
+#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
+#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */
+#define RTC_CALALR_DATE_Pos 24
+#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */
+#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
+#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */
+/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
+#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */
+#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */
+#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */
+#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */
+#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */
+/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
+#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */
+#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */
+#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */
+#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */
+#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */
+/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
+#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */
+#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */
+#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */
+#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */
+#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */
+/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
+#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */
+#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */
+#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */
+#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */
+#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */
+/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
+#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */
+#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */
+#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */
+#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */
+#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */
+/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
+#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */
+#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */
+#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */
+#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */
+/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protect Mode Register -------- */
+#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protect Enable */
+#define RTC_WPMR_WPKEY_Pos 8
+#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR)  */
+#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3U_RTC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_rtt.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_rtt.h
new file mode 100644
index 000000000..72780b0d6
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_rtt.h
@@ -0,0 +1,69 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_RTT_COMPONENT_
+#define _SAM3U_RTT_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Real-time Timer */
+/* ============================================================================= */
+/** \addtogroup SAM3U_RTT Real-time Timer */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Rtt hardware registers */
+typedef struct {
+  RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */
+  RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */
+  RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */
+  RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */
+} Rtt;
+#endif /* __ASSEMBLY__ */
+/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */
+#define RTT_MR_RTPRES_Pos 0
+#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */
+#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)))
+#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */
+#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */
+#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */
+/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */
+#define RTT_AR_ALMV_Pos 0
+#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */
+#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)))
+/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */
+#define RTT_VR_CRTV_Pos 0
+#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */
+/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */
+#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */
+#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */
+
+/*@}*/
+
+
+#endif /* _SAM3U_RTT_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_smc.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_smc.h
new file mode 100644
index 000000000..8effce490
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_smc.h
@@ -0,0 +1,485 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_SMC_COMPONENT_
+#define _SAM3U_SMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Static Memory Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_SMC Static Memory Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief SmcCs_number hardware registers */
+typedef struct {
+  RwReg         SMC_SETUP;        /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */
+  RwReg         SMC_PULSE;        /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */
+  RwReg         SMC_CYCLE;        /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */
+  RwReg         SMC_TIMINGS;      /**< \brief (SmcCs_number Offset: 0xC) SMC Timings Register */
+  RwReg         SMC_MODE;         /**< \brief (SmcCs_number Offset: 0x10) SMC Mode Register */
+} SmcCs_number;
+/** \brief Smc hardware registers */
+#define SMCCS_NUMBER_NUMBER 4
+typedef struct {
+  RwReg         SMC_CFG;          /**< \brief (Smc Offset: 0x000) SMC NFC Configuration Register */
+  WoReg         SMC_CTRL;         /**< \brief (Smc Offset: 0x004) SMC NFC Control Register */
+  RoReg         SMC_SR;           /**< \brief (Smc Offset: 0x008) SMC NFC Status Register */
+  WoReg         SMC_IER;          /**< \brief (Smc Offset: 0x00C) SMC NFC Interrupt Enable Register */
+  WoReg         SMC_IDR;          /**< \brief (Smc Offset: 0x010) SMC NFC Interrupt Disable Register */
+  RoReg         SMC_IMR;          /**< \brief (Smc Offset: 0x014) SMC NFC Interrupt Mask Register */
+  RwReg         SMC_ADDR;         /**< \brief (Smc Offset: 0x018) SMC NFC Address Cycle Zero Register */
+  RwReg         SMC_BANK;         /**< \brief (Smc Offset: 0x01C) SMC Bank Address Register */
+  WoReg         SMC_ECC_CTRL;     /**< \brief (Smc Offset: 0x020) SMC ECC Control Register */
+  RwReg         SMC_ECC_MD;       /**< \brief (Smc Offset: 0x024) SMC ECC Mode Register */
+  RoReg         SMC_ECC_SR1;      /**< \brief (Smc Offset: 0x028) SMC ECC Status 1 Register */
+  RoReg         SMC_ECC_PR0;      /**< \brief (Smc Offset: 0x02C) SMC ECC Parity 0 Register */
+  RoReg         SMC_ECC_PR1;      /**< \brief (Smc Offset: 0x030) SMC ECC parity 1 Register */
+  RoReg         SMC_ECC_SR2;      /**< \brief (Smc Offset: 0x034) SMC ECC status 2 Register */
+  RoReg         SMC_ECC_PR2;      /**< \brief (Smc Offset: 0x038) SMC ECC parity 2 Register */
+  RoReg         SMC_ECC_PR3;      /**< \brief (Smc Offset: 0x03C) SMC ECC parity 3 Register */
+  RoReg         SMC_ECC_PR4;      /**< \brief (Smc Offset: 0x040) SMC ECC parity 4 Register */
+  RoReg         SMC_ECC_PR5;      /**< \brief (Smc Offset: 0x044) SMC ECC parity 5 Register */
+  RoReg         SMC_ECC_PR6;      /**< \brief (Smc Offset: 0x048) SMC ECC parity 6 Register */
+  RoReg         SMC_ECC_PR7;      /**< \brief (Smc Offset: 0x04C) SMC ECC parity 7 Register */
+  RoReg         SMC_ECC_PR8;      /**< \brief (Smc Offset: 0x050) SMC ECC parity 8 Register */
+  RoReg         SMC_ECC_PR9;      /**< \brief (Smc Offset: 0x054) SMC ECC parity 9 Register */
+  RoReg         SMC_ECC_PR10;     /**< \brief (Smc Offset: 0x058) SMC ECC parity 10 Register */
+  RoReg         SMC_ECC_PR11;     /**< \brief (Smc Offset: 0x05C) SMC ECC parity 11 Register */
+  RoReg         SMC_ECC_PR12;     /**< \brief (Smc Offset: 0x060) SMC ECC parity 12 Register */
+  RoReg         SMC_ECC_PR13;     /**< \brief (Smc Offset: 0x064) SMC ECC parity 13 Register */
+  RoReg         SMC_ECC_PR14;     /**< \brief (Smc Offset: 0x068) SMC ECC parity 14 Register */
+  RoReg         SMC_ECC_PR15;     /**< \brief (Smc Offset: 0x06C) SMC ECC parity 15 Register */
+  SmcCs_number  SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x70) CS_number = 0 .. 3 */
+  RoReg         Reserved1[20];
+  RwReg         SMC_OCMS;         /**< \brief (Smc Offset: 0x110) SMC OCMS Register */
+  WoReg         SMC_KEY1;         /**< \brief (Smc Offset: 0x114) SMC OCMS KEY1 Register */
+  WoReg         SMC_KEY2;         /**< \brief (Smc Offset: 0x118) SMC OCMS KEY2 Register */
+  RoReg         Reserved2[50];
+  WoReg         SMC_WPCR;         /**< \brief (Smc Offset: 0x1E4) Write Protection Control Register */
+  RoReg         SMC_WPSR;         /**< \brief (Smc Offset: 0x1E8) Write Protection Status Register */
+} Smc;
+#endif /* __ASSEMBLY__ */
+/* -------- SMC_CFG : (SMC Offset: 0x000) SMC NFC Configuration Register -------- */
+#define SMC_CFG_PAGESIZE_Pos 0
+#define SMC_CFG_PAGESIZE_Msk (0x3u << SMC_CFG_PAGESIZE_Pos) /**< \brief (SMC_CFG)  */
+#define   SMC_CFG_PAGESIZE_PS512_16 (0x0u << 0) /**< \brief (SMC_CFG) Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes */
+#define   SMC_CFG_PAGESIZE_PS1024_32 (0x1u << 0) /**< \brief (SMC_CFG) Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes */
+#define   SMC_CFG_PAGESIZE_PS2048_64 (0x2u << 0) /**< \brief (SMC_CFG) Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes */
+#define   SMC_CFG_PAGESIZE_PS4096_128 (0x3u << 0) /**< \brief (SMC_CFG) Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes */
+#define SMC_CFG_WSPARE (0x1u << 8) /**< \brief (SMC_CFG) Write Spare Area */
+#define SMC_CFG_RSPARE (0x1u << 9) /**< \brief (SMC_CFG) Read Spare Area */
+#define SMC_CFG_EDGECTRL (0x1u << 12) /**< \brief (SMC_CFG) Rising/Falling Edge Detection Control */
+#define SMC_CFG_RBEDGE (0x1u << 13) /**< \brief (SMC_CFG) Ready/Busy Signal Edge Detection */
+#define SMC_CFG_DTOCYC_Pos 16
+#define SMC_CFG_DTOCYC_Msk (0xfu << SMC_CFG_DTOCYC_Pos) /**< \brief (SMC_CFG) Data Timeout Cycle Number */
+#define SMC_CFG_DTOCYC(value) ((SMC_CFG_DTOCYC_Msk & ((value) << SMC_CFG_DTOCYC_Pos)))
+#define SMC_CFG_DTOMUL_Pos 20
+#define SMC_CFG_DTOMUL_Msk (0x7u << SMC_CFG_DTOMUL_Pos) /**< \brief (SMC_CFG) Data Timeout Multiplier */
+#define   SMC_CFG_DTOMUL_X1 (0x0u << 20) /**< \brief (SMC_CFG) DTOCYC */
+#define   SMC_CFG_DTOMUL_X16 (0x1u << 20) /**< \brief (SMC_CFG) DTOCYC x 16 */
+#define   SMC_CFG_DTOMUL_X128 (0x2u << 20) /**< \brief (SMC_CFG) DTOCYC x 128 */
+#define   SMC_CFG_DTOMUL_X256 (0x3u << 20) /**< \brief (SMC_CFG) DTOCYC x 256 */
+#define   SMC_CFG_DTOMUL_X1024 (0x4u << 20) /**< \brief (SMC_CFG) DTOCYC x 1024 */
+#define   SMC_CFG_DTOMUL_X4096 (0x5u << 20) /**< \brief (SMC_CFG) DTOCYC x 4096 */
+#define   SMC_CFG_DTOMUL_X65536 (0x6u << 20) /**< \brief (SMC_CFG) DTOCYC x 65536 */
+#define   SMC_CFG_DTOMUL_X1048576 (0x7u << 20) /**< \brief (SMC_CFG) DTOCYC x 1048576 */
+/* -------- SMC_CTRL : (SMC Offset: 0x004) SMC NFC Control Register -------- */
+#define SMC_CTRL_NFCEN (0x1u << 0) /**< \brief (SMC_CTRL) NAND Flash Controller Enable */
+#define SMC_CTRL_NFCDIS (0x1u << 1) /**< \brief (SMC_CTRL) NAND Flash Controller Disable */
+/* -------- SMC_SR : (SMC Offset: 0x008) SMC NFC Status Register -------- */
+#define SMC_SR_SMCSTS (0x1u << 0) /**< \brief (SMC_SR) NAND Flash Controller status (this field cannot be reset) */
+#define SMC_SR_RB_RISE (0x1u << 4) /**< \brief (SMC_SR) Selected Ready Busy Rising Edge Detected */
+#define SMC_SR_RB_FALL (0x1u << 5) /**< \brief (SMC_SR) Selected Ready Busy Falling Edge Detected */
+#define SMC_SR_NFCBUSY (0x1u << 8) /**< \brief (SMC_SR) NFC Busy (this field cannot be reset) */
+#define SMC_SR_NFCWR (0x1u << 11) /**< \brief (SMC_SR) NFC Write/Read Operation (this field cannot be reset) */
+#define SMC_SR_NFCSID_Pos 12
+#define SMC_SR_NFCSID_Msk (0x7u << SMC_SR_NFCSID_Pos) /**< \brief (SMC_SR) NFC Chip Select ID (this field cannot be reset) */
+#define SMC_SR_XFRDONE (0x1u << 16) /**< \brief (SMC_SR) NFC Data Transfer Terminated */
+#define SMC_SR_CMDDONE (0x1u << 17) /**< \brief (SMC_SR) Command Done */
+#define SMC_SR_DTOE (0x1u << 20) /**< \brief (SMC_SR) Data Timeout Error */
+#define SMC_SR_UNDEF (0x1u << 21) /**< \brief (SMC_SR) Undefined Area Error */
+#define SMC_SR_AWB (0x1u << 22) /**< \brief (SMC_SR) Accessing While Busy */
+#define SMC_SR_NFCASE (0x1u << 23) /**< \brief (SMC_SR) NFC Access Size Error */
+#define SMC_SR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_SR) Ready/Busy Line 0 Edge Detected */
+/* -------- SMC_IER : (SMC Offset: 0x00C) SMC NFC Interrupt Enable Register -------- */
+#define SMC_IER_RB_RISE (0x1u << 4) /**< \brief (SMC_IER) Ready Busy Rising Edge Detection Interrupt Enable */
+#define SMC_IER_RB_FALL (0x1u << 5) /**< \brief (SMC_IER) Ready Busy Falling Edge Detection Interrupt Enable */
+#define SMC_IER_XFRDONE (0x1u << 16) /**< \brief (SMC_IER) Transfer Done Interrupt Enable */
+#define SMC_IER_CMDDONE (0x1u << 17) /**< \brief (SMC_IER) Command Done Interrupt Enable */
+#define SMC_IER_DTOE (0x1u << 20) /**< \brief (SMC_IER) Data Timeout Error Interrupt Enable */
+#define SMC_IER_UNDEF (0x1u << 21) /**< \brief (SMC_IER) Undefined Area Access Interrupt Enable */
+#define SMC_IER_AWB (0x1u << 22) /**< \brief (SMC_IER) Accessing While Busy Interrupt Enable */
+#define SMC_IER_NFCASE (0x1u << 23) /**< \brief (SMC_IER) NFC Access Size Error Interrupt Enable */
+#define SMC_IER_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IER) Ready/Busy Line 0 Interrupt Enable */
+/* -------- SMC_IDR : (SMC Offset: 0x010) SMC NFC Interrupt Disable Register -------- */
+#define SMC_IDR_RB_RISE (0x1u << 4) /**< \brief (SMC_IDR) Ready Busy Rising Edge Detection Interrupt Disable */
+#define SMC_IDR_RB_FALL (0x1u << 5) /**< \brief (SMC_IDR) Ready Busy Falling Edge Detection Interrupt Disable */
+#define SMC_IDR_XFRDONE (0x1u << 16) /**< \brief (SMC_IDR) Transfer Done Interrupt Disable */
+#define SMC_IDR_CMDDONE (0x1u << 17) /**< \brief (SMC_IDR) Command Done Interrupt Disable */
+#define SMC_IDR_DTOE (0x1u << 20) /**< \brief (SMC_IDR) Data Timeout Error Interrupt Disable */
+#define SMC_IDR_UNDEF (0x1u << 21) /**< \brief (SMC_IDR) Undefined Area Access Interrupt Disable */
+#define SMC_IDR_AWB (0x1u << 22) /**< \brief (SMC_IDR) Accessing While Busy Interrupt Disable */
+#define SMC_IDR_NFCASE (0x1u << 23) /**< \brief (SMC_IDR) NFC Access Size Error Interrupt Disable */
+#define SMC_IDR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IDR) Ready/Busy Line 0 Interrupt Disable */
+/* -------- SMC_IMR : (SMC Offset: 0x014) SMC NFC Interrupt Mask Register -------- */
+#define SMC_IMR_RB_RISE (0x1u << 4) /**< \brief (SMC_IMR) Ready Busy Rising Edge Detection Interrupt Mask */
+#define SMC_IMR_RB_FALL (0x1u << 5) /**< \brief (SMC_IMR) Ready Busy Falling Edge Detection Interrupt Mask */
+#define SMC_IMR_XFRDONE (0x1u << 16) /**< \brief (SMC_IMR) Transfer Done Interrupt Mask */
+#define SMC_IMR_CMDDONE (0x1u << 17) /**< \brief (SMC_IMR) Command Done Interrupt Mask */
+#define SMC_IMR_DTOE (0x1u << 20) /**< \brief (SMC_IMR) Data Timeout Error Interrupt Mask */
+#define SMC_IMR_UNDEF (0x1u << 21) /**< \brief (SMC_IMR) Undefined Area Access Interrupt Mask5 */
+#define SMC_IMR_AWB (0x1u << 22) /**< \brief (SMC_IMR) Accessing While Busy Interrupt Mask */
+#define SMC_IMR_NFCASE (0x1u << 23) /**< \brief (SMC_IMR) NFC Access Size Error Interrupt Mask */
+#define SMC_IMR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IMR) Ready/Busy Line 0 Interrupt Mask */
+/* -------- SMC_ADDR : (SMC Offset: 0x018) SMC NFC Address Cycle Zero Register -------- */
+#define SMC_ADDR_ADDR_CYCLE0_Pos 0
+#define SMC_ADDR_ADDR_CYCLE0_Msk (0xffu << SMC_ADDR_ADDR_CYCLE0_Pos) /**< \brief (SMC_ADDR) NAND Flash Array Address cycle 0 */
+#define SMC_ADDR_ADDR_CYCLE0(value) ((SMC_ADDR_ADDR_CYCLE0_Msk & ((value) << SMC_ADDR_ADDR_CYCLE0_Pos)))
+/* -------- SMC_BANK : (SMC Offset: 0x01C) SMC Bank Address Register -------- */
+#define SMC_BANK_BANK_Pos 0
+#define SMC_BANK_BANK_Msk (0x7u << SMC_BANK_BANK_Pos) /**< \brief (SMC_BANK) Bank Identifier */
+#define SMC_BANK_BANK(value) ((SMC_BANK_BANK_Msk & ((value) << SMC_BANK_BANK_Pos)))
+/* -------- SMC_ECC_CTRL : (SMC Offset: 0x020) SMC ECC Control Register -------- */
+#define SMC_ECC_CTRL_RST (0x1u << 0) /**< \brief (SMC_ECC_CTRL) Reset ECC */
+#define SMC_ECC_CTRL_SWRST (0x1u << 1) /**< \brief (SMC_ECC_CTRL) Software Reset */
+/* -------- SMC_ECC_MD : (SMC Offset: 0x024) SMC ECC Mode Register -------- */
+#define SMC_ECC_MD_ECC_PAGESIZE_Pos 0
+#define SMC_ECC_MD_ECC_PAGESIZE_Msk (0x3u << SMC_ECC_MD_ECC_PAGESIZE_Pos) /**< \brief (SMC_ECC_MD) ECC Page Size */
+#define   SMC_ECC_MD_ECC_PAGESIZE_PS512_16 (0x0u << 0) /**< \brief (SMC_ECC_MD) Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes */
+#define   SMC_ECC_MD_ECC_PAGESIZE_PS1024_32 (0x1u << 0) /**< \brief (SMC_ECC_MD) Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes */
+#define   SMC_ECC_MD_ECC_PAGESIZE_PS2048_64 (0x2u << 0) /**< \brief (SMC_ECC_MD) Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes */
+#define   SMC_ECC_MD_ECC_PAGESIZE_PS4096_128 (0x3u << 0) /**< \brief (SMC_ECC_MD) Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes */
+#define SMC_ECC_MD_TYPCORREC_Pos 4
+#define SMC_ECC_MD_TYPCORREC_Msk (0x3u << SMC_ECC_MD_TYPCORREC_Pos) /**< \brief (SMC_ECC_MD) Type of Correction */
+#define   SMC_ECC_MD_TYPCORREC_CPAGE (0x0u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for a page of 512/1024/2048/4096 Bytes  (for 8 or 16-bit NAND Flash) */
+#define   SMC_ECC_MD_TYPCORREC_C256B (0x1u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for 256 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) */
+#define   SMC_ECC_MD_TYPCORREC_C512B (0x2u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for 512 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) */
+/* -------- SMC_ECC_SR1 : (SMC Offset: 0x028) SMC ECC Status 1 Register -------- */
+#define SMC_ECC_SR1_RECERR0 (0x1u << 0) /**< \brief (SMC_ECC_SR1) Recoverable Error */
+#define SMC_ECC_SR1_ECCERR0_Pos 1
+#define SMC_ECC_SR1_ECCERR0_Msk (0x3u << SMC_ECC_SR1_ECCERR0_Pos) /**< \brief (SMC_ECC_SR1) ECC Error */
+#define SMC_ECC_SR1_RECERR1 (0x1u << 4) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 256th and the 511th bytes or the 512nd and the 1023rd bytes */
+#define SMC_ECC_SR1_ECCERR1 (0x1u << 5) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */
+#define SMC_ECC_SR1_MULERR1 (0x1u << 6) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */
+#define SMC_ECC_SR1_RECERR2 (0x1u << 8) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
+#define SMC_ECC_SR1_ECCERR2 (0x1u << 9) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
+#define SMC_ECC_SR1_MULERR2 (0x1u << 10) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
+#define SMC_ECC_SR1_RECERR3 (0x1u << 12) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
+#define SMC_ECC_SR1_ECCERR3 (0x1u << 13) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
+#define SMC_ECC_SR1_MULERR3 (0x1u << 14) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
+#define SMC_ECC_SR1_RECERR4 (0x1u << 16) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */
+#define SMC_ECC_SR1_ECCERR4_Pos 17
+#define SMC_ECC_SR1_ECCERR4_Msk (0x3u << SMC_ECC_SR1_ECCERR4_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */
+#define SMC_ECC_SR1_RECERR5 (0x1u << 20) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */
+#define SMC_ECC_SR1_ECCERR5_Pos 21
+#define SMC_ECC_SR1_ECCERR5_Msk (0x3u << SMC_ECC_SR1_ECCERR5_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */
+#define SMC_ECC_SR1_RECERR6 (0x1u << 24) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */
+#define SMC_ECC_SR1_ECCERR6_Pos 25
+#define SMC_ECC_SR1_ECCERR6_Msk (0x3u << SMC_ECC_SR1_ECCERR6_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */
+#define SMC_ECC_SR1_RECERR7 (0x1u << 28) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */
+#define SMC_ECC_SR1_ECCERR7_Pos 29
+#define SMC_ECC_SR1_ECCERR7_Msk (0x3u << SMC_ECC_SR1_ECCERR7_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */
+/* -------- SMC_ECC_PR0 : (SMC Offset: 0x02C) SMC ECC Parity 0 Register -------- */
+#define SMC_ECC_PR0_BITADDR_Pos 0
+#define SMC_ECC_PR0_BITADDR_Msk (0xfu << SMC_ECC_PR0_BITADDR_Pos) /**< \brief (SMC_ECC_PR0) Bit Address */
+#define SMC_ECC_PR0_WORDADDR_Pos 4
+#define SMC_ECC_PR0_WORDADDR_Msk (0xfffu << SMC_ECC_PR0_WORDADDR_Pos) /**< \brief (SMC_ECC_PR0) Word Address */
+#define SMC_ECC_PR0_BITADDR_W9BIT_Pos 0
+#define SMC_ECC_PR0_BITADDR_W9BIT_Msk (0x7u << SMC_ECC_PR0_BITADDR_W9BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_WORDADDR_W9BIT_Pos 3
+#define SMC_ECC_PR0_WORDADDR_W9BIT_Msk (0x1ffu << SMC_ECC_PR0_WORDADDR_W9BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_NPARITY_Pos 12
+#define SMC_ECC_PR0_NPARITY_Msk (0xfffu << SMC_ECC_PR0_NPARITY_Pos) /**< \brief (SMC_ECC_PR0) Parity N */
+#define SMC_ECC_PR0_BITADDR_W8BIT_Pos 0
+#define SMC_ECC_PR0_BITADDR_W8BIT_Msk (0x7u << SMC_ECC_PR0_BITADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR0_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR0_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR0_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR0_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Parity N */
+/* -------- SMC_ECC_PR1 : (SMC Offset: 0x030) SMC ECC parity 1 Register -------- */
+#define SMC_ECC_PR1_NPARITY_Pos 0
+#define SMC_ECC_PR1_NPARITY_Msk (0xffffu << SMC_ECC_PR1_NPARITY_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
+#define SMC_ECC_PR1_BITADDR_Pos 0
+#define SMC_ECC_PR1_BITADDR_Msk (0x7u << SMC_ECC_PR1_BITADDR_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR1_WORDADDR_Pos 3
+#define SMC_ECC_PR1_WORDADDR_Msk (0x1ffu << SMC_ECC_PR1_WORDADDR_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR1_NPARITY_W9BIT_Pos 12
+#define SMC_ECC_PR1_NPARITY_W9BIT_Msk (0xfffu << SMC_ECC_PR1_NPARITY_W9BIT_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
+#define SMC_ECC_PR1_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR1_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR1_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR1_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR1_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR1_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
+/* -------- SMC_ECC_SR2 : (SMC Offset: 0x034) SMC ECC status 2 Register -------- */
+#define SMC_ECC_SR2_RECERR8 (0x1u << 0) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2048th and the 2303rd bytes */
+#define SMC_ECC_SR2_ECCERR8_Pos 1
+#define SMC_ECC_SR2_ECCERR8_Msk (0x3u << SMC_ECC_SR2_ECCERR8_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2048th and the 2303rd bytes */
+#define SMC_ECC_SR2_RECERR9 (0x1u << 4) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2304th and the 2559th bytes */
+#define SMC_ECC_SR2_ECCERR9 (0x1u << 5) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2304th and the 2559th bytes */
+#define SMC_ECC_SR2_MULERR9 (0x1u << 6) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2304th and the 2559th bytes */
+#define SMC_ECC_SR2_RECERR10 (0x1u << 8) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2560th and the 2815th bytes */
+#define SMC_ECC_SR2_ECCERR10 (0x1u << 9) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2560th and the 2815th bytes */
+#define SMC_ECC_SR2_MULERR10 (0x1u << 10) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2560th and the 2815th bytes */
+#define SMC_ECC_SR2_RECERR11 (0x1u << 12) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2816th and the 3071st bytes */
+#define SMC_ECC_SR2_ECCERR11 (0x1u << 13) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2816th and the 3071st bytes */
+#define SMC_ECC_SR2_MULERR11 (0x1u << 14) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2816th and the 3071st bytes */
+#define SMC_ECC_SR2_RECERR12 (0x1u << 16) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3072nd and the 3327th bytes */
+#define SMC_ECC_SR2_ECCERR12_Pos 17
+#define SMC_ECC_SR2_ECCERR12_Msk (0x3u << SMC_ECC_SR2_ECCERR12_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3072nd and the 3327th bytes */
+#define SMC_ECC_SR2_RECERR13 (0x1u << 20) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3328th and the 3583rd bytes */
+#define SMC_ECC_SR2_ECCERR13_Pos 21
+#define SMC_ECC_SR2_ECCERR13_Msk (0x3u << SMC_ECC_SR2_ECCERR13_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3328th and the 3583rd bytes */
+#define SMC_ECC_SR2_RECERR14 (0x1u << 24) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3584th and the 3839th bytes */
+#define SMC_ECC_SR2_ECCERR14_Pos 25
+#define SMC_ECC_SR2_ECCERR14_Msk (0x3u << SMC_ECC_SR2_ECCERR14_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3584th and the 3839th bytes */
+#define SMC_ECC_SR2_RECERR15 (0x1u << 28) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3840th and the 4095th bytes */
+#define SMC_ECC_SR2_ECCERR15_Pos 29
+#define SMC_ECC_SR2_ECCERR15_Msk (0x3u << SMC_ECC_SR2_ECCERR15_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3840th and the 4095th bytes */
+/* -------- SMC_ECC_PR2 : (SMC Offset: 0x038) SMC ECC parity 2 Register -------- */
+#define SMC_ECC_PR2_BITADDR_Pos 0
+#define SMC_ECC_PR2_BITADDR_Msk (0x7u << SMC_ECC_PR2_BITADDR_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR2_WORDADDR_Pos 3
+#define SMC_ECC_PR2_WORDADDR_Msk (0x1ffu << SMC_ECC_PR2_WORDADDR_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR2_NPARITY_Pos 12
+#define SMC_ECC_PR2_NPARITY_Msk (0xfffu << SMC_ECC_PR2_NPARITY_Pos) /**< \brief (SMC_ECC_PR2) Parity N */
+#define SMC_ECC_PR2_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR2_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR2_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR2_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR2_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR2_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR2) Parity N */
+/* -------- SMC_ECC_PR3 : (SMC Offset: 0x03C) SMC ECC parity 3 Register -------- */
+#define SMC_ECC_PR3_BITADDR_Pos 0
+#define SMC_ECC_PR3_BITADDR_Msk (0x7u << SMC_ECC_PR3_BITADDR_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR3_WORDADDR_Pos 3
+#define SMC_ECC_PR3_WORDADDR_Msk (0x1ffu << SMC_ECC_PR3_WORDADDR_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR3_NPARITY_Pos 12
+#define SMC_ECC_PR3_NPARITY_Msk (0xfffu << SMC_ECC_PR3_NPARITY_Pos) /**< \brief (SMC_ECC_PR3) Parity N */
+#define SMC_ECC_PR3_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR3_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR3_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR3_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR3_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR3_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR3) Parity N */
+/* -------- SMC_ECC_PR4 : (SMC Offset: 0x040) SMC ECC parity 4 Register -------- */
+#define SMC_ECC_PR4_BITADDR_Pos 0
+#define SMC_ECC_PR4_BITADDR_Msk (0x7u << SMC_ECC_PR4_BITADDR_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR4_WORDADDR_Pos 3
+#define SMC_ECC_PR4_WORDADDR_Msk (0x1ffu << SMC_ECC_PR4_WORDADDR_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR4_NPARITY_Pos 12
+#define SMC_ECC_PR4_NPARITY_Msk (0xfffu << SMC_ECC_PR4_NPARITY_Pos) /**< \brief (SMC_ECC_PR4) Parity N */
+#define SMC_ECC_PR4_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR4_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR4_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR4_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR4_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR4_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR4) Parity N */
+/* -------- SMC_ECC_PR5 : (SMC Offset: 0x044) SMC ECC parity 5 Register -------- */
+#define SMC_ECC_PR5_BITADDR_Pos 0
+#define SMC_ECC_PR5_BITADDR_Msk (0x7u << SMC_ECC_PR5_BITADDR_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR5_WORDADDR_Pos 3
+#define SMC_ECC_PR5_WORDADDR_Msk (0x1ffu << SMC_ECC_PR5_WORDADDR_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR5_NPARITY_Pos 12
+#define SMC_ECC_PR5_NPARITY_Msk (0xfffu << SMC_ECC_PR5_NPARITY_Pos) /**< \brief (SMC_ECC_PR5) Parity N */
+#define SMC_ECC_PR5_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR5_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR5_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR5_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR5_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR5_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR5) Parity N */
+/* -------- SMC_ECC_PR6 : (SMC Offset: 0x048) SMC ECC parity 6 Register -------- */
+#define SMC_ECC_PR6_BITADDR_Pos 0
+#define SMC_ECC_PR6_BITADDR_Msk (0x7u << SMC_ECC_PR6_BITADDR_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR6_WORDADDR_Pos 3
+#define SMC_ECC_PR6_WORDADDR_Msk (0x1ffu << SMC_ECC_PR6_WORDADDR_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR6_NPARITY_Pos 12
+#define SMC_ECC_PR6_NPARITY_Msk (0xfffu << SMC_ECC_PR6_NPARITY_Pos) /**< \brief (SMC_ECC_PR6) Parity N */
+#define SMC_ECC_PR6_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR6_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR6_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR6_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR6_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR6_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR6) Parity N */
+/* -------- SMC_ECC_PR7 : (SMC Offset: 0x04C) SMC ECC parity 7 Register -------- */
+#define SMC_ECC_PR7_BITADDR_Pos 0
+#define SMC_ECC_PR7_BITADDR_Msk (0x7u << SMC_ECC_PR7_BITADDR_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR7_WORDADDR_Pos 3
+#define SMC_ECC_PR7_WORDADDR_Msk (0x1ffu << SMC_ECC_PR7_WORDADDR_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR7_NPARITY_Pos 12
+#define SMC_ECC_PR7_NPARITY_Msk (0xfffu << SMC_ECC_PR7_NPARITY_Pos) /**< \brief (SMC_ECC_PR7) Parity N */
+#define SMC_ECC_PR7_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR7_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR7_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR7_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR7_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR7_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR7) Parity N */
+/* -------- SMC_ECC_PR8 : (SMC Offset: 0x050) SMC ECC parity 8 Register -------- */
+#define SMC_ECC_PR8_BITADDR_Pos 0
+#define SMC_ECC_PR8_BITADDR_Msk (0x7u << SMC_ECC_PR8_BITADDR_Pos) /**< \brief (SMC_ECC_PR8) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR8_WORDADDR_Pos 3
+#define SMC_ECC_PR8_WORDADDR_Msk (0xffu << SMC_ECC_PR8_WORDADDR_Pos) /**< \brief (SMC_ECC_PR8) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR8_NPARITY_Pos 12
+#define SMC_ECC_PR8_NPARITY_Msk (0x7ffu << SMC_ECC_PR8_NPARITY_Pos) /**< \brief (SMC_ECC_PR8) Parity N */
+/* -------- SMC_ECC_PR9 : (SMC Offset: 0x054) SMC ECC parity 9 Register -------- */
+#define SMC_ECC_PR9_BITADDR_Pos 0
+#define SMC_ECC_PR9_BITADDR_Msk (0x7u << SMC_ECC_PR9_BITADDR_Pos) /**< \brief (SMC_ECC_PR9) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR9_WORDADDR_Pos 3
+#define SMC_ECC_PR9_WORDADDR_Msk (0xffu << SMC_ECC_PR9_WORDADDR_Pos) /**< \brief (SMC_ECC_PR9) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR9_NPARITY_Pos 12
+#define SMC_ECC_PR9_NPARITY_Msk (0x7ffu << SMC_ECC_PR9_NPARITY_Pos) /**< \brief (SMC_ECC_PR9) Parity N */
+/* -------- SMC_ECC_PR10 : (SMC Offset: 0x058) SMC ECC parity 10 Register -------- */
+#define SMC_ECC_PR10_BITADDR_Pos 0
+#define SMC_ECC_PR10_BITADDR_Msk (0x7u << SMC_ECC_PR10_BITADDR_Pos) /**< \brief (SMC_ECC_PR10) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR10_WORDADDR_Pos 3
+#define SMC_ECC_PR10_WORDADDR_Msk (0xffu << SMC_ECC_PR10_WORDADDR_Pos) /**< \brief (SMC_ECC_PR10) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR10_NPARITY_Pos 12
+#define SMC_ECC_PR10_NPARITY_Msk (0x7ffu << SMC_ECC_PR10_NPARITY_Pos) /**< \brief (SMC_ECC_PR10) Parity N */
+/* -------- SMC_ECC_PR11 : (SMC Offset: 0x05C) SMC ECC parity 11 Register -------- */
+#define SMC_ECC_PR11_BITADDR_Pos 0
+#define SMC_ECC_PR11_BITADDR_Msk (0x7u << SMC_ECC_PR11_BITADDR_Pos) /**< \brief (SMC_ECC_PR11) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR11_WORDADDR_Pos 3
+#define SMC_ECC_PR11_WORDADDR_Msk (0xffu << SMC_ECC_PR11_WORDADDR_Pos) /**< \brief (SMC_ECC_PR11) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR11_NPARITY_Pos 12
+#define SMC_ECC_PR11_NPARITY_Msk (0x7ffu << SMC_ECC_PR11_NPARITY_Pos) /**< \brief (SMC_ECC_PR11) Parity N */
+/* -------- SMC_ECC_PR12 : (SMC Offset: 0x060) SMC ECC parity 12 Register -------- */
+#define SMC_ECC_PR12_BITADDR_Pos 0
+#define SMC_ECC_PR12_BITADDR_Msk (0x7u << SMC_ECC_PR12_BITADDR_Pos) /**< \brief (SMC_ECC_PR12) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR12_WORDADDR_Pos 3
+#define SMC_ECC_PR12_WORDADDR_Msk (0xffu << SMC_ECC_PR12_WORDADDR_Pos) /**< \brief (SMC_ECC_PR12) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR12_NPARITY_Pos 12
+#define SMC_ECC_PR12_NPARITY_Msk (0x7ffu << SMC_ECC_PR12_NPARITY_Pos) /**< \brief (SMC_ECC_PR12) Parity N */
+/* -------- SMC_ECC_PR13 : (SMC Offset: 0x064) SMC ECC parity 13 Register -------- */
+#define SMC_ECC_PR13_BITADDR_Pos 0
+#define SMC_ECC_PR13_BITADDR_Msk (0x7u << SMC_ECC_PR13_BITADDR_Pos) /**< \brief (SMC_ECC_PR13) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR13_WORDADDR_Pos 3
+#define SMC_ECC_PR13_WORDADDR_Msk (0xffu << SMC_ECC_PR13_WORDADDR_Pos) /**< \brief (SMC_ECC_PR13) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR13_NPARITY_Pos 12
+#define SMC_ECC_PR13_NPARITY_Msk (0x7ffu << SMC_ECC_PR13_NPARITY_Pos) /**< \brief (SMC_ECC_PR13) Parity N */
+/* -------- SMC_ECC_PR14 : (SMC Offset: 0x068) SMC ECC parity 14 Register -------- */
+#define SMC_ECC_PR14_BITADDR_Pos 0
+#define SMC_ECC_PR14_BITADDR_Msk (0x7u << SMC_ECC_PR14_BITADDR_Pos) /**< \brief (SMC_ECC_PR14) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR14_WORDADDR_Pos 3
+#define SMC_ECC_PR14_WORDADDR_Msk (0xffu << SMC_ECC_PR14_WORDADDR_Pos) /**< \brief (SMC_ECC_PR14) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR14_NPARITY_Pos 12
+#define SMC_ECC_PR14_NPARITY_Msk (0x7ffu << SMC_ECC_PR14_NPARITY_Pos) /**< \brief (SMC_ECC_PR14) Parity N */
+/* -------- SMC_ECC_PR15 : (SMC Offset: 0x06C) SMC ECC parity 15 Register -------- */
+#define SMC_ECC_PR15_BITADDR_Pos 0
+#define SMC_ECC_PR15_BITADDR_Msk (0x7u << SMC_ECC_PR15_BITADDR_Pos) /**< \brief (SMC_ECC_PR15) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR15_WORDADDR_Pos 3
+#define SMC_ECC_PR15_WORDADDR_Msk (0xffu << SMC_ECC_PR15_WORDADDR_Pos) /**< \brief (SMC_ECC_PR15) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR15_NPARITY_Pos 12
+#define SMC_ECC_PR15_NPARITY_Msk (0x7ffu << SMC_ECC_PR15_NPARITY_Pos) /**< \brief (SMC_ECC_PR15) Parity N */
+/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */
+#define SMC_SETUP_NWE_SETUP_Pos 0
+#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */
+#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))
+#define SMC_SETUP_NCS_WR_SETUP_Pos 8
+#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in Write Access */
+#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))
+#define SMC_SETUP_NRD_SETUP_Pos 16
+#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */
+#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))
+#define SMC_SETUP_NCS_RD_SETUP_Pos 24
+#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in Read Access */
+#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))
+/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */
+#define SMC_PULSE_NWE_PULSE_Pos 0
+#define SMC_PULSE_NWE_PULSE_Msk (0x3fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */
+#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))
+#define SMC_PULSE_NCS_WR_PULSE_Pos 8
+#define SMC_PULSE_NCS_WR_PULSE_Msk (0x3fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */
+#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))
+#define SMC_PULSE_NRD_PULSE_Pos 16
+#define SMC_PULSE_NRD_PULSE_Msk (0x3fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */
+#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))
+#define SMC_PULSE_NCS_RD_PULSE_Pos 24
+#define SMC_PULSE_NCS_RD_PULSE_Msk (0x3fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */
+#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))
+/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */
+#define SMC_CYCLE_NWE_CYCLE_Pos 0
+#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */
+#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))
+#define SMC_CYCLE_NRD_CYCLE_Pos 16
+#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */
+#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))
+/* -------- SMC_TIMINGS : (SMC Offset: N/A) SMC Timings Register -------- */
+#define SMC_TIMINGS_TCLR_Pos 0
+#define SMC_TIMINGS_TCLR_Msk (0xfu << SMC_TIMINGS_TCLR_Pos) /**< \brief (SMC_TIMINGS) CLE to REN Low Delay */
+#define SMC_TIMINGS_TCLR(value) ((SMC_TIMINGS_TCLR_Msk & ((value) << SMC_TIMINGS_TCLR_Pos)))
+#define SMC_TIMINGS_TADL_Pos 4
+#define SMC_TIMINGS_TADL_Msk (0xfu << SMC_TIMINGS_TADL_Pos) /**< \brief (SMC_TIMINGS) ALE to Data Start */
+#define SMC_TIMINGS_TADL(value) ((SMC_TIMINGS_TADL_Msk & ((value) << SMC_TIMINGS_TADL_Pos)))
+#define SMC_TIMINGS_TAR_Pos 8
+#define SMC_TIMINGS_TAR_Msk (0xfu << SMC_TIMINGS_TAR_Pos) /**< \brief (SMC_TIMINGS) ALE to REN Low Delay */
+#define SMC_TIMINGS_TAR(value) ((SMC_TIMINGS_TAR_Msk & ((value) << SMC_TIMINGS_TAR_Pos)))
+#define SMC_TIMINGS_OCMS (0x1u << 12) /**< \brief (SMC_TIMINGS) Off Chip Memory Scrambling Enable */
+#define SMC_TIMINGS_TRR_Pos 16
+#define SMC_TIMINGS_TRR_Msk (0xfu << SMC_TIMINGS_TRR_Pos) /**< \brief (SMC_TIMINGS) Ready to REN Low Delay */
+#define SMC_TIMINGS_TRR(value) ((SMC_TIMINGS_TRR_Msk & ((value) << SMC_TIMINGS_TRR_Pos)))
+#define SMC_TIMINGS_TWB_Pos 24
+#define SMC_TIMINGS_TWB_Msk (0xfu << SMC_TIMINGS_TWB_Pos) /**< \brief (SMC_TIMINGS) WEN High to REN to Busy */
+#define SMC_TIMINGS_TWB(value) ((SMC_TIMINGS_TWB_Msk & ((value) << SMC_TIMINGS_TWB_Pos)))
+#define SMC_TIMINGS_RBNSEL_Pos 28
+#define SMC_TIMINGS_RBNSEL_Msk (0x7u << SMC_TIMINGS_RBNSEL_Pos) /**< \brief (SMC_TIMINGS) Ready/Busy Line Selection */
+#define SMC_TIMINGS_RBNSEL(value) ((SMC_TIMINGS_RBNSEL_Msk & ((value) << SMC_TIMINGS_RBNSEL_Pos)))
+#define SMC_TIMINGS_NFSEL (0x1u << 31) /**< \brief (SMC_TIMINGS) NAND Flash Selection */
+/* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */
+#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE)  */
+#define   SMC_MODE_READ_MODE_NCS_CTRL (0x0u << 0) /**< \brief (SMC_MODE) The Read operation is controlled by the NCS signal. */
+#define   SMC_MODE_READ_MODE_NRD_CTRL (0x1u << 0) /**< \brief (SMC_MODE) The Read operation is controlled by the NRD signal. */
+#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE)  */
+#define   SMC_MODE_WRITE_MODE_NCS_CTRL (0x0u << 1) /**< \brief (SMC_MODE) The Write operation is controller by the NCS signal. */
+#define   SMC_MODE_WRITE_MODE_NWE_CTRL (0x1u << 1) /**< \brief (SMC_MODE) The Write operation is controlled by the NWE signal. */
+#define SMC_MODE_EXNW_MODE_Pos 4
+#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */
+#define   SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */
+#define   SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */
+#define   SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */
+#define SMC_MODE_BAT (0x1u << 8) /**< \brief (SMC_MODE) Byte Access Type */
+#define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */
+#define   SMC_MODE_DBW_BIT_8 (0x0u << 12) /**< \brief (SMC_MODE) 8-bit bus */
+#define   SMC_MODE_DBW_BIT_16 (0x1u << 12) /**< \brief (SMC_MODE) 16-bit bus */
+#define SMC_MODE_TDF_CYCLES_Pos 16
+#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */
+#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))
+#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */
+/* -------- SMC_OCMS : (SMC Offset: 0x110) SMC OCMS Register -------- */
+#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */
+#define SMC_OCMS_SRSE (0x1u << 1) /**< \brief (SMC_OCMS) SRAM Scrambling Enable */
+/* -------- SMC_KEY1 : (SMC Offset: 0x114) SMC OCMS KEY1 Register -------- */
+#define SMC_KEY1_KEY1_Pos 0
+#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */
+#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))
+/* -------- SMC_KEY2 : (SMC Offset: 0x118) SMC OCMS KEY2 Register -------- */
+#define SMC_KEY2_KEY2_Pos 0
+#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */
+#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))
+/* -------- SMC_WPCR : (SMC Offset: 0x1E4) Write Protection Control Register -------- */
+#define SMC_WPCR_WP_EN (0x1u << 0) /**< \brief (SMC_WPCR) Write Protection Enable */
+#define SMC_WPCR_WP_KEY_Pos 8
+#define SMC_WPCR_WP_KEY_Msk (0xffffffu << SMC_WPCR_WP_KEY_Pos) /**< \brief (SMC_WPCR) Write Protection KEY password */
+#define SMC_WPCR_WP_KEY(value) ((SMC_WPCR_WP_KEY_Msk & ((value) << SMC_WPCR_WP_KEY_Pos)))
+/* -------- SMC_WPSR : (SMC Offset: 0x1E8) Write Protection Status Register -------- */
+#define SMC_WPSR_WP_VS_Pos 0
+#define SMC_WPSR_WP_VS_Msk (0xfu << SMC_WPSR_WP_VS_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Status */
+#define SMC_WPSR_WP_VSRC_Pos 8
+#define SMC_WPSR_WP_VSRC_Msk (0xffffu << SMC_WPSR_WP_VSRC_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3U_SMC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_spi.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_spi.h
new file mode 100644
index 000000000..152546a63
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_spi.h
@@ -0,0 +1,160 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_SPI_COMPONENT_
+#define _SAM3U_SPI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Serial Peripheral Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3U_SPI Serial Peripheral Interface */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Spi hardware registers */
+typedef struct {
+  WoReg SPI_CR;        /**< \brief (Spi Offset: 0x00) Control Register */
+  RwReg SPI_MR;        /**< \brief (Spi Offset: 0x04) Mode Register */
+  RoReg SPI_RDR;       /**< \brief (Spi Offset: 0x08) Receive Data Register */
+  WoReg SPI_TDR;       /**< \brief (Spi Offset: 0x0C) Transmit Data Register */
+  RoReg SPI_SR;        /**< \brief (Spi Offset: 0x10) Status Register */
+  WoReg SPI_IER;       /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */
+  WoReg SPI_IDR;       /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */
+  RoReg SPI_IMR;       /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */
+  RoReg Reserved1[4];
+  RwReg SPI_CSR[4];    /**< \brief (Spi Offset: 0x30) Chip Select Register */
+  RoReg Reserved2[41];
+  RwReg SPI_WPMR;      /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */
+  RoReg SPI_WPSR;      /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */
+} Spi;
+#endif /* __ASSEMBLY__ */
+/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
+#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */
+#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */
+#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */
+#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */
+/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
+#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */
+#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */
+#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */
+#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */
+#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */
+#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */
+#define SPI_MR_PCS_Pos 16
+#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */
+#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
+#define SPI_MR_DLYBCS_Pos 24
+#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */
+#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
+/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
+#define SPI_RDR_RD_Pos 0
+#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */
+#define SPI_RDR_PCS_Pos 16
+#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */
+/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
+#define SPI_TDR_TD_Pos 0
+#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */
+#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
+#define SPI_TDR_PCS_Pos 16
+#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */
+#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
+#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
+#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */
+#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */
+#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */
+#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */
+#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */
+#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */
+#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */
+#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
+#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */
+#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */
+#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */
+#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */
+#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */
+#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */
+#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */
+#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */
+#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */
+#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */
+#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */
+#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */
+#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */
+/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
+#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */
+#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */
+#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */
+#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */
+#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */
+#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */
+#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */
+/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
+#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */
+#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */
+#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_BITS_Pos 4
+#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */
+#define   SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */
+#define   SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */
+#define   SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */
+#define   SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */
+#define   SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */
+#define   SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */
+#define   SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */
+#define   SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */
+#define   SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */
+#define SPI_CSR_SCBR_Pos 8
+#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */
+#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
+#define SPI_CSR_DLYBS_Pos 16
+#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */
+#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
+#define SPI_CSR_DLYBCT_Pos 24
+#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */
+#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
+/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */
+#define SPI_WPMR_SPIWPEN (0x1u << 0) /**< \brief (SPI_WPMR) SPI Write Protection Enable */
+#define SPI_WPMR_SPIWPKEY_Pos 8
+#define SPI_WPMR_SPIWPKEY_Msk (0xffffffu << SPI_WPMR_SPIWPKEY_Pos) /**< \brief (SPI_WPMR) SPI Write Protection Key Password */
+#define SPI_WPMR_SPIWPKEY(value) ((SPI_WPMR_SPIWPKEY_Msk & ((value) << SPI_WPMR_SPIWPKEY_Pos)))
+/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
+#define SPI_WPSR_SPIWPVS_Pos 0
+#define SPI_WPSR_SPIWPVS_Msk (0x7u << SPI_WPSR_SPIWPVS_Pos) /**< \brief (SPI_WPSR) SPI Write Protection Violation Status */
+#define SPI_WPSR_SPIWPVSRC_Pos 8
+#define SPI_WPSR_SPIWPVSRC_Msk (0xffu << SPI_WPSR_SPIWPVSRC_Pos) /**< \brief (SPI_WPSR) SPI Write Protection Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3U_SPI_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_ssc.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_ssc.h
new file mode 100644
index 000000000..d8e36cd59
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_ssc.h
@@ -0,0 +1,270 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_SSC_COMPONENT_
+#define _SAM3U_SSC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Synchronous Serial Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_SSC Synchronous Serial Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Ssc hardware registers */
+typedef struct {
+  WoReg SSC_CR;        /**< \brief (Ssc Offset: 0x0) Control Register */
+  RwReg SSC_CMR;       /**< \brief (Ssc Offset: 0x4) Clock Mode Register */
+  RoReg Reserved1[2];
+  RwReg SSC_RCMR;      /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */
+  RwReg SSC_RFMR;      /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */
+  RwReg SSC_TCMR;      /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */
+  RwReg SSC_TFMR;      /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */
+  RoReg SSC_RHR;       /**< \brief (Ssc Offset: 0x20) Receive Holding Register */
+  WoReg SSC_THR;       /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */
+  RoReg Reserved2[2];
+  RoReg SSC_RSHR;      /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */
+  RwReg SSC_TSHR;      /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */
+  RwReg SSC_RC0R;      /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */
+  RwReg SSC_RC1R;      /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */
+  RoReg SSC_SR;        /**< \brief (Ssc Offset: 0x40) Status Register */
+  WoReg SSC_IER;       /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */
+  WoReg SSC_IDR;       /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */
+  RoReg SSC_IMR;       /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */
+  RoReg Reserved3[37];
+  RwReg SSC_WPMR;      /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */
+  RoReg SSC_WPSR;      /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */
+} Ssc;
+#endif /* __ASSEMBLY__ */
+/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */
+#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */
+#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */
+#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */
+#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */
+#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */
+/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */
+#define SSC_CMR_DIV_Pos 0
+#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */
+#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))
+/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */
+#define SSC_RCMR_CKS_Pos 0
+#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */
+#define   SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */
+#define   SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */
+#define   SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */
+#define SSC_RCMR_CKO_Pos 2
+#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */
+#define   SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None */
+#define   SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock */
+#define   SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
+#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */
+#define SSC_RCMR_CKG_Pos 6
+#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */
+#define   SSC_RCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_RCMR) None */
+#define   SSC_RCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_RCMR) Continuous Receive Clock */
+#define   SSC_RCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
+#define SSC_RCMR_START_Pos 8
+#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */
+#define   SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
+#define   SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */
+#define   SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */
+#define   SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */
+#define   SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */
+#define   SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */
+#define   SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */
+#define   SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */
+#define   SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */
+#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */
+#define SSC_RCMR_STTDLY_Pos 16
+#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */
+#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))
+#define SSC_RCMR_PERIOD_Pos 24
+#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */
+#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))
+/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */
+#define SSC_RFMR_DATLEN_Pos 0
+#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */
+#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))
+#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */
+#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */
+#define SSC_RFMR_DATNB_Pos 8
+#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */
+#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))
+#define SSC_RFMR_FSLEN_Pos 16
+#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */
+#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))
+#define SSC_RFMR_FSOS_Pos 20
+#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */
+#define   SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None */
+#define   SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse */
+#define   SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse */
+#define   SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer */
+#define   SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer */
+#define   SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer */
+#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */
+#define   SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */
+#define   SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */
+#define SSC_RFMR_FSLEN_EXT_Pos 28
+#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */
+#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))
+/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */
+#define SSC_TCMR_CKS_Pos 0
+#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */
+#define   SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */
+#define   SSC_TCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_TCMR) TK Clock signal */
+#define   SSC_TCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_TCMR) RK pin */
+#define SSC_TCMR_CKO_Pos 2
+#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */
+#define   SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None */
+#define   SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Receive Clock */
+#define   SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers */
+#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */
+#define SSC_TCMR_CKG_Pos 6
+#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */
+#define   SSC_TCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_TCMR) None */
+#define   SSC_TCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */
+#define   SSC_TCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */
+#define SSC_TCMR_START_Pos 8
+#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */
+#define   SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. */
+#define   SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */
+#define   SSC_TCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */
+#define   SSC_TCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */
+#define   SSC_TCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */
+#define   SSC_TCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */
+#define   SSC_TCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */
+#define   SSC_TCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */
+#define   SSC_TCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_TCMR) Compare 0 */
+#define SSC_TCMR_STTDLY_Pos 16
+#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */
+#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))
+#define SSC_TCMR_PERIOD_Pos 24
+#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */
+#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))
+/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */
+#define SSC_TFMR_DATLEN_Pos 0
+#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */
+#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))
+#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */
+#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */
+#define SSC_TFMR_DATNB_Pos 8
+#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per frame */
+#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))
+#define SSC_TFMR_FSLEN_Pos 16
+#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */
+#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))
+#define SSC_TFMR_FSOS_Pos 20
+#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */
+#define   SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None */
+#define   SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse */
+#define   SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse */
+#define   SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */
+#define   SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */
+#define   SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */
+#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */
+#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */
+#define   SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */
+#define   SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */
+#define SSC_TFMR_FSLEN_EXT_Pos 28
+#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */
+#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))
+/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */
+#define SSC_RHR_RDAT_Pos 0
+#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */
+/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */
+#define SSC_THR_TDAT_Pos 0
+#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */
+#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))
+/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */
+#define SSC_RSHR_RSDAT_Pos 0
+#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */
+/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */
+#define SSC_TSHR_TSDAT_Pos 0
+#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */
+#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))
+/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */
+#define SSC_RC0R_CP0_Pos 0
+#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */
+#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))
+/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */
+#define SSC_RC1R_CP1_Pos 0
+#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */
+#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))
+/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */
+#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */
+#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */
+#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */
+#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */
+#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */
+#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */
+#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */
+#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */
+#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */
+#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */
+/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */
+#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */
+#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */
+#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */
+#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */
+#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */
+#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */
+#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */
+#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */
+/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */
+#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */
+#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */
+#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */
+#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */
+#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */
+#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */
+#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */
+#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */
+/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */
+#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */
+#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */
+#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */
+#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */
+#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */
+#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */
+#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */
+#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */
+/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */
+#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protect Enable */
+#define SSC_WPMR_WPKEY_Pos 8
+#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protect KEY */
+#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)))
+/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */
+#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */
+#define SSC_WPSR_WPVSRC_Pos 8
+#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3U_SSC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_supc.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_supc.h
new file mode 100644
index 000000000..73e7f1fdc
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_supc.h
@@ -0,0 +1,312 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_SUPC_COMPONENT_
+#define _SAM3U_SUPC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Supply Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_SUPC Supply Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Supc hardware registers */
+typedef struct {
+  WoReg SUPC_CR;   /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */
+  RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */
+  RwReg SUPC_MR;   /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */
+  RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */
+  RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */
+  RoReg SUPC_SR;   /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */
+} Supc;
+#endif /* __ASSEMBLY__ */
+/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */
+#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */
+#define   SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */
+#define   SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */
+#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */
+#define   SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */
+#define   SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */
+#define SUPC_CR_KEY_Pos 24
+#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */
+#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))
+/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */
+#define SUPC_SMMR_SMTH_Pos 0
+#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */
+#define   SUPC_SMMR_SMTH_1_9V (0x0u << 0) /**< \brief (SUPC_SMMR) 1.9 V */
+#define   SUPC_SMMR_SMTH_2_0V (0x1u << 0) /**< \brief (SUPC_SMMR) 2.0 V */
+#define   SUPC_SMMR_SMTH_2_1V (0x2u << 0) /**< \brief (SUPC_SMMR) 2.1 V */
+#define   SUPC_SMMR_SMTH_2_2V (0x3u << 0) /**< \brief (SUPC_SMMR) 2.2 V */
+#define   SUPC_SMMR_SMTH_2_3V (0x4u << 0) /**< \brief (SUPC_SMMR) 2.3 V */
+#define   SUPC_SMMR_SMTH_2_4V (0x5u << 0) /**< \brief (SUPC_SMMR) 2.4 V */
+#define   SUPC_SMMR_SMTH_2_5V (0x6u << 0) /**< \brief (SUPC_SMMR) 2.5 V */
+#define   SUPC_SMMR_SMTH_2_6V (0x7u << 0) /**< \brief (SUPC_SMMR) 2.6 V */
+#define   SUPC_SMMR_SMTH_2_7V (0x8u << 0) /**< \brief (SUPC_SMMR) 2.7 V */
+#define   SUPC_SMMR_SMTH_2_8V (0x9u << 0) /**< \brief (SUPC_SMMR) 2.8 V */
+#define   SUPC_SMMR_SMTH_2_9V (0xAu << 0) /**< \brief (SUPC_SMMR) 2.9 V */
+#define   SUPC_SMMR_SMTH_3_0V (0xBu << 0) /**< \brief (SUPC_SMMR) 3.0 V */
+#define   SUPC_SMMR_SMTH_3_1V (0xCu << 0) /**< \brief (SUPC_SMMR) 3.1 V */
+#define   SUPC_SMMR_SMTH_3_2V (0xDu << 0) /**< \brief (SUPC_SMMR) 3.2 V */
+#define   SUPC_SMMR_SMTH_3_3V (0xEu << 0) /**< \brief (SUPC_SMMR) 3.3 V */
+#define   SUPC_SMMR_SMTH_3_4V (0xFu << 0) /**< \brief (SUPC_SMMR) 3.4 V */
+#define SUPC_SMMR_SMSMPL_Pos 8
+#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */
+#define   SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */
+#define   SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */
+#define   SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */
+#define   SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */
+#define   SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */
+#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */
+#define   SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */
+#define   SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */
+#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */
+#define   SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */
+#define   SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */
+/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */
+#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */
+#define   SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */
+#define   SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */
+#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */
+#define   SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */
+#define   SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */
+#define SUPC_MR_VDDIORDYONREG (0x1u << 14) /**< \brief (SUPC_MR)  */
+#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */
+#define   SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */
+#define   SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */
+#define SUPC_MR_KEY_Pos 24
+#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */
+#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))
+/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */
+#define SUPC_WUMR_FWUPEN (0x1u << 0) /**< \brief (SUPC_WUMR) Force Wake Up Enable */
+#define   SUPC_WUMR_FWUPEN_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin has no wake up effect. */
+#define   SUPC_WUMR_FWUPEN_ENABLE (0x1u << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin low forces the wake up of the core power supply. */
+#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */
+#define   SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */
+#define   SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */
+#define   SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */
+#define   SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */
+#define   SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */
+#define   SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_FWUPDBC_Pos 8
+#define SUPC_WUMR_FWUPDBC_Msk (0x7u << SUPC_WUMR_FWUPDBC_Pos) /**< \brief (SUPC_WUMR) Force Wake Up Debouncer Period */
+#define   SUPC_WUMR_FWUPDBC_IMMEDIATE (0x0u << 8) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
+#define   SUPC_WUMR_FWUPDBC_3_SCLK (0x1u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 3 SLCK periods */
+#define   SUPC_WUMR_FWUPDBC_32_SCLK (0x2u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32 SLCK periods */
+#define   SUPC_WUMR_FWUPDBC_512_SCLK (0x3u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 512 SLCK periods */
+#define   SUPC_WUMR_FWUPDBC_4096_SCLK (0x4u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 4,096 SLCK periods */
+#define   SUPC_WUMR_FWUPDBC_32768_SCLK (0x5u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32,768 SLCK periods */
+#define SUPC_WUMR_WKUPDBC_Pos 12
+#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer Period */
+#define   SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
+#define   SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */
+/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */
+#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */
+#define   SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */
+#define   SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */
+#define   SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */
+#define   SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */
+#define   SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */
+#define   SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */
+#define   SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */
+#define   SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */
+#define   SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */
+#define   SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */
+#define   SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */
+#define   SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */
+#define   SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */
+#define   SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */
+#define   SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */
+#define   SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */
+#define   SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */
+#define   SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */
+#define   SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */
+#define   SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */
+#define   SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */
+#define   SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */
+#define   SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */
+#define   SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */
+#define   SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */
+#define   SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */
+#define   SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */
+#define   SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */
+#define   SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */
+#define   SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */
+#define   SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */
+#define   SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */
+#define SUPC_SR_FWUPS (0x1u << 0) /**< \brief (SUPC_SR) FWUP Wake Up Status */
+#define   SUPC_SR_FWUPS_NO (0x0u << 0) /**< \brief (SUPC_SR) no wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_FWUPS_PRESENT (0x1u << 0) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */
+#define   SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */
+#define   SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */
+#define   SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */
+#define   SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */
+#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */
+#define   SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define   SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */
+#define   SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */
+#define   SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */
+#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */
+#define   SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI higher than its threshold at its last measurement. */
+#define   SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI lower than its threshold at its last measurement. */
+#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */
+#define   SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */
+#define   SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */
+#define SUPC_SR_FWUPIS (0x1u << 12) /**< \brief (SUPC_SR) FWUP Input Status */
+#define   SUPC_SR_FWUPIS_LOW (0x0u << 12) /**< \brief (SUPC_SR) FWUP input is tied low. */
+#define   SUPC_SR_FWUPIS_HIGH (0x1u << 12) /**< \brief (SUPC_SR) FWUP input is tied high. */
+#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */
+#define   SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */
+#define   SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */
+#define   SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */
+#define   SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */
+#define   SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */
+#define   SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */
+#define   SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */
+#define   SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */
+#define   SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */
+#define   SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */
+#define   SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */
+#define   SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */
+#define   SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */
+#define   SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */
+#define   SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */
+#define   SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+
+/*@}*/
+
+
+#endif /* _SAM3U_SUPC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_tc.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_tc.h
new file mode 100644
index 000000000..5c046acfb
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_tc.h
@@ -0,0 +1,288 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_TC_COMPONENT_
+#define _SAM3U_TC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Timer Counter */
+/* ============================================================================= */
+/** \addtogroup SAM3U_TC Timer Counter */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief TcChannel hardware registers */
+typedef struct {
+  RwReg      TC_CCR;        /**< \brief (TcChannel Offset: 0x0) Channel Control Register */
+  RwReg      TC_CMR;        /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */
+  RoReg      Reserved1[2];
+  RwReg      TC_CV;         /**< \brief (TcChannel Offset: 0x10) Counter Value */
+  RwReg      TC_RA;         /**< \brief (TcChannel Offset: 0x14) Register A */
+  RwReg      TC_RB;         /**< \brief (TcChannel Offset: 0x18) Register B */
+  RwReg      TC_RC;         /**< \brief (TcChannel Offset: 0x1C) Register C */
+  RwReg      TC_SR;         /**< \brief (TcChannel Offset: 0x20) Status Register */
+  RwReg      TC_IER;        /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
+  RwReg      TC_IDR;        /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
+  RwReg      TC_IMR;        /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */
+  RoReg      Reserved2[4];
+} TcChannel;
+/** \brief Tc hardware registers */
+#define TCCHANNEL_NUMBER 3
+typedef struct {
+  TcChannel  TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */
+  WoReg      TC_BCR;        /**< \brief (Tc Offset: 0xC0) Block Control Register */
+  RwReg      TC_BMR;        /**< \brief (Tc Offset: 0xC4) Block Mode Register */
+  WoReg      TC_QIER;       /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */
+  WoReg      TC_QIDR;       /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */
+  RoReg      TC_QIMR;       /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */
+  RoReg      TC_QISR;       /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */
+} Tc;
+#endif /* __ASSEMBLY__ */
+/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */
+#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */
+#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */
+#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */
+/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */
+#define TC_CMR_TCCLKS_Pos 0
+#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */
+#define   TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */
+#define   TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */
+#define   TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */
+#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */
+#define TC_CMR_BURST_Pos 4
+#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */
+#define   TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define   TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */
+#define   TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */
+#define   TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */
+#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */
+#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */
+#define TC_CMR_ETRGEDG_Pos 8
+#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */
+#define   TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define   TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define   TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define   TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */
+#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */
+#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */
+#define TC_CMR_LDRA_Pos 16
+#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */
+#define   TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define   TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define   TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define   TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_LDRB_Pos 18
+#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */
+#define   TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define   TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define   TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define   TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */
+#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */
+#define TC_CMR_EEVTEDG_Pos 8
+#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */
+#define   TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */
+#define   TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define   TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define   TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_EEVT_Pos 10
+#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */
+#define   TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */
+#define   TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */
+#define   TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */
+#define   TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */
+#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */
+#define TC_CMR_WAVSEL_Pos 13
+#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */
+#define   TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */
+#define TC_CMR_ACPA_Pos 16
+#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */
+#define   TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ACPC_Pos 18
+#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */
+#define   TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_AEEVT_Pos 20
+#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */
+#define   TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */
+#define   TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ASWTRG_Pos 22
+#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */
+#define   TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPB_Pos 24
+#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */
+#define   TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPC_Pos 26
+#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */
+#define   TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BEEVT_Pos 28
+#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */
+#define   TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BSWTRG_Pos 30
+#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */
+#define   TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */
+/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */
+#define TC_CV_CV_Pos 0
+#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */
+/* -------- TC_RA : (TC Offset: N/A) Register A -------- */
+#define TC_RA_RA_Pos 0
+#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */
+#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))
+/* -------- TC_RB : (TC Offset: N/A) Register B -------- */
+#define TC_RB_RB_Pos 0
+#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */
+#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))
+/* -------- TC_RC : (TC Offset: N/A) Register C -------- */
+#define TC_RC_RC_Pos 0
+#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */
+#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))
+/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */
+#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */
+#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */
+#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */
+#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */
+#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */
+#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */
+#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */
+#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */
+#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */
+#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */
+#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */
+/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */
+#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */
+#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */
+#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */
+#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */
+#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */
+#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */
+#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */
+#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */
+/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */
+#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */
+#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */
+#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */
+#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */
+#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */
+#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */
+#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */
+#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */
+/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */
+#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */
+#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */
+#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */
+#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */
+#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */
+#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */
+#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */
+#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */
+/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
+#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */
+/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
+#define TC_BMR_TC0XC0S_Pos 0
+#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */
+#define   TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */
+#define   TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */
+#define   TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */
+#define TC_BMR_TC1XC1S_Pos 2
+#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */
+#define   TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */
+#define   TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */
+#define   TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */
+#define TC_BMR_TC2XC2S_Pos 4
+#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */
+#define   TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */
+#define   TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */
+#define   TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */
+#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */
+#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */
+#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */
+#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */
+#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */
+#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */
+#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */
+#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */
+#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */
+#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */
+#define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR)  */
+#define TC_BMR_MAXFILT_Pos 20
+#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */
+#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))
+/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */
+#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */
+#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */
+#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */
+/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */
+#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */
+#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */
+#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */
+/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */
+#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */
+#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */
+#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */
+/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */
+#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */
+#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */
+#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */
+#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */
+
+/*@}*/
+
+
+#endif /* _SAM3U_TC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_twi.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_twi.h
new file mode 100644
index 000000000..a1816963b
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_twi.h
@@ -0,0 +1,217 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_TWI_COMPONENT_
+#define _SAM3U_TWI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Two-wire Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3U_TWI Two-wire Interface */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Twi hardware registers */
+typedef struct {
+  WoReg TWI_CR;        /**< \brief (Twi Offset: 0x00) Control Register */
+  RwReg TWI_MMR;       /**< \brief (Twi Offset: 0x04) Master Mode Register */
+  RwReg TWI_SMR;       /**< \brief (Twi Offset: 0x08) Slave Mode Register */
+  RwReg TWI_IADR;      /**< \brief (Twi Offset: 0x0C) Internal Address Register */
+  RwReg TWI_CWGR;      /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */
+  RoReg Reserved1[3];
+  RoReg TWI_SR;        /**< \brief (Twi Offset: 0x20) Status Register */
+  WoReg TWI_IER;       /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */
+  WoReg TWI_IDR;       /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */
+  RoReg TWI_IMR;       /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */
+  RoReg TWI_RHR;       /**< \brief (Twi Offset: 0x30) Receive Holding Register */
+  WoReg TWI_THR;       /**< \brief (Twi Offset: 0x34) Transmit Holding Register */
+  RoReg Reserved2[50];
+  RwReg TWI_RPR;       /**< \brief (Twi Offset: 0x100) Receive Pointer Register */
+  RwReg TWI_RCR;       /**< \brief (Twi Offset: 0x104) Receive Counter Register */
+  RwReg TWI_TPR;       /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */
+  RwReg TWI_TCR;       /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */
+  RwReg TWI_RNPR;      /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */
+  RwReg TWI_RNCR;      /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */
+  RwReg TWI_TNPR;      /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */
+  RwReg TWI_TNCR;      /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */
+  WoReg TWI_PTCR;      /**< \brief (Twi Offset: 0x120) Transfer Control Register */
+  RoReg TWI_PTSR;      /**< \brief (Twi Offset: 0x124) Transfer Status Register */
+} Twi;
+#endif /* __ASSEMBLY__ */
+/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */
+#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */
+#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */
+#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */
+#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */
+#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */
+#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */
+#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */
+#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */
+/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */
+#define TWI_MMR_IADRSZ_Pos 8
+#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */
+#define   TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */
+#define   TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */
+#define   TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */
+#define   TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */
+#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */
+#define TWI_MMR_DADR_Pos 16
+#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */
+#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))
+/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */
+#define TWI_SMR_SADR_Pos 16
+#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */
+#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))
+/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */
+#define TWI_IADR_IADR_Pos 0
+#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */
+#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))
+/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */
+#define TWI_CWGR_CLDIV_Pos 0
+#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */
+#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))
+#define TWI_CWGR_CHDIV_Pos 8
+#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */
+#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))
+#define TWI_CWGR_CKDIV_Pos 16
+#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */
+#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))
+/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */
+#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */
+#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */
+#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */
+#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */
+#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */
+#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */
+#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */
+#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */
+#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */
+#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */
+#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */
+#define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */
+#define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */
+#define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */
+#define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */
+/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */
+#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */
+#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */
+#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */
+#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */
+#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */
+#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */
+#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */
+#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */
+#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */
+#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */
+#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */
+#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */
+#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */
+#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */
+/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */
+#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */
+#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */
+#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */
+#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */
+#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */
+#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */
+#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */
+#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */
+#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */
+#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */
+#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */
+#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */
+#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */
+#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */
+/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */
+#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */
+#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */
+#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */
+#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */
+#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */
+#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */
+#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */
+#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */
+#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */
+#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */
+#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */
+#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */
+#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */
+#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */
+/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */
+#define TWI_RHR_RXDATA_Pos 0
+#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */
+/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */
+#define TWI_THR_TXDATA_Pos 0
+#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */
+#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))
+/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */
+#define TWI_RPR_RXPTR_Pos 0
+#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */
+#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos)))
+/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */
+#define TWI_RCR_RXCTR_Pos 0
+#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */
+#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos)))
+/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */
+#define TWI_TPR_TXPTR_Pos 0
+#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */
+#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos)))
+/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */
+#define TWI_TCR_TXCTR_Pos 0
+#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */
+#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos)))
+/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */
+#define TWI_RNPR_RXNPTR_Pos 0
+#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */
+#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos)))
+/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */
+#define TWI_RNCR_RXNCTR_Pos 0
+#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */
+#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos)))
+/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define TWI_TNPR_TXNPTR_Pos 0
+#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */
+#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos)))
+/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define TWI_TNCR_TXNCTR_Pos 0
+#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */
+#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos)))
+/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */
+#define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */
+#define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */
+#define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */
+#define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */
+/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */
+#define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */
+#define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3U_TWI_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_uart.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_uart.h
new file mode 100644
index 000000000..87cc4c1a4
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_uart.h
@@ -0,0 +1,185 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_UART_COMPONENT_
+#define _SAM3U_UART_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM3U_UART Universal Asynchronous Receiver Transmitter */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Uart hardware registers */
+typedef struct {
+  WoReg UART_CR;       /**< \brief (Uart Offset: 0x0000) Control Register */
+  RwReg UART_MR;       /**< \brief (Uart Offset: 0x0004) Mode Register */
+  WoReg UART_IER;      /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */
+  WoReg UART_IDR;      /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */
+  RoReg UART_IMR;      /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */
+  RoReg UART_SR;       /**< \brief (Uart Offset: 0x0014) Status Register */
+  RoReg UART_RHR;      /**< \brief (Uart Offset: 0x0018) Receive Holding Register */
+  WoReg UART_THR;      /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */
+  RwReg UART_BRGR;     /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */
+  RoReg Reserved1[55];
+  RwReg UART_RPR;      /**< \brief (Uart Offset: 0x100) Receive Pointer Register */
+  RwReg UART_RCR;      /**< \brief (Uart Offset: 0x104) Receive Counter Register */
+  RwReg UART_TPR;      /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */
+  RwReg UART_TCR;      /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */
+  RwReg UART_RNPR;     /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */
+  RwReg UART_RNCR;     /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */
+  RwReg UART_TNPR;     /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */
+  RwReg UART_TNCR;     /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */
+  WoReg UART_PTCR;     /**< \brief (Uart Offset: 0x120) Transfer Control Register */
+  RoReg UART_PTSR;     /**< \brief (Uart Offset: 0x124) Transfer Status Register */
+} Uart;
+#endif /* __ASSEMBLY__ */
+/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
+#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */
+#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */
+#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */
+#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */
+#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */
+#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */
+#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */
+/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
+#define UART_MR_PAR_Pos 9
+#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */
+#define   UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */
+#define   UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */
+#define   UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */
+#define   UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */
+#define   UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */
+#define UART_MR_CHMODE_Pos 14
+#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */
+#define   UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */
+#define   UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */
+#define   UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */
+#define   UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */
+/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
+#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */
+#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */
+#define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */
+#define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */
+#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */
+#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */
+#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */
+#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */
+#define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */
+#define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */
+/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
+#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */
+#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */
+#define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */
+#define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */
+#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */
+#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */
+#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */
+#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */
+#define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */
+#define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */
+/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
+#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */
+#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */
+#define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */
+#define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */
+#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */
+#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */
+#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */
+#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */
+#define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */
+#define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */
+/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
+#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */
+#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */
+#define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */
+#define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */
+#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */
+#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */
+#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */
+#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */
+#define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */
+#define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */
+/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
+#define UART_RHR_RXCHR_Pos 0
+#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */
+/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
+#define UART_THR_TXCHR_Pos 0
+#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */
+#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
+/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define UART_BRGR_CD_Pos 0
+#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */
+#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
+/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */
+#define UART_RPR_RXPTR_Pos 0
+#define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */
+#define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos)))
+/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */
+#define UART_RCR_RXCTR_Pos 0
+#define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */
+#define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos)))
+/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */
+#define UART_TPR_TXPTR_Pos 0
+#define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */
+#define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos)))
+/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */
+#define UART_TCR_TXCTR_Pos 0
+#define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */
+#define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos)))
+/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */
+#define UART_RNPR_RXNPTR_Pos 0
+#define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */
+#define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos)))
+/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */
+#define UART_RNCR_RXNCTR_Pos 0
+#define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */
+#define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos)))
+/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define UART_TNPR_TXNPTR_Pos 0
+#define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */
+#define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos)))
+/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define UART_TNCR_TXNCTR_Pos 0
+#define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */
+#define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos)))
+/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */
+#define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */
+#define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */
+#define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */
+#define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */
+/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */
+#define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */
+#define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3U_UART_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_udphs.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_udphs.h
new file mode 100644
index 000000000..f80d3d6c2
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_udphs.h
@@ -0,0 +1,375 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_UDPHS_COMPONENT_
+#define _SAM3U_UDPHS_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR USB High Speed Device Port */
+/* ============================================================================= */
+/** \addtogroup SAM3U_UDPHS USB High Speed Device Port */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief UdphsDma hardware registers */
+typedef struct {
+  RwReg     UDPHS_DMANXTDSC;  /**< \brief (UdphsDma Offset: 0x0) UDPHS DMA Next Descriptor Address Register */
+  RwReg     UDPHS_DMAADDRESS; /**< \brief (UdphsDma Offset: 0x4) UDPHS DMA Channel Address Register */
+  RwReg     UDPHS_DMACONTROL; /**< \brief (UdphsDma Offset: 0x8) UDPHS DMA Channel Control Register */
+  RwReg     UDPHS_DMASTATUS;  /**< \brief (UdphsDma Offset: 0xC) UDPHS DMA Channel Status Register */
+} UdphsDma;
+/** \brief UdphsEpt hardware registers */
+typedef struct {
+  RwReg     UDPHS_EPTCFG;     /**< \brief (UdphsEpt Offset: 0x0) UDPHS Endpoint Configuration Register */
+  RwReg     UDPHS_EPTCTLENB;  /**< \brief (UdphsEpt Offset: 0x4) UDPHS Endpoint Control Enable Register */
+  RwReg     UDPHS_EPTCTLDIS;  /**< \brief (UdphsEpt Offset: 0x8) UDPHS Endpoint Control Disable Register */
+  RwReg     UDPHS_EPTCTL;     /**< \brief (UdphsEpt Offset: 0xC) UDPHS Endpoint Control Register */
+  RoReg     Reserved1[1];
+  RwReg     UDPHS_EPTSETSTA;  /**< \brief (UdphsEpt Offset: 0x14) UDPHS Endpoint Set Status Register */
+  RwReg     UDPHS_EPTCLRSTA;  /**< \brief (UdphsEpt Offset: 0x18) UDPHS Endpoint Clear Status Register */
+  RwReg     UDPHS_EPTSTA;     /**< \brief (UdphsEpt Offset: 0x1C) UDPHS Endpoint Status Register */
+} UdphsEpt;
+/** \brief Udphs hardware registers */
+#define UDPHSEPT_NUMBER 7
+#define UDPHSDMA_NUMBER 6
+typedef struct {
+  RwReg     UDPHS_CTRL;       /**< \brief (Udphs Offset: 0x00) UDPHS Control Register */
+  RoReg     UDPHS_FNUM;       /**< \brief (Udphs Offset: 0x04) UDPHS Frame Number Register */
+  RoReg     Reserved1[2];
+  RwReg     UDPHS_IEN;        /**< \brief (Udphs Offset: 0x10) UDPHS Interrupt Enable Register */
+  RoReg     UDPHS_INTSTA;     /**< \brief (Udphs Offset: 0x14) UDPHS Interrupt Status Register */
+  WoReg     UDPHS_CLRINT;     /**< \brief (Udphs Offset: 0x18) UDPHS Clear Interrupt Register */
+  WoReg     UDPHS_EPTRST;     /**< \brief (Udphs Offset: 0x1C) UDPHS Endpoints Reset Register */
+  RoReg     Reserved2[48];
+  RwReg     UDPHS_TST;        /**< \brief (Udphs Offset: 0xE0) UDPHS Test Register */
+  RoReg     Reserved3[3];
+  RoReg     UDPHS_IPNAME1;    /**< \brief (Udphs Offset: 0xF0) UDPHS Name1 Register */
+  RoReg     UDPHS_IPNAME2;    /**< \brief (Udphs Offset: 0xF4) UDPHS Name2 Register */
+  RoReg     UDPHS_IPFEATURES; /**< \brief (Udphs Offset: 0xF8) UDPHS Features Register */
+  RoReg     Reserved4[1];
+  UdphsEpt  UDPHS_EPT[UDPHSEPT_NUMBER]; /**< \brief (Udphs Offset: 0x100) endpoint = 0 .. 6 */
+  RoReg     Reserved5[72];
+  UdphsDma  UDPHS_DMA[UDPHSDMA_NUMBER]; /**< \brief (Udphs Offset: 0x300) channel = 0 .. 5 */
+} Udphs;
+#endif /* __ASSEMBLY__ */
+/* -------- UDPHS_CTRL : (UDPHS Offset: 0x00) UDPHS Control Register -------- */
+#define UDPHS_CTRL_DEV_ADDR_Pos 0
+#define UDPHS_CTRL_DEV_ADDR_Msk (0x7fu << UDPHS_CTRL_DEV_ADDR_Pos) /**< \brief (UDPHS_CTRL) UDPHS Address */
+#define UDPHS_CTRL_DEV_ADDR(value) ((UDPHS_CTRL_DEV_ADDR_Msk & ((value) << UDPHS_CTRL_DEV_ADDR_Pos)))
+#define UDPHS_CTRL_FADDR_EN (0x1u << 7) /**< \brief (UDPHS_CTRL) Function Address Enable */
+#define UDPHS_CTRL_EN_UDPHS (0x1u << 8) /**< \brief (UDPHS_CTRL) UDPHS Enable */
+#define UDPHS_CTRL_DETACH (0x1u << 9) /**< \brief (UDPHS_CTRL) Detach Command */
+#define UDPHS_CTRL_REWAKEUP (0x1u << 10) /**< \brief (UDPHS_CTRL) Send Remote Wake Up */
+#define UDPHS_CTRL_PULLD_DIS (0x1u << 11) /**< \brief (UDPHS_CTRL) Pull-Down Disable */
+/* -------- UDPHS_FNUM : (UDPHS Offset: 0x04) UDPHS Frame Number Register -------- */
+#define UDPHS_FNUM_MICRO_FRAME_NUM_Pos 0
+#define UDPHS_FNUM_MICRO_FRAME_NUM_Msk (0x7u << UDPHS_FNUM_MICRO_FRAME_NUM_Pos) /**< \brief (UDPHS_FNUM) Microframe Number */
+#define UDPHS_FNUM_FRAME_NUMBER_Pos 3
+#define UDPHS_FNUM_FRAME_NUMBER_Msk (0x7ffu << UDPHS_FNUM_FRAME_NUMBER_Pos) /**< \brief (UDPHS_FNUM) Frame Number as defined in the Packet Field Formats */
+#define UDPHS_FNUM_FNUM_ERR (0x1u << 31) /**< \brief (UDPHS_FNUM) Frame Number CRC Error */
+/* -------- UDPHS_IEN : (UDPHS Offset: 0x10) UDPHS Interrupt Enable Register -------- */
+#define UDPHS_IEN_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_IEN) Suspend Interrupt Enable */
+#define UDPHS_IEN_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_IEN) Micro-SOF Interrupt Enable */
+#define UDPHS_IEN_INT_SOF (0x1u << 3) /**< \brief (UDPHS_IEN) SOF Interrupt Enable */
+#define UDPHS_IEN_ENDRESET (0x1u << 4) /**< \brief (UDPHS_IEN) End Of Reset Interrupt Enable */
+#define UDPHS_IEN_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_IEN) Wake Up CPU Interrupt Enable */
+#define UDPHS_IEN_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_IEN) End Of Resume Interrupt Enable */
+#define UDPHS_IEN_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_IEN) Upstream Resume Interrupt Enable */
+#define UDPHS_IEN_EPT_0 (0x1u << 8) /**< \brief (UDPHS_IEN) Endpoint 0 Interrupt Enable */
+#define UDPHS_IEN_EPT_1 (0x1u << 9) /**< \brief (UDPHS_IEN) Endpoint 1 Interrupt Enable */
+#define UDPHS_IEN_EPT_2 (0x1u << 10) /**< \brief (UDPHS_IEN) Endpoint 2 Interrupt Enable */
+#define UDPHS_IEN_EPT_3 (0x1u << 11) /**< \brief (UDPHS_IEN) Endpoint 3 Interrupt Enable */
+#define UDPHS_IEN_EPT_4 (0x1u << 12) /**< \brief (UDPHS_IEN) Endpoint 4 Interrupt Enable */
+#define UDPHS_IEN_EPT_5 (0x1u << 13) /**< \brief (UDPHS_IEN) Endpoint 5 Interrupt Enable */
+#define UDPHS_IEN_EPT_6 (0x1u << 14) /**< \brief (UDPHS_IEN) Endpoint 6 Interrupt Enable */
+#define UDPHS_IEN_DMA_1 (0x1u << 25) /**< \brief (UDPHS_IEN) DMA Channel 1 Interrupt Enable */
+#define UDPHS_IEN_DMA_2 (0x1u << 26) /**< \brief (UDPHS_IEN) DMA Channel 2 Interrupt Enable */
+#define UDPHS_IEN_DMA_3 (0x1u << 27) /**< \brief (UDPHS_IEN) DMA Channel 3 Interrupt Enable */
+#define UDPHS_IEN_DMA_4 (0x1u << 28) /**< \brief (UDPHS_IEN) DMA Channel 4 Interrupt Enable */
+#define UDPHS_IEN_DMA_5 (0x1u << 29) /**< \brief (UDPHS_IEN) DMA Channel 5 Interrupt Enable */
+#define UDPHS_IEN_DMA_6 (0x1u << 30) /**< \brief (UDPHS_IEN) DMA Channel 6 Interrupt Enable */
+/* -------- UDPHS_INTSTA : (UDPHS Offset: 0x14) UDPHS Interrupt Status Register -------- */
+#define UDPHS_INTSTA_SPEED (0x1u << 0) /**< \brief (UDPHS_INTSTA) Speed Status */
+#define UDPHS_INTSTA_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_INTSTA) Suspend Interrupt */
+#define UDPHS_INTSTA_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_INTSTA) Micro Start Of Frame Interrupt */
+#define UDPHS_INTSTA_INT_SOF (0x1u << 3) /**< \brief (UDPHS_INTSTA) Start Of Frame Interrupt */
+#define UDPHS_INTSTA_ENDRESET (0x1u << 4) /**< \brief (UDPHS_INTSTA) End Of Reset Interrupt */
+#define UDPHS_INTSTA_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_INTSTA) Wake Up CPU Interrupt */
+#define UDPHS_INTSTA_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_INTSTA) End Of Resume Interrupt */
+#define UDPHS_INTSTA_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_INTSTA) Upstream Resume Interrupt */
+#define UDPHS_INTSTA_EPT_0 (0x1u << 8) /**< \brief (UDPHS_INTSTA) Endpoint 0 Interrupt */
+#define UDPHS_INTSTA_EPT_1 (0x1u << 9) /**< \brief (UDPHS_INTSTA) Endpoint 1 Interrupt */
+#define UDPHS_INTSTA_EPT_2 (0x1u << 10) /**< \brief (UDPHS_INTSTA) Endpoint 2 Interrupt */
+#define UDPHS_INTSTA_EPT_3 (0x1u << 11) /**< \brief (UDPHS_INTSTA) Endpoint 3 Interrupt */
+#define UDPHS_INTSTA_EPT_4 (0x1u << 12) /**< \brief (UDPHS_INTSTA) Endpoint 4 Interrupt */
+#define UDPHS_INTSTA_EPT_5 (0x1u << 13) /**< \brief (UDPHS_INTSTA) Endpoint 5 Interrupt */
+#define UDPHS_INTSTA_EPT_6 (0x1u << 14) /**< \brief (UDPHS_INTSTA) Endpoint 6 Interrupt */
+#define UDPHS_INTSTA_DMA_1 (0x1u << 25) /**< \brief (UDPHS_INTSTA) DMA Channel 1 Interrupt */
+#define UDPHS_INTSTA_DMA_2 (0x1u << 26) /**< \brief (UDPHS_INTSTA) DMA Channel 2 Interrupt */
+#define UDPHS_INTSTA_DMA_3 (0x1u << 27) /**< \brief (UDPHS_INTSTA) DMA Channel 3 Interrupt */
+#define UDPHS_INTSTA_DMA_4 (0x1u << 28) /**< \brief (UDPHS_INTSTA) DMA Channel 4 Interrupt */
+#define UDPHS_INTSTA_DMA_5 (0x1u << 29) /**< \brief (UDPHS_INTSTA) DMA Channel 5 Interrupt */
+#define UDPHS_INTSTA_DMA_6 (0x1u << 30) /**< \brief (UDPHS_INTSTA) DMA Channel 6 Interrupt */
+/* -------- UDPHS_CLRINT : (UDPHS Offset: 0x18) UDPHS Clear Interrupt Register -------- */
+#define UDPHS_CLRINT_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_CLRINT) Suspend Interrupt Clear */
+#define UDPHS_CLRINT_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_CLRINT) Micro Start Of Frame Interrupt Clear */
+#define UDPHS_CLRINT_INT_SOF (0x1u << 3) /**< \brief (UDPHS_CLRINT) Start Of Frame Interrupt Clear */
+#define UDPHS_CLRINT_ENDRESET (0x1u << 4) /**< \brief (UDPHS_CLRINT) End Of Reset Interrupt Clear */
+#define UDPHS_CLRINT_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_CLRINT) Wake Up CPU Interrupt Clear */
+#define UDPHS_CLRINT_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_CLRINT) End Of Resume Interrupt Clear */
+#define UDPHS_CLRINT_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_CLRINT) Upstream Resume Interrupt Clear */
+/* -------- UDPHS_EPTRST : (UDPHS Offset: 0x1C) UDPHS Endpoints Reset Register -------- */
+#define UDPHS_EPTRST_EPT_0 (0x1u << 0) /**< \brief (UDPHS_EPTRST) Endpoint 0 Reset */
+#define UDPHS_EPTRST_EPT_1 (0x1u << 1) /**< \brief (UDPHS_EPTRST) Endpoint 1 Reset */
+#define UDPHS_EPTRST_EPT_2 (0x1u << 2) /**< \brief (UDPHS_EPTRST) Endpoint 2 Reset */
+#define UDPHS_EPTRST_EPT_3 (0x1u << 3) /**< \brief (UDPHS_EPTRST) Endpoint 3 Reset */
+#define UDPHS_EPTRST_EPT_4 (0x1u << 4) /**< \brief (UDPHS_EPTRST) Endpoint 4 Reset */
+#define UDPHS_EPTRST_EPT_5 (0x1u << 5) /**< \brief (UDPHS_EPTRST) Endpoint 5 Reset */
+#define UDPHS_EPTRST_EPT_6 (0x1u << 6) /**< \brief (UDPHS_EPTRST) Endpoint 6 Reset */
+/* -------- UDPHS_TST : (UDPHS Offset: 0xE0) UDPHS Test Register -------- */
+#define UDPHS_TST_SPEED_CFG_Pos 0
+#define UDPHS_TST_SPEED_CFG_Msk (0x3u << UDPHS_TST_SPEED_CFG_Pos) /**< \brief (UDPHS_TST) Speed Configuration */
+#define   UDPHS_TST_SPEED_CFG_NORMAL (0x0u << 0) /**< \brief (UDPHS_TST) Normal Mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host supports it and then to automatically switch to High Speed mode */
+#define   UDPHS_TST_SPEED_CFG_HIGH_SPEED (0x2u << 0) /**< \brief (UDPHS_TST) Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug or test purpose. */
+#define   UDPHS_TST_SPEED_CFG_FULL_SPEED (0x3u << 0) /**< \brief (UDPHS_TST) Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this configuration, the macro will not respond to a High Speed reset handshake. */
+#define UDPHS_TST_TST_J (0x1u << 2) /**< \brief (UDPHS_TST) Test J Mode */
+#define UDPHS_TST_TST_K (0x1u << 3) /**< \brief (UDPHS_TST) Test K Mode */
+#define UDPHS_TST_TST_PKT (0x1u << 4) /**< \brief (UDPHS_TST) Test Packet Mode */
+#define UDPHS_TST_OPMODE2 (0x1u << 5) /**< \brief (UDPHS_TST) OpMode2 */
+/* -------- UDPHS_IPNAME1 : (UDPHS Offset: 0xF0) UDPHS Name1 Register -------- */
+#define UDPHS_IPNAME1_IP_NAME1_Pos 0
+#define UDPHS_IPNAME1_IP_NAME1_Msk (0xffffffffu << UDPHS_IPNAME1_IP_NAME1_Pos) /**< \brief (UDPHS_IPNAME1)  */
+/* -------- UDPHS_IPNAME2 : (UDPHS Offset: 0xF4) UDPHS Name2 Register -------- */
+#define UDPHS_IPNAME2_IP_NAME2_Pos 0
+#define UDPHS_IPNAME2_IP_NAME2_Msk (0xffffffffu << UDPHS_IPNAME2_IP_NAME2_Pos) /**< \brief (UDPHS_IPNAME2)  */
+/* -------- UDPHS_IPFEATURES : (UDPHS Offset: 0xF8) UDPHS Features Register -------- */
+#define UDPHS_IPFEATURES_EPT_NBR_MAX_Pos 0
+#define UDPHS_IPFEATURES_EPT_NBR_MAX_Msk (0xfu << UDPHS_IPFEATURES_EPT_NBR_MAX_Pos) /**< \brief (UDPHS_IPFEATURES) Max Number of Endpoints */
+#define UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Pos 4
+#define UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Msk (0x7u << UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Pos) /**< \brief (UDPHS_IPFEATURES) Number of DMA Channels */
+#define UDPHS_IPFEATURES_DMA_B_SIZ (0x1u << 7) /**< \brief (UDPHS_IPFEATURES) DMA Buffer Size */
+#define UDPHS_IPFEATURES_DMA_FIFO_WORD_DEPTH_Pos 8
+#define UDPHS_IPFEATURES_DMA_FIFO_WORD_DEPTH_Msk (0xfu << UDPHS_IPFEATURES_DMA_FIFO_WORD_DEPTH_Pos) /**< \brief (UDPHS_IPFEATURES) DMA FIFO Depth in Words */
+#define UDPHS_IPFEATURES_FIFO_MAX_SIZE_Pos 12
+#define UDPHS_IPFEATURES_FIFO_MAX_SIZE_Msk (0x7u << UDPHS_IPFEATURES_FIFO_MAX_SIZE_Pos) /**< \brief (UDPHS_IPFEATURES) DPRAM Size */
+#define UDPHS_IPFEATURES_BW_DPRAM (0x1u << 15) /**< \brief (UDPHS_IPFEATURES) DPRAM Byte Write Capability */
+#define UDPHS_IPFEATURES_DATAB16_8 (0x1u << 16) /**< \brief (UDPHS_IPFEATURES) UTMI DataBus16_8 */
+#define UDPHS_IPFEATURES_ISO_EPT_1 (0x1u << 17) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_2 (0x1u << 18) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_3 (0x1u << 19) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_4 (0x1u << 20) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_5 (0x1u << 21) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_6 (0x1u << 22) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_7 (0x1u << 23) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_8 (0x1u << 24) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_9 (0x1u << 25) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_10 (0x1u << 26) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_11 (0x1u << 27) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_12 (0x1u << 28) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_13 (0x1u << 29) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_14 (0x1u << 30) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_15 (0x1u << 31) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+/* -------- UDPHS_EPTCFG : (UDPHS Offset: N/A) UDPHS Endpoint Configuration Register -------- */
+#define UDPHS_EPTCFG_EPT_SIZE_Pos 0
+#define UDPHS_EPTCFG_EPT_SIZE_Msk (0x7u << UDPHS_EPTCFG_EPT_SIZE_Pos) /**< \brief (UDPHS_EPTCFG) Endpoint Size */
+#define   UDPHS_EPTCFG_EPT_SIZE_8 (0x0u << 0) /**< \brief (UDPHS_EPTCFG) 8 bytes */
+#define   UDPHS_EPTCFG_EPT_SIZE_16 (0x1u << 0) /**< \brief (UDPHS_EPTCFG) 16 bytes */
+#define   UDPHS_EPTCFG_EPT_SIZE_32 (0x2u << 0) /**< \brief (UDPHS_EPTCFG) 32 bytes */
+#define   UDPHS_EPTCFG_EPT_SIZE_64 (0x3u << 0) /**< \brief (UDPHS_EPTCFG) 64 bytes */
+#define   UDPHS_EPTCFG_EPT_SIZE_128 (0x4u << 0) /**< \brief (UDPHS_EPTCFG) 128 bytes */
+#define   UDPHS_EPTCFG_EPT_SIZE_256 (0x5u << 0) /**< \brief (UDPHS_EPTCFG) 256 bytes */
+#define   UDPHS_EPTCFG_EPT_SIZE_512 (0x6u << 0) /**< \brief (UDPHS_EPTCFG) 512 bytes */
+#define   UDPHS_EPTCFG_EPT_SIZE_1024 (0x7u << 0) /**< \brief (UDPHS_EPTCFG) 1024 bytes */
+#define UDPHS_EPTCFG_EPT_DIR (0x1u << 3) /**< \brief (UDPHS_EPTCFG) Endpoint Direction */
+#define UDPHS_EPTCFG_EPT_TYPE_Pos 4
+#define UDPHS_EPTCFG_EPT_TYPE_Msk (0x3u << UDPHS_EPTCFG_EPT_TYPE_Pos) /**< \brief (UDPHS_EPTCFG) Endpoint Type */
+#define   UDPHS_EPTCFG_EPT_TYPE_CTRL8 (0x0u << 4) /**< \brief (UDPHS_EPTCFG) Control endpoint */
+#define   UDPHS_EPTCFG_EPT_TYPE_ISO (0x1u << 4) /**< \brief (UDPHS_EPTCFG) Isochronous endpoint */
+#define   UDPHS_EPTCFG_EPT_TYPE_BULK (0x2u << 4) /**< \brief (UDPHS_EPTCFG) Bulk endpoint */
+#define   UDPHS_EPTCFG_EPT_TYPE_INT (0x3u << 4) /**< \brief (UDPHS_EPTCFG) Interrupt endpoint */
+#define UDPHS_EPTCFG_BK_NUMBER_Pos 6
+#define UDPHS_EPTCFG_BK_NUMBER_Msk (0x3u << UDPHS_EPTCFG_BK_NUMBER_Pos) /**< \brief (UDPHS_EPTCFG) Number of Banks */
+#define   UDPHS_EPTCFG_BK_NUMBER_0 (0x0u << 6) /**< \brief (UDPHS_EPTCFG) Zero bank, the endpoint is not mapped in memory */
+#define   UDPHS_EPTCFG_BK_NUMBER_1 (0x1u << 6) /**< \brief (UDPHS_EPTCFG) One bank (bank 0) */
+#define   UDPHS_EPTCFG_BK_NUMBER_2 (0x2u << 6) /**< \brief (UDPHS_EPTCFG) Double bank (Ping-Pong: bank0/bank1) */
+#define   UDPHS_EPTCFG_BK_NUMBER_3 (0x3u << 6) /**< \brief (UDPHS_EPTCFG) Triple bank (bank0/bank1/bank2) */
+#define UDPHS_EPTCFG_NB_TRANS_Pos 8
+#define UDPHS_EPTCFG_NB_TRANS_Msk (0x3u << UDPHS_EPTCFG_NB_TRANS_Pos) /**< \brief (UDPHS_EPTCFG) Number Of Transaction per Microframe */
+#define UDPHS_EPTCFG_NB_TRANS(value) ((UDPHS_EPTCFG_NB_TRANS_Msk & ((value) << UDPHS_EPTCFG_NB_TRANS_Pos)))
+#define UDPHS_EPTCFG_EPT_MAPD (0x1u << 31) /**< \brief (UDPHS_EPTCFG) Endpoint Mapped */
+/* -------- UDPHS_EPTCTLENB : (UDPHS Offset: N/A) UDPHS Endpoint Control Enable Register -------- */
+#define UDPHS_EPTCTLENB_EPT_ENABL (0x1u << 0) /**< \brief (UDPHS_EPTCTLENB) Endpoint Enable */
+#define UDPHS_EPTCTLENB_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTLENB) Packet Auto-Valid Enable */
+#define UDPHS_EPTCTLENB_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTLENB) Interrupts Disable DMA */
+#define UDPHS_EPTCTLENB_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTLENB) NYET Disable (Only for High Speed Bulk OUT endpoints) */
+#define UDPHS_EPTCTLENB_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTLENB) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */
+#define UDPHS_EPTCTLENB_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTLENB) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */
+#define UDPHS_EPTCTLENB_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTLENB) Overflow Error Interrupt Enable */
+#define UDPHS_EPTCTLENB_RX_BK_RDY (0x1u << 9) /**< \brief (UDPHS_EPTCTLENB) Received OUT Data Interrupt Enable */
+#define UDPHS_EPTCTLENB_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTLENB) Transmitted IN Data Complete Interrupt Enable */
+#define UDPHS_EPTCTLENB_TX_PK_RDY (0x1u << 11) /**< \brief (UDPHS_EPTCTLENB) TX Packet Ready/Transaction Error Interrupt Enable */
+#define UDPHS_EPTCTLENB_ERR_TRANS (0x1u << 11) /**< \brief (UDPHS_EPTCTLENB) TX Packet Ready/Transaction Error Interrupt Enable */
+#define UDPHS_EPTCTLENB_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTLENB) Received SETUP/Error Flow Interrupt Enable */
+#define UDPHS_EPTCTLENB_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTLENB) Received SETUP/Error Flow Interrupt Enable */
+#define UDPHS_EPTCTLENB_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTLENB) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */
+#define UDPHS_EPTCTLENB_ERR_CRISO (0x1u << 13) /**< \brief (UDPHS_EPTCTLENB) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */
+#define UDPHS_EPTCTLENB_ERR_NBTRA (0x1u << 13) /**< \brief (UDPHS_EPTCTLENB) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */
+#define UDPHS_EPTCTLENB_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTLENB) NAKIN/Bank Flush Error Interrupt Enable */
+#define UDPHS_EPTCTLENB_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTLENB) NAKIN/Bank Flush Error Interrupt Enable */
+#define UDPHS_EPTCTLENB_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTLENB) NAKOUT Interrupt Enable */
+#define UDPHS_EPTCTLENB_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTLENB) Busy Bank Interrupt Enable */
+#define UDPHS_EPTCTLENB_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTLENB) Short Packet Send/Short Packet Interrupt Enable */
+/* -------- UDPHS_EPTCTLDIS : (UDPHS Offset: N/A) UDPHS Endpoint Control Disable Register -------- */
+#define UDPHS_EPTCTLDIS_EPT_DISABL (0x1u << 0) /**< \brief (UDPHS_EPTCTLDIS) Endpoint Disable */
+#define UDPHS_EPTCTLDIS_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTLDIS) Packet Auto-Valid Disable */
+#define UDPHS_EPTCTLDIS_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTLDIS) Interrupts Disable DMA */
+#define UDPHS_EPTCTLDIS_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTLDIS) NYET Enable (Only for High Speed Bulk OUT endpoints) */
+#define UDPHS_EPTCTLDIS_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTLDIS) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */
+#define UDPHS_EPTCTLDIS_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTLDIS) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */
+#define UDPHS_EPTCTLDIS_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTLDIS) Overflow Error Interrupt Disable */
+#define UDPHS_EPTCTLDIS_RX_BK_RDY (0x1u << 9) /**< \brief (UDPHS_EPTCTLDIS) Received OUT Data Interrupt Disable */
+#define UDPHS_EPTCTLDIS_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTLDIS) Transmitted IN Data Complete Interrupt Disable */
+#define UDPHS_EPTCTLDIS_TX_PK_RDY (0x1u << 11) /**< \brief (UDPHS_EPTCTLDIS) TX Packet Ready/Transaction Error Interrupt Disable */
+#define UDPHS_EPTCTLDIS_ERR_TRANS (0x1u << 11) /**< \brief (UDPHS_EPTCTLDIS) TX Packet Ready/Transaction Error Interrupt Disable */
+#define UDPHS_EPTCTLDIS_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTLDIS) Received SETUP/Error Flow Interrupt Disable */
+#define UDPHS_EPTCTLDIS_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTLDIS) Received SETUP/Error Flow Interrupt Disable */
+#define UDPHS_EPTCTLDIS_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTLDIS) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */
+#define UDPHS_EPTCTLDIS_ERR_CRISO (0x1u << 13) /**< \brief (UDPHS_EPTCTLDIS) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */
+#define UDPHS_EPTCTLDIS_ERR_NBTRA (0x1u << 13) /**< \brief (UDPHS_EPTCTLDIS) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */
+#define UDPHS_EPTCTLDIS_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTLDIS) NAKIN/bank flush error Interrupt Disable */
+#define UDPHS_EPTCTLDIS_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTLDIS) NAKIN/bank flush error Interrupt Disable */
+#define UDPHS_EPTCTLDIS_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTLDIS) NAKOUT Interrupt Disable */
+#define UDPHS_EPTCTLDIS_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTLDIS) Busy Bank Interrupt Disable */
+#define UDPHS_EPTCTLDIS_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTLDIS) Short Packet Interrupt Disable */
+/* -------- UDPHS_EPTCTL : (UDPHS Offset: N/A) UDPHS Endpoint Control Register -------- */
+#define UDPHS_EPTCTL_EPT_ENABL (0x1u << 0) /**< \brief (UDPHS_EPTCTL) Endpoint Enable */
+#define UDPHS_EPTCTL_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTL) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */
+#define UDPHS_EPTCTL_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTL) Interrupt Disables DMA */
+#define UDPHS_EPTCTL_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTL) NYET Disable (Only for High Speed Bulk OUT endpoints) */
+#define UDPHS_EPTCTL_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTL) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */
+#define UDPHS_EPTCTL_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTL) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */
+#define UDPHS_EPTCTL_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTL) Overflow Error Interrupt Enabled */
+#define UDPHS_EPTCTL_RX_BK_RDY (0x1u << 9) /**< \brief (UDPHS_EPTCTL) Received OUT Data Interrupt Enabled */
+#define UDPHS_EPTCTL_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTL) Transmitted IN Data Complete Interrupt Enabled */
+#define UDPHS_EPTCTL_TX_PK_RDY (0x1u << 11) /**< \brief (UDPHS_EPTCTL) TX Packet Ready/Transaction Error Interrupt Enabled */
+#define UDPHS_EPTCTL_ERR_TRANS (0x1u << 11) /**< \brief (UDPHS_EPTCTL) TX Packet Ready/Transaction Error Interrupt Enabled */
+#define UDPHS_EPTCTL_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTL) Received SETUP/Error Flow Interrupt Enabled */
+#define UDPHS_EPTCTL_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTL) Received SETUP/Error Flow Interrupt Enabled */
+#define UDPHS_EPTCTL_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTL) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */
+#define UDPHS_EPTCTL_ERR_CRISO (0x1u << 13) /**< \brief (UDPHS_EPTCTL) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */
+#define UDPHS_EPTCTL_ERR_NBTRA (0x1u << 13) /**< \brief (UDPHS_EPTCTL) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */
+#define UDPHS_EPTCTL_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTL) NAKIN/Bank Flush Error Interrupt Enabled */
+#define UDPHS_EPTCTL_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTL) NAKIN/Bank Flush Error Interrupt Enabled */
+#define UDPHS_EPTCTL_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTL) NAKOUT Interrupt Enabled */
+#define UDPHS_EPTCTL_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTL) Busy Bank Interrupt Enabled */
+#define UDPHS_EPTCTL_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTL) Short Packet Interrupt Enabled */
+/* -------- UDPHS_EPTSETSTA : (UDPHS Offset: N/A) UDPHS Endpoint Set Status Register -------- */
+#define UDPHS_EPTSETSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTSETSTA) Stall Handshake Request Set */
+#define UDPHS_EPTSETSTA_KILL_BANK (0x1u << 9) /**< \brief (UDPHS_EPTSETSTA) KILL Bank Set (for IN Endpoint) */
+#define UDPHS_EPTSETSTA_TX_PK_RDY (0x1u << 11) /**< \brief (UDPHS_EPTSETSTA) TX Packet Ready Set */
+/* -------- UDPHS_EPTCLRSTA : (UDPHS Offset: N/A) UDPHS Endpoint Clear Status Register -------- */
+#define UDPHS_EPTCLRSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTCLRSTA) Stall Handshake Request Clear */
+#define UDPHS_EPTCLRSTA_TOGGLESQ (0x1u << 6) /**< \brief (UDPHS_EPTCLRSTA) Data Toggle Clear */
+#define UDPHS_EPTCLRSTA_RX_BK_RDY (0x1u << 9) /**< \brief (UDPHS_EPTCLRSTA) Received OUT Data Clear */
+#define UDPHS_EPTCLRSTA_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCLRSTA) Transmitted IN Data Complete Clear */
+#define UDPHS_EPTCLRSTA_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCLRSTA) Received SETUP/Error Flow Clear */
+#define UDPHS_EPTCLRSTA_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCLRSTA) Received SETUP/Error Flow Clear */
+#define UDPHS_EPTCLRSTA_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCLRSTA) Stall Sent/Number of Transaction Error Clear */
+#define UDPHS_EPTCLRSTA_ERR_NBTRA (0x1u << 13) /**< \brief (UDPHS_EPTCLRSTA) Stall Sent/Number of Transaction Error Clear */
+#define UDPHS_EPTCLRSTA_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCLRSTA) NAKIN/Bank Flush Error Clear */
+#define UDPHS_EPTCLRSTA_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCLRSTA) NAKIN/Bank Flush Error Clear */
+#define UDPHS_EPTCLRSTA_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCLRSTA) NAKOUT Clear */
+/* -------- UDPHS_EPTSTA : (UDPHS Offset: N/A) UDPHS Endpoint Status Register -------- */
+#define UDPHS_EPTSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTSTA) Stall Handshake Request */
+#define UDPHS_EPTSTA_TOGGLESQ_STA_Pos 6
+#define UDPHS_EPTSTA_TOGGLESQ_STA_Msk (0x3u << UDPHS_EPTSTA_TOGGLESQ_STA_Pos) /**< \brief (UDPHS_EPTSTA) Toggle Sequencing */
+#define   UDPHS_EPTSTA_TOGGLESQ_STA_DATA0 (0x0u << 6) /**< \brief (UDPHS_EPTSTA) DATA0 */
+#define   UDPHS_EPTSTA_TOGGLESQ_STA_DATA1 (0x1u << 6) /**< \brief (UDPHS_EPTSTA) DATA1 */
+#define   UDPHS_EPTSTA_TOGGLESQ_STA_DATA2 (0x2u << 6) /**< \brief (UDPHS_EPTSTA) Data2 (only for High Bandwidth Isochronous Endpoint) */
+#define   UDPHS_EPTSTA_TOGGLESQ_STA_MDATA (0x3u << 6) /**< \brief (UDPHS_EPTSTA) MData (only for High Bandwidth Isochronous Endpoint) */
+#define UDPHS_EPTSTA_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTSTA) Overflow Error */
+#define UDPHS_EPTSTA_RX_BK_RDY (0x1u << 9) /**< \brief (UDPHS_EPTSTA) Received OUT Data/KILL Bank */
+#define UDPHS_EPTSTA_KILL_BANK (0x1u << 9) /**< \brief (UDPHS_EPTSTA) Received OUT Data/KILL Bank */
+#define UDPHS_EPTSTA_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTSTA) Transmitted IN Data Complete */
+#define UDPHS_EPTSTA_TX_PK_RDY (0x1u << 11) /**< \brief (UDPHS_EPTSTA) TX Packet Ready/Transaction Error */
+#define UDPHS_EPTSTA_ERR_TRANS (0x1u << 11) /**< \brief (UDPHS_EPTSTA) TX Packet Ready/Transaction Error */
+#define UDPHS_EPTSTA_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTSTA) Received SETUP/Error Flow */
+#define UDPHS_EPTSTA_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTSTA) Received SETUP/Error Flow */
+#define UDPHS_EPTSTA_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTSTA) Stall Sent/CRC ISO Error/Number of Transaction Error */
+#define UDPHS_EPTSTA_ERR_CRISO (0x1u << 13) /**< \brief (UDPHS_EPTSTA) Stall Sent/CRC ISO Error/Number of Transaction Error */
+#define UDPHS_EPTSTA_ERR_NBTRA (0x1u << 13) /**< \brief (UDPHS_EPTSTA) Stall Sent/CRC ISO Error/Number of Transaction Error */
+#define UDPHS_EPTSTA_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTSTA) NAK IN/Bank Flush Error */
+#define UDPHS_EPTSTA_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTSTA) NAK IN/Bank Flush Error */
+#define UDPHS_EPTSTA_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTSTA) NAK OUT */
+#define UDPHS_EPTSTA_CURRENT_BANK_Pos 16
+#define UDPHS_EPTSTA_CURRENT_BANK_Msk (0x3u << UDPHS_EPTSTA_CURRENT_BANK_Pos) /**< \brief (UDPHS_EPTSTA) Current Bank/Control Direction */
+#define UDPHS_EPTSTA_CONTROL_DIR_Pos 16
+#define UDPHS_EPTSTA_CONTROL_DIR_Msk (0x3u << UDPHS_EPTSTA_CONTROL_DIR_Pos) /**< \brief (UDPHS_EPTSTA) Current Bank/Control Direction */
+#define UDPHS_EPTSTA_BUSY_BANK_STA_Pos 18
+#define UDPHS_EPTSTA_BUSY_BANK_STA_Msk (0x3u << UDPHS_EPTSTA_BUSY_BANK_STA_Pos) /**< \brief (UDPHS_EPTSTA) Busy Bank Number */
+#define   UDPHS_EPTSTA_BUSY_BANK_STA_1BUSYBANK (0x0u << 18) /**< \brief (UDPHS_EPTSTA) 1 busy bank */
+#define   UDPHS_EPTSTA_BUSY_BANK_STA_2BUSYBANKS (0x1u << 18) /**< \brief (UDPHS_EPTSTA) 2 busy banks */
+#define   UDPHS_EPTSTA_BUSY_BANK_STA_3BUSYBANKS (0x2u << 18) /**< \brief (UDPHS_EPTSTA) 3 busy banks */
+#define UDPHS_EPTSTA_BYTE_COUNT_Pos 20
+#define UDPHS_EPTSTA_BYTE_COUNT_Msk (0x7ffu << UDPHS_EPTSTA_BYTE_COUNT_Pos) /**< \brief (UDPHS_EPTSTA) UDPHS Byte Count */
+#define UDPHS_EPTSTA_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTSTA) Short Packet */
+/* -------- UDPHS_DMANXTDSC : (UDPHS Offset: N/A) UDPHS DMA Next Descriptor Address Register -------- */
+#define UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos 0
+#define UDPHS_DMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UDPHS_DMANXTDSC)  */
+#define UDPHS_DMANXTDSC_NXT_DSC_ADD(value) ((UDPHS_DMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos)))
+/* -------- UDPHS_DMAADDRESS : (UDPHS Offset: N/A) UDPHS DMA Channel Address Register -------- */
+#define UDPHS_DMAADDRESS_BUFF_ADD_Pos 0
+#define UDPHS_DMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UDPHS_DMAADDRESS_BUFF_ADD_Pos) /**< \brief (UDPHS_DMAADDRESS)  */
+#define UDPHS_DMAADDRESS_BUFF_ADD(value) ((UDPHS_DMAADDRESS_BUFF_ADD_Msk & ((value) << UDPHS_DMAADDRESS_BUFF_ADD_Pos)))
+/* -------- UDPHS_DMACONTROL : (UDPHS Offset: N/A) UDPHS DMA Channel Control Register -------- */
+#define UDPHS_DMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UDPHS_DMACONTROL)  */
+#define UDPHS_DMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UDPHS_DMACONTROL) Load Next Channel Transfer Descriptor Enable (Command) */
+#define UDPHS_DMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UDPHS_DMACONTROL) End of Transfer Enable (Control) */
+#define UDPHS_DMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UDPHS_DMACONTROL) End of Buffer Enable (Control) */
+#define UDPHS_DMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UDPHS_DMACONTROL) End of Transfer Interrupt Enable */
+#define UDPHS_DMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UDPHS_DMACONTROL) End of Buffer Interrupt Enable */
+#define UDPHS_DMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UDPHS_DMACONTROL) Descriptor Loaded Interrupt Enable */
+#define UDPHS_DMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UDPHS_DMACONTROL) Burst Lock Enable */
+#define UDPHS_DMACONTROL_BUFF_LENGTH_Pos 16
+#define UDPHS_DMACONTROL_BUFF_LENGTH_Msk (0xffffu << UDPHS_DMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UDPHS_DMACONTROL) Buffer Byte Length (Write-only) */
+#define UDPHS_DMACONTROL_BUFF_LENGTH(value) ((UDPHS_DMACONTROL_BUFF_LENGTH_Msk & ((value) << UDPHS_DMACONTROL_BUFF_LENGTH_Pos)))
+/* -------- UDPHS_DMASTATUS : (UDPHS Offset: N/A) UDPHS DMA Channel Status Register -------- */
+#define UDPHS_DMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UDPHS_DMASTATUS) Channel Enable Status */
+#define UDPHS_DMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UDPHS_DMASTATUS) Channel Active Status */
+#define UDPHS_DMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UDPHS_DMASTATUS) End of Channel Transfer Status */
+#define UDPHS_DMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UDPHS_DMASTATUS) End of Channel Buffer Status */
+#define UDPHS_DMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UDPHS_DMASTATUS) Descriptor Loaded Status */
+#define UDPHS_DMASTATUS_BUFF_COUNT_Pos 16
+#define UDPHS_DMASTATUS_BUFF_COUNT_Msk (0xffffu << UDPHS_DMASTATUS_BUFF_COUNT_Pos) /**< \brief (UDPHS_DMASTATUS) Buffer Byte Count */
+#define UDPHS_DMASTATUS_BUFF_COUNT(value) ((UDPHS_DMASTATUS_BUFF_COUNT_Msk & ((value) << UDPHS_DMASTATUS_BUFF_COUNT_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3U_UDPHS_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_usart.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_usart.h
new file mode 100644
index 000000000..e90aa6191
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_usart.h
@@ -0,0 +1,355 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_USART_COMPONENT_
+#define _SAM3U_USART_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM3U_USART Universal Synchronous Asynchronous Receiver Transmitter */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Usart hardware registers */
+typedef struct {
+  WoReg US_CR;         /**< \brief (Usart Offset: 0x0000) Control Register */
+  RwReg US_MR;         /**< \brief (Usart Offset: 0x0004) Mode Register */
+  WoReg US_IER;        /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */
+  WoReg US_IDR;        /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */
+  RoReg US_IMR;        /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */
+  RoReg US_CSR;        /**< \brief (Usart Offset: 0x0014) Channel Status Register */
+  RoReg US_RHR;        /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */
+  WoReg US_THR;        /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */
+  RwReg US_BRGR;       /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */
+  RwReg US_RTOR;       /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */
+  RwReg US_TTGR;       /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */
+  RoReg Reserved1[5];
+  RwReg US_FIDI;       /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */
+  RoReg US_NER;        /**< \brief (Usart Offset: 0x0044) Number of Errors Register */
+  RoReg Reserved2[1];
+  RwReg US_IF;         /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */
+  RwReg US_MAN;        /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */
+  RoReg Reserved3[36];
+  RwReg US_WPMR;       /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */
+  RoReg US_WPSR;       /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved4[5];
+  RwReg US_RPR;        /**< \brief (Usart Offset: 0x100) Receive Pointer Register */
+  RwReg US_RCR;        /**< \brief (Usart Offset: 0x104) Receive Counter Register */
+  RwReg US_TPR;        /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */
+  RwReg US_TCR;        /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */
+  RwReg US_RNPR;       /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */
+  RwReg US_RNCR;       /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */
+  RwReg US_TNPR;       /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */
+  RwReg US_TNCR;       /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */
+  WoReg US_PTCR;       /**< \brief (Usart Offset: 0x120) Transfer Control Register */
+  RoReg US_PTSR;       /**< \brief (Usart Offset: 0x124) Transfer Status Register */
+} Usart;
+#endif /* __ASSEMBLY__ */
+/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
+#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */
+#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */
+#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */
+#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */
+#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */
+#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */
+#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */
+#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */
+#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */
+#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */
+#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */
+#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */
+#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */
+#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */
+#define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */
+#define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */
+#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */
+#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */
+#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */
+#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */
+/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
+#define US_MR_USART_MODE_Pos 0
+#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR)  */
+#define   US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */
+#define   US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */
+#define   US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */
+#define   US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */
+#define   US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */
+#define   US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */
+#define   US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */
+#define   US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */
+#define   US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */
+#define US_MR_USCLKS_Pos 4
+#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */
+#define   US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */
+#define   US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */
+#define   US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */
+#define US_MR_CHRL_Pos 6
+#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */
+#define   US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */
+#define   US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */
+#define   US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */
+#define   US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */
+#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */
+#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */
+#define US_MR_PAR_Pos 9
+#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */
+#define   US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */
+#define   US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */
+#define   US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */
+#define   US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */
+#define   US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */
+#define   US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */
+#define US_MR_NBSTOP_Pos 12
+#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */
+#define   US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */
+#define   US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */
+#define   US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */
+#define US_MR_CHMODE_Pos 14
+#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */
+#define   US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */
+#define   US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */
+#define   US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */
+#define   US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */
+#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */
+#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */
+#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */
+#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */
+#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */
+#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */
+#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */
+#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */
+#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) INverted Data */
+#define US_MR_MAX_ITERATION_Pos 24
+#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR)  */
+#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))
+#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */
+#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */
+#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */
+#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */
+/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
+#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */
+#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */
+#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */
+#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */
+#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */
+#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */
+#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */
+#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */
+#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */
+#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */
+#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached */
+#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error */
+#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */
+#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */
+#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non AcknowledgeInterrupt Enable */
+#define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */
+#define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */
+#define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */
+#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
+#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */
+/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
+#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */
+#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */
+#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */
+#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */
+#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */
+#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */
+#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */
+#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */
+#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */
+#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */
+#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max number of Repetitions Reached Disable */
+#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Disable */
+#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */
+#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */
+#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non AcknowledgeInterrupt Disable */
+#define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */
+#define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */
+#define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */
+#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
+#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */
+/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
+#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */
+#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */
+#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */
+#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */
+#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */
+#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */
+#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */
+#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */
+#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */
+#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
+#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max number of Repetitions Reached Mask */
+#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Mask */
+#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */
+#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */
+#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non AcknowledgeInterrupt Mask */
+#define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */
+#define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */
+#define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */
+#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
+#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */
+/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
+#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */
+#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */
+#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */
+#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */
+#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */
+#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */
+#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */
+#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */
+#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */
+#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */
+#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max number of Repetitions Reached */
+#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) SPI Underrun Error */
+#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */
+#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */
+#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non AcknowledgeInterrupt */
+#define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */
+#define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */
+#define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */
+#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */
+#define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */
+#define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */
+#define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */
+#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */
+#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */
+/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */
+#define US_RHR_RXCHR_Pos 0
+#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */
+#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */
+/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */
+#define US_THR_TXCHR_Pos 0
+#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */
+#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
+#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be transmitted */
+/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define US_BRGR_CD_Pos 0
+#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */
+#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
+#define US_BRGR_FP_Pos 16
+#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */
+#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
+/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
+#define US_RTOR_TO_Pos 0
+#define US_RTOR_TO_Msk (0xffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */
+#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
+/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
+#define US_TTGR_TG_Pos 0
+#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */
+#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
+/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */
+#define US_FIDI_FI_DI_RATIO_Pos 0
+#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */
+#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))
+/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */
+#define US_NER_NB_ERRORS_Pos 0
+#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */
+/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */
+#define US_IF_IRDA_FILTER_Pos 0
+#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */
+#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))
+/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */
+#define US_MAN_TX_PL_Pos 0
+#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */
+#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))
+#define US_MAN_TX_PP_Pos 8
+#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */
+#define   US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */
+#define   US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */
+#define   US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */
+#define   US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */
+#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */
+#define US_MAN_RX_PL_Pos 16
+#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */
+#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))
+#define US_MAN_RX_PP_Pos 24
+#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */
+#define   US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */
+#define   US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */
+#define   US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */
+#define   US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */
+#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */
+#define US_MAN_STUCKTO1 (0x1u << 29) /**< \brief (US_MAN)  */
+#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift compensation */
+/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */
+#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */
+#define US_WPMR_WPKEY_Pos 8
+#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */
+#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))
+/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */
+#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */
+#define US_WPSR_WPVSRC_Pos 8
+#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */
+/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */
+#define US_RPR_RXPTR_Pos 0
+#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */
+#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos)))
+/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */
+#define US_RCR_RXCTR_Pos 0
+#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */
+#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos)))
+/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */
+#define US_TPR_TXPTR_Pos 0
+#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */
+#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos)))
+/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */
+#define US_TCR_TXCTR_Pos 0
+#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */
+#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos)))
+/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */
+#define US_RNPR_RXNPTR_Pos 0
+#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */
+#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos)))
+/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */
+#define US_RNCR_RXNCTR_Pos 0
+#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */
+#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos)))
+/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define US_TNPR_TXNPTR_Pos 0
+#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */
+#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos)))
+/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define US_TNCR_TXNCTR_Pos 0
+#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */
+#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos)))
+/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */
+#define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */
+#define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */
+#define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */
+#define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */
+/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */
+#define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */
+#define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3U_USART_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_wdt.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_wdt.h
new file mode 100644
index 000000000..bcf3f478f
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/component_wdt.h
@@ -0,0 +1,72 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_WDT_COMPONENT_
+#define _SAM3U_WDT_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Watchdog Timer */
+/* ============================================================================= */
+/** \addtogroup SAM3U_WDT Watchdog Timer */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Wdt hardware registers */
+typedef struct {
+  WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */
+  RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */
+  RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */
+} Wdt;
+#endif /* __ASSEMBLY__ */
+/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */
+#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */
+#define WDT_CR_KEY_Pos 24
+#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */
+#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))
+/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */
+#define WDT_MR_WDV_Pos 0
+#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */
+#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))
+#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */
+#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */
+#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */
+#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */
+#define WDT_MR_WDD_Pos 16
+#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */
+#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))
+#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */
+#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */
+/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */
+#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */
+#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */
+
+/*@}*/
+
+
+#endif /* _SAM3U_WDT_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_adc.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_adc.h
new file mode 100644
index 000000000..eb16f3c0d
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_adc.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_ADC_INSTANCE_
+#define _SAM3U_ADC_INSTANCE_
+
+/* ========== Register definition for ADC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_ADC_CR              (0x400AC000U) /**< \brief (ADC) Control Register */
+#define REG_ADC_MR              (0x400AC004U) /**< \brief (ADC) Mode Register */
+#define REG_ADC_CHER            (0x400AC010U) /**< \brief (ADC) Channel Enable Register */
+#define REG_ADC_CHDR            (0x400AC014U) /**< \brief (ADC) Channel Disable Register */
+#define REG_ADC_CHSR            (0x400AC018U) /**< \brief (ADC) Channel Status Register */
+#define REG_ADC_SR              (0x400AC01CU) /**< \brief (ADC) Status Register */
+#define REG_ADC_LCDR            (0x400AC020U) /**< \brief (ADC) Last Converted Data Register */
+#define REG_ADC_IER             (0x400AC024U) /**< \brief (ADC) Interrupt Enable Register */
+#define REG_ADC_IDR             (0x400AC028U) /**< \brief (ADC) Interrupt Disable Register */
+#define REG_ADC_IMR             (0x400AC02CU) /**< \brief (ADC) Interrupt Mask Register */
+#define REG_ADC_CDR             (0x400AC030U) /**< \brief (ADC) Channel Data Register */
+#define REG_ADC_RPR             (0x400AC100U) /**< \brief (ADC) Receive Pointer Register */
+#define REG_ADC_RCR             (0x400AC104U) /**< \brief (ADC) Receive Counter Register */
+#define REG_ADC_TPR             (0x400AC108U) /**< \brief (ADC) Transmit Pointer Register */
+#define REG_ADC_TCR             (0x400AC10CU) /**< \brief (ADC) Transmit Counter Register */
+#define REG_ADC_RNPR            (0x400AC110U) /**< \brief (ADC) Receive Next Pointer Register */
+#define REG_ADC_RNCR            (0x400AC114U) /**< \brief (ADC) Receive Next Counter Register */
+#define REG_ADC_TNPR            (0x400AC118U) /**< \brief (ADC) Transmit Next Pointer Register */
+#define REG_ADC_TNCR            (0x400AC11CU) /**< \brief (ADC) Transmit Next Counter Register */
+#define REG_ADC_PTCR            (0x400AC120U) /**< \brief (ADC) Transfer Control Register */
+#define REG_ADC_PTSR            (0x400AC124U) /**< \brief (ADC) Transfer Status Register */
+#else
+#define REG_ADC_CR     (*(WoReg*)0x400AC000U) /**< \brief (ADC) Control Register */
+#define REG_ADC_MR     (*(RwReg*)0x400AC004U) /**< \brief (ADC) Mode Register */
+#define REG_ADC_CHER   (*(WoReg*)0x400AC010U) /**< \brief (ADC) Channel Enable Register */
+#define REG_ADC_CHDR   (*(WoReg*)0x400AC014U) /**< \brief (ADC) Channel Disable Register */
+#define REG_ADC_CHSR   (*(RoReg*)0x400AC018U) /**< \brief (ADC) Channel Status Register */
+#define REG_ADC_SR     (*(RoReg*)0x400AC01CU) /**< \brief (ADC) Status Register */
+#define REG_ADC_LCDR   (*(RoReg*)0x400AC020U) /**< \brief (ADC) Last Converted Data Register */
+#define REG_ADC_IER    (*(WoReg*)0x400AC024U) /**< \brief (ADC) Interrupt Enable Register */
+#define REG_ADC_IDR    (*(WoReg*)0x400AC028U) /**< \brief (ADC) Interrupt Disable Register */
+#define REG_ADC_IMR    (*(RoReg*)0x400AC02CU) /**< \brief (ADC) Interrupt Mask Register */
+#define REG_ADC_CDR    (*(RoReg*)0x400AC030U) /**< \brief (ADC) Channel Data Register */
+#define REG_ADC_RPR    (*(RwReg*)0x400AC100U) /**< \brief (ADC) Receive Pointer Register */
+#define REG_ADC_RCR    (*(RwReg*)0x400AC104U) /**< \brief (ADC) Receive Counter Register */
+#define REG_ADC_TPR    (*(RwReg*)0x400AC108U) /**< \brief (ADC) Transmit Pointer Register */
+#define REG_ADC_TCR    (*(RwReg*)0x400AC10CU) /**< \brief (ADC) Transmit Counter Register */
+#define REG_ADC_RNPR   (*(RwReg*)0x400AC110U) /**< \brief (ADC) Receive Next Pointer Register */
+#define REG_ADC_RNCR   (*(RwReg*)0x400AC114U) /**< \brief (ADC) Receive Next Counter Register */
+#define REG_ADC_TNPR   (*(RwReg*)0x400AC118U) /**< \brief (ADC) Transmit Next Pointer Register */
+#define REG_ADC_TNCR   (*(RwReg*)0x400AC11CU) /**< \brief (ADC) Transmit Next Counter Register */
+#define REG_ADC_PTCR   (*(WoReg*)0x400AC120U) /**< \brief (ADC) Transfer Control Register */
+#define REG_ADC_PTSR   (*(RoReg*)0x400AC124U) /**< \brief (ADC) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_ADC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_adc12b.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_adc12b.h
new file mode 100644
index 000000000..985799389
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_adc12b.h
@@ -0,0 +1,84 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_ADC12B_INSTANCE_
+#define _SAM3U_ADC12B_INSTANCE_
+
+/* ========== Register definition for ADC12B peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_ADC12B_CR              (0x400A8000U) /**< \brief (ADC12B) Control Register */
+#define REG_ADC12B_MR              (0x400A8004U) /**< \brief (ADC12B) Mode Register */
+#define REG_ADC12B_CHER            (0x400A8010U) /**< \brief (ADC12B) Channel Enable Register */
+#define REG_ADC12B_CHDR            (0x400A8014U) /**< \brief (ADC12B) Channel Disable Register */
+#define REG_ADC12B_CHSR            (0x400A8018U) /**< \brief (ADC12B) Channel Status Register */
+#define REG_ADC12B_SR              (0x400A801CU) /**< \brief (ADC12B) Status Register */
+#define REG_ADC12B_LCDR            (0x400A8020U) /**< \brief (ADC12B) Last Converted Data Register */
+#define REG_ADC12B_IER             (0x400A8024U) /**< \brief (ADC12B) Interrupt Enable Register */
+#define REG_ADC12B_IDR             (0x400A8028U) /**< \brief (ADC12B) Interrupt Disable Register */
+#define REG_ADC12B_IMR             (0x400A802CU) /**< \brief (ADC12B) Interrupt Mask Register */
+#define REG_ADC12B_CDR             (0x400A8030U) /**< \brief (ADC12B) Channel Data Register */
+#define REG_ADC12B_ACR             (0x400A8064U) /**< \brief (ADC12B) Analog Control Register */
+#define REG_ADC12B_EMR             (0x400A8068U) /**< \brief (ADC12B) Extended Mode Register */
+#define REG_ADC12B_RPR             (0x400A8100U) /**< \brief (ADC12B) Receive Pointer Register */
+#define REG_ADC12B_RCR             (0x400A8104U) /**< \brief (ADC12B) Receive Counter Register */
+#define REG_ADC12B_TPR             (0x400A8108U) /**< \brief (ADC12B) Transmit Pointer Register */
+#define REG_ADC12B_TCR             (0x400A810CU) /**< \brief (ADC12B) Transmit Counter Register */
+#define REG_ADC12B_RNPR            (0x400A8110U) /**< \brief (ADC12B) Receive Next Pointer Register */
+#define REG_ADC12B_RNCR            (0x400A8114U) /**< \brief (ADC12B) Receive Next Counter Register */
+#define REG_ADC12B_TNPR            (0x400A8118U) /**< \brief (ADC12B) Transmit Next Pointer Register */
+#define REG_ADC12B_TNCR            (0x400A811CU) /**< \brief (ADC12B) Transmit Next Counter Register */
+#define REG_ADC12B_PTCR            (0x400A8120U) /**< \brief (ADC12B) Transfer Control Register */
+#define REG_ADC12B_PTSR            (0x400A8124U) /**< \brief (ADC12B) Transfer Status Register */
+#else
+#define REG_ADC12B_CR     (*(WoReg*)0x400A8000U) /**< \brief (ADC12B) Control Register */
+#define REG_ADC12B_MR     (*(RwReg*)0x400A8004U) /**< \brief (ADC12B) Mode Register */
+#define REG_ADC12B_CHER   (*(WoReg*)0x400A8010U) /**< \brief (ADC12B) Channel Enable Register */
+#define REG_ADC12B_CHDR   (*(WoReg*)0x400A8014U) /**< \brief (ADC12B) Channel Disable Register */
+#define REG_ADC12B_CHSR   (*(RoReg*)0x400A8018U) /**< \brief (ADC12B) Channel Status Register */
+#define REG_ADC12B_SR     (*(RoReg*)0x400A801CU) /**< \brief (ADC12B) Status Register */
+#define REG_ADC12B_LCDR   (*(RoReg*)0x400A8020U) /**< \brief (ADC12B) Last Converted Data Register */
+#define REG_ADC12B_IER    (*(WoReg*)0x400A8024U) /**< \brief (ADC12B) Interrupt Enable Register */
+#define REG_ADC12B_IDR    (*(WoReg*)0x400A8028U) /**< \brief (ADC12B) Interrupt Disable Register */
+#define REG_ADC12B_IMR    (*(RoReg*)0x400A802CU) /**< \brief (ADC12B) Interrupt Mask Register */
+#define REG_ADC12B_CDR    (*(RoReg*)0x400A8030U) /**< \brief (ADC12B) Channel Data Register */
+#define REG_ADC12B_ACR    (*(RwReg*)0x400A8064U) /**< \brief (ADC12B) Analog Control Register */
+#define REG_ADC12B_EMR    (*(RwReg*)0x400A8068U) /**< \brief (ADC12B) Extended Mode Register */
+#define REG_ADC12B_RPR    (*(RwReg*)0x400A8100U) /**< \brief (ADC12B) Receive Pointer Register */
+#define REG_ADC12B_RCR    (*(RwReg*)0x400A8104U) /**< \brief (ADC12B) Receive Counter Register */
+#define REG_ADC12B_TPR    (*(RwReg*)0x400A8108U) /**< \brief (ADC12B) Transmit Pointer Register */
+#define REG_ADC12B_TCR    (*(RwReg*)0x400A810CU) /**< \brief (ADC12B) Transmit Counter Register */
+#define REG_ADC12B_RNPR   (*(RwReg*)0x400A8110U) /**< \brief (ADC12B) Receive Next Pointer Register */
+#define REG_ADC12B_RNCR   (*(RwReg*)0x400A8114U) /**< \brief (ADC12B) Receive Next Counter Register */
+#define REG_ADC12B_TNPR   (*(RwReg*)0x400A8118U) /**< \brief (ADC12B) Transmit Next Pointer Register */
+#define REG_ADC12B_TNCR   (*(RwReg*)0x400A811CU) /**< \brief (ADC12B) Transmit Next Counter Register */
+#define REG_ADC12B_PTCR   (*(WoReg*)0x400A8120U) /**< \brief (ADC12B) Transfer Control Register */
+#define REG_ADC12B_PTSR   (*(RoReg*)0x400A8124U) /**< \brief (ADC12B) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_ADC12B_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_chipid.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_chipid.h
new file mode 100644
index 000000000..0e26b27fd
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_chipid.h
@@ -0,0 +1,42 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_CHIPID_INSTANCE_
+#define _SAM3U_CHIPID_INSTANCE_
+
+/* ========== Register definition for CHIPID peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_CHIPID_CIDR          (0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
+#define REG_CHIPID_EXID          (0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
+#else
+#define REG_CHIPID_CIDR (*(RoReg*)0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
+#define REG_CHIPID_EXID (*(RoReg*)0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_CHIPID_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_dmac.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_dmac.h
new file mode 100644
index 000000000..76972f519
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_dmac.h
@@ -0,0 +1,110 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_DMAC_INSTANCE_
+#define _SAM3U_DMAC_INSTANCE_
+
+/* ========== Register definition for DMAC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_DMAC_GCFG            (0x400B0000U) /**< \brief (DMAC) DMAC Global Configuration Register */
+#define REG_DMAC_EN              (0x400B0004U) /**< \brief (DMAC) DMAC Enable Register */
+#define REG_DMAC_SREQ            (0x400B0008U) /**< \brief (DMAC) DMAC Software Single Request Register */
+#define REG_DMAC_CREQ            (0x400B000CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */
+#define REG_DMAC_LAST            (0x400B0010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */
+#define REG_DMAC_EBCIER          (0x400B0018U) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register. */
+#define REG_DMAC_EBCIDR          (0x400B001CU) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register. */
+#define REG_DMAC_EBCIMR          (0x400B0020U) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register. */
+#define REG_DMAC_EBCISR          (0x400B0024U) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Status Register. */
+#define REG_DMAC_CHER            (0x400B0028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */
+#define REG_DMAC_CHDR            (0x400B002CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */
+#define REG_DMAC_CHSR            (0x400B0030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */
+#define REG_DMAC_SADDR0          (0x400B003CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */
+#define REG_DMAC_DADDR0          (0x400B0040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */
+#define REG_DMAC_DSCR0           (0x400B0044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */
+#define REG_DMAC_CTRLA0          (0x400B0048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */
+#define REG_DMAC_CTRLB0          (0x400B004CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */
+#define REG_DMAC_CFG0            (0x400B0050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */
+#define REG_DMAC_SADDR1          (0x400B0064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */
+#define REG_DMAC_DADDR1          (0x400B0068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */
+#define REG_DMAC_DSCR1           (0x400B006CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */
+#define REG_DMAC_CTRLA1          (0x400B0070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */
+#define REG_DMAC_CTRLB1          (0x400B0074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */
+#define REG_DMAC_CFG1            (0x400B0078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */
+#define REG_DMAC_SADDR2          (0x400B008CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */
+#define REG_DMAC_DADDR2          (0x400B0090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */
+#define REG_DMAC_DSCR2           (0x400B0094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */
+#define REG_DMAC_CTRLA2          (0x400B0098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */
+#define REG_DMAC_CTRLB2          (0x400B009CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */
+#define REG_DMAC_CFG2            (0x400B00A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */
+#define REG_DMAC_SADDR3          (0x400B00B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */
+#define REG_DMAC_DADDR3          (0x400B00B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */
+#define REG_DMAC_DSCR3           (0x400B00BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */
+#define REG_DMAC_CTRLA3          (0x400B00C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */
+#define REG_DMAC_CTRLB3          (0x400B00C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */
+#define REG_DMAC_CFG3            (0x400B00C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */
+#else
+#define REG_DMAC_GCFG   (*(RwReg*)0x400B0000U) /**< \brief (DMAC) DMAC Global Configuration Register */
+#define REG_DMAC_EN     (*(RwReg*)0x400B0004U) /**< \brief (DMAC) DMAC Enable Register */
+#define REG_DMAC_SREQ   (*(RwReg*)0x400B0008U) /**< \brief (DMAC) DMAC Software Single Request Register */
+#define REG_DMAC_CREQ   (*(RwReg*)0x400B000CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */
+#define REG_DMAC_LAST   (*(RwReg*)0x400B0010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */
+#define REG_DMAC_EBCIER (*(WoReg*)0x400B0018U) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register. */
+#define REG_DMAC_EBCIDR (*(WoReg*)0x400B001CU) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register. */
+#define REG_DMAC_EBCIMR (*(RoReg*)0x400B0020U) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register. */
+#define REG_DMAC_EBCISR (*(RoReg*)0x400B0024U) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Status Register. */
+#define REG_DMAC_CHER   (*(WoReg*)0x400B0028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */
+#define REG_DMAC_CHDR   (*(WoReg*)0x400B002CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */
+#define REG_DMAC_CHSR   (*(RoReg*)0x400B0030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */
+#define REG_DMAC_SADDR0 (*(RwReg*)0x400B003CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */
+#define REG_DMAC_DADDR0 (*(RwReg*)0x400B0040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */
+#define REG_DMAC_DSCR0  (*(RwReg*)0x400B0044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */
+#define REG_DMAC_CTRLA0 (*(RwReg*)0x400B0048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */
+#define REG_DMAC_CTRLB0 (*(RwReg*)0x400B004CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */
+#define REG_DMAC_CFG0   (*(RwReg*)0x400B0050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */
+#define REG_DMAC_SADDR1 (*(RwReg*)0x400B0064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */
+#define REG_DMAC_DADDR1 (*(RwReg*)0x400B0068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */
+#define REG_DMAC_DSCR1  (*(RwReg*)0x400B006CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */
+#define REG_DMAC_CTRLA1 (*(RwReg*)0x400B0070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */
+#define REG_DMAC_CTRLB1 (*(RwReg*)0x400B0074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */
+#define REG_DMAC_CFG1   (*(RwReg*)0x400B0078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */
+#define REG_DMAC_SADDR2 (*(RwReg*)0x400B008CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */
+#define REG_DMAC_DADDR2 (*(RwReg*)0x400B0090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */
+#define REG_DMAC_DSCR2  (*(RwReg*)0x400B0094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */
+#define REG_DMAC_CTRLA2 (*(RwReg*)0x400B0098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */
+#define REG_DMAC_CTRLB2 (*(RwReg*)0x400B009CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */
+#define REG_DMAC_CFG2   (*(RwReg*)0x400B00A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */
+#define REG_DMAC_SADDR3 (*(RwReg*)0x400B00B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */
+#define REG_DMAC_DADDR3 (*(RwReg*)0x400B00B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */
+#define REG_DMAC_DSCR3  (*(RwReg*)0x400B00BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */
+#define REG_DMAC_CTRLA3 (*(RwReg*)0x400B00C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */
+#define REG_DMAC_CTRLB3 (*(RwReg*)0x400B00C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */
+#define REG_DMAC_CFG3   (*(RwReg*)0x400B00C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_DMAC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_efc0.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_efc0.h
new file mode 100644
index 000000000..29041cd7b
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_efc0.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_EFC0_INSTANCE_
+#define _SAM3U_EFC0_INSTANCE_
+
+/* ========== Register definition for EFC0 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_EFC0_FMR           (0x400E0800U) /**< \brief (EFC0) EEFC Flash Mode Register */
+#define REG_EFC0_FCR           (0x400E0804U) /**< \brief (EFC0) EEFC Flash Command Register */
+#define REG_EFC0_FSR           (0x400E0808U) /**< \brief (EFC0) EEFC Flash Status Register */
+#define REG_EFC0_FRR           (0x400E080CU) /**< \brief (EFC0) EEFC Flash Result Register */
+#else
+#define REG_EFC0_FMR  (*(RwReg*)0x400E0800U) /**< \brief (EFC0) EEFC Flash Mode Register */
+#define REG_EFC0_FCR  (*(WoReg*)0x400E0804U) /**< \brief (EFC0) EEFC Flash Command Register */
+#define REG_EFC0_FSR  (*(RoReg*)0x400E0808U) /**< \brief (EFC0) EEFC Flash Status Register */
+#define REG_EFC0_FRR  (*(RoReg*)0x400E080CU) /**< \brief (EFC0) EEFC Flash Result Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_EFC0_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_efc1.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_efc1.h
new file mode 100644
index 000000000..11f658759
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_efc1.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_EFC1_INSTANCE_
+#define _SAM3U_EFC1_INSTANCE_
+
+/* ========== Register definition for EFC1 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_EFC1_FMR           (0x400E0A00U) /**< \brief (EFC1) EEFC Flash Mode Register */
+#define REG_EFC1_FCR           (0x400E0A04U) /**< \brief (EFC1) EEFC Flash Command Register */
+#define REG_EFC1_FSR           (0x400E0A08U) /**< \brief (EFC1) EEFC Flash Status Register */
+#define REG_EFC1_FRR           (0x400E0A0CU) /**< \brief (EFC1) EEFC Flash Result Register */
+#else
+#define REG_EFC1_FMR  (*(RwReg*)0x400E0A00U) /**< \brief (EFC1) EEFC Flash Mode Register */
+#define REG_EFC1_FCR  (*(WoReg*)0x400E0A04U) /**< \brief (EFC1) EEFC Flash Command Register */
+#define REG_EFC1_FSR  (*(RoReg*)0x400E0A08U) /**< \brief (EFC1) EEFC Flash Status Register */
+#define REG_EFC1_FRR  (*(RoReg*)0x400E0A0CU) /**< \brief (EFC1) EEFC Flash Result Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_EFC1_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_gpbr.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_gpbr.h
new file mode 100644
index 000000000..3558ec9ec
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_gpbr.h
@@ -0,0 +1,40 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_GPBR_INSTANCE_
+#define _SAM3U_GPBR_INSTANCE_
+
+/* ========== Register definition for GPBR peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_GPBR_GPBR            (0x400E1290U) /**< \brief (GPBR) General Purpose Backup Register */
+#else
+#define REG_GPBR_GPBR   (*(RwReg*)0x400E1290U) /**< \brief (GPBR) General Purpose Backup Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_GPBR_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_hsmci.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_hsmci.h
new file mode 100644
index 000000000..a69746c3c
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_hsmci.h
@@ -0,0 +1,78 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_HSMCI_INSTANCE_
+#define _SAM3U_HSMCI_INSTANCE_
+
+/* ========== Register definition for HSMCI peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_HSMCI_CR                 (0x40000000U) /**< \brief (HSMCI) Control Register */
+#define REG_HSMCI_MR                 (0x40000004U) /**< \brief (HSMCI) Mode Register */
+#define REG_HSMCI_DTOR               (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
+#define REG_HSMCI_SDCR               (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
+#define REG_HSMCI_ARGR               (0x40000010U) /**< \brief (HSMCI) Argument Register */
+#define REG_HSMCI_CMDR               (0x40000014U) /**< \brief (HSMCI) Command Register */
+#define REG_HSMCI_BLKR               (0x40000018U) /**< \brief (HSMCI) Block Register */
+#define REG_HSMCI_CSTOR              (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
+#define REG_HSMCI_RSPR               (0x40000020U) /**< \brief (HSMCI) Response Register */
+#define REG_HSMCI_RDR                (0x40000030U) /**< \brief (HSMCI) Receive Data Register */
+#define REG_HSMCI_TDR                (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
+#define REG_HSMCI_SR                 (0x40000040U) /**< \brief (HSMCI) Status Register */
+#define REG_HSMCI_IER                (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
+#define REG_HSMCI_IDR                (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
+#define REG_HSMCI_IMR                (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
+#define REG_HSMCI_DMA                (0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */
+#define REG_HSMCI_CFG                (0x40000054U) /**< \brief (HSMCI) Configuration Register */
+#define REG_HSMCI_WPMR               (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
+#define REG_HSMCI_WPSR               (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
+#define REG_HSMCI_FIFO               (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
+#else
+#define REG_HSMCI_CR        (*(WoReg*)0x40000000U) /**< \brief (HSMCI) Control Register */
+#define REG_HSMCI_MR        (*(RwReg*)0x40000004U) /**< \brief (HSMCI) Mode Register */
+#define REG_HSMCI_DTOR      (*(RwReg*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
+#define REG_HSMCI_SDCR      (*(RwReg*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
+#define REG_HSMCI_ARGR      (*(RwReg*)0x40000010U) /**< \brief (HSMCI) Argument Register */
+#define REG_HSMCI_CMDR      (*(WoReg*)0x40000014U) /**< \brief (HSMCI) Command Register */
+#define REG_HSMCI_BLKR      (*(RwReg*)0x40000018U) /**< \brief (HSMCI) Block Register */
+#define REG_HSMCI_CSTOR     (*(RwReg*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
+#define REG_HSMCI_RSPR      (*(RoReg*)0x40000020U) /**< \brief (HSMCI) Response Register */
+#define REG_HSMCI_RDR       (*(RoReg*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */
+#define REG_HSMCI_TDR       (*(WoReg*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
+#define REG_HSMCI_SR        (*(RoReg*)0x40000040U) /**< \brief (HSMCI) Status Register */
+#define REG_HSMCI_IER       (*(WoReg*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
+#define REG_HSMCI_IDR       (*(WoReg*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
+#define REG_HSMCI_IMR       (*(RoReg*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
+#define REG_HSMCI_DMA       (*(RwReg*)0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */
+#define REG_HSMCI_CFG       (*(RwReg*)0x40000054U) /**< \brief (HSMCI) Configuration Register */
+#define REG_HSMCI_WPMR      (*(RwReg*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
+#define REG_HSMCI_WPSR      (*(RoReg*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
+#define REG_HSMCI_FIFO      (*(RwReg*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_HSMCI_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_matrix.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_matrix.h
new file mode 100644
index 000000000..ed178fed0
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_matrix.h
@@ -0,0 +1,68 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_MATRIX_INSTANCE_
+#define _SAM3U_MATRIX_INSTANCE_
+
+/* ========== Register definition for MATRIX peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_MATRIX_MCFG              (0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
+#define REG_MATRIX_SCFG              (0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
+#define REG_MATRIX_PRAS0             (0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
+#define REG_MATRIX_PRAS1             (0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
+#define REG_MATRIX_PRAS2             (0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
+#define REG_MATRIX_PRAS3             (0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
+#define REG_MATRIX_PRAS4             (0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
+#define REG_MATRIX_PRAS5             (0x400E02A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
+#define REG_MATRIX_PRAS6             (0x400E02B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
+#define REG_MATRIX_PRAS7             (0x400E02B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
+#define REG_MATRIX_PRAS8             (0x400E02C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
+#define REG_MATRIX_PRAS9             (0x400E02C8U) /**< \brief (MATRIX) Priority Register A for Slave 9 */
+#define REG_MATRIX_MRCR              (0x400E0300U) /**< \brief (MATRIX) Master Remap Control Register */
+#define REG_MATRIX_WPMR              (0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
+#define REG_MATRIX_WPSR              (0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
+#else
+#define REG_MATRIX_MCFG     (*(RwReg*)0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
+#define REG_MATRIX_SCFG     (*(RwReg*)0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
+#define REG_MATRIX_PRAS0    (*(RwReg*)0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
+#define REG_MATRIX_PRAS1    (*(RwReg*)0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
+#define REG_MATRIX_PRAS2    (*(RwReg*)0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
+#define REG_MATRIX_PRAS3    (*(RwReg*)0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
+#define REG_MATRIX_PRAS4    (*(RwReg*)0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
+#define REG_MATRIX_PRAS5    (*(RwReg*)0x400E02A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
+#define REG_MATRIX_PRAS6    (*(RwReg*)0x400E02B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
+#define REG_MATRIX_PRAS7    (*(RwReg*)0x400E02B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
+#define REG_MATRIX_PRAS8    (*(RwReg*)0x400E02C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
+#define REG_MATRIX_PRAS9    (*(RwReg*)0x400E02C8U) /**< \brief (MATRIX) Priority Register A for Slave 9 */
+#define REG_MATRIX_MRCR     (*(RwReg*)0x400E0300U) /**< \brief (MATRIX) Master Remap Control Register */
+#define REG_MATRIX_WPMR     (*(RwReg*)0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
+#define REG_MATRIX_WPSR     (*(RoReg*)0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_MATRIX_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_pioa.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_pioa.h
new file mode 100644
index 000000000..3cecfbf82
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_pioa.h
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_PIOA_INSTANCE_
+#define _SAM3U_PIOA_INSTANCE_
+
+/* ========== Register definition for PIOA peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PIOA_PER             (0x400E0C00U) /**< \brief (PIOA) PIO Enable Register */
+#define REG_PIOA_PDR             (0x400E0C04U) /**< \brief (PIOA) PIO Disable Register */
+#define REG_PIOA_PSR             (0x400E0C08U) /**< \brief (PIOA) PIO Status Register */
+#define REG_PIOA_OER             (0x400E0C10U) /**< \brief (PIOA) Output Enable Register */
+#define REG_PIOA_ODR             (0x400E0C14U) /**< \brief (PIOA) Output Disable Register */
+#define REG_PIOA_OSR             (0x400E0C18U) /**< \brief (PIOA) Output Status Register */
+#define REG_PIOA_IFER            (0x400E0C20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
+#define REG_PIOA_IFDR            (0x400E0C24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
+#define REG_PIOA_IFSR            (0x400E0C28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
+#define REG_PIOA_SODR            (0x400E0C30U) /**< \brief (PIOA) Set Output Data Register */
+#define REG_PIOA_CODR            (0x400E0C34U) /**< \brief (PIOA) Clear Output Data Register */
+#define REG_PIOA_ODSR            (0x400E0C38U) /**< \brief (PIOA) Output Data Status Register */
+#define REG_PIOA_PDSR            (0x400E0C3CU) /**< \brief (PIOA) Pin Data Status Register */
+#define REG_PIOA_IER             (0x400E0C40U) /**< \brief (PIOA) Interrupt Enable Register */
+#define REG_PIOA_IDR             (0x400E0C44U) /**< \brief (PIOA) Interrupt Disable Register */
+#define REG_PIOA_IMR             (0x400E0C48U) /**< \brief (PIOA) Interrupt Mask Register */
+#define REG_PIOA_ISR             (0x400E0C4CU) /**< \brief (PIOA) Interrupt Status Register */
+#define REG_PIOA_MDER            (0x400E0C50U) /**< \brief (PIOA) Multi-driver Enable Register */
+#define REG_PIOA_MDDR            (0x400E0C54U) /**< \brief (PIOA) Multi-driver Disable Register */
+#define REG_PIOA_MDSR            (0x400E0C58U) /**< \brief (PIOA) Multi-driver Status Register */
+#define REG_PIOA_PUDR            (0x400E0C60U) /**< \brief (PIOA) Pull-up Disable Register */
+#define REG_PIOA_PUER            (0x400E0C64U) /**< \brief (PIOA) Pull-up Enable Register */
+#define REG_PIOA_PUSR            (0x400E0C68U) /**< \brief (PIOA) Pad Pull-up Status Register */
+#define REG_PIOA_ABSR            (0x400E0C70U) /**< \brief (PIOA) Peripheral AB Select Register */
+#define REG_PIOA_SCIFSR          (0x400E0C80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */
+#define REG_PIOA_DIFSR           (0x400E0C84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */
+#define REG_PIOA_IFDGSR          (0x400E0C88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOA_SCDR            (0x400E0C8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
+#define REG_PIOA_OWER            (0x400E0CA0U) /**< \brief (PIOA) Output Write Enable */
+#define REG_PIOA_OWDR            (0x400E0CA4U) /**< \brief (PIOA) Output Write Disable */
+#define REG_PIOA_OWSR            (0x400E0CA8U) /**< \brief (PIOA) Output Write Status Register */
+#define REG_PIOA_AIMER           (0x400E0CB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
+#define REG_PIOA_AIMDR           (0x400E0CB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
+#define REG_PIOA_AIMMR           (0x400E0CB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
+#define REG_PIOA_ESR             (0x400E0CC0U) /**< \brief (PIOA) Edge Select Register */
+#define REG_PIOA_LSR             (0x400E0CC4U) /**< \brief (PIOA) Level Select Register */
+#define REG_PIOA_ELSR            (0x400E0CC8U) /**< \brief (PIOA) Edge/Level Status Register */
+#define REG_PIOA_FELLSR          (0x400E0CD0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
+#define REG_PIOA_REHLSR          (0x400E0CD4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
+#define REG_PIOA_FRLHSR          (0x400E0CD8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
+#define REG_PIOA_LOCKSR          (0x400E0CE0U) /**< \brief (PIOA) Lock Status */
+#define REG_PIOA_WPMR            (0x400E0CE4U) /**< \brief (PIOA) Write Protect Mode Register */
+#define REG_PIOA_WPSR            (0x400E0CE8U) /**< \brief (PIOA) Write Protect Status Register */
+#else
+#define REG_PIOA_PER    (*(WoReg*)0x400E0C00U) /**< \brief (PIOA) PIO Enable Register */
+#define REG_PIOA_PDR    (*(WoReg*)0x400E0C04U) /**< \brief (PIOA) PIO Disable Register */
+#define REG_PIOA_PSR    (*(RoReg*)0x400E0C08U) /**< \brief (PIOA) PIO Status Register */
+#define REG_PIOA_OER    (*(WoReg*)0x400E0C10U) /**< \brief (PIOA) Output Enable Register */
+#define REG_PIOA_ODR    (*(WoReg*)0x400E0C14U) /**< \brief (PIOA) Output Disable Register */
+#define REG_PIOA_OSR    (*(RoReg*)0x400E0C18U) /**< \brief (PIOA) Output Status Register */
+#define REG_PIOA_IFER   (*(WoReg*)0x400E0C20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
+#define REG_PIOA_IFDR   (*(WoReg*)0x400E0C24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
+#define REG_PIOA_IFSR   (*(RoReg*)0x400E0C28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
+#define REG_PIOA_SODR   (*(WoReg*)0x400E0C30U) /**< \brief (PIOA) Set Output Data Register */
+#define REG_PIOA_CODR   (*(WoReg*)0x400E0C34U) /**< \brief (PIOA) Clear Output Data Register */
+#define REG_PIOA_ODSR   (*(RwReg*)0x400E0C38U) /**< \brief (PIOA) Output Data Status Register */
+#define REG_PIOA_PDSR   (*(RoReg*)0x400E0C3CU) /**< \brief (PIOA) Pin Data Status Register */
+#define REG_PIOA_IER    (*(WoReg*)0x400E0C40U) /**< \brief (PIOA) Interrupt Enable Register */
+#define REG_PIOA_IDR    (*(WoReg*)0x400E0C44U) /**< \brief (PIOA) Interrupt Disable Register */
+#define REG_PIOA_IMR    (*(RoReg*)0x400E0C48U) /**< \brief (PIOA) Interrupt Mask Register */
+#define REG_PIOA_ISR    (*(RoReg*)0x400E0C4CU) /**< \brief (PIOA) Interrupt Status Register */
+#define REG_PIOA_MDER   (*(WoReg*)0x400E0C50U) /**< \brief (PIOA) Multi-driver Enable Register */
+#define REG_PIOA_MDDR   (*(WoReg*)0x400E0C54U) /**< \brief (PIOA) Multi-driver Disable Register */
+#define REG_PIOA_MDSR   (*(RoReg*)0x400E0C58U) /**< \brief (PIOA) Multi-driver Status Register */
+#define REG_PIOA_PUDR   (*(WoReg*)0x400E0C60U) /**< \brief (PIOA) Pull-up Disable Register */
+#define REG_PIOA_PUER   (*(WoReg*)0x400E0C64U) /**< \brief (PIOA) Pull-up Enable Register */
+#define REG_PIOA_PUSR   (*(RoReg*)0x400E0C68U) /**< \brief (PIOA) Pad Pull-up Status Register */
+#define REG_PIOA_ABSR   (*(RwReg*)0x400E0C70U) /**< \brief (PIOA) Peripheral AB Select Register */
+#define REG_PIOA_SCIFSR (*(WoReg*)0x400E0C80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */
+#define REG_PIOA_DIFSR  (*(WoReg*)0x400E0C84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */
+#define REG_PIOA_IFDGSR (*(RoReg*)0x400E0C88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOA_SCDR   (*(RwReg*)0x400E0C8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
+#define REG_PIOA_OWER   (*(WoReg*)0x400E0CA0U) /**< \brief (PIOA) Output Write Enable */
+#define REG_PIOA_OWDR   (*(WoReg*)0x400E0CA4U) /**< \brief (PIOA) Output Write Disable */
+#define REG_PIOA_OWSR   (*(RoReg*)0x400E0CA8U) /**< \brief (PIOA) Output Write Status Register */
+#define REG_PIOA_AIMER  (*(WoReg*)0x400E0CB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
+#define REG_PIOA_AIMDR  (*(WoReg*)0x400E0CB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
+#define REG_PIOA_AIMMR  (*(RoReg*)0x400E0CB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
+#define REG_PIOA_ESR    (*(WoReg*)0x400E0CC0U) /**< \brief (PIOA) Edge Select Register */
+#define REG_PIOA_LSR    (*(WoReg*)0x400E0CC4U) /**< \brief (PIOA) Level Select Register */
+#define REG_PIOA_ELSR   (*(RoReg*)0x400E0CC8U) /**< \brief (PIOA) Edge/Level Status Register */
+#define REG_PIOA_FELLSR (*(WoReg*)0x400E0CD0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
+#define REG_PIOA_REHLSR (*(WoReg*)0x400E0CD4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
+#define REG_PIOA_FRLHSR (*(RoReg*)0x400E0CD8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
+#define REG_PIOA_LOCKSR (*(RoReg*)0x400E0CE0U) /**< \brief (PIOA) Lock Status */
+#define REG_PIOA_WPMR   (*(RwReg*)0x400E0CE4U) /**< \brief (PIOA) Write Protect Mode Register */
+#define REG_PIOA_WPSR   (*(RoReg*)0x400E0CE8U) /**< \brief (PIOA) Write Protect Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_PIOA_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_piob.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_piob.h
new file mode 100644
index 000000000..a0ad5631b
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_piob.h
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_PIOB_INSTANCE_
+#define _SAM3U_PIOB_INSTANCE_
+
+/* ========== Register definition for PIOB peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PIOB_PER             (0x400E0E00U) /**< \brief (PIOB) PIO Enable Register */
+#define REG_PIOB_PDR             (0x400E0E04U) /**< \brief (PIOB) PIO Disable Register */
+#define REG_PIOB_PSR             (0x400E0E08U) /**< \brief (PIOB) PIO Status Register */
+#define REG_PIOB_OER             (0x400E0E10U) /**< \brief (PIOB) Output Enable Register */
+#define REG_PIOB_ODR             (0x400E0E14U) /**< \brief (PIOB) Output Disable Register */
+#define REG_PIOB_OSR             (0x400E0E18U) /**< \brief (PIOB) Output Status Register */
+#define REG_PIOB_IFER            (0x400E0E20U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
+#define REG_PIOB_IFDR            (0x400E0E24U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
+#define REG_PIOB_IFSR            (0x400E0E28U) /**< \brief (PIOB) Glitch Input Filter Status Register */
+#define REG_PIOB_SODR            (0x400E0E30U) /**< \brief (PIOB) Set Output Data Register */
+#define REG_PIOB_CODR            (0x400E0E34U) /**< \brief (PIOB) Clear Output Data Register */
+#define REG_PIOB_ODSR            (0x400E0E38U) /**< \brief (PIOB) Output Data Status Register */
+#define REG_PIOB_PDSR            (0x400E0E3CU) /**< \brief (PIOB) Pin Data Status Register */
+#define REG_PIOB_IER             (0x400E0E40U) /**< \brief (PIOB) Interrupt Enable Register */
+#define REG_PIOB_IDR             (0x400E0E44U) /**< \brief (PIOB) Interrupt Disable Register */
+#define REG_PIOB_IMR             (0x400E0E48U) /**< \brief (PIOB) Interrupt Mask Register */
+#define REG_PIOB_ISR             (0x400E0E4CU) /**< \brief (PIOB) Interrupt Status Register */
+#define REG_PIOB_MDER            (0x400E0E50U) /**< \brief (PIOB) Multi-driver Enable Register */
+#define REG_PIOB_MDDR            (0x400E0E54U) /**< \brief (PIOB) Multi-driver Disable Register */
+#define REG_PIOB_MDSR            (0x400E0E58U) /**< \brief (PIOB) Multi-driver Status Register */
+#define REG_PIOB_PUDR            (0x400E0E60U) /**< \brief (PIOB) Pull-up Disable Register */
+#define REG_PIOB_PUER            (0x400E0E64U) /**< \brief (PIOB) Pull-up Enable Register */
+#define REG_PIOB_PUSR            (0x400E0E68U) /**< \brief (PIOB) Pad Pull-up Status Register */
+#define REG_PIOB_ABSR            (0x400E0E70U) /**< \brief (PIOB) Peripheral AB Select Register */
+#define REG_PIOB_SCIFSR          (0x400E0E80U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */
+#define REG_PIOB_DIFSR           (0x400E0E84U) /**< \brief (PIOB) Debouncing Input Filter Select Register */
+#define REG_PIOB_IFDGSR          (0x400E0E88U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOB_SCDR            (0x400E0E8CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
+#define REG_PIOB_OWER            (0x400E0EA0U) /**< \brief (PIOB) Output Write Enable */
+#define REG_PIOB_OWDR            (0x400E0EA4U) /**< \brief (PIOB) Output Write Disable */
+#define REG_PIOB_OWSR            (0x400E0EA8U) /**< \brief (PIOB) Output Write Status Register */
+#define REG_PIOB_AIMER           (0x400E0EB0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
+#define REG_PIOB_AIMDR           (0x400E0EB4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
+#define REG_PIOB_AIMMR           (0x400E0EB8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
+#define REG_PIOB_ESR             (0x400E0EC0U) /**< \brief (PIOB) Edge Select Register */
+#define REG_PIOB_LSR             (0x400E0EC4U) /**< \brief (PIOB) Level Select Register */
+#define REG_PIOB_ELSR            (0x400E0EC8U) /**< \brief (PIOB) Edge/Level Status Register */
+#define REG_PIOB_FELLSR          (0x400E0ED0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
+#define REG_PIOB_REHLSR          (0x400E0ED4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
+#define REG_PIOB_FRLHSR          (0x400E0ED8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
+#define REG_PIOB_LOCKSR          (0x400E0EE0U) /**< \brief (PIOB) Lock Status */
+#define REG_PIOB_WPMR            (0x400E0EE4U) /**< \brief (PIOB) Write Protect Mode Register */
+#define REG_PIOB_WPSR            (0x400E0EE8U) /**< \brief (PIOB) Write Protect Status Register */
+#else
+#define REG_PIOB_PER    (*(WoReg*)0x400E0E00U) /**< \brief (PIOB) PIO Enable Register */
+#define REG_PIOB_PDR    (*(WoReg*)0x400E0E04U) /**< \brief (PIOB) PIO Disable Register */
+#define REG_PIOB_PSR    (*(RoReg*)0x400E0E08U) /**< \brief (PIOB) PIO Status Register */
+#define REG_PIOB_OER    (*(WoReg*)0x400E0E10U) /**< \brief (PIOB) Output Enable Register */
+#define REG_PIOB_ODR    (*(WoReg*)0x400E0E14U) /**< \brief (PIOB) Output Disable Register */
+#define REG_PIOB_OSR    (*(RoReg*)0x400E0E18U) /**< \brief (PIOB) Output Status Register */
+#define REG_PIOB_IFER   (*(WoReg*)0x400E0E20U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
+#define REG_PIOB_IFDR   (*(WoReg*)0x400E0E24U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
+#define REG_PIOB_IFSR   (*(RoReg*)0x400E0E28U) /**< \brief (PIOB) Glitch Input Filter Status Register */
+#define REG_PIOB_SODR   (*(WoReg*)0x400E0E30U) /**< \brief (PIOB) Set Output Data Register */
+#define REG_PIOB_CODR   (*(WoReg*)0x400E0E34U) /**< \brief (PIOB) Clear Output Data Register */
+#define REG_PIOB_ODSR   (*(RwReg*)0x400E0E38U) /**< \brief (PIOB) Output Data Status Register */
+#define REG_PIOB_PDSR   (*(RoReg*)0x400E0E3CU) /**< \brief (PIOB) Pin Data Status Register */
+#define REG_PIOB_IER    (*(WoReg*)0x400E0E40U) /**< \brief (PIOB) Interrupt Enable Register */
+#define REG_PIOB_IDR    (*(WoReg*)0x400E0E44U) /**< \brief (PIOB) Interrupt Disable Register */
+#define REG_PIOB_IMR    (*(RoReg*)0x400E0E48U) /**< \brief (PIOB) Interrupt Mask Register */
+#define REG_PIOB_ISR    (*(RoReg*)0x400E0E4CU) /**< \brief (PIOB) Interrupt Status Register */
+#define REG_PIOB_MDER   (*(WoReg*)0x400E0E50U) /**< \brief (PIOB) Multi-driver Enable Register */
+#define REG_PIOB_MDDR   (*(WoReg*)0x400E0E54U) /**< \brief (PIOB) Multi-driver Disable Register */
+#define REG_PIOB_MDSR   (*(RoReg*)0x400E0E58U) /**< \brief (PIOB) Multi-driver Status Register */
+#define REG_PIOB_PUDR   (*(WoReg*)0x400E0E60U) /**< \brief (PIOB) Pull-up Disable Register */
+#define REG_PIOB_PUER   (*(WoReg*)0x400E0E64U) /**< \brief (PIOB) Pull-up Enable Register */
+#define REG_PIOB_PUSR   (*(RoReg*)0x400E0E68U) /**< \brief (PIOB) Pad Pull-up Status Register */
+#define REG_PIOB_ABSR   (*(RwReg*)0x400E0E70U) /**< \brief (PIOB) Peripheral AB Select Register */
+#define REG_PIOB_SCIFSR (*(WoReg*)0x400E0E80U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */
+#define REG_PIOB_DIFSR  (*(WoReg*)0x400E0E84U) /**< \brief (PIOB) Debouncing Input Filter Select Register */
+#define REG_PIOB_IFDGSR (*(RoReg*)0x400E0E88U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOB_SCDR   (*(RwReg*)0x400E0E8CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
+#define REG_PIOB_OWER   (*(WoReg*)0x400E0EA0U) /**< \brief (PIOB) Output Write Enable */
+#define REG_PIOB_OWDR   (*(WoReg*)0x400E0EA4U) /**< \brief (PIOB) Output Write Disable */
+#define REG_PIOB_OWSR   (*(RoReg*)0x400E0EA8U) /**< \brief (PIOB) Output Write Status Register */
+#define REG_PIOB_AIMER  (*(WoReg*)0x400E0EB0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
+#define REG_PIOB_AIMDR  (*(WoReg*)0x400E0EB4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
+#define REG_PIOB_AIMMR  (*(RoReg*)0x400E0EB8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
+#define REG_PIOB_ESR    (*(WoReg*)0x400E0EC0U) /**< \brief (PIOB) Edge Select Register */
+#define REG_PIOB_LSR    (*(WoReg*)0x400E0EC4U) /**< \brief (PIOB) Level Select Register */
+#define REG_PIOB_ELSR   (*(RoReg*)0x400E0EC8U) /**< \brief (PIOB) Edge/Level Status Register */
+#define REG_PIOB_FELLSR (*(WoReg*)0x400E0ED0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
+#define REG_PIOB_REHLSR (*(WoReg*)0x400E0ED4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
+#define REG_PIOB_FRLHSR (*(RoReg*)0x400E0ED8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
+#define REG_PIOB_LOCKSR (*(RoReg*)0x400E0EE0U) /**< \brief (PIOB) Lock Status */
+#define REG_PIOB_WPMR   (*(RwReg*)0x400E0EE4U) /**< \brief (PIOB) Write Protect Mode Register */
+#define REG_PIOB_WPSR   (*(RoReg*)0x400E0EE8U) /**< \brief (PIOB) Write Protect Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_PIOB_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_pioc.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_pioc.h
new file mode 100644
index 000000000..f746e2c23
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_pioc.h
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_PIOC_INSTANCE_
+#define _SAM3U_PIOC_INSTANCE_
+
+/* ========== Register definition for PIOC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PIOC_PER             (0x400E1000U) /**< \brief (PIOC) PIO Enable Register */
+#define REG_PIOC_PDR             (0x400E1004U) /**< \brief (PIOC) PIO Disable Register */
+#define REG_PIOC_PSR             (0x400E1008U) /**< \brief (PIOC) PIO Status Register */
+#define REG_PIOC_OER             (0x400E1010U) /**< \brief (PIOC) Output Enable Register */
+#define REG_PIOC_ODR             (0x400E1014U) /**< \brief (PIOC) Output Disable Register */
+#define REG_PIOC_OSR             (0x400E1018U) /**< \brief (PIOC) Output Status Register */
+#define REG_PIOC_IFER            (0x400E1020U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
+#define REG_PIOC_IFDR            (0x400E1024U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
+#define REG_PIOC_IFSR            (0x400E1028U) /**< \brief (PIOC) Glitch Input Filter Status Register */
+#define REG_PIOC_SODR            (0x400E1030U) /**< \brief (PIOC) Set Output Data Register */
+#define REG_PIOC_CODR            (0x400E1034U) /**< \brief (PIOC) Clear Output Data Register */
+#define REG_PIOC_ODSR            (0x400E1038U) /**< \brief (PIOC) Output Data Status Register */
+#define REG_PIOC_PDSR            (0x400E103CU) /**< \brief (PIOC) Pin Data Status Register */
+#define REG_PIOC_IER             (0x400E1040U) /**< \brief (PIOC) Interrupt Enable Register */
+#define REG_PIOC_IDR             (0x400E1044U) /**< \brief (PIOC) Interrupt Disable Register */
+#define REG_PIOC_IMR             (0x400E1048U) /**< \brief (PIOC) Interrupt Mask Register */
+#define REG_PIOC_ISR             (0x400E104CU) /**< \brief (PIOC) Interrupt Status Register */
+#define REG_PIOC_MDER            (0x400E1050U) /**< \brief (PIOC) Multi-driver Enable Register */
+#define REG_PIOC_MDDR            (0x400E1054U) /**< \brief (PIOC) Multi-driver Disable Register */
+#define REG_PIOC_MDSR            (0x400E1058U) /**< \brief (PIOC) Multi-driver Status Register */
+#define REG_PIOC_PUDR            (0x400E1060U) /**< \brief (PIOC) Pull-up Disable Register */
+#define REG_PIOC_PUER            (0x400E1064U) /**< \brief (PIOC) Pull-up Enable Register */
+#define REG_PIOC_PUSR            (0x400E1068U) /**< \brief (PIOC) Pad Pull-up Status Register */
+#define REG_PIOC_ABSR            (0x400E1070U) /**< \brief (PIOC) Peripheral AB Select Register */
+#define REG_PIOC_SCIFSR          (0x400E1080U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */
+#define REG_PIOC_DIFSR           (0x400E1084U) /**< \brief (PIOC) Debouncing Input Filter Select Register */
+#define REG_PIOC_IFDGSR          (0x400E1088U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOC_SCDR            (0x400E108CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
+#define REG_PIOC_OWER            (0x400E10A0U) /**< \brief (PIOC) Output Write Enable */
+#define REG_PIOC_OWDR            (0x400E10A4U) /**< \brief (PIOC) Output Write Disable */
+#define REG_PIOC_OWSR            (0x400E10A8U) /**< \brief (PIOC) Output Write Status Register */
+#define REG_PIOC_AIMER           (0x400E10B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
+#define REG_PIOC_AIMDR           (0x400E10B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
+#define REG_PIOC_AIMMR           (0x400E10B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
+#define REG_PIOC_ESR             (0x400E10C0U) /**< \brief (PIOC) Edge Select Register */
+#define REG_PIOC_LSR             (0x400E10C4U) /**< \brief (PIOC) Level Select Register */
+#define REG_PIOC_ELSR            (0x400E10C8U) /**< \brief (PIOC) Edge/Level Status Register */
+#define REG_PIOC_FELLSR          (0x400E10D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
+#define REG_PIOC_REHLSR          (0x400E10D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
+#define REG_PIOC_FRLHSR          (0x400E10D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
+#define REG_PIOC_LOCKSR          (0x400E10E0U) /**< \brief (PIOC) Lock Status */
+#define REG_PIOC_WPMR            (0x400E10E4U) /**< \brief (PIOC) Write Protect Mode Register */
+#define REG_PIOC_WPSR            (0x400E10E8U) /**< \brief (PIOC) Write Protect Status Register */
+#else
+#define REG_PIOC_PER    (*(WoReg*)0x400E1000U) /**< \brief (PIOC) PIO Enable Register */
+#define REG_PIOC_PDR    (*(WoReg*)0x400E1004U) /**< \brief (PIOC) PIO Disable Register */
+#define REG_PIOC_PSR    (*(RoReg*)0x400E1008U) /**< \brief (PIOC) PIO Status Register */
+#define REG_PIOC_OER    (*(WoReg*)0x400E1010U) /**< \brief (PIOC) Output Enable Register */
+#define REG_PIOC_ODR    (*(WoReg*)0x400E1014U) /**< \brief (PIOC) Output Disable Register */
+#define REG_PIOC_OSR    (*(RoReg*)0x400E1018U) /**< \brief (PIOC) Output Status Register */
+#define REG_PIOC_IFER   (*(WoReg*)0x400E1020U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
+#define REG_PIOC_IFDR   (*(WoReg*)0x400E1024U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
+#define REG_PIOC_IFSR   (*(RoReg*)0x400E1028U) /**< \brief (PIOC) Glitch Input Filter Status Register */
+#define REG_PIOC_SODR   (*(WoReg*)0x400E1030U) /**< \brief (PIOC) Set Output Data Register */
+#define REG_PIOC_CODR   (*(WoReg*)0x400E1034U) /**< \brief (PIOC) Clear Output Data Register */
+#define REG_PIOC_ODSR   (*(RwReg*)0x400E1038U) /**< \brief (PIOC) Output Data Status Register */
+#define REG_PIOC_PDSR   (*(RoReg*)0x400E103CU) /**< \brief (PIOC) Pin Data Status Register */
+#define REG_PIOC_IER    (*(WoReg*)0x400E1040U) /**< \brief (PIOC) Interrupt Enable Register */
+#define REG_PIOC_IDR    (*(WoReg*)0x400E1044U) /**< \brief (PIOC) Interrupt Disable Register */
+#define REG_PIOC_IMR    (*(RoReg*)0x400E1048U) /**< \brief (PIOC) Interrupt Mask Register */
+#define REG_PIOC_ISR    (*(RoReg*)0x400E104CU) /**< \brief (PIOC) Interrupt Status Register */
+#define REG_PIOC_MDER   (*(WoReg*)0x400E1050U) /**< \brief (PIOC) Multi-driver Enable Register */
+#define REG_PIOC_MDDR   (*(WoReg*)0x400E1054U) /**< \brief (PIOC) Multi-driver Disable Register */
+#define REG_PIOC_MDSR   (*(RoReg*)0x400E1058U) /**< \brief (PIOC) Multi-driver Status Register */
+#define REG_PIOC_PUDR   (*(WoReg*)0x400E1060U) /**< \brief (PIOC) Pull-up Disable Register */
+#define REG_PIOC_PUER   (*(WoReg*)0x400E1064U) /**< \brief (PIOC) Pull-up Enable Register */
+#define REG_PIOC_PUSR   (*(RoReg*)0x400E1068U) /**< \brief (PIOC) Pad Pull-up Status Register */
+#define REG_PIOC_ABSR   (*(RwReg*)0x400E1070U) /**< \brief (PIOC) Peripheral AB Select Register */
+#define REG_PIOC_SCIFSR (*(WoReg*)0x400E1080U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */
+#define REG_PIOC_DIFSR  (*(WoReg*)0x400E1084U) /**< \brief (PIOC) Debouncing Input Filter Select Register */
+#define REG_PIOC_IFDGSR (*(RoReg*)0x400E1088U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOC_SCDR   (*(RwReg*)0x400E108CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
+#define REG_PIOC_OWER   (*(WoReg*)0x400E10A0U) /**< \brief (PIOC) Output Write Enable */
+#define REG_PIOC_OWDR   (*(WoReg*)0x400E10A4U) /**< \brief (PIOC) Output Write Disable */
+#define REG_PIOC_OWSR   (*(RoReg*)0x400E10A8U) /**< \brief (PIOC) Output Write Status Register */
+#define REG_PIOC_AIMER  (*(WoReg*)0x400E10B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
+#define REG_PIOC_AIMDR  (*(WoReg*)0x400E10B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
+#define REG_PIOC_AIMMR  (*(RoReg*)0x400E10B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
+#define REG_PIOC_ESR    (*(WoReg*)0x400E10C0U) /**< \brief (PIOC) Edge Select Register */
+#define REG_PIOC_LSR    (*(WoReg*)0x400E10C4U) /**< \brief (PIOC) Level Select Register */
+#define REG_PIOC_ELSR   (*(RoReg*)0x400E10C8U) /**< \brief (PIOC) Edge/Level Status Register */
+#define REG_PIOC_FELLSR (*(WoReg*)0x400E10D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
+#define REG_PIOC_REHLSR (*(WoReg*)0x400E10D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
+#define REG_PIOC_FRLHSR (*(RoReg*)0x400E10D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
+#define REG_PIOC_LOCKSR (*(RoReg*)0x400E10E0U) /**< \brief (PIOC) Lock Status */
+#define REG_PIOC_WPMR   (*(RwReg*)0x400E10E4U) /**< \brief (PIOC) Write Protect Mode Register */
+#define REG_PIOC_WPSR   (*(RoReg*)0x400E10E8U) /**< \brief (PIOC) Write Protect Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_PIOC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_pmc.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_pmc.h
new file mode 100644
index 000000000..da2468b96
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_pmc.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_PMC_INSTANCE_
+#define _SAM3U_PMC_INSTANCE_
+
+/* ========== Register definition for PMC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PMC_SCER            (0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
+#define REG_PMC_SCDR            (0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
+#define REG_PMC_SCSR            (0x400E0408U) /**< \brief (PMC) System Clock Status Register */
+#define REG_PMC_PCER0           (0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
+#define REG_PMC_PCDR0           (0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
+#define REG_PMC_PCSR0           (0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
+#define REG_CKGR_UCKR           (0x400E041CU) /**< \brief (PMC) UTMI Clock Register */
+#define REG_CKGR_MOR            (0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
+#define REG_CKGR_MCFR           (0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
+#define REG_CKGR_PLLAR          (0x400E0428U) /**< \brief (PMC) PLLA Register */
+#define REG_PMC_MCKR            (0x400E0430U) /**< \brief (PMC) Master Clock Register */
+#define REG_PMC_PCK             (0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
+#define REG_PMC_IER             (0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
+#define REG_PMC_IDR             (0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
+#define REG_PMC_SR              (0x400E0468U) /**< \brief (PMC) Status Register */
+#define REG_PMC_IMR             (0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
+#define REG_PMC_FSMR            (0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
+#define REG_PMC_FSPR            (0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
+#define REG_PMC_FOCR            (0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
+#define REG_PMC_WPMR            (0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
+#define REG_PMC_WPSR            (0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
+#else
+#define REG_PMC_SCER   (*(WoReg*)0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
+#define REG_PMC_SCDR   (*(WoReg*)0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
+#define REG_PMC_SCSR   (*(RoReg*)0x400E0408U) /**< \brief (PMC) System Clock Status Register */
+#define REG_PMC_PCER0  (*(WoReg*)0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
+#define REG_PMC_PCDR0  (*(WoReg*)0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
+#define REG_PMC_PCSR0  (*(RoReg*)0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
+#define REG_CKGR_UCKR  (*(RwReg*)0x400E041CU) /**< \brief (PMC) UTMI Clock Register */
+#define REG_CKGR_MOR   (*(RwReg*)0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
+#define REG_CKGR_MCFR  (*(RoReg*)0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
+#define REG_CKGR_PLLAR (*(RwReg*)0x400E0428U) /**< \brief (PMC) PLLA Register */
+#define REG_PMC_MCKR   (*(RwReg*)0x400E0430U) /**< \brief (PMC) Master Clock Register */
+#define REG_PMC_PCK    (*(RwReg*)0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
+#define REG_PMC_IER    (*(WoReg*)0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
+#define REG_PMC_IDR    (*(WoReg*)0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
+#define REG_PMC_SR     (*(RoReg*)0x400E0468U) /**< \brief (PMC) Status Register */
+#define REG_PMC_IMR    (*(RoReg*)0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
+#define REG_PMC_FSMR   (*(RwReg*)0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
+#define REG_PMC_FSPR   (*(RwReg*)0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
+#define REG_PMC_FOCR   (*(WoReg*)0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
+#define REG_PMC_WPMR   (*(RwReg*)0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
+#define REG_PMC_WPSR   (*(RoReg*)0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_PMC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_pwm.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_pwm.h
new file mode 100644
index 000000000..86e4f5778
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_pwm.h
@@ -0,0 +1,246 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_PWM_INSTANCE_
+#define _SAM3U_PWM_INSTANCE_
+
+/* ========== Register definition for PWM peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PWM_CLK               (0x4008C000U) /**< \brief (PWM) PWM Clock Register */
+#define REG_PWM_ENA               (0x4008C004U) /**< \brief (PWM) PWM Enable Register */
+#define REG_PWM_DIS               (0x4008C008U) /**< \brief (PWM) PWM Disable Register */
+#define REG_PWM_SR                (0x4008C00CU) /**< \brief (PWM) PWM Status Register */
+#define REG_PWM_IER1              (0x4008C010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
+#define REG_PWM_IDR1              (0x4008C014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
+#define REG_PWM_IMR1              (0x4008C018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
+#define REG_PWM_ISR1              (0x4008C01CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
+#define REG_PWM_SCM               (0x4008C020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
+#define REG_PWM_SCUC              (0x4008C028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
+#define REG_PWM_SCUP              (0x4008C02CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
+#define REG_PWM_SCUPUPD           (0x4008C030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
+#define REG_PWM_IER2              (0x4008C034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
+#define REG_PWM_IDR2              (0x4008C038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
+#define REG_PWM_IMR2              (0x4008C03CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
+#define REG_PWM_ISR2              (0x4008C040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
+#define REG_PWM_OOV               (0x4008C044U) /**< \brief (PWM) PWM Output Override Value Register */
+#define REG_PWM_OS                (0x4008C048U) /**< \brief (PWM) PWM Output Selection Register */
+#define REG_PWM_OSS               (0x4008C04CU) /**< \brief (PWM) PWM Output Selection Set Register */
+#define REG_PWM_OSC               (0x4008C050U) /**< \brief (PWM) PWM Output Selection Clear Register */
+#define REG_PWM_OSSUPD            (0x4008C054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
+#define REG_PWM_OSCUPD            (0x4008C058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
+#define REG_PWM_FMR               (0x4008C05CU) /**< \brief (PWM) PWM Fault Mode Register */
+#define REG_PWM_FSR               (0x4008C060U) /**< \brief (PWM) PWM Fault Status Register */
+#define REG_PWM_FCR               (0x4008C064U) /**< \brief (PWM) PWM Fault Clear Register */
+#define REG_PWM_FPV               (0x4008C068U) /**< \brief (PWM) PWM Fault Protection Value Register */
+#define REG_PWM_FPE               (0x4008C06CU) /**< \brief (PWM) PWM Fault Protection Enable Register */
+#define REG_PWM_ELMR              (0x4008C07CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
+#define REG_PWM_WPCR              (0x4008C0E4U) /**< \brief (PWM) PWM Write Protect Control Register */
+#define REG_PWM_WPSR              (0x4008C0E8U) /**< \brief (PWM) PWM Write Protect Status Register */
+#define REG_PWM_RPR               (0x4008C100U) /**< \brief (PWM) Receive Pointer Register */
+#define REG_PWM_RCR               (0x4008C104U) /**< \brief (PWM) Receive Counter Register */
+#define REG_PWM_TPR               (0x4008C108U) /**< \brief (PWM) Transmit Pointer Register */
+#define REG_PWM_TCR               (0x4008C10CU) /**< \brief (PWM) Transmit Counter Register */
+#define REG_PWM_RNPR              (0x4008C110U) /**< \brief (PWM) Receive Next Pointer Register */
+#define REG_PWM_RNCR              (0x4008C114U) /**< \brief (PWM) Receive Next Counter Register */
+#define REG_PWM_TNPR              (0x4008C118U) /**< \brief (PWM) Transmit Next Pointer Register */
+#define REG_PWM_TNCR              (0x4008C11CU) /**< \brief (PWM) Transmit Next Counter Register */
+#define REG_PWM_PTCR              (0x4008C120U) /**< \brief (PWM) Transfer Control Register */
+#define REG_PWM_PTSR              (0x4008C124U) /**< \brief (PWM) Transfer Status Register */
+#define REG_PWM_CMPV0             (0x4008C130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
+#define REG_PWM_CMPVUPD0          (0x4008C134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
+#define REG_PWM_CMPM0             (0x4008C138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
+#define REG_PWM_CMPMUPD0          (0x4008C13CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
+#define REG_PWM_CMPV1             (0x4008C140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
+#define REG_PWM_CMPVUPD1          (0x4008C144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
+#define REG_PWM_CMPM1             (0x4008C148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
+#define REG_PWM_CMPMUPD1          (0x4008C14CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
+#define REG_PWM_CMPV2             (0x4008C150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
+#define REG_PWM_CMPVUPD2          (0x4008C154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
+#define REG_PWM_CMPM2             (0x4008C158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
+#define REG_PWM_CMPMUPD2          (0x4008C15CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
+#define REG_PWM_CMPV3             (0x4008C160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
+#define REG_PWM_CMPVUPD3          (0x4008C164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
+#define REG_PWM_CMPM3             (0x4008C168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
+#define REG_PWM_CMPMUPD3          (0x4008C16CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
+#define REG_PWM_CMPV4             (0x4008C170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
+#define REG_PWM_CMPVUPD4          (0x4008C174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
+#define REG_PWM_CMPM4             (0x4008C178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
+#define REG_PWM_CMPMUPD4          (0x4008C17CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
+#define REG_PWM_CMPV5             (0x4008C180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
+#define REG_PWM_CMPVUPD5          (0x4008C184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
+#define REG_PWM_CMPM5             (0x4008C188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
+#define REG_PWM_CMPMUPD5          (0x4008C18CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
+#define REG_PWM_CMPV6             (0x4008C190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
+#define REG_PWM_CMPVUPD6          (0x4008C194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
+#define REG_PWM_CMPM6             (0x4008C198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
+#define REG_PWM_CMPMUPD6          (0x4008C19CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
+#define REG_PWM_CMPV7             (0x4008C1A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
+#define REG_PWM_CMPVUPD7          (0x4008C1A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
+#define REG_PWM_CMPM7             (0x4008C1A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
+#define REG_PWM_CMPMUPD7          (0x4008C1ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
+#define REG_PWM_CMR0              (0x4008C200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
+#define REG_PWM_CDTY0             (0x4008C204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
+#define REG_PWM_CDTYUPD0          (0x4008C208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
+#define REG_PWM_CPRD0             (0x4008C20CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
+#define REG_PWM_CPRDUPD0          (0x4008C210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
+#define REG_PWM_CCNT0             (0x4008C214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
+#define REG_PWM_DT0               (0x4008C218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
+#define REG_PWM_DTUPD0            (0x4008C21CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
+#define REG_PWM_CMR1              (0x4008C220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
+#define REG_PWM_CDTY1             (0x4008C224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
+#define REG_PWM_CDTYUPD1          (0x4008C228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
+#define REG_PWM_CPRD1             (0x4008C22CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
+#define REG_PWM_CPRDUPD1          (0x4008C230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
+#define REG_PWM_CCNT1             (0x4008C234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
+#define REG_PWM_DT1               (0x4008C238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
+#define REG_PWM_DTUPD1            (0x4008C23CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
+#define REG_PWM_CMR2              (0x4008C240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
+#define REG_PWM_CDTY2             (0x4008C244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
+#define REG_PWM_CDTYUPD2          (0x4008C248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
+#define REG_PWM_CPRD2             (0x4008C24CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
+#define REG_PWM_CPRDUPD2          (0x4008C250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
+#define REG_PWM_CCNT2             (0x4008C254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
+#define REG_PWM_DT2               (0x4008C258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
+#define REG_PWM_DTUPD2            (0x4008C25CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
+#define REG_PWM_CMR3              (0x4008C260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
+#define REG_PWM_CDTY3             (0x4008C264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
+#define REG_PWM_CDTYUPD3          (0x4008C268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
+#define REG_PWM_CPRD3             (0x4008C26CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
+#define REG_PWM_CPRDUPD3          (0x4008C270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
+#define REG_PWM_CCNT3             (0x4008C274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
+#define REG_PWM_DT3               (0x4008C278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
+#define REG_PWM_DTUPD3            (0x4008C27CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
+#else
+#define REG_PWM_CLK      (*(RwReg*)0x4008C000U) /**< \brief (PWM) PWM Clock Register */
+#define REG_PWM_ENA      (*(WoReg*)0x4008C004U) /**< \brief (PWM) PWM Enable Register */
+#define REG_PWM_DIS      (*(WoReg*)0x4008C008U) /**< \brief (PWM) PWM Disable Register */
+#define REG_PWM_SR       (*(RoReg*)0x4008C00CU) /**< \brief (PWM) PWM Status Register */
+#define REG_PWM_IER1     (*(WoReg*)0x4008C010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
+#define REG_PWM_IDR1     (*(WoReg*)0x4008C014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
+#define REG_PWM_IMR1     (*(RoReg*)0x4008C018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
+#define REG_PWM_ISR1     (*(RoReg*)0x4008C01CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
+#define REG_PWM_SCM      (*(RwReg*)0x4008C020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
+#define REG_PWM_SCUC     (*(RwReg*)0x4008C028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
+#define REG_PWM_SCUP     (*(RwReg*)0x4008C02CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
+#define REG_PWM_SCUPUPD  (*(WoReg*)0x4008C030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
+#define REG_PWM_IER2     (*(WoReg*)0x4008C034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
+#define REG_PWM_IDR2     (*(WoReg*)0x4008C038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
+#define REG_PWM_IMR2     (*(RoReg*)0x4008C03CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
+#define REG_PWM_ISR2     (*(RoReg*)0x4008C040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
+#define REG_PWM_OOV      (*(RwReg*)0x4008C044U) /**< \brief (PWM) PWM Output Override Value Register */
+#define REG_PWM_OS       (*(RwReg*)0x4008C048U) /**< \brief (PWM) PWM Output Selection Register */
+#define REG_PWM_OSS      (*(WoReg*)0x4008C04CU) /**< \brief (PWM) PWM Output Selection Set Register */
+#define REG_PWM_OSC      (*(WoReg*)0x4008C050U) /**< \brief (PWM) PWM Output Selection Clear Register */
+#define REG_PWM_OSSUPD   (*(WoReg*)0x4008C054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
+#define REG_PWM_OSCUPD   (*(WoReg*)0x4008C058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
+#define REG_PWM_FMR      (*(RwReg*)0x4008C05CU) /**< \brief (PWM) PWM Fault Mode Register */
+#define REG_PWM_FSR      (*(RoReg*)0x4008C060U) /**< \brief (PWM) PWM Fault Status Register */
+#define REG_PWM_FCR      (*(WoReg*)0x4008C064U) /**< \brief (PWM) PWM Fault Clear Register */
+#define REG_PWM_FPV      (*(RwReg*)0x4008C068U) /**< \brief (PWM) PWM Fault Protection Value Register */
+#define REG_PWM_FPE      (*(RwReg*)0x4008C06CU) /**< \brief (PWM) PWM Fault Protection Enable Register */
+#define REG_PWM_ELMR     (*(RwReg*)0x4008C07CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
+#define REG_PWM_WPCR     (*(WoReg*)0x4008C0E4U) /**< \brief (PWM) PWM Write Protect Control Register */
+#define REG_PWM_WPSR     (*(RoReg*)0x4008C0E8U) /**< \brief (PWM) PWM Write Protect Status Register */
+#define REG_PWM_RPR      (*(RwReg*)0x4008C100U) /**< \brief (PWM) Receive Pointer Register */
+#define REG_PWM_RCR      (*(RwReg*)0x4008C104U) /**< \brief (PWM) Receive Counter Register */
+#define REG_PWM_TPR      (*(RwReg*)0x4008C108U) /**< \brief (PWM) Transmit Pointer Register */
+#define REG_PWM_TCR      (*(RwReg*)0x4008C10CU) /**< \brief (PWM) Transmit Counter Register */
+#define REG_PWM_RNPR     (*(RwReg*)0x4008C110U) /**< \brief (PWM) Receive Next Pointer Register */
+#define REG_PWM_RNCR     (*(RwReg*)0x4008C114U) /**< \brief (PWM) Receive Next Counter Register */
+#define REG_PWM_TNPR     (*(RwReg*)0x4008C118U) /**< \brief (PWM) Transmit Next Pointer Register */
+#define REG_PWM_TNCR     (*(RwReg*)0x4008C11CU) /**< \brief (PWM) Transmit Next Counter Register */
+#define REG_PWM_PTCR     (*(WoReg*)0x4008C120U) /**< \brief (PWM) Transfer Control Register */
+#define REG_PWM_PTSR     (*(RoReg*)0x4008C124U) /**< \brief (PWM) Transfer Status Register */
+#define REG_PWM_CMPV0    (*(RwReg*)0x4008C130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
+#define REG_PWM_CMPVUPD0 (*(WoReg*)0x4008C134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
+#define REG_PWM_CMPM0    (*(RwReg*)0x4008C138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
+#define REG_PWM_CMPMUPD0 (*(WoReg*)0x4008C13CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
+#define REG_PWM_CMPV1    (*(RwReg*)0x4008C140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
+#define REG_PWM_CMPVUPD1 (*(WoReg*)0x4008C144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
+#define REG_PWM_CMPM1    (*(RwReg*)0x4008C148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
+#define REG_PWM_CMPMUPD1 (*(WoReg*)0x4008C14CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
+#define REG_PWM_CMPV2    (*(RwReg*)0x4008C150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
+#define REG_PWM_CMPVUPD2 (*(WoReg*)0x4008C154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
+#define REG_PWM_CMPM2    (*(RwReg*)0x4008C158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
+#define REG_PWM_CMPMUPD2 (*(WoReg*)0x4008C15CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
+#define REG_PWM_CMPV3    (*(RwReg*)0x4008C160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
+#define REG_PWM_CMPVUPD3 (*(WoReg*)0x4008C164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
+#define REG_PWM_CMPM3    (*(RwReg*)0x4008C168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
+#define REG_PWM_CMPMUPD3 (*(WoReg*)0x4008C16CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
+#define REG_PWM_CMPV4    (*(RwReg*)0x4008C170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
+#define REG_PWM_CMPVUPD4 (*(WoReg*)0x4008C174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
+#define REG_PWM_CMPM4    (*(RwReg*)0x4008C178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
+#define REG_PWM_CMPMUPD4 (*(WoReg*)0x4008C17CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
+#define REG_PWM_CMPV5    (*(RwReg*)0x4008C180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
+#define REG_PWM_CMPVUPD5 (*(WoReg*)0x4008C184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
+#define REG_PWM_CMPM5    (*(RwReg*)0x4008C188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
+#define REG_PWM_CMPMUPD5 (*(WoReg*)0x4008C18CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
+#define REG_PWM_CMPV6    (*(RwReg*)0x4008C190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
+#define REG_PWM_CMPVUPD6 (*(WoReg*)0x4008C194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
+#define REG_PWM_CMPM6    (*(RwReg*)0x4008C198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
+#define REG_PWM_CMPMUPD6 (*(WoReg*)0x4008C19CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
+#define REG_PWM_CMPV7    (*(RwReg*)0x4008C1A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
+#define REG_PWM_CMPVUPD7 (*(WoReg*)0x4008C1A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
+#define REG_PWM_CMPM7    (*(RwReg*)0x4008C1A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
+#define REG_PWM_CMPMUPD7 (*(WoReg*)0x4008C1ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
+#define REG_PWM_CMR0     (*(RwReg*)0x4008C200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
+#define REG_PWM_CDTY0    (*(RwReg*)0x4008C204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
+#define REG_PWM_CDTYUPD0 (*(WoReg*)0x4008C208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
+#define REG_PWM_CPRD0    (*(RwReg*)0x4008C20CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
+#define REG_PWM_CPRDUPD0 (*(WoReg*)0x4008C210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
+#define REG_PWM_CCNT0    (*(RoReg*)0x4008C214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
+#define REG_PWM_DT0      (*(RwReg*)0x4008C218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
+#define REG_PWM_DTUPD0   (*(WoReg*)0x4008C21CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
+#define REG_PWM_CMR1     (*(RwReg*)0x4008C220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
+#define REG_PWM_CDTY1    (*(RwReg*)0x4008C224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
+#define REG_PWM_CDTYUPD1 (*(WoReg*)0x4008C228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
+#define REG_PWM_CPRD1    (*(RwReg*)0x4008C22CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
+#define REG_PWM_CPRDUPD1 (*(WoReg*)0x4008C230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
+#define REG_PWM_CCNT1    (*(RoReg*)0x4008C234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
+#define REG_PWM_DT1      (*(RwReg*)0x4008C238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
+#define REG_PWM_DTUPD1   (*(WoReg*)0x4008C23CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
+#define REG_PWM_CMR2     (*(RwReg*)0x4008C240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
+#define REG_PWM_CDTY2    (*(RwReg*)0x4008C244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
+#define REG_PWM_CDTYUPD2 (*(WoReg*)0x4008C248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
+#define REG_PWM_CPRD2    (*(RwReg*)0x4008C24CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
+#define REG_PWM_CPRDUPD2 (*(WoReg*)0x4008C250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
+#define REG_PWM_CCNT2    (*(RoReg*)0x4008C254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
+#define REG_PWM_DT2      (*(RwReg*)0x4008C258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
+#define REG_PWM_DTUPD2   (*(WoReg*)0x4008C25CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
+#define REG_PWM_CMR3     (*(RwReg*)0x4008C260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
+#define REG_PWM_CDTY3    (*(RwReg*)0x4008C264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
+#define REG_PWM_CDTYUPD3 (*(WoReg*)0x4008C268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
+#define REG_PWM_CPRD3    (*(RwReg*)0x4008C26CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
+#define REG_PWM_CPRDUPD3 (*(WoReg*)0x4008C270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
+#define REG_PWM_CCNT3    (*(RoReg*)0x4008C274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
+#define REG_PWM_DT3      (*(RwReg*)0x4008C278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
+#define REG_PWM_DTUPD3   (*(WoReg*)0x4008C27CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_PWM_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_rstc.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_rstc.h
new file mode 100644
index 000000000..e4eaafc54
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_rstc.h
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_RSTC_INSTANCE_
+#define _SAM3U_RSTC_INSTANCE_
+
+/* ========== Register definition for RSTC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_RSTC_CR          (0x400E1200U) /**< \brief (RSTC) Control Register */
+#define REG_RSTC_SR          (0x400E1204U) /**< \brief (RSTC) Status Register */
+#define REG_RSTC_MR          (0x400E1208U) /**< \brief (RSTC) Mode Register */
+#else
+#define REG_RSTC_CR (*(WoReg*)0x400E1200U) /**< \brief (RSTC) Control Register */
+#define REG_RSTC_SR (*(RoReg*)0x400E1204U) /**< \brief (RSTC) Status Register */
+#define REG_RSTC_MR (*(RwReg*)0x400E1208U) /**< \brief (RSTC) Mode Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_RSTC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_rtc.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_rtc.h
new file mode 100644
index 000000000..70848a5f1
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_rtc.h
@@ -0,0 +1,64 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_RTC_INSTANCE_
+#define _SAM3U_RTC_INSTANCE_
+
+/* ========== Register definition for RTC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_RTC_CR              (0x400E1260U) /**< \brief (RTC) Control Register */
+#define REG_RTC_MR              (0x400E1264U) /**< \brief (RTC) Mode Register */
+#define REG_RTC_TIMR            (0x400E1268U) /**< \brief (RTC) Time Register */
+#define REG_RTC_CALR            (0x400E126CU) /**< \brief (RTC) Calendar Register */
+#define REG_RTC_TIMALR          (0x400E1270U) /**< \brief (RTC) Time Alarm Register */
+#define REG_RTC_CALALR          (0x400E1274U) /**< \brief (RTC) Calendar Alarm Register */
+#define REG_RTC_SR              (0x400E1278U) /**< \brief (RTC) Status Register */
+#define REG_RTC_SCCR            (0x400E127CU) /**< \brief (RTC) Status Clear Command Register */
+#define REG_RTC_IER             (0x400E1280U) /**< \brief (RTC) Interrupt Enable Register */
+#define REG_RTC_IDR             (0x400E1284U) /**< \brief (RTC) Interrupt Disable Register */
+#define REG_RTC_IMR             (0x400E1288U) /**< \brief (RTC) Interrupt Mask Register */
+#define REG_RTC_VER             (0x400E128CU) /**< \brief (RTC) Valid Entry Register */
+#define REG_RTC_WPMR            (0x400E1344U) /**< \brief (RTC) Write Protect Mode Register */
+#else
+#define REG_RTC_CR     (*(RwReg*)0x400E1260U) /**< \brief (RTC) Control Register */
+#define REG_RTC_MR     (*(RwReg*)0x400E1264U) /**< \brief (RTC) Mode Register */
+#define REG_RTC_TIMR   (*(RwReg*)0x400E1268U) /**< \brief (RTC) Time Register */
+#define REG_RTC_CALR   (*(RwReg*)0x400E126CU) /**< \brief (RTC) Calendar Register */
+#define REG_RTC_TIMALR (*(RwReg*)0x400E1270U) /**< \brief (RTC) Time Alarm Register */
+#define REG_RTC_CALALR (*(RwReg*)0x400E1274U) /**< \brief (RTC) Calendar Alarm Register */
+#define REG_RTC_SR     (*(RoReg*)0x400E1278U) /**< \brief (RTC) Status Register */
+#define REG_RTC_SCCR   (*(WoReg*)0x400E127CU) /**< \brief (RTC) Status Clear Command Register */
+#define REG_RTC_IER    (*(WoReg*)0x400E1280U) /**< \brief (RTC) Interrupt Enable Register */
+#define REG_RTC_IDR    (*(WoReg*)0x400E1284U) /**< \brief (RTC) Interrupt Disable Register */
+#define REG_RTC_IMR    (*(RoReg*)0x400E1288U) /**< \brief (RTC) Interrupt Mask Register */
+#define REG_RTC_VER    (*(RoReg*)0x400E128CU) /**< \brief (RTC) Valid Entry Register */
+#define REG_RTC_WPMR   (*(RwReg*)0x400E1344U) /**< \brief (RTC) Write Protect Mode Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_RTC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_rtt.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_rtt.h
new file mode 100644
index 000000000..30fb346a0
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_rtt.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_RTT_INSTANCE_
+#define _SAM3U_RTT_INSTANCE_
+
+/* ========== Register definition for RTT peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_RTT_MR          (0x400E1230U) /**< \brief (RTT) Mode Register */
+#define REG_RTT_AR          (0x400E1234U) /**< \brief (RTT) Alarm Register */
+#define REG_RTT_VR          (0x400E1238U) /**< \brief (RTT) Value Register */
+#define REG_RTT_SR          (0x400E123CU) /**< \brief (RTT) Status Register */
+#else
+#define REG_RTT_MR (*(RwReg*)0x400E1230U) /**< \brief (RTT) Mode Register */
+#define REG_RTT_AR (*(RwReg*)0x400E1234U) /**< \brief (RTT) Alarm Register */
+#define REG_RTT_VR (*(RoReg*)0x400E1238U) /**< \brief (RTT) Value Register */
+#define REG_RTT_SR (*(RoReg*)0x400E123CU) /**< \brief (RTT) Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_RTT_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_smc.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_smc.h
new file mode 100644
index 000000000..6cc8e8cb3
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_smc.h
@@ -0,0 +1,144 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_SMC_INSTANCE_
+#define _SAM3U_SMC_INSTANCE_
+
+/* ========== Register definition for SMC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_SMC_CFG               (0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */
+#define REG_SMC_CTRL              (0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */
+#define REG_SMC_SR                (0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */
+#define REG_SMC_IER               (0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */
+#define REG_SMC_IDR               (0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */
+#define REG_SMC_IMR               (0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */
+#define REG_SMC_ADDR              (0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */
+#define REG_SMC_BANK              (0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */
+#define REG_SMC_ECC_CTRL          (0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */
+#define REG_SMC_ECC_MD            (0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */
+#define REG_SMC_ECC_SR1           (0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */
+#define REG_SMC_ECC_PR0           (0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */
+#define REG_SMC_ECC_PR1           (0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */
+#define REG_SMC_ECC_SR2           (0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */
+#define REG_SMC_ECC_PR2           (0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */
+#define REG_SMC_ECC_PR3           (0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */
+#define REG_SMC_ECC_PR4           (0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */
+#define REG_SMC_ECC_PR5           (0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */
+#define REG_SMC_ECC_PR6           (0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */
+#define REG_SMC_ECC_PR7           (0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */
+#define REG_SMC_ECC_PR8           (0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */
+#define REG_SMC_ECC_PR9           (0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */
+#define REG_SMC_ECC_PR10          (0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */
+#define REG_SMC_ECC_PR11          (0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */
+#define REG_SMC_ECC_PR12          (0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */
+#define REG_SMC_ECC_PR13          (0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */
+#define REG_SMC_ECC_PR14          (0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */
+#define REG_SMC_ECC_PR15          (0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */
+#define REG_SMC_SETUP0            (0x400E0070U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
+#define REG_SMC_PULSE0            (0x400E0074U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
+#define REG_SMC_CYCLE0            (0x400E0078U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
+#define REG_SMC_TIMINGS0          (0x400E007CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */
+#define REG_SMC_MODE0             (0x400E0080U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
+#define REG_SMC_SETUP1            (0x400E0084U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
+#define REG_SMC_PULSE1            (0x400E0088U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
+#define REG_SMC_CYCLE1            (0x400E008CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
+#define REG_SMC_TIMINGS1          (0x400E0090U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */
+#define REG_SMC_MODE1             (0x400E0094U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
+#define REG_SMC_SETUP2            (0x400E0098U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
+#define REG_SMC_PULSE2            (0x400E009CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
+#define REG_SMC_CYCLE2            (0x400E00A0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
+#define REG_SMC_TIMINGS2          (0x400E00A4U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */
+#define REG_SMC_MODE2             (0x400E00A8U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
+#define REG_SMC_SETUP3            (0x400E00ACU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
+#define REG_SMC_PULSE3            (0x400E00B0U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
+#define REG_SMC_CYCLE3            (0x400E00B4U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
+#define REG_SMC_TIMINGS3          (0x400E00B8U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */
+#define REG_SMC_MODE3             (0x400E00BCU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
+#define REG_SMC_OCMS              (0x400E0110U) /**< \brief (SMC) SMC OCMS Register */
+#define REG_SMC_KEY1              (0x400E0114U) /**< \brief (SMC) SMC OCMS KEY1 Register */
+#define REG_SMC_KEY2              (0x400E0118U) /**< \brief (SMC) SMC OCMS KEY2 Register */
+#define REG_SMC_WPCR              (0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */
+#define REG_SMC_WPSR              (0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */
+#else
+#define REG_SMC_CFG      (*(RwReg*)0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */
+#define REG_SMC_CTRL     (*(WoReg*)0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */
+#define REG_SMC_SR       (*(RoReg*)0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */
+#define REG_SMC_IER      (*(WoReg*)0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */
+#define REG_SMC_IDR      (*(WoReg*)0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */
+#define REG_SMC_IMR      (*(RoReg*)0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */
+#define REG_SMC_ADDR     (*(RwReg*)0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */
+#define REG_SMC_BANK     (*(RwReg*)0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */
+#define REG_SMC_ECC_CTRL (*(WoReg*)0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */
+#define REG_SMC_ECC_MD   (*(RwReg*)0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */
+#define REG_SMC_ECC_SR1  (*(RoReg*)0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */
+#define REG_SMC_ECC_PR0  (*(RoReg*)0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */
+#define REG_SMC_ECC_PR1  (*(RoReg*)0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */
+#define REG_SMC_ECC_SR2  (*(RoReg*)0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */
+#define REG_SMC_ECC_PR2  (*(RoReg*)0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */
+#define REG_SMC_ECC_PR3  (*(RoReg*)0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */
+#define REG_SMC_ECC_PR4  (*(RoReg*)0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */
+#define REG_SMC_ECC_PR5  (*(RoReg*)0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */
+#define REG_SMC_ECC_PR6  (*(RoReg*)0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */
+#define REG_SMC_ECC_PR7  (*(RoReg*)0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */
+#define REG_SMC_ECC_PR8  (*(RoReg*)0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */
+#define REG_SMC_ECC_PR9  (*(RoReg*)0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */
+#define REG_SMC_ECC_PR10 (*(RoReg*)0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */
+#define REG_SMC_ECC_PR11 (*(RoReg*)0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */
+#define REG_SMC_ECC_PR12 (*(RoReg*)0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */
+#define REG_SMC_ECC_PR13 (*(RoReg*)0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */
+#define REG_SMC_ECC_PR14 (*(RoReg*)0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */
+#define REG_SMC_ECC_PR15 (*(RoReg*)0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */
+#define REG_SMC_SETUP0   (*(RwReg*)0x400E0070U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
+#define REG_SMC_PULSE0   (*(RwReg*)0x400E0074U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
+#define REG_SMC_CYCLE0   (*(RwReg*)0x400E0078U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
+#define REG_SMC_TIMINGS0 (*(RwReg*)0x400E007CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */
+#define REG_SMC_MODE0    (*(RwReg*)0x400E0080U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
+#define REG_SMC_SETUP1   (*(RwReg*)0x400E0084U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
+#define REG_SMC_PULSE1   (*(RwReg*)0x400E0088U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
+#define REG_SMC_CYCLE1   (*(RwReg*)0x400E008CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
+#define REG_SMC_TIMINGS1 (*(RwReg*)0x400E0090U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */
+#define REG_SMC_MODE1    (*(RwReg*)0x400E0094U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
+#define REG_SMC_SETUP2   (*(RwReg*)0x400E0098U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
+#define REG_SMC_PULSE2   (*(RwReg*)0x400E009CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
+#define REG_SMC_CYCLE2   (*(RwReg*)0x400E00A0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
+#define REG_SMC_TIMINGS2 (*(RwReg*)0x400E00A4U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */
+#define REG_SMC_MODE2    (*(RwReg*)0x400E00A8U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
+#define REG_SMC_SETUP3   (*(RwReg*)0x400E00ACU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
+#define REG_SMC_PULSE3   (*(RwReg*)0x400E00B0U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
+#define REG_SMC_CYCLE3   (*(RwReg*)0x400E00B4U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
+#define REG_SMC_TIMINGS3 (*(RwReg*)0x400E00B8U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */
+#define REG_SMC_MODE3    (*(RwReg*)0x400E00BCU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
+#define REG_SMC_OCMS     (*(RwReg*)0x400E0110U) /**< \brief (SMC) SMC OCMS Register */
+#define REG_SMC_KEY1     (*(WoReg*)0x400E0114U) /**< \brief (SMC) SMC OCMS KEY1 Register */
+#define REG_SMC_KEY2     (*(WoReg*)0x400E0118U) /**< \brief (SMC) SMC OCMS KEY2 Register */
+#define REG_SMC_WPCR     (*(WoReg*)0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */
+#define REG_SMC_WPSR     (*(RoReg*)0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_SMC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_spi.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_spi.h
new file mode 100644
index 000000000..01da0f3b1
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_spi.h
@@ -0,0 +1,60 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_SPI_INSTANCE_
+#define _SAM3U_SPI_INSTANCE_
+
+/* ========== Register definition for SPI peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_SPI_CR              (0x40008000U) /**< \brief (SPI) Control Register */
+#define REG_SPI_MR              (0x40008004U) /**< \brief (SPI) Mode Register */
+#define REG_SPI_RDR             (0x40008008U) /**< \brief (SPI) Receive Data Register */
+#define REG_SPI_TDR             (0x4000800CU) /**< \brief (SPI) Transmit Data Register */
+#define REG_SPI_SR              (0x40008010U) /**< \brief (SPI) Status Register */
+#define REG_SPI_IER             (0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
+#define REG_SPI_IDR             (0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
+#define REG_SPI_IMR             (0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
+#define REG_SPI_CSR             (0x40008030U) /**< \brief (SPI) Chip Select Register */
+#define REG_SPI_WPMR            (0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
+#define REG_SPI_WPSR            (0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
+#else
+#define REG_SPI_CR     (*(WoReg*)0x40008000U) /**< \brief (SPI) Control Register */
+#define REG_SPI_MR     (*(RwReg*)0x40008004U) /**< \brief (SPI) Mode Register */
+#define REG_SPI_RDR    (*(RoReg*)0x40008008U) /**< \brief (SPI) Receive Data Register */
+#define REG_SPI_TDR    (*(WoReg*)0x4000800CU) /**< \brief (SPI) Transmit Data Register */
+#define REG_SPI_SR     (*(RoReg*)0x40008010U) /**< \brief (SPI) Status Register */
+#define REG_SPI_IER    (*(WoReg*)0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
+#define REG_SPI_IDR    (*(WoReg*)0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
+#define REG_SPI_IMR    (*(RoReg*)0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
+#define REG_SPI_CSR    (*(RwReg*)0x40008030U) /**< \brief (SPI) Chip Select Register */
+#define REG_SPI_WPMR   (*(RwReg*)0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
+#define REG_SPI_WPSR   (*(RoReg*)0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_SPI_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_ssc.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_ssc.h
new file mode 100644
index 000000000..8960a1196
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_ssc.h
@@ -0,0 +1,74 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_SSC_INSTANCE_
+#define _SAM3U_SSC_INSTANCE_
+
+/* ========== Register definition for SSC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_SSC_CR            (0x40004000U) /**< \brief (SSC) Control Register */
+#define REG_SSC_CMR           (0x40004004U) /**< \brief (SSC) Clock Mode Register */
+#define REG_SSC_RCMR          (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
+#define REG_SSC_RFMR          (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
+#define REG_SSC_TCMR          (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
+#define REG_SSC_TFMR          (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
+#define REG_SSC_RHR           (0x40004020U) /**< \brief (SSC) Receive Holding Register */
+#define REG_SSC_THR           (0x40004024U) /**< \brief (SSC) Transmit Holding Register */
+#define REG_SSC_RSHR          (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
+#define REG_SSC_TSHR          (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
+#define REG_SSC_RC0R          (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
+#define REG_SSC_RC1R          (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
+#define REG_SSC_SR            (0x40004040U) /**< \brief (SSC) Status Register */
+#define REG_SSC_IER           (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
+#define REG_SSC_IDR           (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
+#define REG_SSC_IMR           (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
+#define REG_SSC_WPMR          (0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
+#define REG_SSC_WPSR          (0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
+#else
+#define REG_SSC_CR   (*(WoReg*)0x40004000U) /**< \brief (SSC) Control Register */
+#define REG_SSC_CMR  (*(RwReg*)0x40004004U) /**< \brief (SSC) Clock Mode Register */
+#define REG_SSC_RCMR (*(RwReg*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
+#define REG_SSC_RFMR (*(RwReg*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
+#define REG_SSC_TCMR (*(RwReg*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
+#define REG_SSC_TFMR (*(RwReg*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
+#define REG_SSC_RHR  (*(RoReg*)0x40004020U) /**< \brief (SSC) Receive Holding Register */
+#define REG_SSC_THR  (*(WoReg*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */
+#define REG_SSC_RSHR (*(RoReg*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
+#define REG_SSC_TSHR (*(RwReg*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
+#define REG_SSC_RC0R (*(RwReg*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
+#define REG_SSC_RC1R (*(RwReg*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
+#define REG_SSC_SR   (*(RoReg*)0x40004040U) /**< \brief (SSC) Status Register */
+#define REG_SSC_IER  (*(WoReg*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
+#define REG_SSC_IDR  (*(WoReg*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
+#define REG_SSC_IMR  (*(RoReg*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
+#define REG_SSC_WPMR (*(RwReg*)0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
+#define REG_SSC_WPSR (*(RoReg*)0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_SSC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_supc.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_supc.h
new file mode 100644
index 000000000..cf26eaf8d
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_supc.h
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_SUPC_INSTANCE_
+#define _SAM3U_SUPC_INSTANCE_
+
+/* ========== Register definition for SUPC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_SUPC_CR            (0x400E1210U) /**< \brief (SUPC) Supply Controller Control Register */
+#define REG_SUPC_SMMR          (0x400E1214U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
+#define REG_SUPC_MR            (0x400E1218U) /**< \brief (SUPC) Supply Controller Mode Register */
+#define REG_SUPC_WUMR          (0x400E121CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
+#define REG_SUPC_WUIR          (0x400E1220U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
+#define REG_SUPC_SR            (0x400E1224U) /**< \brief (SUPC) Supply Controller Status Register */
+#else
+#define REG_SUPC_CR   (*(WoReg*)0x400E1210U) /**< \brief (SUPC) Supply Controller Control Register */
+#define REG_SUPC_SMMR (*(RwReg*)0x400E1214U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
+#define REG_SUPC_MR   (*(RwReg*)0x400E1218U) /**< \brief (SUPC) Supply Controller Mode Register */
+#define REG_SUPC_WUMR (*(RwReg*)0x400E121CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
+#define REG_SUPC_WUIR (*(RwReg*)0x400E1220U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
+#define REG_SUPC_SR   (*(RoReg*)0x400E1224U) /**< \brief (SUPC) Supply Controller Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_SUPC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_tc0.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_tc0.h
new file mode 100644
index 000000000..ad44c5513
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_tc0.h
@@ -0,0 +1,110 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_TC0_INSTANCE_
+#define _SAM3U_TC0_INSTANCE_
+
+/* ========== Register definition for TC0 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_TC0_CCR0          (0x40080000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
+#define REG_TC0_CMR0          (0x40080004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
+#define REG_TC0_CV0           (0x40080010U) /**< \brief (TC0) Counter Value (channel = 0) */
+#define REG_TC0_RA0           (0x40080014U) /**< \brief (TC0) Register A (channel = 0) */
+#define REG_TC0_RB0           (0x40080018U) /**< \brief (TC0) Register B (channel = 0) */
+#define REG_TC0_RC0           (0x4008001CU) /**< \brief (TC0) Register C (channel = 0) */
+#define REG_TC0_SR0           (0x40080020U) /**< \brief (TC0) Status Register (channel = 0) */
+#define REG_TC0_IER0          (0x40080024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
+#define REG_TC0_IDR0          (0x40080028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
+#define REG_TC0_IMR0          (0x4008002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
+#define REG_TC0_CCR1          (0x40080040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
+#define REG_TC0_CMR1          (0x40080044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
+#define REG_TC0_CV1           (0x40080050U) /**< \brief (TC0) Counter Value (channel = 1) */
+#define REG_TC0_RA1           (0x40080054U) /**< \brief (TC0) Register A (channel = 1) */
+#define REG_TC0_RB1           (0x40080058U) /**< \brief (TC0) Register B (channel = 1) */
+#define REG_TC0_RC1           (0x4008005CU) /**< \brief (TC0) Register C (channel = 1) */
+#define REG_TC0_SR1           (0x40080060U) /**< \brief (TC0) Status Register (channel = 1) */
+#define REG_TC0_IER1          (0x40080064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
+#define REG_TC0_IDR1          (0x40080068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
+#define REG_TC0_IMR1          (0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
+#define REG_TC0_CCR2          (0x40080080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
+#define REG_TC0_CMR2          (0x40080084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
+#define REG_TC0_CV2           (0x40080090U) /**< \brief (TC0) Counter Value (channel = 2) */
+#define REG_TC0_RA2           (0x40080094U) /**< \brief (TC0) Register A (channel = 2) */
+#define REG_TC0_RB2           (0x40080098U) /**< \brief (TC0) Register B (channel = 2) */
+#define REG_TC0_RC2           (0x4008009CU) /**< \brief (TC0) Register C (channel = 2) */
+#define REG_TC0_SR2           (0x400800A0U) /**< \brief (TC0) Status Register (channel = 2) */
+#define REG_TC0_IER2          (0x400800A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
+#define REG_TC0_IDR2          (0x400800A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
+#define REG_TC0_IMR2          (0x400800ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
+#define REG_TC0_BCR           (0x400800C0U) /**< \brief (TC0) Block Control Register */
+#define REG_TC0_BMR           (0x400800C4U) /**< \brief (TC0) Block Mode Register */
+#define REG_TC0_QIER          (0x400800C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
+#define REG_TC0_QIDR          (0x400800CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
+#define REG_TC0_QIMR          (0x400800D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
+#define REG_TC0_QISR          (0x400800D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
+#else
+#define REG_TC0_CCR0 (*(WoReg*)0x40080000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
+#define REG_TC0_CMR0 (*(RwReg*)0x40080004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
+#define REG_TC0_CV0  (*(RoReg*)0x40080010U) /**< \brief (TC0) Counter Value (channel = 0) */
+#define REG_TC0_RA0  (*(RwReg*)0x40080014U) /**< \brief (TC0) Register A (channel = 0) */
+#define REG_TC0_RB0  (*(RwReg*)0x40080018U) /**< \brief (TC0) Register B (channel = 0) */
+#define REG_TC0_RC0  (*(RwReg*)0x4008001CU) /**< \brief (TC0) Register C (channel = 0) */
+#define REG_TC0_SR0  (*(RoReg*)0x40080020U) /**< \brief (TC0) Status Register (channel = 0) */
+#define REG_TC0_IER0 (*(WoReg*)0x40080024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
+#define REG_TC0_IDR0 (*(WoReg*)0x40080028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
+#define REG_TC0_IMR0 (*(RoReg*)0x4008002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
+#define REG_TC0_CCR1 (*(WoReg*)0x40080040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
+#define REG_TC0_CMR1 (*(RwReg*)0x40080044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
+#define REG_TC0_CV1  (*(RoReg*)0x40080050U) /**< \brief (TC0) Counter Value (channel = 1) */
+#define REG_TC0_RA1  (*(RwReg*)0x40080054U) /**< \brief (TC0) Register A (channel = 1) */
+#define REG_TC0_RB1  (*(RwReg*)0x40080058U) /**< \brief (TC0) Register B (channel = 1) */
+#define REG_TC0_RC1  (*(RwReg*)0x4008005CU) /**< \brief (TC0) Register C (channel = 1) */
+#define REG_TC0_SR1  (*(RoReg*)0x40080060U) /**< \brief (TC0) Status Register (channel = 1) */
+#define REG_TC0_IER1 (*(WoReg*)0x40080064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
+#define REG_TC0_IDR1 (*(WoReg*)0x40080068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
+#define REG_TC0_IMR1 (*(RoReg*)0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
+#define REG_TC0_CCR2 (*(WoReg*)0x40080080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
+#define REG_TC0_CMR2 (*(RwReg*)0x40080084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
+#define REG_TC0_CV2  (*(RoReg*)0x40080090U) /**< \brief (TC0) Counter Value (channel = 2) */
+#define REG_TC0_RA2  (*(RwReg*)0x40080094U) /**< \brief (TC0) Register A (channel = 2) */
+#define REG_TC0_RB2  (*(RwReg*)0x40080098U) /**< \brief (TC0) Register B (channel = 2) */
+#define REG_TC0_RC2  (*(RwReg*)0x4008009CU) /**< \brief (TC0) Register C (channel = 2) */
+#define REG_TC0_SR2  (*(RoReg*)0x400800A0U) /**< \brief (TC0) Status Register (channel = 2) */
+#define REG_TC0_IER2 (*(WoReg*)0x400800A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
+#define REG_TC0_IDR2 (*(WoReg*)0x400800A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
+#define REG_TC0_IMR2 (*(RoReg*)0x400800ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
+#define REG_TC0_BCR  (*(WoReg*)0x400800C0U) /**< \brief (TC0) Block Control Register */
+#define REG_TC0_BMR  (*(RwReg*)0x400800C4U) /**< \brief (TC0) Block Mode Register */
+#define REG_TC0_QIER (*(WoReg*)0x400800C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
+#define REG_TC0_QIDR (*(WoReg*)0x400800CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
+#define REG_TC0_QIMR (*(RoReg*)0x400800D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
+#define REG_TC0_QISR (*(RoReg*)0x400800D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_TC0_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_twi0.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_twi0.h
new file mode 100644
index 000000000..6498136c5
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_twi0.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_TWI0_INSTANCE_
+#define _SAM3U_TWI0_INSTANCE_
+
+/* ========== Register definition for TWI0 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_TWI0_CR            (0x40084000U) /**< \brief (TWI0) Control Register */
+#define REG_TWI0_MMR           (0x40084004U) /**< \brief (TWI0) Master Mode Register */
+#define REG_TWI0_SMR           (0x40084008U) /**< \brief (TWI0) Slave Mode Register */
+#define REG_TWI0_IADR          (0x4008400CU) /**< \brief (TWI0) Internal Address Register */
+#define REG_TWI0_CWGR          (0x40084010U) /**< \brief (TWI0) Clock Waveform Generator Register */
+#define REG_TWI0_SR            (0x40084020U) /**< \brief (TWI0) Status Register */
+#define REG_TWI0_IER           (0x40084024U) /**< \brief (TWI0) Interrupt Enable Register */
+#define REG_TWI0_IDR           (0x40084028U) /**< \brief (TWI0) Interrupt Disable Register */
+#define REG_TWI0_IMR           (0x4008402CU) /**< \brief (TWI0) Interrupt Mask Register */
+#define REG_TWI0_RHR           (0x40084030U) /**< \brief (TWI0) Receive Holding Register */
+#define REG_TWI0_THR           (0x40084034U) /**< \brief (TWI0) Transmit Holding Register */
+#define REG_TWI0_RPR           (0x40084100U) /**< \brief (TWI0) Receive Pointer Register */
+#define REG_TWI0_RCR           (0x40084104U) /**< \brief (TWI0) Receive Counter Register */
+#define REG_TWI0_TPR           (0x40084108U) /**< \brief (TWI0) Transmit Pointer Register */
+#define REG_TWI0_TCR           (0x4008410CU) /**< \brief (TWI0) Transmit Counter Register */
+#define REG_TWI0_RNPR          (0x40084110U) /**< \brief (TWI0) Receive Next Pointer Register */
+#define REG_TWI0_RNCR          (0x40084114U) /**< \brief (TWI0) Receive Next Counter Register */
+#define REG_TWI0_TNPR          (0x40084118U) /**< \brief (TWI0) Transmit Next Pointer Register */
+#define REG_TWI0_TNCR          (0x4008411CU) /**< \brief (TWI0) Transmit Next Counter Register */
+#define REG_TWI0_PTCR          (0x40084120U) /**< \brief (TWI0) Transfer Control Register */
+#define REG_TWI0_PTSR          (0x40084124U) /**< \brief (TWI0) Transfer Status Register */
+#else
+#define REG_TWI0_CR   (*(WoReg*)0x40084000U) /**< \brief (TWI0) Control Register */
+#define REG_TWI0_MMR  (*(RwReg*)0x40084004U) /**< \brief (TWI0) Master Mode Register */
+#define REG_TWI0_SMR  (*(RwReg*)0x40084008U) /**< \brief (TWI0) Slave Mode Register */
+#define REG_TWI0_IADR (*(RwReg*)0x4008400CU) /**< \brief (TWI0) Internal Address Register */
+#define REG_TWI0_CWGR (*(RwReg*)0x40084010U) /**< \brief (TWI0) Clock Waveform Generator Register */
+#define REG_TWI0_SR   (*(RoReg*)0x40084020U) /**< \brief (TWI0) Status Register */
+#define REG_TWI0_IER  (*(WoReg*)0x40084024U) /**< \brief (TWI0) Interrupt Enable Register */
+#define REG_TWI0_IDR  (*(WoReg*)0x40084028U) /**< \brief (TWI0) Interrupt Disable Register */
+#define REG_TWI0_IMR  (*(RoReg*)0x4008402CU) /**< \brief (TWI0) Interrupt Mask Register */
+#define REG_TWI0_RHR  (*(RoReg*)0x40084030U) /**< \brief (TWI0) Receive Holding Register */
+#define REG_TWI0_THR  (*(WoReg*)0x40084034U) /**< \brief (TWI0) Transmit Holding Register */
+#define REG_TWI0_RPR  (*(RwReg*)0x40084100U) /**< \brief (TWI0) Receive Pointer Register */
+#define REG_TWI0_RCR  (*(RwReg*)0x40084104U) /**< \brief (TWI0) Receive Counter Register */
+#define REG_TWI0_TPR  (*(RwReg*)0x40084108U) /**< \brief (TWI0) Transmit Pointer Register */
+#define REG_TWI0_TCR  (*(RwReg*)0x4008410CU) /**< \brief (TWI0) Transmit Counter Register */
+#define REG_TWI0_RNPR (*(RwReg*)0x40084110U) /**< \brief (TWI0) Receive Next Pointer Register */
+#define REG_TWI0_RNCR (*(RwReg*)0x40084114U) /**< \brief (TWI0) Receive Next Counter Register */
+#define REG_TWI0_TNPR (*(RwReg*)0x40084118U) /**< \brief (TWI0) Transmit Next Pointer Register */
+#define REG_TWI0_TNCR (*(RwReg*)0x4008411CU) /**< \brief (TWI0) Transmit Next Counter Register */
+#define REG_TWI0_PTCR (*(WoReg*)0x40084120U) /**< \brief (TWI0) Transfer Control Register */
+#define REG_TWI0_PTSR (*(RoReg*)0x40084124U) /**< \brief (TWI0) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_TWI0_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_twi1.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_twi1.h
new file mode 100644
index 000000000..aabfbad93
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_twi1.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_TWI1_INSTANCE_
+#define _SAM3U_TWI1_INSTANCE_
+
+/* ========== Register definition for TWI1 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_TWI1_CR            (0x40088000U) /**< \brief (TWI1) Control Register */
+#define REG_TWI1_MMR           (0x40088004U) /**< \brief (TWI1) Master Mode Register */
+#define REG_TWI1_SMR           (0x40088008U) /**< \brief (TWI1) Slave Mode Register */
+#define REG_TWI1_IADR          (0x4008800CU) /**< \brief (TWI1) Internal Address Register */
+#define REG_TWI1_CWGR          (0x40088010U) /**< \brief (TWI1) Clock Waveform Generator Register */
+#define REG_TWI1_SR            (0x40088020U) /**< \brief (TWI1) Status Register */
+#define REG_TWI1_IER           (0x40088024U) /**< \brief (TWI1) Interrupt Enable Register */
+#define REG_TWI1_IDR           (0x40088028U) /**< \brief (TWI1) Interrupt Disable Register */
+#define REG_TWI1_IMR           (0x4008802CU) /**< \brief (TWI1) Interrupt Mask Register */
+#define REG_TWI1_RHR           (0x40088030U) /**< \brief (TWI1) Receive Holding Register */
+#define REG_TWI1_THR           (0x40088034U) /**< \brief (TWI1) Transmit Holding Register */
+#define REG_TWI1_RPR           (0x40088100U) /**< \brief (TWI1) Receive Pointer Register */
+#define REG_TWI1_RCR           (0x40088104U) /**< \brief (TWI1) Receive Counter Register */
+#define REG_TWI1_TPR           (0x40088108U) /**< \brief (TWI1) Transmit Pointer Register */
+#define REG_TWI1_TCR           (0x4008810CU) /**< \brief (TWI1) Transmit Counter Register */
+#define REG_TWI1_RNPR          (0x40088110U) /**< \brief (TWI1) Receive Next Pointer Register */
+#define REG_TWI1_RNCR          (0x40088114U) /**< \brief (TWI1) Receive Next Counter Register */
+#define REG_TWI1_TNPR          (0x40088118U) /**< \brief (TWI1) Transmit Next Pointer Register */
+#define REG_TWI1_TNCR          (0x4008811CU) /**< \brief (TWI1) Transmit Next Counter Register */
+#define REG_TWI1_PTCR          (0x40088120U) /**< \brief (TWI1) Transfer Control Register */
+#define REG_TWI1_PTSR          (0x40088124U) /**< \brief (TWI1) Transfer Status Register */
+#else
+#define REG_TWI1_CR   (*(WoReg*)0x40088000U) /**< \brief (TWI1) Control Register */
+#define REG_TWI1_MMR  (*(RwReg*)0x40088004U) /**< \brief (TWI1) Master Mode Register */
+#define REG_TWI1_SMR  (*(RwReg*)0x40088008U) /**< \brief (TWI1) Slave Mode Register */
+#define REG_TWI1_IADR (*(RwReg*)0x4008800CU) /**< \brief (TWI1) Internal Address Register */
+#define REG_TWI1_CWGR (*(RwReg*)0x40088010U) /**< \brief (TWI1) Clock Waveform Generator Register */
+#define REG_TWI1_SR   (*(RoReg*)0x40088020U) /**< \brief (TWI1) Status Register */
+#define REG_TWI1_IER  (*(WoReg*)0x40088024U) /**< \brief (TWI1) Interrupt Enable Register */
+#define REG_TWI1_IDR  (*(WoReg*)0x40088028U) /**< \brief (TWI1) Interrupt Disable Register */
+#define REG_TWI1_IMR  (*(RoReg*)0x4008802CU) /**< \brief (TWI1) Interrupt Mask Register */
+#define REG_TWI1_RHR  (*(RoReg*)0x40088030U) /**< \brief (TWI1) Receive Holding Register */
+#define REG_TWI1_THR  (*(WoReg*)0x40088034U) /**< \brief (TWI1) Transmit Holding Register */
+#define REG_TWI1_RPR  (*(RwReg*)0x40088100U) /**< \brief (TWI1) Receive Pointer Register */
+#define REG_TWI1_RCR  (*(RwReg*)0x40088104U) /**< \brief (TWI1) Receive Counter Register */
+#define REG_TWI1_TPR  (*(RwReg*)0x40088108U) /**< \brief (TWI1) Transmit Pointer Register */
+#define REG_TWI1_TCR  (*(RwReg*)0x4008810CU) /**< \brief (TWI1) Transmit Counter Register */
+#define REG_TWI1_RNPR (*(RwReg*)0x40088110U) /**< \brief (TWI1) Receive Next Pointer Register */
+#define REG_TWI1_RNCR (*(RwReg*)0x40088114U) /**< \brief (TWI1) Receive Next Counter Register */
+#define REG_TWI1_TNPR (*(RwReg*)0x40088118U) /**< \brief (TWI1) Transmit Next Pointer Register */
+#define REG_TWI1_TNCR (*(RwReg*)0x4008811CU) /**< \brief (TWI1) Transmit Next Counter Register */
+#define REG_TWI1_PTCR (*(WoReg*)0x40088120U) /**< \brief (TWI1) Transfer Control Register */
+#define REG_TWI1_PTSR (*(RoReg*)0x40088124U) /**< \brief (TWI1) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_TWI1_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_uart.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_uart.h
new file mode 100644
index 000000000..f0cf7002c
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_uart.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_UART_INSTANCE_
+#define _SAM3U_UART_INSTANCE_
+
+/* ========== Register definition for UART peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_UART_CR            (0x400E0600U) /**< \brief (UART) Control Register */
+#define REG_UART_MR            (0x400E0604U) /**< \brief (UART) Mode Register */
+#define REG_UART_IER           (0x400E0608U) /**< \brief (UART) Interrupt Enable Register */
+#define REG_UART_IDR           (0x400E060CU) /**< \brief (UART) Interrupt Disable Register */
+#define REG_UART_IMR           (0x400E0610U) /**< \brief (UART) Interrupt Mask Register */
+#define REG_UART_SR            (0x400E0614U) /**< \brief (UART) Status Register */
+#define REG_UART_RHR           (0x400E0618U) /**< \brief (UART) Receive Holding Register */
+#define REG_UART_THR           (0x400E061CU) /**< \brief (UART) Transmit Holding Register */
+#define REG_UART_BRGR          (0x400E0620U) /**< \brief (UART) Baud Rate Generator Register */
+#define REG_UART_RPR           (0x400E0700U) /**< \brief (UART) Receive Pointer Register */
+#define REG_UART_RCR           (0x400E0704U) /**< \brief (UART) Receive Counter Register */
+#define REG_UART_TPR           (0x400E0708U) /**< \brief (UART) Transmit Pointer Register */
+#define REG_UART_TCR           (0x400E070CU) /**< \brief (UART) Transmit Counter Register */
+#define REG_UART_RNPR          (0x400E0710U) /**< \brief (UART) Receive Next Pointer Register */
+#define REG_UART_RNCR          (0x400E0714U) /**< \brief (UART) Receive Next Counter Register */
+#define REG_UART_TNPR          (0x400E0718U) /**< \brief (UART) Transmit Next Pointer Register */
+#define REG_UART_TNCR          (0x400E071CU) /**< \brief (UART) Transmit Next Counter Register */
+#define REG_UART_PTCR          (0x400E0720U) /**< \brief (UART) Transfer Control Register */
+#define REG_UART_PTSR          (0x400E0724U) /**< \brief (UART) Transfer Status Register */
+#else
+#define REG_UART_CR   (*(WoReg*)0x400E0600U) /**< \brief (UART) Control Register */
+#define REG_UART_MR   (*(RwReg*)0x400E0604U) /**< \brief (UART) Mode Register */
+#define REG_UART_IER  (*(WoReg*)0x400E0608U) /**< \brief (UART) Interrupt Enable Register */
+#define REG_UART_IDR  (*(WoReg*)0x400E060CU) /**< \brief (UART) Interrupt Disable Register */
+#define REG_UART_IMR  (*(RoReg*)0x400E0610U) /**< \brief (UART) Interrupt Mask Register */
+#define REG_UART_SR   (*(RoReg*)0x400E0614U) /**< \brief (UART) Status Register */
+#define REG_UART_RHR  (*(RoReg*)0x400E0618U) /**< \brief (UART) Receive Holding Register */
+#define REG_UART_THR  (*(WoReg*)0x400E061CU) /**< \brief (UART) Transmit Holding Register */
+#define REG_UART_BRGR (*(RwReg*)0x400E0620U) /**< \brief (UART) Baud Rate Generator Register */
+#define REG_UART_RPR  (*(RwReg*)0x400E0700U) /**< \brief (UART) Receive Pointer Register */
+#define REG_UART_RCR  (*(RwReg*)0x400E0704U) /**< \brief (UART) Receive Counter Register */
+#define REG_UART_TPR  (*(RwReg*)0x400E0708U) /**< \brief (UART) Transmit Pointer Register */
+#define REG_UART_TCR  (*(RwReg*)0x400E070CU) /**< \brief (UART) Transmit Counter Register */
+#define REG_UART_RNPR (*(RwReg*)0x400E0710U) /**< \brief (UART) Receive Next Pointer Register */
+#define REG_UART_RNCR (*(RwReg*)0x400E0714U) /**< \brief (UART) Receive Next Counter Register */
+#define REG_UART_TNPR (*(RwReg*)0x400E0718U) /**< \brief (UART) Transmit Next Pointer Register */
+#define REG_UART_TNCR (*(RwReg*)0x400E071CU) /**< \brief (UART) Transmit Next Counter Register */
+#define REG_UART_PTCR (*(WoReg*)0x400E0720U) /**< \brief (UART) Transfer Control Register */
+#define REG_UART_PTSR (*(RoReg*)0x400E0724U) /**< \brief (UART) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_UART_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_udphs.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_udphs.h
new file mode 100644
index 000000000..5b39da837
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_udphs.h
@@ -0,0 +1,204 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_UDPHS_INSTANCE_
+#define _SAM3U_UDPHS_INSTANCE_
+
+/* ========== Register definition for UDPHS peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_UDPHS_CTRL                 (0x400A4000U) /**< \brief (UDPHS) UDPHS Control Register */
+#define REG_UDPHS_FNUM                 (0x400A4004U) /**< \brief (UDPHS) UDPHS Frame Number Register */
+#define REG_UDPHS_IEN                  (0x400A4010U) /**< \brief (UDPHS) UDPHS Interrupt Enable Register */
+#define REG_UDPHS_INTSTA               (0x400A4014U) /**< \brief (UDPHS) UDPHS Interrupt Status Register */
+#define REG_UDPHS_CLRINT               (0x400A4018U) /**< \brief (UDPHS) UDPHS Clear Interrupt Register */
+#define REG_UDPHS_EPTRST               (0x400A401CU) /**< \brief (UDPHS) UDPHS Endpoints Reset Register */
+#define REG_UDPHS_TST                  (0x400A40E0U) /**< \brief (UDPHS) UDPHS Test Register */
+#define REG_UDPHS_IPNAME1              (0x400A40F0U) /**< \brief (UDPHS) UDPHS Name1 Register */
+#define REG_UDPHS_IPNAME2              (0x400A40F4U) /**< \brief (UDPHS) UDPHS Name2 Register */
+#define REG_UDPHS_IPFEATURES           (0x400A40F8U) /**< \brief (UDPHS) UDPHS Features Register */
+#define REG_UDPHS_EPTCFG0              (0x400A4100U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 0) */
+#define REG_UDPHS_EPTCTLENB0           (0x400A4104U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 0) */
+#define REG_UDPHS_EPTCTLDIS0           (0x400A4108U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 0) */
+#define REG_UDPHS_EPTCTL0              (0x400A410CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 0) */
+#define REG_UDPHS_EPTSETSTA0           (0x400A4114U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 0) */
+#define REG_UDPHS_EPTCLRSTA0           (0x400A4118U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 0) */
+#define REG_UDPHS_EPTSTA0              (0x400A411CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 0) */
+#define REG_UDPHS_EPTCFG1              (0x400A4120U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 1) */
+#define REG_UDPHS_EPTCTLENB1           (0x400A4124U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 1) */
+#define REG_UDPHS_EPTCTLDIS1           (0x400A4128U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 1) */
+#define REG_UDPHS_EPTCTL1              (0x400A412CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 1) */
+#define REG_UDPHS_EPTSETSTA1           (0x400A4134U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 1) */
+#define REG_UDPHS_EPTCLRSTA1           (0x400A4138U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 1) */
+#define REG_UDPHS_EPTSTA1              (0x400A413CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 1) */
+#define REG_UDPHS_EPTCFG2              (0x400A4140U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 2) */
+#define REG_UDPHS_EPTCTLENB2           (0x400A4144U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 2) */
+#define REG_UDPHS_EPTCTLDIS2           (0x400A4148U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 2) */
+#define REG_UDPHS_EPTCTL2              (0x400A414CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 2) */
+#define REG_UDPHS_EPTSETSTA2           (0x400A4154U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 2) */
+#define REG_UDPHS_EPTCLRSTA2           (0x400A4158U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 2) */
+#define REG_UDPHS_EPTSTA2              (0x400A415CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 2) */
+#define REG_UDPHS_EPTCFG3              (0x400A4160U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 3) */
+#define REG_UDPHS_EPTCTLENB3           (0x400A4164U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 3) */
+#define REG_UDPHS_EPTCTLDIS3           (0x400A4168U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 3) */
+#define REG_UDPHS_EPTCTL3              (0x400A416CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 3) */
+#define REG_UDPHS_EPTSETSTA3           (0x400A4174U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 3) */
+#define REG_UDPHS_EPTCLRSTA3           (0x400A4178U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 3) */
+#define REG_UDPHS_EPTSTA3              (0x400A417CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 3) */
+#define REG_UDPHS_EPTCFG4              (0x400A4180U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 4) */
+#define REG_UDPHS_EPTCTLENB4           (0x400A4184U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 4) */
+#define REG_UDPHS_EPTCTLDIS4           (0x400A4188U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 4) */
+#define REG_UDPHS_EPTCTL4              (0x400A418CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 4) */
+#define REG_UDPHS_EPTSETSTA4           (0x400A4194U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 4) */
+#define REG_UDPHS_EPTCLRSTA4           (0x400A4198U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 4) */
+#define REG_UDPHS_EPTSTA4              (0x400A419CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 4) */
+#define REG_UDPHS_EPTCFG5              (0x400A41A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 5) */
+#define REG_UDPHS_EPTCTLENB5           (0x400A41A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 5) */
+#define REG_UDPHS_EPTCTLDIS5           (0x400A41A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 5) */
+#define REG_UDPHS_EPTCTL5              (0x400A41ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 5) */
+#define REG_UDPHS_EPTSETSTA5           (0x400A41B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 5) */
+#define REG_UDPHS_EPTCLRSTA5           (0x400A41B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 5) */
+#define REG_UDPHS_EPTSTA5              (0x400A41BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 5) */
+#define REG_UDPHS_EPTCFG6              (0x400A41C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 6) */
+#define REG_UDPHS_EPTCTLENB6           (0x400A41C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 6) */
+#define REG_UDPHS_EPTCTLDIS6           (0x400A41C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 6) */
+#define REG_UDPHS_EPTCTL6              (0x400A41CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 6) */
+#define REG_UDPHS_EPTSETSTA6           (0x400A41D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 6) */
+#define REG_UDPHS_EPTCLRSTA6           (0x400A41D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 6) */
+#define REG_UDPHS_EPTSTA6              (0x400A41DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 6) */
+#define REG_UDPHS_DMANXTDSC0           (0x400A4300U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 0) */
+#define REG_UDPHS_DMAADDRESS0          (0x400A4304U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 0) */
+#define REG_UDPHS_DMACONTROL0          (0x400A4308U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 0) */
+#define REG_UDPHS_DMASTATUS0           (0x400A430CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 0) */
+#define REG_UDPHS_DMANXTDSC1           (0x400A4310U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 1) */
+#define REG_UDPHS_DMAADDRESS1          (0x400A4314U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 1) */
+#define REG_UDPHS_DMACONTROL1          (0x400A4318U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 1) */
+#define REG_UDPHS_DMASTATUS1           (0x400A431CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 1) */
+#define REG_UDPHS_DMANXTDSC2           (0x400A4320U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 2) */
+#define REG_UDPHS_DMAADDRESS2          (0x400A4324U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 2) */
+#define REG_UDPHS_DMACONTROL2          (0x400A4328U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 2) */
+#define REG_UDPHS_DMASTATUS2           (0x400A432CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 2) */
+#define REG_UDPHS_DMANXTDSC3           (0x400A4330U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 3) */
+#define REG_UDPHS_DMAADDRESS3          (0x400A4334U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 3) */
+#define REG_UDPHS_DMACONTROL3          (0x400A4338U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 3) */
+#define REG_UDPHS_DMASTATUS3           (0x400A433CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 3) */
+#define REG_UDPHS_DMANXTDSC4           (0x400A4340U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 4) */
+#define REG_UDPHS_DMAADDRESS4          (0x400A4344U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 4) */
+#define REG_UDPHS_DMACONTROL4          (0x400A4348U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 4) */
+#define REG_UDPHS_DMASTATUS4           (0x400A434CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 4) */
+#define REG_UDPHS_DMANXTDSC5           (0x400A4350U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 5) */
+#define REG_UDPHS_DMAADDRESS5          (0x400A4354U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 5) */
+#define REG_UDPHS_DMACONTROL5          (0x400A4358U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 5) */
+#define REG_UDPHS_DMASTATUS5           (0x400A435CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 5) */
+#else
+#define REG_UDPHS_CTRL        (*(RwReg*)0x400A4000U) /**< \brief (UDPHS) UDPHS Control Register */
+#define REG_UDPHS_FNUM        (*(RoReg*)0x400A4004U) /**< \brief (UDPHS) UDPHS Frame Number Register */
+#define REG_UDPHS_IEN         (*(RwReg*)0x400A4010U) /**< \brief (UDPHS) UDPHS Interrupt Enable Register */
+#define REG_UDPHS_INTSTA      (*(RoReg*)0x400A4014U) /**< \brief (UDPHS) UDPHS Interrupt Status Register */
+#define REG_UDPHS_CLRINT      (*(WoReg*)0x400A4018U) /**< \brief (UDPHS) UDPHS Clear Interrupt Register */
+#define REG_UDPHS_EPTRST      (*(WoReg*)0x400A401CU) /**< \brief (UDPHS) UDPHS Endpoints Reset Register */
+#define REG_UDPHS_TST         (*(RwReg*)0x400A40E0U) /**< \brief (UDPHS) UDPHS Test Register */
+#define REG_UDPHS_IPNAME1     (*(RoReg*)0x400A40F0U) /**< \brief (UDPHS) UDPHS Name1 Register */
+#define REG_UDPHS_IPNAME2     (*(RoReg*)0x400A40F4U) /**< \brief (UDPHS) UDPHS Name2 Register */
+#define REG_UDPHS_IPFEATURES  (*(RoReg*)0x400A40F8U) /**< \brief (UDPHS) UDPHS Features Register */
+#define REG_UDPHS_EPTCFG0     (*(RwReg*)0x400A4100U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 0) */
+#define REG_UDPHS_EPTCTLENB0  (*(WoReg*)0x400A4104U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 0) */
+#define REG_UDPHS_EPTCTLDIS0  (*(WoReg*)0x400A4108U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 0) */
+#define REG_UDPHS_EPTCTL0     (*(RoReg*)0x400A410CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 0) */
+#define REG_UDPHS_EPTSETSTA0  (*(WoReg*)0x400A4114U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 0) */
+#define REG_UDPHS_EPTCLRSTA0  (*(WoReg*)0x400A4118U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 0) */
+#define REG_UDPHS_EPTSTA0     (*(RoReg*)0x400A411CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 0) */
+#define REG_UDPHS_EPTCFG1     (*(RwReg*)0x400A4120U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 1) */
+#define REG_UDPHS_EPTCTLENB1  (*(WoReg*)0x400A4124U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 1) */
+#define REG_UDPHS_EPTCTLDIS1  (*(WoReg*)0x400A4128U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 1) */
+#define REG_UDPHS_EPTCTL1     (*(RoReg*)0x400A412CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 1) */
+#define REG_UDPHS_EPTSETSTA1  (*(WoReg*)0x400A4134U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 1) */
+#define REG_UDPHS_EPTCLRSTA1  (*(WoReg*)0x400A4138U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 1) */
+#define REG_UDPHS_EPTSTA1     (*(RoReg*)0x400A413CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 1) */
+#define REG_UDPHS_EPTCFG2     (*(RwReg*)0x400A4140U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 2) */
+#define REG_UDPHS_EPTCTLENB2  (*(WoReg*)0x400A4144U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 2) */
+#define REG_UDPHS_EPTCTLDIS2  (*(WoReg*)0x400A4148U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 2) */
+#define REG_UDPHS_EPTCTL2     (*(RoReg*)0x400A414CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 2) */
+#define REG_UDPHS_EPTSETSTA2  (*(WoReg*)0x400A4154U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 2) */
+#define REG_UDPHS_EPTCLRSTA2  (*(WoReg*)0x400A4158U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 2) */
+#define REG_UDPHS_EPTSTA2     (*(RoReg*)0x400A415CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 2) */
+#define REG_UDPHS_EPTCFG3     (*(RwReg*)0x400A4160U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 3) */
+#define REG_UDPHS_EPTCTLENB3  (*(WoReg*)0x400A4164U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 3) */
+#define REG_UDPHS_EPTCTLDIS3  (*(WoReg*)0x400A4168U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 3) */
+#define REG_UDPHS_EPTCTL3     (*(RoReg*)0x400A416CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 3) */
+#define REG_UDPHS_EPTSETSTA3  (*(WoReg*)0x400A4174U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 3) */
+#define REG_UDPHS_EPTCLRSTA3  (*(WoReg*)0x400A4178U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 3) */
+#define REG_UDPHS_EPTSTA3     (*(RoReg*)0x400A417CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 3) */
+#define REG_UDPHS_EPTCFG4     (*(RwReg*)0x400A4180U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 4) */
+#define REG_UDPHS_EPTCTLENB4  (*(WoReg*)0x400A4184U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 4) */
+#define REG_UDPHS_EPTCTLDIS4  (*(WoReg*)0x400A4188U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 4) */
+#define REG_UDPHS_EPTCTL4     (*(RoReg*)0x400A418CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 4) */
+#define REG_UDPHS_EPTSETSTA4  (*(WoReg*)0x400A4194U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 4) */
+#define REG_UDPHS_EPTCLRSTA4  (*(WoReg*)0x400A4198U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 4) */
+#define REG_UDPHS_EPTSTA4     (*(RoReg*)0x400A419CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 4) */
+#define REG_UDPHS_EPTCFG5     (*(RwReg*)0x400A41A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 5) */
+#define REG_UDPHS_EPTCTLENB5  (*(WoReg*)0x400A41A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 5) */
+#define REG_UDPHS_EPTCTLDIS5  (*(WoReg*)0x400A41A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 5) */
+#define REG_UDPHS_EPTCTL5     (*(RoReg*)0x400A41ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 5) */
+#define REG_UDPHS_EPTSETSTA5  (*(WoReg*)0x400A41B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 5) */
+#define REG_UDPHS_EPTCLRSTA5  (*(WoReg*)0x400A41B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 5) */
+#define REG_UDPHS_EPTSTA5     (*(RoReg*)0x400A41BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 5) */
+#define REG_UDPHS_EPTCFG6     (*(RwReg*)0x400A41C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 6) */
+#define REG_UDPHS_EPTCTLENB6  (*(WoReg*)0x400A41C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 6) */
+#define REG_UDPHS_EPTCTLDIS6  (*(WoReg*)0x400A41C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 6) */
+#define REG_UDPHS_EPTCTL6     (*(RoReg*)0x400A41CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 6) */
+#define REG_UDPHS_EPTSETSTA6  (*(WoReg*)0x400A41D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 6) */
+#define REG_UDPHS_EPTCLRSTA6  (*(WoReg*)0x400A41D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 6) */
+#define REG_UDPHS_EPTSTA6     (*(RoReg*)0x400A41DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 6) */
+#define REG_UDPHS_DMANXTDSC0  (*(RwReg*)0x400A4300U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 0) */
+#define REG_UDPHS_DMAADDRESS0 (*(RwReg*)0x400A4304U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 0) */
+#define REG_UDPHS_DMACONTROL0 (*(RwReg*)0x400A4308U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 0) */
+#define REG_UDPHS_DMASTATUS0  (*(RwReg*)0x400A430CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 0) */
+#define REG_UDPHS_DMANXTDSC1  (*(RwReg*)0x400A4310U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 1) */
+#define REG_UDPHS_DMAADDRESS1 (*(RwReg*)0x400A4314U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 1) */
+#define REG_UDPHS_DMACONTROL1 (*(RwReg*)0x400A4318U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 1) */
+#define REG_UDPHS_DMASTATUS1  (*(RwReg*)0x400A431CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 1) */
+#define REG_UDPHS_DMANXTDSC2  (*(RwReg*)0x400A4320U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 2) */
+#define REG_UDPHS_DMAADDRESS2 (*(RwReg*)0x400A4324U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 2) */
+#define REG_UDPHS_DMACONTROL2 (*(RwReg*)0x400A4328U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 2) */
+#define REG_UDPHS_DMASTATUS2  (*(RwReg*)0x400A432CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 2) */
+#define REG_UDPHS_DMANXTDSC3  (*(RwReg*)0x400A4330U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 3) */
+#define REG_UDPHS_DMAADDRESS3 (*(RwReg*)0x400A4334U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 3) */
+#define REG_UDPHS_DMACONTROL3 (*(RwReg*)0x400A4338U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 3) */
+#define REG_UDPHS_DMASTATUS3  (*(RwReg*)0x400A433CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 3) */
+#define REG_UDPHS_DMANXTDSC4  (*(RwReg*)0x400A4340U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 4) */
+#define REG_UDPHS_DMAADDRESS4 (*(RwReg*)0x400A4344U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 4) */
+#define REG_UDPHS_DMACONTROL4 (*(RwReg*)0x400A4348U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 4) */
+#define REG_UDPHS_DMASTATUS4  (*(RwReg*)0x400A434CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 4) */
+#define REG_UDPHS_DMANXTDSC5  (*(RwReg*)0x400A4350U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 5) */
+#define REG_UDPHS_DMAADDRESS5 (*(RwReg*)0x400A4354U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 5) */
+#define REG_UDPHS_DMACONTROL5 (*(RwReg*)0x400A4358U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 5) */
+#define REG_UDPHS_DMASTATUS5  (*(RwReg*)0x400A435CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 5) */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_UDPHS_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_usart0.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_usart0.h
new file mode 100644
index 000000000..67cda384d
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_usart0.h
@@ -0,0 +1,92 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_USART0_INSTANCE_
+#define _SAM3U_USART0_INSTANCE_
+
+/* ========== Register definition for USART0 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_USART0_CR          (0x40090000U) /**< \brief (USART0) Control Register */
+#define REG_USART0_MR          (0x40090004U) /**< \brief (USART0) Mode Register */
+#define REG_USART0_IER          (0x40090008U) /**< \brief (USART0) Interrupt Enable Register */
+#define REG_USART0_IDR          (0x4009000CU) /**< \brief (USART0) Interrupt Disable Register */
+#define REG_USART0_IMR          (0x40090010U) /**< \brief (USART0) Interrupt Mask Register */
+#define REG_USART0_CSR          (0x40090014U) /**< \brief (USART0) Channel Status Register */
+#define REG_USART0_RHR          (0x40090018U) /**< \brief (USART0) Receiver Holding Register */
+#define REG_USART0_THR          (0x4009001CU) /**< \brief (USART0) Transmitter Holding Register */
+#define REG_USART0_BRGR          (0x40090020U) /**< \brief (USART0) Baud Rate Generator Register */
+#define REG_USART0_RTOR          (0x40090024U) /**< \brief (USART0) Receiver Time-out Register */
+#define REG_USART0_TTGR          (0x40090028U) /**< \brief (USART0) Transmitter Timeguard Register */
+#define REG_USART0_FIDI          (0x40090040U) /**< \brief (USART0) FI DI Ratio Register */
+#define REG_USART0_NER          (0x40090044U) /**< \brief (USART0) Number of Errors Register */
+#define REG_USART0_IF          (0x4009004CU) /**< \brief (USART0) IrDA Filter Register */
+#define REG_USART0_MAN          (0x40090050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
+#define REG_USART0_WPMR          (0x400900E4U) /**< \brief (USART0) Write Protect Mode Register */
+#define REG_USART0_WPSR          (0x400900E8U) /**< \brief (USART0) Write Protect Status Register */
+#define REG_USART0_RPR          (0x40090100U) /**< \brief (USART0) Receive Pointer Register */
+#define REG_USART0_RCR          (0x40090104U) /**< \brief (USART0) Receive Counter Register */
+#define REG_USART0_TPR          (0x40090108U) /**< \brief (USART0) Transmit Pointer Register */
+#define REG_USART0_TCR          (0x4009010CU) /**< \brief (USART0) Transmit Counter Register */
+#define REG_USART0_RNPR          (0x40090110U) /**< \brief (USART0) Receive Next Pointer Register */
+#define REG_USART0_RNCR          (0x40090114U) /**< \brief (USART0) Receive Next Counter Register */
+#define REG_USART0_TNPR          (0x40090118U) /**< \brief (USART0) Transmit Next Pointer Register */
+#define REG_USART0_TNCR          (0x4009011CU) /**< \brief (USART0) Transmit Next Counter Register */
+#define REG_USART0_PTCR          (0x40090120U) /**< \brief (USART0) Transfer Control Register */
+#define REG_USART0_PTSR          (0x40090124U) /**< \brief (USART0) Transfer Status Register */
+#else
+#define REG_USART0_CR (*(WoReg*)0x40090000U) /**< \brief (USART0) Control Register */
+#define REG_USART0_MR (*(RwReg*)0x40090004U) /**< \brief (USART0) Mode Register */
+#define REG_USART0_IER (*(WoReg*)0x40090008U) /**< \brief (USART0) Interrupt Enable Register */
+#define REG_USART0_IDR (*(WoReg*)0x4009000CU) /**< \brief (USART0) Interrupt Disable Register */
+#define REG_USART0_IMR (*(RoReg*)0x40090010U) /**< \brief (USART0) Interrupt Mask Register */
+#define REG_USART0_CSR (*(RoReg*)0x40090014U) /**< \brief (USART0) Channel Status Register */
+#define REG_USART0_RHR (*(RoReg*)0x40090018U) /**< \brief (USART0) Receiver Holding Register */
+#define REG_USART0_THR (*(WoReg*)0x4009001CU) /**< \brief (USART0) Transmitter Holding Register */
+#define REG_USART0_BRGR (*(RwReg*)0x40090020U) /**< \brief (USART0) Baud Rate Generator Register */
+#define REG_USART0_RTOR (*(RwReg*)0x40090024U) /**< \brief (USART0) Receiver Time-out Register */
+#define REG_USART0_TTGR (*(RwReg*)0x40090028U) /**< \brief (USART0) Transmitter Timeguard Register */
+#define REG_USART0_FIDI (*(RwReg*)0x40090040U) /**< \brief (USART0) FI DI Ratio Register */
+#define REG_USART0_NER (*(RoReg*)0x40090044U) /**< \brief (USART0) Number of Errors Register */
+#define REG_USART0_IF (*(RwReg*)0x4009004CU) /**< \brief (USART0) IrDA Filter Register */
+#define REG_USART0_MAN (*(RwReg*)0x40090050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
+#define REG_USART0_WPMR (*(RwReg*)0x400900E4U) /**< \brief (USART0) Write Protect Mode Register */
+#define REG_USART0_WPSR (*(RoReg*)0x400900E8U) /**< \brief (USART0) Write Protect Status Register */
+#define REG_USART0_RPR (*(RwReg*)0x40090100U) /**< \brief (USART0) Receive Pointer Register */
+#define REG_USART0_RCR (*(RwReg*)0x40090104U) /**< \brief (USART0) Receive Counter Register */
+#define REG_USART0_TPR (*(RwReg*)0x40090108U) /**< \brief (USART0) Transmit Pointer Register */
+#define REG_USART0_TCR (*(RwReg*)0x4009010CU) /**< \brief (USART0) Transmit Counter Register */
+#define REG_USART0_RNPR (*(RwReg*)0x40090110U) /**< \brief (USART0) Receive Next Pointer Register */
+#define REG_USART0_RNCR (*(RwReg*)0x40090114U) /**< \brief (USART0) Receive Next Counter Register */
+#define REG_USART0_TNPR (*(RwReg*)0x40090118U) /**< \brief (USART0) Transmit Next Pointer Register */
+#define REG_USART0_TNCR (*(RwReg*)0x4009011CU) /**< \brief (USART0) Transmit Next Counter Register */
+#define REG_USART0_PTCR (*(WoReg*)0x40090120U) /**< \brief (USART0) Transfer Control Register */
+#define REG_USART0_PTSR (*(RoReg*)0x40090124U) /**< \brief (USART0) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_USART0_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_usart1.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_usart1.h
new file mode 100644
index 000000000..3cae30973
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_usart1.h
@@ -0,0 +1,92 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_USART1_INSTANCE_
+#define _SAM3U_USART1_INSTANCE_
+
+/* ========== Register definition for USART1 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_USART1_CR          (0x40094000U) /**< \brief (USART1) Control Register */
+#define REG_USART1_MR          (0x40094004U) /**< \brief (USART1) Mode Register */
+#define REG_USART1_IER          (0x40094008U) /**< \brief (USART1) Interrupt Enable Register */
+#define REG_USART1_IDR          (0x4009400CU) /**< \brief (USART1) Interrupt Disable Register */
+#define REG_USART1_IMR          (0x40094010U) /**< \brief (USART1) Interrupt Mask Register */
+#define REG_USART1_CSR          (0x40094014U) /**< \brief (USART1) Channel Status Register */
+#define REG_USART1_RHR          (0x40094018U) /**< \brief (USART1) Receiver Holding Register */
+#define REG_USART1_THR          (0x4009401CU) /**< \brief (USART1) Transmitter Holding Register */
+#define REG_USART1_BRGR          (0x40094020U) /**< \brief (USART1) Baud Rate Generator Register */
+#define REG_USART1_RTOR          (0x40094024U) /**< \brief (USART1) Receiver Time-out Register */
+#define REG_USART1_TTGR          (0x40094028U) /**< \brief (USART1) Transmitter Timeguard Register */
+#define REG_USART1_FIDI          (0x40094040U) /**< \brief (USART1) FI DI Ratio Register */
+#define REG_USART1_NER          (0x40094044U) /**< \brief (USART1) Number of Errors Register */
+#define REG_USART1_IF          (0x4009404CU) /**< \brief (USART1) IrDA Filter Register */
+#define REG_USART1_MAN          (0x40094050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
+#define REG_USART1_WPMR          (0x400940E4U) /**< \brief (USART1) Write Protect Mode Register */
+#define REG_USART1_WPSR          (0x400940E8U) /**< \brief (USART1) Write Protect Status Register */
+#define REG_USART1_RPR          (0x40094100U) /**< \brief (USART1) Receive Pointer Register */
+#define REG_USART1_RCR          (0x40094104U) /**< \brief (USART1) Receive Counter Register */
+#define REG_USART1_TPR          (0x40094108U) /**< \brief (USART1) Transmit Pointer Register */
+#define REG_USART1_TCR          (0x4009410CU) /**< \brief (USART1) Transmit Counter Register */
+#define REG_USART1_RNPR          (0x40094110U) /**< \brief (USART1) Receive Next Pointer Register */
+#define REG_USART1_RNCR          (0x40094114U) /**< \brief (USART1) Receive Next Counter Register */
+#define REG_USART1_TNPR          (0x40094118U) /**< \brief (USART1) Transmit Next Pointer Register */
+#define REG_USART1_TNCR          (0x4009411CU) /**< \brief (USART1) Transmit Next Counter Register */
+#define REG_USART1_PTCR          (0x40094120U) /**< \brief (USART1) Transfer Control Register */
+#define REG_USART1_PTSR          (0x40094124U) /**< \brief (USART1) Transfer Status Register */
+#else
+#define REG_USART1_CR (*(WoReg*)0x40094000U) /**< \brief (USART1) Control Register */
+#define REG_USART1_MR (*(RwReg*)0x40094004U) /**< \brief (USART1) Mode Register */
+#define REG_USART1_IER (*(WoReg*)0x40094008U) /**< \brief (USART1) Interrupt Enable Register */
+#define REG_USART1_IDR (*(WoReg*)0x4009400CU) /**< \brief (USART1) Interrupt Disable Register */
+#define REG_USART1_IMR (*(RoReg*)0x40094010U) /**< \brief (USART1) Interrupt Mask Register */
+#define REG_USART1_CSR (*(RoReg*)0x40094014U) /**< \brief (USART1) Channel Status Register */
+#define REG_USART1_RHR (*(RoReg*)0x40094018U) /**< \brief (USART1) Receiver Holding Register */
+#define REG_USART1_THR (*(WoReg*)0x4009401CU) /**< \brief (USART1) Transmitter Holding Register */
+#define REG_USART1_BRGR (*(RwReg*)0x40094020U) /**< \brief (USART1) Baud Rate Generator Register */
+#define REG_USART1_RTOR (*(RwReg*)0x40094024U) /**< \brief (USART1) Receiver Time-out Register */
+#define REG_USART1_TTGR (*(RwReg*)0x40094028U) /**< \brief (USART1) Transmitter Timeguard Register */
+#define REG_USART1_FIDI (*(RwReg*)0x40094040U) /**< \brief (USART1) FI DI Ratio Register */
+#define REG_USART1_NER (*(RoReg*)0x40094044U) /**< \brief (USART1) Number of Errors Register */
+#define REG_USART1_IF (*(RwReg*)0x4009404CU) /**< \brief (USART1) IrDA Filter Register */
+#define REG_USART1_MAN (*(RwReg*)0x40094050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
+#define REG_USART1_WPMR (*(RwReg*)0x400940E4U) /**< \brief (USART1) Write Protect Mode Register */
+#define REG_USART1_WPSR (*(RoReg*)0x400940E8U) /**< \brief (USART1) Write Protect Status Register */
+#define REG_USART1_RPR (*(RwReg*)0x40094100U) /**< \brief (USART1) Receive Pointer Register */
+#define REG_USART1_RCR (*(RwReg*)0x40094104U) /**< \brief (USART1) Receive Counter Register */
+#define REG_USART1_TPR (*(RwReg*)0x40094108U) /**< \brief (USART1) Transmit Pointer Register */
+#define REG_USART1_TCR (*(RwReg*)0x4009410CU) /**< \brief (USART1) Transmit Counter Register */
+#define REG_USART1_RNPR (*(RwReg*)0x40094110U) /**< \brief (USART1) Receive Next Pointer Register */
+#define REG_USART1_RNCR (*(RwReg*)0x40094114U) /**< \brief (USART1) Receive Next Counter Register */
+#define REG_USART1_TNPR (*(RwReg*)0x40094118U) /**< \brief (USART1) Transmit Next Pointer Register */
+#define REG_USART1_TNCR (*(RwReg*)0x4009411CU) /**< \brief (USART1) Transmit Next Counter Register */
+#define REG_USART1_PTCR (*(WoReg*)0x40094120U) /**< \brief (USART1) Transfer Control Register */
+#define REG_USART1_PTSR (*(RoReg*)0x40094124U) /**< \brief (USART1) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_USART1_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_usart2.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_usart2.h
new file mode 100644
index 000000000..02717fa03
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_usart2.h
@@ -0,0 +1,92 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_USART2_INSTANCE_
+#define _SAM3U_USART2_INSTANCE_
+
+/* ========== Register definition for USART2 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_USART2_CR          (0x40098000U) /**< \brief (USART2) Control Register */
+#define REG_USART2_MR          (0x40098004U) /**< \brief (USART2) Mode Register */
+#define REG_USART2_IER          (0x40098008U) /**< \brief (USART2) Interrupt Enable Register */
+#define REG_USART2_IDR          (0x4009800CU) /**< \brief (USART2) Interrupt Disable Register */
+#define REG_USART2_IMR          (0x40098010U) /**< \brief (USART2) Interrupt Mask Register */
+#define REG_USART2_CSR          (0x40098014U) /**< \brief (USART2) Channel Status Register */
+#define REG_USART2_RHR          (0x40098018U) /**< \brief (USART2) Receiver Holding Register */
+#define REG_USART2_THR          (0x4009801CU) /**< \brief (USART2) Transmitter Holding Register */
+#define REG_USART2_BRGR          (0x40098020U) /**< \brief (USART2) Baud Rate Generator Register */
+#define REG_USART2_RTOR          (0x40098024U) /**< \brief (USART2) Receiver Time-out Register */
+#define REG_USART2_TTGR          (0x40098028U) /**< \brief (USART2) Transmitter Timeguard Register */
+#define REG_USART2_FIDI          (0x40098040U) /**< \brief (USART2) FI DI Ratio Register */
+#define REG_USART2_NER          (0x40098044U) /**< \brief (USART2) Number of Errors Register */
+#define REG_USART2_IF          (0x4009804CU) /**< \brief (USART2) IrDA Filter Register */
+#define REG_USART2_MAN          (0x40098050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
+#define REG_USART2_WPMR          (0x400980E4U) /**< \brief (USART2) Write Protect Mode Register */
+#define REG_USART2_WPSR          (0x400980E8U) /**< \brief (USART2) Write Protect Status Register */
+#define REG_USART2_RPR          (0x40098100U) /**< \brief (USART2) Receive Pointer Register */
+#define REG_USART2_RCR          (0x40098104U) /**< \brief (USART2) Receive Counter Register */
+#define REG_USART2_TPR          (0x40098108U) /**< \brief (USART2) Transmit Pointer Register */
+#define REG_USART2_TCR          (0x4009810CU) /**< \brief (USART2) Transmit Counter Register */
+#define REG_USART2_RNPR          (0x40098110U) /**< \brief (USART2) Receive Next Pointer Register */
+#define REG_USART2_RNCR          (0x40098114U) /**< \brief (USART2) Receive Next Counter Register */
+#define REG_USART2_TNPR          (0x40098118U) /**< \brief (USART2) Transmit Next Pointer Register */
+#define REG_USART2_TNCR          (0x4009811CU) /**< \brief (USART2) Transmit Next Counter Register */
+#define REG_USART2_PTCR          (0x40098120U) /**< \brief (USART2) Transfer Control Register */
+#define REG_USART2_PTSR          (0x40098124U) /**< \brief (USART2) Transfer Status Register */
+#else
+#define REG_USART2_CR (*(WoReg*)0x40098000U) /**< \brief (USART2) Control Register */
+#define REG_USART2_MR (*(RwReg*)0x40098004U) /**< \brief (USART2) Mode Register */
+#define REG_USART2_IER (*(WoReg*)0x40098008U) /**< \brief (USART2) Interrupt Enable Register */
+#define REG_USART2_IDR (*(WoReg*)0x4009800CU) /**< \brief (USART2) Interrupt Disable Register */
+#define REG_USART2_IMR (*(RoReg*)0x40098010U) /**< \brief (USART2) Interrupt Mask Register */
+#define REG_USART2_CSR (*(RoReg*)0x40098014U) /**< \brief (USART2) Channel Status Register */
+#define REG_USART2_RHR (*(RoReg*)0x40098018U) /**< \brief (USART2) Receiver Holding Register */
+#define REG_USART2_THR (*(WoReg*)0x4009801CU) /**< \brief (USART2) Transmitter Holding Register */
+#define REG_USART2_BRGR (*(RwReg*)0x40098020U) /**< \brief (USART2) Baud Rate Generator Register */
+#define REG_USART2_RTOR (*(RwReg*)0x40098024U) /**< \brief (USART2) Receiver Time-out Register */
+#define REG_USART2_TTGR (*(RwReg*)0x40098028U) /**< \brief (USART2) Transmitter Timeguard Register */
+#define REG_USART2_FIDI (*(RwReg*)0x40098040U) /**< \brief (USART2) FI DI Ratio Register */
+#define REG_USART2_NER (*(RoReg*)0x40098044U) /**< \brief (USART2) Number of Errors Register */
+#define REG_USART2_IF (*(RwReg*)0x4009804CU) /**< \brief (USART2) IrDA Filter Register */
+#define REG_USART2_MAN (*(RwReg*)0x40098050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
+#define REG_USART2_WPMR (*(RwReg*)0x400980E4U) /**< \brief (USART2) Write Protect Mode Register */
+#define REG_USART2_WPSR (*(RoReg*)0x400980E8U) /**< \brief (USART2) Write Protect Status Register */
+#define REG_USART2_RPR (*(RwReg*)0x40098100U) /**< \brief (USART2) Receive Pointer Register */
+#define REG_USART2_RCR (*(RwReg*)0x40098104U) /**< \brief (USART2) Receive Counter Register */
+#define REG_USART2_TPR (*(RwReg*)0x40098108U) /**< \brief (USART2) Transmit Pointer Register */
+#define REG_USART2_TCR (*(RwReg*)0x4009810CU) /**< \brief (USART2) Transmit Counter Register */
+#define REG_USART2_RNPR (*(RwReg*)0x40098110U) /**< \brief (USART2) Receive Next Pointer Register */
+#define REG_USART2_RNCR (*(RwReg*)0x40098114U) /**< \brief (USART2) Receive Next Counter Register */
+#define REG_USART2_TNPR (*(RwReg*)0x40098118U) /**< \brief (USART2) Transmit Next Pointer Register */
+#define REG_USART2_TNCR (*(RwReg*)0x4009811CU) /**< \brief (USART2) Transmit Next Counter Register */
+#define REG_USART2_PTCR (*(WoReg*)0x40098120U) /**< \brief (USART2) Transfer Control Register */
+#define REG_USART2_PTSR (*(RoReg*)0x40098124U) /**< \brief (USART2) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_USART2_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_usart3.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_usart3.h
new file mode 100644
index 000000000..363d309b4
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_usart3.h
@@ -0,0 +1,92 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_USART3_INSTANCE_
+#define _SAM3U_USART3_INSTANCE_
+
+/* ========== Register definition for USART3 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_USART3_CR          (0x4009C000U) /**< \brief (USART3) Control Register */
+#define REG_USART3_MR          (0x4009C004U) /**< \brief (USART3) Mode Register */
+#define REG_USART3_IER          (0x4009C008U) /**< \brief (USART3) Interrupt Enable Register */
+#define REG_USART3_IDR          (0x4009C00CU) /**< \brief (USART3) Interrupt Disable Register */
+#define REG_USART3_IMR          (0x4009C010U) /**< \brief (USART3) Interrupt Mask Register */
+#define REG_USART3_CSR          (0x4009C014U) /**< \brief (USART3) Channel Status Register */
+#define REG_USART3_RHR          (0x4009C018U) /**< \brief (USART3) Receiver Holding Register */
+#define REG_USART3_THR          (0x4009C01CU) /**< \brief (USART3) Transmitter Holding Register */
+#define REG_USART3_BRGR          (0x4009C020U) /**< \brief (USART3) Baud Rate Generator Register */
+#define REG_USART3_RTOR          (0x4009C024U) /**< \brief (USART3) Receiver Time-out Register */
+#define REG_USART3_TTGR          (0x4009C028U) /**< \brief (USART3) Transmitter Timeguard Register */
+#define REG_USART3_FIDI          (0x4009C040U) /**< \brief (USART3) FI DI Ratio Register */
+#define REG_USART3_NER          (0x4009C044U) /**< \brief (USART3) Number of Errors Register */
+#define REG_USART3_IF          (0x4009C04CU) /**< \brief (USART3) IrDA Filter Register */
+#define REG_USART3_MAN          (0x4009C050U) /**< \brief (USART3) Manchester Encoder Decoder Register */
+#define REG_USART3_WPMR          (0x4009C0E4U) /**< \brief (USART3) Write Protect Mode Register */
+#define REG_USART3_WPSR          (0x4009C0E8U) /**< \brief (USART3) Write Protect Status Register */
+#define REG_USART3_RPR          (0x4009C100U) /**< \brief (USART3) Receive Pointer Register */
+#define REG_USART3_RCR          (0x4009C104U) /**< \brief (USART3) Receive Counter Register */
+#define REG_USART3_TPR          (0x4009C108U) /**< \brief (USART3) Transmit Pointer Register */
+#define REG_USART3_TCR          (0x4009C10CU) /**< \brief (USART3) Transmit Counter Register */
+#define REG_USART3_RNPR          (0x4009C110U) /**< \brief (USART3) Receive Next Pointer Register */
+#define REG_USART3_RNCR          (0x4009C114U) /**< \brief (USART3) Receive Next Counter Register */
+#define REG_USART3_TNPR          (0x4009C118U) /**< \brief (USART3) Transmit Next Pointer Register */
+#define REG_USART3_TNCR          (0x4009C11CU) /**< \brief (USART3) Transmit Next Counter Register */
+#define REG_USART3_PTCR          (0x4009C120U) /**< \brief (USART3) Transfer Control Register */
+#define REG_USART3_PTSR          (0x4009C124U) /**< \brief (USART3) Transfer Status Register */
+#else
+#define REG_USART3_CR (*(WoReg*)0x4009C000U) /**< \brief (USART3) Control Register */
+#define REG_USART3_MR (*(RwReg*)0x4009C004U) /**< \brief (USART3) Mode Register */
+#define REG_USART3_IER (*(WoReg*)0x4009C008U) /**< \brief (USART3) Interrupt Enable Register */
+#define REG_USART3_IDR (*(WoReg*)0x4009C00CU) /**< \brief (USART3) Interrupt Disable Register */
+#define REG_USART3_IMR (*(RoReg*)0x4009C010U) /**< \brief (USART3) Interrupt Mask Register */
+#define REG_USART3_CSR (*(RoReg*)0x4009C014U) /**< \brief (USART3) Channel Status Register */
+#define REG_USART3_RHR (*(RoReg*)0x4009C018U) /**< \brief (USART3) Receiver Holding Register */
+#define REG_USART3_THR (*(WoReg*)0x4009C01CU) /**< \brief (USART3) Transmitter Holding Register */
+#define REG_USART3_BRGR (*(RwReg*)0x4009C020U) /**< \brief (USART3) Baud Rate Generator Register */
+#define REG_USART3_RTOR (*(RwReg*)0x4009C024U) /**< \brief (USART3) Receiver Time-out Register */
+#define REG_USART3_TTGR (*(RwReg*)0x4009C028U) /**< \brief (USART3) Transmitter Timeguard Register */
+#define REG_USART3_FIDI (*(RwReg*)0x4009C040U) /**< \brief (USART3) FI DI Ratio Register */
+#define REG_USART3_NER (*(RoReg*)0x4009C044U) /**< \brief (USART3) Number of Errors Register */
+#define REG_USART3_IF (*(RwReg*)0x4009C04CU) /**< \brief (USART3) IrDA Filter Register */
+#define REG_USART3_MAN (*(RwReg*)0x4009C050U) /**< \brief (USART3) Manchester Encoder Decoder Register */
+#define REG_USART3_WPMR (*(RwReg*)0x4009C0E4U) /**< \brief (USART3) Write Protect Mode Register */
+#define REG_USART3_WPSR (*(RoReg*)0x4009C0E8U) /**< \brief (USART3) Write Protect Status Register */
+#define REG_USART3_RPR (*(RwReg*)0x4009C100U) /**< \brief (USART3) Receive Pointer Register */
+#define REG_USART3_RCR (*(RwReg*)0x4009C104U) /**< \brief (USART3) Receive Counter Register */
+#define REG_USART3_TPR (*(RwReg*)0x4009C108U) /**< \brief (USART3) Transmit Pointer Register */
+#define REG_USART3_TCR (*(RwReg*)0x4009C10CU) /**< \brief (USART3) Transmit Counter Register */
+#define REG_USART3_RNPR (*(RwReg*)0x4009C110U) /**< \brief (USART3) Receive Next Pointer Register */
+#define REG_USART3_RNCR (*(RwReg*)0x4009C114U) /**< \brief (USART3) Receive Next Counter Register */
+#define REG_USART3_TNPR (*(RwReg*)0x4009C118U) /**< \brief (USART3) Transmit Next Pointer Register */
+#define REG_USART3_TNCR (*(RwReg*)0x4009C11CU) /**< \brief (USART3) Transmit Next Counter Register */
+#define REG_USART3_PTCR (*(WoReg*)0x4009C120U) /**< \brief (USART3) Transfer Control Register */
+#define REG_USART3_PTSR (*(RoReg*)0x4009C124U) /**< \brief (USART3) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_USART3_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_wdt.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_wdt.h
new file mode 100644
index 000000000..f17439520
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/instance_wdt.h
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_WDT_INSTANCE_
+#define _SAM3U_WDT_INSTANCE_
+
+/* ========== Register definition for WDT peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_WDT_CR          (0x400E1250U) /**< \brief (WDT) Control Register */
+#define REG_WDT_MR          (0x400E1254U) /**< \brief (WDT) Mode Register */
+#define REG_WDT_SR          (0x400E1258U) /**< \brief (WDT) Status Register */
+#else
+#define REG_WDT_CR (*(WoReg*)0x400E1250U) /**< \brief (WDT) Control Register */
+#define REG_WDT_MR (*(RwReg*)0x400E1254U) /**< \brief (WDT) Mode Register */
+#define REG_WDT_SR (*(RoReg*)0x400E1258U) /**< \brief (WDT) Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3U_WDT_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/pio/pio_sam3u1c.h b/hardware/sam/system/libsam/cmsis/sam3u/include/pio/pio_sam3u1c.h
new file mode 100644
index 000000000..d1a0dea87
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/pio/pio_sam3u1c.h
@@ -0,0 +1,356 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U1C_PIO_
+#define _SAM3U1C_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15          (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16          (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17          (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18          (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19          (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20          (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21          (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22          (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23          (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24          (1u << 24) /**< \brief Pin Controlled by PB24 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PB5X1_AD0     (1u << 5)  /**< \brief Adc signal: AD0 */
+#define PIO_PB6X1_AD1     (1u << 6)  /**< \brief Adc signal: AD1 */
+#define PIO_PB7X1_AD2     (1u << 7)  /**< \brief Adc signal: AD2 */
+#define PIO_PB8X1_AD3     (1u << 8)  /**< \brief Adc signal: AD3 */
+#define PIO_PC28X1_AD4    (1u << 28) /**< \brief Adc signal: AD4 */
+#define PIO_PC29X1_AD5    (1u << 29) /**< \brief Adc signal: AD5 */
+#define PIO_PC30X1_AD6    (1u << 30) /**< \brief Adc signal: AD6 */
+#define PIO_PC31X1_AD7    (1u << 31) /**< \brief Adc signal: AD7 */
+#define PIO_PA17B_ADTRG   (1u << 17) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for ADC12B peripheral ========== */
+#define PIO_PA22X1_AD12B0 (1u << 22) /**< \brief Adc12b signal: AD12B0 */
+#define PIO_PA30X1_AD12B1 (1u << 30) /**< \brief Adc12b signal: AD12B1 */
+#define PIO_PB3X1_AD12B2  (1u << 3)  /**< \brief Adc12b signal: AD12B2 */
+#define PIO_PB4X1_AD12B3  (1u << 4)  /**< \brief Adc12b signal: AD12B3 */
+#define PIO_PC15X1_AD12B4 (1u << 15) /**< \brief Adc12b signal: AD12B4 */
+#define PIO_PC16X1_AD12B5 (1u << 16) /**< \brief Adc12b signal: AD12B5 */
+#define PIO_PC17X1_AD12B6 (1u << 17) /**< \brief Adc12b signal: AD12B6 */
+#define PIO_PC18X1_AD12B7 (1u << 18) /**< \brief Adc12b signal: AD12B7 */
+#define PIO_PA2B_AD12BTRG (1u << 2)  /**< \brief Adc12b signal: AD12BTRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PB7B_A0       (1u << 7)  /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PB7B_NBS0     (1u << 7)  /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PB8B_A1       (1u << 8)  /**< \brief Ebi signal: A1 */
+#define PIO_PC8A_A10      (1u << 8)  /**< \brief Ebi signal: A10 */
+#define PIO_PC9A_A11      (1u << 9)  /**< \brief Ebi signal: A11 */
+#define PIO_PC10A_A12     (1u << 10) /**< \brief Ebi signal: A12 */
+#define PIO_PC11A_A13     (1u << 11) /**< \brief Ebi signal: A13 */
+#define PIO_PC20A_A14     (1u << 20) /**< \brief Ebi signal: A14 */
+#define PIO_PC21A_A15     (1u << 21) /**< \brief Ebi signal: A15 */
+#define PIO_PC22A_A16     (1u << 22) /**< \brief Ebi signal: A16 */
+#define PIO_PC23A_A17     (1u << 23) /**< \brief Ebi signal: A17 */
+#define PIO_PC24A_A18     (1u << 24) /**< \brief Ebi signal: A18 */
+#define PIO_PC25A_A19     (1u << 25) /**< \brief Ebi signal: A19 */
+#define PIO_PB0B_A2       (1u << 0)  /**< \brief Ebi signal: A2 */
+#define PIO_PC0A_A2       (1u << 0)  /**< \brief Ebi signal: A2 */
+#define PIO_PC13A_A2      (1u << 13) /**< \brief Ebi signal: A2 */
+#define PIO_PC26A_A20     (1u << 26) /**< \brief Ebi signal: A20 */
+#define PIO_PB21A_A21     (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PB21A_NANDALE (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PB22A_A22     (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PB22A_NANDCLE (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PC27A_A23     (1u << 27) /**< \brief Ebi signal: A23 */
+#define PIO_PB1B_A3       (1u << 1)  /**< \brief Ebi signal: A3 */
+#define PIO_PC1A_A3       (1u << 1)  /**< \brief Ebi signal: A3 */
+#define PIO_PC14A_A3      (1u << 14) /**< \brief Ebi signal: A3 */
+#define PIO_PB2B_A4       (1u << 2)  /**< \brief Ebi signal: A4 */
+#define PIO_PC2A_A4       (1u << 2)  /**< \brief Ebi signal: A4 */
+#define PIO_PB3B_A5       (1u << 3)  /**< \brief Ebi signal: A5 */
+#define PIO_PC3A_A5       (1u << 3)  /**< \brief Ebi signal: A5 */
+#define PIO_PB4B_A6       (1u << 4)  /**< \brief Ebi signal: A6 */
+#define PIO_PC4A_A6       (1u << 4)  /**< \brief Ebi signal: A6 */
+#define PIO_PB5B_A7       (1u << 5)  /**< \brief Ebi signal: A7 */
+#define PIO_PC5A_A7       (1u << 5)  /**< \brief Ebi signal: A7 */
+#define PIO_PC6A_A8       (1u << 6)  /**< \brief Ebi signal: A8 */
+#define PIO_PC7A_A9       (1u << 7)  /**< \brief Ebi signal: A9 */
+#define PIO_PB9A_D0       (1u << 9)  /**< \brief Ebi signal: D0 */
+#define PIO_PB10A_D1      (1u << 10) /**< \brief Ebi signal: D1 */
+#define PIO_PB27A_D10     (1u << 27) /**< \brief Ebi signal: D10 */
+#define PIO_PB28A_D11     (1u << 28) /**< \brief Ebi signal: D11 */
+#define PIO_PB29A_D12     (1u << 29) /**< \brief Ebi signal: D12 */
+#define PIO_PB30A_D13     (1u << 30) /**< \brief Ebi signal: D13 */
+#define PIO_PB31A_D14     (1u << 31) /**< \brief Ebi signal: D14 */
+#define PIO_PB6B_D15      (1u << 6)  /**< \brief Ebi signal: D15 */
+#define PIO_PB11A_D2      (1u << 11) /**< \brief Ebi signal: D2 */
+#define PIO_PB12A_D3      (1u << 12) /**< \brief Ebi signal: D3 */
+#define PIO_PB13A_D4      (1u << 13) /**< \brief Ebi signal: D4 */
+#define PIO_PB14A_D5      (1u << 14) /**< \brief Ebi signal: D5 */
+#define PIO_PB15A_D6      (1u << 15) /**< \brief Ebi signal: D6 */
+#define PIO_PB16A_D7      (1u << 16) /**< \brief Ebi signal: D7 */
+#define PIO_PB25A_D8      (1u << 25) /**< \brief Ebi signal: D8 */
+#define PIO_PB26A_D9      (1u << 26) /**< \brief Ebi signal: D9 */
+#define PIO_PB17A_NANDOE  (1u << 17) /**< \brief Ebi signal: NANDOE */
+#define PIO_PB24A_NANDRDY (1u << 24) /**< \brief Ebi signal: NANDRDY */
+#define PIO_PB18A_NANDWE  (1u << 18) /**< \brief Ebi signal: NANDWE */
+#define PIO_PB20A_NCS0    (1u << 20) /**< \brief Ebi signal: NCS0 */
+#define PIO_PA16B_NCS1    (1u << 16) /**< \brief Ebi signal: NCS1 */
+#define PIO_PC12A_NCS1    (1u << 12) /**< \brief Ebi signal: NCS1 */
+#define PIO_PC16A_NCS2    (1u << 16) /**< \brief Ebi signal: NCS2 */
+#define PIO_PC17A_NCS3    (1u << 17) /**< \brief Ebi signal: NCS3 */
+#define PIO_PB19A_NRD     (1u << 19) /**< \brief Ebi signal: NRD */
+#define PIO_PC18A_NWAIT   (1u << 18) /**< \brief Ebi signal: NWAIT */
+#define PIO_PB23A_NWR0    (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PB23A_NWE     (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PC15A_NWR1    (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
+#define PIO_PC15A_NBS1    (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA4A_MCCDA    (1u << 4)  /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA3A_MCCK     (1u << 3)  /**< \brief Hsmci signal: MCCK */
+#define PIO_PA5A_MCDA0    (1u << 5)  /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA6A_MCDA1    (1u << 6)  /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA7A_MCDA2    (1u << 7)  /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA8A_MCDA3    (1u << 8)  /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PC28B_MCDA4   (1u << 28) /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PC29B_MCDA5   (1u << 29) /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PC30B_MCDA6   (1u << 30) /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PC31B_MCDA7   (1u << 31) /**< \brief Hsmci signal: MCDA7 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA21B_PCK0    (1u << 21) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA27B_PCK0    (1u << 27) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA3B_PCK1     (1u << 3)  /**< \brief Pmc signal: PCK1 */
+#define PIO_PB24B_PCK1    (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PB23B_PCK2    (1u << 23) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA11B_PWMFI0  (1u << 11) /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA12B_PWMFI1  (1u << 12) /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PA18B_PWMFI2  (1u << 18) /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA4B_PWMH0    (1u << 4)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA28B_PWMH0   (1u << 28) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0    (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB13B_PWMH0   (1u << 13) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC24B_PWMH0   (1u << 24) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA5B_PWMH1    (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA29B_PWMH1   (1u << 29) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1    (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB14B_PWMH1   (1u << 14) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC25B_PWMH1   (1u << 25) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA6B_PWMH2    (1u << 6)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA15B_PWMH2   (1u << 15) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB2A_PWMH2    (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB15B_PWMH2   (1u << 15) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC26B_PWMH2   (1u << 26) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA20B_PWMH3   (1u << 20) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB3A_PWMH3    (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB16B_PWMH3   (1u << 16) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC27B_PWMH3   (1u << 27) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA7B_PWML0    (1u << 7)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PB17B_PWML0   (1u << 17) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB25B_PWML0   (1u << 25) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC6B_PWML0    (1u << 6)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC29A_PWML0   (1u << 29) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA8B_PWML1    (1u << 8)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PB18B_PWML1   (1u << 18) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB26B_PWML1   (1u << 26) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC7B_PWML1    (1u << 7)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC30A_PWML1   (1u << 30) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA9B_PWML2    (1u << 9)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PB19B_PWML2   (1u << 19) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB27B_PWML2   (1u << 27) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC8B_PWML2    (1u << 8)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PC31A_PWML2   (1u << 31) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA10B_PWML3   (1u << 10) /**< \brief Pwm signal: PWML3 */
+#define PIO_PB20B_PWML3   (1u << 20) /**< \brief Pwm signal: PWML3 */
+#define PIO_PB28B_PWML3   (1u << 28) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC9B_PWML3    (1u << 9)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC16B_PWML3   (1u << 16) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA13A_MISO    (1u << 13) /**< \brief Spi signal: MISO */
+#define PIO_PA14A_MOSI    (1u << 14) /**< \brief Spi signal: MOSI */
+#define PIO_PA16A_NPCS0   (1u << 16) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA0B_NPCS1    (1u << 0)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PC3B_NPCS1    (1u << 3)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PC19B_NPCS1   (1u << 19) /**< \brief Spi signal: NPCS1 */
+#define PIO_PA1B_NPCS2    (1u << 1)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC4B_NPCS2    (1u << 4)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC14B_NPCS2   (1u << 14) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA19B_NPCS3   (1u << 19) /**< \brief Spi signal: NPCS3 */
+#define PIO_PC5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA15A_SPCK    (1u << 15) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA27A_RD      (1u << 27) /**< \brief Ssc signal: RD */
+#define PIO_PA31A_RF      (1u << 31) /**< \brief Ssc signal: RF */
+#define PIO_PA29A_RK      (1u << 29) /**< \brief Ssc signal: RK */
+#define PIO_PA26A_TD      (1u << 26) /**< \brief Ssc signal: TD */
+#define PIO_PA30A_TF      (1u << 30) /**< \brief Ssc signal: TF */
+#define PIO_PA28A_TK      (1u << 28) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA2A_TCLK0    (1u << 2)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PB4A_TCLK1    (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA26B_TCLK2   (1u << 26) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA1A_TIOA0    (1u << 1)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PB5A_TIOA1    (1u << 5)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA30B_TIOA2   (1u << 30) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA0A_TIOB0    (1u << 0)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PB6A_TIOB1    (1u << 6)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA31B_TIOB2   (1u << 31) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA10A_TWCK0   (1u << 10) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA9A_TWD0     (1u << 9)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PA25A_TWCK1   (1u << 25) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PA24A_TWD1    (1u << 24) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA11A_URXD    (1u << 11) /**< \brief Uart signal: URXD */
+#define PIO_PA12A_UTXD    (1u << 12) /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB11B_DCD0    (1u << 11) /**< \brief Usart0 signal: DCD0 */
+#define PIO_PB10B_DSR0    (1u << 10) /**< \brief Usart0 signal: DSR0 */
+#define PIO_PB9B_DTR0     (1u << 9)  /**< \brief Usart0 signal: DTR0 */
+#define PIO_PB12B_RI0     (1u << 12) /**< \brief Usart0 signal: RI0 */
+#define PIO_PB7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA19A_RXD0    (1u << 19) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17A_SCK0    (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA18A_TXD0    (1u << 18) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA23B_CTS1    (1u << 23) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA22B_RTS1    (1u << 22) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA24B_SCK1    (1u << 24) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA20A_TXD1    (1u << 20) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB22B_CTS2    (1u << 22) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB21B_RTS2    (1u << 21) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PA23A_RXD2    (1u << 23) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PA25B_SCK2    (1u << 25) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PA22A_TXD2    (1u << 22) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+#define PIO_PB15_IDX      47
+#define PIO_PB16_IDX      48
+#define PIO_PB17_IDX      49
+#define PIO_PB18_IDX      50
+#define PIO_PB19_IDX      51
+#define PIO_PB20_IDX      52
+#define PIO_PB21_IDX      53
+#define PIO_PB22_IDX      54
+#define PIO_PB23_IDX      55
+#define PIO_PB24_IDX      56
+
+#endif /* _SAM3U1C_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/pio/pio_sam3u1e.h b/hardware/sam/system/libsam/cmsis/sam3u/include/pio/pio_sam3u1e.h
new file mode 100644
index 000000000..3a0a48f23
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/pio/pio_sam3u1e.h
@@ -0,0 +1,440 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U1E_PIO_
+#define _SAM3U1E_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15          (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16          (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17          (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18          (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19          (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20          (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21          (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22          (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23          (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24          (1u << 24) /**< \brief Pin Controlled by PB24 */
+#define PIO_PB25          (1u << 25) /**< \brief Pin Controlled by PB25 */
+#define PIO_PB26          (1u << 26) /**< \brief Pin Controlled by PB26 */
+#define PIO_PB27          (1u << 27) /**< \brief Pin Controlled by PB27 */
+#define PIO_PB28          (1u << 28) /**< \brief Pin Controlled by PB28 */
+#define PIO_PB29          (1u << 29) /**< \brief Pin Controlled by PB29 */
+#define PIO_PB30          (1u << 30) /**< \brief Pin Controlled by PB30 */
+#define PIO_PB31          (1u << 31) /**< \brief Pin Controlled by PB31 */
+#define PIO_PC0           (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1           (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2           (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3           (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4           (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5           (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6           (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7           (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8           (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9           (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10          (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11          (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12          (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13          (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14          (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15          (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16          (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17          (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18          (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19          (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20          (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21          (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22          (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23          (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24          (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25          (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26          (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27          (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28          (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29          (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30          (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31          (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PB5X1_AD0     (1u << 5)  /**< \brief Adc signal: AD0 */
+#define PIO_PB6X1_AD1     (1u << 6)  /**< \brief Adc signal: AD1 */
+#define PIO_PB7X1_AD2     (1u << 7)  /**< \brief Adc signal: AD2 */
+#define PIO_PB8X1_AD3     (1u << 8)  /**< \brief Adc signal: AD3 */
+#define PIO_PC28X1_AD4    (1u << 28) /**< \brief Adc signal: AD4 */
+#define PIO_PC29X1_AD5    (1u << 29) /**< \brief Adc signal: AD5 */
+#define PIO_PC30X1_AD6    (1u << 30) /**< \brief Adc signal: AD6 */
+#define PIO_PC31X1_AD7    (1u << 31) /**< \brief Adc signal: AD7 */
+#define PIO_PA17B_ADTRG   (1u << 17) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for ADC12B peripheral ========== */
+#define PIO_PA22X1_AD12B0 (1u << 22) /**< \brief Adc12b signal: AD12B0 */
+#define PIO_PA30X1_AD12B1 (1u << 30) /**< \brief Adc12b signal: AD12B1 */
+#define PIO_PB3X1_AD12B2  (1u << 3)  /**< \brief Adc12b signal: AD12B2 */
+#define PIO_PB4X1_AD12B3  (1u << 4)  /**< \brief Adc12b signal: AD12B3 */
+#define PIO_PC15X1_AD12B4 (1u << 15) /**< \brief Adc12b signal: AD12B4 */
+#define PIO_PC16X1_AD12B5 (1u << 16) /**< \brief Adc12b signal: AD12B5 */
+#define PIO_PC17X1_AD12B6 (1u << 17) /**< \brief Adc12b signal: AD12B6 */
+#define PIO_PC18X1_AD12B7 (1u << 18) /**< \brief Adc12b signal: AD12B7 */
+#define PIO_PA2B_AD12BTRG (1u << 2)  /**< \brief Adc12b signal: AD12BTRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PB7B_A0       (1u << 7)  /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PB7B_NBS0     (1u << 7)  /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PB8B_A1       (1u << 8)  /**< \brief Ebi signal: A1 */
+#define PIO_PC8A_A10      (1u << 8)  /**< \brief Ebi signal: A10 */
+#define PIO_PC9A_A11      (1u << 9)  /**< \brief Ebi signal: A11 */
+#define PIO_PC10A_A12     (1u << 10) /**< \brief Ebi signal: A12 */
+#define PIO_PC11A_A13     (1u << 11) /**< \brief Ebi signal: A13 */
+#define PIO_PC20A_A14     (1u << 20) /**< \brief Ebi signal: A14 */
+#define PIO_PC21A_A15     (1u << 21) /**< \brief Ebi signal: A15 */
+#define PIO_PC22A_A16     (1u << 22) /**< \brief Ebi signal: A16 */
+#define PIO_PC23A_A17     (1u << 23) /**< \brief Ebi signal: A17 */
+#define PIO_PC24A_A18     (1u << 24) /**< \brief Ebi signal: A18 */
+#define PIO_PC25A_A19     (1u << 25) /**< \brief Ebi signal: A19 */
+#define PIO_PB0B_A2       (1u << 0)  /**< \brief Ebi signal: A2 */
+#define PIO_PC0A_A2       (1u << 0)  /**< \brief Ebi signal: A2 */
+#define PIO_PC13A_A2      (1u << 13) /**< \brief Ebi signal: A2 */
+#define PIO_PC26A_A20     (1u << 26) /**< \brief Ebi signal: A20 */
+#define PIO_PB21A_A21     (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PB21A_NANDALE (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PB22A_A22     (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PB22A_NANDCLE (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PC27A_A23     (1u << 27) /**< \brief Ebi signal: A23 */
+#define PIO_PB1B_A3       (1u << 1)  /**< \brief Ebi signal: A3 */
+#define PIO_PC1A_A3       (1u << 1)  /**< \brief Ebi signal: A3 */
+#define PIO_PC14A_A3      (1u << 14) /**< \brief Ebi signal: A3 */
+#define PIO_PB2B_A4       (1u << 2)  /**< \brief Ebi signal: A4 */
+#define PIO_PC2A_A4       (1u << 2)  /**< \brief Ebi signal: A4 */
+#define PIO_PB3B_A5       (1u << 3)  /**< \brief Ebi signal: A5 */
+#define PIO_PC3A_A5       (1u << 3)  /**< \brief Ebi signal: A5 */
+#define PIO_PB4B_A6       (1u << 4)  /**< \brief Ebi signal: A6 */
+#define PIO_PC4A_A6       (1u << 4)  /**< \brief Ebi signal: A6 */
+#define PIO_PB5B_A7       (1u << 5)  /**< \brief Ebi signal: A7 */
+#define PIO_PC5A_A7       (1u << 5)  /**< \brief Ebi signal: A7 */
+#define PIO_PC6A_A8       (1u << 6)  /**< \brief Ebi signal: A8 */
+#define PIO_PC7A_A9       (1u << 7)  /**< \brief Ebi signal: A9 */
+#define PIO_PB9A_D0       (1u << 9)  /**< \brief Ebi signal: D0 */
+#define PIO_PB10A_D1      (1u << 10) /**< \brief Ebi signal: D1 */
+#define PIO_PB27A_D10     (1u << 27) /**< \brief Ebi signal: D10 */
+#define PIO_PB28A_D11     (1u << 28) /**< \brief Ebi signal: D11 */
+#define PIO_PB29A_D12     (1u << 29) /**< \brief Ebi signal: D12 */
+#define PIO_PB30A_D13     (1u << 30) /**< \brief Ebi signal: D13 */
+#define PIO_PB31A_D14     (1u << 31) /**< \brief Ebi signal: D14 */
+#define PIO_PB6B_D15      (1u << 6)  /**< \brief Ebi signal: D15 */
+#define PIO_PB11A_D2      (1u << 11) /**< \brief Ebi signal: D2 */
+#define PIO_PB12A_D3      (1u << 12) /**< \brief Ebi signal: D3 */
+#define PIO_PB13A_D4      (1u << 13) /**< \brief Ebi signal: D4 */
+#define PIO_PB14A_D5      (1u << 14) /**< \brief Ebi signal: D5 */
+#define PIO_PB15A_D6      (1u << 15) /**< \brief Ebi signal: D6 */
+#define PIO_PB16A_D7      (1u << 16) /**< \brief Ebi signal: D7 */
+#define PIO_PB25A_D8      (1u << 25) /**< \brief Ebi signal: D8 */
+#define PIO_PB26A_D9      (1u << 26) /**< \brief Ebi signal: D9 */
+#define PIO_PB17A_NANDOE  (1u << 17) /**< \brief Ebi signal: NANDOE */
+#define PIO_PB24A_NANDRDY (1u << 24) /**< \brief Ebi signal: NANDRDY */
+#define PIO_PB18A_NANDWE  (1u << 18) /**< \brief Ebi signal: NANDWE */
+#define PIO_PB20A_NCS0    (1u << 20) /**< \brief Ebi signal: NCS0 */
+#define PIO_PA16B_NCS1    (1u << 16) /**< \brief Ebi signal: NCS1 */
+#define PIO_PC12A_NCS1    (1u << 12) /**< \brief Ebi signal: NCS1 */
+#define PIO_PC16A_NCS2    (1u << 16) /**< \brief Ebi signal: NCS2 */
+#define PIO_PC17A_NCS3    (1u << 17) /**< \brief Ebi signal: NCS3 */
+#define PIO_PB19A_NRD     (1u << 19) /**< \brief Ebi signal: NRD */
+#define PIO_PC18A_NWAIT   (1u << 18) /**< \brief Ebi signal: NWAIT */
+#define PIO_PB23A_NWR0    (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PB23A_NWE     (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PC15A_NWR1    (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
+#define PIO_PC15A_NBS1    (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA4A_MCCDA    (1u << 4)  /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA3A_MCCK     (1u << 3)  /**< \brief Hsmci signal: MCCK */
+#define PIO_PA5A_MCDA0    (1u << 5)  /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA6A_MCDA1    (1u << 6)  /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA7A_MCDA2    (1u << 7)  /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA8A_MCDA3    (1u << 8)  /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PC28B_MCDA4   (1u << 28) /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PC29B_MCDA5   (1u << 29) /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PC30B_MCDA6   (1u << 30) /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PC31B_MCDA7   (1u << 31) /**< \brief Hsmci signal: MCDA7 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA21B_PCK0    (1u << 21) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA27B_PCK0    (1u << 27) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA3B_PCK1     (1u << 3)  /**< \brief Pmc signal: PCK1 */
+#define PIO_PB24B_PCK1    (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PB23B_PCK2    (1u << 23) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA11B_PWMFI0  (1u << 11) /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA12B_PWMFI1  (1u << 12) /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PA18B_PWMFI2  (1u << 18) /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA4B_PWMH0    (1u << 4)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA28B_PWMH0   (1u << 28) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0    (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB13B_PWMH0   (1u << 13) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC24B_PWMH0   (1u << 24) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA5B_PWMH1    (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA29B_PWMH1   (1u << 29) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1    (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB14B_PWMH1   (1u << 14) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC25B_PWMH1   (1u << 25) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA6B_PWMH2    (1u << 6)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA15B_PWMH2   (1u << 15) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB2A_PWMH2    (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB15B_PWMH2   (1u << 15) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC26B_PWMH2   (1u << 26) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA20B_PWMH3   (1u << 20) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB3A_PWMH3    (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB16B_PWMH3   (1u << 16) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC27B_PWMH3   (1u << 27) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA7B_PWML0    (1u << 7)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PB17B_PWML0   (1u << 17) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB25B_PWML0   (1u << 25) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC6B_PWML0    (1u << 6)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC29A_PWML0   (1u << 29) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA8B_PWML1    (1u << 8)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PB18B_PWML1   (1u << 18) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB26B_PWML1   (1u << 26) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC7B_PWML1    (1u << 7)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC30A_PWML1   (1u << 30) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA9B_PWML2    (1u << 9)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PB19B_PWML2   (1u << 19) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB27B_PWML2   (1u << 27) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC8B_PWML2    (1u << 8)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PC31A_PWML2   (1u << 31) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA10B_PWML3   (1u << 10) /**< \brief Pwm signal: PWML3 */
+#define PIO_PB20B_PWML3   (1u << 20) /**< \brief Pwm signal: PWML3 */
+#define PIO_PB28B_PWML3   (1u << 28) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC9B_PWML3    (1u << 9)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC16B_PWML3   (1u << 16) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA13A_MISO    (1u << 13) /**< \brief Spi signal: MISO */
+#define PIO_PA14A_MOSI    (1u << 14) /**< \brief Spi signal: MOSI */
+#define PIO_PA16A_NPCS0   (1u << 16) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA0B_NPCS1    (1u << 0)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PC3B_NPCS1    (1u << 3)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PC19B_NPCS1   (1u << 19) /**< \brief Spi signal: NPCS1 */
+#define PIO_PA1B_NPCS2    (1u << 1)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC4B_NPCS2    (1u << 4)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC14B_NPCS2   (1u << 14) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA19B_NPCS3   (1u << 19) /**< \brief Spi signal: NPCS3 */
+#define PIO_PC5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA15A_SPCK    (1u << 15) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA27A_RD      (1u << 27) /**< \brief Ssc signal: RD */
+#define PIO_PA31A_RF      (1u << 31) /**< \brief Ssc signal: RF */
+#define PIO_PA29A_RK      (1u << 29) /**< \brief Ssc signal: RK */
+#define PIO_PA26A_TD      (1u << 26) /**< \brief Ssc signal: TD */
+#define PIO_PA30A_TF      (1u << 30) /**< \brief Ssc signal: TF */
+#define PIO_PA28A_TK      (1u << 28) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA2A_TCLK0    (1u << 2)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PB4A_TCLK1    (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA26B_TCLK2   (1u << 26) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA1A_TIOA0    (1u << 1)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PB5A_TIOA1    (1u << 5)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA30B_TIOA2   (1u << 30) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA0A_TIOB0    (1u << 0)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PB6A_TIOB1    (1u << 6)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA31B_TIOB2   (1u << 31) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA10A_TWCK0   (1u << 10) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA9A_TWD0     (1u << 9)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PA25A_TWCK1   (1u << 25) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PA24A_TWD1    (1u << 24) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA11A_URXD    (1u << 11) /**< \brief Uart signal: URXD */
+#define PIO_PA12A_UTXD    (1u << 12) /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB11B_DCD0    (1u << 11) /**< \brief Usart0 signal: DCD0 */
+#define PIO_PB10B_DSR0    (1u << 10) /**< \brief Usart0 signal: DSR0 */
+#define PIO_PB9B_DTR0     (1u << 9)  /**< \brief Usart0 signal: DTR0 */
+#define PIO_PB12B_RI0     (1u << 12) /**< \brief Usart0 signal: RI0 */
+#define PIO_PB7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA19A_RXD0    (1u << 19) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17A_SCK0    (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA18A_TXD0    (1u << 18) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA23B_CTS1    (1u << 23) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA22B_RTS1    (1u << 22) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA24B_SCK1    (1u << 24) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA20A_TXD1    (1u << 20) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB22B_CTS2    (1u << 22) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB21B_RTS2    (1u << 21) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PA23A_RXD2    (1u << 23) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PA25B_SCK2    (1u << 25) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PA22A_TXD2    (1u << 22) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio definition for USART3 peripheral ========== */
+#define PIO_PC10B_CTS3    (1u << 10) /**< \brief Usart3 signal: CTS3 */
+#define PIO_PC11B_RTS3    (1u << 11) /**< \brief Usart3 signal: RTS3 */
+#define PIO_PC13B_RXD3    (1u << 13) /**< \brief Usart3 signal: RXD3 */
+#define PIO_PC19A_SCK3    (1u << 19) /**< \brief Usart3 signal: SCK3 */
+#define PIO_PC12B_TXD3    (1u << 12) /**< \brief Usart3 signal: TXD3 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+#define PIO_PB15_IDX      47
+#define PIO_PB16_IDX      48
+#define PIO_PB17_IDX      49
+#define PIO_PB18_IDX      50
+#define PIO_PB19_IDX      51
+#define PIO_PB20_IDX      52
+#define PIO_PB21_IDX      53
+#define PIO_PB22_IDX      54
+#define PIO_PB23_IDX      55
+#define PIO_PB24_IDX      56
+#define PIO_PB25_IDX      57
+#define PIO_PB26_IDX      58
+#define PIO_PB27_IDX      59
+#define PIO_PB28_IDX      60
+#define PIO_PB29_IDX      61
+#define PIO_PB30_IDX      62
+#define PIO_PB31_IDX      63
+#define PIO_PC0_IDX       64
+#define PIO_PC1_IDX       65
+#define PIO_PC2_IDX       66
+#define PIO_PC3_IDX       67
+#define PIO_PC4_IDX       68
+#define PIO_PC5_IDX       69
+#define PIO_PC6_IDX       70
+#define PIO_PC7_IDX       71
+#define PIO_PC8_IDX       72
+#define PIO_PC9_IDX       73
+#define PIO_PC10_IDX      74
+#define PIO_PC11_IDX      75
+#define PIO_PC12_IDX      76
+#define PIO_PC13_IDX      77
+#define PIO_PC14_IDX      78
+#define PIO_PC15_IDX      79
+#define PIO_PC16_IDX      80
+#define PIO_PC17_IDX      81
+#define PIO_PC18_IDX      82
+#define PIO_PC19_IDX      83
+#define PIO_PC20_IDX      84
+#define PIO_PC21_IDX      85
+#define PIO_PC22_IDX      86
+#define PIO_PC23_IDX      87
+#define PIO_PC24_IDX      88
+#define PIO_PC25_IDX      89
+#define PIO_PC26_IDX      90
+#define PIO_PC27_IDX      91
+#define PIO_PC28_IDX      92
+#define PIO_PC29_IDX      93
+#define PIO_PC30_IDX      94
+#define PIO_PC31_IDX      95
+
+#endif /* _SAM3U1E_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/pio/pio_sam3u2c.h b/hardware/sam/system/libsam/cmsis/sam3u/include/pio/pio_sam3u2c.h
new file mode 100644
index 000000000..5a3f55661
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/pio/pio_sam3u2c.h
@@ -0,0 +1,356 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U2C_PIO_
+#define _SAM3U2C_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15          (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16          (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17          (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18          (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19          (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20          (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21          (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22          (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23          (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24          (1u << 24) /**< \brief Pin Controlled by PB24 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PB5X1_AD0     (1u << 5)  /**< \brief Adc signal: AD0 */
+#define PIO_PB6X1_AD1     (1u << 6)  /**< \brief Adc signal: AD1 */
+#define PIO_PB7X1_AD2     (1u << 7)  /**< \brief Adc signal: AD2 */
+#define PIO_PB8X1_AD3     (1u << 8)  /**< \brief Adc signal: AD3 */
+#define PIO_PC28X1_AD4    (1u << 28) /**< \brief Adc signal: AD4 */
+#define PIO_PC29X1_AD5    (1u << 29) /**< \brief Adc signal: AD5 */
+#define PIO_PC30X1_AD6    (1u << 30) /**< \brief Adc signal: AD6 */
+#define PIO_PC31X1_AD7    (1u << 31) /**< \brief Adc signal: AD7 */
+#define PIO_PA17B_ADTRG   (1u << 17) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for ADC12B peripheral ========== */
+#define PIO_PA22X1_AD12B0 (1u << 22) /**< \brief Adc12b signal: AD12B0 */
+#define PIO_PA30X1_AD12B1 (1u << 30) /**< \brief Adc12b signal: AD12B1 */
+#define PIO_PB3X1_AD12B2  (1u << 3)  /**< \brief Adc12b signal: AD12B2 */
+#define PIO_PB4X1_AD12B3  (1u << 4)  /**< \brief Adc12b signal: AD12B3 */
+#define PIO_PC15X1_AD12B4 (1u << 15) /**< \brief Adc12b signal: AD12B4 */
+#define PIO_PC16X1_AD12B5 (1u << 16) /**< \brief Adc12b signal: AD12B5 */
+#define PIO_PC17X1_AD12B6 (1u << 17) /**< \brief Adc12b signal: AD12B6 */
+#define PIO_PC18X1_AD12B7 (1u << 18) /**< \brief Adc12b signal: AD12B7 */
+#define PIO_PA2B_AD12BTRG (1u << 2)  /**< \brief Adc12b signal: AD12BTRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PB7B_A0       (1u << 7)  /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PB7B_NBS0     (1u << 7)  /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PB8B_A1       (1u << 8)  /**< \brief Ebi signal: A1 */
+#define PIO_PC8A_A10      (1u << 8)  /**< \brief Ebi signal: A10 */
+#define PIO_PC9A_A11      (1u << 9)  /**< \brief Ebi signal: A11 */
+#define PIO_PC10A_A12     (1u << 10) /**< \brief Ebi signal: A12 */
+#define PIO_PC11A_A13     (1u << 11) /**< \brief Ebi signal: A13 */
+#define PIO_PC20A_A14     (1u << 20) /**< \brief Ebi signal: A14 */
+#define PIO_PC21A_A15     (1u << 21) /**< \brief Ebi signal: A15 */
+#define PIO_PC22A_A16     (1u << 22) /**< \brief Ebi signal: A16 */
+#define PIO_PC23A_A17     (1u << 23) /**< \brief Ebi signal: A17 */
+#define PIO_PC24A_A18     (1u << 24) /**< \brief Ebi signal: A18 */
+#define PIO_PC25A_A19     (1u << 25) /**< \brief Ebi signal: A19 */
+#define PIO_PB0B_A2       (1u << 0)  /**< \brief Ebi signal: A2 */
+#define PIO_PC0A_A2       (1u << 0)  /**< \brief Ebi signal: A2 */
+#define PIO_PC13A_A2      (1u << 13) /**< \brief Ebi signal: A2 */
+#define PIO_PC26A_A20     (1u << 26) /**< \brief Ebi signal: A20 */
+#define PIO_PB21A_A21     (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PB21A_NANDALE (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PB22A_A22     (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PB22A_NANDCLE (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PC27A_A23     (1u << 27) /**< \brief Ebi signal: A23 */
+#define PIO_PB1B_A3       (1u << 1)  /**< \brief Ebi signal: A3 */
+#define PIO_PC1A_A3       (1u << 1)  /**< \brief Ebi signal: A3 */
+#define PIO_PC14A_A3      (1u << 14) /**< \brief Ebi signal: A3 */
+#define PIO_PB2B_A4       (1u << 2)  /**< \brief Ebi signal: A4 */
+#define PIO_PC2A_A4       (1u << 2)  /**< \brief Ebi signal: A4 */
+#define PIO_PB3B_A5       (1u << 3)  /**< \brief Ebi signal: A5 */
+#define PIO_PC3A_A5       (1u << 3)  /**< \brief Ebi signal: A5 */
+#define PIO_PB4B_A6       (1u << 4)  /**< \brief Ebi signal: A6 */
+#define PIO_PC4A_A6       (1u << 4)  /**< \brief Ebi signal: A6 */
+#define PIO_PB5B_A7       (1u << 5)  /**< \brief Ebi signal: A7 */
+#define PIO_PC5A_A7       (1u << 5)  /**< \brief Ebi signal: A7 */
+#define PIO_PC6A_A8       (1u << 6)  /**< \brief Ebi signal: A8 */
+#define PIO_PC7A_A9       (1u << 7)  /**< \brief Ebi signal: A9 */
+#define PIO_PB9A_D0       (1u << 9)  /**< \brief Ebi signal: D0 */
+#define PIO_PB10A_D1      (1u << 10) /**< \brief Ebi signal: D1 */
+#define PIO_PB27A_D10     (1u << 27) /**< \brief Ebi signal: D10 */
+#define PIO_PB28A_D11     (1u << 28) /**< \brief Ebi signal: D11 */
+#define PIO_PB29A_D12     (1u << 29) /**< \brief Ebi signal: D12 */
+#define PIO_PB30A_D13     (1u << 30) /**< \brief Ebi signal: D13 */
+#define PIO_PB31A_D14     (1u << 31) /**< \brief Ebi signal: D14 */
+#define PIO_PB6B_D15      (1u << 6)  /**< \brief Ebi signal: D15 */
+#define PIO_PB11A_D2      (1u << 11) /**< \brief Ebi signal: D2 */
+#define PIO_PB12A_D3      (1u << 12) /**< \brief Ebi signal: D3 */
+#define PIO_PB13A_D4      (1u << 13) /**< \brief Ebi signal: D4 */
+#define PIO_PB14A_D5      (1u << 14) /**< \brief Ebi signal: D5 */
+#define PIO_PB15A_D6      (1u << 15) /**< \brief Ebi signal: D6 */
+#define PIO_PB16A_D7      (1u << 16) /**< \brief Ebi signal: D7 */
+#define PIO_PB25A_D8      (1u << 25) /**< \brief Ebi signal: D8 */
+#define PIO_PB26A_D9      (1u << 26) /**< \brief Ebi signal: D9 */
+#define PIO_PB17A_NANDOE  (1u << 17) /**< \brief Ebi signal: NANDOE */
+#define PIO_PB24A_NANDRDY (1u << 24) /**< \brief Ebi signal: NANDRDY */
+#define PIO_PB18A_NANDWE  (1u << 18) /**< \brief Ebi signal: NANDWE */
+#define PIO_PB20A_NCS0    (1u << 20) /**< \brief Ebi signal: NCS0 */
+#define PIO_PA16B_NCS1    (1u << 16) /**< \brief Ebi signal: NCS1 */
+#define PIO_PC12A_NCS1    (1u << 12) /**< \brief Ebi signal: NCS1 */
+#define PIO_PC16A_NCS2    (1u << 16) /**< \brief Ebi signal: NCS2 */
+#define PIO_PC17A_NCS3    (1u << 17) /**< \brief Ebi signal: NCS3 */
+#define PIO_PB19A_NRD     (1u << 19) /**< \brief Ebi signal: NRD */
+#define PIO_PC18A_NWAIT   (1u << 18) /**< \brief Ebi signal: NWAIT */
+#define PIO_PB23A_NWR0    (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PB23A_NWE     (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PC15A_NWR1    (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
+#define PIO_PC15A_NBS1    (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA4A_MCCDA    (1u << 4)  /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA3A_MCCK     (1u << 3)  /**< \brief Hsmci signal: MCCK */
+#define PIO_PA5A_MCDA0    (1u << 5)  /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA6A_MCDA1    (1u << 6)  /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA7A_MCDA2    (1u << 7)  /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA8A_MCDA3    (1u << 8)  /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PC28B_MCDA4   (1u << 28) /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PC29B_MCDA5   (1u << 29) /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PC30B_MCDA6   (1u << 30) /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PC31B_MCDA7   (1u << 31) /**< \brief Hsmci signal: MCDA7 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA21B_PCK0    (1u << 21) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA27B_PCK0    (1u << 27) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA3B_PCK1     (1u << 3)  /**< \brief Pmc signal: PCK1 */
+#define PIO_PB24B_PCK1    (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PB23B_PCK2    (1u << 23) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA11B_PWMFI0  (1u << 11) /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA12B_PWMFI1  (1u << 12) /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PA18B_PWMFI2  (1u << 18) /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA4B_PWMH0    (1u << 4)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA28B_PWMH0   (1u << 28) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0    (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB13B_PWMH0   (1u << 13) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC24B_PWMH0   (1u << 24) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA5B_PWMH1    (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA29B_PWMH1   (1u << 29) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1    (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB14B_PWMH1   (1u << 14) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC25B_PWMH1   (1u << 25) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA6B_PWMH2    (1u << 6)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA15B_PWMH2   (1u << 15) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB2A_PWMH2    (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB15B_PWMH2   (1u << 15) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC26B_PWMH2   (1u << 26) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA20B_PWMH3   (1u << 20) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB3A_PWMH3    (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB16B_PWMH3   (1u << 16) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC27B_PWMH3   (1u << 27) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA7B_PWML0    (1u << 7)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PB17B_PWML0   (1u << 17) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB25B_PWML0   (1u << 25) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC6B_PWML0    (1u << 6)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC29A_PWML0   (1u << 29) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA8B_PWML1    (1u << 8)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PB18B_PWML1   (1u << 18) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB26B_PWML1   (1u << 26) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC7B_PWML1    (1u << 7)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC30A_PWML1   (1u << 30) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA9B_PWML2    (1u << 9)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PB19B_PWML2   (1u << 19) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB27B_PWML2   (1u << 27) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC8B_PWML2    (1u << 8)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PC31A_PWML2   (1u << 31) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA10B_PWML3   (1u << 10) /**< \brief Pwm signal: PWML3 */
+#define PIO_PB20B_PWML3   (1u << 20) /**< \brief Pwm signal: PWML3 */
+#define PIO_PB28B_PWML3   (1u << 28) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC9B_PWML3    (1u << 9)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC16B_PWML3   (1u << 16) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA13A_MISO    (1u << 13) /**< \brief Spi signal: MISO */
+#define PIO_PA14A_MOSI    (1u << 14) /**< \brief Spi signal: MOSI */
+#define PIO_PA16A_NPCS0   (1u << 16) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA0B_NPCS1    (1u << 0)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PC3B_NPCS1    (1u << 3)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PC19B_NPCS1   (1u << 19) /**< \brief Spi signal: NPCS1 */
+#define PIO_PA1B_NPCS2    (1u << 1)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC4B_NPCS2    (1u << 4)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC14B_NPCS2   (1u << 14) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA19B_NPCS3   (1u << 19) /**< \brief Spi signal: NPCS3 */
+#define PIO_PC5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA15A_SPCK    (1u << 15) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA27A_RD      (1u << 27) /**< \brief Ssc signal: RD */
+#define PIO_PA31A_RF      (1u << 31) /**< \brief Ssc signal: RF */
+#define PIO_PA29A_RK      (1u << 29) /**< \brief Ssc signal: RK */
+#define PIO_PA26A_TD      (1u << 26) /**< \brief Ssc signal: TD */
+#define PIO_PA30A_TF      (1u << 30) /**< \brief Ssc signal: TF */
+#define PIO_PA28A_TK      (1u << 28) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA2A_TCLK0    (1u << 2)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PB4A_TCLK1    (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA26B_TCLK2   (1u << 26) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA1A_TIOA0    (1u << 1)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PB5A_TIOA1    (1u << 5)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA30B_TIOA2   (1u << 30) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA0A_TIOB0    (1u << 0)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PB6A_TIOB1    (1u << 6)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA31B_TIOB2   (1u << 31) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA10A_TWCK0   (1u << 10) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA9A_TWD0     (1u << 9)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PA25A_TWCK1   (1u << 25) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PA24A_TWD1    (1u << 24) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA11A_URXD    (1u << 11) /**< \brief Uart signal: URXD */
+#define PIO_PA12A_UTXD    (1u << 12) /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB11B_DCD0    (1u << 11) /**< \brief Usart0 signal: DCD0 */
+#define PIO_PB10B_DSR0    (1u << 10) /**< \brief Usart0 signal: DSR0 */
+#define PIO_PB9B_DTR0     (1u << 9)  /**< \brief Usart0 signal: DTR0 */
+#define PIO_PB12B_RI0     (1u << 12) /**< \brief Usart0 signal: RI0 */
+#define PIO_PB7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA19A_RXD0    (1u << 19) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17A_SCK0    (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA18A_TXD0    (1u << 18) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA23B_CTS1    (1u << 23) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA22B_RTS1    (1u << 22) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA24B_SCK1    (1u << 24) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA20A_TXD1    (1u << 20) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB22B_CTS2    (1u << 22) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB21B_RTS2    (1u << 21) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PA23A_RXD2    (1u << 23) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PA25B_SCK2    (1u << 25) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PA22A_TXD2    (1u << 22) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+#define PIO_PB15_IDX      47
+#define PIO_PB16_IDX      48
+#define PIO_PB17_IDX      49
+#define PIO_PB18_IDX      50
+#define PIO_PB19_IDX      51
+#define PIO_PB20_IDX      52
+#define PIO_PB21_IDX      53
+#define PIO_PB22_IDX      54
+#define PIO_PB23_IDX      55
+#define PIO_PB24_IDX      56
+
+#endif /* _SAM3U2C_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/pio/pio_sam3u2e.h b/hardware/sam/system/libsam/cmsis/sam3u/include/pio/pio_sam3u2e.h
new file mode 100644
index 000000000..0fa035631
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/pio/pio_sam3u2e.h
@@ -0,0 +1,440 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U2E_PIO_
+#define _SAM3U2E_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15          (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16          (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17          (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18          (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19          (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20          (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21          (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22          (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23          (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24          (1u << 24) /**< \brief Pin Controlled by PB24 */
+#define PIO_PB25          (1u << 25) /**< \brief Pin Controlled by PB25 */
+#define PIO_PB26          (1u << 26) /**< \brief Pin Controlled by PB26 */
+#define PIO_PB27          (1u << 27) /**< \brief Pin Controlled by PB27 */
+#define PIO_PB28          (1u << 28) /**< \brief Pin Controlled by PB28 */
+#define PIO_PB29          (1u << 29) /**< \brief Pin Controlled by PB29 */
+#define PIO_PB30          (1u << 30) /**< \brief Pin Controlled by PB30 */
+#define PIO_PB31          (1u << 31) /**< \brief Pin Controlled by PB31 */
+#define PIO_PC0           (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1           (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2           (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3           (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4           (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5           (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6           (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7           (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8           (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9           (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10          (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11          (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12          (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13          (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14          (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15          (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16          (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17          (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18          (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19          (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20          (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21          (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22          (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23          (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24          (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25          (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26          (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27          (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28          (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29          (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30          (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31          (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PB5X1_AD0     (1u << 5)  /**< \brief Adc signal: AD0 */
+#define PIO_PB6X1_AD1     (1u << 6)  /**< \brief Adc signal: AD1 */
+#define PIO_PB7X1_AD2     (1u << 7)  /**< \brief Adc signal: AD2 */
+#define PIO_PB8X1_AD3     (1u << 8)  /**< \brief Adc signal: AD3 */
+#define PIO_PC28X1_AD4    (1u << 28) /**< \brief Adc signal: AD4 */
+#define PIO_PC29X1_AD5    (1u << 29) /**< \brief Adc signal: AD5 */
+#define PIO_PC30X1_AD6    (1u << 30) /**< \brief Adc signal: AD6 */
+#define PIO_PC31X1_AD7    (1u << 31) /**< \brief Adc signal: AD7 */
+#define PIO_PA17B_ADTRG   (1u << 17) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for ADC12B peripheral ========== */
+#define PIO_PA22X1_AD12B0 (1u << 22) /**< \brief Adc12b signal: AD12B0 */
+#define PIO_PA30X1_AD12B1 (1u << 30) /**< \brief Adc12b signal: AD12B1 */
+#define PIO_PB3X1_AD12B2  (1u << 3)  /**< \brief Adc12b signal: AD12B2 */
+#define PIO_PB4X1_AD12B3  (1u << 4)  /**< \brief Adc12b signal: AD12B3 */
+#define PIO_PC15X1_AD12B4 (1u << 15) /**< \brief Adc12b signal: AD12B4 */
+#define PIO_PC16X1_AD12B5 (1u << 16) /**< \brief Adc12b signal: AD12B5 */
+#define PIO_PC17X1_AD12B6 (1u << 17) /**< \brief Adc12b signal: AD12B6 */
+#define PIO_PC18X1_AD12B7 (1u << 18) /**< \brief Adc12b signal: AD12B7 */
+#define PIO_PA2B_AD12BTRG (1u << 2)  /**< \brief Adc12b signal: AD12BTRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PB7B_A0       (1u << 7)  /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PB7B_NBS0     (1u << 7)  /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PB8B_A1       (1u << 8)  /**< \brief Ebi signal: A1 */
+#define PIO_PC8A_A10      (1u << 8)  /**< \brief Ebi signal: A10 */
+#define PIO_PC9A_A11      (1u << 9)  /**< \brief Ebi signal: A11 */
+#define PIO_PC10A_A12     (1u << 10) /**< \brief Ebi signal: A12 */
+#define PIO_PC11A_A13     (1u << 11) /**< \brief Ebi signal: A13 */
+#define PIO_PC20A_A14     (1u << 20) /**< \brief Ebi signal: A14 */
+#define PIO_PC21A_A15     (1u << 21) /**< \brief Ebi signal: A15 */
+#define PIO_PC22A_A16     (1u << 22) /**< \brief Ebi signal: A16 */
+#define PIO_PC23A_A17     (1u << 23) /**< \brief Ebi signal: A17 */
+#define PIO_PC24A_A18     (1u << 24) /**< \brief Ebi signal: A18 */
+#define PIO_PC25A_A19     (1u << 25) /**< \brief Ebi signal: A19 */
+#define PIO_PB0B_A2       (1u << 0)  /**< \brief Ebi signal: A2 */
+#define PIO_PC0A_A2       (1u << 0)  /**< \brief Ebi signal: A2 */
+#define PIO_PC13A_A2      (1u << 13) /**< \brief Ebi signal: A2 */
+#define PIO_PC26A_A20     (1u << 26) /**< \brief Ebi signal: A20 */
+#define PIO_PB21A_A21     (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PB21A_NANDALE (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PB22A_A22     (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PB22A_NANDCLE (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PC27A_A23     (1u << 27) /**< \brief Ebi signal: A23 */
+#define PIO_PB1B_A3       (1u << 1)  /**< \brief Ebi signal: A3 */
+#define PIO_PC1A_A3       (1u << 1)  /**< \brief Ebi signal: A3 */
+#define PIO_PC14A_A3      (1u << 14) /**< \brief Ebi signal: A3 */
+#define PIO_PB2B_A4       (1u << 2)  /**< \brief Ebi signal: A4 */
+#define PIO_PC2A_A4       (1u << 2)  /**< \brief Ebi signal: A4 */
+#define PIO_PB3B_A5       (1u << 3)  /**< \brief Ebi signal: A5 */
+#define PIO_PC3A_A5       (1u << 3)  /**< \brief Ebi signal: A5 */
+#define PIO_PB4B_A6       (1u << 4)  /**< \brief Ebi signal: A6 */
+#define PIO_PC4A_A6       (1u << 4)  /**< \brief Ebi signal: A6 */
+#define PIO_PB5B_A7       (1u << 5)  /**< \brief Ebi signal: A7 */
+#define PIO_PC5A_A7       (1u << 5)  /**< \brief Ebi signal: A7 */
+#define PIO_PC6A_A8       (1u << 6)  /**< \brief Ebi signal: A8 */
+#define PIO_PC7A_A9       (1u << 7)  /**< \brief Ebi signal: A9 */
+#define PIO_PB9A_D0       (1u << 9)  /**< \brief Ebi signal: D0 */
+#define PIO_PB10A_D1      (1u << 10) /**< \brief Ebi signal: D1 */
+#define PIO_PB27A_D10     (1u << 27) /**< \brief Ebi signal: D10 */
+#define PIO_PB28A_D11     (1u << 28) /**< \brief Ebi signal: D11 */
+#define PIO_PB29A_D12     (1u << 29) /**< \brief Ebi signal: D12 */
+#define PIO_PB30A_D13     (1u << 30) /**< \brief Ebi signal: D13 */
+#define PIO_PB31A_D14     (1u << 31) /**< \brief Ebi signal: D14 */
+#define PIO_PB6B_D15      (1u << 6)  /**< \brief Ebi signal: D15 */
+#define PIO_PB11A_D2      (1u << 11) /**< \brief Ebi signal: D2 */
+#define PIO_PB12A_D3      (1u << 12) /**< \brief Ebi signal: D3 */
+#define PIO_PB13A_D4      (1u << 13) /**< \brief Ebi signal: D4 */
+#define PIO_PB14A_D5      (1u << 14) /**< \brief Ebi signal: D5 */
+#define PIO_PB15A_D6      (1u << 15) /**< \brief Ebi signal: D6 */
+#define PIO_PB16A_D7      (1u << 16) /**< \brief Ebi signal: D7 */
+#define PIO_PB25A_D8      (1u << 25) /**< \brief Ebi signal: D8 */
+#define PIO_PB26A_D9      (1u << 26) /**< \brief Ebi signal: D9 */
+#define PIO_PB17A_NANDOE  (1u << 17) /**< \brief Ebi signal: NANDOE */
+#define PIO_PB24A_NANDRDY (1u << 24) /**< \brief Ebi signal: NANDRDY */
+#define PIO_PB18A_NANDWE  (1u << 18) /**< \brief Ebi signal: NANDWE */
+#define PIO_PB20A_NCS0    (1u << 20) /**< \brief Ebi signal: NCS0 */
+#define PIO_PA16B_NCS1    (1u << 16) /**< \brief Ebi signal: NCS1 */
+#define PIO_PC12A_NCS1    (1u << 12) /**< \brief Ebi signal: NCS1 */
+#define PIO_PC16A_NCS2    (1u << 16) /**< \brief Ebi signal: NCS2 */
+#define PIO_PC17A_NCS3    (1u << 17) /**< \brief Ebi signal: NCS3 */
+#define PIO_PB19A_NRD     (1u << 19) /**< \brief Ebi signal: NRD */
+#define PIO_PC18A_NWAIT   (1u << 18) /**< \brief Ebi signal: NWAIT */
+#define PIO_PB23A_NWR0    (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PB23A_NWE     (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PC15A_NWR1    (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
+#define PIO_PC15A_NBS1    (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA4A_MCCDA    (1u << 4)  /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA3A_MCCK     (1u << 3)  /**< \brief Hsmci signal: MCCK */
+#define PIO_PA5A_MCDA0    (1u << 5)  /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA6A_MCDA1    (1u << 6)  /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA7A_MCDA2    (1u << 7)  /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA8A_MCDA3    (1u << 8)  /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PC28B_MCDA4   (1u << 28) /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PC29B_MCDA5   (1u << 29) /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PC30B_MCDA6   (1u << 30) /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PC31B_MCDA7   (1u << 31) /**< \brief Hsmci signal: MCDA7 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA21B_PCK0    (1u << 21) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA27B_PCK0    (1u << 27) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA3B_PCK1     (1u << 3)  /**< \brief Pmc signal: PCK1 */
+#define PIO_PB24B_PCK1    (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PB23B_PCK2    (1u << 23) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA11B_PWMFI0  (1u << 11) /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA12B_PWMFI1  (1u << 12) /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PA18B_PWMFI2  (1u << 18) /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA4B_PWMH0    (1u << 4)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA28B_PWMH0   (1u << 28) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0    (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB13B_PWMH0   (1u << 13) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC24B_PWMH0   (1u << 24) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA5B_PWMH1    (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA29B_PWMH1   (1u << 29) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1    (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB14B_PWMH1   (1u << 14) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC25B_PWMH1   (1u << 25) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA6B_PWMH2    (1u << 6)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA15B_PWMH2   (1u << 15) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB2A_PWMH2    (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB15B_PWMH2   (1u << 15) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC26B_PWMH2   (1u << 26) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA20B_PWMH3   (1u << 20) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB3A_PWMH3    (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB16B_PWMH3   (1u << 16) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC27B_PWMH3   (1u << 27) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA7B_PWML0    (1u << 7)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PB17B_PWML0   (1u << 17) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB25B_PWML0   (1u << 25) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC6B_PWML0    (1u << 6)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC29A_PWML0   (1u << 29) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA8B_PWML1    (1u << 8)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PB18B_PWML1   (1u << 18) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB26B_PWML1   (1u << 26) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC7B_PWML1    (1u << 7)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC30A_PWML1   (1u << 30) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA9B_PWML2    (1u << 9)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PB19B_PWML2   (1u << 19) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB27B_PWML2   (1u << 27) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC8B_PWML2    (1u << 8)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PC31A_PWML2   (1u << 31) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA10B_PWML3   (1u << 10) /**< \brief Pwm signal: PWML3 */
+#define PIO_PB20B_PWML3   (1u << 20) /**< \brief Pwm signal: PWML3 */
+#define PIO_PB28B_PWML3   (1u << 28) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC9B_PWML3    (1u << 9)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC16B_PWML3   (1u << 16) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA13A_MISO    (1u << 13) /**< \brief Spi signal: MISO */
+#define PIO_PA14A_MOSI    (1u << 14) /**< \brief Spi signal: MOSI */
+#define PIO_PA16A_NPCS0   (1u << 16) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA0B_NPCS1    (1u << 0)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PC3B_NPCS1    (1u << 3)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PC19B_NPCS1   (1u << 19) /**< \brief Spi signal: NPCS1 */
+#define PIO_PA1B_NPCS2    (1u << 1)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC4B_NPCS2    (1u << 4)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC14B_NPCS2   (1u << 14) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA19B_NPCS3   (1u << 19) /**< \brief Spi signal: NPCS3 */
+#define PIO_PC5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA15A_SPCK    (1u << 15) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA27A_RD      (1u << 27) /**< \brief Ssc signal: RD */
+#define PIO_PA31A_RF      (1u << 31) /**< \brief Ssc signal: RF */
+#define PIO_PA29A_RK      (1u << 29) /**< \brief Ssc signal: RK */
+#define PIO_PA26A_TD      (1u << 26) /**< \brief Ssc signal: TD */
+#define PIO_PA30A_TF      (1u << 30) /**< \brief Ssc signal: TF */
+#define PIO_PA28A_TK      (1u << 28) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA2A_TCLK0    (1u << 2)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PB4A_TCLK1    (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA26B_TCLK2   (1u << 26) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA1A_TIOA0    (1u << 1)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PB5A_TIOA1    (1u << 5)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA30B_TIOA2   (1u << 30) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA0A_TIOB0    (1u << 0)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PB6A_TIOB1    (1u << 6)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA31B_TIOB2   (1u << 31) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA10A_TWCK0   (1u << 10) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA9A_TWD0     (1u << 9)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PA25A_TWCK1   (1u << 25) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PA24A_TWD1    (1u << 24) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA11A_URXD    (1u << 11) /**< \brief Uart signal: URXD */
+#define PIO_PA12A_UTXD    (1u << 12) /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB11B_DCD0    (1u << 11) /**< \brief Usart0 signal: DCD0 */
+#define PIO_PB10B_DSR0    (1u << 10) /**< \brief Usart0 signal: DSR0 */
+#define PIO_PB9B_DTR0     (1u << 9)  /**< \brief Usart0 signal: DTR0 */
+#define PIO_PB12B_RI0     (1u << 12) /**< \brief Usart0 signal: RI0 */
+#define PIO_PB7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA19A_RXD0    (1u << 19) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17A_SCK0    (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA18A_TXD0    (1u << 18) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA23B_CTS1    (1u << 23) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA22B_RTS1    (1u << 22) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA24B_SCK1    (1u << 24) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA20A_TXD1    (1u << 20) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB22B_CTS2    (1u << 22) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB21B_RTS2    (1u << 21) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PA23A_RXD2    (1u << 23) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PA25B_SCK2    (1u << 25) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PA22A_TXD2    (1u << 22) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio definition for USART3 peripheral ========== */
+#define PIO_PC10B_CTS3    (1u << 10) /**< \brief Usart3 signal: CTS3 */
+#define PIO_PC11B_RTS3    (1u << 11) /**< \brief Usart3 signal: RTS3 */
+#define PIO_PC13B_RXD3    (1u << 13) /**< \brief Usart3 signal: RXD3 */
+#define PIO_PC19A_SCK3    (1u << 19) /**< \brief Usart3 signal: SCK3 */
+#define PIO_PC12B_TXD3    (1u << 12) /**< \brief Usart3 signal: TXD3 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+#define PIO_PB15_IDX      47
+#define PIO_PB16_IDX      48
+#define PIO_PB17_IDX      49
+#define PIO_PB18_IDX      50
+#define PIO_PB19_IDX      51
+#define PIO_PB20_IDX      52
+#define PIO_PB21_IDX      53
+#define PIO_PB22_IDX      54
+#define PIO_PB23_IDX      55
+#define PIO_PB24_IDX      56
+#define PIO_PB25_IDX      57
+#define PIO_PB26_IDX      58
+#define PIO_PB27_IDX      59
+#define PIO_PB28_IDX      60
+#define PIO_PB29_IDX      61
+#define PIO_PB30_IDX      62
+#define PIO_PB31_IDX      63
+#define PIO_PC0_IDX       64
+#define PIO_PC1_IDX       65
+#define PIO_PC2_IDX       66
+#define PIO_PC3_IDX       67
+#define PIO_PC4_IDX       68
+#define PIO_PC5_IDX       69
+#define PIO_PC6_IDX       70
+#define PIO_PC7_IDX       71
+#define PIO_PC8_IDX       72
+#define PIO_PC9_IDX       73
+#define PIO_PC10_IDX      74
+#define PIO_PC11_IDX      75
+#define PIO_PC12_IDX      76
+#define PIO_PC13_IDX      77
+#define PIO_PC14_IDX      78
+#define PIO_PC15_IDX      79
+#define PIO_PC16_IDX      80
+#define PIO_PC17_IDX      81
+#define PIO_PC18_IDX      82
+#define PIO_PC19_IDX      83
+#define PIO_PC20_IDX      84
+#define PIO_PC21_IDX      85
+#define PIO_PC22_IDX      86
+#define PIO_PC23_IDX      87
+#define PIO_PC24_IDX      88
+#define PIO_PC25_IDX      89
+#define PIO_PC26_IDX      90
+#define PIO_PC27_IDX      91
+#define PIO_PC28_IDX      92
+#define PIO_PC29_IDX      93
+#define PIO_PC30_IDX      94
+#define PIO_PC31_IDX      95
+
+#endif /* _SAM3U2E_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/pio/pio_sam3u4c.h b/hardware/sam/system/libsam/cmsis/sam3u/include/pio/pio_sam3u4c.h
new file mode 100644
index 000000000..602db8ad8
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/pio/pio_sam3u4c.h
@@ -0,0 +1,356 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U4C_PIO_
+#define _SAM3U4C_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15          (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16          (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17          (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18          (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19          (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20          (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21          (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22          (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23          (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24          (1u << 24) /**< \brief Pin Controlled by PB24 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PB5X1_AD0     (1u << 5)  /**< \brief Adc signal: AD0 */
+#define PIO_PB6X1_AD1     (1u << 6)  /**< \brief Adc signal: AD1 */
+#define PIO_PB7X1_AD2     (1u << 7)  /**< \brief Adc signal: AD2 */
+#define PIO_PB8X1_AD3     (1u << 8)  /**< \brief Adc signal: AD3 */
+#define PIO_PC28X1_AD4    (1u << 28) /**< \brief Adc signal: AD4 */
+#define PIO_PC29X1_AD5    (1u << 29) /**< \brief Adc signal: AD5 */
+#define PIO_PC30X1_AD6    (1u << 30) /**< \brief Adc signal: AD6 */
+#define PIO_PC31X1_AD7    (1u << 31) /**< \brief Adc signal: AD7 */
+#define PIO_PA17B_ADTRG   (1u << 17) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for ADC12B peripheral ========== */
+#define PIO_PA22X1_AD12B0 (1u << 22) /**< \brief Adc12b signal: AD12B0 */
+#define PIO_PA30X1_AD12B1 (1u << 30) /**< \brief Adc12b signal: AD12B1 */
+#define PIO_PB3X1_AD12B2  (1u << 3)  /**< \brief Adc12b signal: AD12B2 */
+#define PIO_PB4X1_AD12B3  (1u << 4)  /**< \brief Adc12b signal: AD12B3 */
+#define PIO_PC15X1_AD12B4 (1u << 15) /**< \brief Adc12b signal: AD12B4 */
+#define PIO_PC16X1_AD12B5 (1u << 16) /**< \brief Adc12b signal: AD12B5 */
+#define PIO_PC17X1_AD12B6 (1u << 17) /**< \brief Adc12b signal: AD12B6 */
+#define PIO_PC18X1_AD12B7 (1u << 18) /**< \brief Adc12b signal: AD12B7 */
+#define PIO_PA2B_AD12BTRG (1u << 2)  /**< \brief Adc12b signal: AD12BTRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PB7B_A0       (1u << 7)  /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PB7B_NBS0     (1u << 7)  /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PB8B_A1       (1u << 8)  /**< \brief Ebi signal: A1 */
+#define PIO_PC8A_A10      (1u << 8)  /**< \brief Ebi signal: A10 */
+#define PIO_PC9A_A11      (1u << 9)  /**< \brief Ebi signal: A11 */
+#define PIO_PC10A_A12     (1u << 10) /**< \brief Ebi signal: A12 */
+#define PIO_PC11A_A13     (1u << 11) /**< \brief Ebi signal: A13 */
+#define PIO_PC20A_A14     (1u << 20) /**< \brief Ebi signal: A14 */
+#define PIO_PC21A_A15     (1u << 21) /**< \brief Ebi signal: A15 */
+#define PIO_PC22A_A16     (1u << 22) /**< \brief Ebi signal: A16 */
+#define PIO_PC23A_A17     (1u << 23) /**< \brief Ebi signal: A17 */
+#define PIO_PC24A_A18     (1u << 24) /**< \brief Ebi signal: A18 */
+#define PIO_PC25A_A19     (1u << 25) /**< \brief Ebi signal: A19 */
+#define PIO_PB0B_A2       (1u << 0)  /**< \brief Ebi signal: A2 */
+#define PIO_PC0A_A2       (1u << 0)  /**< \brief Ebi signal: A2 */
+#define PIO_PC13A_A2      (1u << 13) /**< \brief Ebi signal: A2 */
+#define PIO_PC26A_A20     (1u << 26) /**< \brief Ebi signal: A20 */
+#define PIO_PB21A_A21     (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PB21A_NANDALE (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PB22A_A22     (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PB22A_NANDCLE (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PC27A_A23     (1u << 27) /**< \brief Ebi signal: A23 */
+#define PIO_PB1B_A3       (1u << 1)  /**< \brief Ebi signal: A3 */
+#define PIO_PC1A_A3       (1u << 1)  /**< \brief Ebi signal: A3 */
+#define PIO_PC14A_A3      (1u << 14) /**< \brief Ebi signal: A3 */
+#define PIO_PB2B_A4       (1u << 2)  /**< \brief Ebi signal: A4 */
+#define PIO_PC2A_A4       (1u << 2)  /**< \brief Ebi signal: A4 */
+#define PIO_PB3B_A5       (1u << 3)  /**< \brief Ebi signal: A5 */
+#define PIO_PC3A_A5       (1u << 3)  /**< \brief Ebi signal: A5 */
+#define PIO_PB4B_A6       (1u << 4)  /**< \brief Ebi signal: A6 */
+#define PIO_PC4A_A6       (1u << 4)  /**< \brief Ebi signal: A6 */
+#define PIO_PB5B_A7       (1u << 5)  /**< \brief Ebi signal: A7 */
+#define PIO_PC5A_A7       (1u << 5)  /**< \brief Ebi signal: A7 */
+#define PIO_PC6A_A8       (1u << 6)  /**< \brief Ebi signal: A8 */
+#define PIO_PC7A_A9       (1u << 7)  /**< \brief Ebi signal: A9 */
+#define PIO_PB9A_D0       (1u << 9)  /**< \brief Ebi signal: D0 */
+#define PIO_PB10A_D1      (1u << 10) /**< \brief Ebi signal: D1 */
+#define PIO_PB27A_D10     (1u << 27) /**< \brief Ebi signal: D10 */
+#define PIO_PB28A_D11     (1u << 28) /**< \brief Ebi signal: D11 */
+#define PIO_PB29A_D12     (1u << 29) /**< \brief Ebi signal: D12 */
+#define PIO_PB30A_D13     (1u << 30) /**< \brief Ebi signal: D13 */
+#define PIO_PB31A_D14     (1u << 31) /**< \brief Ebi signal: D14 */
+#define PIO_PB6B_D15      (1u << 6)  /**< \brief Ebi signal: D15 */
+#define PIO_PB11A_D2      (1u << 11) /**< \brief Ebi signal: D2 */
+#define PIO_PB12A_D3      (1u << 12) /**< \brief Ebi signal: D3 */
+#define PIO_PB13A_D4      (1u << 13) /**< \brief Ebi signal: D4 */
+#define PIO_PB14A_D5      (1u << 14) /**< \brief Ebi signal: D5 */
+#define PIO_PB15A_D6      (1u << 15) /**< \brief Ebi signal: D6 */
+#define PIO_PB16A_D7      (1u << 16) /**< \brief Ebi signal: D7 */
+#define PIO_PB25A_D8      (1u << 25) /**< \brief Ebi signal: D8 */
+#define PIO_PB26A_D9      (1u << 26) /**< \brief Ebi signal: D9 */
+#define PIO_PB17A_NANDOE  (1u << 17) /**< \brief Ebi signal: NANDOE */
+#define PIO_PB24A_NANDRDY (1u << 24) /**< \brief Ebi signal: NANDRDY */
+#define PIO_PB18A_NANDWE  (1u << 18) /**< \brief Ebi signal: NANDWE */
+#define PIO_PB20A_NCS0    (1u << 20) /**< \brief Ebi signal: NCS0 */
+#define PIO_PA16B_NCS1    (1u << 16) /**< \brief Ebi signal: NCS1 */
+#define PIO_PC12A_NCS1    (1u << 12) /**< \brief Ebi signal: NCS1 */
+#define PIO_PC16A_NCS2    (1u << 16) /**< \brief Ebi signal: NCS2 */
+#define PIO_PC17A_NCS3    (1u << 17) /**< \brief Ebi signal: NCS3 */
+#define PIO_PB19A_NRD     (1u << 19) /**< \brief Ebi signal: NRD */
+#define PIO_PC18A_NWAIT   (1u << 18) /**< \brief Ebi signal: NWAIT */
+#define PIO_PB23A_NWR0    (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PB23A_NWE     (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PC15A_NWR1    (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
+#define PIO_PC15A_NBS1    (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA4A_MCCDA    (1u << 4)  /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA3A_MCCK     (1u << 3)  /**< \brief Hsmci signal: MCCK */
+#define PIO_PA5A_MCDA0    (1u << 5)  /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA6A_MCDA1    (1u << 6)  /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA7A_MCDA2    (1u << 7)  /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA8A_MCDA3    (1u << 8)  /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PC28B_MCDA4   (1u << 28) /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PC29B_MCDA5   (1u << 29) /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PC30B_MCDA6   (1u << 30) /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PC31B_MCDA7   (1u << 31) /**< \brief Hsmci signal: MCDA7 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA21B_PCK0    (1u << 21) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA27B_PCK0    (1u << 27) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA3B_PCK1     (1u << 3)  /**< \brief Pmc signal: PCK1 */
+#define PIO_PB24B_PCK1    (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PB23B_PCK2    (1u << 23) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA11B_PWMFI0  (1u << 11) /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA12B_PWMFI1  (1u << 12) /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PA18B_PWMFI2  (1u << 18) /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA4B_PWMH0    (1u << 4)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA28B_PWMH0   (1u << 28) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0    (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB13B_PWMH0   (1u << 13) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC24B_PWMH0   (1u << 24) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA5B_PWMH1    (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA29B_PWMH1   (1u << 29) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1    (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB14B_PWMH1   (1u << 14) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC25B_PWMH1   (1u << 25) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA6B_PWMH2    (1u << 6)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA15B_PWMH2   (1u << 15) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB2A_PWMH2    (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB15B_PWMH2   (1u << 15) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC26B_PWMH2   (1u << 26) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA20B_PWMH3   (1u << 20) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB3A_PWMH3    (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB16B_PWMH3   (1u << 16) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC27B_PWMH3   (1u << 27) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA7B_PWML0    (1u << 7)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PB17B_PWML0   (1u << 17) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB25B_PWML0   (1u << 25) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC6B_PWML0    (1u << 6)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC29A_PWML0   (1u << 29) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA8B_PWML1    (1u << 8)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PB18B_PWML1   (1u << 18) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB26B_PWML1   (1u << 26) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC7B_PWML1    (1u << 7)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC30A_PWML1   (1u << 30) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA9B_PWML2    (1u << 9)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PB19B_PWML2   (1u << 19) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB27B_PWML2   (1u << 27) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC8B_PWML2    (1u << 8)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PC31A_PWML2   (1u << 31) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA10B_PWML3   (1u << 10) /**< \brief Pwm signal: PWML3 */
+#define PIO_PB20B_PWML3   (1u << 20) /**< \brief Pwm signal: PWML3 */
+#define PIO_PB28B_PWML3   (1u << 28) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC9B_PWML3    (1u << 9)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC16B_PWML3   (1u << 16) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA13A_MISO    (1u << 13) /**< \brief Spi signal: MISO */
+#define PIO_PA14A_MOSI    (1u << 14) /**< \brief Spi signal: MOSI */
+#define PIO_PA16A_NPCS0   (1u << 16) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA0B_NPCS1    (1u << 0)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PC3B_NPCS1    (1u << 3)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PC19B_NPCS1   (1u << 19) /**< \brief Spi signal: NPCS1 */
+#define PIO_PA1B_NPCS2    (1u << 1)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC4B_NPCS2    (1u << 4)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC14B_NPCS2   (1u << 14) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA19B_NPCS3   (1u << 19) /**< \brief Spi signal: NPCS3 */
+#define PIO_PC5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA15A_SPCK    (1u << 15) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA27A_RD      (1u << 27) /**< \brief Ssc signal: RD */
+#define PIO_PA31A_RF      (1u << 31) /**< \brief Ssc signal: RF */
+#define PIO_PA29A_RK      (1u << 29) /**< \brief Ssc signal: RK */
+#define PIO_PA26A_TD      (1u << 26) /**< \brief Ssc signal: TD */
+#define PIO_PA30A_TF      (1u << 30) /**< \brief Ssc signal: TF */
+#define PIO_PA28A_TK      (1u << 28) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA2A_TCLK0    (1u << 2)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PB4A_TCLK1    (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA26B_TCLK2   (1u << 26) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA1A_TIOA0    (1u << 1)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PB5A_TIOA1    (1u << 5)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA30B_TIOA2   (1u << 30) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA0A_TIOB0    (1u << 0)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PB6A_TIOB1    (1u << 6)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA31B_TIOB2   (1u << 31) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA10A_TWCK0   (1u << 10) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA9A_TWD0     (1u << 9)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PA25A_TWCK1   (1u << 25) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PA24A_TWD1    (1u << 24) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA11A_URXD    (1u << 11) /**< \brief Uart signal: URXD */
+#define PIO_PA12A_UTXD    (1u << 12) /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB11B_DCD0    (1u << 11) /**< \brief Usart0 signal: DCD0 */
+#define PIO_PB10B_DSR0    (1u << 10) /**< \brief Usart0 signal: DSR0 */
+#define PIO_PB9B_DTR0     (1u << 9)  /**< \brief Usart0 signal: DTR0 */
+#define PIO_PB12B_RI0     (1u << 12) /**< \brief Usart0 signal: RI0 */
+#define PIO_PB7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA19A_RXD0    (1u << 19) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17A_SCK0    (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA18A_TXD0    (1u << 18) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA23B_CTS1    (1u << 23) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA22B_RTS1    (1u << 22) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA24B_SCK1    (1u << 24) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA20A_TXD1    (1u << 20) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB22B_CTS2    (1u << 22) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB21B_RTS2    (1u << 21) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PA23A_RXD2    (1u << 23) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PA25B_SCK2    (1u << 25) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PA22A_TXD2    (1u << 22) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+#define PIO_PB15_IDX      47
+#define PIO_PB16_IDX      48
+#define PIO_PB17_IDX      49
+#define PIO_PB18_IDX      50
+#define PIO_PB19_IDX      51
+#define PIO_PB20_IDX      52
+#define PIO_PB21_IDX      53
+#define PIO_PB22_IDX      54
+#define PIO_PB23_IDX      55
+#define PIO_PB24_IDX      56
+
+#endif /* _SAM3U4C_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/pio/pio_sam3u4e.h b/hardware/sam/system/libsam/cmsis/sam3u/include/pio/pio_sam3u4e.h
new file mode 100644
index 000000000..8c8fd7a41
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/pio/pio_sam3u4e.h
@@ -0,0 +1,440 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U4E_PIO_
+#define _SAM3U4E_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15          (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16          (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17          (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18          (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19          (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20          (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21          (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22          (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23          (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24          (1u << 24) /**< \brief Pin Controlled by PB24 */
+#define PIO_PB25          (1u << 25) /**< \brief Pin Controlled by PB25 */
+#define PIO_PB26          (1u << 26) /**< \brief Pin Controlled by PB26 */
+#define PIO_PB27          (1u << 27) /**< \brief Pin Controlled by PB27 */
+#define PIO_PB28          (1u << 28) /**< \brief Pin Controlled by PB28 */
+#define PIO_PB29          (1u << 29) /**< \brief Pin Controlled by PB29 */
+#define PIO_PB30          (1u << 30) /**< \brief Pin Controlled by PB30 */
+#define PIO_PB31          (1u << 31) /**< \brief Pin Controlled by PB31 */
+#define PIO_PC0           (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1           (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2           (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3           (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4           (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5           (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6           (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7           (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8           (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9           (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10          (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11          (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12          (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13          (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14          (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15          (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16          (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17          (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18          (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19          (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20          (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21          (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22          (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23          (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24          (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25          (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26          (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27          (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28          (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29          (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30          (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31          (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PB5X1_AD0     (1u << 5)  /**< \brief Adc signal: AD0 */
+#define PIO_PB6X1_AD1     (1u << 6)  /**< \brief Adc signal: AD1 */
+#define PIO_PB7X1_AD2     (1u << 7)  /**< \brief Adc signal: AD2 */
+#define PIO_PB8X1_AD3     (1u << 8)  /**< \brief Adc signal: AD3 */
+#define PIO_PC28X1_AD4    (1u << 28) /**< \brief Adc signal: AD4 */
+#define PIO_PC29X1_AD5    (1u << 29) /**< \brief Adc signal: AD5 */
+#define PIO_PC30X1_AD6    (1u << 30) /**< \brief Adc signal: AD6 */
+#define PIO_PC31X1_AD7    (1u << 31) /**< \brief Adc signal: AD7 */
+#define PIO_PA17B_ADTRG   (1u << 17) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for ADC12B peripheral ========== */
+#define PIO_PA22X1_AD12B0 (1u << 22) /**< \brief Adc12b signal: AD12B0 */
+#define PIO_PA30X1_AD12B1 (1u << 30) /**< \brief Adc12b signal: AD12B1 */
+#define PIO_PB3X1_AD12B2  (1u << 3)  /**< \brief Adc12b signal: AD12B2 */
+#define PIO_PB4X1_AD12B3  (1u << 4)  /**< \brief Adc12b signal: AD12B3 */
+#define PIO_PC15X1_AD12B4 (1u << 15) /**< \brief Adc12b signal: AD12B4 */
+#define PIO_PC16X1_AD12B5 (1u << 16) /**< \brief Adc12b signal: AD12B5 */
+#define PIO_PC17X1_AD12B6 (1u << 17) /**< \brief Adc12b signal: AD12B6 */
+#define PIO_PC18X1_AD12B7 (1u << 18) /**< \brief Adc12b signal: AD12B7 */
+#define PIO_PA2B_AD12BTRG (1u << 2)  /**< \brief Adc12b signal: AD12BTRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PB7B_A0       (1u << 7)  /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PB7B_NBS0     (1u << 7)  /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PB8B_A1       (1u << 8)  /**< \brief Ebi signal: A1 */
+#define PIO_PC8A_A10      (1u << 8)  /**< \brief Ebi signal: A10 */
+#define PIO_PC9A_A11      (1u << 9)  /**< \brief Ebi signal: A11 */
+#define PIO_PC10A_A12     (1u << 10) /**< \brief Ebi signal: A12 */
+#define PIO_PC11A_A13     (1u << 11) /**< \brief Ebi signal: A13 */
+#define PIO_PC20A_A14     (1u << 20) /**< \brief Ebi signal: A14 */
+#define PIO_PC21A_A15     (1u << 21) /**< \brief Ebi signal: A15 */
+#define PIO_PC22A_A16     (1u << 22) /**< \brief Ebi signal: A16 */
+#define PIO_PC23A_A17     (1u << 23) /**< \brief Ebi signal: A17 */
+#define PIO_PC24A_A18     (1u << 24) /**< \brief Ebi signal: A18 */
+#define PIO_PC25A_A19     (1u << 25) /**< \brief Ebi signal: A19 */
+#define PIO_PB0B_A2       (1u << 0)  /**< \brief Ebi signal: A2 */
+#define PIO_PC0A_A2       (1u << 0)  /**< \brief Ebi signal: A2 */
+#define PIO_PC13A_A2      (1u << 13) /**< \brief Ebi signal: A2 */
+#define PIO_PC26A_A20     (1u << 26) /**< \brief Ebi signal: A20 */
+#define PIO_PB21A_A21     (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PB21A_NANDALE (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PB22A_A22     (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PB22A_NANDCLE (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PC27A_A23     (1u << 27) /**< \brief Ebi signal: A23 */
+#define PIO_PB1B_A3       (1u << 1)  /**< \brief Ebi signal: A3 */
+#define PIO_PC1A_A3       (1u << 1)  /**< \brief Ebi signal: A3 */
+#define PIO_PC14A_A3      (1u << 14) /**< \brief Ebi signal: A3 */
+#define PIO_PB2B_A4       (1u << 2)  /**< \brief Ebi signal: A4 */
+#define PIO_PC2A_A4       (1u << 2)  /**< \brief Ebi signal: A4 */
+#define PIO_PB3B_A5       (1u << 3)  /**< \brief Ebi signal: A5 */
+#define PIO_PC3A_A5       (1u << 3)  /**< \brief Ebi signal: A5 */
+#define PIO_PB4B_A6       (1u << 4)  /**< \brief Ebi signal: A6 */
+#define PIO_PC4A_A6       (1u << 4)  /**< \brief Ebi signal: A6 */
+#define PIO_PB5B_A7       (1u << 5)  /**< \brief Ebi signal: A7 */
+#define PIO_PC5A_A7       (1u << 5)  /**< \brief Ebi signal: A7 */
+#define PIO_PC6A_A8       (1u << 6)  /**< \brief Ebi signal: A8 */
+#define PIO_PC7A_A9       (1u << 7)  /**< \brief Ebi signal: A9 */
+#define PIO_PB9A_D0       (1u << 9)  /**< \brief Ebi signal: D0 */
+#define PIO_PB10A_D1      (1u << 10) /**< \brief Ebi signal: D1 */
+#define PIO_PB27A_D10     (1u << 27) /**< \brief Ebi signal: D10 */
+#define PIO_PB28A_D11     (1u << 28) /**< \brief Ebi signal: D11 */
+#define PIO_PB29A_D12     (1u << 29) /**< \brief Ebi signal: D12 */
+#define PIO_PB30A_D13     (1u << 30) /**< \brief Ebi signal: D13 */
+#define PIO_PB31A_D14     (1u << 31) /**< \brief Ebi signal: D14 */
+#define PIO_PB6B_D15      (1u << 6)  /**< \brief Ebi signal: D15 */
+#define PIO_PB11A_D2      (1u << 11) /**< \brief Ebi signal: D2 */
+#define PIO_PB12A_D3      (1u << 12) /**< \brief Ebi signal: D3 */
+#define PIO_PB13A_D4      (1u << 13) /**< \brief Ebi signal: D4 */
+#define PIO_PB14A_D5      (1u << 14) /**< \brief Ebi signal: D5 */
+#define PIO_PB15A_D6      (1u << 15) /**< \brief Ebi signal: D6 */
+#define PIO_PB16A_D7      (1u << 16) /**< \brief Ebi signal: D7 */
+#define PIO_PB25A_D8      (1u << 25) /**< \brief Ebi signal: D8 */
+#define PIO_PB26A_D9      (1u << 26) /**< \brief Ebi signal: D9 */
+#define PIO_PB17A_NANDOE  (1u << 17) /**< \brief Ebi signal: NANDOE */
+#define PIO_PB24A_NANDRDY (1u << 24) /**< \brief Ebi signal: NANDRDY */
+#define PIO_PB18A_NANDWE  (1u << 18) /**< \brief Ebi signal: NANDWE */
+#define PIO_PB20A_NCS0    (1u << 20) /**< \brief Ebi signal: NCS0 */
+#define PIO_PA16B_NCS1    (1u << 16) /**< \brief Ebi signal: NCS1 */
+#define PIO_PC12A_NCS1    (1u << 12) /**< \brief Ebi signal: NCS1 */
+#define PIO_PC16A_NCS2    (1u << 16) /**< \brief Ebi signal: NCS2 */
+#define PIO_PC17A_NCS3    (1u << 17) /**< \brief Ebi signal: NCS3 */
+#define PIO_PB19A_NRD     (1u << 19) /**< \brief Ebi signal: NRD */
+#define PIO_PC18A_NWAIT   (1u << 18) /**< \brief Ebi signal: NWAIT */
+#define PIO_PB23A_NWR0    (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PB23A_NWE     (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PC15A_NWR1    (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
+#define PIO_PC15A_NBS1    (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA4A_MCCDA    (1u << 4)  /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA3A_MCCK     (1u << 3)  /**< \brief Hsmci signal: MCCK */
+#define PIO_PA5A_MCDA0    (1u << 5)  /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA6A_MCDA1    (1u << 6)  /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA7A_MCDA2    (1u << 7)  /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA8A_MCDA3    (1u << 8)  /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PC28B_MCDA4   (1u << 28) /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PC29B_MCDA5   (1u << 29) /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PC30B_MCDA6   (1u << 30) /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PC31B_MCDA7   (1u << 31) /**< \brief Hsmci signal: MCDA7 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA21B_PCK0    (1u << 21) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA27B_PCK0    (1u << 27) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA3B_PCK1     (1u << 3)  /**< \brief Pmc signal: PCK1 */
+#define PIO_PB24B_PCK1    (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PB23B_PCK2    (1u << 23) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA11B_PWMFI0  (1u << 11) /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA12B_PWMFI1  (1u << 12) /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PA18B_PWMFI2  (1u << 18) /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA4B_PWMH0    (1u << 4)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA28B_PWMH0   (1u << 28) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0    (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB13B_PWMH0   (1u << 13) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC24B_PWMH0   (1u << 24) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA5B_PWMH1    (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA29B_PWMH1   (1u << 29) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1    (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB14B_PWMH1   (1u << 14) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC25B_PWMH1   (1u << 25) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA6B_PWMH2    (1u << 6)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA15B_PWMH2   (1u << 15) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB2A_PWMH2    (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB15B_PWMH2   (1u << 15) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC26B_PWMH2   (1u << 26) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA20B_PWMH3   (1u << 20) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB3A_PWMH3    (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB16B_PWMH3   (1u << 16) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC27B_PWMH3   (1u << 27) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA7B_PWML0    (1u << 7)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PB17B_PWML0   (1u << 17) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB25B_PWML0   (1u << 25) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC6B_PWML0    (1u << 6)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC29A_PWML0   (1u << 29) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA8B_PWML1    (1u << 8)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PB18B_PWML1   (1u << 18) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB26B_PWML1   (1u << 26) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC7B_PWML1    (1u << 7)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC30A_PWML1   (1u << 30) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA9B_PWML2    (1u << 9)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PB19B_PWML2   (1u << 19) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB27B_PWML2   (1u << 27) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC8B_PWML2    (1u << 8)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PC31A_PWML2   (1u << 31) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA10B_PWML3   (1u << 10) /**< \brief Pwm signal: PWML3 */
+#define PIO_PB20B_PWML3   (1u << 20) /**< \brief Pwm signal: PWML3 */
+#define PIO_PB28B_PWML3   (1u << 28) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC9B_PWML3    (1u << 9)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC16B_PWML3   (1u << 16) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA13A_MISO    (1u << 13) /**< \brief Spi signal: MISO */
+#define PIO_PA14A_MOSI    (1u << 14) /**< \brief Spi signal: MOSI */
+#define PIO_PA16A_NPCS0   (1u << 16) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA0B_NPCS1    (1u << 0)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PC3B_NPCS1    (1u << 3)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PC19B_NPCS1   (1u << 19) /**< \brief Spi signal: NPCS1 */
+#define PIO_PA1B_NPCS2    (1u << 1)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC4B_NPCS2    (1u << 4)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC14B_NPCS2   (1u << 14) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA19B_NPCS3   (1u << 19) /**< \brief Spi signal: NPCS3 */
+#define PIO_PC5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA15A_SPCK    (1u << 15) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA27A_RD      (1u << 27) /**< \brief Ssc signal: RD */
+#define PIO_PA31A_RF      (1u << 31) /**< \brief Ssc signal: RF */
+#define PIO_PA29A_RK      (1u << 29) /**< \brief Ssc signal: RK */
+#define PIO_PA26A_TD      (1u << 26) /**< \brief Ssc signal: TD */
+#define PIO_PA30A_TF      (1u << 30) /**< \brief Ssc signal: TF */
+#define PIO_PA28A_TK      (1u << 28) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA2A_TCLK0    (1u << 2)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PB4A_TCLK1    (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA26B_TCLK2   (1u << 26) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA1A_TIOA0    (1u << 1)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PB5A_TIOA1    (1u << 5)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA30B_TIOA2   (1u << 30) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA0A_TIOB0    (1u << 0)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PB6A_TIOB1    (1u << 6)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA31B_TIOB2   (1u << 31) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA10A_TWCK0   (1u << 10) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA9A_TWD0     (1u << 9)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PA25A_TWCK1   (1u << 25) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PA24A_TWD1    (1u << 24) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA11A_URXD    (1u << 11) /**< \brief Uart signal: URXD */
+#define PIO_PA12A_UTXD    (1u << 12) /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB11B_DCD0    (1u << 11) /**< \brief Usart0 signal: DCD0 */
+#define PIO_PB10B_DSR0    (1u << 10) /**< \brief Usart0 signal: DSR0 */
+#define PIO_PB9B_DTR0     (1u << 9)  /**< \brief Usart0 signal: DTR0 */
+#define PIO_PB12B_RI0     (1u << 12) /**< \brief Usart0 signal: RI0 */
+#define PIO_PB7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA19A_RXD0    (1u << 19) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17A_SCK0    (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA18A_TXD0    (1u << 18) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA23B_CTS1    (1u << 23) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA22B_RTS1    (1u << 22) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA24B_SCK1    (1u << 24) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA20A_TXD1    (1u << 20) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB22B_CTS2    (1u << 22) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB21B_RTS2    (1u << 21) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PA23A_RXD2    (1u << 23) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PA25B_SCK2    (1u << 25) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PA22A_TXD2    (1u << 22) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio definition for USART3 peripheral ========== */
+#define PIO_PC10B_CTS3    (1u << 10) /**< \brief Usart3 signal: CTS3 */
+#define PIO_PC11B_RTS3    (1u << 11) /**< \brief Usart3 signal: RTS3 */
+#define PIO_PC13B_RXD3    (1u << 13) /**< \brief Usart3 signal: RXD3 */
+#define PIO_PC19A_SCK3    (1u << 19) /**< \brief Usart3 signal: SCK3 */
+#define PIO_PC12B_TXD3    (1u << 12) /**< \brief Usart3 signal: TXD3 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+#define PIO_PB15_IDX      47
+#define PIO_PB16_IDX      48
+#define PIO_PB17_IDX      49
+#define PIO_PB18_IDX      50
+#define PIO_PB19_IDX      51
+#define PIO_PB20_IDX      52
+#define PIO_PB21_IDX      53
+#define PIO_PB22_IDX      54
+#define PIO_PB23_IDX      55
+#define PIO_PB24_IDX      56
+#define PIO_PB25_IDX      57
+#define PIO_PB26_IDX      58
+#define PIO_PB27_IDX      59
+#define PIO_PB28_IDX      60
+#define PIO_PB29_IDX      61
+#define PIO_PB30_IDX      62
+#define PIO_PB31_IDX      63
+#define PIO_PC0_IDX       64
+#define PIO_PC1_IDX       65
+#define PIO_PC2_IDX       66
+#define PIO_PC3_IDX       67
+#define PIO_PC4_IDX       68
+#define PIO_PC5_IDX       69
+#define PIO_PC6_IDX       70
+#define PIO_PC7_IDX       71
+#define PIO_PC8_IDX       72
+#define PIO_PC9_IDX       73
+#define PIO_PC10_IDX      74
+#define PIO_PC11_IDX      75
+#define PIO_PC12_IDX      76
+#define PIO_PC13_IDX      77
+#define PIO_PC14_IDX      78
+#define PIO_PC15_IDX      79
+#define PIO_PC16_IDX      80
+#define PIO_PC17_IDX      81
+#define PIO_PC18_IDX      82
+#define PIO_PC19_IDX      83
+#define PIO_PC20_IDX      84
+#define PIO_PC21_IDX      85
+#define PIO_PC22_IDX      86
+#define PIO_PC23_IDX      87
+#define PIO_PC24_IDX      88
+#define PIO_PC25_IDX      89
+#define PIO_PC26_IDX      90
+#define PIO_PC27_IDX      91
+#define PIO_PC28_IDX      92
+#define PIO_PC29_IDX      93
+#define PIO_PC30_IDX      94
+#define PIO_PC31_IDX      95
+
+#endif /* _SAM3U4E_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u.h b/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u.h
new file mode 100644
index 000000000..856c3b1d4
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u.h
@@ -0,0 +1,49 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_
+#define _SAM3U_
+
+#if defined __SAM3U1C__
+  #include "sam3u1c.h"
+#elif defined __SAM3U1E__
+  #include "sam3u1e.h"
+#elif defined __SAM3U2C__
+  #include "sam3u2c.h"
+#elif defined __SAM3U2E__
+  #include "sam3u2e.h"
+#elif defined __SAM3U4C__
+  #include "sam3u4c.h"
+#elif defined __SAM3U4E__
+  #include "sam3u4e.h"
+#else
+  #error Library does not support the specified device.
+#endif
+
+#endif /* _SAM3U_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u1c.h b/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u1c.h
new file mode 100644
index 000000000..5dc98fbc8
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u1c.h
@@ -0,0 +1,367 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U1C_
+#define _SAM3U1C_
+
+/** \addtogroup SAM3U1C_definitions SAM3U1C definitions
+  This file defines all structures and symbols for SAM3U1C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3U1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U1C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3U1C specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3U1C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3U1C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3U1C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3U1C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3U1C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3U1C Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3U1C Enhanced Embedded Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3U1C Enhanced Embedded Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3U1C Universal Asynchronous Receiver Transmitter (UART) */
+  SMC_IRQn             =  9, /**<  9 SAM3U1C Static Memory Controller (SMC) */
+  PIOA_IRQn            = 10, /**< 10 SAM3U1C Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 11, /**< 11 SAM3U1C Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 13, /**< 13 SAM3U1C USART 0 (USART0) */
+  USART1_IRQn          = 14, /**< 14 SAM3U1C USART 1 (USART1) */
+  USART2_IRQn          = 15, /**< 15 SAM3U1C USART 2 (USART2) */
+  HSMCI_IRQn           = 17, /**< 17 SAM3U1C High Speed Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 18, /**< 18 SAM3U1C Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 19, /**< 19 SAM3U1C Two-Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 20, /**< 20 SAM3U1C Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 21, /**< 21 SAM3U1C Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 22, /**< 22 SAM3U1C Timer Counter 0 (TC0) */
+  TC1_IRQn             = 23, /**< 23 SAM3U1C Timer Counter 1 (TC1) */
+  TC2_IRQn             = 24, /**< 24 SAM3U1C Timer Counter 2 (TC2) */
+  PWM_IRQn             = 25, /**< 25 SAM3U1C Pulse Width Modulation Controller (PWM) */
+  ADC12B_IRQn          = 26, /**< 26 SAM3U1C 12-bit ADC Controller (ADC12B) */
+  ADC_IRQn             = 27, /**< 27 SAM3U1C 10-bit ADC Controller (ADC) */
+  DMAC_IRQn            = 28, /**< 28 SAM3U1C DMA Controller (DMAC) */
+  UDPHS_IRQn           = 29  /**< 29 SAM3U1C USB Device High Speed (UDPHS) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3U1C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3U1C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3U1C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3U1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U1C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_adc12b.h"
+#include "component/component_chipid.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udphs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3U1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U1C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_udphs.h"
+#include "instance/instance_adc12b.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3U1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U1C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Embedded Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART) */
+#define ID_SMC    ( 9) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (10) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (11) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
+#define ID_HSMCI  (17) /**< \brief High Speed Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (18) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (19) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI    (20) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (21) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (22) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (23) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (24) /**< \brief Timer Counter 2 (TC2) */
+#define ID_PWM    (25) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC12B (26) /**< \brief 12-bit ADC Controller (ADC12B) */
+#define ID_ADC    (27) /**< \brief 10-bit ADC Controller (ADC) */
+#define ID_DMAC   (28) /**< \brief DMA Controller (DMAC) */
+#define ID_UDPHS  (29) /**< \brief USB Device High Speed (UDPHS) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3U1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U1C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40084000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40084100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40088000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40088100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x4008C000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x4008C100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40090000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40090100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40094000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40094100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x40098000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x40098100U) /**< \brief (PDC_USART2) Base Address */
+#define UDPHS      (0x400A4000U) /**< \brief (UDPHS     ) Base Address */
+#define ADC12B     (0x400A8000U) /**< \brief (ADC12B    ) Base Address */
+#define PDC_ADC12B (0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
+#define ADC        (0x400AC000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400AC100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400B0000U) /**< \brief (DMAC      ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0600U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0700U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0800U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0A00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0C00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E0E00U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1200U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1210U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1230U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1250U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1260U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1290U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40084000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40084100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40088000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40088100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x4008C000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x4008C100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40090000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40090100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40094000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40094100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x40098000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART2) Base Address */
+#define UDPHS      ((Udphs  *)0x400A4000U) /**< \brief (UDPHS     ) Base Address */
+#define ADC12B     ((Adc12b *)0x400A8000U) /**< \brief (ADC12B    ) Base Address */
+#define PDC_ADC12B ((Pdc    *)0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
+#define ADC        ((Adc    *)0x400AC000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400AC100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400B0000U) /**< \brief (DMAC      ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0600U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0800U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0A00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0C00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E0E00U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1200U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1210U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1230U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1250U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1260U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1290U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3U1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U1C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3u1c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3U1C */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x10000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (8192u)
+#define IFLASH_NB_OF_PAGES      (32u)
+#define IRAM_SIZE               (0x5000u)
+
+#define IFLASH0_ADDR   (0x00080000u) /**< Internal Flash 0 base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR   (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IROM_ADDR      (0x00180000u) /**< Internal ROM base address */
+#define IRAM0_ADDR     (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR     (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR   (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UDPHS_RAM_ADDR (0x20180000u) /**< USB High Speed Device Port RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3U1C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (96000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3U1C_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u1e.h b/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u1e.h
new file mode 100644
index 000000000..94de4a863
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u1e.h
@@ -0,0 +1,379 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U1E_
+#define _SAM3U1E_
+
+/** \addtogroup SAM3U1E_definitions SAM3U1E definitions
+  This file defines all structures and symbols for SAM3U1E:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3U1E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U1E_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3U1E specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3U1E Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3U1E Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3U1E Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3U1E Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3U1E Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3U1E Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3U1E Enhanced Embedded Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3U1E Enhanced Embedded Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3U1E Universal Asynchronous Receiver Transmitter (UART) */
+  SMC_IRQn             =  9, /**<  9 SAM3U1E Static Memory Controller (SMC) */
+  PIOA_IRQn            = 10, /**< 10 SAM3U1E Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 11, /**< 11 SAM3U1E Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 12, /**< 12 SAM3U1E Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 13, /**< 13 SAM3U1E USART 0 (USART0) */
+  USART1_IRQn          = 14, /**< 14 SAM3U1E USART 1 (USART1) */
+  USART2_IRQn          = 15, /**< 15 SAM3U1E USART 2 (USART2) */
+  USART3_IRQn          = 16, /**< 16 SAM3U1E USART 3 (USART3) */
+  HSMCI_IRQn           = 17, /**< 17 SAM3U1E High Speed Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 18, /**< 18 SAM3U1E Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 19, /**< 19 SAM3U1E Two-Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 20, /**< 20 SAM3U1E Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 21, /**< 21 SAM3U1E Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 22, /**< 22 SAM3U1E Timer Counter 0 (TC0) */
+  TC1_IRQn             = 23, /**< 23 SAM3U1E Timer Counter 1 (TC1) */
+  TC2_IRQn             = 24, /**< 24 SAM3U1E Timer Counter 2 (TC2) */
+  PWM_IRQn             = 25, /**< 25 SAM3U1E Pulse Width Modulation Controller (PWM) */
+  ADC12B_IRQn          = 26, /**< 26 SAM3U1E 12-bit ADC Controller (ADC12B) */
+  ADC_IRQn             = 27, /**< 27 SAM3U1E 10-bit ADC Controller (ADC) */
+  DMAC_IRQn            = 28, /**< 28 SAM3U1E DMA Controller (DMAC) */
+  UDPHS_IRQn           = 29  /**< 29 SAM3U1E USB Device High Speed (UDPHS) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3U1E core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3U1E does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3U1E uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3U1E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U1E_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_adc12b.h"
+#include "component/component_chipid.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udphs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3U1E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U1E_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_usart3.h"
+#include "instance/instance_udphs.h"
+#include "instance/instance_adc12b.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3U1E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U1E_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Embedded Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART) */
+#define ID_SMC    ( 9) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (10) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (11) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (12) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
+#define ID_USART3 (16) /**< \brief USART 3 (USART3) */
+#define ID_HSMCI  (17) /**< \brief High Speed Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (18) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (19) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI    (20) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (21) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (22) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (23) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (24) /**< \brief Timer Counter 2 (TC2) */
+#define ID_PWM    (25) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC12B (26) /**< \brief 12-bit ADC Controller (ADC12B) */
+#define ID_ADC    (27) /**< \brief 10-bit ADC Controller (ADC) */
+#define ID_DMAC   (28) /**< \brief DMA Controller (DMAC) */
+#define ID_UDPHS  (29) /**< \brief USB Device High Speed (UDPHS) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3U1E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U1E_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40084000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40084100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40088000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40088100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x4008C000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x4008C100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40090000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40090100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40094000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40094100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x40098000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x40098100U) /**< \brief (PDC_USART2) Base Address */
+#define USART3     (0x4009C000U) /**< \brief (USART3    ) Base Address */
+#define PDC_USART3 (0x4009C100U) /**< \brief (PDC_USART3) Base Address */
+#define UDPHS      (0x400A4000U) /**< \brief (UDPHS     ) Base Address */
+#define ADC12B     (0x400A8000U) /**< \brief (ADC12B    ) Base Address */
+#define PDC_ADC12B (0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
+#define ADC        (0x400AC000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400AC100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400B0000U) /**< \brief (DMAC      ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0600U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0700U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0800U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0A00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0C00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E0E00U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1000U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1200U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1210U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1230U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1250U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1260U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1290U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40084000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40084100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40088000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40088100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x4008C000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x4008C100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40090000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40090100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40094000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40094100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x40098000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART2) Base Address */
+#define USART3     ((Usart  *)0x4009C000U) /**< \brief (USART3    ) Base Address */
+#define PDC_USART3 ((Pdc    *)0x4009C100U) /**< \brief (PDC_USART3) Base Address */
+#define UDPHS      ((Udphs  *)0x400A4000U) /**< \brief (UDPHS     ) Base Address */
+#define ADC12B     ((Adc12b *)0x400A8000U) /**< \brief (ADC12B    ) Base Address */
+#define PDC_ADC12B ((Pdc    *)0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
+#define ADC        ((Adc    *)0x400AC000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400AC100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400B0000U) /**< \brief (DMAC      ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0600U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0800U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0A00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0C00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E0E00U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1000U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1200U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1210U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1230U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1250U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1260U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1290U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3U1E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U1E_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3u1e.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3U1E */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x10000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (8192u)
+#define IFLASH_NB_OF_PAGES      (32u)
+#define IRAM_SIZE               (0x5000u)
+
+#define IFLASH0_ADDR   (0x00080000u) /**< Internal Flash 0 base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR   (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IROM_ADDR      (0x00180000u) /**< Internal ROM base address */
+#define IRAM0_ADDR     (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR     (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR   (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UDPHS_RAM_ADDR (0x20180000u) /**< USB High Speed Device Port RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3U1E */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (96000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3U1E_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u2c.h b/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u2c.h
new file mode 100644
index 000000000..53f0331e4
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u2c.h
@@ -0,0 +1,367 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U2C_
+#define _SAM3U2C_
+
+/** \addtogroup SAM3U2C_definitions SAM3U2C definitions
+  This file defines all structures and symbols for SAM3U2C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3U2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3U2C specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3U2C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3U2C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3U2C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3U2C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3U2C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3U2C Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3U2C Enhanced Embedded Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3U2C Enhanced Embedded Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3U2C Universal Asynchronous Receiver Transmitter (UART) */
+  SMC_IRQn             =  9, /**<  9 SAM3U2C Static Memory Controller (SMC) */
+  PIOA_IRQn            = 10, /**< 10 SAM3U2C Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 11, /**< 11 SAM3U2C Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 13, /**< 13 SAM3U2C USART 0 (USART0) */
+  USART1_IRQn          = 14, /**< 14 SAM3U2C USART 1 (USART1) */
+  USART2_IRQn          = 15, /**< 15 SAM3U2C USART 2 (USART2) */
+  HSMCI_IRQn           = 17, /**< 17 SAM3U2C High Speed Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 18, /**< 18 SAM3U2C Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 19, /**< 19 SAM3U2C Two-Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 20, /**< 20 SAM3U2C Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 21, /**< 21 SAM3U2C Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 22, /**< 22 SAM3U2C Timer Counter 0 (TC0) */
+  TC1_IRQn             = 23, /**< 23 SAM3U2C Timer Counter 1 (TC1) */
+  TC2_IRQn             = 24, /**< 24 SAM3U2C Timer Counter 2 (TC2) */
+  PWM_IRQn             = 25, /**< 25 SAM3U2C Pulse Width Modulation Controller (PWM) */
+  ADC12B_IRQn          = 26, /**< 26 SAM3U2C 12-bit ADC Controller (ADC12B) */
+  ADC_IRQn             = 27, /**< 27 SAM3U2C 10-bit ADC Controller (ADC) */
+  DMAC_IRQn            = 28, /**< 28 SAM3U2C DMA Controller (DMAC) */
+  UDPHS_IRQn           = 29  /**< 29 SAM3U2C USB Device High Speed (UDPHS) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3U2C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3U2C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3U2C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3U2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_adc12b.h"
+#include "component/component_chipid.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udphs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3U2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_udphs.h"
+#include "instance/instance_adc12b.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3U2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Embedded Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART) */
+#define ID_SMC    ( 9) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (10) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (11) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
+#define ID_HSMCI  (17) /**< \brief High Speed Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (18) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (19) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI    (20) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (21) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (22) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (23) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (24) /**< \brief Timer Counter 2 (TC2) */
+#define ID_PWM    (25) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC12B (26) /**< \brief 12-bit ADC Controller (ADC12B) */
+#define ID_ADC    (27) /**< \brief 10-bit ADC Controller (ADC) */
+#define ID_DMAC   (28) /**< \brief DMA Controller (DMAC) */
+#define ID_UDPHS  (29) /**< \brief USB Device High Speed (UDPHS) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3U2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40084000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40084100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40088000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40088100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x4008C000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x4008C100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40090000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40090100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40094000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40094100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x40098000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x40098100U) /**< \brief (PDC_USART2) Base Address */
+#define UDPHS      (0x400A4000U) /**< \brief (UDPHS     ) Base Address */
+#define ADC12B     (0x400A8000U) /**< \brief (ADC12B    ) Base Address */
+#define PDC_ADC12B (0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
+#define ADC        (0x400AC000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400AC100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400B0000U) /**< \brief (DMAC      ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0600U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0700U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0800U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0A00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0C00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E0E00U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1200U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1210U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1230U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1250U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1260U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1290U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40084000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40084100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40088000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40088100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x4008C000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x4008C100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40090000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40090100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40094000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40094100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x40098000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART2) Base Address */
+#define UDPHS      ((Udphs  *)0x400A4000U) /**< \brief (UDPHS     ) Base Address */
+#define ADC12B     ((Adc12b *)0x400A8000U) /**< \brief (ADC12B    ) Base Address */
+#define PDC_ADC12B ((Pdc    *)0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
+#define ADC        ((Adc    *)0x400AC000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400AC100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400B0000U) /**< \brief (DMAC      ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0600U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0800U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0A00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0C00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E0E00U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1200U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1210U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1230U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1250U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1260U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1290U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3U2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3u2c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3U2C */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x20000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (8192u)
+#define IFLASH_NB_OF_PAGES      (64u)
+#define IRAM_SIZE               (0x9000u)
+
+#define IFLASH0_ADDR   (0x00080000u) /**< Internal Flash 0 base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR   (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IROM_ADDR      (0x00180000u) /**< Internal ROM base address */
+#define IRAM0_ADDR     (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR     (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR   (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UDPHS_RAM_ADDR (0x20180000u) /**< USB High Speed Device Port RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3U2C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (96000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3U2C_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u2e.h b/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u2e.h
new file mode 100644
index 000000000..bda7dae88
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u2e.h
@@ -0,0 +1,379 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U2E_
+#define _SAM3U2E_
+
+/** \addtogroup SAM3U2E_definitions SAM3U2E definitions
+  This file defines all structures and symbols for SAM3U2E:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3U2E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2E_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3U2E specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3U2E Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3U2E Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3U2E Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3U2E Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3U2E Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3U2E Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3U2E Enhanced Embedded Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3U2E Enhanced Embedded Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3U2E Universal Asynchronous Receiver Transmitter (UART) */
+  SMC_IRQn             =  9, /**<  9 SAM3U2E Static Memory Controller (SMC) */
+  PIOA_IRQn            = 10, /**< 10 SAM3U2E Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 11, /**< 11 SAM3U2E Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 12, /**< 12 SAM3U2E Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 13, /**< 13 SAM3U2E USART 0 (USART0) */
+  USART1_IRQn          = 14, /**< 14 SAM3U2E USART 1 (USART1) */
+  USART2_IRQn          = 15, /**< 15 SAM3U2E USART 2 (USART2) */
+  USART3_IRQn          = 16, /**< 16 SAM3U2E USART 3 (USART3) */
+  HSMCI_IRQn           = 17, /**< 17 SAM3U2E High Speed Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 18, /**< 18 SAM3U2E Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 19, /**< 19 SAM3U2E Two-Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 20, /**< 20 SAM3U2E Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 21, /**< 21 SAM3U2E Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 22, /**< 22 SAM3U2E Timer Counter 0 (TC0) */
+  TC1_IRQn             = 23, /**< 23 SAM3U2E Timer Counter 1 (TC1) */
+  TC2_IRQn             = 24, /**< 24 SAM3U2E Timer Counter 2 (TC2) */
+  PWM_IRQn             = 25, /**< 25 SAM3U2E Pulse Width Modulation Controller (PWM) */
+  ADC12B_IRQn          = 26, /**< 26 SAM3U2E 12-bit ADC Controller (ADC12B) */
+  ADC_IRQn             = 27, /**< 27 SAM3U2E 10-bit ADC Controller (ADC) */
+  DMAC_IRQn            = 28, /**< 28 SAM3U2E DMA Controller (DMAC) */
+  UDPHS_IRQn           = 29  /**< 29 SAM3U2E USB Device High Speed (UDPHS) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3U2E core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3U2E does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3U2E uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3U2E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2E_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_adc12b.h"
+#include "component/component_chipid.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udphs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3U2E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2E_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_usart3.h"
+#include "instance/instance_udphs.h"
+#include "instance/instance_adc12b.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3U2E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2E_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Embedded Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART) */
+#define ID_SMC    ( 9) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (10) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (11) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (12) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
+#define ID_USART3 (16) /**< \brief USART 3 (USART3) */
+#define ID_HSMCI  (17) /**< \brief High Speed Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (18) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (19) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI    (20) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (21) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (22) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (23) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (24) /**< \brief Timer Counter 2 (TC2) */
+#define ID_PWM    (25) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC12B (26) /**< \brief 12-bit ADC Controller (ADC12B) */
+#define ID_ADC    (27) /**< \brief 10-bit ADC Controller (ADC) */
+#define ID_DMAC   (28) /**< \brief DMA Controller (DMAC) */
+#define ID_UDPHS  (29) /**< \brief USB Device High Speed (UDPHS) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3U2E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2E_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40084000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40084100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40088000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40088100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x4008C000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x4008C100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40090000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40090100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40094000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40094100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x40098000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x40098100U) /**< \brief (PDC_USART2) Base Address */
+#define USART3     (0x4009C000U) /**< \brief (USART3    ) Base Address */
+#define PDC_USART3 (0x4009C100U) /**< \brief (PDC_USART3) Base Address */
+#define UDPHS      (0x400A4000U) /**< \brief (UDPHS     ) Base Address */
+#define ADC12B     (0x400A8000U) /**< \brief (ADC12B    ) Base Address */
+#define PDC_ADC12B (0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
+#define ADC        (0x400AC000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400AC100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400B0000U) /**< \brief (DMAC      ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0600U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0700U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0800U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0A00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0C00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E0E00U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1000U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1200U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1210U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1230U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1250U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1260U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1290U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40084000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40084100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40088000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40088100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x4008C000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x4008C100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40090000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40090100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40094000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40094100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x40098000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART2) Base Address */
+#define USART3     ((Usart  *)0x4009C000U) /**< \brief (USART3    ) Base Address */
+#define PDC_USART3 ((Pdc    *)0x4009C100U) /**< \brief (PDC_USART3) Base Address */
+#define UDPHS      ((Udphs  *)0x400A4000U) /**< \brief (UDPHS     ) Base Address */
+#define ADC12B     ((Adc12b *)0x400A8000U) /**< \brief (ADC12B    ) Base Address */
+#define PDC_ADC12B ((Pdc    *)0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
+#define ADC        ((Adc    *)0x400AC000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400AC100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400B0000U) /**< \brief (DMAC      ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0600U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0800U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0A00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0C00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E0E00U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1000U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1200U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1210U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1230U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1250U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1260U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1290U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3U2E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2E_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3u2e.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3U2E */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x20000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (8192u)
+#define IFLASH_NB_OF_PAGES      (64u)
+#define IRAM_SIZE               (0x9000u)
+
+#define IFLASH0_ADDR   (0x00080000u) /**< Internal Flash 0 base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR   (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IROM_ADDR      (0x00180000u) /**< Internal ROM base address */
+#define IRAM0_ADDR     (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR     (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR   (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UDPHS_RAM_ADDR (0x20180000u) /**< USB High Speed Device Port RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3U2E */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (96000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3U2E_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u4c.h b/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u4c.h
new file mode 100644
index 000000000..3f28f60a8
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u4c.h
@@ -0,0 +1,372 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U4C_
+#define _SAM3U4C_
+
+/** \addtogroup SAM3U4C_definitions SAM3U4C definitions
+  This file defines all structures and symbols for SAM3U4C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3U4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U4C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3U4C specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3U4C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3U4C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3U4C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3U4C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3U4C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3U4C Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3U4C Enhanced Embedded Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3U4C Enhanced Embedded Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3U4C Universal Asynchronous Receiver Transmitter (UART) */
+  SMC_IRQn             =  9, /**<  9 SAM3U4C Static Memory Controller (SMC) */
+  PIOA_IRQn            = 10, /**< 10 SAM3U4C Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 11, /**< 11 SAM3U4C Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 13, /**< 13 SAM3U4C USART 0 (USART0) */
+  USART1_IRQn          = 14, /**< 14 SAM3U4C USART 1 (USART1) */
+  USART2_IRQn          = 15, /**< 15 SAM3U4C USART 2 (USART2) */
+  HSMCI_IRQn           = 17, /**< 17 SAM3U4C High Speed Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 18, /**< 18 SAM3U4C Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 19, /**< 19 SAM3U4C Two-Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 20, /**< 20 SAM3U4C Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 21, /**< 21 SAM3U4C Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 22, /**< 22 SAM3U4C Timer Counter 0 (TC0) */
+  TC1_IRQn             = 23, /**< 23 SAM3U4C Timer Counter 1 (TC1) */
+  TC2_IRQn             = 24, /**< 24 SAM3U4C Timer Counter 2 (TC2) */
+  PWM_IRQn             = 25, /**< 25 SAM3U4C Pulse Width Modulation Controller (PWM) */
+  ADC12B_IRQn          = 26, /**< 26 SAM3U4C 12-bit ADC Controller (ADC12B) */
+  ADC_IRQn             = 27, /**< 27 SAM3U4C 10-bit ADC Controller (ADC) */
+  DMAC_IRQn            = 28, /**< 28 SAM3U4C DMA Controller (DMAC) */
+  UDPHS_IRQn           = 29  /**< 29 SAM3U4C USB Device High Speed (UDPHS) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3U4C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3U4C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3U4C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3U4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U4C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_adc12b.h"
+#include "component/component_chipid.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udphs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3U4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U4C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_udphs.h"
+#include "instance/instance_adc12b.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3U4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U4C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Embedded Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART) */
+#define ID_SMC    ( 9) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (10) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (11) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
+#define ID_HSMCI  (17) /**< \brief High Speed Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (18) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (19) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI    (20) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (21) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (22) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (23) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (24) /**< \brief Timer Counter 2 (TC2) */
+#define ID_PWM    (25) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC12B (26) /**< \brief 12-bit ADC Controller (ADC12B) */
+#define ID_ADC    (27) /**< \brief 10-bit ADC Controller (ADC) */
+#define ID_DMAC   (28) /**< \brief DMA Controller (DMAC) */
+#define ID_UDPHS  (29) /**< \brief USB Device High Speed (UDPHS) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3U4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U4C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40084000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40084100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40088000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40088100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x4008C000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x4008C100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40090000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40090100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40094000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40094100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x40098000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x40098100U) /**< \brief (PDC_USART2) Base Address */
+#define UDPHS      (0x400A4000U) /**< \brief (UDPHS     ) Base Address */
+#define ADC12B     (0x400A8000U) /**< \brief (ADC12B    ) Base Address */
+#define PDC_ADC12B (0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
+#define ADC        (0x400AC000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400AC100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400B0000U) /**< \brief (DMAC      ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0600U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0700U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0800U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0A00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0C00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E0E00U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1200U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1210U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1230U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1250U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1260U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1290U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40084000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40084100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40088000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40088100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x4008C000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x4008C100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40090000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40090100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40094000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40094100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x40098000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART2) Base Address */
+#define UDPHS      ((Udphs  *)0x400A4000U) /**< \brief (UDPHS     ) Base Address */
+#define ADC12B     ((Adc12b *)0x400A8000U) /**< \brief (ADC12B    ) Base Address */
+#define PDC_ADC12B ((Pdc    *)0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
+#define ADC        ((Adc    *)0x400AC000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400AC100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400B0000U) /**< \brief (DMAC      ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0600U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0800U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0A00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0C00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E0E00U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1200U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1210U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1230U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1250U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1260U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1290U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3U4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U4C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3u4c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3U4C */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x20000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (8192u)
+#define IFLASH0_NB_OF_PAGES      (64u)
+#define IFLASH1_SIZE             (0x20000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (8192u)
+#define IFLASH1_NB_OF_PAGES      (64u)
+#define IRAM_SIZE                (0xD000u)
+#define IFLASH_SIZE              (0x40000u)
+
+#define IFLASH0_ADDR   (0x00080000u) /**< Internal Flash 0 base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR   (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IROM_ADDR      (0x00180000u) /**< Internal ROM base address */
+#define IRAM0_ADDR     (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR     (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR   (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UDPHS_RAM_ADDR (0x20180000u) /**< USB High Speed Device Port RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3U4C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (96000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3U4C_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u4e.h b/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u4e.h
new file mode 100644
index 000000000..2d987d8ed
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u4e.h
@@ -0,0 +1,384 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U4E_
+#define _SAM3U4E_
+
+/** \addtogroup SAM3U4E_definitions SAM3U4E definitions
+  This file defines all structures and symbols for SAM3U4E:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3U4E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U4E_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3U4E specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3U4E Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3U4E Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3U4E Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3U4E Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3U4E Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3U4E Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3U4E Enhanced Embedded Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3U4E Enhanced Embedded Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3U4E Universal Asynchronous Receiver Transmitter (UART) */
+  SMC_IRQn             =  9, /**<  9 SAM3U4E Static Memory Controller (SMC) */
+  PIOA_IRQn            = 10, /**< 10 SAM3U4E Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 11, /**< 11 SAM3U4E Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 12, /**< 12 SAM3U4E Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 13, /**< 13 SAM3U4E USART 0 (USART0) */
+  USART1_IRQn          = 14, /**< 14 SAM3U4E USART 1 (USART1) */
+  USART2_IRQn          = 15, /**< 15 SAM3U4E USART 2 (USART2) */
+  USART3_IRQn          = 16, /**< 16 SAM3U4E USART 3 (USART3) */
+  HSMCI_IRQn           = 17, /**< 17 SAM3U4E High Speed Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 18, /**< 18 SAM3U4E Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 19, /**< 19 SAM3U4E Two-Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 20, /**< 20 SAM3U4E Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 21, /**< 21 SAM3U4E Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 22, /**< 22 SAM3U4E Timer Counter 0 (TC0) */
+  TC1_IRQn             = 23, /**< 23 SAM3U4E Timer Counter 1 (TC1) */
+  TC2_IRQn             = 24, /**< 24 SAM3U4E Timer Counter 2 (TC2) */
+  PWM_IRQn             = 25, /**< 25 SAM3U4E Pulse Width Modulation Controller (PWM) */
+  ADC12B_IRQn          = 26, /**< 26 SAM3U4E 12-bit ADC Controller (ADC12B) */
+  ADC_IRQn             = 27, /**< 27 SAM3U4E 10-bit ADC Controller (ADC) */
+  DMAC_IRQn            = 28, /**< 28 SAM3U4E DMA Controller (DMAC) */
+  UDPHS_IRQn           = 29  /**< 29 SAM3U4E USB Device High Speed (UDPHS) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3U4E core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3U4E does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3U4E uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3U4E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U4E_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_adc12b.h"
+#include "component/component_chipid.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udphs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3U4E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U4E_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_usart3.h"
+#include "instance/instance_udphs.h"
+#include "instance/instance_adc12b.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3U4E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U4E_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Embedded Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART) */
+#define ID_SMC    ( 9) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (10) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (11) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (12) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
+#define ID_USART3 (16) /**< \brief USART 3 (USART3) */
+#define ID_HSMCI  (17) /**< \brief High Speed Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (18) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (19) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI    (20) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (21) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (22) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (23) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (24) /**< \brief Timer Counter 2 (TC2) */
+#define ID_PWM    (25) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC12B (26) /**< \brief 12-bit ADC Controller (ADC12B) */
+#define ID_ADC    (27) /**< \brief 10-bit ADC Controller (ADC) */
+#define ID_DMAC   (28) /**< \brief DMA Controller (DMAC) */
+#define ID_UDPHS  (29) /**< \brief USB Device High Speed (UDPHS) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3U4E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U4E_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40084000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40084100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40088000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40088100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x4008C000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x4008C100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40090000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40090100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40094000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40094100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x40098000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x40098100U) /**< \brief (PDC_USART2) Base Address */
+#define USART3     (0x4009C000U) /**< \brief (USART3    ) Base Address */
+#define PDC_USART3 (0x4009C100U) /**< \brief (PDC_USART3) Base Address */
+#define UDPHS      (0x400A4000U) /**< \brief (UDPHS     ) Base Address */
+#define ADC12B     (0x400A8000U) /**< \brief (ADC12B    ) Base Address */
+#define PDC_ADC12B (0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
+#define ADC        (0x400AC000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400AC100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400B0000U) /**< \brief (DMAC      ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0600U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0700U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0800U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0A00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0C00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E0E00U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1000U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1200U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1210U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1230U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1250U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1260U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1290U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40084000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40084100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40088000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40088100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x4008C000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x4008C100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40090000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40090100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40094000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40094100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x40098000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART2) Base Address */
+#define USART3     ((Usart  *)0x4009C000U) /**< \brief (USART3    ) Base Address */
+#define PDC_USART3 ((Pdc    *)0x4009C100U) /**< \brief (PDC_USART3) Base Address */
+#define UDPHS      ((Udphs  *)0x400A4000U) /**< \brief (UDPHS     ) Base Address */
+#define ADC12B     ((Adc12b *)0x400A8000U) /**< \brief (ADC12B    ) Base Address */
+#define PDC_ADC12B ((Pdc    *)0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
+#define ADC        ((Adc    *)0x400AC000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400AC100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400B0000U) /**< \brief (DMAC      ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0600U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0800U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0A00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0C00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E0E00U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1000U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1200U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1210U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1230U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1250U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1260U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1290U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3U4E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U4E_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3u4e.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3U4E */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x20000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (8192u)
+#define IFLASH0_NB_OF_PAGES      (64u)
+#define IFLASH1_SIZE             (0x20000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (8192u)
+#define IFLASH1_NB_OF_PAGES      (64u)
+#define IRAM_SIZE                (0xD000u)
+#define IFLASH_SIZE              (0x40000u)
+
+#define IFLASH0_ADDR   (0x00080000u) /**< Internal Flash 0 base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR   (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IROM_ADDR      (0x00180000u) /**< Internal ROM base address */
+#define IRAM0_ADDR     (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR     (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR   (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UDPHS_RAM_ADDR (0x20180000u) /**< USB High Speed Device Port RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3U4E */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (96000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3U4E_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/source/templates/exceptions.c b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/exceptions.c
new file mode 100644
index 000000000..360160fda
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/exceptions.c
@@ -0,0 +1,139 @@
+/*! \file *********************************************************************
+ *
+ * \brief This file contains the default exception handlers.
+ *
+ * $asf_license$
+ *
+ * \par Purpose
+ *
+ * This file provides basic support for Cortex-M processor based 
+ * microcontrollers.
+ *
+ * \note
+ * The exception handler has weak aliases.
+ * As they are weak aliases, any function with the same name will override
+ * this definition.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+#include "exceptions.h"
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#ifdef __GNUC__
+/* Cortex-M3 core handlers */
+//void Reset_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
+void NMI_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+//void HardFault_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
+void MemManage_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SUPC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SMC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOA_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART2_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART3_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void MCI_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SSC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PWM_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void ADC12B_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void ADC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void DMAC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void UDPHS_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* __GNUC__ */
+
+#ifdef __ICCARM__
+/* Cortex-M3 core handlers */
+//#pragma weak Reset_Handler=Dummy_Handler
+#pragma weak NMI_Handler=Dummy_Handler
+//#pragma weak HardFault_Handler=Dummy_Handler
+#pragma weak MemManage_Handler=Dummy_Handler
+#pragma weak BusFault_Handler=Dummy_Handler
+#pragma weak UsageFault_Handler=Dummy_Handler
+#pragma weak SVC_Handler=Dummy_Handler
+#pragma weak DebugMon_Handler=Dummy_Handler
+#pragma weak PendSV_Handler=Dummy_Handler
+#pragma weak SysTick_Handler=Dummy_Handler
+
+/* Peripherals handlers */
+#pragma weak SUPC_IrqHandler=Dummy_Handler
+#pragma weak RSTC_IrqHandler=Dummy_Handler
+#pragma weak RTC_IrqHandler=Dummy_Handler
+#pragma weak RTT_IrqHandler=Dummy_Handler
+#pragma weak WDT_IrqHandler=Dummy_Handler
+#pragma weak PMC_IrqHandler=Dummy_Handler
+#pragma weak EFC0_IrqHandler=Dummy_Handler
+#pragma weak EFC1_IrqHandler=Dummy_Handler
+#pragma weak UART_IrqHandler=Dummy_Handler
+#pragma weak SMC_IrqHandler=Dummy_Handler
+#pragma weak PIOA_IrqHandler=Dummy_Handler
+#pragma weak PIOB_IrqHandler=Dummy_Handler
+#pragma weak PIOC_IrqHandler=Dummy_Handler
+#pragma weak USART0_IrqHandler=Dummy_Handler
+#pragma weak USART1_IrqHandler=Dummy_Handler
+#pragma weak USART2_IrqHandler=Dummy_Handler
+#pragma weak USART3_IrqHandler=Dummy_Handler
+#pragma weak MCI_IrqHandler=Dummy_Handler
+#pragma weak TWI0_IrqHandler=Dummy_Handler
+#pragma weak TWI1_IrqHandler=Dummy_Handler
+#pragma weak SPI_IrqHandler=Dummy_Handler
+#pragma weak SSC_IrqHandler=Dummy_Handler
+#pragma weak TC0_IrqHandler=Dummy_Handler
+#pragma weak TC1_IrqHandler=Dummy_Handler
+#pragma weak TC2_IrqHandler=Dummy_Handler
+#pragma weak PWM_IrqHandler=Dummy_Handler
+#pragma weak ADC12B_IrqHandler=Dummy_Handler
+#pragma weak ADC_IrqHandler=Dummy_Handler
+#pragma weak DMAC_IrqHandler=Dummy_Handler
+#pragma weak UDPHS_IrqHandler=Dummy_Handler
+#endif /* __ICCARM__ */
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/source/templates/exceptions.h b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/exceptions.h
new file mode 100644
index 000000000..caae7535a
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/exceptions.h
@@ -0,0 +1,86 @@
+/*! \file *********************************************************************
+ *
+ * \brief This file contains the interface for default exception handlers.
+ *
+ * $asf_license$
+ *
+ * \par Purpose
+ *
+ * This file provides basic support for Cortex-M processor based 
+ * microcontrollers.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+#ifndef EXCEPTIONS_H_INCLUDED
+#define EXCEPTIONS_H_INCLUDED
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+/* Function prototype for exception table items (interrupt handler). */
+typedef void (*IntFunc) (void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+void Reset_Handler(void);
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+
+/* Peripherals handlers */
+void SUPC_IrqHandler(void);
+void RSTC_IrqHandler(void);
+void RTC_IrqHandler(void);
+void RTT_IrqHandler(void);
+void WDT_IrqHandler(void);
+void PMC_IrqHandler(void);
+void EFC0_IrqHandler(void);
+void EFC1_IrqHandler(void);
+void UART_IrqHandler(void);
+void SMC_IrqHandler(void);
+void PIOA_IrqHandler(void);
+void PIOB_IrqHandler(void);
+void PIOC_IrqHandler(void);
+void USART0_IrqHandler(void);
+void USART1_IrqHandler(void);
+void USART2_IrqHandler(void);
+void USART3_IrqHandler(void);
+void MCI_IrqHandler(void);
+void TWI0_IrqHandler(void);
+void TWI1_IrqHandler(void);
+void SPI_IrqHandler(void);
+void SSC_IrqHandler(void);
+void TC0_IrqHandler(void);
+void TC1_IrqHandler(void);
+void TC2_IrqHandler(void);
+void PWM_IrqHandler(void);
+void ADC12B_IrqHandler(void);
+void ADC_IrqHandler(void);
+void DMAC_IrqHandler(void);
+void UDPHS_IrqHandler(void);
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#endif /* EXCEPTIONS_H_INCLUDED */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/source/templates/gcc/startup_sam3u.c b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/gcc/startup_sam3u.c
new file mode 100644
index 000000000..67b3a4c72
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/gcc/startup_sam3u.c
@@ -0,0 +1,131 @@
+/*! \file *********************************************************************
+ *
+ * \brief Startup file for SAM3U.
+ *
+ * $asf_license$
+ *
+ * This file defines common SAM series.
+ *
+ * - Compiler:           ARMGCC
+ * - Supported devices:  All SAM3U devices can be used.
+ * - AppNote:
+ *
+ ******************************************************************************/
+
+#include "../exceptions.h"
+#include "sam3.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+IntFunc exception_table[] = {
+
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(IntFunc) (&_estack),
+	Reset_Handler,
+	NMI_Handler,
+	HardFault_Handler,
+	MemManage_Handler,
+	BusFault_Handler,
+	UsageFault_Handler,
+	0, 0, 0, 0,	          /*  Reserved */
+	SVC_Handler,
+	DebugMon_Handler,
+	0,	                  /*  Reserved */
+	PendSV_Handler,
+	SysTick_Handler,
+
+	/* Configurable interrupts */
+	SUPC_IrqHandler,      /* 0  Supply Controller */
+	RSTC_IrqHandler,      /* 1  Reset Controller */
+	RTC_IrqHandler,       /* 2  Real Time Clock */
+	RTT_IrqHandler,       /* 3  Real Time Timer */
+	WDT_IrqHandler,       /* 4  Watchdog Timer */
+	PMC_IrqHandler,       /* 5  PMC */
+	EFC0_IrqHandler,      /* 6  EEFC 0 */
+	EFC1_IrqHandler,      /* 7  EEFC 1 */
+	UART_IrqHandler,      /* 8  UART0 */
+	SMC_IrqHandler,       /* 9  SMC */
+	PIOA_IrqHandler,      /* 10 Parallel IO Controller A */
+	PIOB_IrqHandler,      /* 11 Parallel IO Controller B */
+	PIOC_IrqHandler,      /* 12 Parallel IO Controller C */
+	USART0_IrqHandler,    /* 13 USART 0 */
+	USART1_IrqHandler,    /* 14 USART 1 */
+	USART2_IrqHandler,    /* 15 USART 2 */
+	USART3_IrqHandler,    /* 16 USART 3 */
+	MCI_IrqHandler,       /* 17 MCI */
+	TWI0_IrqHandler,      /* 18 TWI 0 */
+	TWI1_IrqHandler,      /* 19 TWI 1 */
+	SPI_IrqHandler,       /* 20 SPI */
+	SSC_IrqHandler,       /* 21 SSC */
+	TC0_IrqHandler,       /* 22 Timer Counter 0 */
+	TC1_IrqHandler,       /* 23 Timer Counter 1 */
+	TC2_IrqHandler,       /* 24 Timer Counter 2 */
+	PWM_IrqHandler,       /* 25 PWM */
+	ADC12B_IrqHandler,    /* 26 ADC12B controller */
+	ADC_IrqHandler,       /* 27 ADC controller */
+	DMAC_IrqHandler,      /* 28 DMA controller */
+	UDPHS_IrqHandler,     /* 29 USB High Speed Port */
+	Dummy_Handler         /* 30 not used */
+};
+
+/* TEMPORARY PATCH FOR SCB */
+#define SCB_VTOR_TBLBASE_Pos               29                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM0_ADDR) && ((uint32_t) pSrc < IRAM0_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/source/templates/iar/startup_sam3u.c b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/iar/startup_sam3u.c
new file mode 100644
index 000000000..702e6176a
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/iar/startup_sam3u.c
@@ -0,0 +1,108 @@
+/*! \file *********************************************************************
+ *
+ * \brief Startup file for SAM3U.
+ *
+ * $asf_license$
+ *
+ * This file defines common SAM series.
+ *
+ * - Compiler:           IAR EWARM
+ * - Supported devices:  All SAM3U devices can be used.
+ * - AppNote:
+ *
+ ******************************************************************************/
+
+#include "../exceptions.h"
+#include "sam3.h"
+
+typedef void( *intfunc )( void );
+typedef union { intfunc __fun; void * __ptr; } intvec_elem;
+
+void __iar_program_start(void);
+int __low_level_init(void);
+
+/* Exception Table */
+#pragma language=extended
+#pragma segment="CSTACK"
+
+/* The name "__vector_table" has special meaning for C-SPY: */
+/* it is where the SP start value is found, and the NVIC vector */
+/* table register (VTOR) is initialized to this address if != 0 */
+
+#pragma section = ".intvec"
+#pragma location = ".intvec"
+const intvec_elem __vector_table[] = {
+	{.__ptr = __sfe("CSTACK")},
+	Reset_Handler,
+
+	NMI_Handler,
+	HardFault_Handler,
+	MemManage_Handler,
+	BusFault_Handler,
+	UsageFault_Handler,
+	0, 0, 0, 0,	          /*  Reserved */
+	SVC_Handler,
+	DebugMon_Handler,
+	0,	                  /*  Reserved */
+	PendSV_Handler,
+	SysTick_Handler,
+
+	/* Configurable interrupts */
+	SUPC_IrqHandler,      /* 0  Supply Controller */
+	RSTC_IrqHandler,      /* 1  Reset Controller */
+	RTC_IrqHandler,       /* 2  Real Time Clock */
+	RTT_IrqHandler,       /* 3  Real Time Timer */
+	WDT_IrqHandler,       /* 4  Watchdog Timer */
+	PMC_IrqHandler,       /* 5  PMC */
+	EFC0_IrqHandler,      /* 6  EEFC 0 */
+	EFC1_IrqHandler,      /* 7  EEFC 1 */
+	UART_IrqHandler,      /* 8  UART0 */
+	SMC_IrqHandler,       /* 9  SMC */
+	PIOA_IrqHandler,      /* 10 Parallel IO Controller A */
+	PIOB_IrqHandler,      /* 11 Parallel IO Controller B */
+	PIOC_IrqHandler,      /* 12 Parallel IO Controller C */
+	USART0_IrqHandler,    /* 13 USART 0 */
+	USART1_IrqHandler,    /* 14 USART 1 */
+	USART2_IrqHandler,    /* 15 USART 2 */
+	USART3_IrqHandler,    /* 16 USART 3 */
+	MCI_IrqHandler,       /* 17 MCI */
+	TWI0_IrqHandler,      /* 18 TWI 0 */
+	TWI1_IrqHandler,      /* 19 TWI 1 */
+	SPI_IrqHandler,       /* 20 SPI */
+	SSC_IrqHandler,       /* 21 SSC */
+	TC0_IrqHandler,       /* 22 Timer Counter 0 */
+	TC1_IrqHandler,       /* 23 Timer Counter 1 */
+	TC2_IrqHandler,       /* 24 Timer Counter 2 */
+	PWM_IrqHandler,       /* 25 PWM */
+	ADC12B_IrqHandler,    /* 26 ADC12B controller */
+	ADC_IrqHandler,       /* 27 ADC controller */
+	DMAC_IrqHandler,      /* 28 DMA controller */
+	UDPHS_IrqHandler,     /* 29 USB High Speed Port */
+	Dummy_Handler         /* 30 not used */
+};
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+int __low_level_init(void)
+{
+	uint32_t *pSrc = __section_begin(".intvec");
+
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM0_ADDR) && ((uint32_t) pSrc < IRAM0_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	return 1; /* if return 0, the data sections will not be initialized */
+}
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+	__iar_program_start();
+}
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/source/templates/system_sam3u.c b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/system_sam3u.c
new file mode 100644
index 000000000..d4a492afa
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/system_sam3u.c
@@ -0,0 +1,204 @@
+/*! \file *********************************************************************
+ *
+ * \brief Provides the low-level initialization functions that called 
+ * on chip startup.
+ *
+ * $asf_license$
+ *
+ * \par Purpose
+ *
+ * This file provides basic support for Cortex-M processor based 
+ * microcontrollers.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+#include "system_sam3u.h"
+#include "sam3.h"
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+/* Clock settings (96MHz) */
+#define SYS_BOARD_OSCOUNT   (CKGR_MOR_MOSCXTST(0x8))
+#define SYS_BOARD_PLLAR     (CKGR_PLLAR_ONE \
+							| CKGR_PLLAR_MULA(0x7) \
+							| CKGR_PLLAR_PLLACOUNT(0x3f) \
+							| CKGR_PLLAR_DIVA(0x1))
+#define SYS_BOARD_MCKR      (PMC_MCKR_PRES_CLK_1 | PMC_MCKR_CSS_PLLA_CLK)
+
+/* Clock Definitions */
+#define SYS_FREQ_XTAL_32K      	(32768UL)		/* External 32K crystal frequency */
+#define SYS_FREQ_XTAL_XTAL12M	(12000000UL)	/* External 12M crystal frequency */
+#define SYS_UTMIPLL     		(480000000UL)	/* UTMI PLL frequency */
+
+#define SYS_FREQ_FWS_0	(24000000UL)	/* Maximum operating frequency when FWS is 0 */
+#define SYS_FREQ_FWS_1	(40000000UL)	/* Maximum operating frequency when FWS is 1 */
+#define SYS_FREQ_FWS_2	(72000000UL)	/* Maximum operating frequency when FWS is 2 */
+#define SYS_FREQ_FWS_3	(84000000UL)	/* Maximum operating frequency when FWS is 3 */
+
+#define SYS_CKGR_MOR_KEY_VALUE	CKGR_MOR_KEY(0x37) /* Key to unlock MOR register */
+
+/* FIXME: should be generated by sock */
+uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+/**
+ * \brief Setup the microcontroller system.
+ * Initialize the System and update the SystemFrequency variable.
+ */
+void SystemInit(void)
+{
+	/* Set 3 FWS for Embedded Flash Access */
+	EFC0->EEFC_FMR = EEFC_FMR_FWS(CHIP_FLASH_WAIT_STATE);
+	EFC1->EEFC_FMR = EEFC_FMR_FWS(CHIP_FLASH_WAIT_STATE);
+
+	/* Initialize main oscillator */
+	if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {
+		PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | 
+			                    CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
+		while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
+		}
+	}
+
+	/* Switch to 3-20MHz Xtal oscillator */
+	PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | 
+	                           CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
+
+	while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
+	}
+	PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | 
+		                      PMC_MCKR_CSS_MAIN_CLK;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	/* Initialize PLLA */
+	PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
+	while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
+	}
+
+	/* Switch to main clock */
+	PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	/* Switch to PLLA */
+	PMC->PMC_MCKR = SYS_BOARD_MCKR;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	SystemCoreClock = CHIP_FREQ_CPU_MAX;
+}
+
+void SystemCoreClockUpdate(void)
+{
+	/* Determine clock frequency according to clock register values */
+	switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {
+	case PMC_MCKR_CSS_SLOW_CLK:	/* Slow clock */
+		if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
+			SystemCoreClock = SYS_FREQ_XTAL_32K;
+		} else {
+			SystemCoreClock = CHIP_FREQ_SLCK_RC;
+		}
+		break;
+	case PMC_MCKR_CSS_MAIN_CLK:	/* Main clock */
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
+			SystemCoreClock = SYS_FREQ_XTAL_XTAL12M;
+		} else {
+			SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+			switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
+			case CKGR_MOR_MOSCRCF_4_MHz:
+				break;
+			case CKGR_MOR_MOSCRCF_8_MHz:
+				SystemCoreClock *= 2U;
+				break;
+			case CKGR_MOR_MOSCRCF_12_MHz:
+				SystemCoreClock *= 3U;
+				break;
+			default:
+				break;
+			}
+		}
+		break;
+	case PMC_MCKR_CSS_PLLA_CLK:	/* PLLA clock */
+	case PMC_MCKR_CSS_UPLL_CLK:	/* UPLL clock */
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
+			SystemCoreClock = SYS_FREQ_XTAL_XTAL12M;
+		} else {
+			SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+			switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
+			case CKGR_MOR_MOSCRCF_4_MHz:
+				break;
+			case CKGR_MOR_MOSCRCF_8_MHz:
+				SystemCoreClock *= 2U;
+				break;
+			case CKGR_MOR_MOSCRCF_12_MHz:
+				SystemCoreClock *= 3U;
+				break;
+			default:
+				break;
+			}
+		}
+		if ((PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {
+			SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> 
+				                          CKGR_PLLAR_MULA_Pos) + 1U);
+			SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >>
+				                           CKGR_PLLAR_DIVA_Pos));
+		} else {
+			SystemCoreClock = SYS_UTMIPLL / 2U;
+		}
+		break;
+	}
+
+	if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
+		SystemCoreClock /= 3U;
+	} else {
+		SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> 
+			                           PMC_MCKR_PRES_Pos);
+	}
+}
+
+/** 
+ * Initialize flash and watchdog.
+ */
+void system_init_flash_and_watchdog(uint32_t dw_clk)
+{
+	/* Set FWS for embedded Flash access according to operating frequency */
+	if (dw_clk < SYS_FREQ_FWS_0) {
+		EFC0->EEFC_FMR = EEFC_FMR_FWS(0);
+		EFC1->EEFC_FMR = EEFC_FMR_FWS(0);
+	} else if (dw_clk < SYS_FREQ_FWS_1) {
+		EFC0->EEFC_FMR = EEFC_FMR_FWS(1);
+		EFC1->EEFC_FMR = EEFC_FMR_FWS(1);
+	} else if (dw_clk < SYS_FREQ_FWS_2) {
+		EFC0->EEFC_FMR = EEFC_FMR_FWS(2);
+		EFC1->EEFC_FMR = EEFC_FMR_FWS(2);
+	} else if (dw_clk < SYS_FREQ_FWS_3) {
+		EFC0->EEFC_FMR = EEFC_FMR_FWS(3);
+		EFC1->EEFC_FMR = EEFC_FMR_FWS(3);
+	} else {
+		EFC0->EEFC_FMR = EEFC_FMR_FWS(4);
+		EFC1->EEFC_FMR = EEFC_FMR_FWS(4);
+	}
+	
+#ifndef CONFIG_KEEP_WATCHDOG_AFTER_INIT 
+	/* Disable the watchdog */
+	WDT->WDT_MR = WDT_MR_WDDIS;
+#endif
+}
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/source/templates/system_sam3u.h b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/system_sam3u.h
new file mode 100644
index 000000000..82c0118cd
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/system_sam3u.h
@@ -0,0 +1,58 @@
+/*! \file *********************************************************************
+ *
+ * \brief CMSIS Cortex-M# Device Peripheral Access Layer Header File
+ *           for SAM3 devices.
+ *
+ * $asf_license$
+ *
+ * \par Purpose
+ *
+ * This file provides basic support for Cortex-M processor based 
+ * microcontrollers.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+#ifndef SYSTEM_SAM3U_H_INCLUDED
+#define SYSTEM_SAM3U_H_INCLUDED
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#include 
+
+extern uint32_t SystemCoreClock;	/* System Clock Frequency (Core Clock) */
+
+/**
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+void SystemInit(void);
+
+/**
+ * @brief Updates the SystemCoreClock with current core Clock 
+ * retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void);
+
+/** 
+ * Initialize flash and watchdog.
+ */
+void system_init_flash_and_watchdog(uint32_t dw_clk);
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#endif /* SYSTEM_SAM3U_H_INCLUDED */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_adc.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_adc.h
new file mode 100644
index 000000000..70d30de35
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_adc.h
@@ -0,0 +1,522 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_ADC_COMPONENT_
+#define _SAM3XA_ADC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Analog-to-digital Converter */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_ADC Analog-to-digital Converter */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Adc hardware registers */
+typedef struct {
+  WoReg ADC_CR;        /**< \brief (Adc Offset: 0x00) Control Register */
+  RwReg ADC_MR;        /**< \brief (Adc Offset: 0x04) Mode Register */
+  RwReg ADC_SEQR1;     /**< \brief (Adc Offset: 0x08) Channel Sequence Register 1 */
+  RwReg ADC_SEQR2;     /**< \brief (Adc Offset: 0x0C) Channel Sequence Register 2 */
+  WoReg ADC_CHER;      /**< \brief (Adc Offset: 0x10) Channel Enable Register */
+  WoReg ADC_CHDR;      /**< \brief (Adc Offset: 0x14) Channel Disable Register */
+  RoReg ADC_CHSR;      /**< \brief (Adc Offset: 0x18) Channel Status Register */
+  RoReg Reserved1[1];
+  RoReg ADC_LCDR;      /**< \brief (Adc Offset: 0x20) Last Converted Data Register */
+  WoReg ADC_IER;       /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */
+  WoReg ADC_IDR;       /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */
+  RoReg ADC_IMR;       /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */
+  RoReg ADC_ISR;       /**< \brief (Adc Offset: 0x30) Interrupt Status Register */
+  RoReg Reserved2[2];
+  RoReg ADC_OVER;      /**< \brief (Adc Offset: 0x3C) Overrun Status Register */
+  RwReg ADC_EMR;       /**< \brief (Adc Offset: 0x40) Extended Mode Register */
+  RwReg ADC_CWR;       /**< \brief (Adc Offset: 0x44) Compare Window Register */
+  RwReg ADC_CGR;       /**< \brief (Adc Offset: 0x48) Channel Gain Register */
+  RwReg ADC_COR;       /**< \brief (Adc Offset: 0x4C) Channel Offset Register */
+  RoReg ADC_CDR[16];   /**< \brief (Adc Offset: 0x50) Channel Data Register */
+  RoReg Reserved3[1];
+  RwReg ADC_ACR;       /**< \brief (Adc Offset: 0x94) Analog Control Register */
+  RoReg Reserved4[19];
+  RwReg ADC_WPMR;      /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */
+  RoReg ADC_WPSR;      /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved5[5];
+  RwReg ADC_RPR;       /**< \brief (Adc Offset: 0x100) Receive Pointer Register */
+  RwReg ADC_RCR;       /**< \brief (Adc Offset: 0x104) Receive Counter Register */
+  RwReg ADC_TPR;       /**< \brief (Adc Offset: 0x108) Transmit Pointer Register */
+  RwReg ADC_TCR;       /**< \brief (Adc Offset: 0x10C) Transmit Counter Register */
+  RwReg ADC_RNPR;      /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */
+  RwReg ADC_RNCR;      /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */
+  RwReg ADC_TNPR;      /**< \brief (Adc Offset: 0x118) Transmit Next Pointer Register */
+  RwReg ADC_TNCR;      /**< \brief (Adc Offset: 0x11C) Transmit Next Counter Register */
+  WoReg ADC_PTCR;      /**< \brief (Adc Offset: 0x120) Transfer Control Register */
+  RoReg ADC_PTSR;      /**< \brief (Adc Offset: 0x124) Transfer Status Register */
+} Adc;
+#endif /* __ASSEMBLY__ */
+/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */
+#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */
+#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */
+/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */
+#define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */
+#define   ADC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */
+#define   ADC_MR_TRGEN_EN (0x1u << 0) /**< \brief (ADC_MR) Hardware trigger selected by TRGSEL field is enabled. */
+#define ADC_MR_TRGSEL_Pos 1
+#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */
+#define   ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC_MR) External : ADCTRG */
+#define   ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC_MR) TIOA Output of the Timer Counter Channel 0 */
+#define   ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC_MR) TIOA Output of the Timer Counter Channel 1 */
+#define   ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC_MR) TIOA Output of the Timer Counter Channel 2 */
+#define   ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) /**< \brief (ADC_MR) PWM Event Line 0 */
+#define   ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) /**< \brief (ADC_MR) PWM Event Line 0 */
+#define ADC_MR_LOWRES (0x1u << 4) /**< \brief (ADC_MR) Resolution */
+#define   ADC_MR_LOWRES_BITS_12 (0x0u << 4) /**< \brief (ADC_MR) 12-bit resolution */
+#define   ADC_MR_LOWRES_BITS_10 (0x1u << 4) /**< \brief (ADC_MR) 10-bit resolution */
+#define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */
+#define   ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions */
+#define   ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions */
+#define ADC_MR_FWUP (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up */
+#define   ADC_MR_FWUP_OFF (0x0u << 6) /**< \brief (ADC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit */
+#define   ADC_MR_FWUP_ON (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF */
+#define ADC_MR_FREERUN (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode */
+#define   ADC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (ADC_MR) Normal Mode */
+#define   ADC_MR_FREERUN_ON (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode: Never wait for any trigger. */
+#define ADC_MR_PRESCAL_Pos 8
+#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */
+#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos)))
+#define ADC_MR_STARTUP_Pos 16
+#define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */
+#define   ADC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (ADC_MR) 0 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (ADC_MR) 8 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (ADC_MR) 16 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (ADC_MR) 24 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (ADC_MR) 64 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (ADC_MR) 80 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (ADC_MR) 96 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (ADC_MR) 112 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (ADC_MR) 512 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (ADC_MR) 576 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (ADC_MR) 640 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (ADC_MR) 704 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (ADC_MR) 768 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (ADC_MR) 832 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (ADC_MR) 896 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (ADC_MR) 960 periods of ADCClock */
+#define ADC_MR_SETTLING_Pos 20
+#define ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos) /**< \brief (ADC_MR) Analog Settling Time */
+#define   ADC_MR_SETTLING_AST3 (0x0u << 20) /**< \brief (ADC_MR) 3 periods of ADCClock */
+#define   ADC_MR_SETTLING_AST5 (0x1u << 20) /**< \brief (ADC_MR) 5 periods of ADCClock */
+#define   ADC_MR_SETTLING_AST9 (0x2u << 20) /**< \brief (ADC_MR) 9 periods of ADCClock */
+#define   ADC_MR_SETTLING_AST17 (0x3u << 20) /**< \brief (ADC_MR) 17 periods of ADCClock */
+#define ADC_MR_ANACH (0x1u << 23) /**< \brief (ADC_MR) Analog Change */
+#define   ADC_MR_ANACH_NONE (0x0u << 23) /**< \brief (ADC_MR) No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels */
+#define   ADC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (ADC_MR) Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers */
+#define ADC_MR_TRACKTIM_Pos 24
+#define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) /**< \brief (ADC_MR) Tracking Time */
+#define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos)))
+#define ADC_MR_TRANSFER_Pos 28
+#define ADC_MR_TRANSFER_Msk (0x3u << ADC_MR_TRANSFER_Pos) /**< \brief (ADC_MR) Transfer Period */
+#define ADC_MR_TRANSFER(value) ((ADC_MR_TRANSFER_Msk & ((value) << ADC_MR_TRANSFER_Pos)))
+#define ADC_MR_USEQ (0x1u << 31) /**< \brief (ADC_MR) Use Sequence Enable */
+#define   ADC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (ADC_MR) Normal Mode: The controller converts channels in a simple numeric order. */
+#define   ADC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers. */
+/* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */
+#define ADC_SEQR1_USCH1_Pos 0
+#define ADC_SEQR1_USCH1_Msk (0xfu << ADC_SEQR1_USCH1_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 1 */
+#define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos)))
+#define ADC_SEQR1_USCH2_Pos 4
+#define ADC_SEQR1_USCH2_Msk (0xfu << ADC_SEQR1_USCH2_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 2 */
+#define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos)))
+#define ADC_SEQR1_USCH3_Pos 8
+#define ADC_SEQR1_USCH3_Msk (0xfu << ADC_SEQR1_USCH3_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 3 */
+#define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos)))
+#define ADC_SEQR1_USCH4_Pos 12
+#define ADC_SEQR1_USCH4_Msk (0xfu << ADC_SEQR1_USCH4_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 4 */
+#define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos)))
+#define ADC_SEQR1_USCH5_Pos 16
+#define ADC_SEQR1_USCH5_Msk (0xfu << ADC_SEQR1_USCH5_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 5 */
+#define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos)))
+#define ADC_SEQR1_USCH6_Pos 20
+#define ADC_SEQR1_USCH6_Msk (0xfu << ADC_SEQR1_USCH6_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 6 */
+#define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos)))
+#define ADC_SEQR1_USCH7_Pos 24
+#define ADC_SEQR1_USCH7_Msk (0xfu << ADC_SEQR1_USCH7_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 7 */
+#define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos)))
+#define ADC_SEQR1_USCH8_Pos 28
+#define ADC_SEQR1_USCH8_Msk (0xfu << ADC_SEQR1_USCH8_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 8 */
+#define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos)))
+/* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */
+#define ADC_SEQR2_USCH9_Pos 0
+#define ADC_SEQR2_USCH9_Msk (0xfu << ADC_SEQR2_USCH9_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 9 */
+#define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos)))
+#define ADC_SEQR2_USCH10_Pos 4
+#define ADC_SEQR2_USCH10_Msk (0xfu << ADC_SEQR2_USCH10_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 10 */
+#define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos)))
+#define ADC_SEQR2_USCH11_Pos 8
+#define ADC_SEQR2_USCH11_Msk (0xfu << ADC_SEQR2_USCH11_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 11 */
+#define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos)))
+#define ADC_SEQR2_USCH12_Pos 12
+#define ADC_SEQR2_USCH12_Msk (0xfu << ADC_SEQR2_USCH12_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 12 */
+#define ADC_SEQR2_USCH12(value) ((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos)))
+#define ADC_SEQR2_USCH13_Pos 16
+#define ADC_SEQR2_USCH13_Msk (0xfu << ADC_SEQR2_USCH13_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 13 */
+#define ADC_SEQR2_USCH13(value) ((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos)))
+#define ADC_SEQR2_USCH14_Pos 20
+#define ADC_SEQR2_USCH14_Msk (0xfu << ADC_SEQR2_USCH14_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 14 */
+#define ADC_SEQR2_USCH14(value) ((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos)))
+#define ADC_SEQR2_USCH15_Pos 24
+#define ADC_SEQR2_USCH15_Msk (0xfu << ADC_SEQR2_USCH15_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 15 */
+#define ADC_SEQR2_USCH15(value) ((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos)))
+#define ADC_SEQR2_USCH16_Pos 28
+#define ADC_SEQR2_USCH16_Msk (0xfu << ADC_SEQR2_USCH16_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 16 */
+#define ADC_SEQR2_USCH16(value) ((ADC_SEQR2_USCH16_Msk & ((value) << ADC_SEQR2_USCH16_Pos)))
+/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */
+#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */
+#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */
+#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */
+#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */
+#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */
+#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */
+#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */
+#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */
+#define ADC_CHER_CH8 (0x1u << 8) /**< \brief (ADC_CHER) Channel 8 Enable */
+#define ADC_CHER_CH9 (0x1u << 9) /**< \brief (ADC_CHER) Channel 9 Enable */
+#define ADC_CHER_CH10 (0x1u << 10) /**< \brief (ADC_CHER) Channel 10 Enable */
+#define ADC_CHER_CH11 (0x1u << 11) /**< \brief (ADC_CHER) Channel 11 Enable */
+#define ADC_CHER_CH12 (0x1u << 12) /**< \brief (ADC_CHER) Channel 12 Enable */
+#define ADC_CHER_CH13 (0x1u << 13) /**< \brief (ADC_CHER) Channel 13 Enable */
+#define ADC_CHER_CH14 (0x1u << 14) /**< \brief (ADC_CHER) Channel 14 Enable */
+#define ADC_CHER_CH15 (0x1u << 15) /**< \brief (ADC_CHER) Channel 15 Enable */
+/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */
+#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */
+#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */
+#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */
+#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */
+#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */
+#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */
+#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */
+#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */
+#define ADC_CHDR_CH8 (0x1u << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */
+#define ADC_CHDR_CH9 (0x1u << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */
+#define ADC_CHDR_CH10 (0x1u << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */
+#define ADC_CHDR_CH11 (0x1u << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */
+#define ADC_CHDR_CH12 (0x1u << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */
+#define ADC_CHDR_CH13 (0x1u << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */
+#define ADC_CHDR_CH14 (0x1u << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */
+#define ADC_CHDR_CH15 (0x1u << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */
+/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */
+#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */
+#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */
+#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */
+#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */
+#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */
+#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */
+#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */
+#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */
+#define ADC_CHSR_CH8 (0x1u << 8) /**< \brief (ADC_CHSR) Channel 8 Status */
+#define ADC_CHSR_CH9 (0x1u << 9) /**< \brief (ADC_CHSR) Channel 9 Status */
+#define ADC_CHSR_CH10 (0x1u << 10) /**< \brief (ADC_CHSR) Channel 10 Status */
+#define ADC_CHSR_CH11 (0x1u << 11) /**< \brief (ADC_CHSR) Channel 11 Status */
+#define ADC_CHSR_CH12 (0x1u << 12) /**< \brief (ADC_CHSR) Channel 12 Status */
+#define ADC_CHSR_CH13 (0x1u << 13) /**< \brief (ADC_CHSR) Channel 13 Status */
+#define ADC_CHSR_CH14 (0x1u << 14) /**< \brief (ADC_CHSR) Channel 14 Status */
+#define ADC_CHSR_CH15 (0x1u << 15) /**< \brief (ADC_CHSR) Channel 15 Status */
+/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */
+#define ADC_LCDR_LDATA_Pos 0
+#define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */
+#define ADC_LCDR_CHNB_Pos 12
+#define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) /**< \brief (ADC_LCDR) Channel Number */
+/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */
+#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */
+#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */
+#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */
+#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */
+#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */
+#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */
+#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */
+#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */
+#define ADC_IER_EOC8 (0x1u << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */
+#define ADC_IER_EOC9 (0x1u << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */
+#define ADC_IER_EOC10 (0x1u << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */
+#define ADC_IER_EOC11 (0x1u << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */
+#define ADC_IER_EOC12 (0x1u << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */
+#define ADC_IER_EOC13 (0x1u << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */
+#define ADC_IER_EOC14 (0x1u << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */
+#define ADC_IER_EOC15 (0x1u << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */
+#define ADC_IER_DRDY (0x1u << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */
+#define ADC_IER_GOVRE (0x1u << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */
+#define ADC_IER_COMPE (0x1u << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */
+#define ADC_IER_ENDRX (0x1u << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */
+#define ADC_IER_RXBUFF (0x1u << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */
+/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */
+#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */
+#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */
+#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */
+#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */
+#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */
+#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */
+#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */
+#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */
+#define ADC_IDR_EOC8 (0x1u << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */
+#define ADC_IDR_EOC9 (0x1u << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */
+#define ADC_IDR_EOC10 (0x1u << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */
+#define ADC_IDR_EOC11 (0x1u << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */
+#define ADC_IDR_EOC12 (0x1u << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */
+#define ADC_IDR_EOC13 (0x1u << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */
+#define ADC_IDR_EOC14 (0x1u << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */
+#define ADC_IDR_EOC15 (0x1u << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */
+#define ADC_IDR_DRDY (0x1u << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */
+#define ADC_IDR_GOVRE (0x1u << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */
+#define ADC_IDR_COMPE (0x1u << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */
+#define ADC_IDR_ENDRX (0x1u << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */
+#define ADC_IDR_RXBUFF (0x1u << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */
+/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */
+#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */
+#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */
+#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */
+#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */
+#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */
+#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */
+#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */
+#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */
+#define ADC_IMR_EOC8 (0x1u << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */
+#define ADC_IMR_EOC9 (0x1u << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */
+#define ADC_IMR_EOC10 (0x1u << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */
+#define ADC_IMR_EOC11 (0x1u << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */
+#define ADC_IMR_EOC12 (0x1u << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */
+#define ADC_IMR_EOC13 (0x1u << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */
+#define ADC_IMR_EOC14 (0x1u << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */
+#define ADC_IMR_EOC15 (0x1u << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */
+#define ADC_IMR_DRDY (0x1u << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */
+#define ADC_IMR_GOVRE (0x1u << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */
+#define ADC_IMR_COMPE (0x1u << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */
+#define ADC_IMR_ENDRX (0x1u << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */
+#define ADC_IMR_RXBUFF (0x1u << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */
+/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */
+#define ADC_ISR_EOC0 (0x1u << 0) /**< \brief (ADC_ISR) End of Conversion 0 */
+#define ADC_ISR_EOC1 (0x1u << 1) /**< \brief (ADC_ISR) End of Conversion 1 */
+#define ADC_ISR_EOC2 (0x1u << 2) /**< \brief (ADC_ISR) End of Conversion 2 */
+#define ADC_ISR_EOC3 (0x1u << 3) /**< \brief (ADC_ISR) End of Conversion 3 */
+#define ADC_ISR_EOC4 (0x1u << 4) /**< \brief (ADC_ISR) End of Conversion 4 */
+#define ADC_ISR_EOC5 (0x1u << 5) /**< \brief (ADC_ISR) End of Conversion 5 */
+#define ADC_ISR_EOC6 (0x1u << 6) /**< \brief (ADC_ISR) End of Conversion 6 */
+#define ADC_ISR_EOC7 (0x1u << 7) /**< \brief (ADC_ISR) End of Conversion 7 */
+#define ADC_ISR_EOC8 (0x1u << 8) /**< \brief (ADC_ISR) End of Conversion 8 */
+#define ADC_ISR_EOC9 (0x1u << 9) /**< \brief (ADC_ISR) End of Conversion 9 */
+#define ADC_ISR_EOC10 (0x1u << 10) /**< \brief (ADC_ISR) End of Conversion 10 */
+#define ADC_ISR_EOC11 (0x1u << 11) /**< \brief (ADC_ISR) End of Conversion 11 */
+#define ADC_ISR_EOC12 (0x1u << 12) /**< \brief (ADC_ISR) End of Conversion 12 */
+#define ADC_ISR_EOC13 (0x1u << 13) /**< \brief (ADC_ISR) End of Conversion 13 */
+#define ADC_ISR_EOC14 (0x1u << 14) /**< \brief (ADC_ISR) End of Conversion 14 */
+#define ADC_ISR_EOC15 (0x1u << 15) /**< \brief (ADC_ISR) End of Conversion 15 */
+#define ADC_ISR_DRDY (0x1u << 24) /**< \brief (ADC_ISR) Data Ready */
+#define ADC_ISR_GOVRE (0x1u << 25) /**< \brief (ADC_ISR) General Overrun Error */
+#define ADC_ISR_COMPE (0x1u << 26) /**< \brief (ADC_ISR) Comparison Error */
+#define ADC_ISR_ENDRX (0x1u << 27) /**< \brief (ADC_ISR) End of RX Buffer */
+#define ADC_ISR_RXBUFF (0x1u << 28) /**< \brief (ADC_ISR) RX Buffer Full */
+/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */
+#define ADC_OVER_OVRE0 (0x1u << 0) /**< \brief (ADC_OVER) Overrun Error 0 */
+#define ADC_OVER_OVRE1 (0x1u << 1) /**< \brief (ADC_OVER) Overrun Error 1 */
+#define ADC_OVER_OVRE2 (0x1u << 2) /**< \brief (ADC_OVER) Overrun Error 2 */
+#define ADC_OVER_OVRE3 (0x1u << 3) /**< \brief (ADC_OVER) Overrun Error 3 */
+#define ADC_OVER_OVRE4 (0x1u << 4) /**< \brief (ADC_OVER) Overrun Error 4 */
+#define ADC_OVER_OVRE5 (0x1u << 5) /**< \brief (ADC_OVER) Overrun Error 5 */
+#define ADC_OVER_OVRE6 (0x1u << 6) /**< \brief (ADC_OVER) Overrun Error 6 */
+#define ADC_OVER_OVRE7 (0x1u << 7) /**< \brief (ADC_OVER) Overrun Error 7 */
+#define ADC_OVER_OVRE8 (0x1u << 8) /**< \brief (ADC_OVER) Overrun Error 8 */
+#define ADC_OVER_OVRE9 (0x1u << 9) /**< \brief (ADC_OVER) Overrun Error 9 */
+#define ADC_OVER_OVRE10 (0x1u << 10) /**< \brief (ADC_OVER) Overrun Error 10 */
+#define ADC_OVER_OVRE11 (0x1u << 11) /**< \brief (ADC_OVER) Overrun Error 11 */
+#define ADC_OVER_OVRE12 (0x1u << 12) /**< \brief (ADC_OVER) Overrun Error 12 */
+#define ADC_OVER_OVRE13 (0x1u << 13) /**< \brief (ADC_OVER) Overrun Error 13 */
+#define ADC_OVER_OVRE14 (0x1u << 14) /**< \brief (ADC_OVER) Overrun Error 14 */
+#define ADC_OVER_OVRE15 (0x1u << 15) /**< \brief (ADC_OVER) Overrun Error 15 */
+/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */
+#define ADC_EMR_CMPMODE_Pos 0
+#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /**< \brief (ADC_EMR) Comparison Mode */
+#define   ADC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */
+#define   ADC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */
+#define   ADC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is in the comparison window. */
+#define   ADC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is out of the comparison window. */
+#define ADC_EMR_CMPSEL_Pos 4
+#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /**< \brief (ADC_EMR) Comparison Selected Channel */
+#define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos)))
+#define ADC_EMR_CMPALL (0x1u << 9) /**< \brief (ADC_EMR) Compare All Channels */
+#define ADC_EMR_CMPFILTER_Pos 12
+#define ADC_EMR_CMPFILTER_Msk (0x3u << ADC_EMR_CMPFILTER_Pos) /**< \brief (ADC_EMR) Compare Event Filtering */
+#define ADC_EMR_CMPFILTER(value) ((ADC_EMR_CMPFILTER_Msk & ((value) << ADC_EMR_CMPFILTER_Pos)))
+#define ADC_EMR_TAG (0x1u << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */
+/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */
+#define ADC_CWR_LOWTHRES_Pos 0
+#define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) /**< \brief (ADC_CWR) Low Threshold */
+#define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos)))
+#define ADC_CWR_HIGHTHRES_Pos 16
+#define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) /**< \brief (ADC_CWR) High Threshold */
+#define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos)))
+/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */
+#define ADC_CGR_GAIN0_Pos 0
+#define ADC_CGR_GAIN0_Msk (0x3u << ADC_CGR_GAIN0_Pos) /**< \brief (ADC_CGR) Gain for channel 0 */
+#define ADC_CGR_GAIN0(value) ((ADC_CGR_GAIN0_Msk & ((value) << ADC_CGR_GAIN0_Pos)))
+#define ADC_CGR_GAIN1_Pos 2
+#define ADC_CGR_GAIN1_Msk (0x3u << ADC_CGR_GAIN1_Pos) /**< \brief (ADC_CGR) Gain for channel 1 */
+#define ADC_CGR_GAIN1(value) ((ADC_CGR_GAIN1_Msk & ((value) << ADC_CGR_GAIN1_Pos)))
+#define ADC_CGR_GAIN2_Pos 4
+#define ADC_CGR_GAIN2_Msk (0x3u << ADC_CGR_GAIN2_Pos) /**< \brief (ADC_CGR) Gain for channel 2 */
+#define ADC_CGR_GAIN2(value) ((ADC_CGR_GAIN2_Msk & ((value) << ADC_CGR_GAIN2_Pos)))
+#define ADC_CGR_GAIN3_Pos 6
+#define ADC_CGR_GAIN3_Msk (0x3u << ADC_CGR_GAIN3_Pos) /**< \brief (ADC_CGR) Gain for channel 3 */
+#define ADC_CGR_GAIN3(value) ((ADC_CGR_GAIN3_Msk & ((value) << ADC_CGR_GAIN3_Pos)))
+#define ADC_CGR_GAIN4_Pos 8
+#define ADC_CGR_GAIN4_Msk (0x3u << ADC_CGR_GAIN4_Pos) /**< \brief (ADC_CGR) Gain for channel 4 */
+#define ADC_CGR_GAIN4(value) ((ADC_CGR_GAIN4_Msk & ((value) << ADC_CGR_GAIN4_Pos)))
+#define ADC_CGR_GAIN5_Pos 10
+#define ADC_CGR_GAIN5_Msk (0x3u << ADC_CGR_GAIN5_Pos) /**< \brief (ADC_CGR) Gain for channel 5 */
+#define ADC_CGR_GAIN5(value) ((ADC_CGR_GAIN5_Msk & ((value) << ADC_CGR_GAIN5_Pos)))
+#define ADC_CGR_GAIN6_Pos 12
+#define ADC_CGR_GAIN6_Msk (0x3u << ADC_CGR_GAIN6_Pos) /**< \brief (ADC_CGR) Gain for channel 6 */
+#define ADC_CGR_GAIN6(value) ((ADC_CGR_GAIN6_Msk & ((value) << ADC_CGR_GAIN6_Pos)))
+#define ADC_CGR_GAIN7_Pos 14
+#define ADC_CGR_GAIN7_Msk (0x3u << ADC_CGR_GAIN7_Pos) /**< \brief (ADC_CGR) Gain for channel 7 */
+#define ADC_CGR_GAIN7(value) ((ADC_CGR_GAIN7_Msk & ((value) << ADC_CGR_GAIN7_Pos)))
+#define ADC_CGR_GAIN8_Pos 16
+#define ADC_CGR_GAIN8_Msk (0x3u << ADC_CGR_GAIN8_Pos) /**< \brief (ADC_CGR) Gain for channel 8 */
+#define ADC_CGR_GAIN8(value) ((ADC_CGR_GAIN8_Msk & ((value) << ADC_CGR_GAIN8_Pos)))
+#define ADC_CGR_GAIN9_Pos 18
+#define ADC_CGR_GAIN9_Msk (0x3u << ADC_CGR_GAIN9_Pos) /**< \brief (ADC_CGR) Gain for channel 9 */
+#define ADC_CGR_GAIN9(value) ((ADC_CGR_GAIN9_Msk & ((value) << ADC_CGR_GAIN9_Pos)))
+#define ADC_CGR_GAIN10_Pos 20
+#define ADC_CGR_GAIN10_Msk (0x3u << ADC_CGR_GAIN10_Pos) /**< \brief (ADC_CGR) Gain for channel 10 */
+#define ADC_CGR_GAIN10(value) ((ADC_CGR_GAIN10_Msk & ((value) << ADC_CGR_GAIN10_Pos)))
+#define ADC_CGR_GAIN11_Pos 22
+#define ADC_CGR_GAIN11_Msk (0x3u << ADC_CGR_GAIN11_Pos) /**< \brief (ADC_CGR) Gain for channel 11 */
+#define ADC_CGR_GAIN11(value) ((ADC_CGR_GAIN11_Msk & ((value) << ADC_CGR_GAIN11_Pos)))
+#define ADC_CGR_GAIN12_Pos 24
+#define ADC_CGR_GAIN12_Msk (0x3u << ADC_CGR_GAIN12_Pos) /**< \brief (ADC_CGR) Gain for channel 12 */
+#define ADC_CGR_GAIN12(value) ((ADC_CGR_GAIN12_Msk & ((value) << ADC_CGR_GAIN12_Pos)))
+#define ADC_CGR_GAIN13_Pos 26
+#define ADC_CGR_GAIN13_Msk (0x3u << ADC_CGR_GAIN13_Pos) /**< \brief (ADC_CGR) Gain for channel 13 */
+#define ADC_CGR_GAIN13(value) ((ADC_CGR_GAIN13_Msk & ((value) << ADC_CGR_GAIN13_Pos)))
+#define ADC_CGR_GAIN14_Pos 28
+#define ADC_CGR_GAIN14_Msk (0x3u << ADC_CGR_GAIN14_Pos) /**< \brief (ADC_CGR) Gain for channel 14 */
+#define ADC_CGR_GAIN14(value) ((ADC_CGR_GAIN14_Msk & ((value) << ADC_CGR_GAIN14_Pos)))
+#define ADC_CGR_GAIN15_Pos 30
+#define ADC_CGR_GAIN15_Msk (0x3u << ADC_CGR_GAIN15_Pos) /**< \brief (ADC_CGR) Gain for channel 15 */
+#define ADC_CGR_GAIN15(value) ((ADC_CGR_GAIN15_Msk & ((value) << ADC_CGR_GAIN15_Pos)))
+/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */
+#define ADC_COR_OFF0 (0x1u << 0) /**< \brief (ADC_COR) Offset for channel 0 */
+#define ADC_COR_OFF1 (0x1u << 1) /**< \brief (ADC_COR) Offset for channel 1 */
+#define ADC_COR_OFF2 (0x1u << 2) /**< \brief (ADC_COR) Offset for channel 2 */
+#define ADC_COR_OFF3 (0x1u << 3) /**< \brief (ADC_COR) Offset for channel 3 */
+#define ADC_COR_OFF4 (0x1u << 4) /**< \brief (ADC_COR) Offset for channel 4 */
+#define ADC_COR_OFF5 (0x1u << 5) /**< \brief (ADC_COR) Offset for channel 5 */
+#define ADC_COR_OFF6 (0x1u << 6) /**< \brief (ADC_COR) Offset for channel 6 */
+#define ADC_COR_OFF7 (0x1u << 7) /**< \brief (ADC_COR) Offset for channel 7 */
+#define ADC_COR_OFF8 (0x1u << 8) /**< \brief (ADC_COR) Offset for channel 8 */
+#define ADC_COR_OFF9 (0x1u << 9) /**< \brief (ADC_COR) Offset for channel 9 */
+#define ADC_COR_OFF10 (0x1u << 10) /**< \brief (ADC_COR) Offset for channel 10 */
+#define ADC_COR_OFF11 (0x1u << 11) /**< \brief (ADC_COR) Offset for channel 11 */
+#define ADC_COR_OFF12 (0x1u << 12) /**< \brief (ADC_COR) Offset for channel 12 */
+#define ADC_COR_OFF13 (0x1u << 13) /**< \brief (ADC_COR) Offset for channel 13 */
+#define ADC_COR_OFF14 (0x1u << 14) /**< \brief (ADC_COR) Offset for channel 14 */
+#define ADC_COR_OFF15 (0x1u << 15) /**< \brief (ADC_COR) Offset for channel 15 */
+#define ADC_COR_DIFF0 (0x1u << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */
+#define ADC_COR_DIFF1 (0x1u << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */
+#define ADC_COR_DIFF2 (0x1u << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */
+#define ADC_COR_DIFF3 (0x1u << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */
+#define ADC_COR_DIFF4 (0x1u << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */
+#define ADC_COR_DIFF5 (0x1u << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */
+#define ADC_COR_DIFF6 (0x1u << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */
+#define ADC_COR_DIFF7 (0x1u << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */
+#define ADC_COR_DIFF8 (0x1u << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */
+#define ADC_COR_DIFF9 (0x1u << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */
+#define ADC_COR_DIFF10 (0x1u << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */
+#define ADC_COR_DIFF11 (0x1u << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */
+#define ADC_COR_DIFF12 (0x1u << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */
+#define ADC_COR_DIFF13 (0x1u << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */
+#define ADC_COR_DIFF14 (0x1u << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */
+#define ADC_COR_DIFF15 (0x1u << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */
+/* -------- ADC_CDR[16] : (ADC Offset: 0x50) Channel Data Register -------- */
+#define ADC_CDR_DATA_Pos 0
+#define ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[16]) Converted Data */
+/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */
+#define ADC_ACR_TSON (0x1u << 4) /**< \brief (ADC_ACR) Temperature Sensor On */
+#define ADC_ACR_IBCTL_Pos 8
+#define ADC_ACR_IBCTL_Msk (0x3u << ADC_ACR_IBCTL_Pos) /**< \brief (ADC_ACR) ADC Bias Current Control */
+#define ADC_ACR_IBCTL(value) ((ADC_ACR_IBCTL_Msk & ((value) << ADC_ACR_IBCTL_Pos)))
+/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */
+#define ADC_WPMR_WPEN (0x1u << 0) /**< \brief (ADC_WPMR) Write Protect Enable */
+#define ADC_WPMR_WPKEY_Pos 8
+#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /**< \brief (ADC_WPMR) Write Protect KEY */
+#define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos)))
+/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */
+#define ADC_WPSR_WPVS (0x1u << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */
+#define ADC_WPSR_WPVSRC_Pos 8
+#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /**< \brief (ADC_WPSR) Write Protect Violation Source */
+/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */
+#define ADC_RPR_RXPTR_Pos 0
+#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */
+#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos)))
+/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */
+#define ADC_RCR_RXCTR_Pos 0
+#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */
+#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos)))
+/* -------- ADC_TPR : (ADC Offset: 0x108) Transmit Pointer Register -------- */
+#define ADC_TPR_TXPTR_Pos 0
+#define ADC_TPR_TXPTR_Msk (0xffffffffu << ADC_TPR_TXPTR_Pos) /**< \brief (ADC_TPR) Transmit Counter Register */
+#define ADC_TPR_TXPTR(value) ((ADC_TPR_TXPTR_Msk & ((value) << ADC_TPR_TXPTR_Pos)))
+/* -------- ADC_TCR : (ADC Offset: 0x10C) Transmit Counter Register -------- */
+#define ADC_TCR_TXCTR_Pos 0
+#define ADC_TCR_TXCTR_Msk (0xffffu << ADC_TCR_TXCTR_Pos) /**< \brief (ADC_TCR) Transmit Counter Register */
+#define ADC_TCR_TXCTR(value) ((ADC_TCR_TXCTR_Msk & ((value) << ADC_TCR_TXCTR_Pos)))
+/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */
+#define ADC_RNPR_RXNPTR_Pos 0
+#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */
+#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos)))
+/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */
+#define ADC_RNCR_RXNCTR_Pos 0
+#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */
+#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos)))
+/* -------- ADC_TNPR : (ADC Offset: 0x118) Transmit Next Pointer Register -------- */
+#define ADC_TNPR_TXNPTR_Pos 0
+#define ADC_TNPR_TXNPTR_Msk (0xffffffffu << ADC_TNPR_TXNPTR_Pos) /**< \brief (ADC_TNPR) Transmit Next Pointer */
+#define ADC_TNPR_TXNPTR(value) ((ADC_TNPR_TXNPTR_Msk & ((value) << ADC_TNPR_TXNPTR_Pos)))
+/* -------- ADC_TNCR : (ADC Offset: 0x11C) Transmit Next Counter Register -------- */
+#define ADC_TNCR_TXNCTR_Pos 0
+#define ADC_TNCR_TXNCTR_Msk (0xffffu << ADC_TNCR_TXNCTR_Pos) /**< \brief (ADC_TNCR) Transmit Counter Next */
+#define ADC_TNCR_TXNCTR(value) ((ADC_TNCR_TXNCTR_Msk & ((value) << ADC_TNCR_TXNCTR_Pos)))
+/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */
+#define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */
+#define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */
+#define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */
+#define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */
+/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */
+#define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */
+#define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_ADC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_can.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_can.h
new file mode 100644
index 000000000..de0b80ce9
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_can.h
@@ -0,0 +1,309 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_CAN_COMPONENT_
+#define _SAM3XA_CAN_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Controller Area Network */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_CAN Controller Area Network */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief CanMb hardware registers */
+typedef struct {
+  RwReg  CAN_MMR;        /**< \brief (CanMb Offset: 0x0) Mailbox Mode Register */
+  RwReg  CAN_MAM;        /**< \brief (CanMb Offset: 0x4) Mailbox Acceptance Mask Register */
+  RwReg  CAN_MID;        /**< \brief (CanMb Offset: 0x8) Mailbox ID Register */
+  RwReg  CAN_MFID;       /**< \brief (CanMb Offset: 0xC) Mailbox Family ID Register */
+  RwReg  CAN_MSR;        /**< \brief (CanMb Offset: 0x10) Mailbox Status Register */
+  RwReg  CAN_MDL;        /**< \brief (CanMb Offset: 0x14) Mailbox Data Low Register */
+  RwReg  CAN_MDH;        /**< \brief (CanMb Offset: 0x18) Mailbox Data High Register */
+  RwReg  CAN_MCR;        /**< \brief (CanMb Offset: 0x1C) Mailbox Control Register */
+} CanMb;
+/** \brief Can hardware registers */
+#define CANMB_NUMBER 8
+typedef struct {
+  RwReg  CAN_MR;         /**< \brief (Can Offset: 0x0000) Mode Register */
+  WoReg  CAN_IER;        /**< \brief (Can Offset: 0x0004) Interrupt Enable Register */
+  WoReg  CAN_IDR;        /**< \brief (Can Offset: 0x0008) Interrupt Disable Register */
+  RoReg  CAN_IMR;        /**< \brief (Can Offset: 0x000C) Interrupt Mask Register */
+  RoReg  CAN_SR;         /**< \brief (Can Offset: 0x0010) Status Register */
+  RwReg  CAN_BR;         /**< \brief (Can Offset: 0x0014) Baudrate Register */
+  RoReg  CAN_TIM;        /**< \brief (Can Offset: 0x0018) Timer Register */
+  RoReg  CAN_TIMESTP;    /**< \brief (Can Offset: 0x001C) Timestamp Register */
+  RoReg  CAN_ECR;        /**< \brief (Can Offset: 0x0020) Error Counter Register */
+  WoReg  CAN_TCR;        /**< \brief (Can Offset: 0x0024) Transfer Command Register */
+  WoReg  CAN_ACR;        /**< \brief (Can Offset: 0x0028) Abort Command Register */
+  RoReg  Reserved1[117];
+  CanMb  CAN_MB[CANMB_NUMBER]; /**< \brief (Can Offset: 0x200) MB = 0 .. 7 */
+} Can;
+#endif /* __ASSEMBLY__ */
+/* -------- CAN_MR : (CAN Offset: 0x0000) Mode Register -------- */
+#define CAN_MR_CANEN (0x1u << 0) /**< \brief (CAN_MR) CAN Controller Enable */
+#define CAN_MR_LPM (0x1u << 1) /**< \brief (CAN_MR) Disable/Enable Low Power Mode */
+#define CAN_MR_ABM (0x1u << 2) /**< \brief (CAN_MR) Disable/Enable Autobaud/Listen mode */
+#define CAN_MR_OVL (0x1u << 3) /**< \brief (CAN_MR) Disable/Enable Overload Frame */
+#define CAN_MR_TEOF (0x1u << 4) /**< \brief (CAN_MR) Timestamp messages at each end of Frame */
+#define CAN_MR_TTM (0x1u << 5) /**< \brief (CAN_MR) Disable/Enable Time Triggered Mode */
+#define CAN_MR_TIMFRZ (0x1u << 6) /**< \brief (CAN_MR) Enable Timer Freeze */
+#define CAN_MR_DRPT (0x1u << 7) /**< \brief (CAN_MR) Disable Repeat */
+#define CAN_MR_RXSYNC_Pos 24
+#define CAN_MR_RXSYNC_Msk (0x7u << CAN_MR_RXSYNC_Pos) /**< \brief (CAN_MR) Reception Synchronization Stage (not readable) */
+#define   CAN_MR_RXSYNC_DOUBLE_PP (0x0u << 24) /**< \brief (CAN_MR) Rx Signal with Double Synchro Stages (2 Positive Edges) */
+#define   CAN_MR_RXSYNC_DOUBLE_PN (0x1u << 24) /**< \brief (CAN_MR) Rx Signal with Double Synchro Stages (One Positive Edge and One Negative Edge) */
+#define   CAN_MR_RXSYNC_SINGLE_P (0x2u << 24) /**< \brief (CAN_MR) Rx Signal with Single Synchro Stage (Positive Edge) */
+#define   CAN_MR_RXSYNC_NONE (0x3u << 24) /**< \brief (CAN_MR) Rx Signal with No Synchro Stage */
+/* -------- CAN_IER : (CAN Offset: 0x0004) Interrupt Enable Register -------- */
+#define CAN_IER_MB0 (0x1u << 0) /**< \brief (CAN_IER) Mailbox 0 Interrupt Enable */
+#define CAN_IER_MB1 (0x1u << 1) /**< \brief (CAN_IER) Mailbox 1 Interrupt Enable */
+#define CAN_IER_MB2 (0x1u << 2) /**< \brief (CAN_IER) Mailbox 2 Interrupt Enable */
+#define CAN_IER_MB3 (0x1u << 3) /**< \brief (CAN_IER) Mailbox 3 Interrupt Enable */
+#define CAN_IER_MB4 (0x1u << 4) /**< \brief (CAN_IER) Mailbox 4 Interrupt Enable */
+#define CAN_IER_MB5 (0x1u << 5) /**< \brief (CAN_IER) Mailbox 5 Interrupt Enable */
+#define CAN_IER_MB6 (0x1u << 6) /**< \brief (CAN_IER) Mailbox 6 Interrupt Enable */
+#define CAN_IER_MB7 (0x1u << 7) /**< \brief (CAN_IER) Mailbox 7 Interrupt Enable */
+#define CAN_IER_ERRA (0x1u << 16) /**< \brief (CAN_IER) Error Active Mode Interrupt Enable */
+#define CAN_IER_WARN (0x1u << 17) /**< \brief (CAN_IER) Warning Limit Interrupt Enable */
+#define CAN_IER_ERRP (0x1u << 18) /**< \brief (CAN_IER) Error Passive Mode Interrupt Enable */
+#define CAN_IER_BOFF (0x1u << 19) /**< \brief (CAN_IER) Bus Off Mode Interrupt Enable */
+#define CAN_IER_SLEEP (0x1u << 20) /**< \brief (CAN_IER) Sleep Interrupt Enable */
+#define CAN_IER_WAKEUP (0x1u << 21) /**< \brief (CAN_IER) Wakeup Interrupt Enable */
+#define CAN_IER_TOVF (0x1u << 22) /**< \brief (CAN_IER) Timer Overflow Interrupt Enable */
+#define CAN_IER_TSTP (0x1u << 23) /**< \brief (CAN_IER) TimeStamp Interrupt Enable */
+#define CAN_IER_CERR (0x1u << 24) /**< \brief (CAN_IER) CRC Error Interrupt Enable */
+#define CAN_IER_SERR (0x1u << 25) /**< \brief (CAN_IER) Stuffing Error Interrupt Enable */
+#define CAN_IER_AERR (0x1u << 26) /**< \brief (CAN_IER) Acknowledgment Error Interrupt Enable */
+#define CAN_IER_FERR (0x1u << 27) /**< \brief (CAN_IER) Form Error Interrupt Enable */
+#define CAN_IER_BERR (0x1u << 28) /**< \brief (CAN_IER) Bit Error Interrupt Enable */
+/* -------- CAN_IDR : (CAN Offset: 0x0008) Interrupt Disable Register -------- */
+#define CAN_IDR_MB0 (0x1u << 0) /**< \brief (CAN_IDR) Mailbox 0 Interrupt Disable */
+#define CAN_IDR_MB1 (0x1u << 1) /**< \brief (CAN_IDR) Mailbox 1 Interrupt Disable */
+#define CAN_IDR_MB2 (0x1u << 2) /**< \brief (CAN_IDR) Mailbox 2 Interrupt Disable */
+#define CAN_IDR_MB3 (0x1u << 3) /**< \brief (CAN_IDR) Mailbox 3 Interrupt Disable */
+#define CAN_IDR_MB4 (0x1u << 4) /**< \brief (CAN_IDR) Mailbox 4 Interrupt Disable */
+#define CAN_IDR_MB5 (0x1u << 5) /**< \brief (CAN_IDR) Mailbox 5 Interrupt Disable */
+#define CAN_IDR_MB6 (0x1u << 6) /**< \brief (CAN_IDR) Mailbox 6 Interrupt Disable */
+#define CAN_IDR_MB7 (0x1u << 7) /**< \brief (CAN_IDR) Mailbox 7 Interrupt Disable */
+#define CAN_IDR_ERRA (0x1u << 16) /**< \brief (CAN_IDR) Error Active Mode Interrupt Disable */
+#define CAN_IDR_WARN (0x1u << 17) /**< \brief (CAN_IDR) Warning Limit Interrupt Disable */
+#define CAN_IDR_ERRP (0x1u << 18) /**< \brief (CAN_IDR) Error Passive Mode Interrupt Disable */
+#define CAN_IDR_BOFF (0x1u << 19) /**< \brief (CAN_IDR) Bus Off Mode Interrupt Disable */
+#define CAN_IDR_SLEEP (0x1u << 20) /**< \brief (CAN_IDR) Sleep Interrupt Disable */
+#define CAN_IDR_WAKEUP (0x1u << 21) /**< \brief (CAN_IDR) Wakeup Interrupt Disable */
+#define CAN_IDR_TOVF (0x1u << 22) /**< \brief (CAN_IDR) Timer Overflow Interrupt */
+#define CAN_IDR_TSTP (0x1u << 23) /**< \brief (CAN_IDR) TimeStamp Interrupt Disable */
+#define CAN_IDR_CERR (0x1u << 24) /**< \brief (CAN_IDR) CRC Error Interrupt Disable */
+#define CAN_IDR_SERR (0x1u << 25) /**< \brief (CAN_IDR) Stuffing Error Interrupt Disable */
+#define CAN_IDR_AERR (0x1u << 26) /**< \brief (CAN_IDR) Acknowledgment Error Interrupt Disable */
+#define CAN_IDR_FERR (0x1u << 27) /**< \brief (CAN_IDR) Form Error Interrupt Disable */
+#define CAN_IDR_BERR (0x1u << 28) /**< \brief (CAN_IDR) Bit Error Interrupt Disable */
+/* -------- CAN_IMR : (CAN Offset: 0x000C) Interrupt Mask Register -------- */
+#define CAN_IMR_MB0 (0x1u << 0) /**< \brief (CAN_IMR) Mailbox 0 Interrupt Mask */
+#define CAN_IMR_MB1 (0x1u << 1) /**< \brief (CAN_IMR) Mailbox 1 Interrupt Mask */
+#define CAN_IMR_MB2 (0x1u << 2) /**< \brief (CAN_IMR) Mailbox 2 Interrupt Mask */
+#define CAN_IMR_MB3 (0x1u << 3) /**< \brief (CAN_IMR) Mailbox 3 Interrupt Mask */
+#define CAN_IMR_MB4 (0x1u << 4) /**< \brief (CAN_IMR) Mailbox 4 Interrupt Mask */
+#define CAN_IMR_MB5 (0x1u << 5) /**< \brief (CAN_IMR) Mailbox 5 Interrupt Mask */
+#define CAN_IMR_MB6 (0x1u << 6) /**< \brief (CAN_IMR) Mailbox 6 Interrupt Mask */
+#define CAN_IMR_MB7 (0x1u << 7) /**< \brief (CAN_IMR) Mailbox 7 Interrupt Mask */
+#define CAN_IMR_ERRA (0x1u << 16) /**< \brief (CAN_IMR) Error Active Mode Interrupt Mask */
+#define CAN_IMR_WARN (0x1u << 17) /**< \brief (CAN_IMR) Warning Limit Interrupt Mask */
+#define CAN_IMR_ERRP (0x1u << 18) /**< \brief (CAN_IMR) Error Passive Mode Interrupt Mask */
+#define CAN_IMR_BOFF (0x1u << 19) /**< \brief (CAN_IMR) Bus Off Mode Interrupt Mask */
+#define CAN_IMR_SLEEP (0x1u << 20) /**< \brief (CAN_IMR) Sleep Interrupt Mask */
+#define CAN_IMR_WAKEUP (0x1u << 21) /**< \brief (CAN_IMR) Wakeup Interrupt Mask */
+#define CAN_IMR_TOVF (0x1u << 22) /**< \brief (CAN_IMR) Timer Overflow Interrupt Mask */
+#define CAN_IMR_TSTP (0x1u << 23) /**< \brief (CAN_IMR) Timestamp Interrupt Mask */
+#define CAN_IMR_CERR (0x1u << 24) /**< \brief (CAN_IMR) CRC Error Interrupt Mask */
+#define CAN_IMR_SERR (0x1u << 25) /**< \brief (CAN_IMR) Stuffing Error Interrupt Mask */
+#define CAN_IMR_AERR (0x1u << 26) /**< \brief (CAN_IMR) Acknowledgment Error Interrupt Mask */
+#define CAN_IMR_FERR (0x1u << 27) /**< \brief (CAN_IMR) Form Error Interrupt Mask */
+#define CAN_IMR_BERR (0x1u << 28) /**< \brief (CAN_IMR) Bit Error Interrupt Mask */
+/* -------- CAN_SR : (CAN Offset: 0x0010) Status Register -------- */
+#define CAN_SR_MB0 (0x1u << 0) /**< \brief (CAN_SR) Mailbox 0 Event */
+#define CAN_SR_MB1 (0x1u << 1) /**< \brief (CAN_SR) Mailbox 1 Event */
+#define CAN_SR_MB2 (0x1u << 2) /**< \brief (CAN_SR) Mailbox 2 Event */
+#define CAN_SR_MB3 (0x1u << 3) /**< \brief (CAN_SR) Mailbox 3 Event */
+#define CAN_SR_MB4 (0x1u << 4) /**< \brief (CAN_SR) Mailbox 4 Event */
+#define CAN_SR_MB5 (0x1u << 5) /**< \brief (CAN_SR) Mailbox 5 Event */
+#define CAN_SR_MB6 (0x1u << 6) /**< \brief (CAN_SR) Mailbox 6 Event */
+#define CAN_SR_MB7 (0x1u << 7) /**< \brief (CAN_SR) Mailbox 7 Event */
+#define CAN_SR_ERRA (0x1u << 16) /**< \brief (CAN_SR) Error Active Mode */
+#define CAN_SR_WARN (0x1u << 17) /**< \brief (CAN_SR) Warning Limit */
+#define CAN_SR_ERRP (0x1u << 18) /**< \brief (CAN_SR) Error Passive Mode */
+#define CAN_SR_BOFF (0x1u << 19) /**< \brief (CAN_SR) Bus Off Mode */
+#define CAN_SR_SLEEP (0x1u << 20) /**< \brief (CAN_SR) CAN controller in Low power Mode */
+#define CAN_SR_WAKEUP (0x1u << 21) /**< \brief (CAN_SR) CAN controller is not in Low power Mode */
+#define CAN_SR_TOVF (0x1u << 22) /**< \brief (CAN_SR) Timer Overflow */
+#define CAN_SR_TSTP (0x1u << 23) /**< \brief (CAN_SR)  */
+#define CAN_SR_CERR (0x1u << 24) /**< \brief (CAN_SR) Mailbox CRC Error */
+#define CAN_SR_SERR (0x1u << 25) /**< \brief (CAN_SR) Mailbox Stuffing Error */
+#define CAN_SR_AERR (0x1u << 26) /**< \brief (CAN_SR) Acknowledgment Error */
+#define CAN_SR_FERR (0x1u << 27) /**< \brief (CAN_SR) Form Error */
+#define CAN_SR_BERR (0x1u << 28) /**< \brief (CAN_SR) Bit Error */
+#define CAN_SR_RBSY (0x1u << 29) /**< \brief (CAN_SR) Receiver busy */
+#define CAN_SR_TBSY (0x1u << 30) /**< \brief (CAN_SR) Transmitter busy */
+#define CAN_SR_OVLSY (0x1u << 31) /**< \brief (CAN_SR) Overload busy */
+/* -------- CAN_BR : (CAN Offset: 0x0014) Baudrate Register -------- */
+#define CAN_BR_PHASE2_Pos 0
+#define CAN_BR_PHASE2_Msk (0x7u << CAN_BR_PHASE2_Pos) /**< \brief (CAN_BR) Phase 2 segment */
+#define CAN_BR_PHASE2(value) ((CAN_BR_PHASE2_Msk & ((value) << CAN_BR_PHASE2_Pos)))
+#define CAN_BR_PHASE1_Pos 4
+#define CAN_BR_PHASE1_Msk (0x7u << CAN_BR_PHASE1_Pos) /**< \brief (CAN_BR) Phase 1 segment */
+#define CAN_BR_PHASE1(value) ((CAN_BR_PHASE1_Msk & ((value) << CAN_BR_PHASE1_Pos)))
+#define CAN_BR_PROPAG_Pos 8
+#define CAN_BR_PROPAG_Msk (0x7u << CAN_BR_PROPAG_Pos) /**< \brief (CAN_BR) Programming time segment */
+#define CAN_BR_PROPAG(value) ((CAN_BR_PROPAG_Msk & ((value) << CAN_BR_PROPAG_Pos)))
+#define CAN_BR_SJW_Pos 12
+#define CAN_BR_SJW_Msk (0x3u << CAN_BR_SJW_Pos) /**< \brief (CAN_BR) Re-synchronization jump width */
+#define CAN_BR_SJW(value) ((CAN_BR_SJW_Msk & ((value) << CAN_BR_SJW_Pos)))
+#define CAN_BR_BRP_Pos 16
+#define CAN_BR_BRP_Msk (0x7fu << CAN_BR_BRP_Pos) /**< \brief (CAN_BR) Baudrate Prescaler. */
+#define CAN_BR_BRP(value) ((CAN_BR_BRP_Msk & ((value) << CAN_BR_BRP_Pos)))
+#define CAN_BR_SMP (0x1u << 24) /**< \brief (CAN_BR) Sampling Mode */
+#define   CAN_BR_SMP_ONCE (0x0u << 24) /**< \brief (CAN_BR) The incoming bit stream is sampled once at sample point. */
+#define   CAN_BR_SMP_THREE (0x1u << 24) /**< \brief (CAN_BR) The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point. */
+/* -------- CAN_TIM : (CAN Offset: 0x0018) Timer Register -------- */
+#define CAN_TIM_TIMER0 (0x1u << 0) /**< \brief (CAN_TIM) Timer */
+#define CAN_TIM_TIMER1 (0x1u << 1) /**< \brief (CAN_TIM) Timer */
+#define CAN_TIM_TIMER2 (0x1u << 2) /**< \brief (CAN_TIM) Timer */
+#define CAN_TIM_TIMER3 (0x1u << 3) /**< \brief (CAN_TIM) Timer */
+#define CAN_TIM_TIMER4 (0x1u << 4) /**< \brief (CAN_TIM) Timer */
+#define CAN_TIM_TIMER5 (0x1u << 5) /**< \brief (CAN_TIM) Timer */
+#define CAN_TIM_TIMER6 (0x1u << 6) /**< \brief (CAN_TIM) Timer */
+#define CAN_TIM_TIMER7 (0x1u << 7) /**< \brief (CAN_TIM) Timer */
+/* -------- CAN_TIMESTP : (CAN Offset: 0x001C) Timestamp Register -------- */
+#define CAN_TIMESTP_MTIMESTAMP0 (0x1u << 0) /**< \brief (CAN_TIMESTP) Timestamp */
+#define CAN_TIMESTP_MTIMESTAMP1 (0x1u << 1) /**< \brief (CAN_TIMESTP) Timestamp */
+#define CAN_TIMESTP_MTIMESTAMP2 (0x1u << 2) /**< \brief (CAN_TIMESTP) Timestamp */
+#define CAN_TIMESTP_MTIMESTAMP3 (0x1u << 3) /**< \brief (CAN_TIMESTP) Timestamp */
+#define CAN_TIMESTP_MTIMESTAMP4 (0x1u << 4) /**< \brief (CAN_TIMESTP) Timestamp */
+#define CAN_TIMESTP_MTIMESTAMP5 (0x1u << 5) /**< \brief (CAN_TIMESTP) Timestamp */
+#define CAN_TIMESTP_MTIMESTAMP6 (0x1u << 6) /**< \brief (CAN_TIMESTP) Timestamp */
+#define CAN_TIMESTP_MTIMESTAMP7 (0x1u << 7) /**< \brief (CAN_TIMESTP) Timestamp */
+/* -------- CAN_ECR : (CAN Offset: 0x0020) Error Counter Register -------- */
+#define CAN_ECR_REC_Pos 0
+#define CAN_ECR_REC_Msk (0xffu << CAN_ECR_REC_Pos) /**< \brief (CAN_ECR) Receive Error Counter */
+#define CAN_ECR_TEC_Pos 16
+#define CAN_ECR_TEC_Msk (0xffu << CAN_ECR_TEC_Pos) /**< \brief (CAN_ECR) Transmit Error Counter */
+/* -------- CAN_TCR : (CAN Offset: 0x0024) Transfer Command Register -------- */
+#define CAN_TCR_MB0 (0x1u << 0) /**< \brief (CAN_TCR) Transfer Request for Mailbox 0 */
+#define CAN_TCR_MB1 (0x1u << 1) /**< \brief (CAN_TCR) Transfer Request for Mailbox 1 */
+#define CAN_TCR_MB2 (0x1u << 2) /**< \brief (CAN_TCR) Transfer Request for Mailbox 2 */
+#define CAN_TCR_MB3 (0x1u << 3) /**< \brief (CAN_TCR) Transfer Request for Mailbox 3 */
+#define CAN_TCR_MB4 (0x1u << 4) /**< \brief (CAN_TCR) Transfer Request for Mailbox 4 */
+#define CAN_TCR_MB5 (0x1u << 5) /**< \brief (CAN_TCR) Transfer Request for Mailbox 5 */
+#define CAN_TCR_MB6 (0x1u << 6) /**< \brief (CAN_TCR) Transfer Request for Mailbox 6 */
+#define CAN_TCR_MB7 (0x1u << 7) /**< \brief (CAN_TCR) Transfer Request for Mailbox 7 */
+#define CAN_TCR_TIMRST (0x1u << 31) /**< \brief (CAN_TCR) Timer Reset */
+/* -------- CAN_ACR : (CAN Offset: 0x0028) Abort Command Register -------- */
+#define CAN_ACR_MB0 (0x1u << 0) /**< \brief (CAN_ACR) Abort Request for Mailbox 0 */
+#define CAN_ACR_MB1 (0x1u << 1) /**< \brief (CAN_ACR) Abort Request for Mailbox 1 */
+#define CAN_ACR_MB2 (0x1u << 2) /**< \brief (CAN_ACR) Abort Request for Mailbox 2 */
+#define CAN_ACR_MB3 (0x1u << 3) /**< \brief (CAN_ACR) Abort Request for Mailbox 3 */
+#define CAN_ACR_MB4 (0x1u << 4) /**< \brief (CAN_ACR) Abort Request for Mailbox 4 */
+#define CAN_ACR_MB5 (0x1u << 5) /**< \brief (CAN_ACR) Abort Request for Mailbox 5 */
+#define CAN_ACR_MB6 (0x1u << 6) /**< \brief (CAN_ACR) Abort Request for Mailbox 6 */
+#define CAN_ACR_MB7 (0x1u << 7) /**< \brief (CAN_ACR) Abort Request for Mailbox 7 */
+/* -------- CAN_MMR : (CAN Offset: N/A) Mailbox Mode Register -------- */
+#define CAN_MMR_MTIMEMARK0 (0x1u << 0) /**< \brief (CAN_MMR) Mailbox Timemark */
+#define CAN_MMR_MTIMEMARK1 (0x1u << 1) /**< \brief (CAN_MMR) Mailbox Timemark */
+#define CAN_MMR_MTIMEMARK2 (0x1u << 2) /**< \brief (CAN_MMR) Mailbox Timemark */
+#define CAN_MMR_MTIMEMARK3 (0x1u << 3) /**< \brief (CAN_MMR) Mailbox Timemark */
+#define CAN_MMR_MTIMEMARK4 (0x1u << 4) /**< \brief (CAN_MMR) Mailbox Timemark */
+#define CAN_MMR_MTIMEMARK5 (0x1u << 5) /**< \brief (CAN_MMR) Mailbox Timemark */
+#define CAN_MMR_MTIMEMARK6 (0x1u << 6) /**< \brief (CAN_MMR) Mailbox Timemark */
+#define CAN_MMR_MTIMEMARK7 (0x1u << 7) /**< \brief (CAN_MMR) Mailbox Timemark */
+#define CAN_MMR_PRIOR_Pos 16
+#define CAN_MMR_PRIOR_Msk (0xfu << CAN_MMR_PRIOR_Pos) /**< \brief (CAN_MMR) Mailbox Priority */
+#define CAN_MMR_PRIOR(value) ((CAN_MMR_PRIOR_Msk & ((value) << CAN_MMR_PRIOR_Pos)))
+#define CAN_MMR_MOT_Pos 24
+#define CAN_MMR_MOT_Msk (0x7u << CAN_MMR_MOT_Pos) /**< \brief (CAN_MMR) Mailbox Object Type */
+#define   CAN_MMR_MOT_MB_DISABLED (0x0u << 24) /**< \brief (CAN_MMR) Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. */
+#define   CAN_MMR_MOT_MB_RX (0x1u << 24) /**< \brief (CAN_MMR) Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. */
+#define   CAN_MMR_MOT_MB_RX_OVERWRITE (0x2u << 24) /**< \brief (CAN_MMR) Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. */
+#define   CAN_MMR_MOT_MB_TX (0x3u << 24) /**< \brief (CAN_MMR) Transmit mailbox. Mailbox is configured for transmission. */
+#define   CAN_MMR_MOT_MB_CONSUMER (0x4u << 24) /**< \brief (CAN_MMR) Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. */
+#define   CAN_MMR_MOT_MB_PRODUCER (0x5u << 24) /**< \brief (CAN_MMR) Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. */
+/* -------- CAN_MAM : (CAN Offset: N/A) Mailbox Acceptance Mask Register -------- */
+#define CAN_MAM_MIDvB_Pos 0
+#define CAN_MAM_MIDvB_Msk (0x3ffffu << CAN_MAM_MIDvB_Pos) /**< \brief (CAN_MAM) Complementary bits for identifier in extended frame mode */
+#define CAN_MAM_MIDvB(value) ((CAN_MAM_MIDvB_Msk & ((value) << CAN_MAM_MIDvB_Pos)))
+#define CAN_MAM_MIDvA_Pos 18
+#define CAN_MAM_MIDvA_Msk (0x7ffu << CAN_MAM_MIDvA_Pos) /**< \brief (CAN_MAM) Identifier for standard frame mode */
+#define CAN_MAM_MIDvA(value) ((CAN_MAM_MIDvA_Msk & ((value) << CAN_MAM_MIDvA_Pos)))
+#define CAN_MAM_MIDE (0x1u << 29) /**< \brief (CAN_MAM) Identifier Version */
+/* -------- CAN_MID : (CAN Offset: N/A) Mailbox ID Register -------- */
+#define CAN_MID_MIDvB_Pos 0
+#define CAN_MID_MIDvB_Msk (0x3ffffu << CAN_MID_MIDvB_Pos) /**< \brief (CAN_MID) Complementary bits for identifier in extended frame mode */
+#define CAN_MID_MIDvB(value) ((CAN_MID_MIDvB_Msk & ((value) << CAN_MID_MIDvB_Pos)))
+#define CAN_MID_MIDvA_Pos 18
+#define CAN_MID_MIDvA_Msk (0x7ffu << CAN_MID_MIDvA_Pos) /**< \brief (CAN_MID) Identifier for standard frame mode */
+#define CAN_MID_MIDvA(value) ((CAN_MID_MIDvA_Msk & ((value) << CAN_MID_MIDvA_Pos)))
+#define CAN_MID_MIDE (0x1u << 29) /**< \brief (CAN_MID) Identifier Version */
+/* -------- CAN_MFID : (CAN Offset: N/A) Mailbox Family ID Register -------- */
+#define CAN_MFID_MFID_Pos 0
+#define CAN_MFID_MFID_Msk (0x1fffffffu << CAN_MFID_MFID_Pos) /**< \brief (CAN_MFID) Family ID */
+/* -------- CAN_MSR : (CAN Offset: N/A) Mailbox Status Register -------- */
+#define CAN_MSR_MTIMESTAMP0 (0x1u << 0) /**< \brief (CAN_MSR) Timer value */
+#define CAN_MSR_MTIMESTAMP1 (0x1u << 1) /**< \brief (CAN_MSR) Timer value */
+#define CAN_MSR_MTIMESTAMP2 (0x1u << 2) /**< \brief (CAN_MSR) Timer value */
+#define CAN_MSR_MTIMESTAMP3 (0x1u << 3) /**< \brief (CAN_MSR) Timer value */
+#define CAN_MSR_MTIMESTAMP4 (0x1u << 4) /**< \brief (CAN_MSR) Timer value */
+#define CAN_MSR_MTIMESTAMP5 (0x1u << 5) /**< \brief (CAN_MSR) Timer value */
+#define CAN_MSR_MTIMESTAMP6 (0x1u << 6) /**< \brief (CAN_MSR) Timer value */
+#define CAN_MSR_MTIMESTAMP7 (0x1u << 7) /**< \brief (CAN_MSR) Timer value */
+#define CAN_MSR_MDLC_Pos 16
+#define CAN_MSR_MDLC_Msk (0xfu << CAN_MSR_MDLC_Pos) /**< \brief (CAN_MSR) Mailbox Data Length Code */
+#define CAN_MSR_MRTR (0x1u << 20) /**< \brief (CAN_MSR) Mailbox Remote Transmission Request */
+#define CAN_MSR_MABT (0x1u << 22) /**< \brief (CAN_MSR) Mailbox Message Abort */
+#define CAN_MSR_MRDY (0x1u << 23) /**< \brief (CAN_MSR) Mailbox Ready */
+#define CAN_MSR_MMI (0x1u << 24) /**< \brief (CAN_MSR) Mailbox Message Ignored */
+/* -------- CAN_MDL : (CAN Offset: N/A) Mailbox Data Low Register -------- */
+#define CAN_MDL_MDL_Pos 0
+#define CAN_MDL_MDL_Msk (0xffffffffu << CAN_MDL_MDL_Pos) /**< \brief (CAN_MDL) Message Data Low Value */
+#define CAN_MDL_MDL(value) ((CAN_MDL_MDL_Msk & ((value) << CAN_MDL_MDL_Pos)))
+/* -------- CAN_MDH : (CAN Offset: N/A) Mailbox Data High Register -------- */
+#define CAN_MDH_MDH_Pos 0
+#define CAN_MDH_MDH_Msk (0xffffffffu << CAN_MDH_MDH_Pos) /**< \brief (CAN_MDH) Message Data High Value */
+#define CAN_MDH_MDH(value) ((CAN_MDH_MDH_Msk & ((value) << CAN_MDH_MDH_Pos)))
+/* -------- CAN_MCR : (CAN Offset: N/A) Mailbox Control Register -------- */
+#define CAN_MCR_MDLC_Pos 16
+#define CAN_MCR_MDLC_Msk (0xfu << CAN_MCR_MDLC_Pos) /**< \brief (CAN_MCR) Mailbox Data Length Code */
+#define CAN_MCR_MDLC(value) ((CAN_MCR_MDLC_Msk & ((value) << CAN_MCR_MDLC_Pos)))
+#define CAN_MCR_MRTR (0x1u << 20) /**< \brief (CAN_MCR) Mailbox Remote Transmission Request */
+#define CAN_MCR_MACR (0x1u << 22) /**< \brief (CAN_MCR) Abort Request for Mailbox x */
+#define CAN_MCR_MTCR (0x1u << 23) /**< \brief (CAN_MCR) Mailbox Transfer Command */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_CAN_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_chipid.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_chipid.h
new file mode 100644
index 000000000..16bb3659a
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_chipid.h
@@ -0,0 +1,159 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_CHIPID_COMPONENT_
+#define _SAM3XA_CHIPID_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Chip Identifier */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_CHIPID Chip Identifier */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Chipid hardware registers */
+typedef struct {
+  RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */
+  RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */
+} Chipid;
+#endif /* __ASSEMBLY__ */
+/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */
+#define CHIPID_CIDR_VERSION_Pos 0
+#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */
+#define CHIPID_CIDR_EPROC_Pos 5
+#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */
+#define   CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */
+#define   CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */
+#define   CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */
+#define   CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */
+#define   CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */
+#define   CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */
+#define   CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */
+#define CHIPID_CIDR_NVPSIZ_Pos 8
+#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */
+#define   CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */
+#define   CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define   CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define   CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_NVPSIZ2_Pos 12
+#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */
+#define   CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */
+#define   CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_SRAMSIZ_Pos 16
+#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */
+#define   CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_1K (0x1u << 16) /**< \brief (CHIPID_CIDR) 1K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define CHIPID_CIDR_ARCH_Pos 20
+#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */
+#define   CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */
+#define   CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */
+#define   CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */
+#define   CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */
+#define   CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */
+#define   CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */
+#define   CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */
+#define   CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */
+#define   CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */
+#define   CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM4AxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM4XxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM4XxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxG Series (208/217-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM4XxG Series (208/217-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM3SxASeries (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM4SxA Series (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM3SxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM4SxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM3SxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM4SxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */
+#define   CHIPID_CIDR_ARCH_SAM3NxA (0x93u << 20) /**< \brief (CHIPID_CIDR) SAM3NxA Series (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3NxB (0x94u << 20) /**< \brief (CHIPID_CIDR) SAM3NxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3NxC (0x95u << 20) /**< \brief (CHIPID_CIDR) SAM3NxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */
+#define   CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */
+#define CHIPID_CIDR_NVPTYP_Pos 28
+#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */
+#define   CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */
+#define   CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */
+#define   CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */
+#define   CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size      NVPSIZ2 is Flash size */
+#define   CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */
+#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */
+/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */
+#define CHIPID_EXID_EXID_Pos 0
+#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_CHIPID_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_dacc.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_dacc.h
new file mode 100644
index 000000000..afa720599
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_dacc.h
@@ -0,0 +1,227 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_DACC_COMPONENT_
+#define _SAM3XA_DACC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_DACC Digital-to-Analog Converter Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Dacc hardware registers */
+typedef struct {
+  WoReg DACC_CR;       /**< \brief (Dacc Offset: 0x00) Control Register */
+  RwReg DACC_MR;       /**< \brief (Dacc Offset: 0x04) Mode Register */
+  RoReg Reserved1[2];
+  WoReg DACC_CHER;     /**< \brief (Dacc Offset: 0x10) Channel Enable Register */
+  WoReg DACC_CHDR;     /**< \brief (Dacc Offset: 0x14) Channel Disable Register */
+  RoReg DACC_CHSR;     /**< \brief (Dacc Offset: 0x18) Channel Status Register */
+  RoReg Reserved2[1];
+  WoReg DACC_CDR;      /**< \brief (Dacc Offset: 0x20) Conversion Data Register */
+  WoReg DACC_IER;      /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */
+  WoReg DACC_IDR;      /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */
+  RoReg DACC_IMR;      /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */
+  RoReg DACC_ISR;      /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */
+  RoReg Reserved3[24];
+  RwReg DACC_ACR;      /**< \brief (Dacc Offset: 0x94) Analog Current Register */
+  RoReg Reserved4[19];
+  RwReg DACC_WPMR;     /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */
+  RoReg DACC_WPSR;     /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */
+  RoReg Reserved5[5];
+  RwReg DACC_RPR;      /**< \brief (Dacc Offset: 0x100) Receive Pointer Register */
+  RwReg DACC_RCR;      /**< \brief (Dacc Offset: 0x104) Receive Counter Register */
+  RwReg DACC_TPR;      /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */
+  RwReg DACC_TCR;      /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */
+  RwReg DACC_RNPR;     /**< \brief (Dacc Offset: 0x110) Receive Next Pointer Register */
+  RwReg DACC_RNCR;     /**< \brief (Dacc Offset: 0x114) Receive Next Counter Register */
+  RwReg DACC_TNPR;     /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */
+  RwReg DACC_TNCR;     /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */
+  WoReg DACC_PTCR;     /**< \brief (Dacc Offset: 0x120) Transfer Control Register */
+  RoReg DACC_PTSR;     /**< \brief (Dacc Offset: 0x124) Transfer Status Register */
+} Dacc;
+#endif /* __ASSEMBLY__ */
+/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */
+#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */
+/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */
+#define DACC_MR_TRGEN (0x1u << 0) /**< \brief (DACC_MR) Trigger Enable */
+#define   DACC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (DACC_MR) External trigger mode disabled. DACC in free running mode. */
+#define   DACC_MR_TRGEN_EN (0x1u << 0) /**< \brief (DACC_MR) External trigger mode enabled. */
+#define DACC_MR_TRGSEL_Pos 1
+#define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) /**< \brief (DACC_MR) Trigger Selection */
+#define DACC_MR_TRGSEL(value) ((DACC_MR_TRGSEL_Msk & ((value) << DACC_MR_TRGSEL_Pos)))
+#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */
+#define   DACC_MR_WORD_HALF (0x0u << 4) /**< \brief (DACC_MR) Half-Word transfer */
+#define   DACC_MR_WORD_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */
+#define DACC_MR_SLEEP (0x1u << 5) /**< \brief (DACC_MR) Sleep Mode */
+#define DACC_MR_FASTWKUP (0x1u << 6) /**< \brief (DACC_MR) Fast Wake up Mode */
+#define DACC_MR_REFRESH_Pos 8
+#define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */
+#define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos)))
+#define DACC_MR_USER_SEL_Pos 16
+#define DACC_MR_USER_SEL_Msk (0x3u << DACC_MR_USER_SEL_Pos) /**< \brief (DACC_MR) User Channel Selection */
+#define   DACC_MR_USER_SEL_CHANNEL0 (0x0u << 16) /**< \brief (DACC_MR) Channel 0 */
+#define   DACC_MR_USER_SEL_CHANNEL1 (0x1u << 16) /**< \brief (DACC_MR) Channel 1 */
+#define DACC_MR_TAG (0x1u << 20) /**< \brief (DACC_MR) Tag Selection Mode */
+#define   DACC_MR_TAG_DIS (0x0u << 20) /**< \brief (DACC_MR) Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. */
+#define   DACC_MR_TAG_EN (0x1u << 20) /**< \brief (DACC_MR) Tag selection mode enabled */
+#define DACC_MR_MAXS (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode */
+#define DACC_MR_STARTUP_Pos 24
+#define DACC_MR_STARTUP_Msk (0x3fu << DACC_MR_STARTUP_Pos) /**< \brief (DACC_MR) Startup Time Selection */
+#define   DACC_MR_STARTUP_0 (0x0u << 24) /**< \brief (DACC_MR) 0 periods of DACClock */
+#define   DACC_MR_STARTUP_8 (0x1u << 24) /**< \brief (DACC_MR) 8 periods of DACClock */
+#define   DACC_MR_STARTUP_16 (0x2u << 24) /**< \brief (DACC_MR) 16 periods of DACClock */
+#define   DACC_MR_STARTUP_24 (0x3u << 24) /**< \brief (DACC_MR) 24 periods of DACClock */
+#define   DACC_MR_STARTUP_64 (0x4u << 24) /**< \brief (DACC_MR) 64 periods of DACClock */
+#define   DACC_MR_STARTUP_80 (0x5u << 24) /**< \brief (DACC_MR) 80 periods of DACClock */
+#define   DACC_MR_STARTUP_96 (0x6u << 24) /**< \brief (DACC_MR) 96 periods of DACClock */
+#define   DACC_MR_STARTUP_112 (0x7u << 24) /**< \brief (DACC_MR) 112 periods of DACClock */
+#define   DACC_MR_STARTUP_512 (0x8u << 24) /**< \brief (DACC_MR) 512 periods of DACClock */
+#define   DACC_MR_STARTUP_576 (0x9u << 24) /**< \brief (DACC_MR) 576 periods of DACClock */
+#define   DACC_MR_STARTUP_640 (0xAu << 24) /**< \brief (DACC_MR) 640 periods of DACClock */
+#define   DACC_MR_STARTUP_704 (0xBu << 24) /**< \brief (DACC_MR) 704 periods of DACClock */
+#define   DACC_MR_STARTUP_768 (0xCu << 24) /**< \brief (DACC_MR) 768 periods of DACClock */
+#define   DACC_MR_STARTUP_832 (0xDu << 24) /**< \brief (DACC_MR) 832 periods of DACClock */
+#define   DACC_MR_STARTUP_896 (0xEu << 24) /**< \brief (DACC_MR) 896 periods of DACClock */
+#define   DACC_MR_STARTUP_960 (0xFu << 24) /**< \brief (DACC_MR) 960 periods of DACClock */
+#define   DACC_MR_STARTUP_1024 (0x10u << 24) /**< \brief (DACC_MR) 1024 periods of DACClock */
+#define   DACC_MR_STARTUP_1088 (0x11u << 24) /**< \brief (DACC_MR) 1088 periods of DACClock */
+#define   DACC_MR_STARTUP_1152 (0x12u << 24) /**< \brief (DACC_MR) 1152 periods of DACClock */
+#define   DACC_MR_STARTUP_1216 (0x13u << 24) /**< \brief (DACC_MR) 1216 periods of DACClock */
+#define   DACC_MR_STARTUP_1280 (0x14u << 24) /**< \brief (DACC_MR) 1280 periods of DACClock */
+#define   DACC_MR_STARTUP_1344 (0x15u << 24) /**< \brief (DACC_MR) 1344 periods of DACClock */
+#define   DACC_MR_STARTUP_1408 (0x16u << 24) /**< \brief (DACC_MR) 1408 periods of DACClock */
+#define   DACC_MR_STARTUP_1472 (0x17u << 24) /**< \brief (DACC_MR) 1472 periods of DACClock */
+#define   DACC_MR_STARTUP_1536 (0x18u << 24) /**< \brief (DACC_MR) 1536 periods of DACClock */
+#define   DACC_MR_STARTUP_1600 (0x19u << 24) /**< \brief (DACC_MR) 1600 periods of DACClock */
+#define   DACC_MR_STARTUP_1664 (0x1Au << 24) /**< \brief (DACC_MR) 1664 periods of DACClock */
+#define   DACC_MR_STARTUP_1728 (0x1Bu << 24) /**< \brief (DACC_MR) 1728 periods of DACClock */
+#define   DACC_MR_STARTUP_1792 (0x1Cu << 24) /**< \brief (DACC_MR) 1792 periods of DACClock */
+#define   DACC_MR_STARTUP_1856 (0x1Du << 24) /**< \brief (DACC_MR) 1856 periods of DACClock */
+#define   DACC_MR_STARTUP_1920 (0x1Eu << 24) /**< \brief (DACC_MR) 1920 periods of DACClock */
+#define   DACC_MR_STARTUP_1984 (0x1Fu << 24) /**< \brief (DACC_MR) 1984 periods of DACClock */
+/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */
+#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */
+#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */
+/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */
+#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */
+#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */
+/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */
+#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */
+#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */
+/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */
+#define DACC_CDR_DATA_Pos 0
+#define DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos) /**< \brief (DACC_CDR) Data to Convert */
+#define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos)))
+/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */
+#define DACC_IER_TXRDY (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */
+#define DACC_IER_EOC (0x1u << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */
+#define DACC_IER_ENDTX (0x1u << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */
+#define DACC_IER_TXBUFE (0x1u << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */
+/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */
+#define DACC_IDR_TXRDY (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */
+#define DACC_IDR_EOC (0x1u << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */
+#define DACC_IDR_ENDTX (0x1u << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */
+#define DACC_IDR_TXBUFE (0x1u << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */
+/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */
+#define DACC_IMR_TXRDY (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */
+#define DACC_IMR_EOC (0x1u << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */
+#define DACC_IMR_ENDTX (0x1u << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */
+#define DACC_IMR_TXBUFE (0x1u << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */
+/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */
+#define DACC_ISR_TXRDY (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */
+#define DACC_ISR_EOC (0x1u << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */
+#define DACC_ISR_ENDTX (0x1u << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */
+#define DACC_ISR_TXBUFE (0x1u << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */
+/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */
+#define DACC_ACR_IBCTLCH0_Pos 0
+#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */
+#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)))
+#define DACC_ACR_IBCTLCH1_Pos 2
+#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */
+#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)))
+#define DACC_ACR_IBCTLDACCORE_Pos 8
+#define DACC_ACR_IBCTLDACCORE_Msk (0x3u << DACC_ACR_IBCTLDACCORE_Pos) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */
+#define DACC_ACR_IBCTLDACCORE(value) ((DACC_ACR_IBCTLDACCORE_Msk & ((value) << DACC_ACR_IBCTLDACCORE_Pos)))
+/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */
+#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protect Enable */
+#define DACC_WPMR_WPKEY_Pos 8
+#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect KEY */
+#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))
+/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */
+#define DACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (DACC_WPSR) Write protection error */
+#define DACC_WPSR_WPROTADDR_Pos 8
+#define DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos) /**< \brief (DACC_WPSR) Write protection error address */
+/* -------- DACC_RPR : (DACC Offset: 0x100) Receive Pointer Register -------- */
+#define DACC_RPR_RXPTR_Pos 0
+#define DACC_RPR_RXPTR_Msk (0xffffffffu << DACC_RPR_RXPTR_Pos) /**< \brief (DACC_RPR) Receive Pointer Register */
+#define DACC_RPR_RXPTR(value) ((DACC_RPR_RXPTR_Msk & ((value) << DACC_RPR_RXPTR_Pos)))
+/* -------- DACC_RCR : (DACC Offset: 0x104) Receive Counter Register -------- */
+#define DACC_RCR_RXCTR_Pos 0
+#define DACC_RCR_RXCTR_Msk (0xffffu << DACC_RCR_RXCTR_Pos) /**< \brief (DACC_RCR) Receive Counter Register */
+#define DACC_RCR_RXCTR(value) ((DACC_RCR_RXCTR_Msk & ((value) << DACC_RCR_RXCTR_Pos)))
+/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */
+#define DACC_TPR_TXPTR_Pos 0
+#define DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos) /**< \brief (DACC_TPR) Transmit Counter Register */
+#define DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos)))
+/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */
+#define DACC_TCR_TXCTR_Pos 0
+#define DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos) /**< \brief (DACC_TCR) Transmit Counter Register */
+#define DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos)))
+/* -------- DACC_RNPR : (DACC Offset: 0x110) Receive Next Pointer Register -------- */
+#define DACC_RNPR_RXNPTR_Pos 0
+#define DACC_RNPR_RXNPTR_Msk (0xffffffffu << DACC_RNPR_RXNPTR_Pos) /**< \brief (DACC_RNPR) Receive Next Pointer */
+#define DACC_RNPR_RXNPTR(value) ((DACC_RNPR_RXNPTR_Msk & ((value) << DACC_RNPR_RXNPTR_Pos)))
+/* -------- DACC_RNCR : (DACC Offset: 0x114) Receive Next Counter Register -------- */
+#define DACC_RNCR_RXNCTR_Pos 0
+#define DACC_RNCR_RXNCTR_Msk (0xffffu << DACC_RNCR_RXNCTR_Pos) /**< \brief (DACC_RNCR) Receive Next Counter */
+#define DACC_RNCR_RXNCTR(value) ((DACC_RNCR_RXNCTR_Msk & ((value) << DACC_RNCR_RXNCTR_Pos)))
+/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */
+#define DACC_TNPR_TXNPTR_Pos 0
+#define DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos) /**< \brief (DACC_TNPR) Transmit Next Pointer */
+#define DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos)))
+/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */
+#define DACC_TNCR_TXNCTR_Pos 0
+#define DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos) /**< \brief (DACC_TNCR) Transmit Counter Next */
+#define DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos)))
+/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */
+#define DACC_PTCR_RXTEN (0x1u << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */
+#define DACC_PTCR_RXTDIS (0x1u << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */
+#define DACC_PTCR_TXTEN (0x1u << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */
+#define DACC_PTCR_TXTDIS (0x1u << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */
+/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */
+#define DACC_PTSR_RXTEN (0x1u << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */
+#define DACC_PTSR_TXTEN (0x1u << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_DACC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_dmac.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_dmac.h
new file mode 100644
index 000000000..87a8f7672
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_dmac.h
@@ -0,0 +1,367 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_DMAC_COMPONENT_
+#define _SAM3XA_DMAC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR DMA Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_DMAC DMA Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief DmacCh_num hardware registers */
+typedef struct {
+  RwReg       DMAC_SADDR;     /**< \brief (DmacCh_num Offset: 0x0) DMAC Channel Source Address Register */
+  RwReg       DMAC_DADDR;     /**< \brief (DmacCh_num Offset: 0x4) DMAC Channel Destination Address Register */
+  RwReg       DMAC_DSCR;      /**< \brief (DmacCh_num Offset: 0x8) DMAC Channel Descriptor Address Register */
+  RwReg       DMAC_CTRLA;     /**< \brief (DmacCh_num Offset: 0xC) DMAC Channel Control A Register */
+  RwReg       DMAC_CTRLB;     /**< \brief (DmacCh_num Offset: 0x10) DMAC Channel Control B Register */
+  RwReg       DMAC_CFG;       /**< \brief (DmacCh_num Offset: 0x14) DMAC Channel Configuration Register */
+  RoReg       Reserved1[4];
+} DmacCh_num;
+/** \brief Dmac hardware registers */
+#define DMACCH_NUM_NUMBER 6
+typedef struct {
+  RwReg       DMAC_GCFG;      /**< \brief (Dmac Offset: 0x000) DMAC Global Configuration Register */
+  RwReg       DMAC_EN;        /**< \brief (Dmac Offset: 0x004) DMAC Enable Register */
+  RwReg       DMAC_SREQ;      /**< \brief (Dmac Offset: 0x008) DMAC Software Single Request Register */
+  RwReg       DMAC_CREQ;      /**< \brief (Dmac Offset: 0x00C) DMAC Software Chunk Transfer Request Register */
+  RwReg       DMAC_LAST;      /**< \brief (Dmac Offset: 0x010) DMAC Software Last Transfer Flag Register */
+  RoReg       Reserved1[1];
+  WoReg       DMAC_EBCIER;    /**< \brief (Dmac Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */
+  WoReg       DMAC_EBCIDR;    /**< \brief (Dmac Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */
+  RoReg       DMAC_EBCIMR;    /**< \brief (Dmac Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */
+  RoReg       DMAC_EBCISR;    /**< \brief (Dmac Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */
+  WoReg       DMAC_CHER;      /**< \brief (Dmac Offset: 0x028) DMAC Channel Handler Enable Register */
+  WoReg       DMAC_CHDR;      /**< \brief (Dmac Offset: 0x02C) DMAC Channel Handler Disable Register */
+  RoReg       DMAC_CHSR;      /**< \brief (Dmac Offset: 0x030) DMAC Channel Handler Status Register */
+  RoReg       Reserved2[2];
+  DmacCh_num  DMAC_CH_NUM[DMACCH_NUM_NUMBER]; /**< \brief (Dmac Offset: 0x3C) ch_num = 0 .. 5 */
+  RoReg       Reserved3[46];
+  RwReg       DMAC_WPMR;      /**< \brief (Dmac Offset: 0x1E4) DMAC Write Protect Mode Register */
+  RoReg       DMAC_WPSR;      /**< \brief (Dmac Offset: 0x1E8) DMAC Write Protect Status Register */
+} Dmac;
+#endif /* __ASSEMBLY__ */
+/* -------- DMAC_GCFG : (DMAC Offset: 0x000) DMAC Global Configuration Register -------- */
+#define DMAC_GCFG_ARB_CFG (0x1u << 4) /**< \brief (DMAC_GCFG) Arbiter Configuration */
+#define   DMAC_GCFG_ARB_CFG_FIXED (0x0u << 4) /**< \brief (DMAC_GCFG) Fixed priority arbiter. */
+#define   DMAC_GCFG_ARB_CFG_ROUND_ROBIN (0x1u << 4) /**< \brief (DMAC_GCFG) Modified round robin arbiter. */
+/* -------- DMAC_EN : (DMAC Offset: 0x004) DMAC Enable Register -------- */
+#define DMAC_EN_ENABLE (0x1u << 0) /**< \brief (DMAC_EN)  */
+/* -------- DMAC_SREQ : (DMAC Offset: 0x008) DMAC Software Single Request Register -------- */
+#define DMAC_SREQ_SSREQ0 (0x1u << 0) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ0 (0x1u << 1) /**< \brief (DMAC_SREQ) Destination Request */
+#define DMAC_SREQ_SSREQ1 (0x1u << 2) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ1 (0x1u << 3) /**< \brief (DMAC_SREQ) Destination Request */
+#define DMAC_SREQ_SSREQ2 (0x1u << 4) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ2 (0x1u << 5) /**< \brief (DMAC_SREQ) Destination Request */
+#define DMAC_SREQ_SSREQ3 (0x1u << 6) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ3 (0x1u << 7) /**< \brief (DMAC_SREQ) Destination Request */
+#define DMAC_SREQ_SSREQ4 (0x1u << 8) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ4 (0x1u << 9) /**< \brief (DMAC_SREQ) Destination Request */
+#define DMAC_SREQ_SSREQ5 (0x1u << 10) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ5 (0x1u << 11) /**< \brief (DMAC_SREQ) Destination Request */
+/* -------- DMAC_CREQ : (DMAC Offset: 0x00C) DMAC Software Chunk Transfer Request Register -------- */
+#define DMAC_CREQ_SCREQ0 (0x1u << 0) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ0 (0x1u << 1) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+#define DMAC_CREQ_SCREQ1 (0x1u << 2) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ1 (0x1u << 3) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+#define DMAC_CREQ_SCREQ2 (0x1u << 4) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ2 (0x1u << 5) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+#define DMAC_CREQ_SCREQ3 (0x1u << 6) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ3 (0x1u << 7) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+#define DMAC_CREQ_SCREQ4 (0x1u << 8) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ4 (0x1u << 9) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+#define DMAC_CREQ_SCREQ5 (0x1u << 10) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ5 (0x1u << 11) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+/* -------- DMAC_LAST : (DMAC Offset: 0x010) DMAC Software Last Transfer Flag Register -------- */
+#define DMAC_LAST_SLAST0 (0x1u << 0) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST0 (0x1u << 1) /**< \brief (DMAC_LAST) Destination Last */
+#define DMAC_LAST_SLAST1 (0x1u << 2) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST1 (0x1u << 3) /**< \brief (DMAC_LAST) Destination Last */
+#define DMAC_LAST_SLAST2 (0x1u << 4) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST2 (0x1u << 5) /**< \brief (DMAC_LAST) Destination Last */
+#define DMAC_LAST_SLAST3 (0x1u << 6) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST3 (0x1u << 7) /**< \brief (DMAC_LAST) Destination Last */
+#define DMAC_LAST_SLAST4 (0x1u << 8) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST4 (0x1u << 9) /**< \brief (DMAC_LAST) Destination Last */
+#define DMAC_LAST_SLAST5 (0x1u << 10) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST5 (0x1u << 11) /**< \brief (DMAC_LAST) Destination Last */
+/* -------- DMAC_EBCIER : (DMAC Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. -------- */
+#define DMAC_EBCIER_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIER) Access Error [5:0] */
+#define DMAC_EBCIER_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIER) Access Error [5:0] */
+#define DMAC_EBCIER_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIER) Access Error [5:0] */
+#define DMAC_EBCIER_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIER) Access Error [5:0] */
+#define DMAC_EBCIER_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCIER) Access Error [5:0] */
+#define DMAC_EBCIER_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCIER) Access Error [5:0] */
+/* -------- DMAC_EBCIDR : (DMAC Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. -------- */
+#define DMAC_EBCIDR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */
+#define DMAC_EBCIDR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */
+#define DMAC_EBCIDR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */
+#define DMAC_EBCIDR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */
+#define DMAC_EBCIDR_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */
+#define DMAC_EBCIDR_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */
+/* -------- DMAC_EBCIMR : (DMAC Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. -------- */
+#define DMAC_EBCIMR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */
+#define DMAC_EBCIMR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */
+#define DMAC_EBCIMR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */
+#define DMAC_EBCIMR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */
+#define DMAC_EBCIMR_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */
+#define DMAC_EBCIMR_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */
+/* -------- DMAC_EBCISR : (DMAC Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. -------- */
+#define DMAC_EBCISR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCISR) Access Error [5:0] */
+#define DMAC_EBCISR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCISR) Access Error [5:0] */
+#define DMAC_EBCISR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCISR) Access Error [5:0] */
+#define DMAC_EBCISR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCISR) Access Error [5:0] */
+#define DMAC_EBCISR_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCISR) Access Error [5:0] */
+#define DMAC_EBCISR_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCISR) Access Error [5:0] */
+/* -------- DMAC_CHER : (DMAC Offset: 0x028) DMAC Channel Handler Enable Register -------- */
+#define DMAC_CHER_ENA0 (0x1u << 0) /**< \brief (DMAC_CHER) Enable [5:0] */
+#define DMAC_CHER_ENA1 (0x1u << 1) /**< \brief (DMAC_CHER) Enable [5:0] */
+#define DMAC_CHER_ENA2 (0x1u << 2) /**< \brief (DMAC_CHER) Enable [5:0] */
+#define DMAC_CHER_ENA3 (0x1u << 3) /**< \brief (DMAC_CHER) Enable [5:0] */
+#define DMAC_CHER_ENA4 (0x1u << 4) /**< \brief (DMAC_CHER) Enable [5:0] */
+#define DMAC_CHER_ENA5 (0x1u << 5) /**< \brief (DMAC_CHER) Enable [5:0] */
+#define DMAC_CHER_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHER) Suspend [5:0] */
+#define DMAC_CHER_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHER) Suspend [5:0] */
+#define DMAC_CHER_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHER) Suspend [5:0] */
+#define DMAC_CHER_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHER) Suspend [5:0] */
+#define DMAC_CHER_SUSP4 (0x1u << 12) /**< \brief (DMAC_CHER) Suspend [5:0] */
+#define DMAC_CHER_SUSP5 (0x1u << 13) /**< \brief (DMAC_CHER) Suspend [5:0] */
+#define DMAC_CHER_KEEP0 (0x1u << 24) /**< \brief (DMAC_CHER) Keep on [5:0] */
+#define DMAC_CHER_KEEP1 (0x1u << 25) /**< \brief (DMAC_CHER) Keep on [5:0] */
+#define DMAC_CHER_KEEP2 (0x1u << 26) /**< \brief (DMAC_CHER) Keep on [5:0] */
+#define DMAC_CHER_KEEP3 (0x1u << 27) /**< \brief (DMAC_CHER) Keep on [5:0] */
+#define DMAC_CHER_KEEP4 (0x1u << 28) /**< \brief (DMAC_CHER) Keep on [5:0] */
+#define DMAC_CHER_KEEP5 (0x1u << 29) /**< \brief (DMAC_CHER) Keep on [5:0] */
+/* -------- DMAC_CHDR : (DMAC Offset: 0x02C) DMAC Channel Handler Disable Register -------- */
+#define DMAC_CHDR_DIS0 (0x1u << 0) /**< \brief (DMAC_CHDR) Disable [5:0] */
+#define DMAC_CHDR_DIS1 (0x1u << 1) /**< \brief (DMAC_CHDR) Disable [5:0] */
+#define DMAC_CHDR_DIS2 (0x1u << 2) /**< \brief (DMAC_CHDR) Disable [5:0] */
+#define DMAC_CHDR_DIS3 (0x1u << 3) /**< \brief (DMAC_CHDR) Disable [5:0] */
+#define DMAC_CHDR_DIS4 (0x1u << 4) /**< \brief (DMAC_CHDR) Disable [5:0] */
+#define DMAC_CHDR_DIS5 (0x1u << 5) /**< \brief (DMAC_CHDR) Disable [5:0] */
+#define DMAC_CHDR_RES0 (0x1u << 8) /**< \brief (DMAC_CHDR) Resume [5:0] */
+#define DMAC_CHDR_RES1 (0x1u << 9) /**< \brief (DMAC_CHDR) Resume [5:0] */
+#define DMAC_CHDR_RES2 (0x1u << 10) /**< \brief (DMAC_CHDR) Resume [5:0] */
+#define DMAC_CHDR_RES3 (0x1u << 11) /**< \brief (DMAC_CHDR) Resume [5:0] */
+#define DMAC_CHDR_RES4 (0x1u << 12) /**< \brief (DMAC_CHDR) Resume [5:0] */
+#define DMAC_CHDR_RES5 (0x1u << 13) /**< \brief (DMAC_CHDR) Resume [5:0] */
+/* -------- DMAC_CHSR : (DMAC Offset: 0x030) DMAC Channel Handler Status Register -------- */
+#define DMAC_CHSR_ENA0 (0x1u << 0) /**< \brief (DMAC_CHSR) Enable [5:0] */
+#define DMAC_CHSR_ENA1 (0x1u << 1) /**< \brief (DMAC_CHSR) Enable [5:0] */
+#define DMAC_CHSR_ENA2 (0x1u << 2) /**< \brief (DMAC_CHSR) Enable [5:0] */
+#define DMAC_CHSR_ENA3 (0x1u << 3) /**< \brief (DMAC_CHSR) Enable [5:0] */
+#define DMAC_CHSR_ENA4 (0x1u << 4) /**< \brief (DMAC_CHSR) Enable [5:0] */
+#define DMAC_CHSR_ENA5 (0x1u << 5) /**< \brief (DMAC_CHSR) Enable [5:0] */
+#define DMAC_CHSR_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHSR) Suspend [5:0] */
+#define DMAC_CHSR_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHSR) Suspend [5:0] */
+#define DMAC_CHSR_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHSR) Suspend [5:0] */
+#define DMAC_CHSR_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHSR) Suspend [5:0] */
+#define DMAC_CHSR_SUSP4 (0x1u << 12) /**< \brief (DMAC_CHSR) Suspend [5:0] */
+#define DMAC_CHSR_SUSP5 (0x1u << 13) /**< \brief (DMAC_CHSR) Suspend [5:0] */
+#define DMAC_CHSR_EMPT0 (0x1u << 16) /**< \brief (DMAC_CHSR) Empty [5:0] */
+#define DMAC_CHSR_EMPT1 (0x1u << 17) /**< \brief (DMAC_CHSR) Empty [5:0] */
+#define DMAC_CHSR_EMPT2 (0x1u << 18) /**< \brief (DMAC_CHSR) Empty [5:0] */
+#define DMAC_CHSR_EMPT3 (0x1u << 19) /**< \brief (DMAC_CHSR) Empty [5:0] */
+#define DMAC_CHSR_EMPT4 (0x1u << 20) /**< \brief (DMAC_CHSR) Empty [5:0] */
+#define DMAC_CHSR_EMPT5 (0x1u << 21) /**< \brief (DMAC_CHSR) Empty [5:0] */
+#define DMAC_CHSR_STAL0 (0x1u << 24) /**< \brief (DMAC_CHSR) Stalled [5:0] */
+#define DMAC_CHSR_STAL1 (0x1u << 25) /**< \brief (DMAC_CHSR) Stalled [5:0] */
+#define DMAC_CHSR_STAL2 (0x1u << 26) /**< \brief (DMAC_CHSR) Stalled [5:0] */
+#define DMAC_CHSR_STAL3 (0x1u << 27) /**< \brief (DMAC_CHSR) Stalled [5:0] */
+#define DMAC_CHSR_STAL4 (0x1u << 28) /**< \brief (DMAC_CHSR) Stalled [5:0] */
+#define DMAC_CHSR_STAL5 (0x1u << 29) /**< \brief (DMAC_CHSR) Stalled [5:0] */
+/* -------- DMAC_SADDR : (DMAC Offset: N/A) DMAC Channel Source Address Register -------- */
+#define DMAC_SADDR_SADDR_Pos 0
+#define DMAC_SADDR_SADDR_Msk (0xffffffffu << DMAC_SADDR_SADDR_Pos) /**< \brief (DMAC_SADDR) Channel x Source Address */
+#define DMAC_SADDR_SADDR(value) ((DMAC_SADDR_SADDR_Msk & ((value) << DMAC_SADDR_SADDR_Pos)))
+/* -------- DMAC_DADDR : (DMAC Offset: N/A) DMAC Channel Destination Address Register -------- */
+#define DMAC_DADDR_DADDR_Pos 0
+#define DMAC_DADDR_DADDR_Msk (0xffffffffu << DMAC_DADDR_DADDR_Pos) /**< \brief (DMAC_DADDR) Channel x Destination Address */
+#define DMAC_DADDR_DADDR(value) ((DMAC_DADDR_DADDR_Msk & ((value) << DMAC_DADDR_DADDR_Pos)))
+/* -------- DMAC_DSCR : (DMAC Offset: N/A) DMAC Channel Descriptor Address Register -------- */
+#define DMAC_DSCR_DSCR_Pos 2
+#define DMAC_DSCR_DSCR_Msk (0x3fffffffu << DMAC_DSCR_DSCR_Pos) /**< \brief (DMAC_DSCR) Buffer Transfer Descriptor Address */
+#define DMAC_DSCR_DSCR(value) ((DMAC_DSCR_DSCR_Msk & ((value) << DMAC_DSCR_DSCR_Pos)))
+/* -------- DMAC_CTRLA : (DMAC Offset: N/A) DMAC Channel Control A Register -------- */
+#define DMAC_CTRLA_BTSIZE_Pos 0
+#define DMAC_CTRLA_BTSIZE_Msk (0xffffu << DMAC_CTRLA_BTSIZE_Pos) /**< \brief (DMAC_CTRLA) Buffer Transfer Size */
+#define DMAC_CTRLA_BTSIZE(value) ((DMAC_CTRLA_BTSIZE_Msk & ((value) << DMAC_CTRLA_BTSIZE_Pos)))
+#define DMAC_CTRLA_SCSIZE_Pos 16
+#define DMAC_CTRLA_SCSIZE_Msk (0x7u << DMAC_CTRLA_SCSIZE_Pos) /**< \brief (DMAC_CTRLA) Source Chunk Transfer Size. */
+#define   DMAC_CTRLA_SCSIZE_CHK_1 (0x0u << 16) /**< \brief (DMAC_CTRLA) 1 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_4 (0x1u << 16) /**< \brief (DMAC_CTRLA) 4 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_8 (0x2u << 16) /**< \brief (DMAC_CTRLA) 8 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_16 (0x3u << 16) /**< \brief (DMAC_CTRLA) 16 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_32 (0x4u << 16) /**< \brief (DMAC_CTRLA) 32 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_64 (0x5u << 16) /**< \brief (DMAC_CTRLA) 64 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_128 (0x6u << 16) /**< \brief (DMAC_CTRLA) 128 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_256 (0x7u << 16) /**< \brief (DMAC_CTRLA) 256 data transferred */
+#define DMAC_CTRLA_DCSIZE_Pos 20
+#define DMAC_CTRLA_DCSIZE_Msk (0x7u << DMAC_CTRLA_DCSIZE_Pos) /**< \brief (DMAC_CTRLA) Destination Chunk Transfer Size */
+#define   DMAC_CTRLA_DCSIZE_CHK_1 (0x0u << 20) /**< \brief (DMAC_CTRLA) 1 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_4 (0x1u << 20) /**< \brief (DMAC_CTRLA) 4 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_8 (0x2u << 20) /**< \brief (DMAC_CTRLA) 8 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_16 (0x3u << 20) /**< \brief (DMAC_CTRLA) 16 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_32 (0x4u << 20) /**< \brief (DMAC_CTRLA) 32 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_64 (0x5u << 20) /**< \brief (DMAC_CTRLA) 64 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_128 (0x6u << 20) /**< \brief (DMAC_CTRLA) 128 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_256 (0x7u << 20) /**< \brief (DMAC_CTRLA) 256 data transferred */
+#define DMAC_CTRLA_SRC_WIDTH_Pos 24
+#define DMAC_CTRLA_SRC_WIDTH_Msk (0x3u << DMAC_CTRLA_SRC_WIDTH_Pos) /**< \brief (DMAC_CTRLA) Transfer Width for the Source */
+#define   DMAC_CTRLA_SRC_WIDTH_BYTE (0x0u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 8-bit width */
+#define   DMAC_CTRLA_SRC_WIDTH_HALF_WORD (0x1u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 16-bit width */
+#define   DMAC_CTRLA_SRC_WIDTH_WORD (0x2u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 32-bit width */
+#define DMAC_CTRLA_DST_WIDTH_Pos 28
+#define DMAC_CTRLA_DST_WIDTH_Msk (0x3u << DMAC_CTRLA_DST_WIDTH_Pos) /**< \brief (DMAC_CTRLA) Transfer Width for the Destination */
+#define   DMAC_CTRLA_DST_WIDTH_BYTE (0x0u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 8-bit width */
+#define   DMAC_CTRLA_DST_WIDTH_HALF_WORD (0x1u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 16-bit width */
+#define   DMAC_CTRLA_DST_WIDTH_WORD (0x2u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 32-bit width */
+#define DMAC_CTRLA_DONE (0x1u << 31) /**< \brief (DMAC_CTRLA)  */
+/* -------- DMAC_CTRLB : (DMAC Offset: N/A) DMAC Channel Control B Register -------- */
+#define DMAC_CTRLB_SRC_DSCR (0x1u << 16) /**< \brief (DMAC_CTRLB) Source Address Descriptor */
+#define   DMAC_CTRLB_SRC_DSCR_FETCH_FROM_MEM (0x0u << 16) /**< \brief (DMAC_CTRLB) Source address is updated when the descriptor is fetched from the memory. */
+#define   DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE (0x1u << 16) /**< \brief (DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the source. */
+#define DMAC_CTRLB_DST_DSCR (0x1u << 20) /**< \brief (DMAC_CTRLB) Destination Address Descriptor */
+#define   DMAC_CTRLB_DST_DSCR_FETCH_FROM_MEM (0x0u << 20) /**< \brief (DMAC_CTRLB) Destination address is updated when the descriptor is fetched from the memory. */
+#define   DMAC_CTRLB_DST_DSCR_FETCH_DISABLE (0x1u << 20) /**< \brief (DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the destination. */
+#define DMAC_CTRLB_FC_Pos 21
+#define DMAC_CTRLB_FC_Msk (0x7u << DMAC_CTRLB_FC_Pos) /**< \brief (DMAC_CTRLB) Flow Control */
+#define   DMAC_CTRLB_FC_MEM2MEM_DMA_FC (0x0u << 21) /**< \brief (DMAC_CTRLB) Memory-to-Memory Transfer DMAC is flow controller */
+#define   DMAC_CTRLB_FC_MEM2PER_DMA_FC (0x1u << 21) /**< \brief (DMAC_CTRLB) Memory-to-Peripheral Transfer DMAC is flow controller */
+#define   DMAC_CTRLB_FC_PER2MEM_DMA_FC (0x2u << 21) /**< \brief (DMAC_CTRLB) Peripheral-to-Memory Transfer DMAC is flow controller */
+#define   DMAC_CTRLB_FC_PER2PER_DMA_FC (0x3u << 21) /**< \brief (DMAC_CTRLB) Peripheral-to-Peripheral Transfer DMAC is flow controller */
+#define DMAC_CTRLB_SRC_INCR_Pos 24
+#define DMAC_CTRLB_SRC_INCR_Msk (0x3u << DMAC_CTRLB_SRC_INCR_Pos) /**< \brief (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Source */
+#define   DMAC_CTRLB_SRC_INCR_INCREMENTING (0x0u << 24) /**< \brief (DMAC_CTRLB) The source address is incremented */
+#define   DMAC_CTRLB_SRC_INCR_DECREMENTING (0x1u << 24) /**< \brief (DMAC_CTRLB) The source address is decremented */
+#define   DMAC_CTRLB_SRC_INCR_FIXED (0x2u << 24) /**< \brief (DMAC_CTRLB) The source address remains unchanged */
+#define DMAC_CTRLB_DST_INCR_Pos 28
+#define DMAC_CTRLB_DST_INCR_Msk (0x3u << DMAC_CTRLB_DST_INCR_Pos) /**< \brief (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Destination */
+#define   DMAC_CTRLB_DST_INCR_INCREMENTING (0x0u << 28) /**< \brief (DMAC_CTRLB) The destination address is incremented */
+#define   DMAC_CTRLB_DST_INCR_DECREMENTING (0x1u << 28) /**< \brief (DMAC_CTRLB) The destination address is decremented */
+#define   DMAC_CTRLB_DST_INCR_FIXED (0x2u << 28) /**< \brief (DMAC_CTRLB) The destination address remains unchanged */
+#define DMAC_CTRLB_IEN (0x1u << 30) /**< \brief (DMAC_CTRLB)  */
+/* -------- DMAC_CFG : (DMAC Offset: N/A) DMAC Channel Configuration Register -------- */
+#define DMAC_CFG_SRC_PER_Pos 0
+#define DMAC_CFG_SRC_PER_Msk (0xfu << DMAC_CFG_SRC_PER_Pos) /**< \brief (DMAC_CFG) Source with Peripheral identifier */
+#define DMAC_CFG_SRC_PER(value) ((DMAC_CFG_SRC_PER_Msk & ((value) << DMAC_CFG_SRC_PER_Pos)))
+#define DMAC_CFG_DST_PER_Pos 4
+#define DMAC_CFG_DST_PER_Msk (0xfu << DMAC_CFG_DST_PER_Pos) /**< \brief (DMAC_CFG) Destination with Peripheral identifier */
+#define DMAC_CFG_DST_PER(value) ((DMAC_CFG_DST_PER_Msk & ((value) << DMAC_CFG_DST_PER_Pos)))
+#define DMAC_CFG_SRC_H2SEL (0x1u << 9) /**< \brief (DMAC_CFG) Software or Hardware Selection for the Source */
+#define   DMAC_CFG_SRC_H2SEL_SW (0x0u << 9) /**< \brief (DMAC_CFG) Software handshaking interface is used to trigger a transfer request. */
+#define   DMAC_CFG_SRC_H2SEL_HW (0x1u << 9) /**< \brief (DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request. */
+#define DMAC_CFG_DST_H2SEL (0x1u << 13) /**< \brief (DMAC_CFG) Software or Hardware Selection for the Destination */
+#define   DMAC_CFG_DST_H2SEL_SW (0x0u << 13) /**< \brief (DMAC_CFG) Software handshaking interface is used to trigger a transfer request. */
+#define   DMAC_CFG_DST_H2SEL_HW (0x1u << 13) /**< \brief (DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request. */
+#define DMAC_CFG_SOD (0x1u << 16) /**< \brief (DMAC_CFG) Stop On Done */
+#define   DMAC_CFG_SOD_DISABLE (0x0u << 16) /**< \brief (DMAC_CFG) STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. */
+#define   DMAC_CFG_SOD_ENABLE (0x1u << 16) /**< \brief (DMAC_CFG) STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. */
+#define DMAC_CFG_LOCK_IF (0x1u << 20) /**< \brief (DMAC_CFG) Interface Lock */
+#define   DMAC_CFG_LOCK_IF_DISABLE (0x0u << 20) /**< \brief (DMAC_CFG) Interface Lock capability is disabled */
+#define   DMAC_CFG_LOCK_IF_ENABLE (0x1u << 20) /**< \brief (DMAC_CFG) Interface Lock capability is enabled */
+#define DMAC_CFG_LOCK_B (0x1u << 21) /**< \brief (DMAC_CFG) Bus Lock */
+#define   DMAC_CFG_LOCK_B_DISABLE (0x0u << 21) /**< \brief (DMAC_CFG) AHB Bus Locking capability is disabled. */
+#define DMAC_CFG_LOCK_IF_L (0x1u << 22) /**< \brief (DMAC_CFG) Master Interface Arbiter Lock */
+#define   DMAC_CFG_LOCK_IF_L_CHUNK (0x0u << 22) /**< \brief (DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a chunk transfer. */
+#define   DMAC_CFG_LOCK_IF_L_BUFFER (0x1u << 22) /**< \brief (DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a buffer transfer. */
+#define DMAC_CFG_AHB_PROT_Pos 24
+#define DMAC_CFG_AHB_PROT_Msk (0x7u << DMAC_CFG_AHB_PROT_Pos) /**< \brief (DMAC_CFG) AHB Protection */
+#define DMAC_CFG_AHB_PROT(value) ((DMAC_CFG_AHB_PROT_Msk & ((value) << DMAC_CFG_AHB_PROT_Pos)))
+#define DMAC_CFG_FIFOCFG_Pos 28
+#define DMAC_CFG_FIFOCFG_Msk (0x3u << DMAC_CFG_FIFOCFG_Pos) /**< \brief (DMAC_CFG) FIFO Configuration */
+#define   DMAC_CFG_FIFOCFG_ALAP_CFG (0x0u << 28) /**< \brief (DMAC_CFG) The largest defined length AHB burst is performed on the destination AHB interface. */
+#define   DMAC_CFG_FIFOCFG_HALF_CFG (0x1u << 28) /**< \brief (DMAC_CFG) When half FIFO size is available/filled, a source/destination request is serviced. */
+#define   DMAC_CFG_FIFOCFG_ASAP_CFG (0x2u << 28) /**< \brief (DMAC_CFG) When there is enough space/data available to perform a single AHB access, then the request is serviced. */
+/* -------- DMAC_WPMR : (DMAC Offset: 0x1E4) DMAC Write Protect Mode Register -------- */
+#define DMAC_WPMR_WPEN (0x1u << 0) /**< \brief (DMAC_WPMR) Write Protect Enable */
+#define DMAC_WPMR_WPKEY_Pos 8
+#define DMAC_WPMR_WPKEY_Msk (0xffffffu << DMAC_WPMR_WPKEY_Pos) /**< \brief (DMAC_WPMR) Write Protect KEY */
+#define DMAC_WPMR_WPKEY(value) ((DMAC_WPMR_WPKEY_Msk & ((value) << DMAC_WPMR_WPKEY_Pos)))
+/* -------- DMAC_WPSR : (DMAC Offset: 0x1E8) DMAC Write Protect Status Register -------- */
+#define DMAC_WPSR_WPVS (0x1u << 0) /**< \brief (DMAC_WPSR) Write Protect Violation Status */
+#define DMAC_WPSR_WPVSRC_Pos 8
+#define DMAC_WPSR_WPVSRC_Msk (0xffffu << DMAC_WPSR_WPVSRC_Pos) /**< \brief (DMAC_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_DMAC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_efc.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_efc.h
new file mode 100644
index 000000000..ca54f4303
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_efc.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_EFC_COMPONENT_
+#define _SAM3XA_EFC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Embedded Flash Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_EFC Embedded Flash Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Efc hardware registers */
+typedef struct {
+  RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */
+  WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */
+  RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */
+  RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */
+} Efc;
+#endif /* __ASSEMBLY__ */
+/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
+#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */
+#define EEFC_FMR_FWS_Pos 8
+#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */
+#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))
+#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */
+#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */
+/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
+#define EEFC_FCR_FCMD_Pos 0
+#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */
+#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))
+#define EEFC_FCR_FARG_Pos 8
+#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */
+#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))
+#define EEFC_FCR_FKEY_Pos 24
+#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */
+#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)))
+/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
+#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */
+#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */
+#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */
+/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
+#define EEFC_FRR_FVALUE_Pos 0
+#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_EFC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_emac.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_emac.h
new file mode 100644
index 000000000..9ac1aec47
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_emac.h
@@ -0,0 +1,335 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_EMAC_COMPONENT_
+#define _SAM3XA_EMAC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_EMAC Ethernet MAC 10/100 */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief EmacSa hardware registers */
+typedef struct {
+  RwReg   EMAC_SAxB;    /**< \brief (EmacSa Offset: 0x0) Specific Address 1 Bottom Register */
+  RwReg   EMAC_SAxT;    /**< \brief (EmacSa Offset: 0x4) Specific Address 1 Top Register */
+} EmacSa;
+/** \brief Emac hardware registers */
+#define EMACSA_NUMBER 4
+typedef struct {
+  RwReg   EMAC_NCR;     /**< \brief (Emac Offset: 0x00) Network Control Register */
+  RwReg   EMAC_NCFGR;   /**< \brief (Emac Offset: 0x04) Network Configuration Register */
+  RoReg   EMAC_NSR;     /**< \brief (Emac Offset: 0x08) Network Status Register */
+  RoReg   Reserved1[2];
+  RwReg   EMAC_TSR;     /**< \brief (Emac Offset: 0x14) Transmit Status Register */
+  RwReg   EMAC_RBQP;    /**< \brief (Emac Offset: 0x18) Receive Buffer Queue Pointer Register */
+  RwReg   EMAC_TBQP;    /**< \brief (Emac Offset: 0x1C) Transmit Buffer Queue Pointer Register */
+  RwReg   EMAC_RSR;     /**< \brief (Emac Offset: 0x20) Receive Status Register */
+  RwReg   EMAC_ISR;     /**< \brief (Emac Offset: 0x24) Interrupt Status Register */
+  WoReg   EMAC_IER;     /**< \brief (Emac Offset: 0x28) Interrupt Enable Register */
+  WoReg   EMAC_IDR;     /**< \brief (Emac Offset: 0x2C) Interrupt Disable Register */
+  RoReg   EMAC_IMR;     /**< \brief (Emac Offset: 0x30) Interrupt Mask Register */
+  RwReg   EMAC_MAN;     /**< \brief (Emac Offset: 0x34) Phy Maintenance Register */
+  RwReg   EMAC_PTR;     /**< \brief (Emac Offset: 0x38) Pause Time Register */
+  RwReg   EMAC_PFR;     /**< \brief (Emac Offset: 0x3C) Pause Frames Received Register */
+  RwReg   EMAC_FTO;     /**< \brief (Emac Offset: 0x40) Frames Transmitted Ok Register */
+  RwReg   EMAC_SCF;     /**< \brief (Emac Offset: 0x44) Single Collision Frames Register */
+  RwReg   EMAC_MCF;     /**< \brief (Emac Offset: 0x48) Multiple Collision Frames Register */
+  RwReg   EMAC_FRO;     /**< \brief (Emac Offset: 0x4C) Frames Received Ok Register */
+  RwReg   EMAC_FCSE;    /**< \brief (Emac Offset: 0x50) Frame Check Sequence Errors Register */
+  RwReg   EMAC_ALE;     /**< \brief (Emac Offset: 0x54) Alignment Errors Register */
+  RwReg   EMAC_DTF;     /**< \brief (Emac Offset: 0x58) Deferred Transmission Frames Register */
+  RwReg   EMAC_LCOL;    /**< \brief (Emac Offset: 0x5C) Late Collisions Register */
+  RwReg   EMAC_ECOL;    /**< \brief (Emac Offset: 0x60) Excessive Collisions Register */
+  RwReg   EMAC_TUND;    /**< \brief (Emac Offset: 0x64) Transmit Underrun Errors Register */
+  RwReg   EMAC_CSE;     /**< \brief (Emac Offset: 0x68) Carrier Sense Errors Register */
+  RwReg   EMAC_RRE;     /**< \brief (Emac Offset: 0x6C) Receive Resource Errors Register */
+  RwReg   EMAC_ROV;     /**< \brief (Emac Offset: 0x70) Receive Overrun Errors Register */
+  RwReg   EMAC_RSE;     /**< \brief (Emac Offset: 0x74) Receive Symbol Errors Register */
+  RwReg   EMAC_ELE;     /**< \brief (Emac Offset: 0x78) Excessive Length Errors Register */
+  RwReg   EMAC_RJA;     /**< \brief (Emac Offset: 0x7C) Receive Jabbers Register */
+  RwReg   EMAC_USF;     /**< \brief (Emac Offset: 0x80) Undersize Frames Register */
+  RwReg   EMAC_STE;     /**< \brief (Emac Offset: 0x84) SQE Test Errors Register */
+  RwReg   EMAC_RLE;     /**< \brief (Emac Offset: 0x88) Received Length Field Mismatch Register */
+  RoReg   Reserved2[1];
+  RwReg   EMAC_HRB;     /**< \brief (Emac Offset: 0x90) Hash Register Bottom [31:0] Register */
+  RwReg   EMAC_HRT;     /**< \brief (Emac Offset: 0x94) Hash Register Top [63:32] Register */
+  EmacSa  EMAC_SA[EMACSA_NUMBER]; /**< \brief (Emac Offset: 0x98) sa = 1 .. 4 */
+  RwReg   EMAC_TID;     /**< \brief (Emac Offset: 0xB8) Type ID Checking Register */
+  RoReg   Reserved3[1];
+  RwReg   EMAC_USRIO;   /**< \brief (Emac Offset: 0xC0) User Input/Output Register */
+} Emac;
+#endif /* __ASSEMBLY__ */
+/* -------- EMAC_NCR : (EMAC Offset: 0x00) Network Control Register -------- */
+#define EMAC_NCR_LB (0x1u << 0) /**< \brief (EMAC_NCR) LoopBack */
+#define EMAC_NCR_LLB (0x1u << 1) /**< \brief (EMAC_NCR) Loopback local */
+#define EMAC_NCR_RE (0x1u << 2) /**< \brief (EMAC_NCR) Receive enable */
+#define EMAC_NCR_TE (0x1u << 3) /**< \brief (EMAC_NCR) Transmit enable */
+#define EMAC_NCR_MPE (0x1u << 4) /**< \brief (EMAC_NCR) Management port enable */
+#define EMAC_NCR_CLRSTAT (0x1u << 5) /**< \brief (EMAC_NCR) Clear statistics registers */
+#define EMAC_NCR_INCSTAT (0x1u << 6) /**< \brief (EMAC_NCR) Increment statistics registers */
+#define EMAC_NCR_WESTAT (0x1u << 7) /**< \brief (EMAC_NCR) Write enable for statistics registers */
+#define EMAC_NCR_BP (0x1u << 8) /**< \brief (EMAC_NCR) Back pressure */
+#define EMAC_NCR_TSTART (0x1u << 9) /**< \brief (EMAC_NCR) Start transmission */
+#define EMAC_NCR_THALT (0x1u << 10) /**< \brief (EMAC_NCR) Transmit halt */
+/* -------- EMAC_NCFGR : (EMAC Offset: 0x04) Network Configuration Register -------- */
+#define EMAC_NCFGR_SPD (0x1u << 0) /**< \brief (EMAC_NCFGR) Speed */
+#define EMAC_NCFGR_FD (0x1u << 1) /**< \brief (EMAC_NCFGR) Full Duplex */
+#define EMAC_NCFGR_JFRAME (0x1u << 3) /**< \brief (EMAC_NCFGR) Jumbo Frames */
+#define EMAC_NCFGR_CAF (0x1u << 4) /**< \brief (EMAC_NCFGR) Copy All Frames */
+#define EMAC_NCFGR_NBC (0x1u << 5) /**< \brief (EMAC_NCFGR) No Broadcast */
+#define EMAC_NCFGR_MTI (0x1u << 6) /**< \brief (EMAC_NCFGR) Multicast Hash Enable */
+#define EMAC_NCFGR_UNI (0x1u << 7) /**< \brief (EMAC_NCFGR) Unicast Hash Enable */
+#define EMAC_NCFGR_BIG (0x1u << 8) /**< \brief (EMAC_NCFGR) Receive 1536 bytes frames */
+#define EMAC_NCFGR_CLK_Pos 10
+#define EMAC_NCFGR_CLK_Msk (0x3u << EMAC_NCFGR_CLK_Pos) /**< \brief (EMAC_NCFGR) MDC clock divider */
+#define   EMAC_NCFGR_CLK_MCK_8 (0x0u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz). */
+#define   EMAC_NCFGR_CLK_MCK_16 (0x1u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz). */
+#define   EMAC_NCFGR_CLK_MCK_32 (0x2u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz). */
+#define   EMAC_NCFGR_CLK_MCK_64 (0x3u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz). */
+#define EMAC_NCFGR_RTY (0x1u << 12) /**< \brief (EMAC_NCFGR) Retry test */
+#define EMAC_NCFGR_PAE (0x1u << 13) /**< \brief (EMAC_NCFGR) Pause Enable */
+#define EMAC_NCFGR_RBOF_Pos 14
+#define EMAC_NCFGR_RBOF_Msk (0x3u << EMAC_NCFGR_RBOF_Pos) /**< \brief (EMAC_NCFGR) Receive Buffer Offset */
+#define   EMAC_NCFGR_RBOF_OFFSET_0 (0x0u << 14) /**< \brief (EMAC_NCFGR) No offset from start of receive buffer. */
+#define   EMAC_NCFGR_RBOF_OFFSET_1 (0x1u << 14) /**< \brief (EMAC_NCFGR) One-byte offset from start of receive buffer. */
+#define   EMAC_NCFGR_RBOF_OFFSET_2 (0x2u << 14) /**< \brief (EMAC_NCFGR) Two-byte offset from start of receive buffer. */
+#define   EMAC_NCFGR_RBOF_OFFSET_3 (0x3u << 14) /**< \brief (EMAC_NCFGR) Three-byte offset from start of receive buffer. */
+#define EMAC_NCFGR_RLCE (0x1u << 16) /**< \brief (EMAC_NCFGR) Receive Length field Checking Enable */
+#define EMAC_NCFGR_DRFCS (0x1u << 17) /**< \brief (EMAC_NCFGR) Discard Receive FCS */
+#define EMAC_NCFGR_EFRHD (0x1u << 18) /**< \brief (EMAC_NCFGR)  */
+#define EMAC_NCFGR_IRXFCS (0x1u << 19) /**< \brief (EMAC_NCFGR) Ignore RX FCS */
+/* -------- EMAC_NSR : (EMAC Offset: 0x08) Network Status Register -------- */
+#define EMAC_NSR_MDIO (0x1u << 1) /**< \brief (EMAC_NSR)  */
+#define EMAC_NSR_IDLE (0x1u << 2) /**< \brief (EMAC_NSR)  */
+/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */
+#define EMAC_TSR_UBR (0x1u << 0) /**< \brief (EMAC_TSR) Used Bit Read */
+#define EMAC_TSR_COL (0x1u << 1) /**< \brief (EMAC_TSR) Collision Occurred */
+#define EMAC_TSR_RLES (0x1u << 2) /**< \brief (EMAC_TSR) Retry Limit exceeded */
+#define EMAC_TSR_TGO (0x1u << 3) /**< \brief (EMAC_TSR) Transmit Go */
+#define EMAC_TSR_BEX (0x1u << 4) /**< \brief (EMAC_TSR) Buffers exhausted mid frame */
+#define EMAC_TSR_COMP (0x1u << 5) /**< \brief (EMAC_TSR) Transmit Complete */
+#define EMAC_TSR_UND (0x1u << 6) /**< \brief (EMAC_TSR) Transmit Underrun */
+/* -------- EMAC_RBQP : (EMAC Offset: 0x18) Receive Buffer Queue Pointer Register -------- */
+#define EMAC_RBQP_ADDR_Pos 2
+#define EMAC_RBQP_ADDR_Msk (0x3fffffffu << EMAC_RBQP_ADDR_Pos) /**< \brief (EMAC_RBQP) Receive buffer queue pointer address */
+#define EMAC_RBQP_ADDR(value) ((EMAC_RBQP_ADDR_Msk & ((value) << EMAC_RBQP_ADDR_Pos)))
+/* -------- EMAC_TBQP : (EMAC Offset: 0x1C) Transmit Buffer Queue Pointer Register -------- */
+#define EMAC_TBQP_ADDR_Pos 2
+#define EMAC_TBQP_ADDR_Msk (0x3fffffffu << EMAC_TBQP_ADDR_Pos) /**< \brief (EMAC_TBQP) Transmit buffer queue pointer address */
+#define EMAC_TBQP_ADDR(value) ((EMAC_TBQP_ADDR_Msk & ((value) << EMAC_TBQP_ADDR_Pos)))
+/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
+#define EMAC_RSR_BNA (0x1u << 0) /**< \brief (EMAC_RSR) Buffer Not Available */
+#define EMAC_RSR_REC (0x1u << 1) /**< \brief (EMAC_RSR) Frame Received */
+#define EMAC_RSR_OVR (0x1u << 2) /**< \brief (EMAC_RSR) Receive Overrun */
+/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
+#define EMAC_ISR_MFD (0x1u << 0) /**< \brief (EMAC_ISR) Management Frame Done */
+#define EMAC_ISR_RCOMP (0x1u << 1) /**< \brief (EMAC_ISR) Receive Complete */
+#define EMAC_ISR_RXUBR (0x1u << 2) /**< \brief (EMAC_ISR) Receive Used Bit Read */
+#define EMAC_ISR_TXUBR (0x1u << 3) /**< \brief (EMAC_ISR) Transmit Used Bit Read */
+#define EMAC_ISR_TUND (0x1u << 4) /**< \brief (EMAC_ISR) Ethernet Transmit Buffer Underrun */
+#define EMAC_ISR_RLEX (0x1u << 5) /**< \brief (EMAC_ISR) Retry Limit Exceeded */
+#define EMAC_ISR_TXERR (0x1u << 6) /**< \brief (EMAC_ISR) Transmit Error */
+#define EMAC_ISR_TCOMP (0x1u << 7) /**< \brief (EMAC_ISR) Transmit Complete */
+#define EMAC_ISR_ROVR (0x1u << 10) /**< \brief (EMAC_ISR) Receive Overrun */
+#define EMAC_ISR_HRESP (0x1u << 11) /**< \brief (EMAC_ISR) Hresp not OK */
+#define EMAC_ISR_PFRE (0x1u << 12) /**< \brief (EMAC_ISR) Pause Frame Received */
+#define EMAC_ISR_PTZ (0x1u << 13) /**< \brief (EMAC_ISR) Pause Time Zero */
+/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
+#define EMAC_IER_MFD (0x1u << 0) /**< \brief (EMAC_IER) Management Frame sent */
+#define EMAC_IER_RCOMP (0x1u << 1) /**< \brief (EMAC_IER) Receive Complete */
+#define EMAC_IER_RXUBR (0x1u << 2) /**< \brief (EMAC_IER) Receive Used Bit Read */
+#define EMAC_IER_TXUBR (0x1u << 3) /**< \brief (EMAC_IER) Transmit Used Bit Read */
+#define EMAC_IER_TUND (0x1u << 4) /**< \brief (EMAC_IER) Ethernet Transmit Buffer Underrun */
+#define EMAC_IER_RLE (0x1u << 5) /**< \brief (EMAC_IER) Retry Limit Exceeded */
+#define EMAC_IER_TXERR (0x1u << 6) /**< \brief (EMAC_IER)  */
+#define EMAC_IER_TCOMP (0x1u << 7) /**< \brief (EMAC_IER) Transmit Complete */
+#define EMAC_IER_ROVR (0x1u << 10) /**< \brief (EMAC_IER) Receive Overrun */
+#define EMAC_IER_HRESP (0x1u << 11) /**< \brief (EMAC_IER) Hresp not OK */
+#define EMAC_IER_PFR (0x1u << 12) /**< \brief (EMAC_IER) Pause Frame Received */
+#define EMAC_IER_PTZ (0x1u << 13) /**< \brief (EMAC_IER) Pause Time Zero */
+/* -------- EMAC_IDR : (EMAC Offset: 0x2C) Interrupt Disable Register -------- */
+#define EMAC_IDR_MFD (0x1u << 0) /**< \brief (EMAC_IDR) Management Frame sent */
+#define EMAC_IDR_RCOMP (0x1u << 1) /**< \brief (EMAC_IDR) Receive Complete */
+#define EMAC_IDR_RXUBR (0x1u << 2) /**< \brief (EMAC_IDR) Receive Used Bit Read */
+#define EMAC_IDR_TXUBR (0x1u << 3) /**< \brief (EMAC_IDR) Transmit Used Bit Read */
+#define EMAC_IDR_TUND (0x1u << 4) /**< \brief (EMAC_IDR) Ethernet Transmit Buffer Underrun */
+#define EMAC_IDR_RLE (0x1u << 5) /**< \brief (EMAC_IDR) Retry Limit Exceeded */
+#define EMAC_IDR_TXERR (0x1u << 6) /**< \brief (EMAC_IDR)  */
+#define EMAC_IDR_TCOMP (0x1u << 7) /**< \brief (EMAC_IDR) Transmit Complete */
+#define EMAC_IDR_ROVR (0x1u << 10) /**< \brief (EMAC_IDR) Receive Overrun */
+#define EMAC_IDR_HRESP (0x1u << 11) /**< \brief (EMAC_IDR) Hresp not OK */
+#define EMAC_IDR_PFR (0x1u << 12) /**< \brief (EMAC_IDR) Pause Frame Received */
+#define EMAC_IDR_PTZ (0x1u << 13) /**< \brief (EMAC_IDR) Pause Time Zero */
+/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
+#define EMAC_IMR_MFD (0x1u << 0) /**< \brief (EMAC_IMR) Management Frame sent */
+#define EMAC_IMR_RCOMP (0x1u << 1) /**< \brief (EMAC_IMR) Receive Complete */
+#define EMAC_IMR_RXUBR (0x1u << 2) /**< \brief (EMAC_IMR) Receive Used Bit Read */
+#define EMAC_IMR_TXUBR (0x1u << 3) /**< \brief (EMAC_IMR) Transmit Used Bit Read */
+#define EMAC_IMR_TUND (0x1u << 4) /**< \brief (EMAC_IMR) Ethernet Transmit Buffer Underrun */
+#define EMAC_IMR_RLE (0x1u << 5) /**< \brief (EMAC_IMR) Retry Limit Exceeded */
+#define EMAC_IMR_TXERR (0x1u << 6) /**< \brief (EMAC_IMR)  */
+#define EMAC_IMR_TCOMP (0x1u << 7) /**< \brief (EMAC_IMR) Transmit Complete */
+#define EMAC_IMR_ROVR (0x1u << 10) /**< \brief (EMAC_IMR) Receive Overrun */
+#define EMAC_IMR_HRESP (0x1u << 11) /**< \brief (EMAC_IMR) Hresp not OK */
+#define EMAC_IMR_PFR (0x1u << 12) /**< \brief (EMAC_IMR) Pause Frame Received */
+#define EMAC_IMR_PTZ (0x1u << 13) /**< \brief (EMAC_IMR) Pause Time Zero */
+/* -------- EMAC_MAN : (EMAC Offset: 0x34) Phy Maintenance Register -------- */
+#define EMAC_MAN_DATA_Pos 0
+#define EMAC_MAN_DATA_Msk (0xffffu << EMAC_MAN_DATA_Pos) /**< \brief (EMAC_MAN)  */
+#define EMAC_MAN_DATA(value) ((EMAC_MAN_DATA_Msk & ((value) << EMAC_MAN_DATA_Pos)))
+#define EMAC_MAN_CODE_Pos 16
+#define EMAC_MAN_CODE_Msk (0x3u << EMAC_MAN_CODE_Pos) /**< \brief (EMAC_MAN)  */
+#define EMAC_MAN_CODE(value) ((EMAC_MAN_CODE_Msk & ((value) << EMAC_MAN_CODE_Pos)))
+#define EMAC_MAN_REGA_Pos 18
+#define EMAC_MAN_REGA_Msk (0x1fu << EMAC_MAN_REGA_Pos) /**< \brief (EMAC_MAN) Register Address */
+#define EMAC_MAN_REGA(value) ((EMAC_MAN_REGA_Msk & ((value) << EMAC_MAN_REGA_Pos)))
+#define EMAC_MAN_PHYA_Pos 23
+#define EMAC_MAN_PHYA_Msk (0x1fu << EMAC_MAN_PHYA_Pos) /**< \brief (EMAC_MAN) PHY Address */
+#define EMAC_MAN_PHYA(value) ((EMAC_MAN_PHYA_Msk & ((value) << EMAC_MAN_PHYA_Pos)))
+#define EMAC_MAN_RW_Pos 28
+#define EMAC_MAN_RW_Msk (0x3u << EMAC_MAN_RW_Pos) /**< \brief (EMAC_MAN) Read-write */
+#define EMAC_MAN_RW(value) ((EMAC_MAN_RW_Msk & ((value) << EMAC_MAN_RW_Pos)))
+#define EMAC_MAN_SOF_Pos 30
+#define EMAC_MAN_SOF_Msk (0x3u << EMAC_MAN_SOF_Pos) /**< \brief (EMAC_MAN) Start of frame */
+#define EMAC_MAN_SOF(value) ((EMAC_MAN_SOF_Msk & ((value) << EMAC_MAN_SOF_Pos)))
+/* -------- EMAC_PTR : (EMAC Offset: 0x38) Pause Time Register -------- */
+#define EMAC_PTR_PTIME_Pos 0
+#define EMAC_PTR_PTIME_Msk (0xffffu << EMAC_PTR_PTIME_Pos) /**< \brief (EMAC_PTR) Pause Time */
+#define EMAC_PTR_PTIME(value) ((EMAC_PTR_PTIME_Msk & ((value) << EMAC_PTR_PTIME_Pos)))
+/* -------- EMAC_PFR : (EMAC Offset: 0x3C) Pause Frames Received Register -------- */
+#define EMAC_PFR_FROK_Pos 0
+#define EMAC_PFR_FROK_Msk (0xffffu << EMAC_PFR_FROK_Pos) /**< \brief (EMAC_PFR) Pause Frames received OK */
+#define EMAC_PFR_FROK(value) ((EMAC_PFR_FROK_Msk & ((value) << EMAC_PFR_FROK_Pos)))
+/* -------- EMAC_FTO : (EMAC Offset: 0x40) Frames Transmitted Ok Register -------- */
+#define EMAC_FTO_FTOK_Pos 0
+#define EMAC_FTO_FTOK_Msk (0xffffffu << EMAC_FTO_FTOK_Pos) /**< \brief (EMAC_FTO) Frames Transmitted OK */
+#define EMAC_FTO_FTOK(value) ((EMAC_FTO_FTOK_Msk & ((value) << EMAC_FTO_FTOK_Pos)))
+/* -------- EMAC_SCF : (EMAC Offset: 0x44) Single Collision Frames Register -------- */
+#define EMAC_SCF_SCF_Pos 0
+#define EMAC_SCF_SCF_Msk (0xffffu << EMAC_SCF_SCF_Pos) /**< \brief (EMAC_SCF) Single Collision Frames */
+#define EMAC_SCF_SCF(value) ((EMAC_SCF_SCF_Msk & ((value) << EMAC_SCF_SCF_Pos)))
+/* -------- EMAC_MCF : (EMAC Offset: 0x48) Multiple Collision Frames Register -------- */
+#define EMAC_MCF_MCF_Pos 0
+#define EMAC_MCF_MCF_Msk (0xffffu << EMAC_MCF_MCF_Pos) /**< \brief (EMAC_MCF) Multicollision Frames */
+#define EMAC_MCF_MCF(value) ((EMAC_MCF_MCF_Msk & ((value) << EMAC_MCF_MCF_Pos)))
+/* -------- EMAC_FRO : (EMAC Offset: 0x4C) Frames Received Ok Register -------- */
+#define EMAC_FRO_FROK_Pos 0
+#define EMAC_FRO_FROK_Msk (0xffffffu << EMAC_FRO_FROK_Pos) /**< \brief (EMAC_FRO) Frames Received OK */
+#define EMAC_FRO_FROK(value) ((EMAC_FRO_FROK_Msk & ((value) << EMAC_FRO_FROK_Pos)))
+/* -------- EMAC_FCSE : (EMAC Offset: 0x50) Frame Check Sequence Errors Register -------- */
+#define EMAC_FCSE_FCSE_Pos 0
+#define EMAC_FCSE_FCSE_Msk (0xffu << EMAC_FCSE_FCSE_Pos) /**< \brief (EMAC_FCSE) Frame Check Sequence Errors */
+#define EMAC_FCSE_FCSE(value) ((EMAC_FCSE_FCSE_Msk & ((value) << EMAC_FCSE_FCSE_Pos)))
+/* -------- EMAC_ALE : (EMAC Offset: 0x54) Alignment Errors Register -------- */
+#define EMAC_ALE_ALE_Pos 0
+#define EMAC_ALE_ALE_Msk (0xffu << EMAC_ALE_ALE_Pos) /**< \brief (EMAC_ALE) Alignment Errors */
+#define EMAC_ALE_ALE(value) ((EMAC_ALE_ALE_Msk & ((value) << EMAC_ALE_ALE_Pos)))
+/* -------- EMAC_DTF : (EMAC Offset: 0x58) Deferred Transmission Frames Register -------- */
+#define EMAC_DTF_DTF_Pos 0
+#define EMAC_DTF_DTF_Msk (0xffffu << EMAC_DTF_DTF_Pos) /**< \brief (EMAC_DTF) Deferred Transmission Frames */
+#define EMAC_DTF_DTF(value) ((EMAC_DTF_DTF_Msk & ((value) << EMAC_DTF_DTF_Pos)))
+/* -------- EMAC_LCOL : (EMAC Offset: 0x5C) Late Collisions Register -------- */
+#define EMAC_LCOL_LCOL_Pos 0
+#define EMAC_LCOL_LCOL_Msk (0xffu << EMAC_LCOL_LCOL_Pos) /**< \brief (EMAC_LCOL) Late Collisions */
+#define EMAC_LCOL_LCOL(value) ((EMAC_LCOL_LCOL_Msk & ((value) << EMAC_LCOL_LCOL_Pos)))
+/* -------- EMAC_ECOL : (EMAC Offset: 0x60) Excessive Collisions Register -------- */
+#define EMAC_ECOL_EXCOL_Pos 0
+#define EMAC_ECOL_EXCOL_Msk (0xffu << EMAC_ECOL_EXCOL_Pos) /**< \brief (EMAC_ECOL) Excessive Collisions */
+#define EMAC_ECOL_EXCOL(value) ((EMAC_ECOL_EXCOL_Msk & ((value) << EMAC_ECOL_EXCOL_Pos)))
+/* -------- EMAC_TUND : (EMAC Offset: 0x64) Transmit Underrun Errors Register -------- */
+#define EMAC_TUND_TUND_Pos 0
+#define EMAC_TUND_TUND_Msk (0xffu << EMAC_TUND_TUND_Pos) /**< \brief (EMAC_TUND) Transmit Underruns */
+#define EMAC_TUND_TUND(value) ((EMAC_TUND_TUND_Msk & ((value) << EMAC_TUND_TUND_Pos)))
+/* -------- EMAC_CSE : (EMAC Offset: 0x68) Carrier Sense Errors Register -------- */
+#define EMAC_CSE_CSE_Pos 0
+#define EMAC_CSE_CSE_Msk (0xffu << EMAC_CSE_CSE_Pos) /**< \brief (EMAC_CSE) Carrier Sense Errors */
+#define EMAC_CSE_CSE(value) ((EMAC_CSE_CSE_Msk & ((value) << EMAC_CSE_CSE_Pos)))
+/* -------- EMAC_RRE : (EMAC Offset: 0x6C) Receive Resource Errors Register -------- */
+#define EMAC_RRE_RRE_Pos 0
+#define EMAC_RRE_RRE_Msk (0xffffu << EMAC_RRE_RRE_Pos) /**< \brief (EMAC_RRE) Receive Resource Errors */
+#define EMAC_RRE_RRE(value) ((EMAC_RRE_RRE_Msk & ((value) << EMAC_RRE_RRE_Pos)))
+/* -------- EMAC_ROV : (EMAC Offset: 0x70) Receive Overrun Errors Register -------- */
+#define EMAC_ROV_ROVR_Pos 0
+#define EMAC_ROV_ROVR_Msk (0xffu << EMAC_ROV_ROVR_Pos) /**< \brief (EMAC_ROV) Receive Overrun */
+#define EMAC_ROV_ROVR(value) ((EMAC_ROV_ROVR_Msk & ((value) << EMAC_ROV_ROVR_Pos)))
+/* -------- EMAC_RSE : (EMAC Offset: 0x74) Receive Symbol Errors Register -------- */
+#define EMAC_RSE_RSE_Pos 0
+#define EMAC_RSE_RSE_Msk (0xffu << EMAC_RSE_RSE_Pos) /**< \brief (EMAC_RSE) Receive Symbol Errors */
+#define EMAC_RSE_RSE(value) ((EMAC_RSE_RSE_Msk & ((value) << EMAC_RSE_RSE_Pos)))
+/* -------- EMAC_ELE : (EMAC Offset: 0x78) Excessive Length Errors Register -------- */
+#define EMAC_ELE_EXL_Pos 0
+#define EMAC_ELE_EXL_Msk (0xffu << EMAC_ELE_EXL_Pos) /**< \brief (EMAC_ELE) Excessive Length Errors */
+#define EMAC_ELE_EXL(value) ((EMAC_ELE_EXL_Msk & ((value) << EMAC_ELE_EXL_Pos)))
+/* -------- EMAC_RJA : (EMAC Offset: 0x7C) Receive Jabbers Register -------- */
+#define EMAC_RJA_RJB_Pos 0
+#define EMAC_RJA_RJB_Msk (0xffu << EMAC_RJA_RJB_Pos) /**< \brief (EMAC_RJA) Receive Jabbers */
+#define EMAC_RJA_RJB(value) ((EMAC_RJA_RJB_Msk & ((value) << EMAC_RJA_RJB_Pos)))
+/* -------- EMAC_USF : (EMAC Offset: 0x80) Undersize Frames Register -------- */
+#define EMAC_USF_USF_Pos 0
+#define EMAC_USF_USF_Msk (0xffu << EMAC_USF_USF_Pos) /**< \brief (EMAC_USF) Undersize frames */
+#define EMAC_USF_USF(value) ((EMAC_USF_USF_Msk & ((value) << EMAC_USF_USF_Pos)))
+/* -------- EMAC_STE : (EMAC Offset: 0x84) SQE Test Errors Register -------- */
+#define EMAC_STE_SQER_Pos 0
+#define EMAC_STE_SQER_Msk (0xffu << EMAC_STE_SQER_Pos) /**< \brief (EMAC_STE) SQE test errors */
+#define EMAC_STE_SQER(value) ((EMAC_STE_SQER_Msk & ((value) << EMAC_STE_SQER_Pos)))
+/* -------- EMAC_RLE : (EMAC Offset: 0x88) Received Length Field Mismatch Register -------- */
+#define EMAC_RLE_RLFM_Pos 0
+#define EMAC_RLE_RLFM_Msk (0xffu << EMAC_RLE_RLFM_Pos) /**< \brief (EMAC_RLE) Receive Length Field Mismatch */
+#define EMAC_RLE_RLFM(value) ((EMAC_RLE_RLFM_Msk & ((value) << EMAC_RLE_RLFM_Pos)))
+/* -------- EMAC_HRB : (EMAC Offset: 0x90) Hash Register Bottom [31:0] Register -------- */
+#define EMAC_HRB_ADDR_Pos 0
+#define EMAC_HRB_ADDR_Msk (0xffffffffu << EMAC_HRB_ADDR_Pos) /**< \brief (EMAC_HRB)  */
+#define EMAC_HRB_ADDR(value) ((EMAC_HRB_ADDR_Msk & ((value) << EMAC_HRB_ADDR_Pos)))
+/* -------- EMAC_HRT : (EMAC Offset: 0x94) Hash Register Top [63:32] Register -------- */
+#define EMAC_HRT_ADDR_Pos 0
+#define EMAC_HRT_ADDR_Msk (0xffffffffu << EMAC_HRT_ADDR_Pos) /**< \brief (EMAC_HRT)  */
+#define EMAC_HRT_ADDR(value) ((EMAC_HRT_ADDR_Msk & ((value) << EMAC_HRT_ADDR_Pos)))
+/* -------- EMAC_SAxB : (EMAC Offset: N/A) Specific Address 1 Bottom Register -------- */
+#define EMAC_SAxB_ADDR_Pos 0
+#define EMAC_SAxB_ADDR_Msk (0xffffffffu << EMAC_SAxB_ADDR_Pos) /**< \brief (EMAC_SAxB)  */
+#define EMAC_SAxB_ADDR(value) ((EMAC_SAxB_ADDR_Msk & ((value) << EMAC_SAxB_ADDR_Pos)))
+/* -------- EMAC_SAxT : (EMAC Offset: N/A) Specific Address 1 Top Register -------- */
+#define EMAC_SAxT_ADDR_Pos 0
+#define EMAC_SAxT_ADDR_Msk (0xffffu << EMAC_SAxT_ADDR_Pos) /**< \brief (EMAC_SAxT)  */
+#define EMAC_SAxT_ADDR(value) ((EMAC_SAxT_ADDR_Msk & ((value) << EMAC_SAxT_ADDR_Pos)))
+/* -------- EMAC_TID : (EMAC Offset: 0xB8) Type ID Checking Register -------- */
+#define EMAC_TID_TID_Pos 0
+#define EMAC_TID_TID_Msk (0xffffu << EMAC_TID_TID_Pos) /**< \brief (EMAC_TID) Type ID checking */
+#define EMAC_TID_TID(value) ((EMAC_TID_TID_Msk & ((value) << EMAC_TID_TID_Pos)))
+/* -------- EMAC_USRIO : (EMAC Offset: 0xC0) User Input/Output Register -------- */
+#define EMAC_USRIO_RMII (0x1u << 0) /**< \brief (EMAC_USRIO) Reduce MII */
+#define EMAC_USRIO_CLKEN (0x1u << 1) /**< \brief (EMAC_USRIO) Clock Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_EMAC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_gpbr.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_gpbr.h
new file mode 100644
index 000000000..3c386eb69
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_gpbr.h
@@ -0,0 +1,53 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_GPBR_COMPONENT_
+#define _SAM3XA_GPBR_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR General Purpose Backup Register */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_GPBR General Purpose Backup Register */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Gpbr hardware registers */
+typedef struct {
+  RwReg SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */
+} Gpbr;
+#endif /* __ASSEMBLY__ */
+/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */
+#define SYS_GPBR_GPBR_VALUE_Pos 0
+#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */
+#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3XA_GPBR_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_hsmci.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_hsmci.h
new file mode 100644
index 000000000..ae43604d7
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_hsmci.h
@@ -0,0 +1,341 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_HSMCI_COMPONENT_
+#define _SAM3XA_HSMCI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_HSMCI High Speed MultiMedia Card Interface */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Hsmci hardware registers */
+typedef struct {
+  WoReg HSMCI_CR;        /**< \brief (Hsmci Offset: 0x00) Control Register */
+  RwReg HSMCI_MR;        /**< \brief (Hsmci Offset: 0x04) Mode Register */
+  RwReg HSMCI_DTOR;      /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */
+  RwReg HSMCI_SDCR;      /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */
+  RwReg HSMCI_ARGR;      /**< \brief (Hsmci Offset: 0x10) Argument Register */
+  WoReg HSMCI_CMDR;      /**< \brief (Hsmci Offset: 0x14) Command Register */
+  RwReg HSMCI_BLKR;      /**< \brief (Hsmci Offset: 0x18) Block Register */
+  RwReg HSMCI_CSTOR;     /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */
+  RoReg HSMCI_RSPR[4];   /**< \brief (Hsmci Offset: 0x20) Response Register */
+  RoReg HSMCI_RDR;       /**< \brief (Hsmci Offset: 0x30) Receive Data Register */
+  WoReg HSMCI_TDR;       /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */
+  RoReg Reserved1[2];
+  RoReg HSMCI_SR;        /**< \brief (Hsmci Offset: 0x40) Status Register */
+  WoReg HSMCI_IER;       /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */
+  WoReg HSMCI_IDR;       /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */
+  RoReg HSMCI_IMR;       /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */
+  RwReg HSMCI_DMA;       /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */
+  RwReg HSMCI_CFG;       /**< \brief (Hsmci Offset: 0x54) Configuration Register */
+  RoReg Reserved2[35];
+  RwReg HSMCI_WPMR;      /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */
+  RoReg HSMCI_WPSR;      /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */
+  RoReg Reserved3[69];
+  RwReg HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */
+} Hsmci;
+#endif /* __ASSEMBLY__ */
+/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */
+#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */
+#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */
+#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */
+#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */
+#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */
+/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */
+#define HSMCI_MR_CLKDIV_Pos 0
+#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */
+#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))
+#define HSMCI_MR_PWSDIV_Pos 8
+#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */
+#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))
+#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR)  */
+#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR)  */
+#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */
+#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */
+/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */
+#define HSMCI_DTOR_DTOCYC_Pos 0
+#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */
+#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))
+#define HSMCI_DTOR_DTOMUL_Pos 4
+#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */
+#define   HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */
+#define   HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */
+#define   HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */
+#define   HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */
+#define   HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */
+#define   HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */
+#define   HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */
+#define   HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */
+/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */
+#define HSMCI_SDCR_SDCSEL_Pos 0
+#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */
+#define   HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */
+#define   HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) SDCARD/SDIO Slot B selected */
+#define   HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */
+#define   HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */
+#define HSMCI_SDCR_SDCBUS_Pos 6
+#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */
+#define   HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */
+#define   HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */
+#define   HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */
+/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */
+#define HSMCI_ARGR_ARG_Pos 0
+#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */
+#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))
+/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */
+#define HSMCI_CMDR_CMDNB_Pos 0
+#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */
+#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))
+#define HSMCI_CMDR_RSPTYP_Pos 6
+#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */
+#define   HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */
+#define   HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */
+#define   HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */
+#define   HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */
+#define HSMCI_CMDR_SPCMD_Pos 8
+#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */
+#define   HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */
+#define   HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */
+#define   HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */
+#define   HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */
+#define   HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */
+#define   HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */
+#define   HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */
+#define   HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */
+#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */
+#define   HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */
+#define   HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */
+#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */
+#define   HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */
+#define   HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */
+#define HSMCI_CMDR_TRCMD_Pos 16
+#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */
+#define   HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */
+#define   HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */
+#define   HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */
+#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */
+#define   HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */
+#define   HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */
+#define HSMCI_CMDR_TRTYP_Pos 19
+#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */
+#define   HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */
+#define   HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */
+#define   HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */
+#define   HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */
+#define   HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */
+#define HSMCI_CMDR_IOSPCMD_Pos 24
+#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */
+#define   HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */
+#define   HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */
+#define   HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */
+#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */
+#define   HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */
+#define   HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */
+#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */
+/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */
+#define HSMCI_BLKR_BCNT_Pos 0
+#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */
+#define   HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. */
+#define   HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */
+#define   HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */
+#define HSMCI_BLKR_BLKLEN_Pos 16
+#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */
+#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))
+/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */
+#define HSMCI_CSTOR_CSTOCYC_Pos 0
+#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */
+#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))
+#define HSMCI_CSTOR_CSTOMUL_Pos 4
+#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */
+#define   HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */
+#define   HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */
+#define   HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */
+#define   HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */
+#define   HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */
+#define   HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */
+#define   HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */
+#define   HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */
+/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */
+#define HSMCI_RSPR_RSP_Pos 0
+#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */
+/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */
+#define HSMCI_RDR_DATA_Pos 0
+#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */
+/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */
+#define HSMCI_TDR_DATA_Pos 0
+#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */
+#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))
+/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */
+#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */
+#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */
+#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */
+#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */
+#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */
+#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */
+#define HSMCI_SR_SDIOIRQforSlotA (0x1u << 8) /**< \brief (HSMCI_SR)  */
+#define HSMCI_SR_SDIOIRQforSlotB (0x1u << 9) /**< \brief (HSMCI_SR)  */
+#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */
+#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */
+#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */
+#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */
+#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */
+#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */
+#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */
+#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */
+#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */
+#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */
+#define HSMCI_SR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error */
+#define HSMCI_SR_DMADONE (0x1u << 25) /**< \brief (HSMCI_SR) DMA Transfer done */
+#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */
+#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */
+#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */
+#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */
+#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */
+#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */
+/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */
+#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */
+#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */
+#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */
+#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */
+#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */
+#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */
+#define HSMCI_IER_SDIOIRQforSlotA (0x1u << 8) /**< \brief (HSMCI_IER)  */
+#define HSMCI_IER_SDIOIRQforSlotB (0x1u << 9) /**< \brief (HSMCI_IER)  */
+#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */
+#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */
+#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */
+#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */
+#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */
+#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */
+#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */
+#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */
+#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */
+#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */
+#define HSMCI_IER_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */
+#define HSMCI_IER_DMADONE (0x1u << 25) /**< \brief (HSMCI_IER) DMA Transfer completed Interrupt Enable */
+#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */
+#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */
+#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */
+#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */
+#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */
+#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */
+/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */
+#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */
+#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */
+#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */
+#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */
+#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */
+#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */
+#define HSMCI_IDR_SDIOIRQforSlotA (0x1u << 8) /**< \brief (HSMCI_IDR)  */
+#define HSMCI_IDR_SDIOIRQforSlotB (0x1u << 9) /**< \brief (HSMCI_IDR)  */
+#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */
+#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */
+#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */
+#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */
+#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */
+#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */
+#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */
+#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */
+#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */
+#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */
+#define HSMCI_IDR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */
+#define HSMCI_IDR_DMADONE (0x1u << 25) /**< \brief (HSMCI_IDR) DMA Transfer completed Interrupt Disable */
+#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */
+#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */
+#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */
+#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */
+#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */
+#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */
+/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */
+#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */
+#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */
+#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */
+#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */
+#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */
+#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */
+#define HSMCI_IMR_SDIOIRQforSlotA (0x1u << 8) /**< \brief (HSMCI_IMR)  */
+#define HSMCI_IMR_SDIOIRQforSlotB (0x1u << 9) /**< \brief (HSMCI_IMR)  */
+#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */
+#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */
+#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */
+#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */
+#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */
+#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */
+#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */
+#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */
+#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */
+#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */
+#define HSMCI_IMR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */
+#define HSMCI_IMR_DMADONE (0x1u << 25) /**< \brief (HSMCI_IMR) DMA Transfer Completed Interrupt Mask */
+#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */
+#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */
+#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */
+#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */
+#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */
+#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */
+/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */
+#define HSMCI_DMA_OFFSET_Pos 0
+#define HSMCI_DMA_OFFSET_Msk (0x3u << HSMCI_DMA_OFFSET_Pos) /**< \brief (HSMCI_DMA) DMA Write Buffer Offset */
+#define HSMCI_DMA_OFFSET(value) ((HSMCI_DMA_OFFSET_Msk & ((value) << HSMCI_DMA_OFFSET_Pos)))
+#define HSMCI_DMA_CHKSIZE (0x1u << 4) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */
+#define   HSMCI_DMA_CHKSIZE_1 (0x0u << 4) /**< \brief (HSMCI_DMA) 1 data available */
+#define   HSMCI_DMA_CHKSIZE_4 (0x1u << 4) /**< \brief (HSMCI_DMA) 4 data available */
+#define HSMCI_DMA_DMAEN (0x1u << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */
+#define HSMCI_DMA_ROPT (0x1u << 12) /**< \brief (HSMCI_DMA) Read Optimization with padding */
+/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */
+#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */
+#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */
+#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */
+#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */
+/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */
+#define HSMCI_WPMR_WP_EN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */
+#define HSMCI_WPMR_WP_KEY_Pos 8
+#define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) /**< \brief (HSMCI_WPMR) Write Protection Key password */
+#define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos)))
+/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */
+#define HSMCI_WPSR_WP_VS_Pos 0
+#define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */
+#define   HSMCI_WPSR_WP_VS_NONE (0x0u << 0) /**< \brief (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) */
+#define   HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) */
+#define   HSMCI_WPSR_WP_VS_RESET (0x2u << 0) /**< \brief (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). */
+#define   HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) /**< \brief (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. */
+#define HSMCI_WPSR_WP_VSRC_Pos 8
+#define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */
+/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */
+#define HSMCI_FIFO_DATA_Pos 0
+#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */
+#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3XA_HSMCI_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_matrix.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_matrix.h
new file mode 100644
index 000000000..3ec9137ea
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_matrix.h
@@ -0,0 +1,285 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_MATRIX_COMPONENT_
+#define _SAM3XA_MATRIX_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR AHB Bus Matrix */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_MATRIX AHB Bus Matrix */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Matrix hardware registers */
+typedef struct {
+  RwReg MATRIX_MCFG[6]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */
+  RoReg Reserved1[10];
+  RwReg MATRIX_SCFG[9]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */
+  RoReg Reserved2[7];
+  RwReg MATRIX_PRAS0;   /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */
+  RoReg Reserved3[1];
+  RwReg MATRIX_PRAS1;   /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */
+  RoReg Reserved4[1];
+  RwReg MATRIX_PRAS2;   /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */
+  RoReg Reserved5[1];
+  RwReg MATRIX_PRAS3;   /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */
+  RoReg Reserved6[1];
+  RwReg MATRIX_PRAS4;   /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */
+  RoReg Reserved7[1];
+  RwReg MATRIX_PRAS5;   /**< \brief (Matrix Offset: 0x00A8) Priority Register A for Slave 5 */
+  RoReg Reserved8[1];
+  RwReg MATRIX_PRAS6;   /**< \brief (Matrix Offset: 0x00B0) Priority Register A for Slave 6 */
+  RoReg Reserved9[1];
+  RwReg MATRIX_PRAS7;   /**< \brief (Matrix Offset: 0x00B8) Priority Register A for Slave 7 */
+  RoReg Reserved10[1];
+  RwReg MATRIX_PRAS8;   /**< \brief (Matrix Offset: 0x00C0) Priority Register A for Slave 8 */
+  RoReg Reserved11[1];
+  RoReg Reserved12[14];
+  RwReg MATRIX_MRCR;    /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */
+  RoReg Reserved13[4];
+  RwReg CCFG_SYSIO;     /**< \brief (Matrix Offset: 0x0114) System I/O Configuration register */
+  RoReg Reserved14[51];
+  RwReg MATRIX_WPMR;    /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */
+  RoReg MATRIX_WPSR;    /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */
+} Matrix;
+#endif /* __ASSEMBLY__ */
+/* -------- MATRIX_MCFG[6] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */
+#define MATRIX_MCFG_ULBT_Pos 0
+#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[6]) Undefined Length Burst Type */
+#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))
+/* -------- MATRIX_SCFG[9] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
+#define MATRIX_SCFG_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[9]) Maximum Number of Allowed Cycles for a Burst */
+#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[9]) Default Master Type */
+#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
+#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master */
+#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
+#define MATRIX_SCFG_ARBT_Pos 24
+#define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[9]) Arbitration Type */
+#define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos)))
+/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */
+#define MATRIX_PRAS0_M0PR_Pos 0
+#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */
+#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))
+#define MATRIX_PRAS0_M1PR_Pos 4
+#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */
+#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))
+#define MATRIX_PRAS0_M2PR_Pos 8
+#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */
+#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))
+#define MATRIX_PRAS0_M3PR_Pos 12
+#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */
+#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))
+#define MATRIX_PRAS0_M4PR_Pos 16
+#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */
+#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos)))
+#define MATRIX_PRAS0_M5PR_Pos 20
+#define MATRIX_PRAS0_M5PR_Msk (0x3u << MATRIX_PRAS0_M5PR_Pos) /**< \brief (MATRIX_PRAS0) Master 5 Priority */
+#define MATRIX_PRAS0_M5PR(value) ((MATRIX_PRAS0_M5PR_Msk & ((value) << MATRIX_PRAS0_M5PR_Pos)))
+/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */
+#define MATRIX_PRAS1_M0PR_Pos 0
+#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */
+#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))
+#define MATRIX_PRAS1_M1PR_Pos 4
+#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */
+#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))
+#define MATRIX_PRAS1_M2PR_Pos 8
+#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */
+#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))
+#define MATRIX_PRAS1_M3PR_Pos 12
+#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */
+#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))
+#define MATRIX_PRAS1_M4PR_Pos 16
+#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */
+#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos)))
+#define MATRIX_PRAS1_M5PR_Pos 20
+#define MATRIX_PRAS1_M5PR_Msk (0x3u << MATRIX_PRAS1_M5PR_Pos) /**< \brief (MATRIX_PRAS1) Master 5 Priority */
+#define MATRIX_PRAS1_M5PR(value) ((MATRIX_PRAS1_M5PR_Msk & ((value) << MATRIX_PRAS1_M5PR_Pos)))
+/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */
+#define MATRIX_PRAS2_M0PR_Pos 0
+#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */
+#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))
+#define MATRIX_PRAS2_M1PR_Pos 4
+#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */
+#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))
+#define MATRIX_PRAS2_M2PR_Pos 8
+#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */
+#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))
+#define MATRIX_PRAS2_M3PR_Pos 12
+#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */
+#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))
+#define MATRIX_PRAS2_M4PR_Pos 16
+#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */
+#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos)))
+#define MATRIX_PRAS2_M5PR_Pos 20
+#define MATRIX_PRAS2_M5PR_Msk (0x3u << MATRIX_PRAS2_M5PR_Pos) /**< \brief (MATRIX_PRAS2) Master 5 Priority */
+#define MATRIX_PRAS2_M5PR(value) ((MATRIX_PRAS2_M5PR_Msk & ((value) << MATRIX_PRAS2_M5PR_Pos)))
+/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */
+#define MATRIX_PRAS3_M0PR_Pos 0
+#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */
+#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))
+#define MATRIX_PRAS3_M1PR_Pos 4
+#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */
+#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))
+#define MATRIX_PRAS3_M2PR_Pos 8
+#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */
+#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))
+#define MATRIX_PRAS3_M3PR_Pos 12
+#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */
+#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))
+#define MATRIX_PRAS3_M4PR_Pos 16
+#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */
+#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos)))
+#define MATRIX_PRAS3_M5PR_Pos 20
+#define MATRIX_PRAS3_M5PR_Msk (0x3u << MATRIX_PRAS3_M5PR_Pos) /**< \brief (MATRIX_PRAS3) Master 5 Priority */
+#define MATRIX_PRAS3_M5PR(value) ((MATRIX_PRAS3_M5PR_Msk & ((value) << MATRIX_PRAS3_M5PR_Pos)))
+/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */
+#define MATRIX_PRAS4_M0PR_Pos 0
+#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */
+#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos)))
+#define MATRIX_PRAS4_M1PR_Pos 4
+#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */
+#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos)))
+#define MATRIX_PRAS4_M2PR_Pos 8
+#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */
+#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos)))
+#define MATRIX_PRAS4_M3PR_Pos 12
+#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */
+#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos)))
+#define MATRIX_PRAS4_M4PR_Pos 16
+#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */
+#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos)))
+#define MATRIX_PRAS4_M5PR_Pos 20
+#define MATRIX_PRAS4_M5PR_Msk (0x3u << MATRIX_PRAS4_M5PR_Pos) /**< \brief (MATRIX_PRAS4) Master 5 Priority */
+#define MATRIX_PRAS4_M5PR(value) ((MATRIX_PRAS4_M5PR_Msk & ((value) << MATRIX_PRAS4_M5PR_Pos)))
+/* -------- MATRIX_PRAS5 : (MATRIX Offset: 0x00A8) Priority Register A for Slave 5 -------- */
+#define MATRIX_PRAS5_M0PR_Pos 0
+#define MATRIX_PRAS5_M0PR_Msk (0x3u << MATRIX_PRAS5_M0PR_Pos) /**< \brief (MATRIX_PRAS5) Master 0 Priority */
+#define MATRIX_PRAS5_M0PR(value) ((MATRIX_PRAS5_M0PR_Msk & ((value) << MATRIX_PRAS5_M0PR_Pos)))
+#define MATRIX_PRAS5_M1PR_Pos 4
+#define MATRIX_PRAS5_M1PR_Msk (0x3u << MATRIX_PRAS5_M1PR_Pos) /**< \brief (MATRIX_PRAS5) Master 1 Priority */
+#define MATRIX_PRAS5_M1PR(value) ((MATRIX_PRAS5_M1PR_Msk & ((value) << MATRIX_PRAS5_M1PR_Pos)))
+#define MATRIX_PRAS5_M2PR_Pos 8
+#define MATRIX_PRAS5_M2PR_Msk (0x3u << MATRIX_PRAS5_M2PR_Pos) /**< \brief (MATRIX_PRAS5) Master 2 Priority */
+#define MATRIX_PRAS5_M2PR(value) ((MATRIX_PRAS5_M2PR_Msk & ((value) << MATRIX_PRAS5_M2PR_Pos)))
+#define MATRIX_PRAS5_M3PR_Pos 12
+#define MATRIX_PRAS5_M3PR_Msk (0x3u << MATRIX_PRAS5_M3PR_Pos) /**< \brief (MATRIX_PRAS5) Master 3 Priority */
+#define MATRIX_PRAS5_M3PR(value) ((MATRIX_PRAS5_M3PR_Msk & ((value) << MATRIX_PRAS5_M3PR_Pos)))
+#define MATRIX_PRAS5_M4PR_Pos 16
+#define MATRIX_PRAS5_M4PR_Msk (0x3u << MATRIX_PRAS5_M4PR_Pos) /**< \brief (MATRIX_PRAS5) Master 4 Priority */
+#define MATRIX_PRAS5_M4PR(value) ((MATRIX_PRAS5_M4PR_Msk & ((value) << MATRIX_PRAS5_M4PR_Pos)))
+#define MATRIX_PRAS5_M5PR_Pos 20
+#define MATRIX_PRAS5_M5PR_Msk (0x3u << MATRIX_PRAS5_M5PR_Pos) /**< \brief (MATRIX_PRAS5) Master 5 Priority */
+#define MATRIX_PRAS5_M5PR(value) ((MATRIX_PRAS5_M5PR_Msk & ((value) << MATRIX_PRAS5_M5PR_Pos)))
+/* -------- MATRIX_PRAS6 : (MATRIX Offset: 0x00B0) Priority Register A for Slave 6 -------- */
+#define MATRIX_PRAS6_M0PR_Pos 0
+#define MATRIX_PRAS6_M0PR_Msk (0x3u << MATRIX_PRAS6_M0PR_Pos) /**< \brief (MATRIX_PRAS6) Master 0 Priority */
+#define MATRIX_PRAS6_M0PR(value) ((MATRIX_PRAS6_M0PR_Msk & ((value) << MATRIX_PRAS6_M0PR_Pos)))
+#define MATRIX_PRAS6_M1PR_Pos 4
+#define MATRIX_PRAS6_M1PR_Msk (0x3u << MATRIX_PRAS6_M1PR_Pos) /**< \brief (MATRIX_PRAS6) Master 1 Priority */
+#define MATRIX_PRAS6_M1PR(value) ((MATRIX_PRAS6_M1PR_Msk & ((value) << MATRIX_PRAS6_M1PR_Pos)))
+#define MATRIX_PRAS6_M2PR_Pos 8
+#define MATRIX_PRAS6_M2PR_Msk (0x3u << MATRIX_PRAS6_M2PR_Pos) /**< \brief (MATRIX_PRAS6) Master 2 Priority */
+#define MATRIX_PRAS6_M2PR(value) ((MATRIX_PRAS6_M2PR_Msk & ((value) << MATRIX_PRAS6_M2PR_Pos)))
+#define MATRIX_PRAS6_M3PR_Pos 12
+#define MATRIX_PRAS6_M3PR_Msk (0x3u << MATRIX_PRAS6_M3PR_Pos) /**< \brief (MATRIX_PRAS6) Master 3 Priority */
+#define MATRIX_PRAS6_M3PR(value) ((MATRIX_PRAS6_M3PR_Msk & ((value) << MATRIX_PRAS6_M3PR_Pos)))
+#define MATRIX_PRAS6_M4PR_Pos 16
+#define MATRIX_PRAS6_M4PR_Msk (0x3u << MATRIX_PRAS6_M4PR_Pos) /**< \brief (MATRIX_PRAS6) Master 4 Priority */
+#define MATRIX_PRAS6_M4PR(value) ((MATRIX_PRAS6_M4PR_Msk & ((value) << MATRIX_PRAS6_M4PR_Pos)))
+#define MATRIX_PRAS6_M5PR_Pos 20
+#define MATRIX_PRAS6_M5PR_Msk (0x3u << MATRIX_PRAS6_M5PR_Pos) /**< \brief (MATRIX_PRAS6) Master 5 Priority */
+#define MATRIX_PRAS6_M5PR(value) ((MATRIX_PRAS6_M5PR_Msk & ((value) << MATRIX_PRAS6_M5PR_Pos)))
+/* -------- MATRIX_PRAS7 : (MATRIX Offset: 0x00B8) Priority Register A for Slave 7 -------- */
+#define MATRIX_PRAS7_M0PR_Pos 0
+#define MATRIX_PRAS7_M0PR_Msk (0x3u << MATRIX_PRAS7_M0PR_Pos) /**< \brief (MATRIX_PRAS7) Master 0 Priority */
+#define MATRIX_PRAS7_M0PR(value) ((MATRIX_PRAS7_M0PR_Msk & ((value) << MATRIX_PRAS7_M0PR_Pos)))
+#define MATRIX_PRAS7_M1PR_Pos 4
+#define MATRIX_PRAS7_M1PR_Msk (0x3u << MATRIX_PRAS7_M1PR_Pos) /**< \brief (MATRIX_PRAS7) Master 1 Priority */
+#define MATRIX_PRAS7_M1PR(value) ((MATRIX_PRAS7_M1PR_Msk & ((value) << MATRIX_PRAS7_M1PR_Pos)))
+#define MATRIX_PRAS7_M2PR_Pos 8
+#define MATRIX_PRAS7_M2PR_Msk (0x3u << MATRIX_PRAS7_M2PR_Pos) /**< \brief (MATRIX_PRAS7) Master 2 Priority */
+#define MATRIX_PRAS7_M2PR(value) ((MATRIX_PRAS7_M2PR_Msk & ((value) << MATRIX_PRAS7_M2PR_Pos)))
+#define MATRIX_PRAS7_M3PR_Pos 12
+#define MATRIX_PRAS7_M3PR_Msk (0x3u << MATRIX_PRAS7_M3PR_Pos) /**< \brief (MATRIX_PRAS7) Master 3 Priority */
+#define MATRIX_PRAS7_M3PR(value) ((MATRIX_PRAS7_M3PR_Msk & ((value) << MATRIX_PRAS7_M3PR_Pos)))
+#define MATRIX_PRAS7_M4PR_Pos 16
+#define MATRIX_PRAS7_M4PR_Msk (0x3u << MATRIX_PRAS7_M4PR_Pos) /**< \brief (MATRIX_PRAS7) Master 4 Priority */
+#define MATRIX_PRAS7_M4PR(value) ((MATRIX_PRAS7_M4PR_Msk & ((value) << MATRIX_PRAS7_M4PR_Pos)))
+#define MATRIX_PRAS7_M5PR_Pos 20
+#define MATRIX_PRAS7_M5PR_Msk (0x3u << MATRIX_PRAS7_M5PR_Pos) /**< \brief (MATRIX_PRAS7) Master 5 Priority */
+#define MATRIX_PRAS7_M5PR(value) ((MATRIX_PRAS7_M5PR_Msk & ((value) << MATRIX_PRAS7_M5PR_Pos)))
+/* -------- MATRIX_PRAS8 : (MATRIX Offset: 0x00C0) Priority Register A for Slave 8 -------- */
+#define MATRIX_PRAS8_M0PR_Pos 0
+#define MATRIX_PRAS8_M0PR_Msk (0x3u << MATRIX_PRAS8_M0PR_Pos) /**< \brief (MATRIX_PRAS8) Master 0 Priority */
+#define MATRIX_PRAS8_M0PR(value) ((MATRIX_PRAS8_M0PR_Msk & ((value) << MATRIX_PRAS8_M0PR_Pos)))
+#define MATRIX_PRAS8_M1PR_Pos 4
+#define MATRIX_PRAS8_M1PR_Msk (0x3u << MATRIX_PRAS8_M1PR_Pos) /**< \brief (MATRIX_PRAS8) Master 1 Priority */
+#define MATRIX_PRAS8_M1PR(value) ((MATRIX_PRAS8_M1PR_Msk & ((value) << MATRIX_PRAS8_M1PR_Pos)))
+#define MATRIX_PRAS8_M2PR_Pos 8
+#define MATRIX_PRAS8_M2PR_Msk (0x3u << MATRIX_PRAS8_M2PR_Pos) /**< \brief (MATRIX_PRAS8) Master 2 Priority */
+#define MATRIX_PRAS8_M2PR(value) ((MATRIX_PRAS8_M2PR_Msk & ((value) << MATRIX_PRAS8_M2PR_Pos)))
+#define MATRIX_PRAS8_M3PR_Pos 12
+#define MATRIX_PRAS8_M3PR_Msk (0x3u << MATRIX_PRAS8_M3PR_Pos) /**< \brief (MATRIX_PRAS8) Master 3 Priority */
+#define MATRIX_PRAS8_M3PR(value) ((MATRIX_PRAS8_M3PR_Msk & ((value) << MATRIX_PRAS8_M3PR_Pos)))
+#define MATRIX_PRAS8_M4PR_Pos 16
+#define MATRIX_PRAS8_M4PR_Msk (0x3u << MATRIX_PRAS8_M4PR_Pos) /**< \brief (MATRIX_PRAS8) Master 4 Priority */
+#define MATRIX_PRAS8_M4PR(value) ((MATRIX_PRAS8_M4PR_Msk & ((value) << MATRIX_PRAS8_M4PR_Pos)))
+#define MATRIX_PRAS8_M5PR_Pos 20
+#define MATRIX_PRAS8_M5PR_Msk (0x3u << MATRIX_PRAS8_M5PR_Pos) /**< \brief (MATRIX_PRAS8) Master 5 Priority */
+#define MATRIX_PRAS8_M5PR(value) ((MATRIX_PRAS8_M5PR_Msk & ((value) << MATRIX_PRAS8_M5PR_Pos)))
+/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */
+#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 0 */
+#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 1 */
+#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 2 */
+#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 3 */
+#define MATRIX_MRCR_RCB4_Pos 4
+#define MATRIX_MRCR_RCB4_Msk (0x3u << MATRIX_MRCR_RCB4_Pos) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 4 */
+#define MATRIX_MRCR_RCB4(value) ((MATRIX_MRCR_RCB4_Msk & ((value) << MATRIX_MRCR_RCB4_Pos)))
+#define MATRIX_MRCR_RCB5 (0x1u << 6) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 5 */
+/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration register -------- */
+#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PC0 or ERASE Assignment */
+/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */
+#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */
+#define MATRIX_WPMR_WPKEY_Pos 8
+#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */
+#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
+/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */
+#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */
+#define MATRIX_WPSR_WPVSRC_Pos 8
+#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_MATRIX_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_pdc.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_pdc.h
new file mode 100644
index 000000000..fffd19b5c
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_pdc.h
@@ -0,0 +1,98 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PDC_COMPONENT_
+#define _SAM3XA_PDC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_PDC Peripheral DMA Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Pdc hardware registers */
+typedef struct {
+  RwReg PERIPH_RPR;  /**< \brief (Pdc Offset: 0x0) Receive Pointer Register */
+  RwReg PERIPH_RCR;  /**< \brief (Pdc Offset: 0x4) Receive Counter Register */
+  RwReg PERIPH_TPR;  /**< \brief (Pdc Offset: 0x8) Transmit Pointer Register */
+  RwReg PERIPH_TCR;  /**< \brief (Pdc Offset: 0xC) Transmit Counter Register */
+  RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */
+  RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */
+  RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */
+  RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */
+  WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */
+  RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */
+} Pdc;
+#endif /* __ASSEMBLY__ */
+/* -------- PERIPH_RPR : (PDC Offset: 0x0) Receive Pointer Register -------- */
+#define PERIPH_RPR_RXPTR_Pos 0
+#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */
+#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos)))
+/* -------- PERIPH_RCR : (PDC Offset: 0x4) Receive Counter Register -------- */
+#define PERIPH_RCR_RXCTR_Pos 0
+#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */
+#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos)))
+/* -------- PERIPH_TPR : (PDC Offset: 0x8) Transmit Pointer Register -------- */
+#define PERIPH_TPR_TXPTR_Pos 0
+#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */
+#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos)))
+/* -------- PERIPH_TCR : (PDC Offset: 0xC) Transmit Counter Register -------- */
+#define PERIPH_TCR_TXCTR_Pos 0
+#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */
+#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos)))
+/* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */
+#define PERIPH_RNPR_RXNPTR_Pos 0
+#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */
+#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos)))
+/* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */
+#define PERIPH_RNCR_RXNCTR_Pos 0
+#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */
+#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos)))
+/* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */
+#define PERIPH_TNPR_TXNPTR_Pos 0
+#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */
+#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos)))
+/* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */
+#define PERIPH_TNCR_TXNCTR_Pos 0
+#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */
+#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos)))
+/* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */
+#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */
+#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */
+#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */
+#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */
+/* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */
+#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */
+#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_PDC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_pio.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_pio.h
new file mode 100644
index 000000000..df598b8e1
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_pio.h
@@ -0,0 +1,1435 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PIO_COMPONENT_
+#define _SAM3XA_PIO_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_PIO Parallel Input/Output Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Pio hardware registers */
+typedef struct {
+  WoReg PIO_PER;       /**< \brief (Pio Offset: 0x0000) PIO Enable Register */
+  WoReg PIO_PDR;       /**< \brief (Pio Offset: 0x0004) PIO Disable Register */
+  RoReg PIO_PSR;       /**< \brief (Pio Offset: 0x0008) PIO Status Register */
+  RoReg Reserved1[1];
+  WoReg PIO_OER;       /**< \brief (Pio Offset: 0x0010) Output Enable Register */
+  WoReg PIO_ODR;       /**< \brief (Pio Offset: 0x0014) Output Disable Register */
+  RoReg PIO_OSR;       /**< \brief (Pio Offset: 0x0018) Output Status Register */
+  RoReg Reserved2[1];
+  WoReg PIO_IFER;      /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */
+  WoReg PIO_IFDR;      /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */
+  RoReg PIO_IFSR;      /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */
+  RoReg Reserved3[1];
+  WoReg PIO_SODR;      /**< \brief (Pio Offset: 0x0030) Set Output Data Register */
+  WoReg PIO_CODR;      /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */
+  RwReg PIO_ODSR;      /**< \brief (Pio Offset: 0x0038) Output Data Status Register */
+  RoReg PIO_PDSR;      /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */
+  WoReg PIO_IER;       /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */
+  WoReg PIO_IDR;       /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */
+  RoReg PIO_IMR;       /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */
+  RoReg PIO_ISR;       /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */
+  WoReg PIO_MDER;      /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */
+  WoReg PIO_MDDR;      /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */
+  RoReg PIO_MDSR;      /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */
+  RoReg Reserved4[1];
+  WoReg PIO_PUDR;      /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */
+  WoReg PIO_PUER;      /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */
+  RoReg PIO_PUSR;      /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */
+  RoReg Reserved5[1];
+  RwReg PIO_ABSR;      /**< \brief (Pio Offset: 0x0070) Peripheral AB Select Register */
+  RoReg Reserved6[3];
+  WoReg PIO_SCIFSR;    /**< \brief (Pio Offset: 0x0080) System Clock Glitch Input Filter Select Register */
+  WoReg PIO_DIFSR;     /**< \brief (Pio Offset: 0x0084) Debouncing Input Filter Select Register */
+  RoReg PIO_IFDGSR;    /**< \brief (Pio Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register */
+  RwReg PIO_SCDR;      /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */
+  RoReg Reserved7[4];
+  WoReg PIO_OWER;      /**< \brief (Pio Offset: 0x00A0) Output Write Enable */
+  WoReg PIO_OWDR;      /**< \brief (Pio Offset: 0x00A4) Output Write Disable */
+  RoReg PIO_OWSR;      /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */
+  RoReg Reserved8[1];
+  WoReg PIO_AIMER;     /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */
+  WoReg PIO_AIMDR;     /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */
+  RoReg PIO_AIMMR;     /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */
+  RoReg Reserved9[1];
+  WoReg PIO_ESR;       /**< \brief (Pio Offset: 0x00C0) Edge Select Register */
+  WoReg PIO_LSR;       /**< \brief (Pio Offset: 0x00C4) Level Select Register */
+  RoReg PIO_ELSR;      /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */
+  RoReg Reserved10[1];
+  WoReg PIO_FELLSR;    /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */
+  WoReg PIO_REHLSR;    /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */
+  RoReg PIO_FRLHSR;    /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */
+  RoReg Reserved11[1];
+  RoReg PIO_LOCKSR;    /**< \brief (Pio Offset: 0x00E0) Lock Status */
+  RwReg PIO_WPMR;      /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */
+  RoReg PIO_WPSR;      /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */
+} Pio;
+#endif /* __ASSEMBLY__ */
+/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */
+#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */
+/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */
+#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */
+/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */
+#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */
+/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */
+#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */
+/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */
+#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */
+/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */
+#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */
+/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */
+#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */
+/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */
+#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */
+/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */
+#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */
+/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */
+#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */
+/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */
+#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */
+/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */
+#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */
+/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */
+#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */
+/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */
+#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */
+#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */
+#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */
+#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */
+#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */
+/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */
+#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */
+#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */
+/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */
+#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */
+/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */
+#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull Up Enable. */
+/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */
+#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull Up Status. */
+/* -------- PIO_ABSR : (PIO Offset: 0x0070) Peripheral AB Select Register -------- */
+#define PIO_ABSR_P0 (0x1u << 0) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P1 (0x1u << 1) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P2 (0x1u << 2) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P3 (0x1u << 3) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P4 (0x1u << 4) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P5 (0x1u << 5) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P6 (0x1u << 6) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P7 (0x1u << 7) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P8 (0x1u << 8) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P9 (0x1u << 9) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P10 (0x1u << 10) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P11 (0x1u << 11) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P12 (0x1u << 12) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P13 (0x1u << 13) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P14 (0x1u << 14) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P15 (0x1u << 15) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P16 (0x1u << 16) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P17 (0x1u << 17) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P18 (0x1u << 18) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P19 (0x1u << 19) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P20 (0x1u << 20) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P21 (0x1u << 21) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P22 (0x1u << 22) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P23 (0x1u << 23) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P24 (0x1u << 24) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P25 (0x1u << 25) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P26 (0x1u << 26) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P27 (0x1u << 27) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P28 (0x1u << 28) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P29 (0x1u << 29) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P30 (0x1u << 30) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P31 (0x1u << 31) /**< \brief (PIO_ABSR) Peripheral A Select. */
+/* -------- PIO_SCIFSR : (PIO Offset: 0x0080) System Clock Glitch Input Filter Select Register -------- */
+#define PIO_SCIFSR_P0 (0x1u << 0) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P1 (0x1u << 1) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P2 (0x1u << 2) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P3 (0x1u << 3) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P4 (0x1u << 4) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P5 (0x1u << 5) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P6 (0x1u << 6) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P7 (0x1u << 7) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P8 (0x1u << 8) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P9 (0x1u << 9) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P10 (0x1u << 10) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P11 (0x1u << 11) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P12 (0x1u << 12) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P13 (0x1u << 13) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P14 (0x1u << 14) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P15 (0x1u << 15) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P16 (0x1u << 16) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P17 (0x1u << 17) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P18 (0x1u << 18) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P19 (0x1u << 19) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P20 (0x1u << 20) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P21 (0x1u << 21) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P22 (0x1u << 22) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P23 (0x1u << 23) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P24 (0x1u << 24) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P25 (0x1u << 25) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P26 (0x1u << 26) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P27 (0x1u << 27) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P28 (0x1u << 28) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P29 (0x1u << 29) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P30 (0x1u << 30) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P31 (0x1u << 31) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+/* -------- PIO_DIFSR : (PIO Offset: 0x0084) Debouncing Input Filter Select Register -------- */
+#define PIO_DIFSR_P0 (0x1u << 0) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P1 (0x1u << 1) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P2 (0x1u << 2) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P3 (0x1u << 3) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P4 (0x1u << 4) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P5 (0x1u << 5) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P6 (0x1u << 6) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P7 (0x1u << 7) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P8 (0x1u << 8) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P9 (0x1u << 9) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P10 (0x1u << 10) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P11 (0x1u << 11) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P12 (0x1u << 12) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P13 (0x1u << 13) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P14 (0x1u << 14) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P15 (0x1u << 15) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P16 (0x1u << 16) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P17 (0x1u << 17) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P18 (0x1u << 18) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P19 (0x1u << 19) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P20 (0x1u << 20) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P21 (0x1u << 21) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P22 (0x1u << 22) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P23 (0x1u << 23) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P24 (0x1u << 24) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P25 (0x1u << 25) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P26 (0x1u << 26) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P27 (0x1u << 27) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P28 (0x1u << 28) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P29 (0x1u << 29) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P30 (0x1u << 30) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P31 (0x1u << 31) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+/* -------- PIO_IFDGSR : (PIO Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register -------- */
+#define PIO_IFDGSR_P0 (0x1u << 0) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P1 (0x1u << 1) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P2 (0x1u << 2) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P3 (0x1u << 3) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P4 (0x1u << 4) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P5 (0x1u << 5) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P6 (0x1u << 6) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P7 (0x1u << 7) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P8 (0x1u << 8) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P9 (0x1u << 9) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P10 (0x1u << 10) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P11 (0x1u << 11) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P12 (0x1u << 12) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P13 (0x1u << 13) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P14 (0x1u << 14) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P15 (0x1u << 15) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P16 (0x1u << 16) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P17 (0x1u << 17) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P18 (0x1u << 18) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P19 (0x1u << 19) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P20 (0x1u << 20) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P21 (0x1u << 21) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P22 (0x1u << 22) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P23 (0x1u << 23) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P24 (0x1u << 24) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P25 (0x1u << 25) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P26 (0x1u << 26) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P27 (0x1u << 27) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P28 (0x1u << 28) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P29 (0x1u << 29) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P30 (0x1u << 30) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P31 (0x1u << 31) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */
+#define PIO_SCDR_DIV_Pos 0
+#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */
+#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)))
+/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */
+#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable. */
+/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */
+#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable. */
+/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */
+#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status. */
+/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */
+#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */
+#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */
+#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */
+#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */
+#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */
+#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */
+#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */
+#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */
+#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */
+#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status. */
+/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protect Enable */
+#define PIO_WPMR_WPKEY_Pos 8
+#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protect KEY */
+#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)))
+/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */
+#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */
+#define PIO_WPSR_WPVSRC_Pos 8
+#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_PIO_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_pmc.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_pmc.h
new file mode 100644
index 000000000..c33044455
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_pmc.h
@@ -0,0 +1,417 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PMC_COMPONENT_
+#define _SAM3XA_PMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Power Management Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_PMC Power Management Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Pmc hardware registers */
+typedef struct {
+  WoReg PMC_SCER;      /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */
+  WoReg PMC_SCDR;      /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */
+  RoReg PMC_SCSR;      /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */
+  RoReg Reserved1[1];
+  WoReg PMC_PCER0;     /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */
+  WoReg PMC_PCDR0;     /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */
+  RoReg PMC_PCSR0;     /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */
+  RwReg CKGR_UCKR;     /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */
+  RwReg CKGR_MOR;      /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */
+  RoReg CKGR_MCFR;     /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */
+  RwReg CKGR_PLLAR;    /**< \brief (Pmc Offset: 0x0028) PLLA Register */
+  RoReg Reserved2[1];
+  RwReg PMC_MCKR;      /**< \brief (Pmc Offset: 0x0030) Master Clock Register */
+  RoReg Reserved3[1];
+  RwReg PMC_USB;       /**< \brief (Pmc Offset: 0x0038) USB Clock Register */
+  RoReg Reserved4[1];
+  RwReg PMC_PCK[3];    /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */
+  RoReg Reserved5[5];
+  WoReg PMC_IER;       /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */
+  WoReg PMC_IDR;       /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */
+  RoReg PMC_SR;        /**< \brief (Pmc Offset: 0x0068) Status Register */
+  RoReg PMC_IMR;       /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */
+  RwReg PMC_FSMR;      /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */
+  RwReg PMC_FSPR;      /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */
+  WoReg PMC_FOCR;      /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */
+  RoReg Reserved6[26];
+  RwReg PMC_WPMR;      /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */
+  RoReg PMC_WPSR;      /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */
+  RoReg Reserved7[5];
+  WoReg PMC_PCER1;     /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */
+  WoReg PMC_PCDR1;     /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */
+  RoReg PMC_PCSR1;     /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */
+  RwReg PMC_PCR;       /**< \brief (Pmc Offset: 0x010C) Peripheral Control Register */
+} Pmc;
+#endif /* __ASSEMBLY__ */
+/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
+#define PMC_SCER_UOTGCLK (0x1u << 5) /**< \brief (PMC_SCER) Enable USB OTG Clock (48 MHz, USB_48M) for UTMI */
+#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */
+#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */
+#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */
+/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
+#define PMC_SCDR_UOTGCLK (0x1u << 5) /**< \brief (PMC_SCDR) Disable USB OTG Clock (48 MHz, USB_48M) for UTMI */
+#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */
+#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */
+#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */
+/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
+#define PMC_SCSR_UOTGCLK (0x1u << 5) /**< \brief (PMC_SCSR) USB OTG Clock (48 MHz, USB_48M) Clock Status */
+#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */
+#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */
+#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */
+/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
+#define PMC_PCER0_PID2 (0x1u << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */
+#define PMC_PCER0_PID3 (0x1u << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */
+#define PMC_PCER0_PID4 (0x1u << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */
+#define PMC_PCER0_PID5 (0x1u << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */
+#define PMC_PCER0_PID6 (0x1u << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */
+#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */
+#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */
+#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */
+#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */
+#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */
+#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */
+#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */
+#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */
+#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */
+#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */
+#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */
+#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */
+#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */
+#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */
+#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */
+#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */
+#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */
+#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */
+#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */
+#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */
+#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */
+#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */
+#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */
+#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */
+#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */
+/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
+#define PMC_PCDR0_PID2 (0x1u << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */
+#define PMC_PCDR0_PID3 (0x1u << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */
+#define PMC_PCDR0_PID4 (0x1u << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */
+#define PMC_PCDR0_PID5 (0x1u << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */
+#define PMC_PCDR0_PID6 (0x1u << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */
+#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */
+#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */
+#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */
+#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */
+#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */
+#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */
+#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */
+#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */
+#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */
+#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */
+#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */
+#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */
+#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */
+#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */
+#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */
+#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */
+#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */
+#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */
+#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */
+#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */
+#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */
+#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */
+#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */
+#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */
+#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */
+/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
+#define PMC_PCSR0_PID2 (0x1u << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */
+#define PMC_PCSR0_PID3 (0x1u << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */
+#define PMC_PCSR0_PID4 (0x1u << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */
+#define PMC_PCSR0_PID5 (0x1u << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */
+#define PMC_PCSR0_PID6 (0x1u << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */
+#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */
+#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */
+#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */
+#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */
+#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */
+#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */
+#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */
+#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */
+#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */
+#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */
+#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */
+#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */
+#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */
+#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */
+#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */
+#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */
+#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */
+#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */
+#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */
+#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */
+#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */
+#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */
+#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */
+#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */
+#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */
+/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */
+#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */
+#define CKGR_UCKR_UPLLCOUNT_Pos 20
+#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */
+#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)))
+/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
+#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */
+#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */
+#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */
+#define CKGR_MOR_MOSCRCF_Pos 4
+#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */
+#define   CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default) */
+#define   CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz */
+#define   CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz */
+#define CKGR_MOR_MOSCXTST_Pos 8
+#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */
+#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
+#define CKGR_MOR_KEY_Pos 16
+#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */
+#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
+#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */
+#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */
+/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
+#define CKGR_MCFR_MAINF_Pos 0
+#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */
+#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */
+/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
+#define CKGR_PLLAR_DIVA_Pos 0
+#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider */
+#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
+#define CKGR_PLLAR_PLLACOUNT_Pos 8
+#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */
+#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
+#define CKGR_PLLAR_MULA_Pos 16
+#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */
+#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
+#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */
+/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
+#define PMC_MCKR_CSS_Pos 0
+#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */
+#define   PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */
+#define   PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */
+#define   PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */
+#define   PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) UPLL Clock is selected */
+#define PMC_MCKR_PRES_Pos 4
+#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */
+#define   PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */
+#define   PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */
+#define   PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */
+#define   PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */
+#define   PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */
+#define   PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */
+#define   PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */
+#define   PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */
+#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */
+#define PMC_MCKR_UPLLDIV2 (0x1u << 13) /**< \brief (PMC_MCKR)  */
+/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */
+#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */
+#define PMC_USB_USBDIV_Pos 8
+#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock. */
+#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))
+/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
+#define PMC_PCK_CSS_Pos 0
+#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */
+#define   PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */
+#define   PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */
+#define   PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */
+#define   PMC_PCK_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) UPLL Clock is selected */
+#define   PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */
+#define PMC_PCK_PRES_Pos 4
+#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */
+#define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos)))
+#define   PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */
+#define   PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */
+#define   PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */
+#define   PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */
+#define   PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */
+#define   PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */
+#define   PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */
+/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
+#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */
+#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */
+#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */
+#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */
+#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */
+#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */
+#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */
+#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */
+#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */
+#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */
+/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
+#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */
+#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */
+#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */
+#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */
+#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */
+#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */
+#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */
+#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */
+#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */
+#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */
+/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
+#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */
+#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */
+#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */
+#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */
+#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */
+#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */
+#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */
+#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */
+#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */
+#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */
+/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
+#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */
+#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */
+#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */
+#define PMC_IMR_LOCKU (0x1u << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */
+#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */
+#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */
+#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */
+#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */
+#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */
+#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */
+/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
+#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */
+#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */
+#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */
+#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */
+#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */
+#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */
+#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */
+#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */
+#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */
+#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */
+#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */
+#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */
+#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */
+#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */
+#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */
+#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */
+#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */
+#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */
+#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */
+#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low Power Mode */
+/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
+#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
+#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */
+/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */
+#define PMC_WPMR_WPKEY_Pos 8
+#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */
+#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
+/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */
+#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */
+#define PMC_WPSR_WPVSRC_Pos 8
+#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */
+/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */
+#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */
+#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */
+#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */
+#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */
+#define PMC_PCER1_PID36 (0x1u << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */
+#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */
+#define PMC_PCER1_PID38 (0x1u << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */
+#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */
+#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */
+#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */
+#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */
+#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */
+#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */
+/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */
+#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */
+#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */
+#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */
+#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */
+#define PMC_PCDR1_PID36 (0x1u << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */
+#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */
+#define PMC_PCDR1_PID38 (0x1u << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */
+#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */
+#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */
+#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */
+#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */
+#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */
+#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */
+/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */
+#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */
+#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */
+#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */
+#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */
+#define PMC_PCSR1_PID36 (0x1u << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */
+#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */
+#define PMC_PCSR1_PID38 (0x1u << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */
+#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */
+#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */
+#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */
+#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */
+#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */
+#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */
+/* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */
+#define PMC_PCR_PID_Pos 0
+#define PMC_PCR_PID_Msk (0x3fu << PMC_PCR_PID_Pos) /**< \brief (PMC_PCR) Peripheral ID */
+#define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos)))
+#define PMC_PCR_CMD (0x1u << 12) /**< \brief (PMC_PCR) Command */
+#define PMC_PCR_DIV_Pos 16
+#define PMC_PCR_DIV_Msk (0x3u << PMC_PCR_DIV_Pos) /**< \brief (PMC_PCR) Divisor Value */
+#define   PMC_PCR_DIV_PERIPH_DIV_MCK (0x0u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK */
+#define   PMC_PCR_DIV_PERIPH_DIV2_MCK (0x1u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/2 */
+#define   PMC_PCR_DIV_PERIPH_DIV4_MCK (0x2u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/4 */
+#define PMC_PCR_EN (0x1u << 28) /**< \brief (PMC_PCR) Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_PMC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_pwm.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_pwm.h
new file mode 100644
index 000000000..150737fd4
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_pwm.h
@@ -0,0 +1,686 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PWM_COMPONENT_
+#define _SAM3XA_PWM_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_PWM Pulse Width Modulation Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief PwmCh_num hardware registers */
+typedef struct {
+  RwReg      PWM_CMR;       /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */
+  RwReg      PWM_CDTY;      /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */
+  RwReg      PWM_CDTYUPD;   /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */
+  RwReg      PWM_CPRD;      /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */
+  RwReg      PWM_CPRDUPD;   /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */
+  RwReg      PWM_CCNT;      /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */
+  RwReg      PWM_DT;        /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */
+  RwReg      PWM_DTUPD;     /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */
+} PwmCh_num;
+/** \brief PwmCmp hardware registers */
+typedef struct {
+  RwReg      PWM_CMPV;      /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */
+  RwReg      PWM_CMPVUPD;   /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */
+  RwReg      PWM_CMPM;      /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */
+  RwReg      PWM_CMPMUPD;   /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */
+} PwmCmp;
+/** \brief Pwm hardware registers */
+#define PWMCMP_NUMBER 8
+#define PWMCH_NUM_NUMBER 8
+typedef struct {
+  RwReg      PWM_CLK;       /**< \brief (Pwm Offset: 0x00) PWM Clock Register */
+  WoReg      PWM_ENA;       /**< \brief (Pwm Offset: 0x04) PWM Enable Register */
+  WoReg      PWM_DIS;       /**< \brief (Pwm Offset: 0x08) PWM Disable Register */
+  RoReg      PWM_SR;        /**< \brief (Pwm Offset: 0x0C) PWM Status Register */
+  WoReg      PWM_IER1;      /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */
+  WoReg      PWM_IDR1;      /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */
+  RoReg      PWM_IMR1;      /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */
+  RoReg      PWM_ISR1;      /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */
+  RwReg      PWM_SCM;       /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */
+  RoReg      Reserved1[1];
+  RwReg      PWM_SCUC;      /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */
+  RwReg      PWM_SCUP;      /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */
+  WoReg      PWM_SCUPUPD;   /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */
+  WoReg      PWM_IER2;      /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */
+  WoReg      PWM_IDR2;      /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */
+  RoReg      PWM_IMR2;      /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */
+  RoReg      PWM_ISR2;      /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */
+  RwReg      PWM_OOV;       /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */
+  RwReg      PWM_OS;        /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */
+  WoReg      PWM_OSS;       /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */
+  WoReg      PWM_OSC;       /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */
+  WoReg      PWM_OSSUPD;    /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */
+  WoReg      PWM_OSCUPD;    /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */
+  RwReg      PWM_FMR;       /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */
+  RoReg      PWM_FSR;       /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */
+  WoReg      PWM_FCR;       /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */
+  RwReg      PWM_FPV;       /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */
+  RwReg      PWM_FPE1;      /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register 1 */
+  RwReg      PWM_FPE2;      /**< \brief (Pwm Offset: 0x70) PWM Fault Protection Enable Register 2 */
+  RoReg      Reserved2[2];
+  RwReg      PWM_ELMR[2];   /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */
+  RoReg      Reserved3[11];
+  RwReg      PWM_SMMR;      /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */
+  RoReg      Reserved4[12];
+  WoReg      PWM_WPCR;      /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */
+  RoReg      PWM_WPSR;      /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */
+  RoReg      Reserved5[5];
+  RwReg      PWM_RPR;       /**< \brief (Pwm Offset: 0x100) Receive Pointer Register */
+  RwReg      PWM_RCR;       /**< \brief (Pwm Offset: 0x104) Receive Counter Register */
+  RwReg      PWM_TPR;       /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */
+  RwReg      PWM_TCR;       /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */
+  RwReg      PWM_RNPR;      /**< \brief (Pwm Offset: 0x110) Receive Next Pointer Register */
+  RwReg      PWM_RNCR;      /**< \brief (Pwm Offset: 0x114) Receive Next Counter Register */
+  RwReg      PWM_TNPR;      /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */
+  RwReg      PWM_TNCR;      /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */
+  WoReg      PWM_PTCR;      /**< \brief (Pwm Offset: 0x120) Transfer Control Register */
+  RoReg      PWM_PTSR;      /**< \brief (Pwm Offset: 0x124) Transfer Status Register */
+  RoReg      Reserved6[2];
+  PwmCmp     PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */
+  RoReg      Reserved7[20];
+  PwmCh_num  PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 7 */
+} Pwm;
+#endif /* __ASSEMBLY__ */
+/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */
+#define PWM_CLK_DIVA_Pos 0
+#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
+#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))
+#define PWM_CLK_PREA_Pos 8
+#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
+#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))
+#define PWM_CLK_DIVB_Pos 16
+#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
+#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))
+#define PWM_CLK_PREB_Pos 24
+#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
+#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))
+/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
+#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID4 (0x1u << 4) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID5 (0x1u << 5) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID6 (0x1u << 6) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID7 (0x1u << 7) /**< \brief (PWM_ENA) Channel ID */
+/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
+#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID4 (0x1u << 4) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID5 (0x1u << 5) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID6 (0x1u << 6) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID7 (0x1u << 7) /**< \brief (PWM_DIS) Channel ID */
+/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
+#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID4 (0x1u << 4) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID5 (0x1u << 5) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID6 (0x1u << 6) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID7 (0x1u << 7) /**< \brief (PWM_SR) Channel ID */
+/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */
+#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */
+#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */
+#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */
+#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */
+#define PWM_IER1_CHID4 (0x1u << 4) /**< \brief (PWM_IER1) Counter Event on Channel 4 Interrupt Enable */
+#define PWM_IER1_CHID5 (0x1u << 5) /**< \brief (PWM_IER1) Counter Event on Channel 5 Interrupt Enable */
+#define PWM_IER1_CHID6 (0x1u << 6) /**< \brief (PWM_IER1) Counter Event on Channel 6 Interrupt Enable */
+#define PWM_IER1_CHID7 (0x1u << 7) /**< \brief (PWM_IER1) Counter Event on Channel 7 Interrupt Enable */
+#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */
+#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */
+#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */
+#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */
+#define PWM_IER1_FCHID4 (0x1u << 20) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 4 Interrupt Enable */
+#define PWM_IER1_FCHID5 (0x1u << 21) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 5 Interrupt Enable */
+#define PWM_IER1_FCHID6 (0x1u << 22) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 6 Interrupt Enable */
+#define PWM_IER1_FCHID7 (0x1u << 23) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 7 Interrupt Enable */
+/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */
+#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */
+#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */
+#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */
+#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */
+#define PWM_IDR1_CHID4 (0x1u << 4) /**< \brief (PWM_IDR1) Counter Event on Channel 4 Interrupt Disable */
+#define PWM_IDR1_CHID5 (0x1u << 5) /**< \brief (PWM_IDR1) Counter Event on Channel 5 Interrupt Disable */
+#define PWM_IDR1_CHID6 (0x1u << 6) /**< \brief (PWM_IDR1) Counter Event on Channel 6 Interrupt Disable */
+#define PWM_IDR1_CHID7 (0x1u << 7) /**< \brief (PWM_IDR1) Counter Event on Channel 7 Interrupt Disable */
+#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */
+#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */
+#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */
+#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */
+#define PWM_IDR1_FCHID4 (0x1u << 20) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 4 Interrupt Disable */
+#define PWM_IDR1_FCHID5 (0x1u << 21) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 5 Interrupt Disable */
+#define PWM_IDR1_FCHID6 (0x1u << 22) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 6 Interrupt Disable */
+#define PWM_IDR1_FCHID7 (0x1u << 23) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 7 Interrupt Disable */
+/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */
+#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */
+#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */
+#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */
+#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */
+#define PWM_IMR1_CHID4 (0x1u << 4) /**< \brief (PWM_IMR1) Counter Event on Channel 4 Interrupt Mask */
+#define PWM_IMR1_CHID5 (0x1u << 5) /**< \brief (PWM_IMR1) Counter Event on Channel 5 Interrupt Mask */
+#define PWM_IMR1_CHID6 (0x1u << 6) /**< \brief (PWM_IMR1) Counter Event on Channel 6 Interrupt Mask */
+#define PWM_IMR1_CHID7 (0x1u << 7) /**< \brief (PWM_IMR1) Counter Event on Channel 7 Interrupt Mask */
+#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */
+#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */
+#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */
+#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */
+#define PWM_IMR1_FCHID4 (0x1u << 20) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 4 Interrupt Mask */
+#define PWM_IMR1_FCHID5 (0x1u << 21) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 5 Interrupt Mask */
+#define PWM_IMR1_FCHID6 (0x1u << 22) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 6 Interrupt Mask */
+#define PWM_IMR1_FCHID7 (0x1u << 23) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 7 Interrupt Mask */
+/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */
+#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */
+#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */
+#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */
+#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */
+#define PWM_ISR1_CHID4 (0x1u << 4) /**< \brief (PWM_ISR1) Counter Event on Channel 4 */
+#define PWM_ISR1_CHID5 (0x1u << 5) /**< \brief (PWM_ISR1) Counter Event on Channel 5 */
+#define PWM_ISR1_CHID6 (0x1u << 6) /**< \brief (PWM_ISR1) Counter Event on Channel 6 */
+#define PWM_ISR1_CHID7 (0x1u << 7) /**< \brief (PWM_ISR1) Counter Event on Channel 7 */
+#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */
+#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */
+#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */
+#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */
+#define PWM_ISR1_FCHID4 (0x1u << 20) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 4 */
+#define PWM_ISR1_FCHID5 (0x1u << 21) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 5 */
+#define PWM_ISR1_FCHID6 (0x1u << 22) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 6 */
+#define PWM_ISR1_FCHID7 (0x1u << 23) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 7 */
+/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */
+#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */
+#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */
+#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */
+#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */
+#define PWM_SCM_SYNC4 (0x1u << 4) /**< \brief (PWM_SCM) Synchronous Channel 4 */
+#define PWM_SCM_SYNC5 (0x1u << 5) /**< \brief (PWM_SCM) Synchronous Channel 5 */
+#define PWM_SCM_SYNC6 (0x1u << 6) /**< \brief (PWM_SCM) Synchronous Channel 6 */
+#define PWM_SCM_SYNC7 (0x1u << 7) /**< \brief (PWM_SCM) Synchronous Channel 7 */
+#define PWM_SCM_UPDM_Pos 16
+#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */
+#define   PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */
+#define   PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */
+#define   PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels */
+#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */
+#define PWM_SCM_PTRCS_Pos 21
+#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */
+#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))
+/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */
+#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */
+/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */
+#define PWM_SCUP_UPR_Pos 0
+#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */
+#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))
+#define PWM_SCUP_UPRCNT_Pos 4
+#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */
+#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))
+/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */
+#define PWM_SCUPUPD_UPRUPD_Pos 0
+#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */
+#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))
+/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */
+#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */
+#define PWM_IER2_ENDTX (0x1u << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */
+#define PWM_IER2_TXBUFE (0x1u << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */
+#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */
+#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */
+#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */
+#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */
+#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */
+#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */
+#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */
+#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */
+#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */
+#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */
+#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */
+#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */
+#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */
+#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */
+#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */
+#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */
+#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */
+/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */
+#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */
+#define PWM_IDR2_ENDTX (0x1u << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */
+#define PWM_IDR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */
+#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */
+#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */
+#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */
+#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */
+#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */
+#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */
+#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */
+#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */
+#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */
+#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */
+#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */
+#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */
+#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */
+#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */
+#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */
+#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */
+#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */
+/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */
+#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */
+#define PWM_IMR2_ENDTX (0x1u << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */
+#define PWM_IMR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */
+#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */
+#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */
+#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */
+#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */
+#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */
+#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */
+#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */
+#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */
+#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */
+#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */
+#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */
+#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */
+#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */
+#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */
+#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */
+#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */
+#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */
+/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */
+#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */
+#define PWM_ISR2_ENDTX (0x1u << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */
+#define PWM_ISR2_TXBUFE (0x1u << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */
+#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */
+#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */
+#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */
+#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */
+#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */
+#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */
+#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */
+#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */
+#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */
+#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */
+#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */
+#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */
+#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */
+#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */
+#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */
+#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */
+#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */
+/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */
+#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */
+#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */
+#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */
+#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */
+#define PWM_OOV_OOVH4 (0x1u << 4) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 4 */
+#define PWM_OOV_OOVH5 (0x1u << 5) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 5 */
+#define PWM_OOV_OOVH6 (0x1u << 6) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 6 */
+#define PWM_OOV_OOVH7 (0x1u << 7) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 7 */
+#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */
+#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */
+#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */
+#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */
+#define PWM_OOV_OOVL4 (0x1u << 20) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 4 */
+#define PWM_OOV_OOVL5 (0x1u << 21) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 5 */
+#define PWM_OOV_OOVL6 (0x1u << 22) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 6 */
+#define PWM_OOV_OOVL7 (0x1u << 23) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 7 */
+/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */
+#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */
+#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */
+#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */
+#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */
+#define PWM_OS_OSH4 (0x1u << 4) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 4 */
+#define PWM_OS_OSH5 (0x1u << 5) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 5 */
+#define PWM_OS_OSH6 (0x1u << 6) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 6 */
+#define PWM_OS_OSH7 (0x1u << 7) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 7 */
+#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */
+#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */
+#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */
+#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */
+#define PWM_OS_OSL4 (0x1u << 20) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 4 */
+#define PWM_OS_OSL5 (0x1u << 21) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 5 */
+#define PWM_OS_OSL6 (0x1u << 22) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 6 */
+#define PWM_OS_OSL7 (0x1u << 23) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 7 */
+/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */
+#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */
+#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */
+#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */
+#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */
+#define PWM_OSS_OSSH4 (0x1u << 4) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 4 */
+#define PWM_OSS_OSSH5 (0x1u << 5) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 5 */
+#define PWM_OSS_OSSH6 (0x1u << 6) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 6 */
+#define PWM_OSS_OSSH7 (0x1u << 7) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 7 */
+#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */
+#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */
+#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */
+#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */
+#define PWM_OSS_OSSL4 (0x1u << 20) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 4 */
+#define PWM_OSS_OSSL5 (0x1u << 21) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 5 */
+#define PWM_OSS_OSSL6 (0x1u << 22) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 6 */
+#define PWM_OSS_OSSL7 (0x1u << 23) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 7 */
+/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */
+#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */
+#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */
+#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */
+#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */
+#define PWM_OSC_OSCH4 (0x1u << 4) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 4 */
+#define PWM_OSC_OSCH5 (0x1u << 5) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 5 */
+#define PWM_OSC_OSCH6 (0x1u << 6) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 6 */
+#define PWM_OSC_OSCH7 (0x1u << 7) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 7 */
+#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */
+#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */
+#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */
+#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */
+#define PWM_OSC_OSCL4 (0x1u << 20) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 4 */
+#define PWM_OSC_OSCL5 (0x1u << 21) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 5 */
+#define PWM_OSC_OSCL6 (0x1u << 22) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 6 */
+#define PWM_OSC_OSCL7 (0x1u << 23) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 7 */
+/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */
+#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */
+#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */
+#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */
+#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */
+#define PWM_OSSUPD_OSSUPH4 (0x1u << 4) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 4 */
+#define PWM_OSSUPD_OSSUPH5 (0x1u << 5) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 5 */
+#define PWM_OSSUPD_OSSUPH6 (0x1u << 6) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 6 */
+#define PWM_OSSUPD_OSSUPH7 (0x1u << 7) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 7 */
+#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */
+#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */
+#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */
+#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */
+#define PWM_OSSUPD_OSSUPL4 (0x1u << 20) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 4 */
+#define PWM_OSSUPD_OSSUPL5 (0x1u << 21) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 5 */
+#define PWM_OSSUPD_OSSUPL6 (0x1u << 22) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 6 */
+#define PWM_OSSUPD_OSSUPL7 (0x1u << 23) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 7 */
+/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */
+#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */
+#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */
+#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */
+#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */
+#define PWM_OSCUPD_OSCUPH4 (0x1u << 4) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 4 */
+#define PWM_OSCUPD_OSCUPH5 (0x1u << 5) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 5 */
+#define PWM_OSCUPD_OSCUPH6 (0x1u << 6) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 6 */
+#define PWM_OSCUPD_OSCUPH7 (0x1u << 7) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 7 */
+#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */
+#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */
+#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */
+#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */
+#define PWM_OSCUPD_OSCUPL4 (0x1u << 20) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 4 */
+#define PWM_OSCUPD_OSCUPL5 (0x1u << 21) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 5 */
+#define PWM_OSCUPD_OSCUPDL6 (0x1u << 22) /**< \brief (PWM_OSCUPD)  */
+#define PWM_OSCUPD_OSCUPL7 (0x1u << 23) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 7 */
+/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */
+#define PWM_FMR_FPOL_Pos 0
+#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))
+#define PWM_FMR_FMOD_Pos 8
+#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))
+#define PWM_FMR_FFIL_Pos 16
+#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))
+/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */
+#define PWM_FSR_FIV_Pos 0
+#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value (fault input bit varies from 0 to 5) */
+#define PWM_FSR_FS_Pos 8
+#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status (fault input bit varies from 0 to 5) */
+/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */
+#define PWM_FCR_FCLR_Pos 0
+#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear (fault input bit varies from 0 to 5) */
+#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))
+/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */
+#define PWM_FPV_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */
+#define PWM_FPV_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */
+#define PWM_FPV_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */
+#define PWM_FPV_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */
+#define PWM_FPV_FPVH4 (0x1u << 4) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 4 */
+#define PWM_FPV_FPVH5 (0x1u << 5) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 5 */
+#define PWM_FPV_FPVH6 (0x1u << 6) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 6 */
+#define PWM_FPV_FPVH7 (0x1u << 7) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 7 */
+#define PWM_FPV_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */
+#define PWM_FPV_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */
+#define PWM_FPV_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */
+#define PWM_FPV_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */
+#define PWM_FPV_FPVL4 (0x1u << 20) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 4 */
+#define PWM_FPV_FPVL5 (0x1u << 21) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 5 */
+#define PWM_FPV_FPVL6 (0x1u << 22) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 6 */
+#define PWM_FPV_FPVL7 (0x1u << 23) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 7 */
+/* -------- PWM_FPE1 : (PWM Offset: 0x6C) PWM Fault Protection Enable Register 1 -------- */
+#define PWM_FPE1_FPE0_Pos 0
+#define PWM_FPE1_FPE0_Msk (0xffu << PWM_FPE1_FPE0_Pos) /**< \brief (PWM_FPE1) Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) */
+#define PWM_FPE1_FPE0(value) ((PWM_FPE1_FPE0_Msk & ((value) << PWM_FPE1_FPE0_Pos)))
+#define PWM_FPE1_FPE1_Pos 8
+#define PWM_FPE1_FPE1_Msk (0xffu << PWM_FPE1_FPE1_Pos) /**< \brief (PWM_FPE1) Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) */
+#define PWM_FPE1_FPE1(value) ((PWM_FPE1_FPE1_Msk & ((value) << PWM_FPE1_FPE1_Pos)))
+#define PWM_FPE1_FPE2_Pos 16
+#define PWM_FPE1_FPE2_Msk (0xffu << PWM_FPE1_FPE2_Pos) /**< \brief (PWM_FPE1) Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) */
+#define PWM_FPE1_FPE2(value) ((PWM_FPE1_FPE2_Msk & ((value) << PWM_FPE1_FPE2_Pos)))
+#define PWM_FPE1_FPE3_Pos 24
+#define PWM_FPE1_FPE3_Msk (0xffu << PWM_FPE1_FPE3_Pos) /**< \brief (PWM_FPE1) Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) */
+#define PWM_FPE1_FPE3(value) ((PWM_FPE1_FPE3_Msk & ((value) << PWM_FPE1_FPE3_Pos)))
+/* -------- PWM_FPE2 : (PWM Offset: 0x70) PWM Fault Protection Enable Register 2 -------- */
+#define PWM_FPE2_FPE4_Pos 0
+#define PWM_FPE2_FPE4_Msk (0xffu << PWM_FPE2_FPE4_Pos) /**< \brief (PWM_FPE2) Fault Protection Enable for channel 4 (fault input bit varies from 0 to 5) */
+#define PWM_FPE2_FPE4(value) ((PWM_FPE2_FPE4_Msk & ((value) << PWM_FPE2_FPE4_Pos)))
+#define PWM_FPE2_FPE5_Pos 8
+#define PWM_FPE2_FPE5_Msk (0xffu << PWM_FPE2_FPE5_Pos) /**< \brief (PWM_FPE2) Fault Protection Enable for channel 5 (fault input bit varies from 0 to 5) */
+#define PWM_FPE2_FPE5(value) ((PWM_FPE2_FPE5_Msk & ((value) << PWM_FPE2_FPE5_Pos)))
+#define PWM_FPE2_FPE6_Pos 16
+#define PWM_FPE2_FPE6_Msk (0xffu << PWM_FPE2_FPE6_Pos) /**< \brief (PWM_FPE2) Fault Protection Enable for channel 6 (fault input bit varies from 0 to 5) */
+#define PWM_FPE2_FPE6(value) ((PWM_FPE2_FPE6_Msk & ((value) << PWM_FPE2_FPE6_Pos)))
+#define PWM_FPE2_FPE7_Pos 24
+#define PWM_FPE2_FPE7_Msk (0xffu << PWM_FPE2_FPE7_Pos) /**< \brief (PWM_FPE2) Fault Protection Enable for channel 7 (fault input bit varies from 0 to 5) */
+#define PWM_FPE2_FPE7(value) ((PWM_FPE2_FPE7_Msk & ((value) << PWM_FPE2_FPE7_Pos)))
+/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */
+#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */
+#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */
+#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */
+#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */
+#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */
+#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */
+#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */
+#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */
+/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */
+#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_GCEN2 (0x1u << 2) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_GCEN3 (0x1u << 3) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */
+#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */
+#define PWM_SMMR_DOWN2 (0x1u << 18) /**< \brief (PWM_SMMR) DOWN Count */
+#define PWM_SMMR_DOWN3 (0x1u << 19) /**< \brief (PWM_SMMR) DOWN Count */
+/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */
+#define PWM_WPCR_WPCMD_Pos 0
+#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protect Command */
+#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))
+#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */
+#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */
+#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */
+#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */
+#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */
+#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */
+#define PWM_WPCR_WPKEY_Pos 8
+#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protect Key */
+#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))
+/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */
+#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */
+#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPVSRC_Pos 16
+#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */
+/* -------- PWM_RPR : (PWM Offset: 0x100) Receive Pointer Register -------- */
+#define PWM_RPR_RXPTR_Pos 0
+#define PWM_RPR_RXPTR_Msk (0xffffffffu << PWM_RPR_RXPTR_Pos) /**< \brief (PWM_RPR) Receive Pointer Register */
+#define PWM_RPR_RXPTR(value) ((PWM_RPR_RXPTR_Msk & ((value) << PWM_RPR_RXPTR_Pos)))
+/* -------- PWM_RCR : (PWM Offset: 0x104) Receive Counter Register -------- */
+#define PWM_RCR_RXCTR_Pos 0
+#define PWM_RCR_RXCTR_Msk (0xffffu << PWM_RCR_RXCTR_Pos) /**< \brief (PWM_RCR) Receive Counter Register */
+#define PWM_RCR_RXCTR(value) ((PWM_RCR_RXCTR_Msk & ((value) << PWM_RCR_RXCTR_Pos)))
+/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */
+#define PWM_TPR_TXPTR_Pos 0
+#define PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos) /**< \brief (PWM_TPR) Transmit Counter Register */
+#define PWM_TPR_TXPTR(value) ((PWM_TPR_TXPTR_Msk & ((value) << PWM_TPR_TXPTR_Pos)))
+/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */
+#define PWM_TCR_TXCTR_Pos 0
+#define PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos) /**< \brief (PWM_TCR) Transmit Counter Register */
+#define PWM_TCR_TXCTR(value) ((PWM_TCR_TXCTR_Msk & ((value) << PWM_TCR_TXCTR_Pos)))
+/* -------- PWM_RNPR : (PWM Offset: 0x110) Receive Next Pointer Register -------- */
+#define PWM_RNPR_RXNPTR_Pos 0
+#define PWM_RNPR_RXNPTR_Msk (0xffffffffu << PWM_RNPR_RXNPTR_Pos) /**< \brief (PWM_RNPR) Receive Next Pointer */
+#define PWM_RNPR_RXNPTR(value) ((PWM_RNPR_RXNPTR_Msk & ((value) << PWM_RNPR_RXNPTR_Pos)))
+/* -------- PWM_RNCR : (PWM Offset: 0x114) Receive Next Counter Register -------- */
+#define PWM_RNCR_RXNCTR_Pos 0
+#define PWM_RNCR_RXNCTR_Msk (0xffffu << PWM_RNCR_RXNCTR_Pos) /**< \brief (PWM_RNCR) Receive Next Counter */
+#define PWM_RNCR_RXNCTR(value) ((PWM_RNCR_RXNCTR_Msk & ((value) << PWM_RNCR_RXNCTR_Pos)))
+/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */
+#define PWM_TNPR_TXNPTR_Pos 0
+#define PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos) /**< \brief (PWM_TNPR) Transmit Next Pointer */
+#define PWM_TNPR_TXNPTR(value) ((PWM_TNPR_TXNPTR_Msk & ((value) << PWM_TNPR_TXNPTR_Pos)))
+/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */
+#define PWM_TNCR_TXNCTR_Pos 0
+#define PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos) /**< \brief (PWM_TNCR) Transmit Counter Next */
+#define PWM_TNCR_TXNCTR(value) ((PWM_TNCR_TXNCTR_Msk & ((value) << PWM_TNCR_TXNCTR_Pos)))
+/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */
+#define PWM_PTCR_RXTEN (0x1u << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */
+#define PWM_PTCR_RXTDIS (0x1u << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */
+#define PWM_PTCR_TXTEN (0x1u << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */
+#define PWM_PTCR_TXTDIS (0x1u << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */
+/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */
+#define PWM_PTSR_RXTEN (0x1u << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */
+#define PWM_PTSR_TXTEN (0x1u << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */
+/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */
+#define PWM_CMPV_CV_Pos 0
+#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */
+#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))
+#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */
+/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */
+#define PWM_CMPVUPD_CVUPD_Pos 0
+#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */
+#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))
+#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */
+/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */
+#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */
+#define PWM_CMPM_CTR_Pos 4
+#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */
+#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))
+#define PWM_CMPM_CPR_Pos 8
+#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */
+#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))
+#define PWM_CMPM_CPRCNT_Pos 12
+#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */
+#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))
+#define PWM_CMPM_CUPR_Pos 16
+#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */
+#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))
+#define PWM_CMPM_CUPRCNT_Pos 20
+#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */
+#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))
+/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */
+#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */
+#define PWM_CMPMUPD_CTRUPD_Pos 4
+#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */
+#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))
+#define PWM_CMPMUPD_CPRUPD_Pos 8
+#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */
+#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))
+#define PWM_CMPMUPD_CUPRUPD_Pos 16
+#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */
+#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))
+/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */
+#define PWM_CMR_CPRE_Pos 0
+#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */
+#define   PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master clock */
+#define   PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Master clock/2 */
+#define   PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Master clock/4 */
+#define   PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Master clock/8 */
+#define   PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Master clock/16 */
+#define   PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Master clock/32 */
+#define   PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Master clock/64 */
+#define   PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Master clock/128 */
+#define   PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Master clock/256 */
+#define   PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Master clock/512 */
+#define   PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Master clock/1024 */
+#define   PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */
+#define   PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */
+#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */
+#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */
+#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */
+#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */
+#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */
+#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */
+/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */
+#define PWM_CDTY_CDTY_Pos 0
+#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */
+#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))
+/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */
+#define PWM_CDTYUPD_CDTYUPD_Pos 0
+#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */
+#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))
+/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */
+#define PWM_CPRD_CPRD_Pos 0
+#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */
+#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))
+/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */
+#define PWM_CPRDUPD_CPRDUPD_Pos 0
+#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */
+#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))
+/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */
+#define PWM_CCNT_CNT_Pos 0
+#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */
+/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */
+#define PWM_DT_DTH_Pos 0
+#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */
+#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))
+#define PWM_DT_DTL_Pos 16
+#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */
+#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))
+/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */
+#define PWM_DTUPD_DTHUPD_Pos 0
+#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */
+#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))
+#define PWM_DTUPD_DTLUPD_Pos 16
+#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */
+#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3XA_PWM_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_rstc.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_rstc.h
new file mode 100644
index 000000000..225a768b4
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_rstc.h
@@ -0,0 +1,73 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_RSTC_COMPONENT_
+#define _SAM3XA_RSTC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Reset Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_RSTC Reset Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Rstc hardware registers */
+typedef struct {
+  WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
+  RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
+  RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
+} Rstc;
+#endif /* __ASSEMBLY__ */
+/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
+#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */
+#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */
+#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */
+#define RSTC_CR_KEY_Pos 24
+#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Password */
+#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
+/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
+#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */
+#define RSTC_SR_RSTTYP_Pos 8
+#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */
+#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
+#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
+/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
+#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */
+#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
+#define RSTC_MR_ERSTL_Pos 8
+#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */
+#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
+#define RSTC_MR_KEY_Pos 24
+#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */
+#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3XA_RSTC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_rtc.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_rtc.h
new file mode 100644
index 000000000..0f29c6c18
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_rtc.h
@@ -0,0 +1,168 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_RTC_COMPONENT_
+#define _SAM3XA_RTC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Real-time Clock */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_RTC Real-time Clock */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Rtc hardware registers */
+typedef struct {
+  RwReg RTC_CR;        /**< \brief (Rtc Offset: 0x00) Control Register */
+  RwReg RTC_MR;        /**< \brief (Rtc Offset: 0x04) Mode Register */
+  RwReg RTC_TIMR;      /**< \brief (Rtc Offset: 0x08) Time Register */
+  RwReg RTC_CALR;      /**< \brief (Rtc Offset: 0x0C) Calendar Register */
+  RwReg RTC_TIMALR;    /**< \brief (Rtc Offset: 0x10) Time Alarm Register */
+  RwReg RTC_CALALR;    /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */
+  RoReg RTC_SR;        /**< \brief (Rtc Offset: 0x18) Status Register */
+  WoReg RTC_SCCR;      /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */
+  WoReg RTC_IER;       /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */
+  WoReg RTC_IDR;       /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */
+  RoReg RTC_IMR;       /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */
+  RoReg RTC_VER;       /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */
+  RoReg Reserved1[45];
+  RwReg RTC_WPMR;      /**< \brief (Rtc Offset: 0xE4) Write Protect Mode Register */
+} Rtc;
+#endif /* __ASSEMBLY__ */
+/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
+#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */
+#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */
+#define RTC_CR_TIMEVSEL_Pos 8
+#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */
+#define   RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */
+#define   RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */
+#define   RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */
+#define   RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */
+#define RTC_CR_CALEVSEL_Pos 16
+#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */
+#define   RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */
+#define   RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */
+#define   RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */
+/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
+#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */
+/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
+#define RTC_TIMR_SEC_Pos 0
+#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */
+#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
+#define RTC_TIMR_MIN_Pos 8
+#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */
+#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
+#define RTC_TIMR_HOUR_Pos 16
+#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */
+#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
+#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */
+/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
+#define RTC_CALR_CENT_Pos 0
+#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */
+#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
+#define RTC_CALR_YEAR_Pos 8
+#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */
+#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
+#define RTC_CALR_MONTH_Pos 16
+#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */
+#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
+#define RTC_CALR_DAY_Pos 21
+#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */
+#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
+#define RTC_CALR_DATE_Pos 24
+#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */
+#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
+/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
+#define RTC_TIMALR_SEC_Pos 0
+#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */
+#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
+#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */
+#define RTC_TIMALR_MIN_Pos 8
+#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */
+#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
+#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */
+#define RTC_TIMALR_HOUR_Pos 16
+#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */
+#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
+#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */
+#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */
+/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
+#define RTC_CALALR_MONTH_Pos 16
+#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */
+#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
+#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */
+#define RTC_CALALR_DATE_Pos 24
+#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */
+#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
+#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */
+/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
+#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */
+#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */
+#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */
+#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */
+#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */
+/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
+#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */
+#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */
+#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */
+#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */
+#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */
+/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
+#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */
+#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */
+#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */
+#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */
+#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */
+/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
+#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */
+#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */
+#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */
+#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */
+#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */
+/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
+#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */
+#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */
+#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */
+#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */
+#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */
+/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
+#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */
+#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */
+#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */
+#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */
+/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protect Mode Register -------- */
+#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protect Enable */
+#define RTC_WPMR_WPKEY_Pos 8
+#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR)  */
+#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3XA_RTC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_rtt.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_rtt.h
new file mode 100644
index 000000000..0903a2254
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_rtt.h
@@ -0,0 +1,69 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_RTT_COMPONENT_
+#define _SAM3XA_RTT_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Real-time Timer */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_RTT Real-time Timer */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Rtt hardware registers */
+typedef struct {
+  RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */
+  RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */
+  RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */
+  RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */
+} Rtt;
+#endif /* __ASSEMBLY__ */
+/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */
+#define RTT_MR_RTPRES_Pos 0
+#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */
+#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)))
+#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */
+#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */
+#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */
+/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */
+#define RTT_AR_ALMV_Pos 0
+#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */
+#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)))
+/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */
+#define RTT_VR_CRTV_Pos 0
+#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */
+/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */
+#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */
+#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_RTT_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_sdramc.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_sdramc.h
new file mode 100644
index 000000000..ac1069551
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_sdramc.h
@@ -0,0 +1,188 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SDRAMC_COMPONENT_
+#define _SAM3XA_SDRAMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR SDRAM Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_SDRAMC SDRAM Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Sdramc hardware registers */
+typedef struct {
+  RwReg SDRAMC_MR;    /**< \brief (Sdramc Offset: 0x00) SDRAMC Mode Register */
+  RwReg SDRAMC_TR;    /**< \brief (Sdramc Offset: 0x04) SDRAMC Refresh Timer Register */
+  RwReg SDRAMC_CR;    /**< \brief (Sdramc Offset: 0x08) SDRAMC Configuration Register */
+  RoReg Reserved1[1];
+  RwReg SDRAMC_LPR;   /**< \brief (Sdramc Offset: 0x10) SDRAMC Low Power Register */
+  WoReg SDRAMC_IER;   /**< \brief (Sdramc Offset: 0x14) SDRAMC Interrupt Enable Register */
+  WoReg SDRAMC_IDR;   /**< \brief (Sdramc Offset: 0x18) SDRAMC Interrupt Disable Register */
+  RoReg SDRAMC_IMR;   /**< \brief (Sdramc Offset: 0x1C) SDRAMC Interrupt Mask Register */
+  RoReg SDRAMC_ISR;   /**< \brief (Sdramc Offset: 0x20) SDRAMC Interrupt Status Register */
+  RwReg SDRAMC_MDR;   /**< \brief (Sdramc Offset: 0x24) SDRAMC Memory Device Register */
+  RwReg SDRAMC_CR1;   /**< \brief (Sdramc Offset: 0x28) SDRAMC Configuration Register 1 */
+  RwReg SDRAMC_OCMS;  /**< \brief (Sdramc Offset: 0x2C) SDRAMC OCMS Register 1 */
+} Sdramc;
+#endif /* __ASSEMBLY__ */
+/* -------- SDRAMC_MR : (SDRAMC Offset: 0x00) SDRAMC Mode Register -------- */
+#define SDRAMC_MR_MODE_Pos 0
+#define SDRAMC_MR_MODE_Msk (0x7u << SDRAMC_MR_MODE_Pos) /**< \brief (SDRAMC_MR) SDRAMC Command Mode */
+#define   SDRAMC_MR_MODE_NORMAL (0x0u << 0) /**< \brief (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM. */
+#define   SDRAMC_MR_MODE_NOP (0x1u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */
+#define   SDRAMC_MR_MODE_ALLBANKS_PRECHARGE (0x2u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */
+#define   SDRAMC_MR_MODE_LOAD_MODEREG (0x3u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */
+#define   SDRAMC_MR_MODE_AUTO_REFRESH (0x4u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, command must be followed by a write to the SDRAM. */
+#define   SDRAMC_MR_MODE_EXT_LOAD_MODEREG (0x5u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. */
+#define   SDRAMC_MR_MODE_DEEP_POWERDOWN (0x6u << 0) /**< \brief (SDRAMC_MR) Deep power-down mode. Enters deep power-down mode. */
+/* -------- SDRAMC_TR : (SDRAMC Offset: 0x04) SDRAMC Refresh Timer Register -------- */
+#define SDRAMC_TR_COUNT_Pos 0
+#define SDRAMC_TR_COUNT_Msk (0xfffu << SDRAMC_TR_COUNT_Pos) /**< \brief (SDRAMC_TR) SDRAMC Refresh Timer Count */
+#define SDRAMC_TR_COUNT(value) ((SDRAMC_TR_COUNT_Msk & ((value) << SDRAMC_TR_COUNT_Pos)))
+/* -------- SDRAMC_CR : (SDRAMC Offset: 0x08) SDRAMC Configuration Register -------- */
+#define SDRAMC_CR_NC_Pos 0
+#define SDRAMC_CR_NC_Msk (0x3u << SDRAMC_CR_NC_Pos) /**< \brief (SDRAMC_CR) Number of Column Bits */
+#define   SDRAMC_CR_NC_COL8 (0x0u << 0) /**< \brief (SDRAMC_CR) 8 column bits */
+#define   SDRAMC_CR_NC_COL9 (0x1u << 0) /**< \brief (SDRAMC_CR) 9 column bits */
+#define   SDRAMC_CR_NC_COL10 (0x2u << 0) /**< \brief (SDRAMC_CR) 10 column bits */
+#define   SDRAMC_CR_NC_COL11 (0x3u << 0) /**< \brief (SDRAMC_CR) 11 column bits */
+#define SDRAMC_CR_NR_Pos 2
+#define SDRAMC_CR_NR_Msk (0x3u << SDRAMC_CR_NR_Pos) /**< \brief (SDRAMC_CR) Number of Row Bits */
+#define   SDRAMC_CR_NR_ROW11 (0x0u << 2) /**< \brief (SDRAMC_CR) 11 row bits */
+#define   SDRAMC_CR_NR_ROW12 (0x1u << 2) /**< \brief (SDRAMC_CR) 12 row bits */
+#define   SDRAMC_CR_NR_ROW13 (0x2u << 2) /**< \brief (SDRAMC_CR) 13 row bits */
+#define SDRAMC_CR_NB (0x1u << 4) /**< \brief (SDRAMC_CR) Number of Banks */
+#define   SDRAMC_CR_NB_BANK2 (0x0u << 4) /**< \brief (SDRAMC_CR) 2 banks */
+#define   SDRAMC_CR_NB_BANK4 (0x1u << 4) /**< \brief (SDRAMC_CR) 4 banks */
+#define SDRAMC_CR_CAS_Pos 5
+#define SDRAMC_CR_CAS_Msk (0x3u << SDRAMC_CR_CAS_Pos) /**< \brief (SDRAMC_CR) CAS Latency */
+#define   SDRAMC_CR_CAS_LATENCY1 (0x1u << 5) /**< \brief (SDRAMC_CR) 1 cycle CAS latency */
+#define   SDRAMC_CR_CAS_LATENCY2 (0x2u << 5) /**< \brief (SDRAMC_CR) 2 cycle CAS latency */
+#define   SDRAMC_CR_CAS_LATENCY3 (0x3u << 5) /**< \brief (SDRAMC_CR) 3 cycle CAS latency */
+#define SDRAMC_CR_DBW (0x1u << 7) /**< \brief (SDRAMC_CR) Data Bus Width */
+#define SDRAMC_CR_TWR_Pos 8
+#define SDRAMC_CR_TWR_Msk (0xfu << SDRAMC_CR_TWR_Pos) /**< \brief (SDRAMC_CR) Write Recovery Delay */
+#define SDRAMC_CR_TWR(value) ((SDRAMC_CR_TWR_Msk & ((value) << SDRAMC_CR_TWR_Pos)))
+#define SDRAMC_CR_TRC_TRFC_Pos 12
+#define SDRAMC_CR_TRC_TRFC_Msk (0xfu << SDRAMC_CR_TRC_TRFC_Pos) /**< \brief (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle */
+#define SDRAMC_CR_TRC_TRFC(value) ((SDRAMC_CR_TRC_TRFC_Msk & ((value) << SDRAMC_CR_TRC_TRFC_Pos)))
+#define SDRAMC_CR_TRP_Pos 16
+#define SDRAMC_CR_TRP_Msk (0xfu << SDRAMC_CR_TRP_Pos) /**< \brief (SDRAMC_CR) Row Precharge Delay */
+#define SDRAMC_CR_TRP(value) ((SDRAMC_CR_TRP_Msk & ((value) << SDRAMC_CR_TRP_Pos)))
+#define SDRAMC_CR_TRCD_Pos 20
+#define SDRAMC_CR_TRCD_Msk (0xfu << SDRAMC_CR_TRCD_Pos) /**< \brief (SDRAMC_CR) Row to Column Delay */
+#define SDRAMC_CR_TRCD(value) ((SDRAMC_CR_TRCD_Msk & ((value) << SDRAMC_CR_TRCD_Pos)))
+#define SDRAMC_CR_TRAS_Pos 24
+#define SDRAMC_CR_TRAS_Msk (0xfu << SDRAMC_CR_TRAS_Pos) /**< \brief (SDRAMC_CR) Active to Precharge Delay */
+#define SDRAMC_CR_TRAS(value) ((SDRAMC_CR_TRAS_Msk & ((value) << SDRAMC_CR_TRAS_Pos)))
+#define SDRAMC_CR_TXSR_Pos 28
+#define SDRAMC_CR_TXSR_Msk (0xfu << SDRAMC_CR_TXSR_Pos) /**< \brief (SDRAMC_CR) Exit Self Refresh to Active Delay */
+#define SDRAMC_CR_TXSR(value) ((SDRAMC_CR_TXSR_Msk & ((value) << SDRAMC_CR_TXSR_Pos)))
+/* -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAMC Low Power Register -------- */
+#define SDRAMC_LPR_LPCB_Pos 0
+#define SDRAMC_LPR_LPCB_Msk (0x3u << SDRAMC_LPR_LPCB_Pos) /**< \brief (SDRAMC_LPR) Low-power Configuration Bits */
+#define   SDRAMC_LPR_LPCB_DISABLED (0x0u << 0) /**< \brief (SDRAMC_LPR) Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. */
+#define   SDRAMC_LPR_LPCB_SELF_REFRESH (0x1u << 0) /**< \brief (SDRAMC_LPR) The SDRAM Controller issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access. */
+#define   SDRAMC_LPR_LPCB_POWER_DOWN (0x2u << 0) /**< \brief (SDRAMC_LPR) The SDRAM Controller issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access. */
+#define   SDRAMC_LPR_LPCB_DEEP_POWER_DOWN (0x3u << 0) /**< \brief (SDRAMC_LPR) The SDRAM Controller issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. */
+#define SDRAMC_LPR_PASR_Pos 4
+#define SDRAMC_LPR_PASR_Msk (0x7u << SDRAMC_LPR_PASR_Pos) /**< \brief (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) */
+#define SDRAMC_LPR_PASR(value) ((SDRAMC_LPR_PASR_Msk & ((value) << SDRAMC_LPR_PASR_Pos)))
+#define SDRAMC_LPR_TCSR_Pos 8
+#define SDRAMC_LPR_TCSR_Msk (0x3u << SDRAMC_LPR_TCSR_Pos) /**< \brief (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) */
+#define SDRAMC_LPR_TCSR(value) ((SDRAMC_LPR_TCSR_Msk & ((value) << SDRAMC_LPR_TCSR_Pos)))
+#define SDRAMC_LPR_DS_Pos 10
+#define SDRAMC_LPR_DS_Msk (0x3u << SDRAMC_LPR_DS_Pos) /**< \brief (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) */
+#define SDRAMC_LPR_DS(value) ((SDRAMC_LPR_DS_Msk & ((value) << SDRAMC_LPR_DS_Pos)))
+#define SDRAMC_LPR_TIMEOUT_Pos 12
+#define SDRAMC_LPR_TIMEOUT_Msk (0x3u << SDRAMC_LPR_TIMEOUT_Pos) /**< \brief (SDRAMC_LPR) Time to define when low-power mode is enable */
+#define   SDRAMC_LPR_TIMEOUT_LP_LAST_XFER (0x0u << 12) /**< \brief (SDRAMC_LPR) The SDRAM controller activates the SDRAM low-power mode immediately after the end of the last transfer. */
+#define   SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64 (0x1u << 12) /**< \brief (SDRAMC_LPR) The SDRAM controller activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. */
+#define   SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128 (0x2u << 12) /**< \brief (SDRAMC_LPR) The SDRAM controller activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. */
+/* -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAMC Interrupt Enable Register -------- */
+#define SDRAMC_IER_RES (0x1u << 0) /**< \brief (SDRAMC_IER) Refresh Error Status */
+/* -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAMC Interrupt Disable Register -------- */
+#define SDRAMC_IDR_RES (0x1u << 0) /**< \brief (SDRAMC_IDR) Refresh Error Status */
+/* -------- SDRAMC_IMR : (SDRAMC Offset: 0x1C) SDRAMC Interrupt Mask Register -------- */
+#define SDRAMC_IMR_RES (0x1u << 0) /**< \brief (SDRAMC_IMR) Refresh Error Status */
+/* -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAMC Interrupt Status Register -------- */
+#define SDRAMC_ISR_RES (0x1u << 0) /**< \brief (SDRAMC_ISR) Refresh Error Status */
+/* -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAMC Memory Device Register -------- */
+#define SDRAMC_MDR_MD_Pos 0
+#define SDRAMC_MDR_MD_Msk (0x3u << SDRAMC_MDR_MD_Pos) /**< \brief (SDRAMC_MDR) Memory Device Type */
+#define   SDRAMC_MDR_MD_SDRAM (0x0u << 0) /**< \brief (SDRAMC_MDR) SDRAM */
+#define   SDRAMC_MDR_MD_LPSDRAM (0x1u << 0) /**< \brief (SDRAMC_MDR) Low-power SDRAM */
+/* -------- SDRAMC_CR1 : (SDRAMC Offset: 0x28) SDRAMC Configuration Register 1 -------- */
+#define SDRAMC_CR1_NC_Pos 0
+#define SDRAMC_CR1_NC_Msk (0x3u << SDRAMC_CR1_NC_Pos) /**< \brief (SDRAMC_CR1) Number of Column Bits */
+#define   SDRAMC_CR1_NC_COL8 (0x0u << 0) /**< \brief (SDRAMC_CR1) 8 column bits */
+#define   SDRAMC_CR1_NC_COL9 (0x1u << 0) /**< \brief (SDRAMC_CR1) 9 column bits */
+#define   SDRAMC_CR1_NC_COL10 (0x2u << 0) /**< \brief (SDRAMC_CR1) 10 column bits */
+#define   SDRAMC_CR1_NC_COL11 (0x3u << 0) /**< \brief (SDRAMC_CR1) 11 column bits */
+#define SDRAMC_CR1_NR_Pos 2
+#define SDRAMC_CR1_NR_Msk (0x3u << SDRAMC_CR1_NR_Pos) /**< \brief (SDRAMC_CR1) Number of Row Bits */
+#define   SDRAMC_CR1_NR_ROW11 (0x0u << 2) /**< \brief (SDRAMC_CR1) 11 row bits */
+#define   SDRAMC_CR1_NR_ROW12 (0x1u << 2) /**< \brief (SDRAMC_CR1) 12 row bits */
+#define   SDRAMC_CR1_NR_ROW13 (0x2u << 2) /**< \brief (SDRAMC_CR1) 13 row bits */
+#define SDRAMC_CR1_NB (0x1u << 4) /**< \brief (SDRAMC_CR1) Number of Banks */
+#define   SDRAMC_CR1_NB_BANK2 (0x0u << 4) /**< \brief (SDRAMC_CR1) 2 banks */
+#define   SDRAMC_CR1_NB_BANK4 (0x1u << 4) /**< \brief (SDRAMC_CR1) 4 banks */
+#define SDRAMC_CR1_CAS_Pos 5
+#define SDRAMC_CR1_CAS_Msk (0x3u << SDRAMC_CR1_CAS_Pos) /**< \brief (SDRAMC_CR1) CAS Latency */
+#define   SDRAMC_CR1_CAS_LATENCY1 (0x1u << 5) /**< \brief (SDRAMC_CR1) 1 cycle CAS latency */
+#define   SDRAMC_CR1_CAS_LATENCY2 (0x2u << 5) /**< \brief (SDRAMC_CR1) 2 cycle CAS latency */
+#define   SDRAMC_CR1_CAS_LATENCY3 (0x3u << 5) /**< \brief (SDRAMC_CR1) 3 cycle CAS latency */
+#define SDRAMC_CR1_DBW (0x1u << 7) /**< \brief (SDRAMC_CR1) Data Bus Width */
+#define SDRAMC_CR1_TWR_Pos 8
+#define SDRAMC_CR1_TWR_Msk (0xfu << SDRAMC_CR1_TWR_Pos) /**< \brief (SDRAMC_CR1) Write Recovery Delay */
+#define SDRAMC_CR1_TWR(value) ((SDRAMC_CR1_TWR_Msk & ((value) << SDRAMC_CR1_TWR_Pos)))
+#define SDRAMC_CR1_TRC_TRFC_Pos 12
+#define SDRAMC_CR1_TRC_TRFC_Msk (0xfu << SDRAMC_CR1_TRC_TRFC_Pos) /**< \brief (SDRAMC_CR1) Row Cycle Delay and Row Refresh Cycle */
+#define SDRAMC_CR1_TRC_TRFC(value) ((SDRAMC_CR1_TRC_TRFC_Msk & ((value) << SDRAMC_CR1_TRC_TRFC_Pos)))
+#define SDRAMC_CR1_TRP_Pos 16
+#define SDRAMC_CR1_TRP_Msk (0xfu << SDRAMC_CR1_TRP_Pos) /**< \brief (SDRAMC_CR1) Row Precharge Delay */
+#define SDRAMC_CR1_TRP(value) ((SDRAMC_CR1_TRP_Msk & ((value) << SDRAMC_CR1_TRP_Pos)))
+#define SDRAMC_CR1_TRCD_Pos 20
+#define SDRAMC_CR1_TRCD_Msk (0xfu << SDRAMC_CR1_TRCD_Pos) /**< \brief (SDRAMC_CR1) Row to Column Delay */
+#define SDRAMC_CR1_TRCD(value) ((SDRAMC_CR1_TRCD_Msk & ((value) << SDRAMC_CR1_TRCD_Pos)))
+#define SDRAMC_CR1_TRAS_Pos 24
+#define SDRAMC_CR1_TRAS_Msk (0xfu << SDRAMC_CR1_TRAS_Pos) /**< \brief (SDRAMC_CR1) Active to Precharge Delay */
+#define SDRAMC_CR1_TRAS(value) ((SDRAMC_CR1_TRAS_Msk & ((value) << SDRAMC_CR1_TRAS_Pos)))
+#define SDRAMC_CR1_TXSR_Pos 28
+#define SDRAMC_CR1_TXSR_Msk (0xfu << SDRAMC_CR1_TXSR_Pos) /**< \brief (SDRAMC_CR1) Exit Self Refresh to Active Delay */
+#define SDRAMC_CR1_TXSR(value) ((SDRAMC_CR1_TXSR_Msk & ((value) << SDRAMC_CR1_TXSR_Pos)))
+/* -------- SDRAMC_OCMS : (SDRAMC Offset: 0x2C) SDRAMC OCMS Register 1 -------- */
+#define SDRAMC_OCMS_SDR_SE (0x1u << 0) /**< \brief (SDRAMC_OCMS) SDRAM Memory Controller Scrambling Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_SDRAMC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_smc.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_smc.h
new file mode 100644
index 000000000..eec8fa3ae
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_smc.h
@@ -0,0 +1,484 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SMC_COMPONENT_
+#define _SAM3XA_SMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Static Memory Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_SMC Static Memory Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief SmcCs_number hardware registers */
+typedef struct {
+  RwReg         SMC_SETUP;        /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */
+  RwReg         SMC_PULSE;        /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */
+  RwReg         SMC_CYCLE;        /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */
+  RwReg         SMC_TIMINGS;      /**< \brief (SmcCs_number Offset: 0xC) SMC Timings Register */
+  RwReg         SMC_MODE;         /**< \brief (SmcCs_number Offset: 0x10) SMC Mode Register */
+} SmcCs_number;
+/** \brief Smc hardware registers */
+#define SMCCS_NUMBER_NUMBER 8
+typedef struct {
+  RwReg         SMC_CFG;          /**< \brief (Smc Offset: 0x000) SMC NFC Configuration Register */
+  WoReg         SMC_CTRL;         /**< \brief (Smc Offset: 0x004) SMC NFC Control Register */
+  RoReg         SMC_SR;           /**< \brief (Smc Offset: 0x008) SMC NFC Status Register */
+  WoReg         SMC_IER;          /**< \brief (Smc Offset: 0x00C) SMC NFC Interrupt Enable Register */
+  WoReg         SMC_IDR;          /**< \brief (Smc Offset: 0x010) SMC NFC Interrupt Disable Register */
+  RoReg         SMC_IMR;          /**< \brief (Smc Offset: 0x014) SMC NFC Interrupt Mask Register */
+  RwReg         SMC_ADDR;         /**< \brief (Smc Offset: 0x018) SMC NFC Address Cycle Zero Register */
+  RwReg         SMC_BANK;         /**< \brief (Smc Offset: 0x01C) SMC Bank Address Register */
+  WoReg         SMC_ECC_CTRL;     /**< \brief (Smc Offset: 0x020) SMC ECC Control Register */
+  RwReg         SMC_ECC_MD;       /**< \brief (Smc Offset: 0x024) SMC ECC Mode Register */
+  RoReg         SMC_ECC_SR1;      /**< \brief (Smc Offset: 0x028) SMC ECC Status 1 Register */
+  RoReg         SMC_ECC_PR0;      /**< \brief (Smc Offset: 0x02C) SMC ECC Parity 0 Register */
+  RoReg         SMC_ECC_PR1;      /**< \brief (Smc Offset: 0x030) SMC ECC parity 1 Register */
+  RoReg         SMC_ECC_SR2;      /**< \brief (Smc Offset: 0x034) SMC ECC status 2 Register */
+  RoReg         SMC_ECC_PR2;      /**< \brief (Smc Offset: 0x038) SMC ECC parity 2 Register */
+  RoReg         SMC_ECC_PR3;      /**< \brief (Smc Offset: 0x03C) SMC ECC parity 3 Register */
+  RoReg         SMC_ECC_PR4;      /**< \brief (Smc Offset: 0x040) SMC ECC parity 4 Register */
+  RoReg         SMC_ECC_PR5;      /**< \brief (Smc Offset: 0x044) SMC ECC parity 5 Register */
+  RoReg         SMC_ECC_PR6;      /**< \brief (Smc Offset: 0x048) SMC ECC parity 6 Register */
+  RoReg         SMC_ECC_PR7;      /**< \brief (Smc Offset: 0x04C) SMC ECC parity 7 Register */
+  RoReg         SMC_ECC_PR8;      /**< \brief (Smc Offset: 0x050) SMC ECC parity 8 Register */
+  RoReg         SMC_ECC_PR9;      /**< \brief (Smc Offset: 0x054) SMC ECC parity 9 Register */
+  RoReg         SMC_ECC_PR10;     /**< \brief (Smc Offset: 0x058) SMC ECC parity 10 Register */
+  RoReg         SMC_ECC_PR11;     /**< \brief (Smc Offset: 0x05C) SMC ECC parity 11 Register */
+  RoReg         SMC_ECC_PR12;     /**< \brief (Smc Offset: 0x060) SMC ECC parity 12 Register */
+  RoReg         SMC_ECC_PR13;     /**< \brief (Smc Offset: 0x064) SMC ECC parity 13 Register */
+  RoReg         SMC_ECC_PR14;     /**< \brief (Smc Offset: 0x068) SMC ECC parity 14 Register */
+  RoReg         SMC_ECC_PR15;     /**< \brief (Smc Offset: 0x06C) SMC ECC parity 15 Register */
+  SmcCs_number  SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x70) CS_number = 0 .. 7 */
+  RwReg         SMC_OCMS;         /**< \brief (Smc Offset: 0x110) SMC OCMS Register */
+  WoReg         SMC_KEY1;         /**< \brief (Smc Offset: 0x114) SMC OCMS KEY1 Register */
+  WoReg         SMC_KEY2;         /**< \brief (Smc Offset: 0x118) SMC OCMS KEY2 Register */
+  RoReg         Reserved1[50];
+  WoReg         SMC_WPCR;         /**< \brief (Smc Offset: 0x1E4) Write Protection Control Register */
+  RoReg         SMC_WPSR;         /**< \brief (Smc Offset: 0x1E8) Write Protection Status Register */
+} Smc;
+#endif /* __ASSEMBLY__ */
+/* -------- SMC_CFG : (SMC Offset: 0x000) SMC NFC Configuration Register -------- */
+#define SMC_CFG_PAGESIZE_Pos 0
+#define SMC_CFG_PAGESIZE_Msk (0x3u << SMC_CFG_PAGESIZE_Pos) /**< \brief (SMC_CFG)  */
+#define   SMC_CFG_PAGESIZE_PS512_16 (0x0u << 0) /**< \brief (SMC_CFG) Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes */
+#define   SMC_CFG_PAGESIZE_PS1024_32 (0x1u << 0) /**< \brief (SMC_CFG) Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes */
+#define   SMC_CFG_PAGESIZE_PS2048_64 (0x2u << 0) /**< \brief (SMC_CFG) Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes */
+#define   SMC_CFG_PAGESIZE_PS4096_128 (0x3u << 0) /**< \brief (SMC_CFG) Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes */
+#define SMC_CFG_WSPARE (0x1u << 8) /**< \brief (SMC_CFG) Write Spare Area */
+#define SMC_CFG_RSPARE (0x1u << 9) /**< \brief (SMC_CFG) Read Spare Area */
+#define SMC_CFG_EDGECTRL (0x1u << 12) /**< \brief (SMC_CFG) Rising/Falling Edge Detection Control */
+#define SMC_CFG_RBEDGE (0x1u << 13) /**< \brief (SMC_CFG) Ready/Busy Signal Edge Detection */
+#define SMC_CFG_DTOCYC_Pos 16
+#define SMC_CFG_DTOCYC_Msk (0xfu << SMC_CFG_DTOCYC_Pos) /**< \brief (SMC_CFG) Data Timeout Cycle Number */
+#define SMC_CFG_DTOCYC(value) ((SMC_CFG_DTOCYC_Msk & ((value) << SMC_CFG_DTOCYC_Pos)))
+#define SMC_CFG_DTOMUL_Pos 20
+#define SMC_CFG_DTOMUL_Msk (0x7u << SMC_CFG_DTOMUL_Pos) /**< \brief (SMC_CFG) Data Timeout Multiplier */
+#define   SMC_CFG_DTOMUL_X1 (0x0u << 20) /**< \brief (SMC_CFG) DTOCYC */
+#define   SMC_CFG_DTOMUL_X16 (0x1u << 20) /**< \brief (SMC_CFG) DTOCYC x 16 */
+#define   SMC_CFG_DTOMUL_X128 (0x2u << 20) /**< \brief (SMC_CFG) DTOCYC x 128 */
+#define   SMC_CFG_DTOMUL_X256 (0x3u << 20) /**< \brief (SMC_CFG) DTOCYC x 256 */
+#define   SMC_CFG_DTOMUL_X1024 (0x4u << 20) /**< \brief (SMC_CFG) DTOCYC x 1024 */
+#define   SMC_CFG_DTOMUL_X4096 (0x5u << 20) /**< \brief (SMC_CFG) DTOCYC x 4096 */
+#define   SMC_CFG_DTOMUL_X65536 (0x6u << 20) /**< \brief (SMC_CFG) DTOCYC x 65536 */
+#define   SMC_CFG_DTOMUL_X1048576 (0x7u << 20) /**< \brief (SMC_CFG) DTOCYC x 1048576 */
+/* -------- SMC_CTRL : (SMC Offset: 0x004) SMC NFC Control Register -------- */
+#define SMC_CTRL_NFCEN (0x1u << 0) /**< \brief (SMC_CTRL) NAND Flash Controller Enable */
+#define SMC_CTRL_NFCDIS (0x1u << 1) /**< \brief (SMC_CTRL) NAND Flash Controller Disable */
+/* -------- SMC_SR : (SMC Offset: 0x008) SMC NFC Status Register -------- */
+#define SMC_SR_SMCSTS (0x1u << 0) /**< \brief (SMC_SR) NAND Flash Controller status (this field cannot be reset) */
+#define SMC_SR_RB_RISE (0x1u << 4) /**< \brief (SMC_SR) Selected Ready Busy Rising Edge Detected */
+#define SMC_SR_RB_FALL (0x1u << 5) /**< \brief (SMC_SR) Selected Ready Busy Falling Edge Detected */
+#define SMC_SR_NFCBUSY (0x1u << 8) /**< \brief (SMC_SR) NFC Busy (this field cannot be reset) */
+#define SMC_SR_NFCWR (0x1u << 11) /**< \brief (SMC_SR) NFC Write/Read Operation (this field cannot be reset) */
+#define SMC_SR_NFCSID_Pos 12
+#define SMC_SR_NFCSID_Msk (0x7u << SMC_SR_NFCSID_Pos) /**< \brief (SMC_SR) NFC Chip Select ID (this field cannot be reset) */
+#define SMC_SR_XFRDONE (0x1u << 16) /**< \brief (SMC_SR) NFC Data Transfer Terminated */
+#define SMC_SR_CMDDONE (0x1u << 17) /**< \brief (SMC_SR) Command Done */
+#define SMC_SR_DTOE (0x1u << 20) /**< \brief (SMC_SR) Data Timeout Error */
+#define SMC_SR_UNDEF (0x1u << 21) /**< \brief (SMC_SR) Undefined Area Error */
+#define SMC_SR_AWB (0x1u << 22) /**< \brief (SMC_SR) Accessing While Busy */
+#define SMC_SR_NFCASE (0x1u << 23) /**< \brief (SMC_SR) NFC Access Size Error */
+#define SMC_SR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_SR) Ready/Busy Line 0 Edge Detected */
+/* -------- SMC_IER : (SMC Offset: 0x00C) SMC NFC Interrupt Enable Register -------- */
+#define SMC_IER_RB_RISE (0x1u << 4) /**< \brief (SMC_IER) Ready Busy Rising Edge Detection Interrupt Enable */
+#define SMC_IER_RB_FALL (0x1u << 5) /**< \brief (SMC_IER) Ready Busy Falling Edge Detection Interrupt Enable */
+#define SMC_IER_XFRDONE (0x1u << 16) /**< \brief (SMC_IER) Transfer Done Interrupt Enable */
+#define SMC_IER_CMDDONE (0x1u << 17) /**< \brief (SMC_IER) Command Done Interrupt Enable */
+#define SMC_IER_DTOE (0x1u << 20) /**< \brief (SMC_IER) Data Timeout Error Interrupt Enable */
+#define SMC_IER_UNDEF (0x1u << 21) /**< \brief (SMC_IER) Undefined Area Access Interrupt Enable */
+#define SMC_IER_AWB (0x1u << 22) /**< \brief (SMC_IER) Accessing While Busy Interrupt Enable */
+#define SMC_IER_NFCASE (0x1u << 23) /**< \brief (SMC_IER) NFC Access Size Error Interrupt Enable */
+#define SMC_IER_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IER) Ready/Busy Line 0 Interrupt Enable */
+/* -------- SMC_IDR : (SMC Offset: 0x010) SMC NFC Interrupt Disable Register -------- */
+#define SMC_IDR_RB_RISE (0x1u << 4) /**< \brief (SMC_IDR) Ready Busy Rising Edge Detection Interrupt Disable */
+#define SMC_IDR_RB_FALL (0x1u << 5) /**< \brief (SMC_IDR) Ready Busy Falling Edge Detection Interrupt Disable */
+#define SMC_IDR_XFRDONE (0x1u << 16) /**< \brief (SMC_IDR) Transfer Done Interrupt Disable */
+#define SMC_IDR_CMDDONE (0x1u << 17) /**< \brief (SMC_IDR) Command Done Interrupt Disable */
+#define SMC_IDR_DTOE (0x1u << 20) /**< \brief (SMC_IDR) Data Timeout Error Interrupt Disable */
+#define SMC_IDR_UNDEF (0x1u << 21) /**< \brief (SMC_IDR) Undefined Area Access Interrupt Disable */
+#define SMC_IDR_AWB (0x1u << 22) /**< \brief (SMC_IDR) Accessing While Busy Interrupt Disable */
+#define SMC_IDR_NFCASE (0x1u << 23) /**< \brief (SMC_IDR) NFC Access Size Error Interrupt Disable */
+#define SMC_IDR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IDR) Ready/Busy Line 0 Interrupt Disable */
+/* -------- SMC_IMR : (SMC Offset: 0x014) SMC NFC Interrupt Mask Register -------- */
+#define SMC_IMR_RB_RISE (0x1u << 4) /**< \brief (SMC_IMR) Ready Busy Rising Edge Detection Interrupt Mask */
+#define SMC_IMR_RB_FALL (0x1u << 5) /**< \brief (SMC_IMR) Ready Busy Falling Edge Detection Interrupt Mask */
+#define SMC_IMR_XFRDONE (0x1u << 16) /**< \brief (SMC_IMR) Transfer Done Interrupt Mask */
+#define SMC_IMR_CMDDONE (0x1u << 17) /**< \brief (SMC_IMR) Command Done Interrupt Mask */
+#define SMC_IMR_DTOE (0x1u << 20) /**< \brief (SMC_IMR) Data Timeout Error Interrupt Mask */
+#define SMC_IMR_UNDEF (0x1u << 21) /**< \brief (SMC_IMR) Undefined Area Access Interrupt Mask5 */
+#define SMC_IMR_AWB (0x1u << 22) /**< \brief (SMC_IMR) Accessing While Busy Interrupt Mask */
+#define SMC_IMR_NFCASE (0x1u << 23) /**< \brief (SMC_IMR) NFC Access Size Error Interrupt Mask */
+#define SMC_IMR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IMR) Ready/Busy Line 0 Interrupt Mask */
+/* -------- SMC_ADDR : (SMC Offset: 0x018) SMC NFC Address Cycle Zero Register -------- */
+#define SMC_ADDR_ADDR_CYCLE0_Pos 0
+#define SMC_ADDR_ADDR_CYCLE0_Msk (0xffu << SMC_ADDR_ADDR_CYCLE0_Pos) /**< \brief (SMC_ADDR) NAND Flash Array Address cycle 0 */
+#define SMC_ADDR_ADDR_CYCLE0(value) ((SMC_ADDR_ADDR_CYCLE0_Msk & ((value) << SMC_ADDR_ADDR_CYCLE0_Pos)))
+/* -------- SMC_BANK : (SMC Offset: 0x01C) SMC Bank Address Register -------- */
+#define SMC_BANK_BANK_Pos 0
+#define SMC_BANK_BANK_Msk (0x7u << SMC_BANK_BANK_Pos) /**< \brief (SMC_BANK) Bank Identifier */
+#define SMC_BANK_BANK(value) ((SMC_BANK_BANK_Msk & ((value) << SMC_BANK_BANK_Pos)))
+/* -------- SMC_ECC_CTRL : (SMC Offset: 0x020) SMC ECC Control Register -------- */
+#define SMC_ECC_CTRL_RST (0x1u << 0) /**< \brief (SMC_ECC_CTRL) Reset ECC */
+#define SMC_ECC_CTRL_SWRST (0x1u << 1) /**< \brief (SMC_ECC_CTRL) Software Reset */
+/* -------- SMC_ECC_MD : (SMC Offset: 0x024) SMC ECC Mode Register -------- */
+#define SMC_ECC_MD_ECC_PAGESIZE_Pos 0
+#define SMC_ECC_MD_ECC_PAGESIZE_Msk (0x3u << SMC_ECC_MD_ECC_PAGESIZE_Pos) /**< \brief (SMC_ECC_MD) ECC Page Size */
+#define   SMC_ECC_MD_ECC_PAGESIZE_PS512_16 (0x0u << 0) /**< \brief (SMC_ECC_MD) Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes */
+#define   SMC_ECC_MD_ECC_PAGESIZE_PS1024_32 (0x1u << 0) /**< \brief (SMC_ECC_MD) Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes */
+#define   SMC_ECC_MD_ECC_PAGESIZE_PS2048_64 (0x2u << 0) /**< \brief (SMC_ECC_MD) Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes */
+#define   SMC_ECC_MD_ECC_PAGESIZE_PS4096_128 (0x3u << 0) /**< \brief (SMC_ECC_MD) Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes */
+#define SMC_ECC_MD_TYPCORREC_Pos 4
+#define SMC_ECC_MD_TYPCORREC_Msk (0x3u << SMC_ECC_MD_TYPCORREC_Pos) /**< \brief (SMC_ECC_MD) Type of Correction */
+#define   SMC_ECC_MD_TYPCORREC_CPAGE (0x0u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for a page of 512/1024/2048/4096 Bytes  (for 8 or 16-bit NAND Flash) */
+#define   SMC_ECC_MD_TYPCORREC_C256B (0x1u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for 256 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) */
+#define   SMC_ECC_MD_TYPCORREC_C512B (0x2u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for 512 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) */
+/* -------- SMC_ECC_SR1 : (SMC Offset: 0x028) SMC ECC Status 1 Register -------- */
+#define SMC_ECC_SR1_RECERR0 (0x1u << 0) /**< \brief (SMC_ECC_SR1) Recoverable Error */
+#define SMC_ECC_SR1_ECCERR0_Pos 1
+#define SMC_ECC_SR1_ECCERR0_Msk (0x3u << SMC_ECC_SR1_ECCERR0_Pos) /**< \brief (SMC_ECC_SR1) ECC Error */
+#define SMC_ECC_SR1_RECERR1 (0x1u << 4) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 256th and the 511th bytes or the 512nd and the 1023rd bytes */
+#define SMC_ECC_SR1_ECCERR1 (0x1u << 5) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */
+#define SMC_ECC_SR1_MULERR1 (0x1u << 6) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */
+#define SMC_ECC_SR1_RECERR2 (0x1u << 8) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
+#define SMC_ECC_SR1_ECCERR2 (0x1u << 9) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
+#define SMC_ECC_SR1_MULERR2 (0x1u << 10) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
+#define SMC_ECC_SR1_RECERR3 (0x1u << 12) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
+#define SMC_ECC_SR1_ECCERR3 (0x1u << 13) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
+#define SMC_ECC_SR1_MULERR3 (0x1u << 14) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
+#define SMC_ECC_SR1_RECERR4 (0x1u << 16) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */
+#define SMC_ECC_SR1_ECCERR4_Pos 17
+#define SMC_ECC_SR1_ECCERR4_Msk (0x3u << SMC_ECC_SR1_ECCERR4_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */
+#define SMC_ECC_SR1_RECERR5 (0x1u << 20) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */
+#define SMC_ECC_SR1_ECCERR5_Pos 21
+#define SMC_ECC_SR1_ECCERR5_Msk (0x3u << SMC_ECC_SR1_ECCERR5_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */
+#define SMC_ECC_SR1_RECERR6 (0x1u << 24) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */
+#define SMC_ECC_SR1_ECCERR6_Pos 25
+#define SMC_ECC_SR1_ECCERR6_Msk (0x3u << SMC_ECC_SR1_ECCERR6_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */
+#define SMC_ECC_SR1_RECERR7 (0x1u << 28) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */
+#define SMC_ECC_SR1_ECCERR7_Pos 29
+#define SMC_ECC_SR1_ECCERR7_Msk (0x3u << SMC_ECC_SR1_ECCERR7_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */
+/* -------- SMC_ECC_PR0 : (SMC Offset: 0x02C) SMC ECC Parity 0 Register -------- */
+#define SMC_ECC_PR0_BITADDR_Pos 0
+#define SMC_ECC_PR0_BITADDR_Msk (0xfu << SMC_ECC_PR0_BITADDR_Pos) /**< \brief (SMC_ECC_PR0) Bit Address */
+#define SMC_ECC_PR0_WORDADDR_Pos 4
+#define SMC_ECC_PR0_WORDADDR_Msk (0xfffu << SMC_ECC_PR0_WORDADDR_Pos) /**< \brief (SMC_ECC_PR0) Word Address */
+#define SMC_ECC_PR0_BITADDR_W9BIT_Pos 0
+#define SMC_ECC_PR0_BITADDR_W9BIT_Msk (0x7u << SMC_ECC_PR0_BITADDR_W9BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_WORDADDR_W9BIT_Pos 3
+#define SMC_ECC_PR0_WORDADDR_W9BIT_Msk (0x1ffu << SMC_ECC_PR0_WORDADDR_W9BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_NPARITY_Pos 12
+#define SMC_ECC_PR0_NPARITY_Msk (0xfffu << SMC_ECC_PR0_NPARITY_Pos) /**< \brief (SMC_ECC_PR0) Parity N */
+#define SMC_ECC_PR0_BITADDR_W8BIT_Pos 0
+#define SMC_ECC_PR0_BITADDR_W8BIT_Msk (0x7u << SMC_ECC_PR0_BITADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR0_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR0_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR0_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR0_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Parity N */
+/* -------- SMC_ECC_PR1 : (SMC Offset: 0x030) SMC ECC parity 1 Register -------- */
+#define SMC_ECC_PR1_NPARITY_Pos 0
+#define SMC_ECC_PR1_NPARITY_Msk (0xffffu << SMC_ECC_PR1_NPARITY_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
+#define SMC_ECC_PR1_BITADDR_Pos 0
+#define SMC_ECC_PR1_BITADDR_Msk (0x7u << SMC_ECC_PR1_BITADDR_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR1_WORDADDR_Pos 3
+#define SMC_ECC_PR1_WORDADDR_Msk (0x1ffu << SMC_ECC_PR1_WORDADDR_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR1_NPARITY_W9BIT_Pos 12
+#define SMC_ECC_PR1_NPARITY_W9BIT_Msk (0xfffu << SMC_ECC_PR1_NPARITY_W9BIT_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
+#define SMC_ECC_PR1_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR1_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR1_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR1_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR1_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR1_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
+/* -------- SMC_ECC_SR2 : (SMC Offset: 0x034) SMC ECC status 2 Register -------- */
+#define SMC_ECC_SR2_RECERR8 (0x1u << 0) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2048th and the 2303rd bytes */
+#define SMC_ECC_SR2_ECCERR8_Pos 1
+#define SMC_ECC_SR2_ECCERR8_Msk (0x3u << SMC_ECC_SR2_ECCERR8_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2048th and the 2303rd bytes */
+#define SMC_ECC_SR2_RECERR9 (0x1u << 4) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2304th and the 2559th bytes */
+#define SMC_ECC_SR2_ECCERR9 (0x1u << 5) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2304th and the 2559th bytes */
+#define SMC_ECC_SR2_MULERR9 (0x1u << 6) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2304th and the 2559th bytes */
+#define SMC_ECC_SR2_RECERR10 (0x1u << 8) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2560th and the 2815th bytes */
+#define SMC_ECC_SR2_ECCERR10 (0x1u << 9) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2560th and the 2815th bytes */
+#define SMC_ECC_SR2_MULERR10 (0x1u << 10) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2560th and the 2815th bytes */
+#define SMC_ECC_SR2_RECERR11 (0x1u << 12) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2816th and the 3071st bytes */
+#define SMC_ECC_SR2_ECCERR11 (0x1u << 13) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2816th and the 3071st bytes */
+#define SMC_ECC_SR2_MULERR11 (0x1u << 14) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2816th and the 3071st bytes */
+#define SMC_ECC_SR2_RECERR12 (0x1u << 16) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3072nd and the 3327th bytes */
+#define SMC_ECC_SR2_ECCERR12_Pos 17
+#define SMC_ECC_SR2_ECCERR12_Msk (0x3u << SMC_ECC_SR2_ECCERR12_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3072nd and the 3327th bytes */
+#define SMC_ECC_SR2_RECERR13 (0x1u << 20) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3328th and the 3583rd bytes */
+#define SMC_ECC_SR2_ECCERR13_Pos 21
+#define SMC_ECC_SR2_ECCERR13_Msk (0x3u << SMC_ECC_SR2_ECCERR13_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3328th and the 3583rd bytes */
+#define SMC_ECC_SR2_RECERR14 (0x1u << 24) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3584th and the 3839th bytes */
+#define SMC_ECC_SR2_ECCERR14_Pos 25
+#define SMC_ECC_SR2_ECCERR14_Msk (0x3u << SMC_ECC_SR2_ECCERR14_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3584th and the 3839th bytes */
+#define SMC_ECC_SR2_RECERR15 (0x1u << 28) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3840th and the 4095th bytes */
+#define SMC_ECC_SR2_ECCERR15_Pos 29
+#define SMC_ECC_SR2_ECCERR15_Msk (0x3u << SMC_ECC_SR2_ECCERR15_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3840th and the 4095th bytes */
+/* -------- SMC_ECC_PR2 : (SMC Offset: 0x038) SMC ECC parity 2 Register -------- */
+#define SMC_ECC_PR2_BITADDR_Pos 0
+#define SMC_ECC_PR2_BITADDR_Msk (0x7u << SMC_ECC_PR2_BITADDR_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR2_WORDADDR_Pos 3
+#define SMC_ECC_PR2_WORDADDR_Msk (0x1ffu << SMC_ECC_PR2_WORDADDR_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR2_NPARITY_Pos 12
+#define SMC_ECC_PR2_NPARITY_Msk (0xfffu << SMC_ECC_PR2_NPARITY_Pos) /**< \brief (SMC_ECC_PR2) Parity N */
+#define SMC_ECC_PR2_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR2_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR2_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR2_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR2_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR2_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR2) Parity N */
+/* -------- SMC_ECC_PR3 : (SMC Offset: 0x03C) SMC ECC parity 3 Register -------- */
+#define SMC_ECC_PR3_BITADDR_Pos 0
+#define SMC_ECC_PR3_BITADDR_Msk (0x7u << SMC_ECC_PR3_BITADDR_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR3_WORDADDR_Pos 3
+#define SMC_ECC_PR3_WORDADDR_Msk (0x1ffu << SMC_ECC_PR3_WORDADDR_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR3_NPARITY_Pos 12
+#define SMC_ECC_PR3_NPARITY_Msk (0xfffu << SMC_ECC_PR3_NPARITY_Pos) /**< \brief (SMC_ECC_PR3) Parity N */
+#define SMC_ECC_PR3_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR3_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR3_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR3_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR3_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR3_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR3) Parity N */
+/* -------- SMC_ECC_PR4 : (SMC Offset: 0x040) SMC ECC parity 4 Register -------- */
+#define SMC_ECC_PR4_BITADDR_Pos 0
+#define SMC_ECC_PR4_BITADDR_Msk (0x7u << SMC_ECC_PR4_BITADDR_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR4_WORDADDR_Pos 3
+#define SMC_ECC_PR4_WORDADDR_Msk (0x1ffu << SMC_ECC_PR4_WORDADDR_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR4_NPARITY_Pos 12
+#define SMC_ECC_PR4_NPARITY_Msk (0xfffu << SMC_ECC_PR4_NPARITY_Pos) /**< \brief (SMC_ECC_PR4) Parity N */
+#define SMC_ECC_PR4_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR4_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR4_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR4_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR4_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR4_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR4) Parity N */
+/* -------- SMC_ECC_PR5 : (SMC Offset: 0x044) SMC ECC parity 5 Register -------- */
+#define SMC_ECC_PR5_BITADDR_Pos 0
+#define SMC_ECC_PR5_BITADDR_Msk (0x7u << SMC_ECC_PR5_BITADDR_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR5_WORDADDR_Pos 3
+#define SMC_ECC_PR5_WORDADDR_Msk (0x1ffu << SMC_ECC_PR5_WORDADDR_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR5_NPARITY_Pos 12
+#define SMC_ECC_PR5_NPARITY_Msk (0xfffu << SMC_ECC_PR5_NPARITY_Pos) /**< \brief (SMC_ECC_PR5) Parity N */
+#define SMC_ECC_PR5_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR5_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR5_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR5_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR5_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR5_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR5) Parity N */
+/* -------- SMC_ECC_PR6 : (SMC Offset: 0x048) SMC ECC parity 6 Register -------- */
+#define SMC_ECC_PR6_BITADDR_Pos 0
+#define SMC_ECC_PR6_BITADDR_Msk (0x7u << SMC_ECC_PR6_BITADDR_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR6_WORDADDR_Pos 3
+#define SMC_ECC_PR6_WORDADDR_Msk (0x1ffu << SMC_ECC_PR6_WORDADDR_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR6_NPARITY_Pos 12
+#define SMC_ECC_PR6_NPARITY_Msk (0xfffu << SMC_ECC_PR6_NPARITY_Pos) /**< \brief (SMC_ECC_PR6) Parity N */
+#define SMC_ECC_PR6_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR6_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR6_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR6_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR6_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR6_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR6) Parity N */
+/* -------- SMC_ECC_PR7 : (SMC Offset: 0x04C) SMC ECC parity 7 Register -------- */
+#define SMC_ECC_PR7_BITADDR_Pos 0
+#define SMC_ECC_PR7_BITADDR_Msk (0x7u << SMC_ECC_PR7_BITADDR_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR7_WORDADDR_Pos 3
+#define SMC_ECC_PR7_WORDADDR_Msk (0x1ffu << SMC_ECC_PR7_WORDADDR_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR7_NPARITY_Pos 12
+#define SMC_ECC_PR7_NPARITY_Msk (0xfffu << SMC_ECC_PR7_NPARITY_Pos) /**< \brief (SMC_ECC_PR7) Parity N */
+#define SMC_ECC_PR7_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR7_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR7_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR7_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR7_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR7_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR7) Parity N */
+/* -------- SMC_ECC_PR8 : (SMC Offset: 0x050) SMC ECC parity 8 Register -------- */
+#define SMC_ECC_PR8_BITADDR_Pos 0
+#define SMC_ECC_PR8_BITADDR_Msk (0x7u << SMC_ECC_PR8_BITADDR_Pos) /**< \brief (SMC_ECC_PR8) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR8_WORDADDR_Pos 3
+#define SMC_ECC_PR8_WORDADDR_Msk (0xffu << SMC_ECC_PR8_WORDADDR_Pos) /**< \brief (SMC_ECC_PR8) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR8_NPARITY_Pos 12
+#define SMC_ECC_PR8_NPARITY_Msk (0x7ffu << SMC_ECC_PR8_NPARITY_Pos) /**< \brief (SMC_ECC_PR8) Parity N */
+/* -------- SMC_ECC_PR9 : (SMC Offset: 0x054) SMC ECC parity 9 Register -------- */
+#define SMC_ECC_PR9_BITADDR_Pos 0
+#define SMC_ECC_PR9_BITADDR_Msk (0x7u << SMC_ECC_PR9_BITADDR_Pos) /**< \brief (SMC_ECC_PR9) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR9_WORDADDR_Pos 3
+#define SMC_ECC_PR9_WORDADDR_Msk (0xffu << SMC_ECC_PR9_WORDADDR_Pos) /**< \brief (SMC_ECC_PR9) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR9_NPARITY_Pos 12
+#define SMC_ECC_PR9_NPARITY_Msk (0x7ffu << SMC_ECC_PR9_NPARITY_Pos) /**< \brief (SMC_ECC_PR9) Parity N */
+/* -------- SMC_ECC_PR10 : (SMC Offset: 0x058) SMC ECC parity 10 Register -------- */
+#define SMC_ECC_PR10_BITADDR_Pos 0
+#define SMC_ECC_PR10_BITADDR_Msk (0x7u << SMC_ECC_PR10_BITADDR_Pos) /**< \brief (SMC_ECC_PR10) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR10_WORDADDR_Pos 3
+#define SMC_ECC_PR10_WORDADDR_Msk (0xffu << SMC_ECC_PR10_WORDADDR_Pos) /**< \brief (SMC_ECC_PR10) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR10_NPARITY_Pos 12
+#define SMC_ECC_PR10_NPARITY_Msk (0x7ffu << SMC_ECC_PR10_NPARITY_Pos) /**< \brief (SMC_ECC_PR10) Parity N */
+/* -------- SMC_ECC_PR11 : (SMC Offset: 0x05C) SMC ECC parity 11 Register -------- */
+#define SMC_ECC_PR11_BITADDR_Pos 0
+#define SMC_ECC_PR11_BITADDR_Msk (0x7u << SMC_ECC_PR11_BITADDR_Pos) /**< \brief (SMC_ECC_PR11) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR11_WORDADDR_Pos 3
+#define SMC_ECC_PR11_WORDADDR_Msk (0xffu << SMC_ECC_PR11_WORDADDR_Pos) /**< \brief (SMC_ECC_PR11) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR11_NPARITY_Pos 12
+#define SMC_ECC_PR11_NPARITY_Msk (0x7ffu << SMC_ECC_PR11_NPARITY_Pos) /**< \brief (SMC_ECC_PR11) Parity N */
+/* -------- SMC_ECC_PR12 : (SMC Offset: 0x060) SMC ECC parity 12 Register -------- */
+#define SMC_ECC_PR12_BITADDR_Pos 0
+#define SMC_ECC_PR12_BITADDR_Msk (0x7u << SMC_ECC_PR12_BITADDR_Pos) /**< \brief (SMC_ECC_PR12) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR12_WORDADDR_Pos 3
+#define SMC_ECC_PR12_WORDADDR_Msk (0xffu << SMC_ECC_PR12_WORDADDR_Pos) /**< \brief (SMC_ECC_PR12) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR12_NPARITY_Pos 12
+#define SMC_ECC_PR12_NPARITY_Msk (0x7ffu << SMC_ECC_PR12_NPARITY_Pos) /**< \brief (SMC_ECC_PR12) Parity N */
+/* -------- SMC_ECC_PR13 : (SMC Offset: 0x064) SMC ECC parity 13 Register -------- */
+#define SMC_ECC_PR13_BITADDR_Pos 0
+#define SMC_ECC_PR13_BITADDR_Msk (0x7u << SMC_ECC_PR13_BITADDR_Pos) /**< \brief (SMC_ECC_PR13) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR13_WORDADDR_Pos 3
+#define SMC_ECC_PR13_WORDADDR_Msk (0xffu << SMC_ECC_PR13_WORDADDR_Pos) /**< \brief (SMC_ECC_PR13) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR13_NPARITY_Pos 12
+#define SMC_ECC_PR13_NPARITY_Msk (0x7ffu << SMC_ECC_PR13_NPARITY_Pos) /**< \brief (SMC_ECC_PR13) Parity N */
+/* -------- SMC_ECC_PR14 : (SMC Offset: 0x068) SMC ECC parity 14 Register -------- */
+#define SMC_ECC_PR14_BITADDR_Pos 0
+#define SMC_ECC_PR14_BITADDR_Msk (0x7u << SMC_ECC_PR14_BITADDR_Pos) /**< \brief (SMC_ECC_PR14) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR14_WORDADDR_Pos 3
+#define SMC_ECC_PR14_WORDADDR_Msk (0xffu << SMC_ECC_PR14_WORDADDR_Pos) /**< \brief (SMC_ECC_PR14) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR14_NPARITY_Pos 12
+#define SMC_ECC_PR14_NPARITY_Msk (0x7ffu << SMC_ECC_PR14_NPARITY_Pos) /**< \brief (SMC_ECC_PR14) Parity N */
+/* -------- SMC_ECC_PR15 : (SMC Offset: 0x06C) SMC ECC parity 15 Register -------- */
+#define SMC_ECC_PR15_BITADDR_Pos 0
+#define SMC_ECC_PR15_BITADDR_Msk (0x7u << SMC_ECC_PR15_BITADDR_Pos) /**< \brief (SMC_ECC_PR15) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR15_WORDADDR_Pos 3
+#define SMC_ECC_PR15_WORDADDR_Msk (0xffu << SMC_ECC_PR15_WORDADDR_Pos) /**< \brief (SMC_ECC_PR15) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR15_NPARITY_Pos 12
+#define SMC_ECC_PR15_NPARITY_Msk (0x7ffu << SMC_ECC_PR15_NPARITY_Pos) /**< \brief (SMC_ECC_PR15) Parity N */
+/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */
+#define SMC_SETUP_NWE_SETUP_Pos 0
+#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */
+#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))
+#define SMC_SETUP_NCS_WR_SETUP_Pos 8
+#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in Write Access */
+#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))
+#define SMC_SETUP_NRD_SETUP_Pos 16
+#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */
+#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))
+#define SMC_SETUP_NCS_RD_SETUP_Pos 24
+#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in Read Access */
+#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))
+/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */
+#define SMC_PULSE_NWE_PULSE_Pos 0
+#define SMC_PULSE_NWE_PULSE_Msk (0x3fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */
+#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))
+#define SMC_PULSE_NCS_WR_PULSE_Pos 8
+#define SMC_PULSE_NCS_WR_PULSE_Msk (0x3fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */
+#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))
+#define SMC_PULSE_NRD_PULSE_Pos 16
+#define SMC_PULSE_NRD_PULSE_Msk (0x3fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */
+#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))
+#define SMC_PULSE_NCS_RD_PULSE_Pos 24
+#define SMC_PULSE_NCS_RD_PULSE_Msk (0x3fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */
+#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))
+/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */
+#define SMC_CYCLE_NWE_CYCLE_Pos 0
+#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */
+#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))
+#define SMC_CYCLE_NRD_CYCLE_Pos 16
+#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */
+#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))
+/* -------- SMC_TIMINGS : (SMC Offset: N/A) SMC Timings Register -------- */
+#define SMC_TIMINGS_TCLR_Pos 0
+#define SMC_TIMINGS_TCLR_Msk (0xfu << SMC_TIMINGS_TCLR_Pos) /**< \brief (SMC_TIMINGS) CLE to REN Low Delay */
+#define SMC_TIMINGS_TCLR(value) ((SMC_TIMINGS_TCLR_Msk & ((value) << SMC_TIMINGS_TCLR_Pos)))
+#define SMC_TIMINGS_TADL_Pos 4
+#define SMC_TIMINGS_TADL_Msk (0xfu << SMC_TIMINGS_TADL_Pos) /**< \brief (SMC_TIMINGS) ALE to Data Start */
+#define SMC_TIMINGS_TADL(value) ((SMC_TIMINGS_TADL_Msk & ((value) << SMC_TIMINGS_TADL_Pos)))
+#define SMC_TIMINGS_TAR_Pos 8
+#define SMC_TIMINGS_TAR_Msk (0xfu << SMC_TIMINGS_TAR_Pos) /**< \brief (SMC_TIMINGS) ALE to REN Low Delay */
+#define SMC_TIMINGS_TAR(value) ((SMC_TIMINGS_TAR_Msk & ((value) << SMC_TIMINGS_TAR_Pos)))
+#define SMC_TIMINGS_OCMS (0x1u << 12) /**< \brief (SMC_TIMINGS) Off Chip Memory Scrambling Enable */
+#define SMC_TIMINGS_TRR_Pos 16
+#define SMC_TIMINGS_TRR_Msk (0xfu << SMC_TIMINGS_TRR_Pos) /**< \brief (SMC_TIMINGS) Ready to REN Low Delay */
+#define SMC_TIMINGS_TRR(value) ((SMC_TIMINGS_TRR_Msk & ((value) << SMC_TIMINGS_TRR_Pos)))
+#define SMC_TIMINGS_TWB_Pos 24
+#define SMC_TIMINGS_TWB_Msk (0xfu << SMC_TIMINGS_TWB_Pos) /**< \brief (SMC_TIMINGS) WEN High to REN to Busy */
+#define SMC_TIMINGS_TWB(value) ((SMC_TIMINGS_TWB_Msk & ((value) << SMC_TIMINGS_TWB_Pos)))
+#define SMC_TIMINGS_RBNSEL_Pos 28
+#define SMC_TIMINGS_RBNSEL_Msk (0x7u << SMC_TIMINGS_RBNSEL_Pos) /**< \brief (SMC_TIMINGS) Ready/Busy Line Selection */
+#define SMC_TIMINGS_RBNSEL(value) ((SMC_TIMINGS_RBNSEL_Msk & ((value) << SMC_TIMINGS_RBNSEL_Pos)))
+#define SMC_TIMINGS_NFSEL (0x1u << 31) /**< \brief (SMC_TIMINGS) NAND Flash Selection */
+/* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */
+#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE)  */
+#define   SMC_MODE_READ_MODE_NCS_CTRL (0x0u << 0) /**< \brief (SMC_MODE) The Read operation is controlled by the NCS signal. */
+#define   SMC_MODE_READ_MODE_NRD_CTRL (0x1u << 0) /**< \brief (SMC_MODE) The Read operation is controlled by the NRD signal. */
+#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE)  */
+#define   SMC_MODE_WRITE_MODE_NCS_CTRL (0x0u << 1) /**< \brief (SMC_MODE) The Write operation is controller by the NCS signal. */
+#define   SMC_MODE_WRITE_MODE_NWE_CTRL (0x1u << 1) /**< \brief (SMC_MODE) The Write operation is controlled by the NWE signal. */
+#define SMC_MODE_EXNW_MODE_Pos 4
+#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */
+#define   SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */
+#define   SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */
+#define   SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */
+#define SMC_MODE_BAT (0x1u << 8) /**< \brief (SMC_MODE) Byte Access Type */
+#define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */
+#define   SMC_MODE_DBW_BIT_8 (0x0u << 12) /**< \brief (SMC_MODE) 8-bit bus */
+#define   SMC_MODE_DBW_BIT_16 (0x1u << 12) /**< \brief (SMC_MODE) 16-bit bus */
+#define SMC_MODE_TDF_CYCLES_Pos 16
+#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */
+#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))
+#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */
+/* -------- SMC_OCMS : (SMC Offset: 0x110) SMC OCMS Register -------- */
+#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */
+#define SMC_OCMS_SRSE (0x1u << 1) /**< \brief (SMC_OCMS) SRAM Scrambling Enable */
+/* -------- SMC_KEY1 : (SMC Offset: 0x114) SMC OCMS KEY1 Register -------- */
+#define SMC_KEY1_KEY1_Pos 0
+#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */
+#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))
+/* -------- SMC_KEY2 : (SMC Offset: 0x118) SMC OCMS KEY2 Register -------- */
+#define SMC_KEY2_KEY2_Pos 0
+#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */
+#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))
+/* -------- SMC_WPCR : (SMC Offset: 0x1E4) Write Protection Control Register -------- */
+#define SMC_WPCR_WP_EN (0x1u << 0) /**< \brief (SMC_WPCR) Write Protection Enable */
+#define SMC_WPCR_WP_KEY_Pos 8
+#define SMC_WPCR_WP_KEY_Msk (0xffffffu << SMC_WPCR_WP_KEY_Pos) /**< \brief (SMC_WPCR) Write Protection KEY password */
+#define SMC_WPCR_WP_KEY(value) ((SMC_WPCR_WP_KEY_Msk & ((value) << SMC_WPCR_WP_KEY_Pos)))
+/* -------- SMC_WPSR : (SMC Offset: 0x1E8) Write Protection Status Register -------- */
+#define SMC_WPSR_WP_VS_Pos 0
+#define SMC_WPSR_WP_VS_Msk (0xfu << SMC_WPSR_WP_VS_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Status */
+#define SMC_WPSR_WP_VSRC_Pos 8
+#define SMC_WPSR_WP_VSRC_Msk (0xffffu << SMC_WPSR_WP_VSRC_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_SMC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_spi.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_spi.h
new file mode 100644
index 000000000..eaae250a9
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_spi.h
@@ -0,0 +1,160 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SPI_COMPONENT_
+#define _SAM3XA_SPI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Serial Peripheral Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_SPI Serial Peripheral Interface */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Spi hardware registers */
+typedef struct {
+  WoReg SPI_CR;        /**< \brief (Spi Offset: 0x00) Control Register */
+  RwReg SPI_MR;        /**< \brief (Spi Offset: 0x04) Mode Register */
+  RoReg SPI_RDR;       /**< \brief (Spi Offset: 0x08) Receive Data Register */
+  WoReg SPI_TDR;       /**< \brief (Spi Offset: 0x0C) Transmit Data Register */
+  RoReg SPI_SR;        /**< \brief (Spi Offset: 0x10) Status Register */
+  WoReg SPI_IER;       /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */
+  WoReg SPI_IDR;       /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */
+  RoReg SPI_IMR;       /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */
+  RoReg Reserved1[4];
+  RwReg SPI_CSR[4];    /**< \brief (Spi Offset: 0x30) Chip Select Register */
+  RoReg Reserved2[41];
+  RwReg SPI_WPMR;      /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */
+  RoReg SPI_WPSR;      /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */
+} Spi;
+#endif /* __ASSEMBLY__ */
+/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
+#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */
+#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */
+#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */
+#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */
+/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
+#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */
+#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */
+#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */
+#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */
+#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */
+#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */
+#define SPI_MR_PCS_Pos 16
+#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */
+#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
+#define SPI_MR_DLYBCS_Pos 24
+#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */
+#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
+/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
+#define SPI_RDR_RD_Pos 0
+#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */
+#define SPI_RDR_PCS_Pos 16
+#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */
+/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
+#define SPI_TDR_TD_Pos 0
+#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */
+#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
+#define SPI_TDR_PCS_Pos 16
+#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */
+#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
+#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
+#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */
+#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */
+#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */
+#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */
+#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */
+#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */
+#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */
+#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
+#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */
+#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */
+#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */
+#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */
+#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */
+#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */
+#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */
+#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */
+#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */
+#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */
+#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */
+#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */
+#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */
+/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
+#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */
+#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */
+#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */
+#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */
+#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */
+#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */
+#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */
+/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
+#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */
+#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */
+#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_BITS_Pos 4
+#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */
+#define   SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */
+#define   SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */
+#define   SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */
+#define   SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */
+#define   SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */
+#define   SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */
+#define   SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */
+#define   SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */
+#define   SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */
+#define SPI_CSR_SCBR_Pos 8
+#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */
+#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
+#define SPI_CSR_DLYBS_Pos 16
+#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */
+#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
+#define SPI_CSR_DLYBCT_Pos 24
+#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */
+#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
+/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */
+#define SPI_WPMR_SPIWPEN (0x1u << 0) /**< \brief (SPI_WPMR) SPI Write Protection Enable */
+#define SPI_WPMR_SPIWPKEY_Pos 8
+#define SPI_WPMR_SPIWPKEY_Msk (0xffffffu << SPI_WPMR_SPIWPKEY_Pos) /**< \brief (SPI_WPMR) SPI Write Protection Key Password */
+#define SPI_WPMR_SPIWPKEY(value) ((SPI_WPMR_SPIWPKEY_Msk & ((value) << SPI_WPMR_SPIWPKEY_Pos)))
+/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
+#define SPI_WPSR_SPIWPVS_Pos 0
+#define SPI_WPSR_SPIWPVS_Msk (0x7u << SPI_WPSR_SPIWPVS_Pos) /**< \brief (SPI_WPSR) SPI Write Protection Violation Status */
+#define SPI_WPSR_SPIWPVSRC_Pos 8
+#define SPI_WPSR_SPIWPVSRC_Msk (0xffu << SPI_WPSR_SPIWPVSRC_Pos) /**< \brief (SPI_WPSR) SPI Write Protection Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_SPI_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_ssc.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_ssc.h
new file mode 100644
index 000000000..ba96be3c0
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_ssc.h
@@ -0,0 +1,270 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SSC_COMPONENT_
+#define _SAM3XA_SSC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Synchronous Serial Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_SSC Synchronous Serial Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Ssc hardware registers */
+typedef struct {
+  WoReg SSC_CR;        /**< \brief (Ssc Offset: 0x0) Control Register */
+  RwReg SSC_CMR;       /**< \brief (Ssc Offset: 0x4) Clock Mode Register */
+  RoReg Reserved1[2];
+  RwReg SSC_RCMR;      /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */
+  RwReg SSC_RFMR;      /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */
+  RwReg SSC_TCMR;      /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */
+  RwReg SSC_TFMR;      /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */
+  RoReg SSC_RHR;       /**< \brief (Ssc Offset: 0x20) Receive Holding Register */
+  WoReg SSC_THR;       /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */
+  RoReg Reserved2[2];
+  RoReg SSC_RSHR;      /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */
+  RwReg SSC_TSHR;      /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */
+  RwReg SSC_RC0R;      /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */
+  RwReg SSC_RC1R;      /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */
+  RoReg SSC_SR;        /**< \brief (Ssc Offset: 0x40) Status Register */
+  WoReg SSC_IER;       /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */
+  WoReg SSC_IDR;       /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */
+  RoReg SSC_IMR;       /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */
+  RoReg Reserved3[37];
+  RwReg SSC_WPMR;      /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */
+  RoReg SSC_WPSR;      /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */
+} Ssc;
+#endif /* __ASSEMBLY__ */
+/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */
+#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */
+#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */
+#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */
+#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */
+#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */
+/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */
+#define SSC_CMR_DIV_Pos 0
+#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */
+#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))
+/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */
+#define SSC_RCMR_CKS_Pos 0
+#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */
+#define   SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */
+#define   SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */
+#define   SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */
+#define SSC_RCMR_CKO_Pos 2
+#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */
+#define   SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None */
+#define   SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock */
+#define   SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
+#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */
+#define SSC_RCMR_CKG_Pos 6
+#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */
+#define   SSC_RCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_RCMR) None */
+#define   SSC_RCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_RCMR) Continuous Receive Clock */
+#define   SSC_RCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
+#define SSC_RCMR_START_Pos 8
+#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */
+#define   SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
+#define   SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */
+#define   SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */
+#define   SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */
+#define   SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */
+#define   SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */
+#define   SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */
+#define   SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */
+#define   SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */
+#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */
+#define SSC_RCMR_STTDLY_Pos 16
+#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */
+#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))
+#define SSC_RCMR_PERIOD_Pos 24
+#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */
+#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))
+/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */
+#define SSC_RFMR_DATLEN_Pos 0
+#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */
+#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))
+#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */
+#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */
+#define SSC_RFMR_DATNB_Pos 8
+#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */
+#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))
+#define SSC_RFMR_FSLEN_Pos 16
+#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */
+#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))
+#define SSC_RFMR_FSOS_Pos 20
+#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */
+#define   SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None */
+#define   SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse */
+#define   SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse */
+#define   SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer */
+#define   SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer */
+#define   SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer */
+#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */
+#define   SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */
+#define   SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */
+#define SSC_RFMR_FSLEN_EXT_Pos 28
+#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */
+#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))
+/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */
+#define SSC_TCMR_CKS_Pos 0
+#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */
+#define   SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */
+#define   SSC_TCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_TCMR) TK Clock signal */
+#define   SSC_TCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_TCMR) RK pin */
+#define SSC_TCMR_CKO_Pos 2
+#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */
+#define   SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None */
+#define   SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Receive Clock */
+#define   SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers */
+#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */
+#define SSC_TCMR_CKG_Pos 6
+#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */
+#define   SSC_TCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_TCMR) None */
+#define   SSC_TCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */
+#define   SSC_TCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */
+#define SSC_TCMR_START_Pos 8
+#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */
+#define   SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. */
+#define   SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */
+#define   SSC_TCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */
+#define   SSC_TCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */
+#define   SSC_TCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */
+#define   SSC_TCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */
+#define   SSC_TCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */
+#define   SSC_TCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */
+#define   SSC_TCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_TCMR) Compare 0 */
+#define SSC_TCMR_STTDLY_Pos 16
+#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */
+#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))
+#define SSC_TCMR_PERIOD_Pos 24
+#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */
+#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))
+/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */
+#define SSC_TFMR_DATLEN_Pos 0
+#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */
+#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))
+#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */
+#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */
+#define SSC_TFMR_DATNB_Pos 8
+#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per frame */
+#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))
+#define SSC_TFMR_FSLEN_Pos 16
+#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */
+#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))
+#define SSC_TFMR_FSOS_Pos 20
+#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */
+#define   SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None */
+#define   SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse */
+#define   SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse */
+#define   SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */
+#define   SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */
+#define   SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */
+#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */
+#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */
+#define   SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */
+#define   SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */
+#define SSC_TFMR_FSLEN_EXT_Pos 28
+#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */
+#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))
+/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */
+#define SSC_RHR_RDAT_Pos 0
+#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */
+/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */
+#define SSC_THR_TDAT_Pos 0
+#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */
+#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))
+/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */
+#define SSC_RSHR_RSDAT_Pos 0
+#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */
+/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */
+#define SSC_TSHR_TSDAT_Pos 0
+#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */
+#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))
+/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */
+#define SSC_RC0R_CP0_Pos 0
+#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */
+#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))
+/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */
+#define SSC_RC1R_CP1_Pos 0
+#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */
+#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))
+/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */
+#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */
+#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */
+#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */
+#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */
+#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */
+#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */
+#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */
+#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */
+#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */
+#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */
+/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */
+#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */
+#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */
+#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */
+#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */
+#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */
+#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */
+#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */
+#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */
+/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */
+#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */
+#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */
+#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */
+#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */
+#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */
+#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */
+#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */
+#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */
+/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */
+#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */
+#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */
+#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */
+#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */
+#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */
+#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */
+#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */
+#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */
+/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */
+#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protect Enable */
+#define SSC_WPMR_WPKEY_Pos 8
+#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protect KEY */
+#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)))
+/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */
+#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */
+#define SSC_WPSR_WPVSRC_Pos 8
+#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_SSC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_supc.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_supc.h
new file mode 100644
index 000000000..36af1123c
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_supc.h
@@ -0,0 +1,312 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SUPC_COMPONENT_
+#define _SAM3XA_SUPC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Supply Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_SUPC Supply Controller */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Supc hardware registers */
+typedef struct {
+  WoReg SUPC_CR;   /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */
+  RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */
+  RwReg SUPC_MR;   /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */
+  RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */
+  RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */
+  RoReg SUPC_SR;   /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */
+} Supc;
+#endif /* __ASSEMBLY__ */
+/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */
+#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */
+#define   SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */
+#define   SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */
+#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */
+#define   SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */
+#define   SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */
+#define SUPC_CR_KEY_Pos 24
+#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */
+#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))
+/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */
+#define SUPC_SMMR_SMTH_Pos 0
+#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */
+#define   SUPC_SMMR_SMTH_1_9V (0x0u << 0) /**< \brief (SUPC_SMMR) 1.9 V */
+#define   SUPC_SMMR_SMTH_2_0V (0x1u << 0) /**< \brief (SUPC_SMMR) 2.0 V */
+#define   SUPC_SMMR_SMTH_2_1V (0x2u << 0) /**< \brief (SUPC_SMMR) 2.1 V */
+#define   SUPC_SMMR_SMTH_2_2V (0x3u << 0) /**< \brief (SUPC_SMMR) 2.2 V */
+#define   SUPC_SMMR_SMTH_2_3V (0x4u << 0) /**< \brief (SUPC_SMMR) 2.3 V */
+#define   SUPC_SMMR_SMTH_2_4V (0x5u << 0) /**< \brief (SUPC_SMMR) 2.4 V */
+#define   SUPC_SMMR_SMTH_2_5V (0x6u << 0) /**< \brief (SUPC_SMMR) 2.5 V */
+#define   SUPC_SMMR_SMTH_2_6V (0x7u << 0) /**< \brief (SUPC_SMMR) 2.6 V */
+#define   SUPC_SMMR_SMTH_2_7V (0x8u << 0) /**< \brief (SUPC_SMMR) 2.7 V */
+#define   SUPC_SMMR_SMTH_2_8V (0x9u << 0) /**< \brief (SUPC_SMMR) 2.8 V */
+#define   SUPC_SMMR_SMTH_2_9V (0xAu << 0) /**< \brief (SUPC_SMMR) 2.9 V */
+#define   SUPC_SMMR_SMTH_3_0V (0xBu << 0) /**< \brief (SUPC_SMMR) 3.0 V */
+#define   SUPC_SMMR_SMTH_3_1V (0xCu << 0) /**< \brief (SUPC_SMMR) 3.1 V */
+#define   SUPC_SMMR_SMTH_3_2V (0xDu << 0) /**< \brief (SUPC_SMMR) 3.2 V */
+#define   SUPC_SMMR_SMTH_3_3V (0xEu << 0) /**< \brief (SUPC_SMMR) 3.3 V */
+#define   SUPC_SMMR_SMTH_3_4V (0xFu << 0) /**< \brief (SUPC_SMMR) 3.4 V */
+#define SUPC_SMMR_SMSMPL_Pos 8
+#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */
+#define   SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */
+#define   SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */
+#define   SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */
+#define   SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */
+#define   SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */
+#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */
+#define   SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */
+#define   SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */
+#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */
+#define   SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */
+#define   SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */
+/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */
+#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */
+#define   SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */
+#define   SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */
+#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */
+#define   SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */
+#define   SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */
+#define SUPC_MR_VDDIORDYONREG (0x1u << 14) /**< \brief (SUPC_MR)  */
+#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */
+#define   SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */
+#define   SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */
+#define SUPC_MR_KEY_Pos 24
+#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */
+#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))
+/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */
+#define SUPC_WUMR_FWUPEN (0x1u << 0) /**< \brief (SUPC_WUMR) Force Wake Up Enable */
+#define   SUPC_WUMR_FWUPEN_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin has no wake up effect. */
+#define   SUPC_WUMR_FWUPEN_ENABLE (0x1u << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin low forces the wake up of the core power supply. */
+#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */
+#define   SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */
+#define   SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */
+#define   SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */
+#define   SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */
+#define   SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */
+#define   SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_FWUPDBC_Pos 8
+#define SUPC_WUMR_FWUPDBC_Msk (0x7u << SUPC_WUMR_FWUPDBC_Pos) /**< \brief (SUPC_WUMR) Force Wake Up Debouncer Period */
+#define   SUPC_WUMR_FWUPDBC_IMMEDIATE (0x0u << 8) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
+#define   SUPC_WUMR_FWUPDBC_3_SCLK (0x1u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 3 SLCK periods */
+#define   SUPC_WUMR_FWUPDBC_32_SCLK (0x2u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32 SLCK periods */
+#define   SUPC_WUMR_FWUPDBC_512_SCLK (0x3u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 512 SLCK periods */
+#define   SUPC_WUMR_FWUPDBC_4096_SCLK (0x4u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 4,096 SLCK periods */
+#define   SUPC_WUMR_FWUPDBC_32768_SCLK (0x5u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32,768 SLCK periods */
+#define SUPC_WUMR_WKUPDBC_Pos 12
+#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer Period */
+#define   SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
+#define   SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */
+/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */
+#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */
+#define   SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */
+#define   SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */
+#define   SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */
+#define   SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */
+#define   SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */
+#define   SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */
+#define   SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */
+#define   SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */
+#define   SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */
+#define   SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */
+#define   SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */
+#define   SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */
+#define   SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */
+#define   SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */
+#define   SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */
+#define   SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */
+#define   SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */
+#define   SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */
+#define   SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */
+#define   SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */
+#define   SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */
+#define   SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */
+#define   SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */
+#define   SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */
+#define   SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */
+#define   SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */
+#define   SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */
+#define   SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */
+#define   SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */
+#define   SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */
+#define   SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */
+#define   SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */
+#define SUPC_SR_FWUPS (0x1u << 0) /**< \brief (SUPC_SR) FWUP Wake Up Status */
+#define   SUPC_SR_FWUPS_NO (0x0u << 0) /**< \brief (SUPC_SR) no wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_FWUPS_PRESENT (0x1u << 0) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */
+#define   SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */
+#define   SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */
+#define   SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */
+#define   SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */
+#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */
+#define   SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define   SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */
+#define   SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */
+#define   SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */
+#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */
+#define   SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI higher than its threshold at its last measurement. */
+#define   SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI lower than its threshold at its last measurement. */
+#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */
+#define   SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */
+#define   SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */
+#define SUPC_SR_FWUPIS (0x1u << 12) /**< \brief (SUPC_SR) FWUP Input Status */
+#define   SUPC_SR_FWUPIS_LOW (0x0u << 12) /**< \brief (SUPC_SR) FWUP input is tied low. */
+#define   SUPC_SR_FWUPIS_HIGH (0x1u << 12) /**< \brief (SUPC_SR) FWUP input is tied high. */
+#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */
+#define   SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */
+#define   SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */
+#define   SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */
+#define   SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */
+#define   SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */
+#define   SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */
+#define   SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */
+#define   SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */
+#define   SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */
+#define   SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */
+#define   SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */
+#define   SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */
+#define   SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */
+#define   SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */
+#define   SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */
+#define   SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_SUPC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_tc.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_tc.h
new file mode 100644
index 000000000..88324bb18
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_tc.h
@@ -0,0 +1,303 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_TC_COMPONENT_
+#define _SAM3XA_TC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Timer Counter */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_TC Timer Counter */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief TcChannel hardware registers */
+typedef struct {
+  RwReg      TC_CCR;        /**< \brief (TcChannel Offset: 0x0) Channel Control Register */
+  RwReg      TC_CMR;        /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */
+  RwReg      TC_SMMR;       /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */
+  RoReg      Reserved1[1];
+  RwReg      TC_CV;         /**< \brief (TcChannel Offset: 0x10) Counter Value */
+  RwReg      TC_RA;         /**< \brief (TcChannel Offset: 0x14) Register A */
+  RwReg      TC_RB;         /**< \brief (TcChannel Offset: 0x18) Register B */
+  RwReg      TC_RC;         /**< \brief (TcChannel Offset: 0x1C) Register C */
+  RwReg      TC_SR;         /**< \brief (TcChannel Offset: 0x20) Status Register */
+  RwReg      TC_IER;        /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
+  RwReg      TC_IDR;        /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
+  RwReg      TC_IMR;        /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */
+  RoReg      Reserved2[4];
+} TcChannel;
+/** \brief Tc hardware registers */
+#define TCCHANNEL_NUMBER 3
+typedef struct {
+  TcChannel  TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */
+  WoReg      TC_BCR;        /**< \brief (Tc Offset: 0xC0) Block Control Register */
+  RwReg      TC_BMR;        /**< \brief (Tc Offset: 0xC4) Block Mode Register */
+  WoReg      TC_QIER;       /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */
+  WoReg      TC_QIDR;       /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */
+  RoReg      TC_QIMR;       /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */
+  RoReg      TC_QISR;       /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */
+  RwReg      TC_FMR;        /**< \brief (Tc Offset: 0xD8) Fault Mode Register */
+  RoReg      Reserved1[2];
+  RwReg      TC_WPMR;       /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */
+} Tc;
+#endif /* __ASSEMBLY__ */
+/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */
+#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */
+#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */
+#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */
+/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */
+#define TC_CMR_TCCLKS_Pos 0
+#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */
+#define   TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */
+#define   TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */
+#define   TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */
+#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */
+#define TC_CMR_BURST_Pos 4
+#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */
+#define   TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define   TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */
+#define   TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */
+#define   TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */
+#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */
+#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */
+#define TC_CMR_ETRGEDG_Pos 8
+#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */
+#define   TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define   TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define   TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define   TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */
+#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */
+#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */
+#define TC_CMR_LDRA_Pos 16
+#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */
+#define   TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define   TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define   TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define   TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_LDRB_Pos 18
+#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */
+#define   TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define   TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define   TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define   TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */
+#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */
+#define TC_CMR_EEVTEDG_Pos 8
+#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */
+#define   TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */
+#define   TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define   TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define   TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_EEVT_Pos 10
+#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */
+#define   TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */
+#define   TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */
+#define   TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */
+#define   TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */
+#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */
+#define TC_CMR_WAVSEL_Pos 13
+#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */
+#define   TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */
+#define TC_CMR_ACPA_Pos 16
+#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */
+#define   TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ACPC_Pos 18
+#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */
+#define   TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_AEEVT_Pos 20
+#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */
+#define   TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */
+#define   TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ASWTRG_Pos 22
+#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */
+#define   TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPB_Pos 24
+#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */
+#define   TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPC_Pos 26
+#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */
+#define   TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BEEVT_Pos 28
+#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */
+#define   TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BSWTRG_Pos 30
+#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */
+#define   TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */
+/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */
+#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */
+#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) DOWN Count */
+/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */
+#define TC_CV_CV_Pos 0
+#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */
+/* -------- TC_RA : (TC Offset: N/A) Register A -------- */
+#define TC_RA_RA_Pos 0
+#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */
+#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))
+/* -------- TC_RB : (TC Offset: N/A) Register B -------- */
+#define TC_RB_RB_Pos 0
+#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */
+#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))
+/* -------- TC_RC : (TC Offset: N/A) Register C -------- */
+#define TC_RC_RC_Pos 0
+#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */
+#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))
+/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */
+#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */
+#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */
+#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */
+#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */
+#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */
+#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */
+#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */
+#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */
+#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */
+#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */
+#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */
+/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */
+#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */
+#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */
+#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */
+#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */
+#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */
+#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */
+#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */
+#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */
+/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */
+#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */
+#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */
+#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */
+#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */
+#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */
+#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */
+#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */
+#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */
+/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */
+#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */
+#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */
+#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */
+#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */
+#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */
+#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */
+#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */
+#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */
+/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
+#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */
+/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
+#define TC_BMR_TC0XC0S_Pos 0
+#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */
+#define   TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */
+#define   TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */
+#define   TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */
+#define TC_BMR_TC1XC1S_Pos 2
+#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */
+#define   TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */
+#define   TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */
+#define   TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */
+#define TC_BMR_TC2XC2S_Pos 4
+#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */
+#define   TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */
+#define   TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */
+#define   TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */
+#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */
+#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */
+#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */
+#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */
+#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */
+#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */
+#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */
+#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */
+#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */
+#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */
+#define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR)  */
+#define TC_BMR_MAXFILT_Pos 20
+#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */
+#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))
+/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */
+#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */
+#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */
+#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */
+/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */
+#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */
+#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */
+#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */
+/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */
+#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */
+#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */
+#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */
+/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */
+#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */
+#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */
+#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */
+#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */
+/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */
+#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */
+#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */
+/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */
+#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protect Enable */
+#define TC_WPMR_WPKEY_Pos 8
+#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protect KEY */
+#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3XA_TC_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_trng.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_trng.h
new file mode 100644
index 000000000..4deac7f75
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_trng.h
@@ -0,0 +1,72 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_TRNG_COMPONENT_
+#define _SAM3XA_TRNG_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR True Random Number Generator */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_TRNG True Random Number Generator */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Trng hardware registers */
+typedef struct {
+  WoReg TRNG_CR;       /**< \brief (Trng Offset: 0x00) Control Register */
+  RoReg Reserved1[3];
+  WoReg TRNG_IER;      /**< \brief (Trng Offset: 0x10) Interrupt Enable Register */
+  WoReg TRNG_IDR;      /**< \brief (Trng Offset: 0x14) Interrupt Disable Register */
+  RoReg TRNG_IMR;      /**< \brief (Trng Offset: 0x18) Interrupt Mask Register */
+  RoReg TRNG_ISR;      /**< \brief (Trng Offset: 0x1C) Interrupt Status Register */
+  RoReg Reserved2[12];
+  RoReg TRNG_ODATA;    /**< \brief (Trng Offset: 0x50) Output Data Register */
+} Trng;
+#endif /* __ASSEMBLY__ */
+/* -------- TRNG_CR : (TRNG Offset: 0x00) Control Register -------- */
+#define TRNG_CR_ENABLE (0x1u << 0) /**< \brief (TRNG_CR) Enables the TRNG to provide random values */
+#define TRNG_CR_KEY_Pos 8
+#define TRNG_CR_KEY_Msk (0xffffffu << TRNG_CR_KEY_Pos) /**< \brief (TRNG_CR) Security Key */
+#define TRNG_CR_KEY(value) ((TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos)))
+/* -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- */
+#define TRNG_IER_DATRDY (0x1u << 0) /**< \brief (TRNG_IER) Data Ready Interrupt Enable */
+/* -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- */
+#define TRNG_IDR_DATRDY (0x1u << 0) /**< \brief (TRNG_IDR) Data Ready Interrupt Disable */
+/* -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- */
+#define TRNG_IMR_DATRDY (0x1u << 0) /**< \brief (TRNG_IMR) Data Ready Interrupt Mask */
+/* -------- TRNG_ISR : (TRNG Offset: 0x1C) Interrupt Status Register -------- */
+#define TRNG_ISR_DATRDY (0x1u << 0) /**< \brief (TRNG_ISR) Data Ready */
+/* -------- TRNG_ODATA : (TRNG Offset: 0x50) Output Data Register -------- */
+#define TRNG_ODATA_ODATA_Pos 0
+#define TRNG_ODATA_ODATA_Msk (0xffffffffu << TRNG_ODATA_ODATA_Pos) /**< \brief (TRNG_ODATA) Output Data */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_TRNG_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_twi.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_twi.h
new file mode 100644
index 000000000..cdc10d858
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_twi.h
@@ -0,0 +1,217 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_TWI_COMPONENT_
+#define _SAM3XA_TWI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Two-wire Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_TWI Two-wire Interface */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Twi hardware registers */
+typedef struct {
+  WoReg TWI_CR;        /**< \brief (Twi Offset: 0x00) Control Register */
+  RwReg TWI_MMR;       /**< \brief (Twi Offset: 0x04) Master Mode Register */
+  RwReg TWI_SMR;       /**< \brief (Twi Offset: 0x08) Slave Mode Register */
+  RwReg TWI_IADR;      /**< \brief (Twi Offset: 0x0C) Internal Address Register */
+  RwReg TWI_CWGR;      /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */
+  RoReg Reserved1[3];
+  RoReg TWI_SR;        /**< \brief (Twi Offset: 0x20) Status Register */
+  WoReg TWI_IER;       /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */
+  WoReg TWI_IDR;       /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */
+  RoReg TWI_IMR;       /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */
+  RoReg TWI_RHR;       /**< \brief (Twi Offset: 0x30) Receive Holding Register */
+  WoReg TWI_THR;       /**< \brief (Twi Offset: 0x34) Transmit Holding Register */
+  RoReg Reserved2[50];
+  RwReg TWI_RPR;       /**< \brief (Twi Offset: 0x100) Receive Pointer Register */
+  RwReg TWI_RCR;       /**< \brief (Twi Offset: 0x104) Receive Counter Register */
+  RwReg TWI_TPR;       /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */
+  RwReg TWI_TCR;       /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */
+  RwReg TWI_RNPR;      /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */
+  RwReg TWI_RNCR;      /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */
+  RwReg TWI_TNPR;      /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */
+  RwReg TWI_TNCR;      /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */
+  WoReg TWI_PTCR;      /**< \brief (Twi Offset: 0x120) Transfer Control Register */
+  RoReg TWI_PTSR;      /**< \brief (Twi Offset: 0x124) Transfer Status Register */
+} Twi;
+#endif /* __ASSEMBLY__ */
+/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */
+#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */
+#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */
+#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */
+#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */
+#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */
+#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */
+#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */
+#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */
+/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */
+#define TWI_MMR_IADRSZ_Pos 8
+#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */
+#define   TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */
+#define   TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */
+#define   TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */
+#define   TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */
+#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */
+#define TWI_MMR_DADR_Pos 16
+#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */
+#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))
+/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */
+#define TWI_SMR_SADR_Pos 16
+#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */
+#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))
+/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */
+#define TWI_IADR_IADR_Pos 0
+#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */
+#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))
+/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */
+#define TWI_CWGR_CLDIV_Pos 0
+#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */
+#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))
+#define TWI_CWGR_CHDIV_Pos 8
+#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */
+#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))
+#define TWI_CWGR_CKDIV_Pos 16
+#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */
+#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))
+/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */
+#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */
+#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */
+#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */
+#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */
+#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */
+#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */
+#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */
+#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */
+#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */
+#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */
+#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */
+#define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */
+#define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */
+#define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */
+#define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */
+/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */
+#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */
+#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */
+#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */
+#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */
+#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */
+#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */
+#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */
+#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */
+#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */
+#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */
+#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */
+#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */
+#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */
+#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */
+/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */
+#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */
+#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */
+#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */
+#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */
+#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */
+#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */
+#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */
+#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */
+#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */
+#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */
+#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */
+#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */
+#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */
+#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */
+/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */
+#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */
+#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */
+#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */
+#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */
+#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */
+#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */
+#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */
+#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */
+#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */
+#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */
+#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */
+#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */
+#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */
+#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */
+/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */
+#define TWI_RHR_RXDATA_Pos 0
+#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */
+/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */
+#define TWI_THR_TXDATA_Pos 0
+#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */
+#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))
+/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */
+#define TWI_RPR_RXPTR_Pos 0
+#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */
+#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos)))
+/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */
+#define TWI_RCR_RXCTR_Pos 0
+#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */
+#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos)))
+/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */
+#define TWI_TPR_TXPTR_Pos 0
+#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */
+#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos)))
+/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */
+#define TWI_TCR_TXCTR_Pos 0
+#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */
+#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos)))
+/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */
+#define TWI_RNPR_RXNPTR_Pos 0
+#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */
+#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos)))
+/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */
+#define TWI_RNCR_RXNCTR_Pos 0
+#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */
+#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos)))
+/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define TWI_TNPR_TXNPTR_Pos 0
+#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */
+#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos)))
+/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define TWI_TNCR_TXNCTR_Pos 0
+#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */
+#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos)))
+/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */
+#define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */
+#define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */
+#define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */
+#define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */
+/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */
+#define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */
+#define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_TWI_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_uart.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_uart.h
new file mode 100644
index 000000000..dc8f47c93
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_uart.h
@@ -0,0 +1,185 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_UART_COMPONENT_
+#define _SAM3XA_UART_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_UART Universal Asynchronous Receiver Transmitter */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Uart hardware registers */
+typedef struct {
+  WoReg UART_CR;       /**< \brief (Uart Offset: 0x0000) Control Register */
+  RwReg UART_MR;       /**< \brief (Uart Offset: 0x0004) Mode Register */
+  WoReg UART_IER;      /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */
+  WoReg UART_IDR;      /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */
+  RoReg UART_IMR;      /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */
+  RoReg UART_SR;       /**< \brief (Uart Offset: 0x0014) Status Register */
+  RoReg UART_RHR;      /**< \brief (Uart Offset: 0x0018) Receive Holding Register */
+  WoReg UART_THR;      /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */
+  RwReg UART_BRGR;     /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */
+  RoReg Reserved1[55];
+  RwReg UART_RPR;      /**< \brief (Uart Offset: 0x100) Receive Pointer Register */
+  RwReg UART_RCR;      /**< \brief (Uart Offset: 0x104) Receive Counter Register */
+  RwReg UART_TPR;      /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */
+  RwReg UART_TCR;      /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */
+  RwReg UART_RNPR;     /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */
+  RwReg UART_RNCR;     /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */
+  RwReg UART_TNPR;     /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */
+  RwReg UART_TNCR;     /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */
+  WoReg UART_PTCR;     /**< \brief (Uart Offset: 0x120) Transfer Control Register */
+  RoReg UART_PTSR;     /**< \brief (Uart Offset: 0x124) Transfer Status Register */
+} Uart;
+#endif /* __ASSEMBLY__ */
+/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
+#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */
+#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */
+#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */
+#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */
+#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */
+#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */
+#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */
+/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
+#define UART_MR_PAR_Pos 9
+#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */
+#define   UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */
+#define   UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */
+#define   UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */
+#define   UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */
+#define   UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */
+#define UART_MR_CHMODE_Pos 14
+#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */
+#define   UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */
+#define   UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */
+#define   UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */
+#define   UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */
+/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
+#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */
+#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */
+#define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */
+#define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */
+#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */
+#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */
+#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */
+#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */
+#define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */
+#define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */
+/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
+#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */
+#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */
+#define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */
+#define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */
+#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */
+#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */
+#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */
+#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */
+#define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */
+#define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */
+/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
+#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */
+#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */
+#define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */
+#define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */
+#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */
+#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */
+#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */
+#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */
+#define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */
+#define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */
+/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
+#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */
+#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */
+#define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */
+#define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */
+#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */
+#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */
+#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */
+#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */
+#define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */
+#define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */
+/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
+#define UART_RHR_RXCHR_Pos 0
+#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */
+/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
+#define UART_THR_TXCHR_Pos 0
+#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */
+#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
+/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define UART_BRGR_CD_Pos 0
+#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */
+#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
+/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */
+#define UART_RPR_RXPTR_Pos 0
+#define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */
+#define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos)))
+/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */
+#define UART_RCR_RXCTR_Pos 0
+#define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */
+#define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos)))
+/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */
+#define UART_TPR_TXPTR_Pos 0
+#define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */
+#define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos)))
+/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */
+#define UART_TCR_TXCTR_Pos 0
+#define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */
+#define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos)))
+/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */
+#define UART_RNPR_RXNPTR_Pos 0
+#define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */
+#define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos)))
+/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */
+#define UART_RNCR_RXNCTR_Pos 0
+#define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */
+#define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos)))
+/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define UART_TNPR_TXNPTR_Pos 0
+#define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */
+#define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos)))
+/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define UART_TNCR_TXNCTR_Pos 0
+#define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */
+#define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos)))
+/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */
+#define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */
+#define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */
+#define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */
+#define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */
+/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */
+#define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */
+#define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_UART_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_uotghs.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_uotghs.h
new file mode 100644
index 000000000..15ec768e5
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_uotghs.h
@@ -0,0 +1,938 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_UOTGHS_COMPONENT_
+#define _SAM3XA_UOTGHS_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR USB On-The-Go Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_UOTGHS USB On-The-Go Interface */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief UotghsDevdma hardware registers */
+typedef struct {
+  RwReg         UOTGHS_DEVDMANXTDSC;   /**< \brief (UotghsDevdma Offset: 0x0) Device DMA Channel Next Descriptor Address Register */
+  RwReg         UOTGHS_DEVDMAADDRESS;  /**< \brief (UotghsDevdma Offset: 0x4) Device DMA Channel Address Register */
+  RwReg         UOTGHS_DEVDMACONTROL;  /**< \brief (UotghsDevdma Offset: 0x8) Device DMA Channel Control Register */
+  RwReg         UOTGHS_DEVDMASTATUS;   /**< \brief (UotghsDevdma Offset: 0xC) Device DMA Channel Status Register */
+} UotghsDevdma;
+/** \brief UotghsHstdma hardware registers */
+typedef struct {
+  RwReg         UOTGHS_HSTDMANXTDSC;   /**< \brief (UotghsHstdma Offset: 0x0) Host DMA Channel Next Descriptor Address Register */
+  RwReg         UOTGHS_HSTDMAADDRESS;  /**< \brief (UotghsHstdma Offset: 0x4) Host DMA Channel Address Register */
+  RwReg         UOTGHS_HSTDMACONTROL;  /**< \brief (UotghsHstdma Offset: 0x8) Host DMA Channel Control Register */
+  RwReg         UOTGHS_HSTDMASTATUS;   /**< \brief (UotghsHstdma Offset: 0xC) Host DMA Channel Status Register */
+} UotghsHstdma;
+/** \brief Uotghs hardware registers */
+#define UOTGHSDEVDMA_NUMBER 7
+#define UOTGHSHSTDMA_NUMBER 7
+typedef struct {
+  RwReg         UOTGHS_DEVCTRL;        /**< \brief (Uotghs Offset: 0x0000) Device General Control Register */
+  RoReg         UOTGHS_DEVISR;         /**< \brief (Uotghs Offset: 0x0004) Device Global Interrupt Status Register */
+  WoReg         UOTGHS_DEVICR;         /**< \brief (Uotghs Offset: 0x0008) Device Global Interrupt Clear Register */
+  WoReg         UOTGHS_DEVIFR;         /**< \brief (Uotghs Offset: 0x000C) Device Global Interrupt Set Register */
+  RoReg         UOTGHS_DEVIMR;         /**< \brief (Uotghs Offset: 0x0010) Device Global Interrupt Mask Register */
+  WoReg         UOTGHS_DEVIDR;         /**< \brief (Uotghs Offset: 0x0014) Device Global Interrupt Disable Register */
+  WoReg         UOTGHS_DEVIER;         /**< \brief (Uotghs Offset: 0x0018) Device Global Interrupt Enable Register */
+  RwReg         UOTGHS_DEVEPT;         /**< \brief (Uotghs Offset: 0x001C) Device Endpoint Register */
+  RoReg         UOTGHS_DEVFNUM;        /**< \brief (Uotghs Offset: 0x0020) Device Frame Number Register */
+  RoReg         Reserved1[55];
+  RwReg         UOTGHS_DEVEPTCFG[10];  /**< \brief (Uotghs Offset: 0x100) Device Endpoint Configuration Register (n = 0) */
+  RoReg         Reserved2[2];
+  RoReg         UOTGHS_DEVEPTISR[10];  /**< \brief (Uotghs Offset: 0x130) Device Endpoint Status Register (n = 0) */
+  RoReg         Reserved3[2];
+  WoReg         UOTGHS_DEVEPTICR[10];  /**< \brief (Uotghs Offset: 0x160) Device Endpoint Clear Register (n = 0) */
+  RoReg         Reserved4[2];
+  WoReg         UOTGHS_DEVEPTIFR[10];  /**< \brief (Uotghs Offset: 0x190) Device Endpoint Set Register (n = 0) */
+  RoReg         Reserved5[2];
+  RoReg         UOTGHS_DEVEPTIMR[10];  /**< \brief (Uotghs Offset: 0x1C0) Device Endpoint Mask Register (n = 0) */
+  RoReg         Reserved6[2];
+  WoReg         UOTGHS_DEVEPTIER[10];  /**< \brief (Uotghs Offset: 0x1F0) Device Endpoint Enable Register (n = 0) */
+  RoReg         Reserved7[2];
+  WoReg         UOTGHS_DEVEPTIDR[10];  /**< \brief (Uotghs Offset: 0x220) Device Endpoint Disable Register (n = 0) */
+  RoReg         Reserved8[50];
+  UotghsDevdma  UOTGHS_DEVDMA[UOTGHSDEVDMA_NUMBER]; /**< \brief (Uotghs Offset: 0x310) n = 1 .. 7 */
+  RoReg         Reserved9[32];
+  RwReg         UOTGHS_HSTCTRL;        /**< \brief (Uotghs Offset: 0x0400) Host General Control Register */
+  RoReg         UOTGHS_HSTISR;         /**< \brief (Uotghs Offset: 0x0404) Host Global Interrupt Status Register */
+  WoReg         UOTGHS_HSTICR;         /**< \brief (Uotghs Offset: 0x0408) Host Global Interrupt Clear Register */
+  WoReg         UOTGHS_HSTIFR;         /**< \brief (Uotghs Offset: 0x040C) Host Global Interrupt Set Register */
+  RoReg         UOTGHS_HSTIMR;         /**< \brief (Uotghs Offset: 0x0410) Host Global Interrupt Mask Register */
+  WoReg         UOTGHS_HSTIDR;         /**< \brief (Uotghs Offset: 0x0414) Host Global Interrupt Disable Register */
+  WoReg         UOTGHS_HSTIER;         /**< \brief (Uotghs Offset: 0x0418) Host Global Interrupt Enable Register */
+  RwReg         UOTGHS_HSTPIP;         /**< \brief (Uotghs Offset: 0x0041C) Host Pipe Register */
+  RwReg         UOTGHS_HSTFNUM;        /**< \brief (Uotghs Offset: 0x0420) Host Frame Number Register */
+  RwReg         UOTGHS_HSTADDR1;       /**< \brief (Uotghs Offset: 0x0424) Host Address 1 Register */
+  RwReg         UOTGHS_HSTADDR2;       /**< \brief (Uotghs Offset: 0x0428) Host Address 2 Register */
+  RwReg         UOTGHS_HSTADDR3;       /**< \brief (Uotghs Offset: 0x042C) Host Address 3 Register */
+  RoReg         Reserved10[52];
+  RwReg         UOTGHS_HSTPIPCFG[10];  /**< \brief (Uotghs Offset: 0x500) Host Pipe Configuration Register (n = 0) */
+  RoReg         Reserved11[2];
+  RoReg         UOTGHS_HSTPIPISR[10];  /**< \brief (Uotghs Offset: 0x530) Host Pipe Status Register (n = 0) */
+  RoReg         Reserved12[2];
+  WoReg         UOTGHS_HSTPIPICR[10];  /**< \brief (Uotghs Offset: 0x560) Host Pipe Clear Register (n = 0) */
+  RoReg         Reserved13[2];
+  WoReg         UOTGHS_HSTPIPIFR[10];  /**< \brief (Uotghs Offset: 0x590) Host Pipe Set Register (n = 0) */
+  RoReg         Reserved14[2];
+  RoReg         UOTGHS_HSTPIPIMR[10];  /**< \brief (Uotghs Offset: 0x5C0) Host Pipe Mask Register (n = 0) */
+  RoReg         Reserved15[2];
+  WoReg         UOTGHS_HSTPIPIER[10];  /**< \brief (Uotghs Offset: 0x5F0) Host Pipe Enable Register (n = 0) */
+  RoReg         Reserved16[2];
+  WoReg         UOTGHS_HSTPIPIDR[10];  /**< \brief (Uotghs Offset: 0x620) Host Pipe Disable Register (n = 0) */
+  RoReg         Reserved17[2];
+  RwReg         UOTGHS_HSTPIPINRQ[10]; /**< \brief (Uotghs Offset: 0x650) Host Pipe IN Request Register (n = 0) */
+  RoReg         Reserved18[2];
+  RwReg         UOTGHS_HSTPIPERR[10];  /**< \brief (Uotghs Offset: 0x680) Host Pipe Error Register (n = 0) */
+  RoReg         Reserved19[26];
+  UotghsHstdma  UOTGHS_HSTDMA[UOTGHSHSTDMA_NUMBER]; /**< \brief (Uotghs Offset: 0x710) n = 1 .. 7 */
+  RoReg         Reserved20[32];
+  RwReg         UOTGHS_CTRL;           /**< \brief (Uotghs Offset: 0x0800) General Control Register */
+  RoReg         UOTGHS_SR;             /**< \brief (Uotghs Offset: 0x0804) General Status Register */
+  WoReg         UOTGHS_SCR;            /**< \brief (Uotghs Offset: 0x0808) General Status Clear Register */
+  WoReg         UOTGHS_SFR;            /**< \brief (Uotghs Offset: 0x080C) General Status Set Register */
+  RoReg         Reserved21[7];
+  RoReg         UOTGHS_FSM;            /**< \brief (Uotghs Offset: 0x082C) General Finite State Machine Register */
+} Uotghs;
+#endif /* __ASSEMBLY__ */
+/* -------- UOTGHS_DEVCTRL : (UOTGHS Offset: 0x0000) Device General Control Register -------- */
+#define UOTGHS_DEVCTRL_UADD_Pos 0
+#define UOTGHS_DEVCTRL_UADD_Msk (0x7fu << UOTGHS_DEVCTRL_UADD_Pos) /**< \brief (UOTGHS_DEVCTRL) USB Address */
+#define UOTGHS_DEVCTRL_UADD(value) ((UOTGHS_DEVCTRL_UADD_Msk & ((value) << UOTGHS_DEVCTRL_UADD_Pos)))
+#define UOTGHS_DEVCTRL_ADDEN (0x1u << 7) /**< \brief (UOTGHS_DEVCTRL) Address Enable */
+#define UOTGHS_DEVCTRL_DETACH (0x1u << 8) /**< \brief (UOTGHS_DEVCTRL) Detach */
+#define UOTGHS_DEVCTRL_RMWKUP (0x1u << 9) /**< \brief (UOTGHS_DEVCTRL) Remote Wake-Up */
+#define UOTGHS_DEVCTRL_SPDCONF_Pos 10
+#define UOTGHS_DEVCTRL_SPDCONF_Msk (0x3u << UOTGHS_DEVCTRL_SPDCONF_Pos) /**< \brief (UOTGHS_DEVCTRL) Mode Configuration */
+#define   UOTGHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10) /**< \brief (UOTGHS_DEVCTRL) The peripheral starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the host is high-speed capable. */
+#define   UOTGHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10) /**< \brief (UOTGHS_DEVCTRL) For a better consumption, if high-speed is not needed. */
+#define   UOTGHS_DEVCTRL_SPDCONF_HIGH_SPEED (0x2u << 10) /**< \brief (UOTGHS_DEVCTRL) Forced high speed. */
+#define   UOTGHS_DEVCTRL_SPDCONF_FORCED_FS (0x3u << 10) /**< \brief (UOTGHS_DEVCTRL) The peripheral remains in full-speed mode whatever the host speed capability. */
+#define UOTGHS_DEVCTRL_LS (0x1u << 12) /**< \brief (UOTGHS_DEVCTRL) Low-Speed Mode Force */
+#define UOTGHS_DEVCTRL_TSTJ (0x1u << 13) /**< \brief (UOTGHS_DEVCTRL) Test mode J */
+#define UOTGHS_DEVCTRL_TSTK (0x1u << 14) /**< \brief (UOTGHS_DEVCTRL) Test mode K */
+#define UOTGHS_DEVCTRL_TSTPCKT (0x1u << 15) /**< \brief (UOTGHS_DEVCTRL) Test packet mode */
+#define UOTGHS_DEVCTRL_OPMODE2 (0x1u << 16) /**< \brief (UOTGHS_DEVCTRL) Specific Operational mode */
+/* -------- UOTGHS_DEVISR : (UOTGHS Offset: 0x0004) Device Global Interrupt Status Register -------- */
+#define UOTGHS_DEVISR_SUSP (0x1u << 0) /**< \brief (UOTGHS_DEVISR) Suspend Interrupt */
+#define UOTGHS_DEVISR_MSOF (0x1u << 1) /**< \brief (UOTGHS_DEVISR) Micro Start of Frame Interrupt */
+#define UOTGHS_DEVISR_SOF (0x1u << 2) /**< \brief (UOTGHS_DEVISR) Start of Frame Interrupt */
+#define UOTGHS_DEVISR_EORST (0x1u << 3) /**< \brief (UOTGHS_DEVISR) End of Reset Interrupt */
+#define UOTGHS_DEVISR_WAKEUP (0x1u << 4) /**< \brief (UOTGHS_DEVISR) Wake-Up Interrupt */
+#define UOTGHS_DEVISR_EORSM (0x1u << 5) /**< \brief (UOTGHS_DEVISR) End of Resume Interrupt */
+#define UOTGHS_DEVISR_UPRSM (0x1u << 6) /**< \brief (UOTGHS_DEVISR) Upstream Resume Interrupt */
+#define UOTGHS_DEVISR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVISR) Endpoint 0 Interrupt */
+#define UOTGHS_DEVISR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVISR) Endpoint 1 Interrupt */
+#define UOTGHS_DEVISR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVISR) Endpoint 2 Interrupt */
+#define UOTGHS_DEVISR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVISR) Endpoint 3 Interrupt */
+#define UOTGHS_DEVISR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVISR) Endpoint 4 Interrupt */
+#define UOTGHS_DEVISR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVISR) Endpoint 5 Interrupt */
+#define UOTGHS_DEVISR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVISR) Endpoint 6 Interrupt */
+#define UOTGHS_DEVISR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVISR) Endpoint 7 Interrupt */
+#define UOTGHS_DEVISR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVISR) Endpoint 8 Interrupt */
+#define UOTGHS_DEVISR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVISR) Endpoint 9 Interrupt */
+#define UOTGHS_DEVISR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVISR) DMA Channel 1 Interrupt */
+#define UOTGHS_DEVISR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVISR) DMA Channel 2 Interrupt */
+#define UOTGHS_DEVISR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVISR) DMA Channel 3 Interrupt */
+#define UOTGHS_DEVISR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVISR) DMA Channel 4 Interrupt */
+#define UOTGHS_DEVISR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVISR) DMA Channel 5 Interrupt */
+#define UOTGHS_DEVISR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVISR) DMA Channel 6 Interrupt */
+/* -------- UOTGHS_DEVICR : (UOTGHS Offset: 0x0008) Device Global Interrupt Clear Register -------- */
+#define UOTGHS_DEVICR_SUSPC (0x1u << 0) /**< \brief (UOTGHS_DEVICR) Suspend Interrupt Clear */
+#define UOTGHS_DEVICR_MSOFC (0x1u << 1) /**< \brief (UOTGHS_DEVICR) Micro Start of Frame Interrupt Clear */
+#define UOTGHS_DEVICR_SOFC (0x1u << 2) /**< \brief (UOTGHS_DEVICR) Start of Frame Interrupt Clear */
+#define UOTGHS_DEVICR_EORSTC (0x1u << 3) /**< \brief (UOTGHS_DEVICR) End of Reset Interrupt Clear */
+#define UOTGHS_DEVICR_WAKEUPC (0x1u << 4) /**< \brief (UOTGHS_DEVICR) Wake-Up Interrupt Clear */
+#define UOTGHS_DEVICR_EORSMC (0x1u << 5) /**< \brief (UOTGHS_DEVICR) End of Resume Interrupt Clear */
+#define UOTGHS_DEVICR_UPRSMC (0x1u << 6) /**< \brief (UOTGHS_DEVICR) Upstream Resume Interrupt Clear */
+/* -------- UOTGHS_DEVIFR : (UOTGHS Offset: 0x000C) Device Global Interrupt Set Register -------- */
+#define UOTGHS_DEVIFR_SUSPS (0x1u << 0) /**< \brief (UOTGHS_DEVIFR) Suspend Interrupt Set */
+#define UOTGHS_DEVIFR_MSOFS (0x1u << 1) /**< \brief (UOTGHS_DEVIFR) Micro Start of Frame Interrupt Set */
+#define UOTGHS_DEVIFR_SOFS (0x1u << 2) /**< \brief (UOTGHS_DEVIFR) Start of Frame Interrupt Set */
+#define UOTGHS_DEVIFR_EORSTS (0x1u << 3) /**< \brief (UOTGHS_DEVIFR) End of Reset Interrupt Set */
+#define UOTGHS_DEVIFR_WAKEUPS (0x1u << 4) /**< \brief (UOTGHS_DEVIFR) Wake-Up Interrupt Set */
+#define UOTGHS_DEVIFR_EORSMS (0x1u << 5) /**< \brief (UOTGHS_DEVIFR) End of Resume Interrupt Set */
+#define UOTGHS_DEVIFR_UPRSMS (0x1u << 6) /**< \brief (UOTGHS_DEVIFR) Upstream Resume Interrupt Set */
+#define UOTGHS_DEVIFR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIFR) DMA Channel 1 Interrupt Set */
+#define UOTGHS_DEVIFR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIFR) DMA Channel 2 Interrupt Set */
+#define UOTGHS_DEVIFR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIFR) DMA Channel 3 Interrupt Set */
+#define UOTGHS_DEVIFR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIFR) DMA Channel 4 Interrupt Set */
+#define UOTGHS_DEVIFR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIFR) DMA Channel 5 Interrupt Set */
+#define UOTGHS_DEVIFR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIFR) DMA Channel 6 Interrupt Set */
+/* -------- UOTGHS_DEVIMR : (UOTGHS Offset: 0x0010) Device Global Interrupt Mask Register -------- */
+#define UOTGHS_DEVIMR_SUSPE (0x1u << 0) /**< \brief (UOTGHS_DEVIMR) Suspend Interrupt Mask */
+#define UOTGHS_DEVIMR_MSOFE (0x1u << 1) /**< \brief (UOTGHS_DEVIMR) Micro Start of Frame Interrupt Mask */
+#define UOTGHS_DEVIMR_SOFE (0x1u << 2) /**< \brief (UOTGHS_DEVIMR) Start of Frame Interrupt Mask */
+#define UOTGHS_DEVIMR_EORSTE (0x1u << 3) /**< \brief (UOTGHS_DEVIMR) End of Reset Interrupt Mask */
+#define UOTGHS_DEVIMR_WAKEUPE (0x1u << 4) /**< \brief (UOTGHS_DEVIMR) Wake-Up Interrupt Mask */
+#define UOTGHS_DEVIMR_EORSME (0x1u << 5) /**< \brief (UOTGHS_DEVIMR) End of Resume Interrupt Mask */
+#define UOTGHS_DEVIMR_UPRSME (0x1u << 6) /**< \brief (UOTGHS_DEVIMR) Upstream Resume Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIMR) Endpoint 0 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIMR) Endpoint 1 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIMR) Endpoint 2 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIMR) Endpoint 3 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIMR) Endpoint 4 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIMR) Endpoint 5 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIMR) Endpoint 6 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIMR) Endpoint 7 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIMR) Endpoint 8 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIMR) Endpoint 9 Interrupt Mask */
+#define UOTGHS_DEVIMR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIMR) DMA Channel 1 Interrupt Mask */
+#define UOTGHS_DEVIMR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIMR) DMA Channel 2 Interrupt Mask */
+#define UOTGHS_DEVIMR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIMR) DMA Channel 3 Interrupt Mask */
+#define UOTGHS_DEVIMR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIMR) DMA Channel 4 Interrupt Mask */
+#define UOTGHS_DEVIMR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIMR) DMA Channel 5 Interrupt Mask */
+#define UOTGHS_DEVIMR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIMR) DMA Channel 6 Interrupt Mask */
+/* -------- UOTGHS_DEVIDR : (UOTGHS Offset: 0x0014) Device Global Interrupt Disable Register -------- */
+#define UOTGHS_DEVIDR_SUSPEC (0x1u << 0) /**< \brief (UOTGHS_DEVIDR) Suspend Interrupt Disable */
+#define UOTGHS_DEVIDR_MSOFEC (0x1u << 1) /**< \brief (UOTGHS_DEVIDR) Micro Start of Frame Interrupt Disable */
+#define UOTGHS_DEVIDR_SOFEC (0x1u << 2) /**< \brief (UOTGHS_DEVIDR) Start of Frame Interrupt Disable */
+#define UOTGHS_DEVIDR_EORSTEC (0x1u << 3) /**< \brief (UOTGHS_DEVIDR) End of Reset Interrupt Disable */
+#define UOTGHS_DEVIDR_WAKEUPEC (0x1u << 4) /**< \brief (UOTGHS_DEVIDR) Wake-Up Interrupt Disable */
+#define UOTGHS_DEVIDR_EORSMEC (0x1u << 5) /**< \brief (UOTGHS_DEVIDR) End of Resume Interrupt Disable */
+#define UOTGHS_DEVIDR_UPRSMEC (0x1u << 6) /**< \brief (UOTGHS_DEVIDR) Upstream Resume Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIDR) Endpoint 0 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIDR) Endpoint 1 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIDR) Endpoint 2 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIDR) Endpoint 3 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIDR) Endpoint 4 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIDR) Endpoint 5 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIDR) Endpoint 6 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIDR) Endpoint 7 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIDR) Endpoint 8 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIDR) Endpoint 9 Interrupt Disable */
+#define UOTGHS_DEVIDR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIDR) DMA Channel 1 Interrupt Disable */
+#define UOTGHS_DEVIDR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIDR) DMA Channel 2 Interrupt Disable */
+#define UOTGHS_DEVIDR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIDR) DMA Channel 3 Interrupt Disable */
+#define UOTGHS_DEVIDR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIDR) DMA Channel 4 Interrupt Disable */
+#define UOTGHS_DEVIDR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIDR) DMA Channel 5 Interrupt Disable */
+#define UOTGHS_DEVIDR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIDR) DMA Channel 6 Interrupt Disable */
+/* -------- UOTGHS_DEVIER : (UOTGHS Offset: 0x0018) Device Global Interrupt Enable Register -------- */
+#define UOTGHS_DEVIER_SUSPES (0x1u << 0) /**< \brief (UOTGHS_DEVIER) Suspend Interrupt Enable */
+#define UOTGHS_DEVIER_MSOFES (0x1u << 1) /**< \brief (UOTGHS_DEVIER) Micro Start of Frame Interrupt Enable */
+#define UOTGHS_DEVIER_SOFES (0x1u << 2) /**< \brief (UOTGHS_DEVIER) Start of Frame Interrupt Enable */
+#define UOTGHS_DEVIER_EORSTES (0x1u << 3) /**< \brief (UOTGHS_DEVIER) End of Reset Interrupt Enable */
+#define UOTGHS_DEVIER_WAKEUPES (0x1u << 4) /**< \brief (UOTGHS_DEVIER) Wake-Up Interrupt Enable */
+#define UOTGHS_DEVIER_EORSMES (0x1u << 5) /**< \brief (UOTGHS_DEVIER) End of Resume Interrupt Enable */
+#define UOTGHS_DEVIER_UPRSMES (0x1u << 6) /**< \brief (UOTGHS_DEVIER) Upstream Resume Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIER) Endpoint 0 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIER) Endpoint 1 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIER) Endpoint 2 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIER) Endpoint 3 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIER) Endpoint 4 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIER) Endpoint 5 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIER) Endpoint 6 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIER) Endpoint 7 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIER) Endpoint 8 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIER) Endpoint 9 Interrupt Enable */
+#define UOTGHS_DEVIER_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIER) DMA Channel 1 Interrupt Enable */
+#define UOTGHS_DEVIER_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIER) DMA Channel 2 Interrupt Enable */
+#define UOTGHS_DEVIER_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIER) DMA Channel 3 Interrupt Enable */
+#define UOTGHS_DEVIER_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIER) DMA Channel 4 Interrupt Enable */
+#define UOTGHS_DEVIER_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIER) DMA Channel 5 Interrupt Enable */
+#define UOTGHS_DEVIER_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIER) DMA Channel 6 Interrupt Enable */
+/* -------- UOTGHS_DEVEPT : (UOTGHS Offset: 0x001C) Device Endpoint Register -------- */
+#define UOTGHS_DEVEPT_EPEN0 (0x1u << 0) /**< \brief (UOTGHS_DEVEPT) Endpoint 0 Enable */
+#define UOTGHS_DEVEPT_EPEN1 (0x1u << 1) /**< \brief (UOTGHS_DEVEPT) Endpoint 1 Enable */
+#define UOTGHS_DEVEPT_EPEN2 (0x1u << 2) /**< \brief (UOTGHS_DEVEPT) Endpoint 2 Enable */
+#define UOTGHS_DEVEPT_EPEN3 (0x1u << 3) /**< \brief (UOTGHS_DEVEPT) Endpoint 3 Enable */
+#define UOTGHS_DEVEPT_EPEN4 (0x1u << 4) /**< \brief (UOTGHS_DEVEPT) Endpoint 4 Enable */
+#define UOTGHS_DEVEPT_EPEN5 (0x1u << 5) /**< \brief (UOTGHS_DEVEPT) Endpoint 5 Enable */
+#define UOTGHS_DEVEPT_EPEN6 (0x1u << 6) /**< \brief (UOTGHS_DEVEPT) Endpoint 6 Enable */
+#define UOTGHS_DEVEPT_EPEN7 (0x1u << 7) /**< \brief (UOTGHS_DEVEPT) Endpoint 7 Enable */
+#define UOTGHS_DEVEPT_EPEN8 (0x1u << 8) /**< \brief (UOTGHS_DEVEPT) Endpoint 8 Enable */
+#define UOTGHS_DEVEPT_EPRST0 (0x1u << 16) /**< \brief (UOTGHS_DEVEPT) Endpoint 0 Reset */
+#define UOTGHS_DEVEPT_EPRST1 (0x1u << 17) /**< \brief (UOTGHS_DEVEPT) Endpoint 1 Reset */
+#define UOTGHS_DEVEPT_EPRST2 (0x1u << 18) /**< \brief (UOTGHS_DEVEPT) Endpoint 2 Reset */
+#define UOTGHS_DEVEPT_EPRST3 (0x1u << 19) /**< \brief (UOTGHS_DEVEPT) Endpoint 3 Reset */
+#define UOTGHS_DEVEPT_EPRST4 (0x1u << 20) /**< \brief (UOTGHS_DEVEPT) Endpoint 4 Reset */
+#define UOTGHS_DEVEPT_EPRST5 (0x1u << 21) /**< \brief (UOTGHS_DEVEPT) Endpoint 5 Reset */
+#define UOTGHS_DEVEPT_EPRST6 (0x1u << 22) /**< \brief (UOTGHS_DEVEPT) Endpoint 6 Reset */
+#define UOTGHS_DEVEPT_EPRST7 (0x1u << 23) /**< \brief (UOTGHS_DEVEPT) Endpoint 7 Reset */
+#define UOTGHS_DEVEPT_EPRST8 (0x1u << 24) /**< \brief (UOTGHS_DEVEPT) Endpoint 8 Reset */
+/* -------- UOTGHS_DEVFNUM : (UOTGHS Offset: 0x0020) Device Frame Number Register -------- */
+#define UOTGHS_DEVFNUM_MFNUM_Pos 0
+#define UOTGHS_DEVFNUM_MFNUM_Msk (0x7u << UOTGHS_DEVFNUM_MFNUM_Pos) /**< \brief (UOTGHS_DEVFNUM) Micro Frame Number */
+#define UOTGHS_DEVFNUM_FNUM_Pos 3
+#define UOTGHS_DEVFNUM_FNUM_Msk (0x7ffu << UOTGHS_DEVFNUM_FNUM_Pos) /**< \brief (UOTGHS_DEVFNUM) Frame Number */
+#define UOTGHS_DEVFNUM_FNCERR (0x1u << 15) /**< \brief (UOTGHS_DEVFNUM) Frame Number CRC Error */
+/* -------- UOTGHS_DEVEPTCFG[10] : (UOTGHS Offset: 0x100) Device Endpoint Configuration Register (n = 0) -------- */
+#define UOTGHS_DEVEPTCFG_ALLOC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Memory Allocate */
+#define UOTGHS_DEVEPTCFG_EPBK_Pos 2
+#define UOTGHS_DEVEPTCFG_EPBK_Msk (0x3u << UOTGHS_DEVEPTCFG_EPBK_Pos) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Banks */
+#define   UOTGHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2) /**< \brief (UOTGHS_DEVEPTCFG[10]) Single-bank endpoint */
+#define   UOTGHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2) /**< \brief (UOTGHS_DEVEPTCFG[10]) Double-bank endpoint */
+#define   UOTGHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2) /**< \brief (UOTGHS_DEVEPTCFG[10]) Triple-bank endpoint */
+#define UOTGHS_DEVEPTCFG_EPSIZE_Pos 4
+#define UOTGHS_DEVEPTCFG_EPSIZE_Msk (0x7u << UOTGHS_DEVEPTCFG_EPSIZE_Pos) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Size */
+#define   UOTGHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 8 bytes */
+#define   UOTGHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 16 bytes */
+#define   UOTGHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 32 bytes */
+#define   UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 64 bytes */
+#define   UOTGHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 128 bytes */
+#define   UOTGHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 256 bytes */
+#define   UOTGHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 512 bytes */
+#define   UOTGHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 1024 bytes */
+#define UOTGHS_DEVEPTCFG_EPDIR (0x1u << 8) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Direction */
+#define   UOTGHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8) /**< \brief (UOTGHS_DEVEPTCFG[10]) The endpoint direction is OUT. */
+#define   UOTGHS_DEVEPTCFG_EPDIR_IN (0x1u << 8) /**< \brief (UOTGHS_DEVEPTCFG[10]) The endpoint direction is IN (nor for control endpoints). */
+#define UOTGHS_DEVEPTCFG_AUTOSW (0x1u << 9) /**< \brief (UOTGHS_DEVEPTCFG[10]) Automatic Switch */
+#define UOTGHS_DEVEPTCFG_EPTYPE_Pos 11
+#define UOTGHS_DEVEPTCFG_EPTYPE_Msk (0x3u << UOTGHS_DEVEPTCFG_EPTYPE_Pos) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Type */
+#define   UOTGHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11) /**< \brief (UOTGHS_DEVEPTCFG[10]) Control */
+#define   UOTGHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11) /**< \brief (UOTGHS_DEVEPTCFG[10]) Isochronous */
+#define   UOTGHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11) /**< \brief (UOTGHS_DEVEPTCFG[10]) Bulk */
+#define   UOTGHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11) /**< \brief (UOTGHS_DEVEPTCFG[10]) Interrupt */
+#define UOTGHS_DEVEPTCFG_NBTRANS_Pos 13
+#define UOTGHS_DEVEPTCFG_NBTRANS_Msk (0x3u << UOTGHS_DEVEPTCFG_NBTRANS_Pos) /**< \brief (UOTGHS_DEVEPTCFG[10]) Number of transaction per microframe for isochronous endpoint */
+#define   UOTGHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13) /**< \brief (UOTGHS_DEVEPTCFG[10]) reserved to endpoint that does not have the high-bandwidth isochronous capability. */
+#define   UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13) /**< \brief (UOTGHS_DEVEPTCFG[10]) default value: one transaction per micro-frame. */
+#define   UOTGHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13) /**< \brief (UOTGHS_DEVEPTCFG[10]) 2 transactions per micro-frame. This endpoint should be configured as double-bank. */
+#define   UOTGHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13) /**< \brief (UOTGHS_DEVEPTCFG[10]) 3 transactions per micro-frame. This endpoint should be configured as triple-bank. */
+/* -------- UOTGHS_DEVEPTISR[10] : (UOTGHS Offset: 0x130) Device Endpoint Status Register (n = 0) -------- */
+#define UOTGHS_DEVEPTISR_TXINI (0x1u << 0) /**< \brief (UOTGHS_DEVEPTISR[10]) Transmitted IN Data Interrupt */
+#define UOTGHS_DEVEPTISR_RXOUTI (0x1u << 1) /**< \brief (UOTGHS_DEVEPTISR[10]) Received OUT Data Interrupt */
+#define UOTGHS_DEVEPTISR_RXSTPI (0x1u << 2) /**< \brief (UOTGHS_DEVEPTISR[10]) Received SETUP Interrupt */
+#define UOTGHS_DEVEPTISR_UNDERFI (0x1u << 2) /**< \brief (UOTGHS_DEVEPTISR[10]) Underflow Interrupt */
+#define UOTGHS_DEVEPTISR_NAKOUTI (0x1u << 3) /**< \brief (UOTGHS_DEVEPTISR[10]) NAKed OUT Interrupt */
+#define UOTGHS_DEVEPTISR_HBISOINERRI (0x1u << 3) /**< \brief (UOTGHS_DEVEPTISR[10]) High bandwidth isochronous IN Underflow Error Interrupt */
+#define UOTGHS_DEVEPTISR_NAKINI (0x1u << 4) /**< \brief (UOTGHS_DEVEPTISR[10]) NAKed IN Interrupt */
+#define UOTGHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4) /**< \brief (UOTGHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Flush Interrupt */
+#define UOTGHS_DEVEPTISR_OVERFI (0x1u << 5) /**< \brief (UOTGHS_DEVEPTISR[10]) Overflow Interrupt */
+#define UOTGHS_DEVEPTISR_STALLEDI (0x1u << 6) /**< \brief (UOTGHS_DEVEPTISR[10]) STALLed Interrupt */
+#define UOTGHS_DEVEPTISR_CRCERRI (0x1u << 6) /**< \brief (UOTGHS_DEVEPTISR[10]) CRC Error Interrupt */
+#define UOTGHS_DEVEPTISR_SHORTPACKET (0x1u << 7) /**< \brief (UOTGHS_DEVEPTISR[10]) Short Packet Interrupt */
+#define UOTGHS_DEVEPTISR_DTSEQ_Pos 8
+#define UOTGHS_DEVEPTISR_DTSEQ_Msk (0x3u << UOTGHS_DEVEPTISR_DTSEQ_Pos) /**< \brief (UOTGHS_DEVEPTISR[10]) Data Toggle Sequence */
+#define   UOTGHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (UOTGHS_DEVEPTISR[10]) Data0 toggle sequence */
+#define   UOTGHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (UOTGHS_DEVEPTISR[10]) Data1 toggle sequence */
+#define   UOTGHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8) /**< \brief (UOTGHS_DEVEPTISR[10]) Data2 toggle sequence (for high-bandwidth isochronous endpoint) */
+#define   UOTGHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8) /**< \brief (UOTGHS_DEVEPTISR[10]) MData toggle sequence (for high-bandwidth isochronous endpoint) */
+#define UOTGHS_DEVEPTISR_ERRORTRANS (0x1u << 10) /**< \brief (UOTGHS_DEVEPTISR[10]) High-bandwidth isochronous OUT endpoint transaction error Interrupt */
+#define UOTGHS_DEVEPTISR_NBUSYBK_Pos 12
+#define UOTGHS_DEVEPTISR_NBUSYBK_Msk (0x3u << UOTGHS_DEVEPTISR_NBUSYBK_Pos) /**< \brief (UOTGHS_DEVEPTISR[10]) Number of Busy Banks */
+#define   UOTGHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (UOTGHS_DEVEPTISR[10]) 0 busy bank (all banks free) */
+#define   UOTGHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (UOTGHS_DEVEPTISR[10]) 1 busy bank */
+#define   UOTGHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (UOTGHS_DEVEPTISR[10]) 2 busy banks */
+#define   UOTGHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (UOTGHS_DEVEPTISR[10]) 3 busy banks */
+#define UOTGHS_DEVEPTISR_CURRBK_Pos 14
+#define UOTGHS_DEVEPTISR_CURRBK_Msk (0x3u << UOTGHS_DEVEPTISR_CURRBK_Pos) /**< \brief (UOTGHS_DEVEPTISR[10]) Current Bank */
+#define   UOTGHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (UOTGHS_DEVEPTISR[10]) Current bank is bank0 */
+#define   UOTGHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (UOTGHS_DEVEPTISR[10]) Current bank is bank1 */
+#define   UOTGHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (UOTGHS_DEVEPTISR[10]) Current bank is bank2 */
+#define UOTGHS_DEVEPTISR_RWALL (0x1u << 16) /**< \brief (UOTGHS_DEVEPTISR[10]) Read-write Allowed */
+#define UOTGHS_DEVEPTISR_CTRLDIR (0x1u << 17) /**< \brief (UOTGHS_DEVEPTISR[10]) Control Direction */
+#define UOTGHS_DEVEPTISR_CFGOK (0x1u << 18) /**< \brief (UOTGHS_DEVEPTISR[10]) Configuration OK Status */
+#define UOTGHS_DEVEPTISR_BYCT_Pos 20
+#define UOTGHS_DEVEPTISR_BYCT_Msk (0x7ffu << UOTGHS_DEVEPTISR_BYCT_Pos) /**< \brief (UOTGHS_DEVEPTISR[10]) Byte Count */
+/* -------- UOTGHS_DEVEPTICR[10] : (UOTGHS Offset: 0x160) Device Endpoint Clear Register (n = 0) -------- */
+#define UOTGHS_DEVEPTICR_TXINIC (0x1u << 0) /**< \brief (UOTGHS_DEVEPTICR[10]) Transmitted IN Data Interrupt Clear */
+#define UOTGHS_DEVEPTICR_RXOUTIC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTICR[10]) Received OUT Data Interrupt Clear */
+#define UOTGHS_DEVEPTICR_RXSTPIC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTICR[10]) Received SETUP Interrupt Clear */
+#define UOTGHS_DEVEPTICR_UNDERFIC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTICR[10]) Underflow Interrupt Clear */
+#define UOTGHS_DEVEPTICR_NAKOUTIC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTICR[10]) NAKed OUT Interrupt Clear */
+#define UOTGHS_DEVEPTICR_HBISOINERRIC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTICR[10]) High bandwidth isochronous IN Underflow Error Interrupt Clear */
+#define UOTGHS_DEVEPTICR_NAKINIC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTICR[10]) NAKed IN Interrupt Clear */
+#define UOTGHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */
+#define UOTGHS_DEVEPTICR_OVERFIC (0x1u << 5) /**< \brief (UOTGHS_DEVEPTICR[10]) Overflow Interrupt Clear */
+#define UOTGHS_DEVEPTICR_STALLEDIC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTICR[10]) STALLed Interrupt Clear */
+#define UOTGHS_DEVEPTICR_CRCERRIC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTICR[10]) CRC Error Interrupt Clear */
+#define UOTGHS_DEVEPTICR_SHORTPACKETC (0x1u << 7) /**< \brief (UOTGHS_DEVEPTICR[10]) Short Packet Interrupt Clear */
+/* -------- UOTGHS_DEVEPTIFR[10] : (UOTGHS Offset: 0x190) Device Endpoint Set Register (n = 0) -------- */
+#define UOTGHS_DEVEPTIFR_TXINIS (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIFR[10]) Transmitted IN Data Interrupt Set */
+#define UOTGHS_DEVEPTIFR_RXOUTIS (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIFR[10]) Received OUT Data Interrupt Set */
+#define UOTGHS_DEVEPTIFR_RXSTPIS (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIFR[10]) Received SETUP Interrupt Set */
+#define UOTGHS_DEVEPTIFR_UNDERFIS (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIFR[10]) Underflow Interrupt Set */
+#define UOTGHS_DEVEPTIFR_NAKOUTIS (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIFR[10]) NAKed OUT Interrupt Set */
+#define UOTGHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIFR[10]) High bandwidth isochronous IN Underflow Error Interrupt Set */
+#define UOTGHS_DEVEPTIFR_NAKINIS (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIFR[10]) NAKed IN Interrupt Set */
+#define UOTGHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Flush Interrupt Set */
+#define UOTGHS_DEVEPTIFR_OVERFIS (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIFR[10]) Overflow Interrupt Set */
+#define UOTGHS_DEVEPTIFR_STALLEDIS (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIFR[10]) STALLed Interrupt Set */
+#define UOTGHS_DEVEPTIFR_CRCERRIS (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIFR[10]) CRC Error Interrupt Set */
+#define UOTGHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIFR[10]) Short Packet Interrupt Set */
+#define UOTGHS_DEVEPTIFR_NBUSYBKS (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIFR[10]) Number of Busy Banks Interrupt Set */
+/* -------- UOTGHS_DEVEPTIMR[10] : (UOTGHS Offset: 0x1C0) Device Endpoint Mask Register (n = 0) -------- */
+#define UOTGHS_DEVEPTIMR_TXINE (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIMR[10]) Transmitted IN Data Interrupt */
+#define UOTGHS_DEVEPTIMR_RXOUTE (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIMR[10]) Received OUT Data Interrupt */
+#define UOTGHS_DEVEPTIMR_RXSTPE (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIMR[10]) Received SETUP Interrupt */
+#define UOTGHS_DEVEPTIMR_UNDERFE (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIMR[10]) Underflow Interrupt */
+#define UOTGHS_DEVEPTIMR_NAKOUTE (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIMR[10]) NAKed OUT Interrupt */
+#define UOTGHS_DEVEPTIMR_HBISOINERRE (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Error Interrupt */
+#define UOTGHS_DEVEPTIMR_NAKINE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIMR[10]) NAKed IN Interrupt */
+#define UOTGHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Flush Interrupt */
+#define UOTGHS_DEVEPTIMR_OVERFE (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIMR[10]) Overflow Interrupt */
+#define UOTGHS_DEVEPTIMR_STALLEDE (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIMR[10]) STALLed Interrupt */
+#define UOTGHS_DEVEPTIMR_CRCERRE (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIMR[10]) CRC Error Interrupt */
+#define UOTGHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIMR[10]) Short Packet Interrupt */
+#define UOTGHS_DEVEPTIMR_MDATAE (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIMR[10]) MData Interrupt */
+#define UOTGHS_DEVEPTIMR_DATAXE (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIMR[10]) DataX Interrupt */
+#define UOTGHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIMR[10]) Transaction Error Interrupt */
+#define UOTGHS_DEVEPTIMR_NBUSYBKE (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIMR[10]) Number of Busy Banks Interrupt */
+#define UOTGHS_DEVEPTIMR_KILLBK (0x1u << 13) /**< \brief (UOTGHS_DEVEPTIMR[10]) Kill IN Bank */
+#define UOTGHS_DEVEPTIMR_FIFOCON (0x1u << 14) /**< \brief (UOTGHS_DEVEPTIMR[10]) FIFO Control */
+#define UOTGHS_DEVEPTIMR_EPDISHDMA (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIMR[10]) Endpoint Interrupts Disable HDMA Request */
+#define UOTGHS_DEVEPTIMR_NYETDIS (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIMR[10]) NYET Token Disable */
+#define UOTGHS_DEVEPTIMR_RSTDT (0x1u << 18) /**< \brief (UOTGHS_DEVEPTIMR[10]) Reset Data Toggle */
+#define UOTGHS_DEVEPTIMR_STALLRQ (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIMR[10]) STALL Request */
+/* -------- UOTGHS_DEVEPTIER[10] : (UOTGHS Offset: 0x1F0) Device Endpoint Enable Register (n = 0) -------- */
+#define UOTGHS_DEVEPTIER_TXINES (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIER[10]) Transmitted IN Data Interrupt Enable */
+#define UOTGHS_DEVEPTIER_RXOUTES (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIER[10]) Received OUT Data Interrupt Enable */
+#define UOTGHS_DEVEPTIER_RXSTPES (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIER[10]) Received SETUP Interrupt Enable */
+#define UOTGHS_DEVEPTIER_UNDERFES (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIER[10]) Underflow Interrupt Enable */
+#define UOTGHS_DEVEPTIER_NAKOUTES (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIER[10]) NAKed OUT Interrupt Enable */
+#define UOTGHS_DEVEPTIER_HBISOINERRES (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Error Interrupt Enable */
+#define UOTGHS_DEVEPTIER_NAKINES (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIER[10]) NAKed IN Interrupt Enable */
+#define UOTGHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Flush Interrupt Enable */
+#define UOTGHS_DEVEPTIER_OVERFES (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIER[10]) Overflow Interrupt Enable */
+#define UOTGHS_DEVEPTIER_STALLEDES (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIER[10]) STALLed Interrupt Enable */
+#define UOTGHS_DEVEPTIER_CRCERRES (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIER[10]) CRC Error Interrupt Enable */
+#define UOTGHS_DEVEPTIER_SHORTPACKETES (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIER[10]) Short Packet Interrupt Enable */
+#define UOTGHS_DEVEPTIER_MDATAES (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIER[10]) MData Interrupt Enable */
+#define UOTGHS_DEVEPTIER_DATAXES (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIER[10]) DataX Interrupt Enable */
+#define UOTGHS_DEVEPTIER_ERRORTRANSES (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIER[10]) Transaction Error Interrupt Enable */
+#define UOTGHS_DEVEPTIER_NBUSYBKES (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIER[10]) Number of Busy Banks Interrupt Enable */
+#define UOTGHS_DEVEPTIER_KILLBKS (0x1u << 13) /**< \brief (UOTGHS_DEVEPTIER[10]) Kill IN Bank */
+#define UOTGHS_DEVEPTIER_EPDISHDMAS (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIER[10]) Endpoint Interrupts Disable HDMA Request Enable */
+#define UOTGHS_DEVEPTIER_NYETDISS (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIER[10]) NYET Token Disable Enable */
+#define UOTGHS_DEVEPTIER_RSTDTS (0x1u << 18) /**< \brief (UOTGHS_DEVEPTIER[10]) Reset Data Toggle Enable */
+#define UOTGHS_DEVEPTIER_STALLRQS (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIER[10]) STALL Request Enable */
+/* -------- UOTGHS_DEVEPTIDR[10] : (UOTGHS Offset: 0x220) Device Endpoint Disable Register (n = 0) -------- */
+#define UOTGHS_DEVEPTIDR_TXINEC (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIDR[10]) Transmitted IN Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_RXOUTEC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIDR[10]) Received OUT Data Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_RXSTPEC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIDR[10]) Received SETUP Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_UNDERFEC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIDR[10]) Underflow Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_NAKOUTEC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIDR[10]) NAKed OUT Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_HBISOINERREC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Error Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_NAKINEC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIDR[10]) NAKed IN Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_OVERFEC (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIDR[10]) Overflow Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_STALLEDEC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIDR[10]) STALLed Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_CRCERREC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIDR[10]) CRC Error Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIDR[10]) Shortpacket Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_MDATEC (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIDR[10]) MData Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_DATAXEC (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIDR[10]) DataX Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIDR[10]) Transaction Error Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIDR[10]) Number of Busy Banks Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_FIFOCONC (0x1u << 14) /**< \brief (UOTGHS_DEVEPTIDR[10]) FIFO Control Clear */
+#define UOTGHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIDR[10]) Endpoint Interrupts Disable HDMA Request Clear */
+#define UOTGHS_DEVEPTIDR_NYETDISC (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIDR[10]) NYET Token Disable Clear */
+#define UOTGHS_DEVEPTIDR_STALLRQC (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIDR[10]) STALL Request Clear */
+/* -------- UOTGHS_DEVDMANXTDSC : (UOTGHS Offset: N/A) Device DMA Channel Next Descriptor Address Register -------- */
+#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0
+#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UOTGHS_DEVDMANXTDSC) Next Descriptor Address */
+#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos)))
+/* -------- UOTGHS_DEVDMAADDRESS : (UOTGHS Offset: N/A) Device DMA Channel Address Register -------- */
+#define UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos 0
+#define UOTGHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< \brief (UOTGHS_DEVDMAADDRESS) Buffer Address */
+#define UOTGHS_DEVDMAADDRESS_BUFF_ADD(value) ((UOTGHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos)))
+/* -------- UOTGHS_DEVDMACONTROL : (UOTGHS Offset: N/A) Device DMA Channel Control Register -------- */
+#define UOTGHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_DEVDMACONTROL) Channel Enable Command */
+#define UOTGHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UOTGHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */
+#define UOTGHS_DEVDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UOTGHS_DEVDMACONTROL) End of Transfer Enable Control */
+#define UOTGHS_DEVDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UOTGHS_DEVDMACONTROL) End of Buffer Enable Control */
+#define UOTGHS_DEVDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UOTGHS_DEVDMACONTROL) End of Transfer Interrupt Enable */
+#define UOTGHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UOTGHS_DEVDMACONTROL) End of Buffer Interrupt Enable */
+#define UOTGHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UOTGHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable */
+#define UOTGHS_DEVDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UOTGHS_DEVDMACONTROL) Burst Lock Enable */
+#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16
+#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UOTGHS_DEVDMACONTROL) Buffer Byte Length (Write-only) */
+#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH(value) ((UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos)))
+/* -------- UOTGHS_DEVDMASTATUS : (UOTGHS Offset: N/A) Device DMA Channel Status Register -------- */
+#define UOTGHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_DEVDMASTATUS) Channel Enable Status */
+#define UOTGHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UOTGHS_DEVDMASTATUS) Channel Active Status */
+#define UOTGHS_DEVDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UOTGHS_DEVDMASTATUS) End of Channel Transfer Status */
+#define UOTGHS_DEVDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UOTGHS_DEVDMASTATUS) End of Channel Buffer Status */
+#define UOTGHS_DEVDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UOTGHS_DEVDMASTATUS) Descriptor Loaded Status */
+#define UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos 16
+#define UOTGHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< \brief (UOTGHS_DEVDMASTATUS) Buffer Byte Count */
+#define UOTGHS_DEVDMASTATUS_BUFF_COUNT(value) ((UOTGHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos)))
+/* -------- UOTGHS_HSTCTRL : (UOTGHS Offset: 0x0400) Host General Control Register -------- */
+#define UOTGHS_HSTCTRL_SOFE (0x1u << 8) /**< \brief (UOTGHS_HSTCTRL) Start of Frame Generation Enable */
+#define UOTGHS_HSTCTRL_RESET (0x1u << 9) /**< \brief (UOTGHS_HSTCTRL) Send USB Reset */
+#define UOTGHS_HSTCTRL_RESUME (0x1u << 10) /**< \brief (UOTGHS_HSTCTRL) Send USB Resume */
+#define UOTGHS_HSTCTRL_SPDCONF_Pos 12
+#define UOTGHS_HSTCTRL_SPDCONF_Msk (0x3u << UOTGHS_HSTCTRL_SPDCONF_Pos) /**< \brief (UOTGHS_HSTCTRL) Mode Configuration */
+#define   UOTGHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12) /**< \brief (UOTGHS_HSTCTRL) The host starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the downstream peripheral is high-speed capable. */
+#define   UOTGHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12) /**< \brief (UOTGHS_HSTCTRL) For a better consumption, if high-speed is not needed. */
+#define   UOTGHS_HSTCTRL_SPDCONF_HIGH_SPEED (0x2u << 12) /**< \brief (UOTGHS_HSTCTRL) Forced high speed. */
+#define   UOTGHS_HSTCTRL_SPDCONF_FORCED_FS (0x3u << 12) /**< \brief (UOTGHS_HSTCTRL) The host remains to full-speed mode whatever the peripheral speed capability. */
+/* -------- UOTGHS_HSTISR : (UOTGHS Offset: 0x0404) Host Global Interrupt Status Register -------- */
+#define UOTGHS_HSTISR_DCONNI (0x1u << 0) /**< \brief (UOTGHS_HSTISR) Device Connection Interrupt */
+#define UOTGHS_HSTISR_DDISCI (0x1u << 1) /**< \brief (UOTGHS_HSTISR) Device Disconnection Interrupt */
+#define UOTGHS_HSTISR_RSTI (0x1u << 2) /**< \brief (UOTGHS_HSTISR) USB Reset Sent Interrupt */
+#define UOTGHS_HSTISR_RSMEDI (0x1u << 3) /**< \brief (UOTGHS_HSTISR) Downstream Resume Sent Interrupt */
+#define UOTGHS_HSTISR_RXRSMI (0x1u << 4) /**< \brief (UOTGHS_HSTISR) Upstream Resume Received Interrupt */
+#define UOTGHS_HSTISR_HSOFI (0x1u << 5) /**< \brief (UOTGHS_HSTISR) Host Start of Frame Interrupt */
+#define UOTGHS_HSTISR_HWUPI (0x1u << 6) /**< \brief (UOTGHS_HSTISR) Host Wake-Up Interrupt */
+#define UOTGHS_HSTISR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTISR) Pipe 0 Interrupt */
+#define UOTGHS_HSTISR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTISR) Pipe 1 Interrupt */
+#define UOTGHS_HSTISR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTISR) Pipe 2 Interrupt */
+#define UOTGHS_HSTISR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTISR) Pipe 3 Interrupt */
+#define UOTGHS_HSTISR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTISR) Pipe 4 Interrupt */
+#define UOTGHS_HSTISR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTISR) Pipe 5 Interrupt */
+#define UOTGHS_HSTISR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTISR) Pipe 6 Interrupt */
+#define UOTGHS_HSTISR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTISR) Pipe 7 Interrupt */
+#define UOTGHS_HSTISR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTISR) Pipe 8 Interrupt */
+#define UOTGHS_HSTISR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTISR) Pipe 9 Interrupt */
+#define UOTGHS_HSTISR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTISR) DMA Channel 1 Interrupt */
+#define UOTGHS_HSTISR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTISR) DMA Channel 2 Interrupt */
+#define UOTGHS_HSTISR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTISR) DMA Channel 3 Interrupt */
+#define UOTGHS_HSTISR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTISR) DMA Channel 4 Interrupt */
+#define UOTGHS_HSTISR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTISR) DMA Channel 5 Interrupt */
+#define UOTGHS_HSTISR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTISR) DMA Channel 6 Interrupt */
+/* -------- UOTGHS_HSTICR : (UOTGHS Offset: 0x0408) Host Global Interrupt Clear Register -------- */
+#define UOTGHS_HSTICR_DCONNIC (0x1u << 0) /**< \brief (UOTGHS_HSTICR) Device Connection Interrupt Clear */
+#define UOTGHS_HSTICR_DDISCIC (0x1u << 1) /**< \brief (UOTGHS_HSTICR) Device Disconnection Interrupt Clear */
+#define UOTGHS_HSTICR_RSTIC (0x1u << 2) /**< \brief (UOTGHS_HSTICR) USB Reset Sent Interrupt Clear */
+#define UOTGHS_HSTICR_RSMEDIC (0x1u << 3) /**< \brief (UOTGHS_HSTICR) Downstream Resume Sent Interrupt Clear */
+#define UOTGHS_HSTICR_RXRSMIC (0x1u << 4) /**< \brief (UOTGHS_HSTICR) Upstream Resume Received Interrupt Clear */
+#define UOTGHS_HSTICR_HSOFIC (0x1u << 5) /**< \brief (UOTGHS_HSTICR) Host Start of Frame Interrupt Clear */
+#define UOTGHS_HSTICR_HWUPIC (0x1u << 6) /**< \brief (UOTGHS_HSTICR) Host Wake-Up Interrupt Clear */
+/* -------- UOTGHS_HSTIFR : (UOTGHS Offset: 0x040C) Host Global Interrupt Set Register -------- */
+#define UOTGHS_HSTIFR_DCONNIS (0x1u << 0) /**< \brief (UOTGHS_HSTIFR) Device Connection Interrupt Set */
+#define UOTGHS_HSTIFR_DDISCIS (0x1u << 1) /**< \brief (UOTGHS_HSTIFR) Device Disconnection Interrupt Set */
+#define UOTGHS_HSTIFR_RSTIS (0x1u << 2) /**< \brief (UOTGHS_HSTIFR) USB Reset Sent Interrupt Set */
+#define UOTGHS_HSTIFR_RSMEDIS (0x1u << 3) /**< \brief (UOTGHS_HSTIFR) Downstream Resume Sent Interrupt Set */
+#define UOTGHS_HSTIFR_RXRSMIS (0x1u << 4) /**< \brief (UOTGHS_HSTIFR) Upstream Resume Received Interrupt Set */
+#define UOTGHS_HSTIFR_HSOFIS (0x1u << 5) /**< \brief (UOTGHS_HSTIFR) Host Start of Frame Interrupt Set */
+#define UOTGHS_HSTIFR_HWUPIS (0x1u << 6) /**< \brief (UOTGHS_HSTIFR) Host Wake-Up Interrupt Set */
+#define UOTGHS_HSTIFR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIFR) DMA Channel 1 Interrupt Set */
+#define UOTGHS_HSTIFR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIFR) DMA Channel 2 Interrupt Set */
+#define UOTGHS_HSTIFR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIFR) DMA Channel 3 Interrupt Set */
+#define UOTGHS_HSTIFR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIFR) DMA Channel 4 Interrupt Set */
+#define UOTGHS_HSTIFR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIFR) DMA Channel 5 Interrupt Set */
+#define UOTGHS_HSTIFR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIFR) DMA Channel 6 Interrupt Set */
+/* -------- UOTGHS_HSTIMR : (UOTGHS Offset: 0x0410) Host Global Interrupt Mask Register -------- */
+#define UOTGHS_HSTIMR_DCONNIE (0x1u << 0) /**< \brief (UOTGHS_HSTIMR) Device Connection Interrupt Enable */
+#define UOTGHS_HSTIMR_DDISCIE (0x1u << 1) /**< \brief (UOTGHS_HSTIMR) Device Disconnection Interrupt Enable */
+#define UOTGHS_HSTIMR_RSTIE (0x1u << 2) /**< \brief (UOTGHS_HSTIMR) USB Reset Sent Interrupt Enable */
+#define UOTGHS_HSTIMR_RSMEDIE (0x1u << 3) /**< \brief (UOTGHS_HSTIMR) Downstream Resume Sent Interrupt Enable */
+#define UOTGHS_HSTIMR_RXRSMIE (0x1u << 4) /**< \brief (UOTGHS_HSTIMR) Upstream Resume Received Interrupt Enable */
+#define UOTGHS_HSTIMR_HSOFIE (0x1u << 5) /**< \brief (UOTGHS_HSTIMR) Host Start of Frame Interrupt Enable */
+#define UOTGHS_HSTIMR_HWUPIE (0x1u << 6) /**< \brief (UOTGHS_HSTIMR) Host Wake-Up Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIMR) Pipe 0 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIMR) Pipe 1 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIMR) Pipe 2 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIMR) Pipe 3 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIMR) Pipe 4 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIMR) Pipe 5 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIMR) Pipe 6 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIMR) Pipe 7 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIMR) Pipe 8 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIMR) Pipe 9 Interrupt Enable */
+#define UOTGHS_HSTIMR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIMR) DMA Channel 1 Interrupt Enable */
+#define UOTGHS_HSTIMR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIMR) DMA Channel 2 Interrupt Enable */
+#define UOTGHS_HSTIMR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIMR) DMA Channel 3 Interrupt Enable */
+#define UOTGHS_HSTIMR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIMR) DMA Channel 4 Interrupt Enable */
+#define UOTGHS_HSTIMR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIMR) DMA Channel 5 Interrupt Enable */
+#define UOTGHS_HSTIMR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIMR) DMA Channel 6 Interrupt Enable */
+/* -------- UOTGHS_HSTIDR : (UOTGHS Offset: 0x0414) Host Global Interrupt Disable Register -------- */
+#define UOTGHS_HSTIDR_DCONNIEC (0x1u << 0) /**< \brief (UOTGHS_HSTIDR) Device Connection Interrupt Disable */
+#define UOTGHS_HSTIDR_DDISCIEC (0x1u << 1) /**< \brief (UOTGHS_HSTIDR) Device Disconnection Interrupt Disable */
+#define UOTGHS_HSTIDR_RSTIEC (0x1u << 2) /**< \brief (UOTGHS_HSTIDR) USB Reset Sent Interrupt Disable */
+#define UOTGHS_HSTIDR_RSMEDIEC (0x1u << 3) /**< \brief (UOTGHS_HSTIDR) Downstream Resume Sent Interrupt Disable */
+#define UOTGHS_HSTIDR_RXRSMIEC (0x1u << 4) /**< \brief (UOTGHS_HSTIDR) Upstream Resume Received Interrupt Disable */
+#define UOTGHS_HSTIDR_HSOFIEC (0x1u << 5) /**< \brief (UOTGHS_HSTIDR) Host Start of Frame Interrupt Disable */
+#define UOTGHS_HSTIDR_HWUPIEC (0x1u << 6) /**< \brief (UOTGHS_HSTIDR) Host Wake-Up Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIDR) Pipe 0 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIDR) Pipe 1 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIDR) Pipe 2 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIDR) Pipe 3 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIDR) Pipe 4 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIDR) Pipe 5 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIDR) Pipe 6 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIDR) Pipe 7 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIDR) Pipe 8 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIDR) Pipe 9 Interrupt Disable */
+#define UOTGHS_HSTIDR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIDR) DMA Channel 1 Interrupt Disable */
+#define UOTGHS_HSTIDR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIDR) DMA Channel 2 Interrupt Disable */
+#define UOTGHS_HSTIDR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIDR) DMA Channel 3 Interrupt Disable */
+#define UOTGHS_HSTIDR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIDR) DMA Channel 4 Interrupt Disable */
+#define UOTGHS_HSTIDR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIDR) DMA Channel 5 Interrupt Disable */
+#define UOTGHS_HSTIDR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIDR) DMA Channel 6 Interrupt Disable */
+/* -------- UOTGHS_HSTIER : (UOTGHS Offset: 0x0418) Host Global Interrupt Enable Register -------- */
+#define UOTGHS_HSTIER_DCONNIES (0x1u << 0) /**< \brief (UOTGHS_HSTIER) Device Connection Interrupt Enable */
+#define UOTGHS_HSTIER_DDISCIES (0x1u << 1) /**< \brief (UOTGHS_HSTIER) Device Disconnection Interrupt Enable */
+#define UOTGHS_HSTIER_RSTIES (0x1u << 2) /**< \brief (UOTGHS_HSTIER) USB Reset Sent Interrupt Enable */
+#define UOTGHS_HSTIER_RSMEDIES (0x1u << 3) /**< \brief (UOTGHS_HSTIER) Downstream Resume Sent Interrupt Enable */
+#define UOTGHS_HSTIER_RXRSMIES (0x1u << 4) /**< \brief (UOTGHS_HSTIER) Upstream Resume Received Interrupt Enable */
+#define UOTGHS_HSTIER_HSOFIES (0x1u << 5) /**< \brief (UOTGHS_HSTIER) Host Start of Frame Interrupt Enable */
+#define UOTGHS_HSTIER_HWUPIES (0x1u << 6) /**< \brief (UOTGHS_HSTIER) Host Wake-Up Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIER) Pipe 0 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIER) Pipe 1 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIER) Pipe 2 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIER) Pipe 3 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIER) Pipe 4 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIER) Pipe 5 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIER) Pipe 6 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIER) Pipe 7 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIER) Pipe 8 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIER) Pipe 9 Interrupt Enable */
+#define UOTGHS_HSTIER_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIER) DMA Channel 1 Interrupt Enable */
+#define UOTGHS_HSTIER_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIER) DMA Channel 2 Interrupt Enable */
+#define UOTGHS_HSTIER_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIER) DMA Channel 3 Interrupt Enable */
+#define UOTGHS_HSTIER_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIER) DMA Channel 4 Interrupt Enable */
+#define UOTGHS_HSTIER_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIER) DMA Channel 5 Interrupt Enable */
+#define UOTGHS_HSTIER_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIER) DMA Channel 6 Interrupt Enable */
+/* -------- UOTGHS_HSTPIP : (UOTGHS Offset: 0x0041C) Host Pipe Register -------- */
+#define UOTGHS_HSTPIP_PEN0 (0x1u << 0) /**< \brief (UOTGHS_HSTPIP) Pipe 0 Enable */
+#define UOTGHS_HSTPIP_PEN1 (0x1u << 1) /**< \brief (UOTGHS_HSTPIP) Pipe 1 Enable */
+#define UOTGHS_HSTPIP_PEN2 (0x1u << 2) /**< \brief (UOTGHS_HSTPIP) Pipe 2 Enable */
+#define UOTGHS_HSTPIP_PEN3 (0x1u << 3) /**< \brief (UOTGHS_HSTPIP) Pipe 3 Enable */
+#define UOTGHS_HSTPIP_PEN4 (0x1u << 4) /**< \brief (UOTGHS_HSTPIP) Pipe 4 Enable */
+#define UOTGHS_HSTPIP_PEN5 (0x1u << 5) /**< \brief (UOTGHS_HSTPIP) Pipe 5 Enable */
+#define UOTGHS_HSTPIP_PEN6 (0x1u << 6) /**< \brief (UOTGHS_HSTPIP) Pipe 6 Enable */
+#define UOTGHS_HSTPIP_PEN7 (0x1u << 7) /**< \brief (UOTGHS_HSTPIP) Pipe 7 Enable */
+#define UOTGHS_HSTPIP_PEN8 (0x1u << 8) /**< \brief (UOTGHS_HSTPIP) Pipe 8 Enable */
+#define UOTGHS_HSTPIP_PRST0 (0x1u << 16) /**< \brief (UOTGHS_HSTPIP) Pipe 0 Reset */
+#define UOTGHS_HSTPIP_PRST1 (0x1u << 17) /**< \brief (UOTGHS_HSTPIP) Pipe 1 Reset */
+#define UOTGHS_HSTPIP_PRST2 (0x1u << 18) /**< \brief (UOTGHS_HSTPIP) Pipe 2 Reset */
+#define UOTGHS_HSTPIP_PRST3 (0x1u << 19) /**< \brief (UOTGHS_HSTPIP) Pipe 3 Reset */
+#define UOTGHS_HSTPIP_PRST4 (0x1u << 20) /**< \brief (UOTGHS_HSTPIP) Pipe 4 Reset */
+#define UOTGHS_HSTPIP_PRST5 (0x1u << 21) /**< \brief (UOTGHS_HSTPIP) Pipe 5 Reset */
+#define UOTGHS_HSTPIP_PRST6 (0x1u << 22) /**< \brief (UOTGHS_HSTPIP) Pipe 6 Reset */
+#define UOTGHS_HSTPIP_PRST7 (0x1u << 23) /**< \brief (UOTGHS_HSTPIP) Pipe 7 Reset */
+#define UOTGHS_HSTPIP_PRST8 (0x1u << 24) /**< \brief (UOTGHS_HSTPIP) Pipe 8 Reset */
+/* -------- UOTGHS_HSTFNUM : (UOTGHS Offset: 0x0420) Host Frame Number Register -------- */
+#define UOTGHS_HSTFNUM_MFNUM_Pos 0
+#define UOTGHS_HSTFNUM_MFNUM_Msk (0x7u << UOTGHS_HSTFNUM_MFNUM_Pos) /**< \brief (UOTGHS_HSTFNUM) Micro Frame Number */
+#define UOTGHS_HSTFNUM_MFNUM(value) ((UOTGHS_HSTFNUM_MFNUM_Msk & ((value) << UOTGHS_HSTFNUM_MFNUM_Pos)))
+#define UOTGHS_HSTFNUM_FNUM_Pos 3
+#define UOTGHS_HSTFNUM_FNUM_Msk (0x7ffu << UOTGHS_HSTFNUM_FNUM_Pos) /**< \brief (UOTGHS_HSTFNUM) Frame Number */
+#define UOTGHS_HSTFNUM_FNUM(value) ((UOTGHS_HSTFNUM_FNUM_Msk & ((value) << UOTGHS_HSTFNUM_FNUM_Pos)))
+#define UOTGHS_HSTFNUM_FLENHIGH_Pos 16
+#define UOTGHS_HSTFNUM_FLENHIGH_Msk (0xffu << UOTGHS_HSTFNUM_FLENHIGH_Pos) /**< \brief (UOTGHS_HSTFNUM) Frame Length */
+#define UOTGHS_HSTFNUM_FLENHIGH(value) ((UOTGHS_HSTFNUM_FLENHIGH_Msk & ((value) << UOTGHS_HSTFNUM_FLENHIGH_Pos)))
+/* -------- UOTGHS_HSTADDR1 : (UOTGHS Offset: 0x0424) Host Address 1 Register -------- */
+#define UOTGHS_HSTADDR1_HSTADDRP0_Pos 0
+#define UOTGHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP0_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */
+#define UOTGHS_HSTADDR1_HSTADDRP0(value) ((UOTGHS_HSTADDR1_HSTADDRP0_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP0_Pos)))
+#define UOTGHS_HSTADDR1_HSTADDRP1_Pos 8
+#define UOTGHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP1_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */
+#define UOTGHS_HSTADDR1_HSTADDRP1(value) ((UOTGHS_HSTADDR1_HSTADDRP1_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP1_Pos)))
+#define UOTGHS_HSTADDR1_HSTADDRP2_Pos 16
+#define UOTGHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP2_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */
+#define UOTGHS_HSTADDR1_HSTADDRP2(value) ((UOTGHS_HSTADDR1_HSTADDRP2_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP2_Pos)))
+#define UOTGHS_HSTADDR1_HSTADDRP3_Pos 24
+#define UOTGHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP3_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */
+#define UOTGHS_HSTADDR1_HSTADDRP3(value) ((UOTGHS_HSTADDR1_HSTADDRP3_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP3_Pos)))
+/* -------- UOTGHS_HSTADDR2 : (UOTGHS Offset: 0x0428) Host Address 2 Register -------- */
+#define UOTGHS_HSTADDR2_HSTADDRP4_Pos 0
+#define UOTGHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP4_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */
+#define UOTGHS_HSTADDR2_HSTADDRP4(value) ((UOTGHS_HSTADDR2_HSTADDRP4_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP4_Pos)))
+#define UOTGHS_HSTADDR2_HSTADDRP5_Pos 8
+#define UOTGHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP5_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */
+#define UOTGHS_HSTADDR2_HSTADDRP5(value) ((UOTGHS_HSTADDR2_HSTADDRP5_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP5_Pos)))
+#define UOTGHS_HSTADDR2_HSTADDRP6_Pos 16
+#define UOTGHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP6_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */
+#define UOTGHS_HSTADDR2_HSTADDRP6(value) ((UOTGHS_HSTADDR2_HSTADDRP6_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP6_Pos)))
+#define UOTGHS_HSTADDR2_HSTADDRP7_Pos 24
+#define UOTGHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP7_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */
+#define UOTGHS_HSTADDR2_HSTADDRP7(value) ((UOTGHS_HSTADDR2_HSTADDRP7_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP7_Pos)))
+/* -------- UOTGHS_HSTADDR3 : (UOTGHS Offset: 0x042C) Host Address 3 Register -------- */
+#define UOTGHS_HSTADDR3_HSTADDRP8_Pos 0
+#define UOTGHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << UOTGHS_HSTADDR3_HSTADDRP8_Pos) /**< \brief (UOTGHS_HSTADDR3) USB Host Address */
+#define UOTGHS_HSTADDR3_HSTADDRP8(value) ((UOTGHS_HSTADDR3_HSTADDRP8_Msk & ((value) << UOTGHS_HSTADDR3_HSTADDRP8_Pos)))
+#define UOTGHS_HSTADDR3_HSTADDRP9_Pos 8
+#define UOTGHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << UOTGHS_HSTADDR3_HSTADDRP9_Pos) /**< \brief (UOTGHS_HSTADDR3) USB Host Address */
+#define UOTGHS_HSTADDR3_HSTADDRP9(value) ((UOTGHS_HSTADDR3_HSTADDRP9_Msk & ((value) << UOTGHS_HSTADDR3_HSTADDRP9_Pos)))
+/* -------- UOTGHS_HSTPIPCFG[10] : (UOTGHS Offset: 0x500) Host Pipe Configuration Register (n = 0) -------- */
+#define UOTGHS_HSTPIPCFG_ALLOC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Memory Allocate */
+#define UOTGHS_HSTPIPCFG_PBK_Pos 2
+#define UOTGHS_HSTPIPCFG_PBK_Msk (0x3u << UOTGHS_HSTPIPCFG_PBK_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Banks */
+#define   UOTGHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2) /**< \brief (UOTGHS_HSTPIPCFG[10]) Single-bank pipe */
+#define   UOTGHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2) /**< \brief (UOTGHS_HSTPIPCFG[10]) Double-bank pipe */
+#define   UOTGHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2) /**< \brief (UOTGHS_HSTPIPCFG[10]) Triple-bank pipe */
+#define UOTGHS_HSTPIPCFG_PSIZE_Pos 4
+#define UOTGHS_HSTPIPCFG_PSIZE_Msk (0x7u << UOTGHS_HSTPIPCFG_PSIZE_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Size */
+#define   UOTGHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 8 bytes */
+#define   UOTGHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 16 bytes */
+#define   UOTGHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 32 bytes */
+#define   UOTGHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 64 bytes */
+#define   UOTGHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 128 bytes */
+#define   UOTGHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 256 bytes */
+#define   UOTGHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 512 bytes */
+#define   UOTGHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 1024 bytes */
+#define UOTGHS_HSTPIPCFG_PTOKEN_Pos 8
+#define UOTGHS_HSTPIPCFG_PTOKEN_Msk (0x3u << UOTGHS_HSTPIPCFG_PTOKEN_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Token */
+#define   UOTGHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8) /**< \brief (UOTGHS_HSTPIPCFG[10]) SETUP */
+#define   UOTGHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8) /**< \brief (UOTGHS_HSTPIPCFG[10]) IN */
+#define   UOTGHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8) /**< \brief (UOTGHS_HSTPIPCFG[10]) OUT */
+#define UOTGHS_HSTPIPCFG_AUTOSW (0x1u << 10) /**< \brief (UOTGHS_HSTPIPCFG[10]) Automatic Switch */
+#define UOTGHS_HSTPIPCFG_PTYPE_Pos 12
+#define UOTGHS_HSTPIPCFG_PTYPE_Msk (0x3u << UOTGHS_HSTPIPCFG_PTYPE_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Type */
+#define   UOTGHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12) /**< \brief (UOTGHS_HSTPIPCFG[10]) Control */
+#define   UOTGHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12) /**< \brief (UOTGHS_HSTPIPCFG[10]) Isochronous */
+#define   UOTGHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12) /**< \brief (UOTGHS_HSTPIPCFG[10]) Bulk */
+#define   UOTGHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12) /**< \brief (UOTGHS_HSTPIPCFG[10]) Interrupt */
+#define UOTGHS_HSTPIPCFG_PEPNUM_Pos 16
+#define UOTGHS_HSTPIPCFG_PEPNUM_Msk (0xfu << UOTGHS_HSTPIPCFG_PEPNUM_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Endpoint Number */
+#define UOTGHS_HSTPIPCFG_PEPNUM(value) ((UOTGHS_HSTPIPCFG_PEPNUM_Msk & ((value) << UOTGHS_HSTPIPCFG_PEPNUM_Pos)))
+#define UOTGHS_HSTPIPCFG_PINGEN (0x1u << 20) /**< \brief (UOTGHS_HSTPIPCFG[10]) Ping Enable */
+#define UOTGHS_HSTPIPCFG_INTFRQ_Pos 24
+#define UOTGHS_HSTPIPCFG_INTFRQ_Msk (0xffu << UOTGHS_HSTPIPCFG_INTFRQ_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Interrupt Request Frequency */
+#define UOTGHS_HSTPIPCFG_INTFRQ(value) ((UOTGHS_HSTPIPCFG_INTFRQ_Msk & ((value) << UOTGHS_HSTPIPCFG_INTFRQ_Pos)))
+#define UOTGHS_HSTPIPCFG_BINTERVAL_Pos 24
+#define UOTGHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << UOTGHS_HSTPIPCFG_BINTERVAL_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) bInterval parameter for the Bulk-Out/Ping transaction */
+#define UOTGHS_HSTPIPCFG_BINTERVAL(value) ((UOTGHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << UOTGHS_HSTPIPCFG_BINTERVAL_Pos)))
+/* -------- UOTGHS_HSTPIPISR[10] : (UOTGHS Offset: 0x530) Host Pipe Status Register (n = 0) -------- */
+#define UOTGHS_HSTPIPISR_RXINI (0x1u << 0) /**< \brief (UOTGHS_HSTPIPISR[10]) Received IN Data Interrupt */
+#define UOTGHS_HSTPIPISR_TXOUTI (0x1u << 1) /**< \brief (UOTGHS_HSTPIPISR[10]) Transmitted OUT Data Interrupt */
+#define UOTGHS_HSTPIPISR_TXSTPI (0x1u << 2) /**< \brief (UOTGHS_HSTPIPISR[10]) Transmitted SETUP Interrupt */
+#define UOTGHS_HSTPIPISR_UNDERFI (0x1u << 2) /**< \brief (UOTGHS_HSTPIPISR[10]) Underflow Interrupt */
+#define UOTGHS_HSTPIPISR_PERRI (0x1u << 3) /**< \brief (UOTGHS_HSTPIPISR[10]) Pipe Error Interrupt */
+#define UOTGHS_HSTPIPISR_NAKEDI (0x1u << 4) /**< \brief (UOTGHS_HSTPIPISR[10]) NAKed Interrupt */
+#define UOTGHS_HSTPIPISR_OVERFI (0x1u << 5) /**< \brief (UOTGHS_HSTPIPISR[10]) Overflow Interrupt */
+#define UOTGHS_HSTPIPISR_RXSTALLDI (0x1u << 6) /**< \brief (UOTGHS_HSTPIPISR[10]) Received STALLed Interrupt */
+#define UOTGHS_HSTPIPISR_CRCERRI (0x1u << 6) /**< \brief (UOTGHS_HSTPIPISR[10]) CRC Error Interrupt */
+#define UOTGHS_HSTPIPISR_SHORTPACKETI (0x1u << 7) /**< \brief (UOTGHS_HSTPIPISR[10]) Short Packet Interrupt */
+#define UOTGHS_HSTPIPISR_DTSEQ_Pos 8
+#define UOTGHS_HSTPIPISR_DTSEQ_Msk (0x3u << UOTGHS_HSTPIPISR_DTSEQ_Pos) /**< \brief (UOTGHS_HSTPIPISR[10]) Data Toggle Sequence */
+#define   UOTGHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (UOTGHS_HSTPIPISR[10]) Data0 toggle sequence */
+#define   UOTGHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (UOTGHS_HSTPIPISR[10]) Data1 toggle sequence */
+#define UOTGHS_HSTPIPISR_NBUSYBK_Pos 12
+#define UOTGHS_HSTPIPISR_NBUSYBK_Msk (0x3u << UOTGHS_HSTPIPISR_NBUSYBK_Pos) /**< \brief (UOTGHS_HSTPIPISR[10]) Number of Busy Banks */
+#define   UOTGHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (UOTGHS_HSTPIPISR[10]) 0 busy bank (all banks free) */
+#define   UOTGHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (UOTGHS_HSTPIPISR[10]) 1 busy bank */
+#define   UOTGHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (UOTGHS_HSTPIPISR[10]) 2 busy banks */
+#define   UOTGHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (UOTGHS_HSTPIPISR[10]) 3 busy banks */
+#define UOTGHS_HSTPIPISR_CURRBK_Pos 14
+#define UOTGHS_HSTPIPISR_CURRBK_Msk (0x3u << UOTGHS_HSTPIPISR_CURRBK_Pos) /**< \brief (UOTGHS_HSTPIPISR[10]) Current Bank */
+#define   UOTGHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (UOTGHS_HSTPIPISR[10]) Current bank is bank0 */
+#define   UOTGHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (UOTGHS_HSTPIPISR[10]) Current bank is bank1 */
+#define   UOTGHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (UOTGHS_HSTPIPISR[10]) Current bank is bank2 */
+#define UOTGHS_HSTPIPISR_RWALL (0x1u << 16) /**< \brief (UOTGHS_HSTPIPISR[10]) Read-write Allowed */
+#define UOTGHS_HSTPIPISR_CFGOK (0x1u << 18) /**< \brief (UOTGHS_HSTPIPISR[10]) Configuration OK Status */
+#define UOTGHS_HSTPIPISR_PBYCT_Pos 20
+#define UOTGHS_HSTPIPISR_PBYCT_Msk (0x7ffu << UOTGHS_HSTPIPISR_PBYCT_Pos) /**< \brief (UOTGHS_HSTPIPISR[10]) Pipe Byte Count */
+/* -------- UOTGHS_HSTPIPICR[10] : (UOTGHS Offset: 0x560) Host Pipe Clear Register (n = 0) -------- */
+#define UOTGHS_HSTPIPICR_RXINIC (0x1u << 0) /**< \brief (UOTGHS_HSTPIPICR[10]) Received IN Data Interrupt Clear */
+#define UOTGHS_HSTPIPICR_TXOUTIC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPICR[10]) Transmitted OUT Data Interrupt Clear */
+#define UOTGHS_HSTPIPICR_TXSTPIC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPICR[10]) Transmitted SETUP Interrupt Clear */
+#define UOTGHS_HSTPIPICR_UNDERFIC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPICR[10]) Underflow Interrupt Clear */
+#define UOTGHS_HSTPIPICR_NAKEDIC (0x1u << 4) /**< \brief (UOTGHS_HSTPIPICR[10]) NAKed Interrupt Clear */
+#define UOTGHS_HSTPIPICR_OVERFIC (0x1u << 5) /**< \brief (UOTGHS_HSTPIPICR[10]) Overflow Interrupt Clear */
+#define UOTGHS_HSTPIPICR_RXSTALLDIC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPICR[10]) Received STALLed Interrupt Clear */
+#define UOTGHS_HSTPIPICR_CRCERRIC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPICR[10]) CRC Error Interrupt Clear */
+#define UOTGHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7) /**< \brief (UOTGHS_HSTPIPICR[10]) Short Packet Interrupt Clear */
+/* -------- UOTGHS_HSTPIPIFR[10] : (UOTGHS Offset: 0x590) Host Pipe Set Register (n = 0) -------- */
+#define UOTGHS_HSTPIPIFR_RXINIS (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIFR[10]) Received IN Data Interrupt Set */
+#define UOTGHS_HSTPIPIFR_TXOUTIS (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIFR[10]) Transmitted OUT Data Interrupt Set */
+#define UOTGHS_HSTPIPIFR_TXSTPIS (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIFR[10]) Transmitted SETUP Interrupt Set */
+#define UOTGHS_HSTPIPIFR_UNDERFIS (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIFR[10]) Underflow Interrupt Set */
+#define UOTGHS_HSTPIPIFR_PERRIS (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIFR[10]) Pipe Error Interrupt Set */
+#define UOTGHS_HSTPIPIFR_NAKEDIS (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIFR[10]) NAKed Interrupt Set */
+#define UOTGHS_HSTPIPIFR_OVERFIS (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIFR[10]) Overflow Interrupt Set */
+#define UOTGHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIFR[10]) Received STALLed Interrupt Set */
+#define UOTGHS_HSTPIPIFR_CRCERRIS (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIFR[10]) CRC Error Interrupt Set */
+#define UOTGHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIFR[10]) Short Packet Interrupt Set */
+#define UOTGHS_HSTPIPIFR_NBUSYBKS (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIFR[10]) Number of Busy Banks Set */
+/* -------- UOTGHS_HSTPIPIMR[10] : (UOTGHS Offset: 0x5C0) Host Pipe Mask Register (n = 0) -------- */
+#define UOTGHS_HSTPIPIMR_RXINE (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIMR[10]) Received IN Data Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_TXOUTE (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIMR[10]) Transmitted OUT Data Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_TXSTPE (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIMR[10]) Transmitted SETUP Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_UNDERFIE (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIMR[10]) Underflow Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_PERRE (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIMR[10]) Pipe Error Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_NAKEDE (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIMR[10]) NAKed Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_OVERFIE (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIMR[10]) Overflow Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_RXSTALLDE (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIMR[10]) Received STALLed Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_CRCERRE (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIMR[10]) CRC Error Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIMR[10]) Short Packet Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_NBUSYBKE (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIMR[10]) Number of Busy Banks Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_FIFOCON (0x1u << 14) /**< \brief (UOTGHS_HSTPIPIMR[10]) FIFO Control */
+#define UOTGHS_HSTPIPIMR_PDISHDMA (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIMR[10]) Pipe Interrupts Disable HDMA Request Enable */
+#define UOTGHS_HSTPIPIMR_PFREEZE (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIMR[10]) Pipe Freeze */
+#define UOTGHS_HSTPIPIMR_RSTDT (0x1u << 18) /**< \brief (UOTGHS_HSTPIPIMR[10]) Reset Data Toggle */
+/* -------- UOTGHS_HSTPIPIER[10] : (UOTGHS Offset: 0x5F0) Host Pipe Enable Register (n = 0) -------- */
+#define UOTGHS_HSTPIPIER_RXINES (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIER[10]) Received IN Data Interrupt Enable */
+#define UOTGHS_HSTPIPIER_TXOUTES (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIER[10]) Transmitted OUT Data Interrupt Enable */
+#define UOTGHS_HSTPIPIER_TXSTPES (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIER[10]) Transmitted SETUP Interrupt Enable */
+#define UOTGHS_HSTPIPIER_UNDERFIES (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIER[10]) Underflow Interrupt Enable */
+#define UOTGHS_HSTPIPIER_PERRES (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIER[10]) Pipe Error Interrupt Enable */
+#define UOTGHS_HSTPIPIER_NAKEDES (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIER[10]) NAKed Interrupt Enable */
+#define UOTGHS_HSTPIPIER_OVERFIES (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIER[10]) Overflow Interrupt Enable */
+#define UOTGHS_HSTPIPIER_RXSTALLDES (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIER[10]) Received STALLed Interrupt Enable */
+#define UOTGHS_HSTPIPIER_CRCERRES (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIER[10]) CRC Error Interrupt Enable */
+#define UOTGHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIER[10]) Short Packet Interrupt Enable */
+#define UOTGHS_HSTPIPIER_NBUSYBKES (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIER[10]) Number of Busy Banks Enable */
+#define UOTGHS_HSTPIPIER_PDISHDMAS (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIER[10]) Pipe Interrupts Disable HDMA Request Enable */
+#define UOTGHS_HSTPIPIER_PFREEZES (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIER[10]) Pipe Freeze Enable */
+#define UOTGHS_HSTPIPIER_RSTDTS (0x1u << 18) /**< \brief (UOTGHS_HSTPIPIER[10]) Reset Data Toggle Enable */
+/* -------- UOTGHS_HSTPIPIDR[10] : (UOTGHS Offset: 0x620) Host Pipe Disable Register (n = 0) -------- */
+#define UOTGHS_HSTPIPIDR_RXINEC (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIDR[10]) Received IN Data Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_TXOUTEC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIDR[10]) Transmitted OUT Data Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_TXSTPEC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIDR[10]) Transmitted SETUP Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_UNDERFIEC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIDR[10]) Underflow Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_PERREC (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIDR[10]) Pipe Error Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_NAKEDEC (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIDR[10]) NAKed Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_OVERFIEC (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIDR[10]) Overflow Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIDR[10]) Received STALLed Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_CRCERREC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIDR[10]) CRC Error Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIDR[10]) Short Packet Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIDR[10]) Number of Busy Banks Disable */
+#define UOTGHS_HSTPIPIDR_FIFOCONC (0x1u << 14) /**< \brief (UOTGHS_HSTPIPIDR[10]) FIFO Control Disable */
+#define UOTGHS_HSTPIPIDR_PDISHDMAC (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIDR[10]) Pipe Interrupts Disable HDMA Request Disable */
+#define UOTGHS_HSTPIPIDR_PFREEZEC (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIDR[10]) Pipe Freeze Disable */
+/* -------- UOTGHS_HSTPIPINRQ[10] : (UOTGHS Offset: 0x650) Host Pipe IN Request Register (n = 0) -------- */
+#define UOTGHS_HSTPIPINRQ_INRQ_Pos 0
+#define UOTGHS_HSTPIPINRQ_INRQ_Msk (0xffu << UOTGHS_HSTPIPINRQ_INRQ_Pos) /**< \brief (UOTGHS_HSTPIPINRQ[10]) IN Request Number before Freeze */
+#define UOTGHS_HSTPIPINRQ_INRQ(value) ((UOTGHS_HSTPIPINRQ_INRQ_Msk & ((value) << UOTGHS_HSTPIPINRQ_INRQ_Pos)))
+#define UOTGHS_HSTPIPINRQ_INMODE (0x1u << 8) /**< \brief (UOTGHS_HSTPIPINRQ[10]) IN Request Mode */
+/* -------- UOTGHS_HSTPIPERR[10] : (UOTGHS Offset: 0x680) Host Pipe Error Register (n = 0) -------- */
+#define UOTGHS_HSTPIPERR_DATATGL (0x1u << 0) /**< \brief (UOTGHS_HSTPIPERR[10]) Data Toggle Error */
+#define UOTGHS_HSTPIPERR_DATAPID (0x1u << 1) /**< \brief (UOTGHS_HSTPIPERR[10]) Data PID Error */
+#define UOTGHS_HSTPIPERR_PID (0x1u << 2) /**< \brief (UOTGHS_HSTPIPERR[10]) PID Error */
+#define UOTGHS_HSTPIPERR_TIMEOUT (0x1u << 3) /**< \brief (UOTGHS_HSTPIPERR[10]) Time-Out Error */
+#define UOTGHS_HSTPIPERR_CRC16 (0x1u << 4) /**< \brief (UOTGHS_HSTPIPERR[10]) CRC16 Error */
+#define UOTGHS_HSTPIPERR_COUNTER_Pos 5
+#define UOTGHS_HSTPIPERR_COUNTER_Msk (0x3u << UOTGHS_HSTPIPERR_COUNTER_Pos) /**< \brief (UOTGHS_HSTPIPERR[10]) Error Counter */
+#define UOTGHS_HSTPIPERR_COUNTER(value) ((UOTGHS_HSTPIPERR_COUNTER_Msk & ((value) << UOTGHS_HSTPIPERR_COUNTER_Pos)))
+/* -------- UOTGHS_HSTDMANXTDSC : (UOTGHS Offset: N/A) Host DMA Channel Next Descriptor Address Register -------- */
+#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0
+#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UOTGHS_HSTDMANXTDSC) Next Descriptor Address */
+#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos)))
+/* -------- UOTGHS_HSTDMAADDRESS : (UOTGHS Offset: N/A) Host DMA Channel Address Register -------- */
+#define UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos 0
+#define UOTGHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< \brief (UOTGHS_HSTDMAADDRESS) Buffer Address */
+#define UOTGHS_HSTDMAADDRESS_BUFF_ADD(value) ((UOTGHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos)))
+/* -------- UOTGHS_HSTDMACONTROL : (UOTGHS Offset: N/A) Host DMA Channel Control Register -------- */
+#define UOTGHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_HSTDMACONTROL) Channel Enable Command */
+#define UOTGHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UOTGHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */
+#define UOTGHS_HSTDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UOTGHS_HSTDMACONTROL) End of Transfer Enable (Control) */
+#define UOTGHS_HSTDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UOTGHS_HSTDMACONTROL) End of Buffer Enable Control */
+#define UOTGHS_HSTDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UOTGHS_HSTDMACONTROL) End of Transfer Interrupt Enable */
+#define UOTGHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UOTGHS_HSTDMACONTROL) End of Buffer Interrupt Enable */
+#define UOTGHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UOTGHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable */
+#define UOTGHS_HSTDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UOTGHS_HSTDMACONTROL) Burst Lock Enable */
+#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16
+#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UOTGHS_HSTDMACONTROL) Buffer Byte Length (Write-only) */
+#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH(value) ((UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos)))
+/* -------- UOTGHS_HSTDMASTATUS : (UOTGHS Offset: N/A) Host DMA Channel Status Register -------- */
+#define UOTGHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_HSTDMASTATUS) Channel Enable Status */
+#define UOTGHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UOTGHS_HSTDMASTATUS) Channel Active Status */
+#define UOTGHS_HSTDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UOTGHS_HSTDMASTATUS) End of Channel Transfer Status */
+#define UOTGHS_HSTDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UOTGHS_HSTDMASTATUS) End of Channel Buffer Status */
+#define UOTGHS_HSTDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UOTGHS_HSTDMASTATUS) Descriptor Loaded Status */
+#define UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos 16
+#define UOTGHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< \brief (UOTGHS_HSTDMASTATUS) Buffer Byte Count */
+#define UOTGHS_HSTDMASTATUS_BUFF_COUNT(value) ((UOTGHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos)))
+/* -------- UOTGHS_CTRL : (UOTGHS Offset: 0x0800) General Control Register -------- */
+#define UOTGHS_CTRL_IDTE (0x1u << 0) /**< \brief (UOTGHS_CTRL) ID Transition Interrupt Enable */
+#define UOTGHS_CTRL_VBUSTE (0x1u << 1) /**< \brief (UOTGHS_CTRL) VBus Transition Interrupt Enable */
+#define UOTGHS_CTRL_SRPE (0x1u << 2) /**< \brief (UOTGHS_CTRL) SRP Interrupt Enable */
+#define UOTGHS_CTRL_VBERRE (0x1u << 3) /**< \brief (UOTGHS_CTRL) VBus Error Interrupt Enable */
+#define UOTGHS_CTRL_BCERRE (0x1u << 4) /**< \brief (UOTGHS_CTRL) B-Connection Error Interrupt Enable */
+#define UOTGHS_CTRL_ROLEEXE (0x1u << 5) /**< \brief (UOTGHS_CTRL) Role Exchange Interrupt Enable */
+#define UOTGHS_CTRL_HNPERRE (0x1u << 6) /**< \brief (UOTGHS_CTRL) HNP Error Interrupt Enable */
+#define UOTGHS_CTRL_STOE (0x1u << 7) /**< \brief (UOTGHS_CTRL) Suspend Time-Out Interrupt Enable */
+#define UOTGHS_CTRL_VBUSHWC (0x1u << 8) /**< \brief (UOTGHS_CTRL) VBus Hardware Control */
+#define UOTGHS_CTRL_SRPSEL (0x1u << 9) /**< \brief (UOTGHS_CTRL) SRP Selection */
+#define UOTGHS_CTRL_SRPREQ (0x1u << 10) /**< \brief (UOTGHS_CTRL) SRP Request */
+#define UOTGHS_CTRL_HNPREQ (0x1u << 11) /**< \brief (UOTGHS_CTRL) HNP Request */
+#define UOTGHS_CTRL_OTGPADE (0x1u << 12) /**< \brief (UOTGHS_CTRL) OTG Pad Enable */
+#define UOTGHS_CTRL_VBUSPO (0x1u << 13) /**< \brief (UOTGHS_CTRL) VBus Polarity Off */
+#define UOTGHS_CTRL_FRZCLK (0x1u << 14) /**< \brief (UOTGHS_CTRL) Freeze USB Clock */
+#define UOTGHS_CTRL_USBE (0x1u << 15) /**< \brief (UOTGHS_CTRL) UOTGHS Enable */
+#define UOTGHS_CTRL_TIMVALUE_Pos 16
+#define UOTGHS_CTRL_TIMVALUE_Msk (0x3u << UOTGHS_CTRL_TIMVALUE_Pos) /**< \brief (UOTGHS_CTRL) Timer Value */
+#define UOTGHS_CTRL_TIMVALUE(value) ((UOTGHS_CTRL_TIMVALUE_Msk & ((value) << UOTGHS_CTRL_TIMVALUE_Pos)))
+#define UOTGHS_CTRL_TIMPAGE_Pos 20
+#define UOTGHS_CTRL_TIMPAGE_Msk (0x3u << UOTGHS_CTRL_TIMPAGE_Pos) /**< \brief (UOTGHS_CTRL) Timer Page */
+#define UOTGHS_CTRL_TIMPAGE(value) ((UOTGHS_CTRL_TIMPAGE_Msk & ((value) << UOTGHS_CTRL_TIMPAGE_Pos)))
+#define UOTGHS_CTRL_UNLOCK (0x1u << 22) /**< \brief (UOTGHS_CTRL) Timer Access Unlock */
+#define UOTGHS_CTRL_UIDE (0x1u << 24) /**< \brief (UOTGHS_CTRL) UOTGID Pin Enable */
+#define   UOTGHS_CTRL_UIDE_UIMOD (0x0u << 24) /**< \brief (UOTGHS_CTRL) The USB mode (device/host) is selected from the UIMOD bit. */
+#define   UOTGHS_CTRL_UIDE_UOTGID (0x1u << 24) /**< \brief (UOTGHS_CTRL) The USB mode (device/host) is selected from the UOTGID input pin. */
+#define UOTGHS_CTRL_UIMOD (0x1u << 25) /**< \brief (UOTGHS_CTRL) UOTGHS Mode */
+#define   UOTGHS_CTRL_UIMOD_Host (0x0u << 25) /**< \brief (UOTGHS_CTRL) The module is in USB host mode. */
+#define   UOTGHS_CTRL_UIMOD_Device (0x1u << 25) /**< \brief (UOTGHS_CTRL) The module is in USB device mode. */
+/* -------- UOTGHS_SR : (UOTGHS Offset: 0x0804) General Status Register -------- */
+#define UOTGHS_SR_IDTI (0x1u << 0) /**< \brief (UOTGHS_SR) ID Transition Interrupt */
+#define UOTGHS_SR_VBUSTI (0x1u << 1) /**< \brief (UOTGHS_SR) VBus Transition Interrupt */
+#define UOTGHS_SR_SRPI (0x1u << 2) /**< \brief (UOTGHS_SR) SRP Interrupt */
+#define UOTGHS_SR_VBERRI (0x1u << 3) /**< \brief (UOTGHS_SR) VBus Error Interrupt */
+#define UOTGHS_SR_BCERRI (0x1u << 4) /**< \brief (UOTGHS_SR) B-Connection Error Interrupt */
+#define UOTGHS_SR_ROLEEXI (0x1u << 5) /**< \brief (UOTGHS_SR) Role Exchange Interrupt */
+#define UOTGHS_SR_HNPERRI (0x1u << 6) /**< \brief (UOTGHS_SR) HNP Error Interrupt */
+#define UOTGHS_SR_STOI (0x1u << 7) /**< \brief (UOTGHS_SR) Suspend Time-Out Interrupt */
+#define UOTGHS_SR_VBUSRQ (0x1u << 9) /**< \brief (UOTGHS_SR) VBus Request */
+#define UOTGHS_SR_ID (0x1u << 10) /**< \brief (UOTGHS_SR) UOTGID Pin State */
+#define UOTGHS_SR_VBUS (0x1u << 11) /**< \brief (UOTGHS_SR) VBus Level */
+#define UOTGHS_SR_SPEED_Pos 12
+#define UOTGHS_SR_SPEED_Msk (0x3u << UOTGHS_SR_SPEED_Pos) /**< \brief (UOTGHS_SR) Speed Status */
+#define   UOTGHS_SR_SPEED_FULL_SPEED (0x0u << 12) /**< \brief (UOTGHS_SR) Full-Speed mode */
+#define   UOTGHS_SR_SPEED_HIGH_SPEED (0x1u << 12) /**< \brief (UOTGHS_SR) High-Speed mode */
+#define   UOTGHS_SR_SPEED_LOW_SPEED (0x2u << 12) /**< \brief (UOTGHS_SR) Low-Speed mode */
+#define UOTGHS_SR_CLKUSABLE (0x1u << 14) /**< \brief (UOTGHS_SR) UTMI Clock Usable */
+/* -------- UOTGHS_SCR : (UOTGHS Offset: 0x0808) General Status Clear Register -------- */
+#define UOTGHS_SCR_IDTIC (0x1u << 0) /**< \brief (UOTGHS_SCR) ID Transition Interrupt Clear */
+#define UOTGHS_SCR_VBUSTIC (0x1u << 1) /**< \brief (UOTGHS_SCR) VBus Transition Interrupt Clear */
+#define UOTGHS_SCR_SRPIC (0x1u << 2) /**< \brief (UOTGHS_SCR) SRP Interrupt Clear */
+#define UOTGHS_SCR_VBERRIC (0x1u << 3) /**< \brief (UOTGHS_SCR) VBus Error Interrupt Clear */
+#define UOTGHS_SCR_BCERRIC (0x1u << 4) /**< \brief (UOTGHS_SCR) B-Connection Error Interrupt Clear */
+#define UOTGHS_SCR_ROLEEXIC (0x1u << 5) /**< \brief (UOTGHS_SCR) Role Exchange Interrupt Clear */
+#define UOTGHS_SCR_HNPERRIC (0x1u << 6) /**< \brief (UOTGHS_SCR) HNP Error Interrupt Clear */
+#define UOTGHS_SCR_STOIC (0x1u << 7) /**< \brief (UOTGHS_SCR) Suspend Time-Out Interrupt Clear */
+#define UOTGHS_SCR_VBUSRQC (0x1u << 9) /**< \brief (UOTGHS_SCR) VBus Request Clear */
+/* -------- UOTGHS_SFR : (UOTGHS Offset: 0x080C) General Status Set Register -------- */
+#define UOTGHS_SFR_IDTIS (0x1u << 0) /**< \brief (UOTGHS_SFR) ID Transition Interrupt Set */
+#define UOTGHS_SFR_VBUSTIS (0x1u << 1) /**< \brief (UOTGHS_SFR) VBus Transition Interrupt Set */
+#define UOTGHS_SFR_SRPIS (0x1u << 2) /**< \brief (UOTGHS_SFR) SRP Interrupt Set */
+#define UOTGHS_SFR_VBERRIS (0x1u << 3) /**< \brief (UOTGHS_SFR) VBus Error Interrupt Set */
+#define UOTGHS_SFR_BCERRIS (0x1u << 4) /**< \brief (UOTGHS_SFR) B-Connection Error Interrupt Set */
+#define UOTGHS_SFR_ROLEEXIS (0x1u << 5) /**< \brief (UOTGHS_SFR) Role Exchange Interrupt Set */
+#define UOTGHS_SFR_HNPERRIS (0x1u << 6) /**< \brief (UOTGHS_SFR) HNP Error Interrupt Set */
+#define UOTGHS_SFR_STOIS (0x1u << 7) /**< \brief (UOTGHS_SFR) Suspend Time-Out Interrupt Set */
+#define UOTGHS_SFR_VBUSRQS (0x1u << 9) /**< \brief (UOTGHS_SFR) VBus Request Set */
+/* -------- UOTGHS_FSM : (UOTGHS Offset: 0x082C) General Finite State Machine Register -------- */
+#define UOTGHS_FSM_DRDSTATE_Pos 0
+#define UOTGHS_FSM_DRDSTATE_Msk (0xfu << UOTGHS_FSM_DRDSTATE_Pos) /**< \brief (UOTGHS_FSM)  */
+#define   UOTGHS_FSM_DRDSTATE_A_IDLESTATE (0x0u << 0) /**< \brief (UOTGHS_FSM) This is the start state for A-devices (when the ID pin is 0) */
+#define   UOTGHS_FSM_DRDSTATE_A_WAIT_VRISE (0x1u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V). */
+#define   UOTGHS_FSM_DRDSTATE_A_WAIT_BCON (0x2u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the B-device to signal a connection. */
+#define   UOTGHS_FSM_DRDSTATE_A_HOST (0x3u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device that operates in Host mode is operational. */
+#define   UOTGHS_FSM_DRDSTATE_A_SUSPEND (0x4u << 0) /**< \brief (UOTGHS_FSM) The A-device operating as a host is in the suspend mode. */
+#define   UOTGHS_FSM_DRDSTATE_A_PERIPHERAL (0x5u << 0) /**< \brief (UOTGHS_FSM) The A-device operates as a peripheral. */
+#define   UOTGHS_FSM_DRDSTATE_A_WAIT_VFALL (0x6u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V). */
+#define   UOTGHS_FSM_DRDSTATE_A_VBUS_ERR (0x7u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state. */
+#define   UOTGHS_FSM_DRDSTATE_A_WAIT_DISCHARGE (0x8u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the data USB line to discharge (100 us). */
+#define   UOTGHS_FSM_DRDSTATE_B_IDLE (0x9u << 0) /**< \brief (UOTGHS_FSM) This is the start state for B-device (when the ID pin is 1). */
+#define   UOTGHS_FSM_DRDSTATE_B_PERIPHERAL (0xAu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device acts as the peripheral. */
+#define   UOTGHS_FSM_DRDSTATE_B_WAIT_BEGIN_HNP (0xBu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device is in suspend mode and waits until 3 ms before initiating the HNP protocol if requested. */
+#define   UOTGHS_FSM_DRDSTATE_B_WAIT_DISCHARGE (0xCu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device waits for the data USB line to discharge (100 us) before becoming Host. */
+#define   UOTGHS_FSM_DRDSTATE_B_WAIT_ACON (0xDu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. */
+#define   UOTGHS_FSM_DRDSTATE_B_HOST (0xEu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device acts as the Host. */
+#define   UOTGHS_FSM_DRDSTATE_B_SRP_INIT (0xFu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device attempts to start a session using the SRP protocol. */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_UOTGHS_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_usart.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_usart.h
new file mode 100644
index 000000000..4e9ad8e8e
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_usart.h
@@ -0,0 +1,396 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_USART_COMPONENT_
+#define _SAM3XA_USART_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_USART Universal Synchronous Asynchronous Receiver Transmitter */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Usart hardware registers */
+typedef struct {
+  WoReg US_CR;         /**< \brief (Usart Offset: 0x0000) Control Register */
+  RwReg US_MR;         /**< \brief (Usart Offset: 0x0004) Mode Register */
+  WoReg US_IER;        /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */
+  WoReg US_IDR;        /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */
+  RoReg US_IMR;        /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */
+  RoReg US_CSR;        /**< \brief (Usart Offset: 0x0014) Channel Status Register */
+  RoReg US_RHR;        /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */
+  WoReg US_THR;        /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */
+  RwReg US_BRGR;       /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */
+  RwReg US_RTOR;       /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */
+  RwReg US_TTGR;       /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */
+  RoReg Reserved1[5];
+  RwReg US_FIDI;       /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */
+  RoReg US_NER;        /**< \brief (Usart Offset: 0x0044) Number of Errors Register */
+  RoReg Reserved2[1];
+  RwReg US_IF;         /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */
+  RwReg US_MAN;        /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */
+  RwReg US_LINMR;      /**< \brief (Usart Offset: 0x0054) LIN Mode Register */
+  RwReg US_LINIR;      /**< \brief (Usart Offset: 0x0058) LIN Identifier Register */
+  RoReg Reserved3[34];
+  RwReg US_WPMR;       /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */
+  RoReg US_WPSR;       /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved4[5];
+  RwReg US_RPR;        /**< \brief (Usart Offset: 0x100) Receive Pointer Register */
+  RwReg US_RCR;        /**< \brief (Usart Offset: 0x104) Receive Counter Register */
+  RwReg US_TPR;        /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */
+  RwReg US_TCR;        /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */
+  RwReg US_RNPR;       /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */
+  RwReg US_RNCR;       /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */
+  RwReg US_TNPR;       /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */
+  RwReg US_TNCR;       /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */
+  WoReg US_PTCR;       /**< \brief (Usart Offset: 0x120) Transfer Control Register */
+  RoReg US_PTSR;       /**< \brief (Usart Offset: 0x124) Transfer Status Register */
+} Usart;
+#endif /* __ASSEMBLY__ */
+/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
+#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */
+#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */
+#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */
+#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */
+#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */
+#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */
+#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */
+#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */
+#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */
+#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */
+#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */
+#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */
+#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */
+#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */
+#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */
+#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */
+#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */
+#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */
+#define US_CR_LINABT (0x1u << 20) /**< \brief (US_CR) Abort LIN Transmission */
+#define US_CR_LINWKUP (0x1u << 21) /**< \brief (US_CR) Send LIN Wakeup Signal */
+/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
+#define US_MR_USART_MODE_Pos 0
+#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR)  */
+#define   US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */
+#define   US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */
+#define   US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */
+#define   US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */
+#define   US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */
+#define   US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */
+#define   US_MR_USART_MODE_LIN_MASTER (0xAu << 0) /**< \brief (US_MR) LIN Master */
+#define   US_MR_USART_MODE_LIN_SLAVE (0xBu << 0) /**< \brief (US_MR) LIN Slave */
+#define   US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */
+#define   US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */
+#define US_MR_USCLKS_Pos 4
+#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */
+#define   US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */
+#define   US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */
+#define   US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */
+#define US_MR_CHRL_Pos 6
+#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */
+#define   US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */
+#define   US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */
+#define   US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */
+#define   US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */
+#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */
+#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */
+#define US_MR_PAR_Pos 9
+#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */
+#define   US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */
+#define   US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */
+#define   US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */
+#define   US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */
+#define   US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */
+#define   US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */
+#define US_MR_NBSTOP_Pos 12
+#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */
+#define   US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */
+#define   US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */
+#define   US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */
+#define US_MR_CHMODE_Pos 14
+#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */
+#define   US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */
+#define   US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */
+#define   US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */
+#define   US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */
+#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */
+#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */
+#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */
+#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */
+#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */
+#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */
+#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */
+#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */
+#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) INverted Data */
+#define US_MR_MAX_ITERATION_Pos 24
+#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR)  */
+#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))
+#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */
+#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */
+#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */
+#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */
+/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
+#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */
+#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */
+#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */
+#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */
+#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */
+#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */
+#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */
+#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */
+#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */
+#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */
+#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached */
+#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error */
+#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */
+#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */
+#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */
+#define US_IER_LINBK (0x1u << 13) /**< \brief (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable */
+#define US_IER_LINID (0x1u << 14) /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */
+#define US_IER_LINTC (0x1u << 15) /**< \brief (US_IER) LIN Transfer Completed Interrupt Enable */
+#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
+#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */
+#define US_IER_LINBE (0x1u << 25) /**< \brief (US_IER) LIN Bus Error Interrupt Enable */
+#define US_IER_LINISFE (0x1u << 26) /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */
+#define US_IER_LINIPE (0x1u << 27) /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */
+#define US_IER_LINCE (0x1u << 28) /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */
+#define US_IER_LINSNRE (0x1u << 29) /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */
+/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
+#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */
+#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */
+#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */
+#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */
+#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */
+#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */
+#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */
+#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */
+#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */
+#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */
+#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max number of Repetitions Reached Disable */
+#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Disable */
+#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */
+#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */
+#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */
+#define US_IDR_LINBK (0x1u << 13) /**< \brief (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable */
+#define US_IDR_LINID (0x1u << 14) /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */
+#define US_IDR_LINTC (0x1u << 15) /**< \brief (US_IDR) LIN Transfer Completed Interrupt Disable */
+#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
+#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */
+#define US_IDR_LINBE (0x1u << 25) /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */
+#define US_IDR_LINISFE (0x1u << 26) /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */
+#define US_IDR_LINIPE (0x1u << 27) /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */
+#define US_IDR_LINCE (0x1u << 28) /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */
+#define US_IDR_LINSNRE (0x1u << 29) /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */
+/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
+#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */
+#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */
+#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */
+#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */
+#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */
+#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */
+#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */
+#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */
+#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */
+#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
+#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max number of Repetitions Reached Mask */
+#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Mask */
+#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */
+#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */
+#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */
+#define US_IMR_LINBK (0x1u << 13) /**< \brief (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask */
+#define US_IMR_LINID (0x1u << 14) /**< \brief (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask */
+#define US_IMR_LINTC (0x1u << 15) /**< \brief (US_IMR) LIN Transfer Completed Interrupt Mask */
+#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
+#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */
+#define US_IMR_LINBE (0x1u << 25) /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */
+#define US_IMR_LINISFE (0x1u << 26) /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */
+#define US_IMR_LINIPE (0x1u << 27) /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */
+#define US_IMR_LINCE (0x1u << 28) /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */
+#define US_IMR_LINSNRE (0x1u << 29) /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */
+/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
+#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */
+#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */
+#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */
+#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */
+#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */
+#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */
+#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */
+#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */
+#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */
+#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */
+#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max number of Repetitions Reached */
+#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) SPI Underrun Error */
+#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */
+#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */
+#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non Acknowledge Interrupt */
+#define US_CSR_LINBK (0x1u << 13) /**< \brief (US_CSR) LIN Break Sent or LIN Break Received */
+#define US_CSR_LINID (0x1u << 14) /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received */
+#define US_CSR_LINTC (0x1u << 15) /**< \brief (US_CSR) LIN Transfer Completed */
+#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */
+#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */
+#define US_CSR_LINBLS (0x1u << 23) /**< \brief (US_CSR) LIN Bus Line Status */
+#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */
+#define US_CSR_LINBE (0x1u << 25) /**< \brief (US_CSR) LIN Bit Error */
+#define US_CSR_LINISFE (0x1u << 26) /**< \brief (US_CSR) LIN Inconsistent Synch Field Error */
+#define US_CSR_LINIPE (0x1u << 27) /**< \brief (US_CSR) LIN Identifier Parity Error */
+#define US_CSR_LINCE (0x1u << 28) /**< \brief (US_CSR) LIN Checksum Error */
+#define US_CSR_LINSNRE (0x1u << 29) /**< \brief (US_CSR) LIN Slave Not Responding Error */
+/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */
+#define US_RHR_RXCHR_Pos 0
+#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */
+#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */
+/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */
+#define US_THR_TXCHR_Pos 0
+#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */
+#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
+#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be transmitted */
+/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define US_BRGR_CD_Pos 0
+#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */
+#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
+#define US_BRGR_FP_Pos 16
+#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */
+#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
+/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
+#define US_RTOR_TO_Pos 0
+#define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */
+#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
+/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
+#define US_TTGR_TG_Pos 0
+#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */
+#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
+/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */
+#define US_FIDI_FI_DI_RATIO_Pos 0
+#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */
+#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))
+/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */
+#define US_NER_NB_ERRORS_Pos 0
+#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */
+/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */
+#define US_IF_IRDA_FILTER_Pos 0
+#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */
+#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))
+/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */
+#define US_MAN_TX_PL_Pos 0
+#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */
+#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))
+#define US_MAN_TX_PP_Pos 8
+#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */
+#define   US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */
+#define   US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */
+#define   US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */
+#define   US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */
+#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */
+#define US_MAN_RX_PL_Pos 16
+#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */
+#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))
+#define US_MAN_RX_PP_Pos 24
+#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */
+#define   US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */
+#define   US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */
+#define   US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */
+#define   US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */
+#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */
+#define US_MAN_STUCKTO1 (0x1u << 29) /**< \brief (US_MAN)  */
+#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift compensation */
+/* -------- US_LINMR : (USART Offset: 0x0054) LIN Mode Register -------- */
+#define US_LINMR_NACT_Pos 0
+#define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos) /**< \brief (US_LINMR) LIN Node Action */
+#define   US_LINMR_NACT_PUBLISH (0x0u << 0) /**< \brief (US_LINMR) The USART transmits the response. */
+#define   US_LINMR_NACT_SUBSCRIBE (0x1u << 0) /**< \brief (US_LINMR) The USART receives the response. */
+#define   US_LINMR_NACT_IGNORE (0x2u << 0) /**< \brief (US_LINMR) The USART does not transmit and does not receive the response. */
+#define US_LINMR_PARDIS (0x1u << 2) /**< \brief (US_LINMR) Parity Disable */
+#define US_LINMR_CHKDIS (0x1u << 3) /**< \brief (US_LINMR) Checksum Disable */
+#define US_LINMR_CHKTYP (0x1u << 4) /**< \brief (US_LINMR) Checksum Type */
+#define US_LINMR_DLM (0x1u << 5) /**< \brief (US_LINMR) Data Length Mode */
+#define US_LINMR_FSDIS (0x1u << 6) /**< \brief (US_LINMR) Frame Slot Mode Disable */
+#define US_LINMR_WKUPTYP (0x1u << 7) /**< \brief (US_LINMR) Wakeup Signal Type */
+#define US_LINMR_DLC_Pos 8
+#define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos) /**< \brief (US_LINMR) Data Length Control */
+#define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos)))
+#define US_LINMR_PDCM (0x1u << 16) /**< \brief (US_LINMR) PDC Mode */
+/* -------- US_LINIR : (USART Offset: 0x0058) LIN Identifier Register -------- */
+#define US_LINIR_IDCHR_Pos 0
+#define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos) /**< \brief (US_LINIR) Identifier Character */
+#define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos)))
+/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */
+#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */
+#define US_WPMR_WPKEY_Pos 8
+#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */
+#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))
+/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */
+#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */
+#define US_WPSR_WPVSRC_Pos 8
+#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */
+/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */
+#define US_RPR_RXPTR_Pos 0
+#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */
+#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos)))
+/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */
+#define US_RCR_RXCTR_Pos 0
+#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */
+#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos)))
+/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */
+#define US_TPR_TXPTR_Pos 0
+#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */
+#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos)))
+/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */
+#define US_TCR_TXCTR_Pos 0
+#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */
+#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos)))
+/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */
+#define US_RNPR_RXNPTR_Pos 0
+#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */
+#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos)))
+/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */
+#define US_RNCR_RXNCTR_Pos 0
+#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */
+#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos)))
+/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define US_TNPR_TXNPTR_Pos 0
+#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */
+#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos)))
+/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define US_TNCR_TXNCTR_Pos 0
+#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */
+#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos)))
+/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */
+#define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */
+#define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */
+#define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */
+#define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */
+/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */
+#define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */
+#define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_USART_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_wdt.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_wdt.h
new file mode 100644
index 000000000..aa5772b3d
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/component/component_wdt.h
@@ -0,0 +1,72 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_WDT_COMPONENT_
+#define _SAM3XA_WDT_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Watchdog Timer */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_WDT Watchdog Timer */
+/*@{*/
+
+#ifndef __ASSEMBLY__
+/** \brief Wdt hardware registers */
+typedef struct {
+  WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */
+  RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */
+  RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */
+} Wdt;
+#endif /* __ASSEMBLY__ */
+/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */
+#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */
+#define WDT_CR_KEY_Pos 24
+#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */
+#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))
+/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */
+#define WDT_MR_WDV_Pos 0
+#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */
+#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))
+#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */
+#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */
+#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */
+#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */
+#define WDT_MR_WDD_Pos 16
+#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */
+#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))
+#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */
+#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */
+/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */
+#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */
+#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_WDT_COMPONENT_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_adc.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_adc.h
new file mode 100644
index 000000000..a9f2279d0
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_adc.h
@@ -0,0 +1,100 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_ADC_INSTANCE_
+#define _SAM3XA_ADC_INSTANCE_
+
+/* ========== Register definition for ADC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_ADC_CR               (0x400C0000U) /**< \brief (ADC) Control Register */
+#define REG_ADC_MR               (0x400C0004U) /**< \brief (ADC) Mode Register */
+#define REG_ADC_SEQR1            (0x400C0008U) /**< \brief (ADC) Channel Sequence Register 1 */
+#define REG_ADC_SEQR2            (0x400C000CU) /**< \brief (ADC) Channel Sequence Register 2 */
+#define REG_ADC_CHER             (0x400C0010U) /**< \brief (ADC) Channel Enable Register */
+#define REG_ADC_CHDR             (0x400C0014U) /**< \brief (ADC) Channel Disable Register */
+#define REG_ADC_CHSR             (0x400C0018U) /**< \brief (ADC) Channel Status Register */
+#define REG_ADC_LCDR             (0x400C0020U) /**< \brief (ADC) Last Converted Data Register */
+#define REG_ADC_IER              (0x400C0024U) /**< \brief (ADC) Interrupt Enable Register */
+#define REG_ADC_IDR              (0x400C0028U) /**< \brief (ADC) Interrupt Disable Register */
+#define REG_ADC_IMR              (0x400C002CU) /**< \brief (ADC) Interrupt Mask Register */
+#define REG_ADC_ISR              (0x400C0030U) /**< \brief (ADC) Interrupt Status Register */
+#define REG_ADC_OVER             (0x400C003CU) /**< \brief (ADC) Overrun Status Register */
+#define REG_ADC_EMR              (0x400C0040U) /**< \brief (ADC) Extended Mode Register */
+#define REG_ADC_CWR              (0x400C0044U) /**< \brief (ADC) Compare Window Register */
+#define REG_ADC_CGR              (0x400C0048U) /**< \brief (ADC) Channel Gain Register */
+#define REG_ADC_COR              (0x400C004CU) /**< \brief (ADC) Channel Offset Register */
+#define REG_ADC_CDR              (0x400C0050U) /**< \brief (ADC) Channel Data Register */
+#define REG_ADC_ACR              (0x400C0094U) /**< \brief (ADC) Analog Control Register */
+#define REG_ADC_WPMR             (0x400C00E4U) /**< \brief (ADC) Write Protect Mode Register */
+#define REG_ADC_WPSR             (0x400C00E8U) /**< \brief (ADC) Write Protect Status Register */
+#define REG_ADC_RPR              (0x400C0100U) /**< \brief (ADC) Receive Pointer Register */
+#define REG_ADC_RCR              (0x400C0104U) /**< \brief (ADC) Receive Counter Register */
+#define REG_ADC_TPR              (0x400C0108U) /**< \brief (ADC) Transmit Pointer Register */
+#define REG_ADC_TCR              (0x400C010CU) /**< \brief (ADC) Transmit Counter Register */
+#define REG_ADC_RNPR             (0x400C0110U) /**< \brief (ADC) Receive Next Pointer Register */
+#define REG_ADC_RNCR             (0x400C0114U) /**< \brief (ADC) Receive Next Counter Register */
+#define REG_ADC_TNPR             (0x400C0118U) /**< \brief (ADC) Transmit Next Pointer Register */
+#define REG_ADC_TNCR             (0x400C011CU) /**< \brief (ADC) Transmit Next Counter Register */
+#define REG_ADC_PTCR             (0x400C0120U) /**< \brief (ADC) Transfer Control Register */
+#define REG_ADC_PTSR             (0x400C0124U) /**< \brief (ADC) Transfer Status Register */
+#else
+#define REG_ADC_CR      (*(WoReg*)0x400C0000U) /**< \brief (ADC) Control Register */
+#define REG_ADC_MR      (*(RwReg*)0x400C0004U) /**< \brief (ADC) Mode Register */
+#define REG_ADC_SEQR1   (*(RwReg*)0x400C0008U) /**< \brief (ADC) Channel Sequence Register 1 */
+#define REG_ADC_SEQR2   (*(RwReg*)0x400C000CU) /**< \brief (ADC) Channel Sequence Register 2 */
+#define REG_ADC_CHER    (*(WoReg*)0x400C0010U) /**< \brief (ADC) Channel Enable Register */
+#define REG_ADC_CHDR    (*(WoReg*)0x400C0014U) /**< \brief (ADC) Channel Disable Register */
+#define REG_ADC_CHSR    (*(RoReg*)0x400C0018U) /**< \brief (ADC) Channel Status Register */
+#define REG_ADC_LCDR    (*(RoReg*)0x400C0020U) /**< \brief (ADC) Last Converted Data Register */
+#define REG_ADC_IER     (*(WoReg*)0x400C0024U) /**< \brief (ADC) Interrupt Enable Register */
+#define REG_ADC_IDR     (*(WoReg*)0x400C0028U) /**< \brief (ADC) Interrupt Disable Register */
+#define REG_ADC_IMR     (*(RoReg*)0x400C002CU) /**< \brief (ADC) Interrupt Mask Register */
+#define REG_ADC_ISR     (*(RoReg*)0x400C0030U) /**< \brief (ADC) Interrupt Status Register */
+#define REG_ADC_OVER    (*(RoReg*)0x400C003CU) /**< \brief (ADC) Overrun Status Register */
+#define REG_ADC_EMR     (*(RwReg*)0x400C0040U) /**< \brief (ADC) Extended Mode Register */
+#define REG_ADC_CWR     (*(RwReg*)0x400C0044U) /**< \brief (ADC) Compare Window Register */
+#define REG_ADC_CGR     (*(RwReg*)0x400C0048U) /**< \brief (ADC) Channel Gain Register */
+#define REG_ADC_COR     (*(RwReg*)0x400C004CU) /**< \brief (ADC) Channel Offset Register */
+#define REG_ADC_CDR     (*(RoReg*)0x400C0050U) /**< \brief (ADC) Channel Data Register */
+#define REG_ADC_ACR     (*(RwReg*)0x400C0094U) /**< \brief (ADC) Analog Control Register */
+#define REG_ADC_WPMR    (*(RwReg*)0x400C00E4U) /**< \brief (ADC) Write Protect Mode Register */
+#define REG_ADC_WPSR    (*(RoReg*)0x400C00E8U) /**< \brief (ADC) Write Protect Status Register */
+#define REG_ADC_RPR     (*(RwReg*)0x400C0100U) /**< \brief (ADC) Receive Pointer Register */
+#define REG_ADC_RCR     (*(RwReg*)0x400C0104U) /**< \brief (ADC) Receive Counter Register */
+#define REG_ADC_TPR     (*(RwReg*)0x400C0108U) /**< \brief (ADC) Transmit Pointer Register */
+#define REG_ADC_TCR     (*(RwReg*)0x400C010CU) /**< \brief (ADC) Transmit Counter Register */
+#define REG_ADC_RNPR    (*(RwReg*)0x400C0110U) /**< \brief (ADC) Receive Next Pointer Register */
+#define REG_ADC_RNCR    (*(RwReg*)0x400C0114U) /**< \brief (ADC) Receive Next Counter Register */
+#define REG_ADC_TNPR    (*(RwReg*)0x400C0118U) /**< \brief (ADC) Transmit Next Pointer Register */
+#define REG_ADC_TNCR    (*(RwReg*)0x400C011CU) /**< \brief (ADC) Transmit Next Counter Register */
+#define REG_ADC_PTCR    (*(WoReg*)0x400C0120U) /**< \brief (ADC) Transfer Control Register */
+#define REG_ADC_PTSR    (*(RoReg*)0x400C0124U) /**< \brief (ADC) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_ADC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_can0.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_can0.h
new file mode 100644
index 000000000..0307bef86
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_can0.h
@@ -0,0 +1,188 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_CAN0_INSTANCE_
+#define _SAM3XA_CAN0_INSTANCE_
+
+/* ========== Register definition for CAN0 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_CAN0_MR               (0x400B4000U) /**< \brief (CAN0) Mode Register */
+#define REG_CAN0_IER              (0x400B4004U) /**< \brief (CAN0) Interrupt Enable Register */
+#define REG_CAN0_IDR              (0x400B4008U) /**< \brief (CAN0) Interrupt Disable Register */
+#define REG_CAN0_IMR              (0x400B400CU) /**< \brief (CAN0) Interrupt Mask Register */
+#define REG_CAN0_SR               (0x400B4010U) /**< \brief (CAN0) Status Register */
+#define REG_CAN0_BR               (0x400B4014U) /**< \brief (CAN0) Baudrate Register */
+#define REG_CAN0_TIM              (0x400B4018U) /**< \brief (CAN0) Timer Register */
+#define REG_CAN0_TIMESTP          (0x400B401CU) /**< \brief (CAN0) Timestamp Register */
+#define REG_CAN0_ECR              (0x400B4020U) /**< \brief (CAN0) Error Counter Register */
+#define REG_CAN0_TCR              (0x400B4024U) /**< \brief (CAN0) Transfer Command Register */
+#define REG_CAN0_ACR              (0x400B4028U) /**< \brief (CAN0) Abort Command Register */
+#define REG_CAN0_MMR0             (0x400B4200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */
+#define REG_CAN0_MAM0             (0x400B4204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */
+#define REG_CAN0_MID0             (0x400B4208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */
+#define REG_CAN0_MFID0            (0x400B420CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */
+#define REG_CAN0_MSR0             (0x400B4210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */
+#define REG_CAN0_MDL0             (0x400B4214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */
+#define REG_CAN0_MDH0             (0x400B4218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */
+#define REG_CAN0_MCR0             (0x400B421CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */
+#define REG_CAN0_MMR1             (0x400B4220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */
+#define REG_CAN0_MAM1             (0x400B4224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */
+#define REG_CAN0_MID1             (0x400B4228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */
+#define REG_CAN0_MFID1            (0x400B422CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */
+#define REG_CAN0_MSR1             (0x400B4230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */
+#define REG_CAN0_MDL1             (0x400B4234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */
+#define REG_CAN0_MDH1             (0x400B4238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */
+#define REG_CAN0_MCR1             (0x400B423CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */
+#define REG_CAN0_MMR2             (0x400B4240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */
+#define REG_CAN0_MAM2             (0x400B4244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */
+#define REG_CAN0_MID2             (0x400B4248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */
+#define REG_CAN0_MFID2            (0x400B424CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */
+#define REG_CAN0_MSR2             (0x400B4250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */
+#define REG_CAN0_MDL2             (0x400B4254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */
+#define REG_CAN0_MDH2             (0x400B4258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */
+#define REG_CAN0_MCR2             (0x400B425CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */
+#define REG_CAN0_MMR3             (0x400B4260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */
+#define REG_CAN0_MAM3             (0x400B4264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */
+#define REG_CAN0_MID3             (0x400B4268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */
+#define REG_CAN0_MFID3            (0x400B426CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */
+#define REG_CAN0_MSR3             (0x400B4270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */
+#define REG_CAN0_MDL3             (0x400B4274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */
+#define REG_CAN0_MDH3             (0x400B4278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */
+#define REG_CAN0_MCR3             (0x400B427CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */
+#define REG_CAN0_MMR4             (0x400B4280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */
+#define REG_CAN0_MAM4             (0x400B4284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */
+#define REG_CAN0_MID4             (0x400B4288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */
+#define REG_CAN0_MFID4            (0x400B428CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */
+#define REG_CAN0_MSR4             (0x400B4290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */
+#define REG_CAN0_MDL4             (0x400B4294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */
+#define REG_CAN0_MDH4             (0x400B4298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */
+#define REG_CAN0_MCR4             (0x400B429CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */
+#define REG_CAN0_MMR5             (0x400B42A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */
+#define REG_CAN0_MAM5             (0x400B42A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */
+#define REG_CAN0_MID5             (0x400B42A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */
+#define REG_CAN0_MFID5            (0x400B42ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */
+#define REG_CAN0_MSR5             (0x400B42B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */
+#define REG_CAN0_MDL5             (0x400B42B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */
+#define REG_CAN0_MDH5             (0x400B42B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */
+#define REG_CAN0_MCR5             (0x400B42BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */
+#define REG_CAN0_MMR6             (0x400B42C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */
+#define REG_CAN0_MAM6             (0x400B42C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */
+#define REG_CAN0_MID6             (0x400B42C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */
+#define REG_CAN0_MFID6            (0x400B42CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */
+#define REG_CAN0_MSR6             (0x400B42D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */
+#define REG_CAN0_MDL6             (0x400B42D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */
+#define REG_CAN0_MDH6             (0x400B42D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */
+#define REG_CAN0_MCR6             (0x400B42DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */
+#define REG_CAN0_MMR7             (0x400B42E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */
+#define REG_CAN0_MAM7             (0x400B42E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */
+#define REG_CAN0_MID7             (0x400B42E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */
+#define REG_CAN0_MFID7            (0x400B42ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */
+#define REG_CAN0_MSR7             (0x400B42F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */
+#define REG_CAN0_MDL7             (0x400B42F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */
+#define REG_CAN0_MDH7             (0x400B42F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */
+#define REG_CAN0_MCR7             (0x400B42FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */
+#else
+#define REG_CAN0_MR      (*(RwReg*)0x400B4000U) /**< \brief (CAN0) Mode Register */
+#define REG_CAN0_IER     (*(WoReg*)0x400B4004U) /**< \brief (CAN0) Interrupt Enable Register */
+#define REG_CAN0_IDR     (*(WoReg*)0x400B4008U) /**< \brief (CAN0) Interrupt Disable Register */
+#define REG_CAN0_IMR     (*(RoReg*)0x400B400CU) /**< \brief (CAN0) Interrupt Mask Register */
+#define REG_CAN0_SR      (*(RoReg*)0x400B4010U) /**< \brief (CAN0) Status Register */
+#define REG_CAN0_BR      (*(RwReg*)0x400B4014U) /**< \brief (CAN0) Baudrate Register */
+#define REG_CAN0_TIM     (*(RoReg*)0x400B4018U) /**< \brief (CAN0) Timer Register */
+#define REG_CAN0_TIMESTP (*(RoReg*)0x400B401CU) /**< \brief (CAN0) Timestamp Register */
+#define REG_CAN0_ECR     (*(RoReg*)0x400B4020U) /**< \brief (CAN0) Error Counter Register */
+#define REG_CAN0_TCR     (*(WoReg*)0x400B4024U) /**< \brief (CAN0) Transfer Command Register */
+#define REG_CAN0_ACR     (*(WoReg*)0x400B4028U) /**< \brief (CAN0) Abort Command Register */
+#define REG_CAN0_MMR0    (*(RwReg*)0x400B4200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */
+#define REG_CAN0_MAM0    (*(RwReg*)0x400B4204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */
+#define REG_CAN0_MID0    (*(RwReg*)0x400B4208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */
+#define REG_CAN0_MFID0   (*(RoReg*)0x400B420CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */
+#define REG_CAN0_MSR0    (*(RoReg*)0x400B4210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */
+#define REG_CAN0_MDL0    (*(RwReg*)0x400B4214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */
+#define REG_CAN0_MDH0    (*(RwReg*)0x400B4218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */
+#define REG_CAN0_MCR0    (*(WoReg*)0x400B421CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */
+#define REG_CAN0_MMR1    (*(RwReg*)0x400B4220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */
+#define REG_CAN0_MAM1    (*(RwReg*)0x400B4224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */
+#define REG_CAN0_MID1    (*(RwReg*)0x400B4228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */
+#define REG_CAN0_MFID1   (*(RoReg*)0x400B422CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */
+#define REG_CAN0_MSR1    (*(RoReg*)0x400B4230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */
+#define REG_CAN0_MDL1    (*(RwReg*)0x400B4234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */
+#define REG_CAN0_MDH1    (*(RwReg*)0x400B4238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */
+#define REG_CAN0_MCR1    (*(WoReg*)0x400B423CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */
+#define REG_CAN0_MMR2    (*(RwReg*)0x400B4240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */
+#define REG_CAN0_MAM2    (*(RwReg*)0x400B4244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */
+#define REG_CAN0_MID2    (*(RwReg*)0x400B4248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */
+#define REG_CAN0_MFID2   (*(RoReg*)0x400B424CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */
+#define REG_CAN0_MSR2    (*(RoReg*)0x400B4250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */
+#define REG_CAN0_MDL2    (*(RwReg*)0x400B4254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */
+#define REG_CAN0_MDH2    (*(RwReg*)0x400B4258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */
+#define REG_CAN0_MCR2    (*(WoReg*)0x400B425CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */
+#define REG_CAN0_MMR3    (*(RwReg*)0x400B4260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */
+#define REG_CAN0_MAM3    (*(RwReg*)0x400B4264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */
+#define REG_CAN0_MID3    (*(RwReg*)0x400B4268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */
+#define REG_CAN0_MFID3   (*(RoReg*)0x400B426CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */
+#define REG_CAN0_MSR3    (*(RoReg*)0x400B4270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */
+#define REG_CAN0_MDL3    (*(RwReg*)0x400B4274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */
+#define REG_CAN0_MDH3    (*(RwReg*)0x400B4278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */
+#define REG_CAN0_MCR3    (*(WoReg*)0x400B427CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */
+#define REG_CAN0_MMR4    (*(RwReg*)0x400B4280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */
+#define REG_CAN0_MAM4    (*(RwReg*)0x400B4284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */
+#define REG_CAN0_MID4    (*(RwReg*)0x400B4288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */
+#define REG_CAN0_MFID4   (*(RoReg*)0x400B428CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */
+#define REG_CAN0_MSR4    (*(RoReg*)0x400B4290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */
+#define REG_CAN0_MDL4    (*(RwReg*)0x400B4294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */
+#define REG_CAN0_MDH4    (*(RwReg*)0x400B4298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */
+#define REG_CAN0_MCR4    (*(WoReg*)0x400B429CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */
+#define REG_CAN0_MMR5    (*(RwReg*)0x400B42A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */
+#define REG_CAN0_MAM5    (*(RwReg*)0x400B42A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */
+#define REG_CAN0_MID5    (*(RwReg*)0x400B42A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */
+#define REG_CAN0_MFID5   (*(RoReg*)0x400B42ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */
+#define REG_CAN0_MSR5    (*(RoReg*)0x400B42B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */
+#define REG_CAN0_MDL5    (*(RwReg*)0x400B42B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */
+#define REG_CAN0_MDH5    (*(RwReg*)0x400B42B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */
+#define REG_CAN0_MCR5    (*(WoReg*)0x400B42BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */
+#define REG_CAN0_MMR6    (*(RwReg*)0x400B42C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */
+#define REG_CAN0_MAM6    (*(RwReg*)0x400B42C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */
+#define REG_CAN0_MID6    (*(RwReg*)0x400B42C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */
+#define REG_CAN0_MFID6   (*(RoReg*)0x400B42CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */
+#define REG_CAN0_MSR6    (*(RoReg*)0x400B42D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */
+#define REG_CAN0_MDL6    (*(RwReg*)0x400B42D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */
+#define REG_CAN0_MDH6    (*(RwReg*)0x400B42D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */
+#define REG_CAN0_MCR6    (*(WoReg*)0x400B42DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */
+#define REG_CAN0_MMR7    (*(RwReg*)0x400B42E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */
+#define REG_CAN0_MAM7    (*(RwReg*)0x400B42E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */
+#define REG_CAN0_MID7    (*(RwReg*)0x400B42E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */
+#define REG_CAN0_MFID7   (*(RoReg*)0x400B42ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */
+#define REG_CAN0_MSR7    (*(RoReg*)0x400B42F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */
+#define REG_CAN0_MDL7    (*(RwReg*)0x400B42F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */
+#define REG_CAN0_MDH7    (*(RwReg*)0x400B42F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */
+#define REG_CAN0_MCR7    (*(WoReg*)0x400B42FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_CAN0_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_can1.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_can1.h
new file mode 100644
index 000000000..4662d18ab
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_can1.h
@@ -0,0 +1,188 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_CAN1_INSTANCE_
+#define _SAM3XA_CAN1_INSTANCE_
+
+/* ========== Register definition for CAN1 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_CAN1_MR               (0x400B8000U) /**< \brief (CAN1) Mode Register */
+#define REG_CAN1_IER              (0x400B8004U) /**< \brief (CAN1) Interrupt Enable Register */
+#define REG_CAN1_IDR              (0x400B8008U) /**< \brief (CAN1) Interrupt Disable Register */
+#define REG_CAN1_IMR              (0x400B800CU) /**< \brief (CAN1) Interrupt Mask Register */
+#define REG_CAN1_SR               (0x400B8010U) /**< \brief (CAN1) Status Register */
+#define REG_CAN1_BR               (0x400B8014U) /**< \brief (CAN1) Baudrate Register */
+#define REG_CAN1_TIM              (0x400B8018U) /**< \brief (CAN1) Timer Register */
+#define REG_CAN1_TIMESTP          (0x400B801CU) /**< \brief (CAN1) Timestamp Register */
+#define REG_CAN1_ECR              (0x400B8020U) /**< \brief (CAN1) Error Counter Register */
+#define REG_CAN1_TCR              (0x400B8024U) /**< \brief (CAN1) Transfer Command Register */
+#define REG_CAN1_ACR              (0x400B8028U) /**< \brief (CAN1) Abort Command Register */
+#define REG_CAN1_MMR0             (0x400B8200U) /**< \brief (CAN1) Mailbox Mode Register (MB = 0) */
+#define REG_CAN1_MAM0             (0x400B8204U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 0) */
+#define REG_CAN1_MID0             (0x400B8208U) /**< \brief (CAN1) Mailbox ID Register (MB = 0) */
+#define REG_CAN1_MFID0            (0x400B820CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 0) */
+#define REG_CAN1_MSR0             (0x400B8210U) /**< \brief (CAN1) Mailbox Status Register (MB = 0) */
+#define REG_CAN1_MDL0             (0x400B8214U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 0) */
+#define REG_CAN1_MDH0             (0x400B8218U) /**< \brief (CAN1) Mailbox Data High Register (MB = 0) */
+#define REG_CAN1_MCR0             (0x400B821CU) /**< \brief (CAN1) Mailbox Control Register (MB = 0) */
+#define REG_CAN1_MMR1             (0x400B8220U) /**< \brief (CAN1) Mailbox Mode Register (MB = 1) */
+#define REG_CAN1_MAM1             (0x400B8224U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 1) */
+#define REG_CAN1_MID1             (0x400B8228U) /**< \brief (CAN1) Mailbox ID Register (MB = 1) */
+#define REG_CAN1_MFID1            (0x400B822CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 1) */
+#define REG_CAN1_MSR1             (0x400B8230U) /**< \brief (CAN1) Mailbox Status Register (MB = 1) */
+#define REG_CAN1_MDL1             (0x400B8234U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 1) */
+#define REG_CAN1_MDH1             (0x400B8238U) /**< \brief (CAN1) Mailbox Data High Register (MB = 1) */
+#define REG_CAN1_MCR1             (0x400B823CU) /**< \brief (CAN1) Mailbox Control Register (MB = 1) */
+#define REG_CAN1_MMR2             (0x400B8240U) /**< \brief (CAN1) Mailbox Mode Register (MB = 2) */
+#define REG_CAN1_MAM2             (0x400B8244U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 2) */
+#define REG_CAN1_MID2             (0x400B8248U) /**< \brief (CAN1) Mailbox ID Register (MB = 2) */
+#define REG_CAN1_MFID2            (0x400B824CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 2) */
+#define REG_CAN1_MSR2             (0x400B8250U) /**< \brief (CAN1) Mailbox Status Register (MB = 2) */
+#define REG_CAN1_MDL2             (0x400B8254U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 2) */
+#define REG_CAN1_MDH2             (0x400B8258U) /**< \brief (CAN1) Mailbox Data High Register (MB = 2) */
+#define REG_CAN1_MCR2             (0x400B825CU) /**< \brief (CAN1) Mailbox Control Register (MB = 2) */
+#define REG_CAN1_MMR3             (0x400B8260U) /**< \brief (CAN1) Mailbox Mode Register (MB = 3) */
+#define REG_CAN1_MAM3             (0x400B8264U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 3) */
+#define REG_CAN1_MID3             (0x400B8268U) /**< \brief (CAN1) Mailbox ID Register (MB = 3) */
+#define REG_CAN1_MFID3            (0x400B826CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 3) */
+#define REG_CAN1_MSR3             (0x400B8270U) /**< \brief (CAN1) Mailbox Status Register (MB = 3) */
+#define REG_CAN1_MDL3             (0x400B8274U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 3) */
+#define REG_CAN1_MDH3             (0x400B8278U) /**< \brief (CAN1) Mailbox Data High Register (MB = 3) */
+#define REG_CAN1_MCR3             (0x400B827CU) /**< \brief (CAN1) Mailbox Control Register (MB = 3) */
+#define REG_CAN1_MMR4             (0x400B8280U) /**< \brief (CAN1) Mailbox Mode Register (MB = 4) */
+#define REG_CAN1_MAM4             (0x400B8284U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 4) */
+#define REG_CAN1_MID4             (0x400B8288U) /**< \brief (CAN1) Mailbox ID Register (MB = 4) */
+#define REG_CAN1_MFID4            (0x400B828CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 4) */
+#define REG_CAN1_MSR4             (0x400B8290U) /**< \brief (CAN1) Mailbox Status Register (MB = 4) */
+#define REG_CAN1_MDL4             (0x400B8294U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 4) */
+#define REG_CAN1_MDH4             (0x400B8298U) /**< \brief (CAN1) Mailbox Data High Register (MB = 4) */
+#define REG_CAN1_MCR4             (0x400B829CU) /**< \brief (CAN1) Mailbox Control Register (MB = 4) */
+#define REG_CAN1_MMR5             (0x400B82A0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 5) */
+#define REG_CAN1_MAM5             (0x400B82A4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 5) */
+#define REG_CAN1_MID5             (0x400B82A8U) /**< \brief (CAN1) Mailbox ID Register (MB = 5) */
+#define REG_CAN1_MFID5            (0x400B82ACU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 5) */
+#define REG_CAN1_MSR5             (0x400B82B0U) /**< \brief (CAN1) Mailbox Status Register (MB = 5) */
+#define REG_CAN1_MDL5             (0x400B82B4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 5) */
+#define REG_CAN1_MDH5             (0x400B82B8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 5) */
+#define REG_CAN1_MCR5             (0x400B82BCU) /**< \brief (CAN1) Mailbox Control Register (MB = 5) */
+#define REG_CAN1_MMR6             (0x400B82C0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 6) */
+#define REG_CAN1_MAM6             (0x400B82C4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 6) */
+#define REG_CAN1_MID6             (0x400B82C8U) /**< \brief (CAN1) Mailbox ID Register (MB = 6) */
+#define REG_CAN1_MFID6            (0x400B82CCU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 6) */
+#define REG_CAN1_MSR6             (0x400B82D0U) /**< \brief (CAN1) Mailbox Status Register (MB = 6) */
+#define REG_CAN1_MDL6             (0x400B82D4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 6) */
+#define REG_CAN1_MDH6             (0x400B82D8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 6) */
+#define REG_CAN1_MCR6             (0x400B82DCU) /**< \brief (CAN1) Mailbox Control Register (MB = 6) */
+#define REG_CAN1_MMR7             (0x400B82E0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 7) */
+#define REG_CAN1_MAM7             (0x400B82E4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 7) */
+#define REG_CAN1_MID7             (0x400B82E8U) /**< \brief (CAN1) Mailbox ID Register (MB = 7) */
+#define REG_CAN1_MFID7            (0x400B82ECU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 7) */
+#define REG_CAN1_MSR7             (0x400B82F0U) /**< \brief (CAN1) Mailbox Status Register (MB = 7) */
+#define REG_CAN1_MDL7             (0x400B82F4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 7) */
+#define REG_CAN1_MDH7             (0x400B82F8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 7) */
+#define REG_CAN1_MCR7             (0x400B82FCU) /**< \brief (CAN1) Mailbox Control Register (MB = 7) */
+#else
+#define REG_CAN1_MR      (*(RwReg*)0x400B8000U) /**< \brief (CAN1) Mode Register */
+#define REG_CAN1_IER     (*(WoReg*)0x400B8004U) /**< \brief (CAN1) Interrupt Enable Register */
+#define REG_CAN1_IDR     (*(WoReg*)0x400B8008U) /**< \brief (CAN1) Interrupt Disable Register */
+#define REG_CAN1_IMR     (*(RoReg*)0x400B800CU) /**< \brief (CAN1) Interrupt Mask Register */
+#define REG_CAN1_SR      (*(RoReg*)0x400B8010U) /**< \brief (CAN1) Status Register */
+#define REG_CAN1_BR      (*(RwReg*)0x400B8014U) /**< \brief (CAN1) Baudrate Register */
+#define REG_CAN1_TIM     (*(RoReg*)0x400B8018U) /**< \brief (CAN1) Timer Register */
+#define REG_CAN1_TIMESTP (*(RoReg*)0x400B801CU) /**< \brief (CAN1) Timestamp Register */
+#define REG_CAN1_ECR     (*(RoReg*)0x400B8020U) /**< \brief (CAN1) Error Counter Register */
+#define REG_CAN1_TCR     (*(WoReg*)0x400B8024U) /**< \brief (CAN1) Transfer Command Register */
+#define REG_CAN1_ACR     (*(WoReg*)0x400B8028U) /**< \brief (CAN1) Abort Command Register */
+#define REG_CAN1_MMR0    (*(RwReg*)0x400B8200U) /**< \brief (CAN1) Mailbox Mode Register (MB = 0) */
+#define REG_CAN1_MAM0    (*(RwReg*)0x400B8204U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 0) */
+#define REG_CAN1_MID0    (*(RwReg*)0x400B8208U) /**< \brief (CAN1) Mailbox ID Register (MB = 0) */
+#define REG_CAN1_MFID0   (*(RoReg*)0x400B820CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 0) */
+#define REG_CAN1_MSR0    (*(RoReg*)0x400B8210U) /**< \brief (CAN1) Mailbox Status Register (MB = 0) */
+#define REG_CAN1_MDL0    (*(RwReg*)0x400B8214U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 0) */
+#define REG_CAN1_MDH0    (*(RwReg*)0x400B8218U) /**< \brief (CAN1) Mailbox Data High Register (MB = 0) */
+#define REG_CAN1_MCR0    (*(WoReg*)0x400B821CU) /**< \brief (CAN1) Mailbox Control Register (MB = 0) */
+#define REG_CAN1_MMR1    (*(RwReg*)0x400B8220U) /**< \brief (CAN1) Mailbox Mode Register (MB = 1) */
+#define REG_CAN1_MAM1    (*(RwReg*)0x400B8224U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 1) */
+#define REG_CAN1_MID1    (*(RwReg*)0x400B8228U) /**< \brief (CAN1) Mailbox ID Register (MB = 1) */
+#define REG_CAN1_MFID1   (*(RoReg*)0x400B822CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 1) */
+#define REG_CAN1_MSR1    (*(RoReg*)0x400B8230U) /**< \brief (CAN1) Mailbox Status Register (MB = 1) */
+#define REG_CAN1_MDL1    (*(RwReg*)0x400B8234U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 1) */
+#define REG_CAN1_MDH1    (*(RwReg*)0x400B8238U) /**< \brief (CAN1) Mailbox Data High Register (MB = 1) */
+#define REG_CAN1_MCR1    (*(WoReg*)0x400B823CU) /**< \brief (CAN1) Mailbox Control Register (MB = 1) */
+#define REG_CAN1_MMR2    (*(RwReg*)0x400B8240U) /**< \brief (CAN1) Mailbox Mode Register (MB = 2) */
+#define REG_CAN1_MAM2    (*(RwReg*)0x400B8244U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 2) */
+#define REG_CAN1_MID2    (*(RwReg*)0x400B8248U) /**< \brief (CAN1) Mailbox ID Register (MB = 2) */
+#define REG_CAN1_MFID2   (*(RoReg*)0x400B824CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 2) */
+#define REG_CAN1_MSR2    (*(RoReg*)0x400B8250U) /**< \brief (CAN1) Mailbox Status Register (MB = 2) */
+#define REG_CAN1_MDL2    (*(RwReg*)0x400B8254U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 2) */
+#define REG_CAN1_MDH2    (*(RwReg*)0x400B8258U) /**< \brief (CAN1) Mailbox Data High Register (MB = 2) */
+#define REG_CAN1_MCR2    (*(WoReg*)0x400B825CU) /**< \brief (CAN1) Mailbox Control Register (MB = 2) */
+#define REG_CAN1_MMR3    (*(RwReg*)0x400B8260U) /**< \brief (CAN1) Mailbox Mode Register (MB = 3) */
+#define REG_CAN1_MAM3    (*(RwReg*)0x400B8264U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 3) */
+#define REG_CAN1_MID3    (*(RwReg*)0x400B8268U) /**< \brief (CAN1) Mailbox ID Register (MB = 3) */
+#define REG_CAN1_MFID3   (*(RoReg*)0x400B826CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 3) */
+#define REG_CAN1_MSR3    (*(RoReg*)0x400B8270U) /**< \brief (CAN1) Mailbox Status Register (MB = 3) */
+#define REG_CAN1_MDL3    (*(RwReg*)0x400B8274U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 3) */
+#define REG_CAN1_MDH3    (*(RwReg*)0x400B8278U) /**< \brief (CAN1) Mailbox Data High Register (MB = 3) */
+#define REG_CAN1_MCR3    (*(WoReg*)0x400B827CU) /**< \brief (CAN1) Mailbox Control Register (MB = 3) */
+#define REG_CAN1_MMR4    (*(RwReg*)0x400B8280U) /**< \brief (CAN1) Mailbox Mode Register (MB = 4) */
+#define REG_CAN1_MAM4    (*(RwReg*)0x400B8284U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 4) */
+#define REG_CAN1_MID4    (*(RwReg*)0x400B8288U) /**< \brief (CAN1) Mailbox ID Register (MB = 4) */
+#define REG_CAN1_MFID4   (*(RoReg*)0x400B828CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 4) */
+#define REG_CAN1_MSR4    (*(RoReg*)0x400B8290U) /**< \brief (CAN1) Mailbox Status Register (MB = 4) */
+#define REG_CAN1_MDL4    (*(RwReg*)0x400B8294U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 4) */
+#define REG_CAN1_MDH4    (*(RwReg*)0x400B8298U) /**< \brief (CAN1) Mailbox Data High Register (MB = 4) */
+#define REG_CAN1_MCR4    (*(WoReg*)0x400B829CU) /**< \brief (CAN1) Mailbox Control Register (MB = 4) */
+#define REG_CAN1_MMR5    (*(RwReg*)0x400B82A0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 5) */
+#define REG_CAN1_MAM5    (*(RwReg*)0x400B82A4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 5) */
+#define REG_CAN1_MID5    (*(RwReg*)0x400B82A8U) /**< \brief (CAN1) Mailbox ID Register (MB = 5) */
+#define REG_CAN1_MFID5   (*(RoReg*)0x400B82ACU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 5) */
+#define REG_CAN1_MSR5    (*(RoReg*)0x400B82B0U) /**< \brief (CAN1) Mailbox Status Register (MB = 5) */
+#define REG_CAN1_MDL5    (*(RwReg*)0x400B82B4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 5) */
+#define REG_CAN1_MDH5    (*(RwReg*)0x400B82B8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 5) */
+#define REG_CAN1_MCR5    (*(WoReg*)0x400B82BCU) /**< \brief (CAN1) Mailbox Control Register (MB = 5) */
+#define REG_CAN1_MMR6    (*(RwReg*)0x400B82C0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 6) */
+#define REG_CAN1_MAM6    (*(RwReg*)0x400B82C4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 6) */
+#define REG_CAN1_MID6    (*(RwReg*)0x400B82C8U) /**< \brief (CAN1) Mailbox ID Register (MB = 6) */
+#define REG_CAN1_MFID6   (*(RoReg*)0x400B82CCU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 6) */
+#define REG_CAN1_MSR6    (*(RoReg*)0x400B82D0U) /**< \brief (CAN1) Mailbox Status Register (MB = 6) */
+#define REG_CAN1_MDL6    (*(RwReg*)0x400B82D4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 6) */
+#define REG_CAN1_MDH6    (*(RwReg*)0x400B82D8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 6) */
+#define REG_CAN1_MCR6    (*(WoReg*)0x400B82DCU) /**< \brief (CAN1) Mailbox Control Register (MB = 6) */
+#define REG_CAN1_MMR7    (*(RwReg*)0x400B82E0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 7) */
+#define REG_CAN1_MAM7    (*(RwReg*)0x400B82E4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 7) */
+#define REG_CAN1_MID7    (*(RwReg*)0x400B82E8U) /**< \brief (CAN1) Mailbox ID Register (MB = 7) */
+#define REG_CAN1_MFID7   (*(RoReg*)0x400B82ECU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 7) */
+#define REG_CAN1_MSR7    (*(RoReg*)0x400B82F0U) /**< \brief (CAN1) Mailbox Status Register (MB = 7) */
+#define REG_CAN1_MDL7    (*(RwReg*)0x400B82F4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 7) */
+#define REG_CAN1_MDH7    (*(RwReg*)0x400B82F8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 7) */
+#define REG_CAN1_MCR7    (*(WoReg*)0x400B82FCU) /**< \brief (CAN1) Mailbox Control Register (MB = 7) */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_CAN1_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_chipid.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_chipid.h
new file mode 100644
index 000000000..b5f550d22
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_chipid.h
@@ -0,0 +1,42 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_CHIPID_INSTANCE_
+#define _SAM3XA_CHIPID_INSTANCE_
+
+/* ========== Register definition for CHIPID peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_CHIPID_CIDR          (0x400E0940U) /**< \brief (CHIPID) Chip ID Register */
+#define REG_CHIPID_EXID          (0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */
+#else
+#define REG_CHIPID_CIDR (*(RoReg*)0x400E0940U) /**< \brief (CHIPID) Chip ID Register */
+#define REG_CHIPID_EXID (*(RoReg*)0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_CHIPID_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_dacc.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_dacc.h
new file mode 100644
index 000000000..e27cb4ef7
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_dacc.h
@@ -0,0 +1,84 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_DACC_INSTANCE_
+#define _SAM3XA_DACC_INSTANCE_
+
+/* ========== Register definition for DACC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_DACC_CR            (0x400C8000U) /**< \brief (DACC) Control Register */
+#define REG_DACC_MR            (0x400C8004U) /**< \brief (DACC) Mode Register */
+#define REG_DACC_CHER          (0x400C8010U) /**< \brief (DACC) Channel Enable Register */
+#define REG_DACC_CHDR          (0x400C8014U) /**< \brief (DACC) Channel Disable Register */
+#define REG_DACC_CHSR          (0x400C8018U) /**< \brief (DACC) Channel Status Register */
+#define REG_DACC_CDR           (0x400C8020U) /**< \brief (DACC) Conversion Data Register */
+#define REG_DACC_IER           (0x400C8024U) /**< \brief (DACC) Interrupt Enable Register */
+#define REG_DACC_IDR           (0x400C8028U) /**< \brief (DACC) Interrupt Disable Register */
+#define REG_DACC_IMR           (0x400C802CU) /**< \brief (DACC) Interrupt Mask Register */
+#define REG_DACC_ISR           (0x400C8030U) /**< \brief (DACC) Interrupt Status Register */
+#define REG_DACC_ACR           (0x400C8094U) /**< \brief (DACC) Analog Current Register */
+#define REG_DACC_WPMR          (0x400C80E4U) /**< \brief (DACC) Write Protect Mode register */
+#define REG_DACC_WPSR          (0x400C80E8U) /**< \brief (DACC) Write Protect Status register */
+#define REG_DACC_RPR           (0x400C8100U) /**< \brief (DACC) Receive Pointer Register */
+#define REG_DACC_RCR           (0x400C8104U) /**< \brief (DACC) Receive Counter Register */
+#define REG_DACC_TPR           (0x400C8108U) /**< \brief (DACC) Transmit Pointer Register */
+#define REG_DACC_TCR           (0x400C810CU) /**< \brief (DACC) Transmit Counter Register */
+#define REG_DACC_RNPR          (0x400C8110U) /**< \brief (DACC) Receive Next Pointer Register */
+#define REG_DACC_RNCR          (0x400C8114U) /**< \brief (DACC) Receive Next Counter Register */
+#define REG_DACC_TNPR          (0x400C8118U) /**< \brief (DACC) Transmit Next Pointer Register */
+#define REG_DACC_TNCR          (0x400C811CU) /**< \brief (DACC) Transmit Next Counter Register */
+#define REG_DACC_PTCR          (0x400C8120U) /**< \brief (DACC) Transfer Control Register */
+#define REG_DACC_PTSR          (0x400C8124U) /**< \brief (DACC) Transfer Status Register */
+#else
+#define REG_DACC_CR   (*(WoReg*)0x400C8000U) /**< \brief (DACC) Control Register */
+#define REG_DACC_MR   (*(RwReg*)0x400C8004U) /**< \brief (DACC) Mode Register */
+#define REG_DACC_CHER (*(WoReg*)0x400C8010U) /**< \brief (DACC) Channel Enable Register */
+#define REG_DACC_CHDR (*(WoReg*)0x400C8014U) /**< \brief (DACC) Channel Disable Register */
+#define REG_DACC_CHSR (*(RoReg*)0x400C8018U) /**< \brief (DACC) Channel Status Register */
+#define REG_DACC_CDR  (*(WoReg*)0x400C8020U) /**< \brief (DACC) Conversion Data Register */
+#define REG_DACC_IER  (*(WoReg*)0x400C8024U) /**< \brief (DACC) Interrupt Enable Register */
+#define REG_DACC_IDR  (*(WoReg*)0x400C8028U) /**< \brief (DACC) Interrupt Disable Register */
+#define REG_DACC_IMR  (*(RoReg*)0x400C802CU) /**< \brief (DACC) Interrupt Mask Register */
+#define REG_DACC_ISR  (*(RoReg*)0x400C8030U) /**< \brief (DACC) Interrupt Status Register */
+#define REG_DACC_ACR  (*(RwReg*)0x400C8094U) /**< \brief (DACC) Analog Current Register */
+#define REG_DACC_WPMR (*(RwReg*)0x400C80E4U) /**< \brief (DACC) Write Protect Mode register */
+#define REG_DACC_WPSR (*(RoReg*)0x400C80E8U) /**< \brief (DACC) Write Protect Status register */
+#define REG_DACC_RPR  (*(RwReg*)0x400C8100U) /**< \brief (DACC) Receive Pointer Register */
+#define REG_DACC_RCR  (*(RwReg*)0x400C8104U) /**< \brief (DACC) Receive Counter Register */
+#define REG_DACC_TPR  (*(RwReg*)0x400C8108U) /**< \brief (DACC) Transmit Pointer Register */
+#define REG_DACC_TCR  (*(RwReg*)0x400C810CU) /**< \brief (DACC) Transmit Counter Register */
+#define REG_DACC_RNPR (*(RwReg*)0x400C8110U) /**< \brief (DACC) Receive Next Pointer Register */
+#define REG_DACC_RNCR (*(RwReg*)0x400C8114U) /**< \brief (DACC) Receive Next Counter Register */
+#define REG_DACC_TNPR (*(RwReg*)0x400C8118U) /**< \brief (DACC) Transmit Next Pointer Register */
+#define REG_DACC_TNCR (*(RwReg*)0x400C811CU) /**< \brief (DACC) Transmit Next Counter Register */
+#define REG_DACC_PTCR (*(WoReg*)0x400C8120U) /**< \brief (DACC) Transfer Control Register */
+#define REG_DACC_PTSR (*(RoReg*)0x400C8124U) /**< \brief (DACC) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_DACC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_dmac.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_dmac.h
new file mode 100644
index 000000000..1301e38eb
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_dmac.h
@@ -0,0 +1,138 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_DMAC_INSTANCE_
+#define _SAM3XA_DMAC_INSTANCE_
+
+/* ========== Register definition for DMAC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_DMAC_GCFG            (0x400C4000U) /**< \brief (DMAC) DMAC Global Configuration Register */
+#define REG_DMAC_EN              (0x400C4004U) /**< \brief (DMAC) DMAC Enable Register */
+#define REG_DMAC_SREQ            (0x400C4008U) /**< \brief (DMAC) DMAC Software Single Request Register */
+#define REG_DMAC_CREQ            (0x400C400CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */
+#define REG_DMAC_LAST            (0x400C4010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */
+#define REG_DMAC_EBCIER          (0x400C4018U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */
+#define REG_DMAC_EBCIDR          (0x400C401CU) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */
+#define REG_DMAC_EBCIMR          (0x400C4020U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */
+#define REG_DMAC_EBCISR          (0x400C4024U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */
+#define REG_DMAC_CHER            (0x400C4028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */
+#define REG_DMAC_CHDR            (0x400C402CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */
+#define REG_DMAC_CHSR            (0x400C4030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */
+#define REG_DMAC_SADDR0          (0x400C403CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */
+#define REG_DMAC_DADDR0          (0x400C4040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */
+#define REG_DMAC_DSCR0           (0x400C4044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */
+#define REG_DMAC_CTRLA0          (0x400C4048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */
+#define REG_DMAC_CTRLB0          (0x400C404CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */
+#define REG_DMAC_CFG0            (0x400C4050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */
+#define REG_DMAC_SADDR1          (0x400C4064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */
+#define REG_DMAC_DADDR1          (0x400C4068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */
+#define REG_DMAC_DSCR1           (0x400C406CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */
+#define REG_DMAC_CTRLA1          (0x400C4070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */
+#define REG_DMAC_CTRLB1          (0x400C4074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */
+#define REG_DMAC_CFG1            (0x400C4078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */
+#define REG_DMAC_SADDR2          (0x400C408CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */
+#define REG_DMAC_DADDR2          (0x400C4090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */
+#define REG_DMAC_DSCR2           (0x400C4094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */
+#define REG_DMAC_CTRLA2          (0x400C4098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */
+#define REG_DMAC_CTRLB2          (0x400C409CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */
+#define REG_DMAC_CFG2            (0x400C40A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */
+#define REG_DMAC_SADDR3          (0x400C40B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */
+#define REG_DMAC_DADDR3          (0x400C40B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */
+#define REG_DMAC_DSCR3           (0x400C40BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */
+#define REG_DMAC_CTRLA3          (0x400C40C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */
+#define REG_DMAC_CTRLB3          (0x400C40C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */
+#define REG_DMAC_CFG3            (0x400C40C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */
+#define REG_DMAC_SADDR4          (0x400C40DCU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 4) */
+#define REG_DMAC_DADDR4          (0x400C40E0U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 4) */
+#define REG_DMAC_DSCR4           (0x400C40E4U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 4) */
+#define REG_DMAC_CTRLA4          (0x400C40E8U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 4) */
+#define REG_DMAC_CTRLB4          (0x400C40ECU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 4) */
+#define REG_DMAC_CFG4            (0x400C40F0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 4) */
+#define REG_DMAC_SADDR5          (0x400C4104U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 5) */
+#define REG_DMAC_DADDR5          (0x400C4108U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 5) */
+#define REG_DMAC_DSCR5           (0x400C410CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 5) */
+#define REG_DMAC_CTRLA5          (0x400C4110U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 5) */
+#define REG_DMAC_CTRLB5          (0x400C4114U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 5) */
+#define REG_DMAC_CFG5            (0x400C4118U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 5) */
+#define REG_DMAC_WPMR            (0x400C41E4U) /**< \brief (DMAC) DMAC Write Protect Mode Register */
+#define REG_DMAC_WPSR            (0x400C41E8U) /**< \brief (DMAC) DMAC Write Protect Status Register */
+#else
+#define REG_DMAC_GCFG   (*(RwReg*)0x400C4000U) /**< \brief (DMAC) DMAC Global Configuration Register */
+#define REG_DMAC_EN     (*(RwReg*)0x400C4004U) /**< \brief (DMAC) DMAC Enable Register */
+#define REG_DMAC_SREQ   (*(RwReg*)0x400C4008U) /**< \brief (DMAC) DMAC Software Single Request Register */
+#define REG_DMAC_CREQ   (*(RwReg*)0x400C400CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */
+#define REG_DMAC_LAST   (*(RwReg*)0x400C4010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */
+#define REG_DMAC_EBCIER (*(WoReg*)0x400C4018U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */
+#define REG_DMAC_EBCIDR (*(WoReg*)0x400C401CU) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */
+#define REG_DMAC_EBCIMR (*(RoReg*)0x400C4020U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */
+#define REG_DMAC_EBCISR (*(RoReg*)0x400C4024U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */
+#define REG_DMAC_CHER   (*(WoReg*)0x400C4028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */
+#define REG_DMAC_CHDR   (*(WoReg*)0x400C402CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */
+#define REG_DMAC_CHSR   (*(RoReg*)0x400C4030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */
+#define REG_DMAC_SADDR0 (*(RwReg*)0x400C403CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */
+#define REG_DMAC_DADDR0 (*(RwReg*)0x400C4040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */
+#define REG_DMAC_DSCR0  (*(RwReg*)0x400C4044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */
+#define REG_DMAC_CTRLA0 (*(RwReg*)0x400C4048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */
+#define REG_DMAC_CTRLB0 (*(RwReg*)0x400C404CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */
+#define REG_DMAC_CFG0   (*(RwReg*)0x400C4050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */
+#define REG_DMAC_SADDR1 (*(RwReg*)0x400C4064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */
+#define REG_DMAC_DADDR1 (*(RwReg*)0x400C4068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */
+#define REG_DMAC_DSCR1  (*(RwReg*)0x400C406CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */
+#define REG_DMAC_CTRLA1 (*(RwReg*)0x400C4070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */
+#define REG_DMAC_CTRLB1 (*(RwReg*)0x400C4074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */
+#define REG_DMAC_CFG1   (*(RwReg*)0x400C4078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */
+#define REG_DMAC_SADDR2 (*(RwReg*)0x400C408CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */
+#define REG_DMAC_DADDR2 (*(RwReg*)0x400C4090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */
+#define REG_DMAC_DSCR2  (*(RwReg*)0x400C4094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */
+#define REG_DMAC_CTRLA2 (*(RwReg*)0x400C4098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */
+#define REG_DMAC_CTRLB2 (*(RwReg*)0x400C409CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */
+#define REG_DMAC_CFG2   (*(RwReg*)0x400C40A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */
+#define REG_DMAC_SADDR3 (*(RwReg*)0x400C40B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */
+#define REG_DMAC_DADDR3 (*(RwReg*)0x400C40B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */
+#define REG_DMAC_DSCR3  (*(RwReg*)0x400C40BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */
+#define REG_DMAC_CTRLA3 (*(RwReg*)0x400C40C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */
+#define REG_DMAC_CTRLB3 (*(RwReg*)0x400C40C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */
+#define REG_DMAC_CFG3   (*(RwReg*)0x400C40C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */
+#define REG_DMAC_SADDR4 (*(RwReg*)0x400C40DCU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 4) */
+#define REG_DMAC_DADDR4 (*(RwReg*)0x400C40E0U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 4) */
+#define REG_DMAC_DSCR4  (*(RwReg*)0x400C40E4U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 4) */
+#define REG_DMAC_CTRLA4 (*(RwReg*)0x400C40E8U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 4) */
+#define REG_DMAC_CTRLB4 (*(RwReg*)0x400C40ECU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 4) */
+#define REG_DMAC_CFG4   (*(RwReg*)0x400C40F0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 4) */
+#define REG_DMAC_SADDR5 (*(RwReg*)0x400C4104U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 5) */
+#define REG_DMAC_DADDR5 (*(RwReg*)0x400C4108U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 5) */
+#define REG_DMAC_DSCR5  (*(RwReg*)0x400C410CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 5) */
+#define REG_DMAC_CTRLA5 (*(RwReg*)0x400C4110U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 5) */
+#define REG_DMAC_CTRLB5 (*(RwReg*)0x400C4114U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 5) */
+#define REG_DMAC_CFG5   (*(RwReg*)0x400C4118U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 5) */
+#define REG_DMAC_WPMR   (*(RwReg*)0x400C41E4U) /**< \brief (DMAC) DMAC Write Protect Mode Register */
+#define REG_DMAC_WPSR   (*(RoReg*)0x400C41E8U) /**< \brief (DMAC) DMAC Write Protect Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_DMAC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_efc0.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_efc0.h
new file mode 100644
index 000000000..278d2cc57
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_efc0.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_EFC0_INSTANCE_
+#define _SAM3XA_EFC0_INSTANCE_
+
+/* ========== Register definition for EFC0 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_EFC0_FMR           (0x400E0A00U) /**< \brief (EFC0) EEFC Flash Mode Register */
+#define REG_EFC0_FCR           (0x400E0A04U) /**< \brief (EFC0) EEFC Flash Command Register */
+#define REG_EFC0_FSR           (0x400E0A08U) /**< \brief (EFC0) EEFC Flash Status Register */
+#define REG_EFC0_FRR           (0x400E0A0CU) /**< \brief (EFC0) EEFC Flash Result Register */
+#else
+#define REG_EFC0_FMR  (*(RwReg*)0x400E0A00U) /**< \brief (EFC0) EEFC Flash Mode Register */
+#define REG_EFC0_FCR  (*(WoReg*)0x400E0A04U) /**< \brief (EFC0) EEFC Flash Command Register */
+#define REG_EFC0_FSR  (*(RoReg*)0x400E0A08U) /**< \brief (EFC0) EEFC Flash Status Register */
+#define REG_EFC0_FRR  (*(RoReg*)0x400E0A0CU) /**< \brief (EFC0) EEFC Flash Result Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_EFC0_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_efc1.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_efc1.h
new file mode 100644
index 000000000..3fb5cb54c
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_efc1.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_EFC1_INSTANCE_
+#define _SAM3XA_EFC1_INSTANCE_
+
+/* ========== Register definition for EFC1 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_EFC1_FMR           (0x400E0C00U) /**< \brief (EFC1) EEFC Flash Mode Register */
+#define REG_EFC1_FCR           (0x400E0C04U) /**< \brief (EFC1) EEFC Flash Command Register */
+#define REG_EFC1_FSR           (0x400E0C08U) /**< \brief (EFC1) EEFC Flash Status Register */
+#define REG_EFC1_FRR           (0x400E0C0CU) /**< \brief (EFC1) EEFC Flash Result Register */
+#else
+#define REG_EFC1_FMR  (*(RwReg*)0x400E0C00U) /**< \brief (EFC1) EEFC Flash Mode Register */
+#define REG_EFC1_FCR  (*(WoReg*)0x400E0C04U) /**< \brief (EFC1) EEFC Flash Command Register */
+#define REG_EFC1_FSR  (*(RoReg*)0x400E0C08U) /**< \brief (EFC1) EEFC Flash Status Register */
+#define REG_EFC1_FRR  (*(RoReg*)0x400E0C0CU) /**< \brief (EFC1) EEFC Flash Result Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_EFC1_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_emac.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_emac.h
new file mode 100644
index 000000000..c67415ea3
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_emac.h
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_EMAC_INSTANCE_
+#define _SAM3XA_EMAC_INSTANCE_
+
+/* ========== Register definition for EMAC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_EMAC_NCR            (0x400B0000U) /**< \brief (EMAC) Network Control Register */
+#define REG_EMAC_NCFGR          (0x400B0004U) /**< \brief (EMAC) Network Configuration Register */
+#define REG_EMAC_NSR            (0x400B0008U) /**< \brief (EMAC) Network Status Register */
+#define REG_EMAC_TSR            (0x400B0014U) /**< \brief (EMAC) Transmit Status Register */
+#define REG_EMAC_RBQP           (0x400B0018U) /**< \brief (EMAC) Receive Buffer Queue Pointer Register */
+#define REG_EMAC_TBQP           (0x400B001CU) /**< \brief (EMAC) Transmit Buffer Queue Pointer Register */
+#define REG_EMAC_RSR            (0x400B0020U) /**< \brief (EMAC) Receive Status Register */
+#define REG_EMAC_ISR            (0x400B0024U) /**< \brief (EMAC) Interrupt Status Register */
+#define REG_EMAC_IER            (0x400B0028U) /**< \brief (EMAC) Interrupt Enable Register */
+#define REG_EMAC_IDR            (0x400B002CU) /**< \brief (EMAC) Interrupt Disable Register */
+#define REG_EMAC_IMR            (0x400B0030U) /**< \brief (EMAC) Interrupt Mask Register */
+#define REG_EMAC_MAN            (0x400B0034U) /**< \brief (EMAC) Phy Maintenance Register */
+#define REG_EMAC_PTR            (0x400B0038U) /**< \brief (EMAC) Pause Time Register */
+#define REG_EMAC_PFR            (0x400B003CU) /**< \brief (EMAC) Pause Frames Received Register */
+#define REG_EMAC_FTO            (0x400B0040U) /**< \brief (EMAC) Frames Transmitted Ok Register */
+#define REG_EMAC_SCF            (0x400B0044U) /**< \brief (EMAC) Single Collision Frames Register */
+#define REG_EMAC_MCF            (0x400B0048U) /**< \brief (EMAC) Multiple Collision Frames Register */
+#define REG_EMAC_FRO            (0x400B004CU) /**< \brief (EMAC) Frames Received Ok Register */
+#define REG_EMAC_FCSE           (0x400B0050U) /**< \brief (EMAC) Frame Check Sequence Errors Register */
+#define REG_EMAC_ALE            (0x400B0054U) /**< \brief (EMAC) Alignment Errors Register */
+#define REG_EMAC_DTF            (0x400B0058U) /**< \brief (EMAC) Deferred Transmission Frames Register */
+#define REG_EMAC_LCOL           (0x400B005CU) /**< \brief (EMAC) Late Collisions Register */
+#define REG_EMAC_ECOL           (0x400B0060U) /**< \brief (EMAC) Excessive Collisions Register */
+#define REG_EMAC_TUND           (0x400B0064U) /**< \brief (EMAC) Transmit Underrun Errors Register */
+#define REG_EMAC_CSE            (0x400B0068U) /**< \brief (EMAC) Carrier Sense Errors Register */
+#define REG_EMAC_RRE            (0x400B006CU) /**< \brief (EMAC) Receive Resource Errors Register */
+#define REG_EMAC_ROV            (0x400B0070U) /**< \brief (EMAC) Receive Overrun Errors Register */
+#define REG_EMAC_RSE            (0x400B0074U) /**< \brief (EMAC) Receive Symbol Errors Register */
+#define REG_EMAC_ELE            (0x400B0078U) /**< \brief (EMAC) Excessive Length Errors Register */
+#define REG_EMAC_RJA            (0x400B007CU) /**< \brief (EMAC) Receive Jabbers Register */
+#define REG_EMAC_USF            (0x400B0080U) /**< \brief (EMAC) Undersize Frames Register */
+#define REG_EMAC_STE            (0x400B0084U) /**< \brief (EMAC) SQE Test Errors Register */
+#define REG_EMAC_RLE            (0x400B0088U) /**< \brief (EMAC) Received Length Field Mismatch Register */
+#define REG_EMAC_HRB            (0x400B0090U) /**< \brief (EMAC) Hash Register Bottom [31:0] Register */
+#define REG_EMAC_HRT            (0x400B0094U) /**< \brief (EMAC) Hash Register Top [63:32] Register */
+#define REG_EMAC_SA1B           (0x400B0098U) /**< \brief (EMAC) Specific Address 1 Bottom Register */
+#define REG_EMAC_SA1T           (0x400B009CU) /**< \brief (EMAC) Specific Address 1 Top Register */
+#define REG_EMAC_SA2B           (0x400B00A0U) /**< \brief (EMAC) Specific Address 2 Bottom Register */
+#define REG_EMAC_SA2T           (0x400B00A4U) /**< \brief (EMAC) Specific Address 2 Top Register */
+#define REG_EMAC_SA3B           (0x400B00A8U) /**< \brief (EMAC) Specific Address 3 Bottom Register */
+#define REG_EMAC_SA3T           (0x400B00ACU) /**< \brief (EMAC) Specific Address 3 Top Register */
+#define REG_EMAC_SA4B           (0x400B00B0U) /**< \brief (EMAC) Specific Address 4 Bottom Register */
+#define REG_EMAC_SA4T           (0x400B00B4U) /**< \brief (EMAC) Specific Address 4 Top Register */
+#define REG_EMAC_TID            (0x400B00B8U) /**< \brief (EMAC) Type ID Checking Register */
+#define REG_EMAC_USRIO          (0x400B00C0U) /**< \brief (EMAC) User Input/Output Register */
+#else
+#define REG_EMAC_NCR   (*(RwReg*)0x400B0000U) /**< \brief (EMAC) Network Control Register */
+#define REG_EMAC_NCFGR (*(RwReg*)0x400B0004U) /**< \brief (EMAC) Network Configuration Register */
+#define REG_EMAC_NSR   (*(RoReg*)0x400B0008U) /**< \brief (EMAC) Network Status Register */
+#define REG_EMAC_TSR   (*(RwReg*)0x400B0014U) /**< \brief (EMAC) Transmit Status Register */
+#define REG_EMAC_RBQP  (*(RwReg*)0x400B0018U) /**< \brief (EMAC) Receive Buffer Queue Pointer Register */
+#define REG_EMAC_TBQP  (*(RwReg*)0x400B001CU) /**< \brief (EMAC) Transmit Buffer Queue Pointer Register */
+#define REG_EMAC_RSR   (*(RwReg*)0x400B0020U) /**< \brief (EMAC) Receive Status Register */
+#define REG_EMAC_ISR   (*(RwReg*)0x400B0024U) /**< \brief (EMAC) Interrupt Status Register */
+#define REG_EMAC_IER   (*(WoReg*)0x400B0028U) /**< \brief (EMAC) Interrupt Enable Register */
+#define REG_EMAC_IDR   (*(WoReg*)0x400B002CU) /**< \brief (EMAC) Interrupt Disable Register */
+#define REG_EMAC_IMR   (*(RoReg*)0x400B0030U) /**< \brief (EMAC) Interrupt Mask Register */
+#define REG_EMAC_MAN   (*(RwReg*)0x400B0034U) /**< \brief (EMAC) Phy Maintenance Register */
+#define REG_EMAC_PTR   (*(RwReg*)0x400B0038U) /**< \brief (EMAC) Pause Time Register */
+#define REG_EMAC_PFR   (*(RwReg*)0x400B003CU) /**< \brief (EMAC) Pause Frames Received Register */
+#define REG_EMAC_FTO   (*(RwReg*)0x400B0040U) /**< \brief (EMAC) Frames Transmitted Ok Register */
+#define REG_EMAC_SCF   (*(RwReg*)0x400B0044U) /**< \brief (EMAC) Single Collision Frames Register */
+#define REG_EMAC_MCF   (*(RwReg*)0x400B0048U) /**< \brief (EMAC) Multiple Collision Frames Register */
+#define REG_EMAC_FRO   (*(RwReg*)0x400B004CU) /**< \brief (EMAC) Frames Received Ok Register */
+#define REG_EMAC_FCSE  (*(RwReg*)0x400B0050U) /**< \brief (EMAC) Frame Check Sequence Errors Register */
+#define REG_EMAC_ALE   (*(RwReg*)0x400B0054U) /**< \brief (EMAC) Alignment Errors Register */
+#define REG_EMAC_DTF   (*(RwReg*)0x400B0058U) /**< \brief (EMAC) Deferred Transmission Frames Register */
+#define REG_EMAC_LCOL  (*(RwReg*)0x400B005CU) /**< \brief (EMAC) Late Collisions Register */
+#define REG_EMAC_ECOL  (*(RwReg*)0x400B0060U) /**< \brief (EMAC) Excessive Collisions Register */
+#define REG_EMAC_TUND  (*(RwReg*)0x400B0064U) /**< \brief (EMAC) Transmit Underrun Errors Register */
+#define REG_EMAC_CSE   (*(RwReg*)0x400B0068U) /**< \brief (EMAC) Carrier Sense Errors Register */
+#define REG_EMAC_RRE   (*(RwReg*)0x400B006CU) /**< \brief (EMAC) Receive Resource Errors Register */
+#define REG_EMAC_ROV   (*(RwReg*)0x400B0070U) /**< \brief (EMAC) Receive Overrun Errors Register */
+#define REG_EMAC_RSE   (*(RwReg*)0x400B0074U) /**< \brief (EMAC) Receive Symbol Errors Register */
+#define REG_EMAC_ELE   (*(RwReg*)0x400B0078U) /**< \brief (EMAC) Excessive Length Errors Register */
+#define REG_EMAC_RJA   (*(RwReg*)0x400B007CU) /**< \brief (EMAC) Receive Jabbers Register */
+#define REG_EMAC_USF   (*(RwReg*)0x400B0080U) /**< \brief (EMAC) Undersize Frames Register */
+#define REG_EMAC_STE   (*(RwReg*)0x400B0084U) /**< \brief (EMAC) SQE Test Errors Register */
+#define REG_EMAC_RLE   (*(RwReg*)0x400B0088U) /**< \brief (EMAC) Received Length Field Mismatch Register */
+#define REG_EMAC_HRB   (*(RwReg*)0x400B0090U) /**< \brief (EMAC) Hash Register Bottom [31:0] Register */
+#define REG_EMAC_HRT   (*(RwReg*)0x400B0094U) /**< \brief (EMAC) Hash Register Top [63:32] Register */
+#define REG_EMAC_SA1B  (*(RwReg*)0x400B0098U) /**< \brief (EMAC) Specific Address 1 Bottom Register */
+#define REG_EMAC_SA1T  (*(RwReg*)0x400B009CU) /**< \brief (EMAC) Specific Address 1 Top Register */
+#define REG_EMAC_SA2B  (*(RwReg*)0x400B00A0U) /**< \brief (EMAC) Specific Address 2 Bottom Register */
+#define REG_EMAC_SA2T  (*(RwReg*)0x400B00A4U) /**< \brief (EMAC) Specific Address 2 Top Register */
+#define REG_EMAC_SA3B  (*(RwReg*)0x400B00A8U) /**< \brief (EMAC) Specific Address 3 Bottom Register */
+#define REG_EMAC_SA3T  (*(RwReg*)0x400B00ACU) /**< \brief (EMAC) Specific Address 3 Top Register */
+#define REG_EMAC_SA4B  (*(RwReg*)0x400B00B0U) /**< \brief (EMAC) Specific Address 4 Bottom Register */
+#define REG_EMAC_SA4T  (*(RwReg*)0x400B00B4U) /**< \brief (EMAC) Specific Address 4 Top Register */
+#define REG_EMAC_TID   (*(RwReg*)0x400B00B8U) /**< \brief (EMAC) Type ID Checking Register */
+#define REG_EMAC_USRIO (*(RwReg*)0x400B00C0U) /**< \brief (EMAC) User Input/Output Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_EMAC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_gpbr.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_gpbr.h
new file mode 100644
index 000000000..b96b12e94
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_gpbr.h
@@ -0,0 +1,40 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_GPBR_INSTANCE_
+#define _SAM3XA_GPBR_INSTANCE_
+
+/* ========== Register definition for GPBR peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_GPBR_GPBR            (0x400E1A90U) /**< \brief (GPBR) General Purpose Backup Register */
+#else
+#define REG_GPBR_GPBR   (*(RwReg*)0x400E1A90U) /**< \brief (GPBR) General Purpose Backup Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_GPBR_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_hsmci.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_hsmci.h
new file mode 100644
index 000000000..8fbfe4fd4
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_hsmci.h
@@ -0,0 +1,78 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_HSMCI_INSTANCE_
+#define _SAM3XA_HSMCI_INSTANCE_
+
+/* ========== Register definition for HSMCI peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_HSMCI_CR                 (0x40000000U) /**< \brief (HSMCI) Control Register */
+#define REG_HSMCI_MR                 (0x40000004U) /**< \brief (HSMCI) Mode Register */
+#define REG_HSMCI_DTOR               (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
+#define REG_HSMCI_SDCR               (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
+#define REG_HSMCI_ARGR               (0x40000010U) /**< \brief (HSMCI) Argument Register */
+#define REG_HSMCI_CMDR               (0x40000014U) /**< \brief (HSMCI) Command Register */
+#define REG_HSMCI_BLKR               (0x40000018U) /**< \brief (HSMCI) Block Register */
+#define REG_HSMCI_CSTOR              (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
+#define REG_HSMCI_RSPR               (0x40000020U) /**< \brief (HSMCI) Response Register */
+#define REG_HSMCI_RDR                (0x40000030U) /**< \brief (HSMCI) Receive Data Register */
+#define REG_HSMCI_TDR                (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
+#define REG_HSMCI_SR                 (0x40000040U) /**< \brief (HSMCI) Status Register */
+#define REG_HSMCI_IER                (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
+#define REG_HSMCI_IDR                (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
+#define REG_HSMCI_IMR                (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
+#define REG_HSMCI_DMA                (0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */
+#define REG_HSMCI_CFG                (0x40000054U) /**< \brief (HSMCI) Configuration Register */
+#define REG_HSMCI_WPMR               (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
+#define REG_HSMCI_WPSR               (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
+#define REG_HSMCI_FIFO               (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
+#else
+#define REG_HSMCI_CR        (*(WoReg*)0x40000000U) /**< \brief (HSMCI) Control Register */
+#define REG_HSMCI_MR        (*(RwReg*)0x40000004U) /**< \brief (HSMCI) Mode Register */
+#define REG_HSMCI_DTOR      (*(RwReg*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
+#define REG_HSMCI_SDCR      (*(RwReg*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
+#define REG_HSMCI_ARGR      (*(RwReg*)0x40000010U) /**< \brief (HSMCI) Argument Register */
+#define REG_HSMCI_CMDR      (*(WoReg*)0x40000014U) /**< \brief (HSMCI) Command Register */
+#define REG_HSMCI_BLKR      (*(RwReg*)0x40000018U) /**< \brief (HSMCI) Block Register */
+#define REG_HSMCI_CSTOR     (*(RwReg*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
+#define REG_HSMCI_RSPR      (*(RoReg*)0x40000020U) /**< \brief (HSMCI) Response Register */
+#define REG_HSMCI_RDR       (*(RoReg*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */
+#define REG_HSMCI_TDR       (*(WoReg*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
+#define REG_HSMCI_SR        (*(RoReg*)0x40000040U) /**< \brief (HSMCI) Status Register */
+#define REG_HSMCI_IER       (*(WoReg*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
+#define REG_HSMCI_IDR       (*(WoReg*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
+#define REG_HSMCI_IMR       (*(RoReg*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
+#define REG_HSMCI_DMA       (*(RwReg*)0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */
+#define REG_HSMCI_CFG       (*(RwReg*)0x40000054U) /**< \brief (HSMCI) Configuration Register */
+#define REG_HSMCI_WPMR      (*(RwReg*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
+#define REG_HSMCI_WPSR      (*(RoReg*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
+#define REG_HSMCI_FIFO      (*(RwReg*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_HSMCI_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_matrix.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_matrix.h
new file mode 100644
index 000000000..c7fe7ec62
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_matrix.h
@@ -0,0 +1,68 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_MATRIX_INSTANCE_
+#define _SAM3XA_MATRIX_INSTANCE_
+
+/* ========== Register definition for MATRIX peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_MATRIX_MCFG             (0x400E0400U) /**< \brief (MATRIX) Master Configuration Register */
+#define REG_MATRIX_SCFG             (0x400E0440U) /**< \brief (MATRIX) Slave Configuration Register */
+#define REG_MATRIX_PRAS0            (0x400E0480U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
+#define REG_MATRIX_PRAS1            (0x400E0488U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
+#define REG_MATRIX_PRAS2            (0x400E0490U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
+#define REG_MATRIX_PRAS3            (0x400E0498U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
+#define REG_MATRIX_PRAS4            (0x400E04A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
+#define REG_MATRIX_PRAS5            (0x400E04A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
+#define REG_MATRIX_PRAS6            (0x400E04B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
+#define REG_MATRIX_PRAS7            (0x400E04B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
+#define REG_MATRIX_PRAS8            (0x400E04C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
+#define REG_MATRIX_MRCR             (0x400E0500U) /**< \brief (MATRIX) Master Remap Control Register */
+#define REG_CCFG_SYSIO              (0x400E0514U) /**< \brief (MATRIX) System I/O Configuration register */
+#define REG_MATRIX_WPMR             (0x400E05E4U) /**< \brief (MATRIX) Write Protect Mode Register */
+#define REG_MATRIX_WPSR             (0x400E05E8U) /**< \brief (MATRIX) Write Protect Status Register */
+#else
+#define REG_MATRIX_MCFG    (*(RwReg*)0x400E0400U) /**< \brief (MATRIX) Master Configuration Register */
+#define REG_MATRIX_SCFG    (*(RwReg*)0x400E0440U) /**< \brief (MATRIX) Slave Configuration Register */
+#define REG_MATRIX_PRAS0   (*(RwReg*)0x400E0480U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
+#define REG_MATRIX_PRAS1   (*(RwReg*)0x400E0488U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
+#define REG_MATRIX_PRAS2   (*(RwReg*)0x400E0490U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
+#define REG_MATRIX_PRAS3   (*(RwReg*)0x400E0498U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
+#define REG_MATRIX_PRAS4   (*(RwReg*)0x400E04A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
+#define REG_MATRIX_PRAS5   (*(RwReg*)0x400E04A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
+#define REG_MATRIX_PRAS6   (*(RwReg*)0x400E04B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
+#define REG_MATRIX_PRAS7   (*(RwReg*)0x400E04B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
+#define REG_MATRIX_PRAS8   (*(RwReg*)0x400E04C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
+#define REG_MATRIX_MRCR    (*(RwReg*)0x400E0500U) /**< \brief (MATRIX) Master Remap Control Register */
+#define REG_CCFG_SYSIO     (*(RwReg*)0x400E0514U) /**< \brief (MATRIX) System I/O Configuration register */
+#define REG_MATRIX_WPMR    (*(RwReg*)0x400E05E4U) /**< \brief (MATRIX) Write Protect Mode Register */
+#define REG_MATRIX_WPSR    (*(RoReg*)0x400E05E8U) /**< \brief (MATRIX) Write Protect Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_MATRIX_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_pioa.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_pioa.h
new file mode 100644
index 000000000..b678d0598
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_pioa.h
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PIOA_INSTANCE_
+#define _SAM3XA_PIOA_INSTANCE_
+
+/* ========== Register definition for PIOA peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PIOA_PER             (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
+#define REG_PIOA_PDR             (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
+#define REG_PIOA_PSR             (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
+#define REG_PIOA_OER             (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
+#define REG_PIOA_ODR             (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
+#define REG_PIOA_OSR             (0x400E0E18U) /**< \brief (PIOA) Output Status Register */
+#define REG_PIOA_IFER            (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
+#define REG_PIOA_IFDR            (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
+#define REG_PIOA_IFSR            (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
+#define REG_PIOA_SODR            (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
+#define REG_PIOA_CODR            (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
+#define REG_PIOA_ODSR            (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
+#define REG_PIOA_PDSR            (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
+#define REG_PIOA_IER             (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
+#define REG_PIOA_IDR             (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
+#define REG_PIOA_IMR             (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
+#define REG_PIOA_ISR             (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
+#define REG_PIOA_MDER            (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
+#define REG_PIOA_MDDR            (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
+#define REG_PIOA_MDSR            (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
+#define REG_PIOA_PUDR            (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
+#define REG_PIOA_PUER            (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
+#define REG_PIOA_PUSR            (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
+#define REG_PIOA_ABSR            (0x400E0E70U) /**< \brief (PIOA) Peripheral AB Select Register */
+#define REG_PIOA_SCIFSR          (0x400E0E80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */
+#define REG_PIOA_DIFSR           (0x400E0E84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */
+#define REG_PIOA_IFDGSR          (0x400E0E88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOA_SCDR            (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
+#define REG_PIOA_OWER            (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
+#define REG_PIOA_OWDR            (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
+#define REG_PIOA_OWSR            (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
+#define REG_PIOA_AIMER           (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
+#define REG_PIOA_AIMDR           (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
+#define REG_PIOA_AIMMR           (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
+#define REG_PIOA_ESR             (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
+#define REG_PIOA_LSR             (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
+#define REG_PIOA_ELSR            (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
+#define REG_PIOA_FELLSR          (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
+#define REG_PIOA_REHLSR          (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
+#define REG_PIOA_FRLHSR          (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
+#define REG_PIOA_LOCKSR          (0x400E0EE0U) /**< \brief (PIOA) Lock Status */
+#define REG_PIOA_WPMR            (0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
+#define REG_PIOA_WPSR            (0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
+#else
+#define REG_PIOA_PER    (*(WoReg*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
+#define REG_PIOA_PDR    (*(WoReg*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
+#define REG_PIOA_PSR    (*(RoReg*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
+#define REG_PIOA_OER    (*(WoReg*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
+#define REG_PIOA_ODR    (*(WoReg*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
+#define REG_PIOA_OSR    (*(RoReg*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */
+#define REG_PIOA_IFER   (*(WoReg*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
+#define REG_PIOA_IFDR   (*(WoReg*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
+#define REG_PIOA_IFSR   (*(RoReg*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
+#define REG_PIOA_SODR   (*(WoReg*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
+#define REG_PIOA_CODR   (*(WoReg*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
+#define REG_PIOA_ODSR   (*(RwReg*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
+#define REG_PIOA_PDSR   (*(RoReg*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
+#define REG_PIOA_IER    (*(WoReg*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
+#define REG_PIOA_IDR    (*(WoReg*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
+#define REG_PIOA_IMR    (*(RoReg*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
+#define REG_PIOA_ISR    (*(RoReg*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
+#define REG_PIOA_MDER   (*(WoReg*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
+#define REG_PIOA_MDDR   (*(WoReg*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
+#define REG_PIOA_MDSR   (*(RoReg*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
+#define REG_PIOA_PUDR   (*(WoReg*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
+#define REG_PIOA_PUER   (*(WoReg*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
+#define REG_PIOA_PUSR   (*(RoReg*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
+#define REG_PIOA_ABSR   (*(RwReg*)0x400E0E70U) /**< \brief (PIOA) Peripheral AB Select Register */
+#define REG_PIOA_SCIFSR (*(WoReg*)0x400E0E80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */
+#define REG_PIOA_DIFSR  (*(WoReg*)0x400E0E84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */
+#define REG_PIOA_IFDGSR (*(RoReg*)0x400E0E88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOA_SCDR   (*(RwReg*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
+#define REG_PIOA_OWER   (*(WoReg*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
+#define REG_PIOA_OWDR   (*(WoReg*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
+#define REG_PIOA_OWSR   (*(RoReg*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
+#define REG_PIOA_AIMER  (*(WoReg*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
+#define REG_PIOA_AIMDR  (*(WoReg*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
+#define REG_PIOA_AIMMR  (*(RoReg*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
+#define REG_PIOA_ESR    (*(WoReg*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
+#define REG_PIOA_LSR    (*(WoReg*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
+#define REG_PIOA_ELSR   (*(RoReg*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
+#define REG_PIOA_FELLSR (*(WoReg*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
+#define REG_PIOA_REHLSR (*(WoReg*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
+#define REG_PIOA_FRLHSR (*(RoReg*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
+#define REG_PIOA_LOCKSR (*(RoReg*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */
+#define REG_PIOA_WPMR   (*(RwReg*)0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
+#define REG_PIOA_WPSR   (*(RoReg*)0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_PIOA_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_piob.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_piob.h
new file mode 100644
index 000000000..36e88e401
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_piob.h
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PIOB_INSTANCE_
+#define _SAM3XA_PIOB_INSTANCE_
+
+/* ========== Register definition for PIOB peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PIOB_PER             (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
+#define REG_PIOB_PDR             (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
+#define REG_PIOB_PSR             (0x400E1008U) /**< \brief (PIOB) PIO Status Register */
+#define REG_PIOB_OER             (0x400E1010U) /**< \brief (PIOB) Output Enable Register */
+#define REG_PIOB_ODR             (0x400E1014U) /**< \brief (PIOB) Output Disable Register */
+#define REG_PIOB_OSR             (0x400E1018U) /**< \brief (PIOB) Output Status Register */
+#define REG_PIOB_IFER            (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
+#define REG_PIOB_IFDR            (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
+#define REG_PIOB_IFSR            (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
+#define REG_PIOB_SODR            (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
+#define REG_PIOB_CODR            (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
+#define REG_PIOB_ODSR            (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
+#define REG_PIOB_PDSR            (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
+#define REG_PIOB_IER             (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
+#define REG_PIOB_IDR             (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
+#define REG_PIOB_IMR             (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
+#define REG_PIOB_ISR             (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
+#define REG_PIOB_MDER            (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
+#define REG_PIOB_MDDR            (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
+#define REG_PIOB_MDSR            (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
+#define REG_PIOB_PUDR            (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
+#define REG_PIOB_PUER            (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
+#define REG_PIOB_PUSR            (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
+#define REG_PIOB_ABSR            (0x400E1070U) /**< \brief (PIOB) Peripheral AB Select Register */
+#define REG_PIOB_SCIFSR          (0x400E1080U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */
+#define REG_PIOB_DIFSR           (0x400E1084U) /**< \brief (PIOB) Debouncing Input Filter Select Register */
+#define REG_PIOB_IFDGSR          (0x400E1088U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOB_SCDR            (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
+#define REG_PIOB_OWER            (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
+#define REG_PIOB_OWDR            (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
+#define REG_PIOB_OWSR            (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
+#define REG_PIOB_AIMER           (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
+#define REG_PIOB_AIMDR           (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
+#define REG_PIOB_AIMMR           (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
+#define REG_PIOB_ESR             (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
+#define REG_PIOB_LSR             (0x400E10C4U) /**< \brief (PIOB) Level Select Register */
+#define REG_PIOB_ELSR            (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
+#define REG_PIOB_FELLSR          (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
+#define REG_PIOB_REHLSR          (0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
+#define REG_PIOB_FRLHSR          (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
+#define REG_PIOB_LOCKSR          (0x400E10E0U) /**< \brief (PIOB) Lock Status */
+#define REG_PIOB_WPMR            (0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
+#define REG_PIOB_WPSR            (0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
+#else
+#define REG_PIOB_PER    (*(WoReg*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
+#define REG_PIOB_PDR    (*(WoReg*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
+#define REG_PIOB_PSR    (*(RoReg*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */
+#define REG_PIOB_OER    (*(WoReg*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */
+#define REG_PIOB_ODR    (*(WoReg*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */
+#define REG_PIOB_OSR    (*(RoReg*)0x400E1018U) /**< \brief (PIOB) Output Status Register */
+#define REG_PIOB_IFER   (*(WoReg*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
+#define REG_PIOB_IFDR   (*(WoReg*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
+#define REG_PIOB_IFSR   (*(RoReg*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
+#define REG_PIOB_SODR   (*(WoReg*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
+#define REG_PIOB_CODR   (*(WoReg*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
+#define REG_PIOB_ODSR   (*(RwReg*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
+#define REG_PIOB_PDSR   (*(RoReg*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
+#define REG_PIOB_IER    (*(WoReg*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
+#define REG_PIOB_IDR    (*(WoReg*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
+#define REG_PIOB_IMR    (*(RoReg*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
+#define REG_PIOB_ISR    (*(RoReg*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
+#define REG_PIOB_MDER   (*(WoReg*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
+#define REG_PIOB_MDDR   (*(WoReg*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
+#define REG_PIOB_MDSR   (*(RoReg*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
+#define REG_PIOB_PUDR   (*(WoReg*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
+#define REG_PIOB_PUER   (*(WoReg*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
+#define REG_PIOB_PUSR   (*(RoReg*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
+#define REG_PIOB_ABSR   (*(RwReg*)0x400E1070U) /**< \brief (PIOB) Peripheral AB Select Register */
+#define REG_PIOB_SCIFSR (*(WoReg*)0x400E1080U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */
+#define REG_PIOB_DIFSR  (*(WoReg*)0x400E1084U) /**< \brief (PIOB) Debouncing Input Filter Select Register */
+#define REG_PIOB_IFDGSR (*(RoReg*)0x400E1088U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOB_SCDR   (*(RwReg*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
+#define REG_PIOB_OWER   (*(WoReg*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
+#define REG_PIOB_OWDR   (*(WoReg*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
+#define REG_PIOB_OWSR   (*(RoReg*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
+#define REG_PIOB_AIMER  (*(WoReg*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
+#define REG_PIOB_AIMDR  (*(WoReg*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
+#define REG_PIOB_AIMMR  (*(RoReg*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
+#define REG_PIOB_ESR    (*(WoReg*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
+#define REG_PIOB_LSR    (*(WoReg*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */
+#define REG_PIOB_ELSR   (*(RoReg*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
+#define REG_PIOB_FELLSR (*(WoReg*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
+#define REG_PIOB_REHLSR (*(WoReg*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
+#define REG_PIOB_FRLHSR (*(RoReg*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
+#define REG_PIOB_LOCKSR (*(RoReg*)0x400E10E0U) /**< \brief (PIOB) Lock Status */
+#define REG_PIOB_WPMR   (*(RwReg*)0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
+#define REG_PIOB_WPSR   (*(RoReg*)0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_PIOB_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_pioc.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_pioc.h
new file mode 100644
index 000000000..bda3019ae
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_pioc.h
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PIOC_INSTANCE_
+#define _SAM3XA_PIOC_INSTANCE_
+
+/* ========== Register definition for PIOC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PIOC_PER             (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
+#define REG_PIOC_PDR             (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
+#define REG_PIOC_PSR             (0x400E1208U) /**< \brief (PIOC) PIO Status Register */
+#define REG_PIOC_OER             (0x400E1210U) /**< \brief (PIOC) Output Enable Register */
+#define REG_PIOC_ODR             (0x400E1214U) /**< \brief (PIOC) Output Disable Register */
+#define REG_PIOC_OSR             (0x400E1218U) /**< \brief (PIOC) Output Status Register */
+#define REG_PIOC_IFER            (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
+#define REG_PIOC_IFDR            (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
+#define REG_PIOC_IFSR            (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
+#define REG_PIOC_SODR            (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
+#define REG_PIOC_CODR            (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
+#define REG_PIOC_ODSR            (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
+#define REG_PIOC_PDSR            (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
+#define REG_PIOC_IER             (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
+#define REG_PIOC_IDR             (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
+#define REG_PIOC_IMR             (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
+#define REG_PIOC_ISR             (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
+#define REG_PIOC_MDER            (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
+#define REG_PIOC_MDDR            (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
+#define REG_PIOC_MDSR            (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
+#define REG_PIOC_PUDR            (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
+#define REG_PIOC_PUER            (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
+#define REG_PIOC_PUSR            (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
+#define REG_PIOC_ABSR            (0x400E1270U) /**< \brief (PIOC) Peripheral AB Select Register */
+#define REG_PIOC_SCIFSR          (0x400E1280U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */
+#define REG_PIOC_DIFSR           (0x400E1284U) /**< \brief (PIOC) Debouncing Input Filter Select Register */
+#define REG_PIOC_IFDGSR          (0x400E1288U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOC_SCDR            (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
+#define REG_PIOC_OWER            (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
+#define REG_PIOC_OWDR            (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
+#define REG_PIOC_OWSR            (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
+#define REG_PIOC_AIMER           (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
+#define REG_PIOC_AIMDR           (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
+#define REG_PIOC_AIMMR           (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
+#define REG_PIOC_ESR             (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
+#define REG_PIOC_LSR             (0x400E12C4U) /**< \brief (PIOC) Level Select Register */
+#define REG_PIOC_ELSR            (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
+#define REG_PIOC_FELLSR          (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
+#define REG_PIOC_REHLSR          (0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
+#define REG_PIOC_FRLHSR          (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
+#define REG_PIOC_LOCKSR          (0x400E12E0U) /**< \brief (PIOC) Lock Status */
+#define REG_PIOC_WPMR            (0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
+#define REG_PIOC_WPSR            (0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
+#else
+#define REG_PIOC_PER    (*(WoReg*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
+#define REG_PIOC_PDR    (*(WoReg*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
+#define REG_PIOC_PSR    (*(RoReg*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */
+#define REG_PIOC_OER    (*(WoReg*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */
+#define REG_PIOC_ODR    (*(WoReg*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */
+#define REG_PIOC_OSR    (*(RoReg*)0x400E1218U) /**< \brief (PIOC) Output Status Register */
+#define REG_PIOC_IFER   (*(WoReg*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
+#define REG_PIOC_IFDR   (*(WoReg*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
+#define REG_PIOC_IFSR   (*(RoReg*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
+#define REG_PIOC_SODR   (*(WoReg*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
+#define REG_PIOC_CODR   (*(WoReg*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
+#define REG_PIOC_ODSR   (*(RwReg*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
+#define REG_PIOC_PDSR   (*(RoReg*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
+#define REG_PIOC_IER    (*(WoReg*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
+#define REG_PIOC_IDR    (*(WoReg*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
+#define REG_PIOC_IMR    (*(RoReg*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
+#define REG_PIOC_ISR    (*(RoReg*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
+#define REG_PIOC_MDER   (*(WoReg*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
+#define REG_PIOC_MDDR   (*(WoReg*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
+#define REG_PIOC_MDSR   (*(RoReg*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
+#define REG_PIOC_PUDR   (*(WoReg*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
+#define REG_PIOC_PUER   (*(WoReg*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
+#define REG_PIOC_PUSR   (*(RoReg*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
+#define REG_PIOC_ABSR   (*(RwReg*)0x400E1270U) /**< \brief (PIOC) Peripheral AB Select Register */
+#define REG_PIOC_SCIFSR (*(WoReg*)0x400E1280U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */
+#define REG_PIOC_DIFSR  (*(WoReg*)0x400E1284U) /**< \brief (PIOC) Debouncing Input Filter Select Register */
+#define REG_PIOC_IFDGSR (*(RoReg*)0x400E1288U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOC_SCDR   (*(RwReg*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
+#define REG_PIOC_OWER   (*(WoReg*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
+#define REG_PIOC_OWDR   (*(WoReg*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
+#define REG_PIOC_OWSR   (*(RoReg*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
+#define REG_PIOC_AIMER  (*(WoReg*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
+#define REG_PIOC_AIMDR  (*(WoReg*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
+#define REG_PIOC_AIMMR  (*(RoReg*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
+#define REG_PIOC_ESR    (*(WoReg*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
+#define REG_PIOC_LSR    (*(WoReg*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */
+#define REG_PIOC_ELSR   (*(RoReg*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
+#define REG_PIOC_FELLSR (*(WoReg*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
+#define REG_PIOC_REHLSR (*(WoReg*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
+#define REG_PIOC_FRLHSR (*(RoReg*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
+#define REG_PIOC_LOCKSR (*(RoReg*)0x400E12E0U) /**< \brief (PIOC) Lock Status */
+#define REG_PIOC_WPMR   (*(RwReg*)0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
+#define REG_PIOC_WPSR   (*(RoReg*)0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_PIOC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_piod.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_piod.h
new file mode 100644
index 000000000..e58a65d9e
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_piod.h
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PIOD_INSTANCE_
+#define _SAM3XA_PIOD_INSTANCE_
+
+/* ========== Register definition for PIOD peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PIOD_PER             (0x400E1400U) /**< \brief (PIOD) PIO Enable Register */
+#define REG_PIOD_PDR             (0x400E1404U) /**< \brief (PIOD) PIO Disable Register */
+#define REG_PIOD_PSR             (0x400E1408U) /**< \brief (PIOD) PIO Status Register */
+#define REG_PIOD_OER             (0x400E1410U) /**< \brief (PIOD) Output Enable Register */
+#define REG_PIOD_ODR             (0x400E1414U) /**< \brief (PIOD) Output Disable Register */
+#define REG_PIOD_OSR             (0x400E1418U) /**< \brief (PIOD) Output Status Register */
+#define REG_PIOD_IFER            (0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */
+#define REG_PIOD_IFDR            (0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */
+#define REG_PIOD_IFSR            (0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */
+#define REG_PIOD_SODR            (0x400E1430U) /**< \brief (PIOD) Set Output Data Register */
+#define REG_PIOD_CODR            (0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */
+#define REG_PIOD_ODSR            (0x400E1438U) /**< \brief (PIOD) Output Data Status Register */
+#define REG_PIOD_PDSR            (0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */
+#define REG_PIOD_IER             (0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */
+#define REG_PIOD_IDR             (0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */
+#define REG_PIOD_IMR             (0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */
+#define REG_PIOD_ISR             (0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */
+#define REG_PIOD_MDER            (0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */
+#define REG_PIOD_MDDR            (0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */
+#define REG_PIOD_MDSR            (0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */
+#define REG_PIOD_PUDR            (0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */
+#define REG_PIOD_PUER            (0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */
+#define REG_PIOD_PUSR            (0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */
+#define REG_PIOD_ABSR            (0x400E1470U) /**< \brief (PIOD) Peripheral AB Select Register */
+#define REG_PIOD_SCIFSR          (0x400E1480U) /**< \brief (PIOD) System Clock Glitch Input Filter Select Register */
+#define REG_PIOD_DIFSR           (0x400E1484U) /**< \brief (PIOD) Debouncing Input Filter Select Register */
+#define REG_PIOD_IFDGSR          (0x400E1488U) /**< \brief (PIOD) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOD_SCDR            (0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */
+#define REG_PIOD_OWER            (0x400E14A0U) /**< \brief (PIOD) Output Write Enable */
+#define REG_PIOD_OWDR            (0x400E14A4U) /**< \brief (PIOD) Output Write Disable */
+#define REG_PIOD_OWSR            (0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */
+#define REG_PIOD_AIMER           (0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */
+#define REG_PIOD_AIMDR           (0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */
+#define REG_PIOD_AIMMR           (0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */
+#define REG_PIOD_ESR             (0x400E14C0U) /**< \brief (PIOD) Edge Select Register */
+#define REG_PIOD_LSR             (0x400E14C4U) /**< \brief (PIOD) Level Select Register */
+#define REG_PIOD_ELSR            (0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */
+#define REG_PIOD_FELLSR          (0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */
+#define REG_PIOD_REHLSR          (0x400E14D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */
+#define REG_PIOD_FRLHSR          (0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */
+#define REG_PIOD_LOCKSR          (0x400E14E0U) /**< \brief (PIOD) Lock Status */
+#define REG_PIOD_WPMR            (0x400E14E4U) /**< \brief (PIOD) Write Protect Mode Register */
+#define REG_PIOD_WPSR            (0x400E14E8U) /**< \brief (PIOD) Write Protect Status Register */
+#else
+#define REG_PIOD_PER    (*(WoReg*)0x400E1400U) /**< \brief (PIOD) PIO Enable Register */
+#define REG_PIOD_PDR    (*(WoReg*)0x400E1404U) /**< \brief (PIOD) PIO Disable Register */
+#define REG_PIOD_PSR    (*(RoReg*)0x400E1408U) /**< \brief (PIOD) PIO Status Register */
+#define REG_PIOD_OER    (*(WoReg*)0x400E1410U) /**< \brief (PIOD) Output Enable Register */
+#define REG_PIOD_ODR    (*(WoReg*)0x400E1414U) /**< \brief (PIOD) Output Disable Register */
+#define REG_PIOD_OSR    (*(RoReg*)0x400E1418U) /**< \brief (PIOD) Output Status Register */
+#define REG_PIOD_IFER   (*(WoReg*)0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */
+#define REG_PIOD_IFDR   (*(WoReg*)0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */
+#define REG_PIOD_IFSR   (*(RoReg*)0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */
+#define REG_PIOD_SODR   (*(WoReg*)0x400E1430U) /**< \brief (PIOD) Set Output Data Register */
+#define REG_PIOD_CODR   (*(WoReg*)0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */
+#define REG_PIOD_ODSR   (*(RwReg*)0x400E1438U) /**< \brief (PIOD) Output Data Status Register */
+#define REG_PIOD_PDSR   (*(RoReg*)0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */
+#define REG_PIOD_IER    (*(WoReg*)0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */
+#define REG_PIOD_IDR    (*(WoReg*)0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */
+#define REG_PIOD_IMR    (*(RoReg*)0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */
+#define REG_PIOD_ISR    (*(RoReg*)0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */
+#define REG_PIOD_MDER   (*(WoReg*)0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */
+#define REG_PIOD_MDDR   (*(WoReg*)0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */
+#define REG_PIOD_MDSR   (*(RoReg*)0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */
+#define REG_PIOD_PUDR   (*(WoReg*)0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */
+#define REG_PIOD_PUER   (*(WoReg*)0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */
+#define REG_PIOD_PUSR   (*(RoReg*)0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */
+#define REG_PIOD_ABSR   (*(RwReg*)0x400E1470U) /**< \brief (PIOD) Peripheral AB Select Register */
+#define REG_PIOD_SCIFSR (*(WoReg*)0x400E1480U) /**< \brief (PIOD) System Clock Glitch Input Filter Select Register */
+#define REG_PIOD_DIFSR  (*(WoReg*)0x400E1484U) /**< \brief (PIOD) Debouncing Input Filter Select Register */
+#define REG_PIOD_IFDGSR (*(RoReg*)0x400E1488U) /**< \brief (PIOD) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOD_SCDR   (*(RwReg*)0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */
+#define REG_PIOD_OWER   (*(WoReg*)0x400E14A0U) /**< \brief (PIOD) Output Write Enable */
+#define REG_PIOD_OWDR   (*(WoReg*)0x400E14A4U) /**< \brief (PIOD) Output Write Disable */
+#define REG_PIOD_OWSR   (*(RoReg*)0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */
+#define REG_PIOD_AIMER  (*(WoReg*)0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */
+#define REG_PIOD_AIMDR  (*(WoReg*)0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */
+#define REG_PIOD_AIMMR  (*(RoReg*)0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */
+#define REG_PIOD_ESR    (*(WoReg*)0x400E14C0U) /**< \brief (PIOD) Edge Select Register */
+#define REG_PIOD_LSR    (*(WoReg*)0x400E14C4U) /**< \brief (PIOD) Level Select Register */
+#define REG_PIOD_ELSR   (*(RoReg*)0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */
+#define REG_PIOD_FELLSR (*(WoReg*)0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */
+#define REG_PIOD_REHLSR (*(WoReg*)0x400E14D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */
+#define REG_PIOD_FRLHSR (*(RoReg*)0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */
+#define REG_PIOD_LOCKSR (*(RoReg*)0x400E14E0U) /**< \brief (PIOD) Lock Status */
+#define REG_PIOD_WPMR   (*(RwReg*)0x400E14E4U) /**< \brief (PIOD) Write Protect Mode Register */
+#define REG_PIOD_WPSR   (*(RoReg*)0x400E14E8U) /**< \brief (PIOD) Write Protect Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_PIOD_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_pioe.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_pioe.h
new file mode 100644
index 000000000..f4c6f0dac
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_pioe.h
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PIOE_INSTANCE_
+#define _SAM3XA_PIOE_INSTANCE_
+
+/* ========== Register definition for PIOE peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PIOE_PER             (0x400E1600U) /**< \brief (PIOE) PIO Enable Register */
+#define REG_PIOE_PDR             (0x400E1604U) /**< \brief (PIOE) PIO Disable Register */
+#define REG_PIOE_PSR             (0x400E1608U) /**< \brief (PIOE) PIO Status Register */
+#define REG_PIOE_OER             (0x400E1610U) /**< \brief (PIOE) Output Enable Register */
+#define REG_PIOE_ODR             (0x400E1614U) /**< \brief (PIOE) Output Disable Register */
+#define REG_PIOE_OSR             (0x400E1618U) /**< \brief (PIOE) Output Status Register */
+#define REG_PIOE_IFER            (0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */
+#define REG_PIOE_IFDR            (0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */
+#define REG_PIOE_IFSR            (0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */
+#define REG_PIOE_SODR            (0x400E1630U) /**< \brief (PIOE) Set Output Data Register */
+#define REG_PIOE_CODR            (0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */
+#define REG_PIOE_ODSR            (0x400E1638U) /**< \brief (PIOE) Output Data Status Register */
+#define REG_PIOE_PDSR            (0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */
+#define REG_PIOE_IER             (0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */
+#define REG_PIOE_IDR             (0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */
+#define REG_PIOE_IMR             (0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */
+#define REG_PIOE_ISR             (0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */
+#define REG_PIOE_MDER            (0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */
+#define REG_PIOE_MDDR            (0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */
+#define REG_PIOE_MDSR            (0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */
+#define REG_PIOE_PUDR            (0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */
+#define REG_PIOE_PUER            (0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */
+#define REG_PIOE_PUSR            (0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */
+#define REG_PIOE_ABSR            (0x400E1670U) /**< \brief (PIOE) Peripheral AB Select Register */
+#define REG_PIOE_SCIFSR          (0x400E1680U) /**< \brief (PIOE) System Clock Glitch Input Filter Select Register */
+#define REG_PIOE_DIFSR           (0x400E1684U) /**< \brief (PIOE) Debouncing Input Filter Select Register */
+#define REG_PIOE_IFDGSR          (0x400E1688U) /**< \brief (PIOE) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOE_SCDR            (0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */
+#define REG_PIOE_OWER            (0x400E16A0U) /**< \brief (PIOE) Output Write Enable */
+#define REG_PIOE_OWDR            (0x400E16A4U) /**< \brief (PIOE) Output Write Disable */
+#define REG_PIOE_OWSR            (0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */
+#define REG_PIOE_AIMER           (0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */
+#define REG_PIOE_AIMDR           (0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disables Register */
+#define REG_PIOE_AIMMR           (0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */
+#define REG_PIOE_ESR             (0x400E16C0U) /**< \brief (PIOE) Edge Select Register */
+#define REG_PIOE_LSR             (0x400E16C4U) /**< \brief (PIOE) Level Select Register */
+#define REG_PIOE_ELSR            (0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */
+#define REG_PIOE_FELLSR          (0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low Level Select Register */
+#define REG_PIOE_REHLSR          (0x400E16D4U) /**< \brief (PIOE) Rising Edge/ High Level Select Register */
+#define REG_PIOE_FRLHSR          (0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */
+#define REG_PIOE_LOCKSR          (0x400E16E0U) /**< \brief (PIOE) Lock Status */
+#define REG_PIOE_WPMR            (0x400E16E4U) /**< \brief (PIOE) Write Protect Mode Register */
+#define REG_PIOE_WPSR            (0x400E16E8U) /**< \brief (PIOE) Write Protect Status Register */
+#else
+#define REG_PIOE_PER    (*(WoReg*)0x400E1600U) /**< \brief (PIOE) PIO Enable Register */
+#define REG_PIOE_PDR    (*(WoReg*)0x400E1604U) /**< \brief (PIOE) PIO Disable Register */
+#define REG_PIOE_PSR    (*(RoReg*)0x400E1608U) /**< \brief (PIOE) PIO Status Register */
+#define REG_PIOE_OER    (*(WoReg*)0x400E1610U) /**< \brief (PIOE) Output Enable Register */
+#define REG_PIOE_ODR    (*(WoReg*)0x400E1614U) /**< \brief (PIOE) Output Disable Register */
+#define REG_PIOE_OSR    (*(RoReg*)0x400E1618U) /**< \brief (PIOE) Output Status Register */
+#define REG_PIOE_IFER   (*(WoReg*)0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */
+#define REG_PIOE_IFDR   (*(WoReg*)0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */
+#define REG_PIOE_IFSR   (*(RoReg*)0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */
+#define REG_PIOE_SODR   (*(WoReg*)0x400E1630U) /**< \brief (PIOE) Set Output Data Register */
+#define REG_PIOE_CODR   (*(WoReg*)0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */
+#define REG_PIOE_ODSR   (*(RwReg*)0x400E1638U) /**< \brief (PIOE) Output Data Status Register */
+#define REG_PIOE_PDSR   (*(RoReg*)0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */
+#define REG_PIOE_IER    (*(WoReg*)0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */
+#define REG_PIOE_IDR    (*(WoReg*)0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */
+#define REG_PIOE_IMR    (*(RoReg*)0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */
+#define REG_PIOE_ISR    (*(RoReg*)0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */
+#define REG_PIOE_MDER   (*(WoReg*)0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */
+#define REG_PIOE_MDDR   (*(WoReg*)0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */
+#define REG_PIOE_MDSR   (*(RoReg*)0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */
+#define REG_PIOE_PUDR   (*(WoReg*)0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */
+#define REG_PIOE_PUER   (*(WoReg*)0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */
+#define REG_PIOE_PUSR   (*(RoReg*)0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */
+#define REG_PIOE_ABSR   (*(RwReg*)0x400E1670U) /**< \brief (PIOE) Peripheral AB Select Register */
+#define REG_PIOE_SCIFSR (*(WoReg*)0x400E1680U) /**< \brief (PIOE) System Clock Glitch Input Filter Select Register */
+#define REG_PIOE_DIFSR  (*(WoReg*)0x400E1684U) /**< \brief (PIOE) Debouncing Input Filter Select Register */
+#define REG_PIOE_IFDGSR (*(RoReg*)0x400E1688U) /**< \brief (PIOE) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOE_SCDR   (*(RwReg*)0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */
+#define REG_PIOE_OWER   (*(WoReg*)0x400E16A0U) /**< \brief (PIOE) Output Write Enable */
+#define REG_PIOE_OWDR   (*(WoReg*)0x400E16A4U) /**< \brief (PIOE) Output Write Disable */
+#define REG_PIOE_OWSR   (*(RoReg*)0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */
+#define REG_PIOE_AIMER  (*(WoReg*)0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */
+#define REG_PIOE_AIMDR  (*(WoReg*)0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disables Register */
+#define REG_PIOE_AIMMR  (*(RoReg*)0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */
+#define REG_PIOE_ESR    (*(WoReg*)0x400E16C0U) /**< \brief (PIOE) Edge Select Register */
+#define REG_PIOE_LSR    (*(WoReg*)0x400E16C4U) /**< \brief (PIOE) Level Select Register */
+#define REG_PIOE_ELSR   (*(RoReg*)0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */
+#define REG_PIOE_FELLSR (*(WoReg*)0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low Level Select Register */
+#define REG_PIOE_REHLSR (*(WoReg*)0x400E16D4U) /**< \brief (PIOE) Rising Edge/ High Level Select Register */
+#define REG_PIOE_FRLHSR (*(RoReg*)0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */
+#define REG_PIOE_LOCKSR (*(RoReg*)0x400E16E0U) /**< \brief (PIOE) Lock Status */
+#define REG_PIOE_WPMR   (*(RwReg*)0x400E16E4U) /**< \brief (PIOE) Write Protect Mode Register */
+#define REG_PIOE_WPSR   (*(RoReg*)0x400E16E8U) /**< \brief (PIOE) Write Protect Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_PIOE_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_piof.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_piof.h
new file mode 100644
index 000000000..7d6846a67
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_piof.h
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PIOF_INSTANCE_
+#define _SAM3XA_PIOF_INSTANCE_
+
+/* ========== Register definition for PIOF peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PIOF_PER             (0x400E1800U) /**< \brief (PIOF) PIO Enable Register */
+#define REG_PIOF_PDR             (0x400E1804U) /**< \brief (PIOF) PIO Disable Register */
+#define REG_PIOF_PSR             (0x400E1808U) /**< \brief (PIOF) PIO Status Register */
+#define REG_PIOF_OER             (0x400E1810U) /**< \brief (PIOF) Output Enable Register */
+#define REG_PIOF_ODR             (0x400E1814U) /**< \brief (PIOF) Output Disable Register */
+#define REG_PIOF_OSR             (0x400E1818U) /**< \brief (PIOF) Output Status Register */
+#define REG_PIOF_IFER            (0x400E1820U) /**< \brief (PIOF) Glitch Input Filter Enable Register */
+#define REG_PIOF_IFDR            (0x400E1824U) /**< \brief (PIOF) Glitch Input Filter Disable Register */
+#define REG_PIOF_IFSR            (0x400E1828U) /**< \brief (PIOF) Glitch Input Filter Status Register */
+#define REG_PIOF_SODR            (0x400E1830U) /**< \brief (PIOF) Set Output Data Register */
+#define REG_PIOF_CODR            (0x400E1834U) /**< \brief (PIOF) Clear Output Data Register */
+#define REG_PIOF_ODSR            (0x400E1838U) /**< \brief (PIOF) Output Data Status Register */
+#define REG_PIOF_PDSR            (0x400E183CU) /**< \brief (PIOF) Pin Data Status Register */
+#define REG_PIOF_IER             (0x400E1840U) /**< \brief (PIOF) Interrupt Enable Register */
+#define REG_PIOF_IDR             (0x400E1844U) /**< \brief (PIOF) Interrupt Disable Register */
+#define REG_PIOF_IMR             (0x400E1848U) /**< \brief (PIOF) Interrupt Mask Register */
+#define REG_PIOF_ISR             (0x400E184CU) /**< \brief (PIOF) Interrupt Status Register */
+#define REG_PIOF_MDER            (0x400E1850U) /**< \brief (PIOF) Multi-driver Enable Register */
+#define REG_PIOF_MDDR            (0x400E1854U) /**< \brief (PIOF) Multi-driver Disable Register */
+#define REG_PIOF_MDSR            (0x400E1858U) /**< \brief (PIOF) Multi-driver Status Register */
+#define REG_PIOF_PUDR            (0x400E1860U) /**< \brief (PIOF) Pull-up Disable Register */
+#define REG_PIOF_PUER            (0x400E1864U) /**< \brief (PIOF) Pull-up Enable Register */
+#define REG_PIOF_PUSR            (0x400E1868U) /**< \brief (PIOF) Pad Pull-up Status Register */
+#define REG_PIOF_ABSR            (0x400E1870U) /**< \brief (PIOF) Peripheral AB Select Register */
+#define REG_PIOF_SCIFSR          (0x400E1880U) /**< \brief (PIOF) System Clock Glitch Input Filter Select Register */
+#define REG_PIOF_DIFSR           (0x400E1884U) /**< \brief (PIOF) Debouncing Input Filter Select Register */
+#define REG_PIOF_IFDGSR          (0x400E1888U) /**< \brief (PIOF) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOF_SCDR            (0x400E188CU) /**< \brief (PIOF) Slow Clock Divider Debouncing Register */
+#define REG_PIOF_OWER            (0x400E18A0U) /**< \brief (PIOF) Output Write Enable */
+#define REG_PIOF_OWDR            (0x400E18A4U) /**< \brief (PIOF) Output Write Disable */
+#define REG_PIOF_OWSR            (0x400E18A8U) /**< \brief (PIOF) Output Write Status Register */
+#define REG_PIOF_AIMER           (0x400E18B0U) /**< \brief (PIOF) Additional Interrupt Modes Enable Register */
+#define REG_PIOF_AIMDR           (0x400E18B4U) /**< \brief (PIOF) Additional Interrupt Modes Disables Register */
+#define REG_PIOF_AIMMR           (0x400E18B8U) /**< \brief (PIOF) Additional Interrupt Modes Mask Register */
+#define REG_PIOF_ESR             (0x400E18C0U) /**< \brief (PIOF) Edge Select Register */
+#define REG_PIOF_LSR             (0x400E18C4U) /**< \brief (PIOF) Level Select Register */
+#define REG_PIOF_ELSR            (0x400E18C8U) /**< \brief (PIOF) Edge/Level Status Register */
+#define REG_PIOF_FELLSR          (0x400E18D0U) /**< \brief (PIOF) Falling Edge/Low Level Select Register */
+#define REG_PIOF_REHLSR          (0x400E18D4U) /**< \brief (PIOF) Rising Edge/ High Level Select Register */
+#define REG_PIOF_FRLHSR          (0x400E18D8U) /**< \brief (PIOF) Fall/Rise - Low/High Status Register */
+#define REG_PIOF_LOCKSR          (0x400E18E0U) /**< \brief (PIOF) Lock Status */
+#define REG_PIOF_WPMR            (0x400E18E4U) /**< \brief (PIOF) Write Protect Mode Register */
+#define REG_PIOF_WPSR            (0x400E18E8U) /**< \brief (PIOF) Write Protect Status Register */
+#else
+#define REG_PIOF_PER    (*(WoReg*)0x400E1800U) /**< \brief (PIOF) PIO Enable Register */
+#define REG_PIOF_PDR    (*(WoReg*)0x400E1804U) /**< \brief (PIOF) PIO Disable Register */
+#define REG_PIOF_PSR    (*(RoReg*)0x400E1808U) /**< \brief (PIOF) PIO Status Register */
+#define REG_PIOF_OER    (*(WoReg*)0x400E1810U) /**< \brief (PIOF) Output Enable Register */
+#define REG_PIOF_ODR    (*(WoReg*)0x400E1814U) /**< \brief (PIOF) Output Disable Register */
+#define REG_PIOF_OSR    (*(RoReg*)0x400E1818U) /**< \brief (PIOF) Output Status Register */
+#define REG_PIOF_IFER   (*(WoReg*)0x400E1820U) /**< \brief (PIOF) Glitch Input Filter Enable Register */
+#define REG_PIOF_IFDR   (*(WoReg*)0x400E1824U) /**< \brief (PIOF) Glitch Input Filter Disable Register */
+#define REG_PIOF_IFSR   (*(RoReg*)0x400E1828U) /**< \brief (PIOF) Glitch Input Filter Status Register */
+#define REG_PIOF_SODR   (*(WoReg*)0x400E1830U) /**< \brief (PIOF) Set Output Data Register */
+#define REG_PIOF_CODR   (*(WoReg*)0x400E1834U) /**< \brief (PIOF) Clear Output Data Register */
+#define REG_PIOF_ODSR   (*(RwReg*)0x400E1838U) /**< \brief (PIOF) Output Data Status Register */
+#define REG_PIOF_PDSR   (*(RoReg*)0x400E183CU) /**< \brief (PIOF) Pin Data Status Register */
+#define REG_PIOF_IER    (*(WoReg*)0x400E1840U) /**< \brief (PIOF) Interrupt Enable Register */
+#define REG_PIOF_IDR    (*(WoReg*)0x400E1844U) /**< \brief (PIOF) Interrupt Disable Register */
+#define REG_PIOF_IMR    (*(RoReg*)0x400E1848U) /**< \brief (PIOF) Interrupt Mask Register */
+#define REG_PIOF_ISR    (*(RoReg*)0x400E184CU) /**< \brief (PIOF) Interrupt Status Register */
+#define REG_PIOF_MDER   (*(WoReg*)0x400E1850U) /**< \brief (PIOF) Multi-driver Enable Register */
+#define REG_PIOF_MDDR   (*(WoReg*)0x400E1854U) /**< \brief (PIOF) Multi-driver Disable Register */
+#define REG_PIOF_MDSR   (*(RoReg*)0x400E1858U) /**< \brief (PIOF) Multi-driver Status Register */
+#define REG_PIOF_PUDR   (*(WoReg*)0x400E1860U) /**< \brief (PIOF) Pull-up Disable Register */
+#define REG_PIOF_PUER   (*(WoReg*)0x400E1864U) /**< \brief (PIOF) Pull-up Enable Register */
+#define REG_PIOF_PUSR   (*(RoReg*)0x400E1868U) /**< \brief (PIOF) Pad Pull-up Status Register */
+#define REG_PIOF_ABSR   (*(RwReg*)0x400E1870U) /**< \brief (PIOF) Peripheral AB Select Register */
+#define REG_PIOF_SCIFSR (*(WoReg*)0x400E1880U) /**< \brief (PIOF) System Clock Glitch Input Filter Select Register */
+#define REG_PIOF_DIFSR  (*(WoReg*)0x400E1884U) /**< \brief (PIOF) Debouncing Input Filter Select Register */
+#define REG_PIOF_IFDGSR (*(RoReg*)0x400E1888U) /**< \brief (PIOF) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOF_SCDR   (*(RwReg*)0x400E188CU) /**< \brief (PIOF) Slow Clock Divider Debouncing Register */
+#define REG_PIOF_OWER   (*(WoReg*)0x400E18A0U) /**< \brief (PIOF) Output Write Enable */
+#define REG_PIOF_OWDR   (*(WoReg*)0x400E18A4U) /**< \brief (PIOF) Output Write Disable */
+#define REG_PIOF_OWSR   (*(RoReg*)0x400E18A8U) /**< \brief (PIOF) Output Write Status Register */
+#define REG_PIOF_AIMER  (*(WoReg*)0x400E18B0U) /**< \brief (PIOF) Additional Interrupt Modes Enable Register */
+#define REG_PIOF_AIMDR  (*(WoReg*)0x400E18B4U) /**< \brief (PIOF) Additional Interrupt Modes Disables Register */
+#define REG_PIOF_AIMMR  (*(RoReg*)0x400E18B8U) /**< \brief (PIOF) Additional Interrupt Modes Mask Register */
+#define REG_PIOF_ESR    (*(WoReg*)0x400E18C0U) /**< \brief (PIOF) Edge Select Register */
+#define REG_PIOF_LSR    (*(WoReg*)0x400E18C4U) /**< \brief (PIOF) Level Select Register */
+#define REG_PIOF_ELSR   (*(RoReg*)0x400E18C8U) /**< \brief (PIOF) Edge/Level Status Register */
+#define REG_PIOF_FELLSR (*(WoReg*)0x400E18D0U) /**< \brief (PIOF) Falling Edge/Low Level Select Register */
+#define REG_PIOF_REHLSR (*(WoReg*)0x400E18D4U) /**< \brief (PIOF) Rising Edge/ High Level Select Register */
+#define REG_PIOF_FRLHSR (*(RoReg*)0x400E18D8U) /**< \brief (PIOF) Fall/Rise - Low/High Status Register */
+#define REG_PIOF_LOCKSR (*(RoReg*)0x400E18E0U) /**< \brief (PIOF) Lock Status */
+#define REG_PIOF_WPMR   (*(RwReg*)0x400E18E4U) /**< \brief (PIOF) Write Protect Mode Register */
+#define REG_PIOF_WPSR   (*(RoReg*)0x400E18E8U) /**< \brief (PIOF) Write Protect Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_PIOF_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_pmc.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_pmc.h
new file mode 100644
index 000000000..1c867c775
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_pmc.h
@@ -0,0 +1,90 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PMC_INSTANCE_
+#define _SAM3XA_PMC_INSTANCE_
+
+/* ========== Register definition for PMC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PMC_SCER            (0x400E0600U) /**< \brief (PMC) System Clock Enable Register */
+#define REG_PMC_SCDR            (0x400E0604U) /**< \brief (PMC) System Clock Disable Register */
+#define REG_PMC_SCSR            (0x400E0608U) /**< \brief (PMC) System Clock Status Register */
+#define REG_PMC_PCER0           (0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
+#define REG_PMC_PCDR0           (0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
+#define REG_PMC_PCSR0           (0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
+#define REG_CKGR_UCKR           (0x400E061CU) /**< \brief (PMC) UTMI Clock Register */
+#define REG_CKGR_MOR            (0x400E0620U) /**< \brief (PMC) Main Oscillator Register */
+#define REG_CKGR_MCFR           (0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */
+#define REG_CKGR_PLLAR          (0x400E0628U) /**< \brief (PMC) PLLA Register */
+#define REG_PMC_MCKR            (0x400E0630U) /**< \brief (PMC) Master Clock Register */
+#define REG_PMC_USB             (0x400E0638U) /**< \brief (PMC) USB Clock Register */
+#define REG_PMC_PCK             (0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */
+#define REG_PMC_IER             (0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */
+#define REG_PMC_IDR             (0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */
+#define REG_PMC_SR              (0x400E0668U) /**< \brief (PMC) Status Register */
+#define REG_PMC_IMR             (0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */
+#define REG_PMC_FSMR            (0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */
+#define REG_PMC_FSPR            (0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */
+#define REG_PMC_FOCR            (0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */
+#define REG_PMC_WPMR            (0x400E06E4U) /**< \brief (PMC) Write Protect Mode Register */
+#define REG_PMC_WPSR            (0x400E06E8U) /**< \brief (PMC) Write Protect Status Register */
+#define REG_PMC_PCER1           (0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
+#define REG_PMC_PCDR1           (0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
+#define REG_PMC_PCSR1           (0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
+#define REG_PMC_PCR             (0x400E070CU) /**< \brief (PMC) Peripheral Control Register */
+#else
+#define REG_PMC_SCER   (*(WoReg*)0x400E0600U) /**< \brief (PMC) System Clock Enable Register */
+#define REG_PMC_SCDR   (*(WoReg*)0x400E0604U) /**< \brief (PMC) System Clock Disable Register */
+#define REG_PMC_SCSR   (*(RoReg*)0x400E0608U) /**< \brief (PMC) System Clock Status Register */
+#define REG_PMC_PCER0  (*(WoReg*)0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
+#define REG_PMC_PCDR0  (*(WoReg*)0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
+#define REG_PMC_PCSR0  (*(RoReg*)0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
+#define REG_CKGR_UCKR  (*(RwReg*)0x400E061CU) /**< \brief (PMC) UTMI Clock Register */
+#define REG_CKGR_MOR   (*(RwReg*)0x400E0620U) /**< \brief (PMC) Main Oscillator Register */
+#define REG_CKGR_MCFR  (*(RoReg*)0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */
+#define REG_CKGR_PLLAR (*(RwReg*)0x400E0628U) /**< \brief (PMC) PLLA Register */
+#define REG_PMC_MCKR   (*(RwReg*)0x400E0630U) /**< \brief (PMC) Master Clock Register */
+#define REG_PMC_USB    (*(RwReg*)0x400E0638U) /**< \brief (PMC) USB Clock Register */
+#define REG_PMC_PCK    (*(RwReg*)0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */
+#define REG_PMC_IER    (*(WoReg*)0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */
+#define REG_PMC_IDR    (*(WoReg*)0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */
+#define REG_PMC_SR     (*(RoReg*)0x400E0668U) /**< \brief (PMC) Status Register */
+#define REG_PMC_IMR    (*(RoReg*)0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */
+#define REG_PMC_FSMR   (*(RwReg*)0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */
+#define REG_PMC_FSPR   (*(RwReg*)0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */
+#define REG_PMC_FOCR   (*(WoReg*)0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */
+#define REG_PMC_WPMR   (*(RwReg*)0x400E06E4U) /**< \brief (PMC) Write Protect Mode Register */
+#define REG_PMC_WPSR   (*(RoReg*)0x400E06E8U) /**< \brief (PMC) Write Protect Status Register */
+#define REG_PMC_PCER1  (*(WoReg*)0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
+#define REG_PMC_PCDR1  (*(WoReg*)0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
+#define REG_PMC_PCSR1  (*(RoReg*)0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
+#define REG_PMC_PCR    (*(RwReg*)0x400E070CU) /**< \brief (PMC) Peripheral Control Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_PMC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_pwm.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_pwm.h
new file mode 100644
index 000000000..79859cf8a
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_pwm.h
@@ -0,0 +1,314 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PWM_INSTANCE_
+#define _SAM3XA_PWM_INSTANCE_
+
+/* ========== Register definition for PWM peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_PWM_CLK               (0x40094000U) /**< \brief (PWM) PWM Clock Register */
+#define REG_PWM_ENA               (0x40094004U) /**< \brief (PWM) PWM Enable Register */
+#define REG_PWM_DIS               (0x40094008U) /**< \brief (PWM) PWM Disable Register */
+#define REG_PWM_SR                (0x4009400CU) /**< \brief (PWM) PWM Status Register */
+#define REG_PWM_IER1              (0x40094010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
+#define REG_PWM_IDR1              (0x40094014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
+#define REG_PWM_IMR1              (0x40094018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
+#define REG_PWM_ISR1              (0x4009401CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
+#define REG_PWM_SCM               (0x40094020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
+#define REG_PWM_SCUC              (0x40094028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
+#define REG_PWM_SCUP              (0x4009402CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
+#define REG_PWM_SCUPUPD           (0x40094030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
+#define REG_PWM_IER2              (0x40094034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
+#define REG_PWM_IDR2              (0x40094038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
+#define REG_PWM_IMR2              (0x4009403CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
+#define REG_PWM_ISR2              (0x40094040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
+#define REG_PWM_OOV               (0x40094044U) /**< \brief (PWM) PWM Output Override Value Register */
+#define REG_PWM_OS                (0x40094048U) /**< \brief (PWM) PWM Output Selection Register */
+#define REG_PWM_OSS               (0x4009404CU) /**< \brief (PWM) PWM Output Selection Set Register */
+#define REG_PWM_OSC               (0x40094050U) /**< \brief (PWM) PWM Output Selection Clear Register */
+#define REG_PWM_OSSUPD            (0x40094054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
+#define REG_PWM_OSCUPD            (0x40094058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
+#define REG_PWM_FMR               (0x4009405CU) /**< \brief (PWM) PWM Fault Mode Register */
+#define REG_PWM_FSR               (0x40094060U) /**< \brief (PWM) PWM Fault Status Register */
+#define REG_PWM_FCR               (0x40094064U) /**< \brief (PWM) PWM Fault Clear Register */
+#define REG_PWM_FPV               (0x40094068U) /**< \brief (PWM) PWM Fault Protection Value Register */
+#define REG_PWM_FPE1              (0x4009406CU) /**< \brief (PWM) PWM Fault Protection Enable Register 1 */
+#define REG_PWM_FPE2              (0x40094070U) /**< \brief (PWM) PWM Fault Protection Enable Register 2 */
+#define REG_PWM_ELMR              (0x4009407CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
+#define REG_PWM_SMMR              (0x400940B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */
+#define REG_PWM_WPCR              (0x400940E4U) /**< \brief (PWM) PWM Write Protect Control Register */
+#define REG_PWM_WPSR              (0x400940E8U) /**< \brief (PWM) PWM Write Protect Status Register */
+#define REG_PWM_RPR               (0x40094100U) /**< \brief (PWM) Receive Pointer Register */
+#define REG_PWM_RCR               (0x40094104U) /**< \brief (PWM) Receive Counter Register */
+#define REG_PWM_TPR               (0x40094108U) /**< \brief (PWM) Transmit Pointer Register */
+#define REG_PWM_TCR               (0x4009410CU) /**< \brief (PWM) Transmit Counter Register */
+#define REG_PWM_RNPR              (0x40094110U) /**< \brief (PWM) Receive Next Pointer Register */
+#define REG_PWM_RNCR              (0x40094114U) /**< \brief (PWM) Receive Next Counter Register */
+#define REG_PWM_TNPR              (0x40094118U) /**< \brief (PWM) Transmit Next Pointer Register */
+#define REG_PWM_TNCR              (0x4009411CU) /**< \brief (PWM) Transmit Next Counter Register */
+#define REG_PWM_PTCR              (0x40094120U) /**< \brief (PWM) Transfer Control Register */
+#define REG_PWM_PTSR              (0x40094124U) /**< \brief (PWM) Transfer Status Register */
+#define REG_PWM_CMPV0             (0x40094130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
+#define REG_PWM_CMPVUPD0          (0x40094134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
+#define REG_PWM_CMPM0             (0x40094138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
+#define REG_PWM_CMPMUPD0          (0x4009413CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
+#define REG_PWM_CMPV1             (0x40094140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
+#define REG_PWM_CMPVUPD1          (0x40094144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
+#define REG_PWM_CMPM1             (0x40094148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
+#define REG_PWM_CMPMUPD1          (0x4009414CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
+#define REG_PWM_CMPV2             (0x40094150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
+#define REG_PWM_CMPVUPD2          (0x40094154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
+#define REG_PWM_CMPM2             (0x40094158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
+#define REG_PWM_CMPMUPD2          (0x4009415CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
+#define REG_PWM_CMPV3             (0x40094160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
+#define REG_PWM_CMPVUPD3          (0x40094164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
+#define REG_PWM_CMPM3             (0x40094168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
+#define REG_PWM_CMPMUPD3          (0x4009416CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
+#define REG_PWM_CMPV4             (0x40094170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
+#define REG_PWM_CMPVUPD4          (0x40094174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
+#define REG_PWM_CMPM4             (0x40094178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
+#define REG_PWM_CMPMUPD4          (0x4009417CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
+#define REG_PWM_CMPV5             (0x40094180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
+#define REG_PWM_CMPVUPD5          (0x40094184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
+#define REG_PWM_CMPM5             (0x40094188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
+#define REG_PWM_CMPMUPD5          (0x4009418CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
+#define REG_PWM_CMPV6             (0x40094190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
+#define REG_PWM_CMPVUPD6          (0x40094194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
+#define REG_PWM_CMPM6             (0x40094198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
+#define REG_PWM_CMPMUPD6          (0x4009419CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
+#define REG_PWM_CMPV7             (0x400941A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
+#define REG_PWM_CMPVUPD7          (0x400941A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
+#define REG_PWM_CMPM7             (0x400941A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
+#define REG_PWM_CMPMUPD7          (0x400941ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
+#define REG_PWM_CMR0              (0x40094200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
+#define REG_PWM_CDTY0             (0x40094204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
+#define REG_PWM_CDTYUPD0          (0x40094208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
+#define REG_PWM_CPRD0             (0x4009420CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
+#define REG_PWM_CPRDUPD0          (0x40094210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
+#define REG_PWM_CCNT0             (0x40094214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
+#define REG_PWM_DT0               (0x40094218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
+#define REG_PWM_DTUPD0            (0x4009421CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
+#define REG_PWM_CMR1              (0x40094220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
+#define REG_PWM_CDTY1             (0x40094224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
+#define REG_PWM_CDTYUPD1          (0x40094228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
+#define REG_PWM_CPRD1             (0x4009422CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
+#define REG_PWM_CPRDUPD1          (0x40094230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
+#define REG_PWM_CCNT1             (0x40094234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
+#define REG_PWM_DT1               (0x40094238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
+#define REG_PWM_DTUPD1            (0x4009423CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
+#define REG_PWM_CMR2              (0x40094240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
+#define REG_PWM_CDTY2             (0x40094244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
+#define REG_PWM_CDTYUPD2          (0x40094248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
+#define REG_PWM_CPRD2             (0x4009424CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
+#define REG_PWM_CPRDUPD2          (0x40094250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
+#define REG_PWM_CCNT2             (0x40094254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
+#define REG_PWM_DT2               (0x40094258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
+#define REG_PWM_DTUPD2            (0x4009425CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
+#define REG_PWM_CMR3              (0x40094260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
+#define REG_PWM_CDTY3             (0x40094264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
+#define REG_PWM_CDTYUPD3          (0x40094268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
+#define REG_PWM_CPRD3             (0x4009426CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
+#define REG_PWM_CPRDUPD3          (0x40094270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
+#define REG_PWM_CCNT3             (0x40094274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
+#define REG_PWM_DT3               (0x40094278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
+#define REG_PWM_DTUPD3            (0x4009427CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
+#define REG_PWM_CMR4              (0x40094280U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 4) */
+#define REG_PWM_CDTY4             (0x40094284U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 4) */
+#define REG_PWM_CDTYUPD4          (0x40094288U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 4) */
+#define REG_PWM_CPRD4             (0x4009428CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 4) */
+#define REG_PWM_CPRDUPD4          (0x40094290U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 4) */
+#define REG_PWM_CCNT4             (0x40094294U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 4) */
+#define REG_PWM_DT4               (0x40094298U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 4) */
+#define REG_PWM_DTUPD4            (0x4009429CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 4) */
+#define REG_PWM_CMR5              (0x400942A0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 5) */
+#define REG_PWM_CDTY5             (0x400942A4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 5) */
+#define REG_PWM_CDTYUPD5          (0x400942A8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 5) */
+#define REG_PWM_CPRD5             (0x400942ACU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 5) */
+#define REG_PWM_CPRDUPD5          (0x400942B0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 5) */
+#define REG_PWM_CCNT5             (0x400942B4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 5) */
+#define REG_PWM_DT5               (0x400942B8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 5) */
+#define REG_PWM_DTUPD5            (0x400942BCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 5) */
+#define REG_PWM_CMR6              (0x400942C0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 6) */
+#define REG_PWM_CDTY6             (0x400942C4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 6) */
+#define REG_PWM_CDTYUPD6          (0x400942C8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 6) */
+#define REG_PWM_CPRD6             (0x400942CCU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 6) */
+#define REG_PWM_CPRDUPD6          (0x400942D0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 6) */
+#define REG_PWM_CCNT6             (0x400942D4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 6) */
+#define REG_PWM_DT6               (0x400942D8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 6) */
+#define REG_PWM_DTUPD6            (0x400942DCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 6) */
+#define REG_PWM_CMR7              (0x400942E0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 7) */
+#define REG_PWM_CDTY7             (0x400942E4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 7) */
+#define REG_PWM_CDTYUPD7          (0x400942E8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 7) */
+#define REG_PWM_CPRD7             (0x400942ECU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 7) */
+#define REG_PWM_CPRDUPD7          (0x400942F0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 7) */
+#define REG_PWM_CCNT7             (0x400942F4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 7) */
+#define REG_PWM_DT7               (0x400942F8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 7) */
+#define REG_PWM_DTUPD7            (0x400942FCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 7) */
+#else
+#define REG_PWM_CLK      (*(RwReg*)0x40094000U) /**< \brief (PWM) PWM Clock Register */
+#define REG_PWM_ENA      (*(WoReg*)0x40094004U) /**< \brief (PWM) PWM Enable Register */
+#define REG_PWM_DIS      (*(WoReg*)0x40094008U) /**< \brief (PWM) PWM Disable Register */
+#define REG_PWM_SR       (*(RoReg*)0x4009400CU) /**< \brief (PWM) PWM Status Register */
+#define REG_PWM_IER1     (*(WoReg*)0x40094010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
+#define REG_PWM_IDR1     (*(WoReg*)0x40094014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
+#define REG_PWM_IMR1     (*(RoReg*)0x40094018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
+#define REG_PWM_ISR1     (*(RoReg*)0x4009401CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
+#define REG_PWM_SCM      (*(RwReg*)0x40094020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
+#define REG_PWM_SCUC     (*(RwReg*)0x40094028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
+#define REG_PWM_SCUP     (*(RwReg*)0x4009402CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
+#define REG_PWM_SCUPUPD  (*(WoReg*)0x40094030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
+#define REG_PWM_IER2     (*(WoReg*)0x40094034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
+#define REG_PWM_IDR2     (*(WoReg*)0x40094038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
+#define REG_PWM_IMR2     (*(RoReg*)0x4009403CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
+#define REG_PWM_ISR2     (*(RoReg*)0x40094040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
+#define REG_PWM_OOV      (*(RwReg*)0x40094044U) /**< \brief (PWM) PWM Output Override Value Register */
+#define REG_PWM_OS       (*(RwReg*)0x40094048U) /**< \brief (PWM) PWM Output Selection Register */
+#define REG_PWM_OSS      (*(WoReg*)0x4009404CU) /**< \brief (PWM) PWM Output Selection Set Register */
+#define REG_PWM_OSC      (*(WoReg*)0x40094050U) /**< \brief (PWM) PWM Output Selection Clear Register */
+#define REG_PWM_OSSUPD   (*(WoReg*)0x40094054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
+#define REG_PWM_OSCUPD   (*(WoReg*)0x40094058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
+#define REG_PWM_FMR      (*(RwReg*)0x4009405CU) /**< \brief (PWM) PWM Fault Mode Register */
+#define REG_PWM_FSR      (*(RoReg*)0x40094060U) /**< \brief (PWM) PWM Fault Status Register */
+#define REG_PWM_FCR      (*(WoReg*)0x40094064U) /**< \brief (PWM) PWM Fault Clear Register */
+#define REG_PWM_FPV      (*(RwReg*)0x40094068U) /**< \brief (PWM) PWM Fault Protection Value Register */
+#define REG_PWM_FPE1     (*(RwReg*)0x4009406CU) /**< \brief (PWM) PWM Fault Protection Enable Register 1 */
+#define REG_PWM_FPE2     (*(RwReg*)0x40094070U) /**< \brief (PWM) PWM Fault Protection Enable Register 2 */
+#define REG_PWM_ELMR     (*(RwReg*)0x4009407CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
+#define REG_PWM_SMMR     (*(RwReg*)0x400940B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */
+#define REG_PWM_WPCR     (*(WoReg*)0x400940E4U) /**< \brief (PWM) PWM Write Protect Control Register */
+#define REG_PWM_WPSR     (*(RoReg*)0x400940E8U) /**< \brief (PWM) PWM Write Protect Status Register */
+#define REG_PWM_RPR      (*(RwReg*)0x40094100U) /**< \brief (PWM) Receive Pointer Register */
+#define REG_PWM_RCR      (*(RwReg*)0x40094104U) /**< \brief (PWM) Receive Counter Register */
+#define REG_PWM_TPR      (*(RwReg*)0x40094108U) /**< \brief (PWM) Transmit Pointer Register */
+#define REG_PWM_TCR      (*(RwReg*)0x4009410CU) /**< \brief (PWM) Transmit Counter Register */
+#define REG_PWM_RNPR     (*(RwReg*)0x40094110U) /**< \brief (PWM) Receive Next Pointer Register */
+#define REG_PWM_RNCR     (*(RwReg*)0x40094114U) /**< \brief (PWM) Receive Next Counter Register */
+#define REG_PWM_TNPR     (*(RwReg*)0x40094118U) /**< \brief (PWM) Transmit Next Pointer Register */
+#define REG_PWM_TNCR     (*(RwReg*)0x4009411CU) /**< \brief (PWM) Transmit Next Counter Register */
+#define REG_PWM_PTCR     (*(WoReg*)0x40094120U) /**< \brief (PWM) Transfer Control Register */
+#define REG_PWM_PTSR     (*(RoReg*)0x40094124U) /**< \brief (PWM) Transfer Status Register */
+#define REG_PWM_CMPV0    (*(RwReg*)0x40094130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
+#define REG_PWM_CMPVUPD0 (*(WoReg*)0x40094134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
+#define REG_PWM_CMPM0    (*(RwReg*)0x40094138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
+#define REG_PWM_CMPMUPD0 (*(WoReg*)0x4009413CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
+#define REG_PWM_CMPV1    (*(RwReg*)0x40094140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
+#define REG_PWM_CMPVUPD1 (*(WoReg*)0x40094144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
+#define REG_PWM_CMPM1    (*(RwReg*)0x40094148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
+#define REG_PWM_CMPMUPD1 (*(WoReg*)0x4009414CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
+#define REG_PWM_CMPV2    (*(RwReg*)0x40094150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
+#define REG_PWM_CMPVUPD2 (*(WoReg*)0x40094154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
+#define REG_PWM_CMPM2    (*(RwReg*)0x40094158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
+#define REG_PWM_CMPMUPD2 (*(WoReg*)0x4009415CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
+#define REG_PWM_CMPV3    (*(RwReg*)0x40094160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
+#define REG_PWM_CMPVUPD3 (*(WoReg*)0x40094164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
+#define REG_PWM_CMPM3    (*(RwReg*)0x40094168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
+#define REG_PWM_CMPMUPD3 (*(WoReg*)0x4009416CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
+#define REG_PWM_CMPV4    (*(RwReg*)0x40094170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
+#define REG_PWM_CMPVUPD4 (*(WoReg*)0x40094174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
+#define REG_PWM_CMPM4    (*(RwReg*)0x40094178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
+#define REG_PWM_CMPMUPD4 (*(WoReg*)0x4009417CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
+#define REG_PWM_CMPV5    (*(RwReg*)0x40094180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
+#define REG_PWM_CMPVUPD5 (*(WoReg*)0x40094184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
+#define REG_PWM_CMPM5    (*(RwReg*)0x40094188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
+#define REG_PWM_CMPMUPD5 (*(WoReg*)0x4009418CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
+#define REG_PWM_CMPV6    (*(RwReg*)0x40094190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
+#define REG_PWM_CMPVUPD6 (*(WoReg*)0x40094194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
+#define REG_PWM_CMPM6    (*(RwReg*)0x40094198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
+#define REG_PWM_CMPMUPD6 (*(WoReg*)0x4009419CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
+#define REG_PWM_CMPV7    (*(RwReg*)0x400941A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
+#define REG_PWM_CMPVUPD7 (*(WoReg*)0x400941A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
+#define REG_PWM_CMPM7    (*(RwReg*)0x400941A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
+#define REG_PWM_CMPMUPD7 (*(WoReg*)0x400941ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
+#define REG_PWM_CMR0     (*(RwReg*)0x40094200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
+#define REG_PWM_CDTY0    (*(RwReg*)0x40094204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
+#define REG_PWM_CDTYUPD0 (*(WoReg*)0x40094208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
+#define REG_PWM_CPRD0    (*(RwReg*)0x4009420CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
+#define REG_PWM_CPRDUPD0 (*(WoReg*)0x40094210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
+#define REG_PWM_CCNT0    (*(RoReg*)0x40094214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
+#define REG_PWM_DT0      (*(RwReg*)0x40094218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
+#define REG_PWM_DTUPD0   (*(WoReg*)0x4009421CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
+#define REG_PWM_CMR1     (*(RwReg*)0x40094220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
+#define REG_PWM_CDTY1    (*(RwReg*)0x40094224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
+#define REG_PWM_CDTYUPD1 (*(WoReg*)0x40094228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
+#define REG_PWM_CPRD1    (*(RwReg*)0x4009422CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
+#define REG_PWM_CPRDUPD1 (*(WoReg*)0x40094230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
+#define REG_PWM_CCNT1    (*(RoReg*)0x40094234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
+#define REG_PWM_DT1      (*(RwReg*)0x40094238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
+#define REG_PWM_DTUPD1   (*(WoReg*)0x4009423CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
+#define REG_PWM_CMR2     (*(RwReg*)0x40094240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
+#define REG_PWM_CDTY2    (*(RwReg*)0x40094244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
+#define REG_PWM_CDTYUPD2 (*(WoReg*)0x40094248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
+#define REG_PWM_CPRD2    (*(RwReg*)0x4009424CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
+#define REG_PWM_CPRDUPD2 (*(WoReg*)0x40094250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
+#define REG_PWM_CCNT2    (*(RoReg*)0x40094254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
+#define REG_PWM_DT2      (*(RwReg*)0x40094258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
+#define REG_PWM_DTUPD2   (*(WoReg*)0x4009425CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
+#define REG_PWM_CMR3     (*(RwReg*)0x40094260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
+#define REG_PWM_CDTY3    (*(RwReg*)0x40094264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
+#define REG_PWM_CDTYUPD3 (*(WoReg*)0x40094268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
+#define REG_PWM_CPRD3    (*(RwReg*)0x4009426CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
+#define REG_PWM_CPRDUPD3 (*(WoReg*)0x40094270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
+#define REG_PWM_CCNT3    (*(RoReg*)0x40094274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
+#define REG_PWM_DT3      (*(RwReg*)0x40094278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
+#define REG_PWM_DTUPD3   (*(WoReg*)0x4009427CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
+#define REG_PWM_CMR4     (*(RwReg*)0x40094280U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 4) */
+#define REG_PWM_CDTY4    (*(RwReg*)0x40094284U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 4) */
+#define REG_PWM_CDTYUPD4 (*(WoReg*)0x40094288U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 4) */
+#define REG_PWM_CPRD4    (*(RwReg*)0x4009428CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 4) */
+#define REG_PWM_CPRDUPD4 (*(WoReg*)0x40094290U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 4) */
+#define REG_PWM_CCNT4    (*(RoReg*)0x40094294U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 4) */
+#define REG_PWM_DT4      (*(RwReg*)0x40094298U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 4) */
+#define REG_PWM_DTUPD4   (*(WoReg*)0x4009429CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 4) */
+#define REG_PWM_CMR5     (*(RwReg*)0x400942A0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 5) */
+#define REG_PWM_CDTY5    (*(RwReg*)0x400942A4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 5) */
+#define REG_PWM_CDTYUPD5 (*(WoReg*)0x400942A8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 5) */
+#define REG_PWM_CPRD5    (*(RwReg*)0x400942ACU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 5) */
+#define REG_PWM_CPRDUPD5 (*(WoReg*)0x400942B0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 5) */
+#define REG_PWM_CCNT5    (*(RoReg*)0x400942B4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 5) */
+#define REG_PWM_DT5      (*(RwReg*)0x400942B8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 5) */
+#define REG_PWM_DTUPD5   (*(WoReg*)0x400942BCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 5) */
+#define REG_PWM_CMR6     (*(RwReg*)0x400942C0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 6) */
+#define REG_PWM_CDTY6    (*(RwReg*)0x400942C4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 6) */
+#define REG_PWM_CDTYUPD6 (*(WoReg*)0x400942C8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 6) */
+#define REG_PWM_CPRD6    (*(RwReg*)0x400942CCU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 6) */
+#define REG_PWM_CPRDUPD6 (*(WoReg*)0x400942D0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 6) */
+#define REG_PWM_CCNT6    (*(RoReg*)0x400942D4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 6) */
+#define REG_PWM_DT6      (*(RwReg*)0x400942D8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 6) */
+#define REG_PWM_DTUPD6   (*(WoReg*)0x400942DCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 6) */
+#define REG_PWM_CMR7     (*(RwReg*)0x400942E0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 7) */
+#define REG_PWM_CDTY7    (*(RwReg*)0x400942E4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 7) */
+#define REG_PWM_CDTYUPD7 (*(WoReg*)0x400942E8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 7) */
+#define REG_PWM_CPRD7    (*(RwReg*)0x400942ECU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 7) */
+#define REG_PWM_CPRDUPD7 (*(WoReg*)0x400942F0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 7) */
+#define REG_PWM_CCNT7    (*(RoReg*)0x400942F4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 7) */
+#define REG_PWM_DT7      (*(RwReg*)0x400942F8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 7) */
+#define REG_PWM_DTUPD7   (*(WoReg*)0x400942FCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 7) */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_PWM_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_rstc.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_rstc.h
new file mode 100644
index 000000000..e2cd8dd25
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_rstc.h
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_RSTC_INSTANCE_
+#define _SAM3XA_RSTC_INSTANCE_
+
+/* ========== Register definition for RSTC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_RSTC_CR          (0x400E1A00U) /**< \brief (RSTC) Control Register */
+#define REG_RSTC_SR          (0x400E1A04U) /**< \brief (RSTC) Status Register */
+#define REG_RSTC_MR          (0x400E1A08U) /**< \brief (RSTC) Mode Register */
+#else
+#define REG_RSTC_CR (*(WoReg*)0x400E1A00U) /**< \brief (RSTC) Control Register */
+#define REG_RSTC_SR (*(RoReg*)0x400E1A04U) /**< \brief (RSTC) Status Register */
+#define REG_RSTC_MR (*(RwReg*)0x400E1A08U) /**< \brief (RSTC) Mode Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_RSTC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_rtc.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_rtc.h
new file mode 100644
index 000000000..3aedcc492
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_rtc.h
@@ -0,0 +1,64 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_RTC_INSTANCE_
+#define _SAM3XA_RTC_INSTANCE_
+
+/* ========== Register definition for RTC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_RTC_CR              (0x400E1A60U) /**< \brief (RTC) Control Register */
+#define REG_RTC_MR              (0x400E1A64U) /**< \brief (RTC) Mode Register */
+#define REG_RTC_TIMR            (0x400E1A68U) /**< \brief (RTC) Time Register */
+#define REG_RTC_CALR            (0x400E1A6CU) /**< \brief (RTC) Calendar Register */
+#define REG_RTC_TIMALR          (0x400E1A70U) /**< \brief (RTC) Time Alarm Register */
+#define REG_RTC_CALALR          (0x400E1A74U) /**< \brief (RTC) Calendar Alarm Register */
+#define REG_RTC_SR              (0x400E1A78U) /**< \brief (RTC) Status Register */
+#define REG_RTC_SCCR            (0x400E1A7CU) /**< \brief (RTC) Status Clear Command Register */
+#define REG_RTC_IER             (0x400E1A80U) /**< \brief (RTC) Interrupt Enable Register */
+#define REG_RTC_IDR             (0x400E1A84U) /**< \brief (RTC) Interrupt Disable Register */
+#define REG_RTC_IMR             (0x400E1A88U) /**< \brief (RTC) Interrupt Mask Register */
+#define REG_RTC_VER             (0x400E1A8CU) /**< \brief (RTC) Valid Entry Register */
+#define REG_RTC_WPMR            (0x400E1B44U) /**< \brief (RTC) Write Protect Mode Register */
+#else
+#define REG_RTC_CR     (*(RwReg*)0x400E1A60U) /**< \brief (RTC) Control Register */
+#define REG_RTC_MR     (*(RwReg*)0x400E1A64U) /**< \brief (RTC) Mode Register */
+#define REG_RTC_TIMR   (*(RwReg*)0x400E1A68U) /**< \brief (RTC) Time Register */
+#define REG_RTC_CALR   (*(RwReg*)0x400E1A6CU) /**< \brief (RTC) Calendar Register */
+#define REG_RTC_TIMALR (*(RwReg*)0x400E1A70U) /**< \brief (RTC) Time Alarm Register */
+#define REG_RTC_CALALR (*(RwReg*)0x400E1A74U) /**< \brief (RTC) Calendar Alarm Register */
+#define REG_RTC_SR     (*(RoReg*)0x400E1A78U) /**< \brief (RTC) Status Register */
+#define REG_RTC_SCCR   (*(WoReg*)0x400E1A7CU) /**< \brief (RTC) Status Clear Command Register */
+#define REG_RTC_IER    (*(WoReg*)0x400E1A80U) /**< \brief (RTC) Interrupt Enable Register */
+#define REG_RTC_IDR    (*(WoReg*)0x400E1A84U) /**< \brief (RTC) Interrupt Disable Register */
+#define REG_RTC_IMR    (*(RoReg*)0x400E1A88U) /**< \brief (RTC) Interrupt Mask Register */
+#define REG_RTC_VER    (*(RoReg*)0x400E1A8CU) /**< \brief (RTC) Valid Entry Register */
+#define REG_RTC_WPMR   (*(RwReg*)0x400E1B44U) /**< \brief (RTC) Write Protect Mode Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_RTC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_rtt.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_rtt.h
new file mode 100644
index 000000000..912a296ca
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_rtt.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_RTT_INSTANCE_
+#define _SAM3XA_RTT_INSTANCE_
+
+/* ========== Register definition for RTT peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_RTT_MR          (0x400E1A30U) /**< \brief (RTT) Mode Register */
+#define REG_RTT_AR          (0x400E1A34U) /**< \brief (RTT) Alarm Register */
+#define REG_RTT_VR          (0x400E1A38U) /**< \brief (RTT) Value Register */
+#define REG_RTT_SR          (0x400E1A3CU) /**< \brief (RTT) Status Register */
+#else
+#define REG_RTT_MR (*(RwReg*)0x400E1A30U) /**< \brief (RTT) Mode Register */
+#define REG_RTT_AR (*(RwReg*)0x400E1A34U) /**< \brief (RTT) Alarm Register */
+#define REG_RTT_VR (*(RoReg*)0x400E1A38U) /**< \brief (RTT) Value Register */
+#define REG_RTT_SR (*(RoReg*)0x400E1A3CU) /**< \brief (RTT) Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_RTT_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_sdramc.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_sdramc.h
new file mode 100644
index 000000000..aebb86366
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_sdramc.h
@@ -0,0 +1,60 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SDRAMC_INSTANCE_
+#define _SAM3XA_SDRAMC_INSTANCE_
+
+/* ========== Register definition for SDRAMC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_SDRAMC_MR            (0x400E0200U) /**< \brief (SDRAMC) SDRAMC Mode Register */
+#define REG_SDRAMC_TR            (0x400E0204U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */
+#define REG_SDRAMC_CR            (0x400E0208U) /**< \brief (SDRAMC) SDRAMC Configuration Register */
+#define REG_SDRAMC_LPR           (0x400E0210U) /**< \brief (SDRAMC) SDRAMC Low Power Register */
+#define REG_SDRAMC_IER           (0x400E0214U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */
+#define REG_SDRAMC_IDR           (0x400E0218U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */
+#define REG_SDRAMC_IMR           (0x400E021CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */
+#define REG_SDRAMC_ISR           (0x400E0220U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */
+#define REG_SDRAMC_MDR           (0x400E0224U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */
+#define REG_SDRAMC_CR1           (0x400E0228U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */
+#define REG_SDRAMC_OCMS          (0x400E022CU) /**< \brief (SDRAMC) SDRAMC OCMS Register 1 */
+#else
+#define REG_SDRAMC_MR   (*(RwReg*)0x400E0200U) /**< \brief (SDRAMC) SDRAMC Mode Register */
+#define REG_SDRAMC_TR   (*(RwReg*)0x400E0204U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */
+#define REG_SDRAMC_CR   (*(RwReg*)0x400E0208U) /**< \brief (SDRAMC) SDRAMC Configuration Register */
+#define REG_SDRAMC_LPR  (*(RwReg*)0x400E0210U) /**< \brief (SDRAMC) SDRAMC Low Power Register */
+#define REG_SDRAMC_IER  (*(WoReg*)0x400E0214U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */
+#define REG_SDRAMC_IDR  (*(WoReg*)0x400E0218U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */
+#define REG_SDRAMC_IMR  (*(RoReg*)0x400E021CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */
+#define REG_SDRAMC_ISR  (*(RoReg*)0x400E0220U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */
+#define REG_SDRAMC_MDR  (*(RwReg*)0x400E0224U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */
+#define REG_SDRAMC_CR1  (*(RwReg*)0x400E0228U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */
+#define REG_SDRAMC_OCMS (*(RwReg*)0x400E022CU) /**< \brief (SDRAMC) SDRAMC OCMS Register 1 */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_SDRAMC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_smc.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_smc.h
new file mode 100644
index 000000000..c5115cf63
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_smc.h
@@ -0,0 +1,184 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SMC_INSTANCE_
+#define _SAM3XA_SMC_INSTANCE_
+
+/* ========== Register definition for SMC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_SMC_CFG               (0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */
+#define REG_SMC_CTRL              (0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */
+#define REG_SMC_SR                (0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */
+#define REG_SMC_IER               (0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */
+#define REG_SMC_IDR               (0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */
+#define REG_SMC_IMR               (0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */
+#define REG_SMC_ADDR              (0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */
+#define REG_SMC_BANK              (0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */
+#define REG_SMC_ECC_CTRL          (0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */
+#define REG_SMC_ECC_MD            (0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */
+#define REG_SMC_ECC_SR1           (0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */
+#define REG_SMC_ECC_PR0           (0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */
+#define REG_SMC_ECC_PR1           (0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */
+#define REG_SMC_ECC_SR2           (0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */
+#define REG_SMC_ECC_PR2           (0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */
+#define REG_SMC_ECC_PR3           (0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */
+#define REG_SMC_ECC_PR4           (0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */
+#define REG_SMC_ECC_PR5           (0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */
+#define REG_SMC_ECC_PR6           (0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */
+#define REG_SMC_ECC_PR7           (0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */
+#define REG_SMC_ECC_PR8           (0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */
+#define REG_SMC_ECC_PR9           (0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */
+#define REG_SMC_ECC_PR10          (0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */
+#define REG_SMC_ECC_PR11          (0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */
+#define REG_SMC_ECC_PR12          (0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */
+#define REG_SMC_ECC_PR13          (0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */
+#define REG_SMC_ECC_PR14          (0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */
+#define REG_SMC_ECC_PR15          (0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */
+#define REG_SMC_SETUP0            (0x400E0070U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
+#define REG_SMC_PULSE0            (0x400E0074U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
+#define REG_SMC_CYCLE0            (0x400E0078U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
+#define REG_SMC_TIMINGS0          (0x400E007CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */
+#define REG_SMC_MODE0             (0x400E0080U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
+#define REG_SMC_SETUP1            (0x400E0084U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
+#define REG_SMC_PULSE1            (0x400E0088U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
+#define REG_SMC_CYCLE1            (0x400E008CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
+#define REG_SMC_TIMINGS1          (0x400E0090U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */
+#define REG_SMC_MODE1             (0x400E0094U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
+#define REG_SMC_SETUP2            (0x400E0098U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
+#define REG_SMC_PULSE2            (0x400E009CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
+#define REG_SMC_CYCLE2            (0x400E00A0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
+#define REG_SMC_TIMINGS2          (0x400E00A4U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */
+#define REG_SMC_MODE2             (0x400E00A8U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
+#define REG_SMC_SETUP3            (0x400E00ACU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
+#define REG_SMC_PULSE3            (0x400E00B0U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
+#define REG_SMC_CYCLE3            (0x400E00B4U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
+#define REG_SMC_TIMINGS3          (0x400E00B8U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */
+#define REG_SMC_MODE3             (0x400E00BCU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
+#define REG_SMC_SETUP4            (0x400E00C0U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */
+#define REG_SMC_PULSE4            (0x400E00C4U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */
+#define REG_SMC_CYCLE4            (0x400E00C8U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */
+#define REG_SMC_TIMINGS4          (0x400E00CCU) /**< \brief (SMC) SMC Timings Register (CS_number = 4) */
+#define REG_SMC_MODE4             (0x400E00D0U) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */
+#define REG_SMC_SETUP5            (0x400E00D4U) /**< \brief (SMC) SMC Setup Register (CS_number = 5) */
+#define REG_SMC_PULSE5            (0x400E00D8U) /**< \brief (SMC) SMC Pulse Register (CS_number = 5) */
+#define REG_SMC_CYCLE5            (0x400E00DCU) /**< \brief (SMC) SMC Cycle Register (CS_number = 5) */
+#define REG_SMC_TIMINGS5          (0x400E00E0U) /**< \brief (SMC) SMC Timings Register (CS_number = 5) */
+#define REG_SMC_MODE5             (0x400E00E4U) /**< \brief (SMC) SMC Mode Register (CS_number = 5) */
+#define REG_SMC_SETUP6            (0x400E00E8U) /**< \brief (SMC) SMC Setup Register (CS_number = 6) */
+#define REG_SMC_PULSE6            (0x400E00ECU) /**< \brief (SMC) SMC Pulse Register (CS_number = 6) */
+#define REG_SMC_CYCLE6            (0x400E00F0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 6) */
+#define REG_SMC_TIMINGS6          (0x400E00F4U) /**< \brief (SMC) SMC Timings Register (CS_number = 6) */
+#define REG_SMC_MODE6             (0x400E00F8U) /**< \brief (SMC) SMC Mode Register (CS_number = 6) */
+#define REG_SMC_SETUP7            (0x400E00FCU) /**< \brief (SMC) SMC Setup Register (CS_number = 7) */
+#define REG_SMC_PULSE7            (0x400E0100U) /**< \brief (SMC) SMC Pulse Register (CS_number = 7) */
+#define REG_SMC_CYCLE7            (0x400E0104U) /**< \brief (SMC) SMC Cycle Register (CS_number = 7) */
+#define REG_SMC_TIMINGS7          (0x400E0108U) /**< \brief (SMC) SMC Timings Register (CS_number = 7) */
+#define REG_SMC_MODE7             (0x400E010CU) /**< \brief (SMC) SMC Mode Register (CS_number = 7) */
+#define REG_SMC_OCMS              (0x400E0110U) /**< \brief (SMC) SMC OCMS Register */
+#define REG_SMC_KEY1              (0x400E0114U) /**< \brief (SMC) SMC OCMS KEY1 Register */
+#define REG_SMC_KEY2              (0x400E0118U) /**< \brief (SMC) SMC OCMS KEY2 Register */
+#define REG_SMC_WPCR              (0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */
+#define REG_SMC_WPSR              (0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */
+#else
+#define REG_SMC_CFG      (*(RwReg*)0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */
+#define REG_SMC_CTRL     (*(WoReg*)0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */
+#define REG_SMC_SR       (*(RoReg*)0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */
+#define REG_SMC_IER      (*(WoReg*)0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */
+#define REG_SMC_IDR      (*(WoReg*)0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */
+#define REG_SMC_IMR      (*(RoReg*)0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */
+#define REG_SMC_ADDR     (*(RwReg*)0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */
+#define REG_SMC_BANK     (*(RwReg*)0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */
+#define REG_SMC_ECC_CTRL (*(WoReg*)0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */
+#define REG_SMC_ECC_MD   (*(RwReg*)0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */
+#define REG_SMC_ECC_SR1  (*(RoReg*)0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */
+#define REG_SMC_ECC_PR0  (*(RoReg*)0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */
+#define REG_SMC_ECC_PR1  (*(RoReg*)0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */
+#define REG_SMC_ECC_SR2  (*(RoReg*)0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */
+#define REG_SMC_ECC_PR2  (*(RoReg*)0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */
+#define REG_SMC_ECC_PR3  (*(RoReg*)0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */
+#define REG_SMC_ECC_PR4  (*(RoReg*)0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */
+#define REG_SMC_ECC_PR5  (*(RoReg*)0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */
+#define REG_SMC_ECC_PR6  (*(RoReg*)0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */
+#define REG_SMC_ECC_PR7  (*(RoReg*)0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */
+#define REG_SMC_ECC_PR8  (*(RoReg*)0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */
+#define REG_SMC_ECC_PR9  (*(RoReg*)0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */
+#define REG_SMC_ECC_PR10 (*(RoReg*)0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */
+#define REG_SMC_ECC_PR11 (*(RoReg*)0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */
+#define REG_SMC_ECC_PR12 (*(RoReg*)0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */
+#define REG_SMC_ECC_PR13 (*(RoReg*)0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */
+#define REG_SMC_ECC_PR14 (*(RoReg*)0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */
+#define REG_SMC_ECC_PR15 (*(RoReg*)0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */
+#define REG_SMC_SETUP0   (*(RwReg*)0x400E0070U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
+#define REG_SMC_PULSE0   (*(RwReg*)0x400E0074U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
+#define REG_SMC_CYCLE0   (*(RwReg*)0x400E0078U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
+#define REG_SMC_TIMINGS0 (*(RwReg*)0x400E007CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */
+#define REG_SMC_MODE0    (*(RwReg*)0x400E0080U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
+#define REG_SMC_SETUP1   (*(RwReg*)0x400E0084U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
+#define REG_SMC_PULSE1   (*(RwReg*)0x400E0088U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
+#define REG_SMC_CYCLE1   (*(RwReg*)0x400E008CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
+#define REG_SMC_TIMINGS1 (*(RwReg*)0x400E0090U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */
+#define REG_SMC_MODE1    (*(RwReg*)0x400E0094U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
+#define REG_SMC_SETUP2   (*(RwReg*)0x400E0098U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
+#define REG_SMC_PULSE2   (*(RwReg*)0x400E009CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
+#define REG_SMC_CYCLE2   (*(RwReg*)0x400E00A0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
+#define REG_SMC_TIMINGS2 (*(RwReg*)0x400E00A4U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */
+#define REG_SMC_MODE2    (*(RwReg*)0x400E00A8U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
+#define REG_SMC_SETUP3   (*(RwReg*)0x400E00ACU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
+#define REG_SMC_PULSE3   (*(RwReg*)0x400E00B0U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
+#define REG_SMC_CYCLE3   (*(RwReg*)0x400E00B4U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
+#define REG_SMC_TIMINGS3 (*(RwReg*)0x400E00B8U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */
+#define REG_SMC_MODE3    (*(RwReg*)0x400E00BCU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
+#define REG_SMC_SETUP4   (*(RwReg*)0x400E00C0U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */
+#define REG_SMC_PULSE4   (*(RwReg*)0x400E00C4U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */
+#define REG_SMC_CYCLE4   (*(RwReg*)0x400E00C8U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */
+#define REG_SMC_TIMINGS4 (*(RwReg*)0x400E00CCU) /**< \brief (SMC) SMC Timings Register (CS_number = 4) */
+#define REG_SMC_MODE4    (*(RwReg*)0x400E00D0U) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */
+#define REG_SMC_SETUP5   (*(RwReg*)0x400E00D4U) /**< \brief (SMC) SMC Setup Register (CS_number = 5) */
+#define REG_SMC_PULSE5   (*(RwReg*)0x400E00D8U) /**< \brief (SMC) SMC Pulse Register (CS_number = 5) */
+#define REG_SMC_CYCLE5   (*(RwReg*)0x400E00DCU) /**< \brief (SMC) SMC Cycle Register (CS_number = 5) */
+#define REG_SMC_TIMINGS5 (*(RwReg*)0x400E00E0U) /**< \brief (SMC) SMC Timings Register (CS_number = 5) */
+#define REG_SMC_MODE5    (*(RwReg*)0x400E00E4U) /**< \brief (SMC) SMC Mode Register (CS_number = 5) */
+#define REG_SMC_SETUP6   (*(RwReg*)0x400E00E8U) /**< \brief (SMC) SMC Setup Register (CS_number = 6) */
+#define REG_SMC_PULSE6   (*(RwReg*)0x400E00ECU) /**< \brief (SMC) SMC Pulse Register (CS_number = 6) */
+#define REG_SMC_CYCLE6   (*(RwReg*)0x400E00F0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 6) */
+#define REG_SMC_TIMINGS6 (*(RwReg*)0x400E00F4U) /**< \brief (SMC) SMC Timings Register (CS_number = 6) */
+#define REG_SMC_MODE6    (*(RwReg*)0x400E00F8U) /**< \brief (SMC) SMC Mode Register (CS_number = 6) */
+#define REG_SMC_SETUP7   (*(RwReg*)0x400E00FCU) /**< \brief (SMC) SMC Setup Register (CS_number = 7) */
+#define REG_SMC_PULSE7   (*(RwReg*)0x400E0100U) /**< \brief (SMC) SMC Pulse Register (CS_number = 7) */
+#define REG_SMC_CYCLE7   (*(RwReg*)0x400E0104U) /**< \brief (SMC) SMC Cycle Register (CS_number = 7) */
+#define REG_SMC_TIMINGS7 (*(RwReg*)0x400E0108U) /**< \brief (SMC) SMC Timings Register (CS_number = 7) */
+#define REG_SMC_MODE7    (*(RwReg*)0x400E010CU) /**< \brief (SMC) SMC Mode Register (CS_number = 7) */
+#define REG_SMC_OCMS     (*(RwReg*)0x400E0110U) /**< \brief (SMC) SMC OCMS Register */
+#define REG_SMC_KEY1     (*(WoReg*)0x400E0114U) /**< \brief (SMC) SMC OCMS KEY1 Register */
+#define REG_SMC_KEY2     (*(WoReg*)0x400E0118U) /**< \brief (SMC) SMC OCMS KEY2 Register */
+#define REG_SMC_WPCR     (*(WoReg*)0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */
+#define REG_SMC_WPSR     (*(RoReg*)0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_SMC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_spi0.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_spi0.h
new file mode 100644
index 000000000..9d957ce16
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_spi0.h
@@ -0,0 +1,60 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SPI0_INSTANCE_
+#define _SAM3XA_SPI0_INSTANCE_
+
+/* ========== Register definition for SPI0 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_SPI0_CR              (0x40008000U) /**< \brief (SPI0) Control Register */
+#define REG_SPI0_MR              (0x40008004U) /**< \brief (SPI0) Mode Register */
+#define REG_SPI0_RDR             (0x40008008U) /**< \brief (SPI0) Receive Data Register */
+#define REG_SPI0_TDR             (0x4000800CU) /**< \brief (SPI0) Transmit Data Register */
+#define REG_SPI0_SR              (0x40008010U) /**< \brief (SPI0) Status Register */
+#define REG_SPI0_IER             (0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */
+#define REG_SPI0_IDR             (0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */
+#define REG_SPI0_IMR             (0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */
+#define REG_SPI0_CSR             (0x40008030U) /**< \brief (SPI0) Chip Select Register */
+#define REG_SPI0_WPMR            (0x400080E4U) /**< \brief (SPI0) Write Protection Control Register */
+#define REG_SPI0_WPSR            (0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */
+#else
+#define REG_SPI0_CR     (*(WoReg*)0x40008000U) /**< \brief (SPI0) Control Register */
+#define REG_SPI0_MR     (*(RwReg*)0x40008004U) /**< \brief (SPI0) Mode Register */
+#define REG_SPI0_RDR    (*(RoReg*)0x40008008U) /**< \brief (SPI0) Receive Data Register */
+#define REG_SPI0_TDR    (*(WoReg*)0x4000800CU) /**< \brief (SPI0) Transmit Data Register */
+#define REG_SPI0_SR     (*(RoReg*)0x40008010U) /**< \brief (SPI0) Status Register */
+#define REG_SPI0_IER    (*(WoReg*)0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */
+#define REG_SPI0_IDR    (*(WoReg*)0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */
+#define REG_SPI0_IMR    (*(RoReg*)0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */
+#define REG_SPI0_CSR    (*(RwReg*)0x40008030U) /**< \brief (SPI0) Chip Select Register */
+#define REG_SPI0_WPMR   (*(RwReg*)0x400080E4U) /**< \brief (SPI0) Write Protection Control Register */
+#define REG_SPI0_WPSR   (*(RoReg*)0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_SPI0_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_spi1.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_spi1.h
new file mode 100644
index 000000000..f47352bae
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_spi1.h
@@ -0,0 +1,60 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SPI1_INSTANCE_
+#define _SAM3XA_SPI1_INSTANCE_
+
+/* ========== Register definition for SPI1 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_SPI1_CR              (0x4000C000U) /**< \brief (SPI1) Control Register */
+#define REG_SPI1_MR              (0x4000C004U) /**< \brief (SPI1) Mode Register */
+#define REG_SPI1_RDR             (0x4000C008U) /**< \brief (SPI1) Receive Data Register */
+#define REG_SPI1_TDR             (0x4000C00CU) /**< \brief (SPI1) Transmit Data Register */
+#define REG_SPI1_SR              (0x4000C010U) /**< \brief (SPI1) Status Register */
+#define REG_SPI1_IER             (0x4000C014U) /**< \brief (SPI1) Interrupt Enable Register */
+#define REG_SPI1_IDR             (0x4000C018U) /**< \brief (SPI1) Interrupt Disable Register */
+#define REG_SPI1_IMR             (0x4000C01CU) /**< \brief (SPI1) Interrupt Mask Register */
+#define REG_SPI1_CSR             (0x4000C030U) /**< \brief (SPI1) Chip Select Register */
+#define REG_SPI1_WPMR            (0x4000C0E4U) /**< \brief (SPI1) Write Protection Control Register */
+#define REG_SPI1_WPSR            (0x4000C0E8U) /**< \brief (SPI1) Write Protection Status Register */
+#else
+#define REG_SPI1_CR     (*(WoReg*)0x4000C000U) /**< \brief (SPI1) Control Register */
+#define REG_SPI1_MR     (*(RwReg*)0x4000C004U) /**< \brief (SPI1) Mode Register */
+#define REG_SPI1_RDR    (*(RoReg*)0x4000C008U) /**< \brief (SPI1) Receive Data Register */
+#define REG_SPI1_TDR    (*(WoReg*)0x4000C00CU) /**< \brief (SPI1) Transmit Data Register */
+#define REG_SPI1_SR     (*(RoReg*)0x4000C010U) /**< \brief (SPI1) Status Register */
+#define REG_SPI1_IER    (*(WoReg*)0x4000C014U) /**< \brief (SPI1) Interrupt Enable Register */
+#define REG_SPI1_IDR    (*(WoReg*)0x4000C018U) /**< \brief (SPI1) Interrupt Disable Register */
+#define REG_SPI1_IMR    (*(RoReg*)0x4000C01CU) /**< \brief (SPI1) Interrupt Mask Register */
+#define REG_SPI1_CSR    (*(RwReg*)0x4000C030U) /**< \brief (SPI1) Chip Select Register */
+#define REG_SPI1_WPMR   (*(RwReg*)0x4000C0E4U) /**< \brief (SPI1) Write Protection Control Register */
+#define REG_SPI1_WPSR   (*(RoReg*)0x4000C0E8U) /**< \brief (SPI1) Write Protection Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_SPI1_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_ssc.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_ssc.h
new file mode 100644
index 000000000..34c1c0a00
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_ssc.h
@@ -0,0 +1,74 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SSC_INSTANCE_
+#define _SAM3XA_SSC_INSTANCE_
+
+/* ========== Register definition for SSC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_SSC_CR            (0x40004000U) /**< \brief (SSC) Control Register */
+#define REG_SSC_CMR           (0x40004004U) /**< \brief (SSC) Clock Mode Register */
+#define REG_SSC_RCMR          (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
+#define REG_SSC_RFMR          (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
+#define REG_SSC_TCMR          (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
+#define REG_SSC_TFMR          (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
+#define REG_SSC_RHR           (0x40004020U) /**< \brief (SSC) Receive Holding Register */
+#define REG_SSC_THR           (0x40004024U) /**< \brief (SSC) Transmit Holding Register */
+#define REG_SSC_RSHR          (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
+#define REG_SSC_TSHR          (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
+#define REG_SSC_RC0R          (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
+#define REG_SSC_RC1R          (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
+#define REG_SSC_SR            (0x40004040U) /**< \brief (SSC) Status Register */
+#define REG_SSC_IER           (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
+#define REG_SSC_IDR           (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
+#define REG_SSC_IMR           (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
+#define REG_SSC_WPMR          (0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
+#define REG_SSC_WPSR          (0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
+#else
+#define REG_SSC_CR   (*(WoReg*)0x40004000U) /**< \brief (SSC) Control Register */
+#define REG_SSC_CMR  (*(RwReg*)0x40004004U) /**< \brief (SSC) Clock Mode Register */
+#define REG_SSC_RCMR (*(RwReg*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
+#define REG_SSC_RFMR (*(RwReg*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
+#define REG_SSC_TCMR (*(RwReg*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
+#define REG_SSC_TFMR (*(RwReg*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
+#define REG_SSC_RHR  (*(RoReg*)0x40004020U) /**< \brief (SSC) Receive Holding Register */
+#define REG_SSC_THR  (*(WoReg*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */
+#define REG_SSC_RSHR (*(RoReg*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
+#define REG_SSC_TSHR (*(RwReg*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
+#define REG_SSC_RC0R (*(RwReg*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
+#define REG_SSC_RC1R (*(RwReg*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
+#define REG_SSC_SR   (*(RoReg*)0x40004040U) /**< \brief (SSC) Status Register */
+#define REG_SSC_IER  (*(WoReg*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
+#define REG_SSC_IDR  (*(WoReg*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
+#define REG_SSC_IMR  (*(RoReg*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
+#define REG_SSC_WPMR (*(RwReg*)0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
+#define REG_SSC_WPSR (*(RoReg*)0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_SSC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_supc.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_supc.h
new file mode 100644
index 000000000..5d5ecb50a
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_supc.h
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SUPC_INSTANCE_
+#define _SAM3XA_SUPC_INSTANCE_
+
+/* ========== Register definition for SUPC peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_SUPC_CR            (0x400E1A10U) /**< \brief (SUPC) Supply Controller Control Register */
+#define REG_SUPC_SMMR          (0x400E1A14U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
+#define REG_SUPC_MR            (0x400E1A18U) /**< \brief (SUPC) Supply Controller Mode Register */
+#define REG_SUPC_WUMR          (0x400E1A1CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
+#define REG_SUPC_WUIR          (0x400E1A20U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
+#define REG_SUPC_SR            (0x400E1A24U) /**< \brief (SUPC) Supply Controller Status Register */
+#else
+#define REG_SUPC_CR   (*(WoReg*)0x400E1A10U) /**< \brief (SUPC) Supply Controller Control Register */
+#define REG_SUPC_SMMR (*(RwReg*)0x400E1A14U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
+#define REG_SUPC_MR   (*(RwReg*)0x400E1A18U) /**< \brief (SUPC) Supply Controller Mode Register */
+#define REG_SUPC_WUMR (*(RwReg*)0x400E1A1CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
+#define REG_SUPC_WUIR (*(RwReg*)0x400E1A20U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
+#define REG_SUPC_SR   (*(RoReg*)0x400E1A24U) /**< \brief (SUPC) Supply Controller Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_SUPC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_tc0.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_tc0.h
new file mode 100644
index 000000000..10c6624ef
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_tc0.h
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_TC0_INSTANCE_
+#define _SAM3XA_TC0_INSTANCE_
+
+/* ========== Register definition for TC0 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_TC0_CCR0           (0x40080000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
+#define REG_TC0_CMR0           (0x40080004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
+#define REG_TC0_SMMR0          (0x40080008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC0_CV0            (0x40080010U) /**< \brief (TC0) Counter Value (channel = 0) */
+#define REG_TC0_RA0            (0x40080014U) /**< \brief (TC0) Register A (channel = 0) */
+#define REG_TC0_RB0            (0x40080018U) /**< \brief (TC0) Register B (channel = 0) */
+#define REG_TC0_RC0            (0x4008001CU) /**< \brief (TC0) Register C (channel = 0) */
+#define REG_TC0_SR0            (0x40080020U) /**< \brief (TC0) Status Register (channel = 0) */
+#define REG_TC0_IER0           (0x40080024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
+#define REG_TC0_IDR0           (0x40080028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
+#define REG_TC0_IMR0           (0x4008002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
+#define REG_TC0_CCR1           (0x40080040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
+#define REG_TC0_CMR1           (0x40080044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
+#define REG_TC0_SMMR1          (0x40080048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC0_CV1            (0x40080050U) /**< \brief (TC0) Counter Value (channel = 1) */
+#define REG_TC0_RA1            (0x40080054U) /**< \brief (TC0) Register A (channel = 1) */
+#define REG_TC0_RB1            (0x40080058U) /**< \brief (TC0) Register B (channel = 1) */
+#define REG_TC0_RC1            (0x4008005CU) /**< \brief (TC0) Register C (channel = 1) */
+#define REG_TC0_SR1            (0x40080060U) /**< \brief (TC0) Status Register (channel = 1) */
+#define REG_TC0_IER1           (0x40080064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
+#define REG_TC0_IDR1           (0x40080068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
+#define REG_TC0_IMR1           (0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
+#define REG_TC0_CCR2           (0x40080080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
+#define REG_TC0_CMR2           (0x40080084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
+#define REG_TC0_SMMR2          (0x40080088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC0_CV2            (0x40080090U) /**< \brief (TC0) Counter Value (channel = 2) */
+#define REG_TC0_RA2            (0x40080094U) /**< \brief (TC0) Register A (channel = 2) */
+#define REG_TC0_RB2            (0x40080098U) /**< \brief (TC0) Register B (channel = 2) */
+#define REG_TC0_RC2            (0x4008009CU) /**< \brief (TC0) Register C (channel = 2) */
+#define REG_TC0_SR2            (0x400800A0U) /**< \brief (TC0) Status Register (channel = 2) */
+#define REG_TC0_IER2           (0x400800A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
+#define REG_TC0_IDR2           (0x400800A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
+#define REG_TC0_IMR2           (0x400800ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
+#define REG_TC0_BCR            (0x400800C0U) /**< \brief (TC0) Block Control Register */
+#define REG_TC0_BMR            (0x400800C4U) /**< \brief (TC0) Block Mode Register */
+#define REG_TC0_QIER           (0x400800C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
+#define REG_TC0_QIDR           (0x400800CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
+#define REG_TC0_QIMR           (0x400800D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
+#define REG_TC0_QISR           (0x400800D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
+#define REG_TC0_FMR            (0x400800D8U) /**< \brief (TC0) Fault Mode Register */
+#define REG_TC0_WPMR           (0x400800E4U) /**< \brief (TC0) Write Protect Mode Register */
+#else
+#define REG_TC0_CCR0  (*(WoReg*)0x40080000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
+#define REG_TC0_CMR0  (*(RwReg*)0x40080004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
+#define REG_TC0_SMMR0 (*(RwReg*)0x40080008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC0_CV0   (*(RoReg*)0x40080010U) /**< \brief (TC0) Counter Value (channel = 0) */
+#define REG_TC0_RA0   (*(RwReg*)0x40080014U) /**< \brief (TC0) Register A (channel = 0) */
+#define REG_TC0_RB0   (*(RwReg*)0x40080018U) /**< \brief (TC0) Register B (channel = 0) */
+#define REG_TC0_RC0   (*(RwReg*)0x4008001CU) /**< \brief (TC0) Register C (channel = 0) */
+#define REG_TC0_SR0   (*(RoReg*)0x40080020U) /**< \brief (TC0) Status Register (channel = 0) */
+#define REG_TC0_IER0  (*(WoReg*)0x40080024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
+#define REG_TC0_IDR0  (*(WoReg*)0x40080028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
+#define REG_TC0_IMR0  (*(RoReg*)0x4008002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
+#define REG_TC0_CCR1  (*(WoReg*)0x40080040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
+#define REG_TC0_CMR1  (*(RwReg*)0x40080044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
+#define REG_TC0_SMMR1 (*(RwReg*)0x40080048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC0_CV1   (*(RoReg*)0x40080050U) /**< \brief (TC0) Counter Value (channel = 1) */
+#define REG_TC0_RA1   (*(RwReg*)0x40080054U) /**< \brief (TC0) Register A (channel = 1) */
+#define REG_TC0_RB1   (*(RwReg*)0x40080058U) /**< \brief (TC0) Register B (channel = 1) */
+#define REG_TC0_RC1   (*(RwReg*)0x4008005CU) /**< \brief (TC0) Register C (channel = 1) */
+#define REG_TC0_SR1   (*(RoReg*)0x40080060U) /**< \brief (TC0) Status Register (channel = 1) */
+#define REG_TC0_IER1  (*(WoReg*)0x40080064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
+#define REG_TC0_IDR1  (*(WoReg*)0x40080068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
+#define REG_TC0_IMR1  (*(RoReg*)0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
+#define REG_TC0_CCR2  (*(WoReg*)0x40080080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
+#define REG_TC0_CMR2  (*(RwReg*)0x40080084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
+#define REG_TC0_SMMR2 (*(RwReg*)0x40080088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC0_CV2   (*(RoReg*)0x40080090U) /**< \brief (TC0) Counter Value (channel = 2) */
+#define REG_TC0_RA2   (*(RwReg*)0x40080094U) /**< \brief (TC0) Register A (channel = 2) */
+#define REG_TC0_RB2   (*(RwReg*)0x40080098U) /**< \brief (TC0) Register B (channel = 2) */
+#define REG_TC0_RC2   (*(RwReg*)0x4008009CU) /**< \brief (TC0) Register C (channel = 2) */
+#define REG_TC0_SR2   (*(RoReg*)0x400800A0U) /**< \brief (TC0) Status Register (channel = 2) */
+#define REG_TC0_IER2  (*(WoReg*)0x400800A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
+#define REG_TC0_IDR2  (*(WoReg*)0x400800A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
+#define REG_TC0_IMR2  (*(RoReg*)0x400800ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
+#define REG_TC0_BCR   (*(WoReg*)0x400800C0U) /**< \brief (TC0) Block Control Register */
+#define REG_TC0_BMR   (*(RwReg*)0x400800C4U) /**< \brief (TC0) Block Mode Register */
+#define REG_TC0_QIER  (*(WoReg*)0x400800C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
+#define REG_TC0_QIDR  (*(WoReg*)0x400800CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
+#define REG_TC0_QIMR  (*(RoReg*)0x400800D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
+#define REG_TC0_QISR  (*(RoReg*)0x400800D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
+#define REG_TC0_FMR   (*(RwReg*)0x400800D8U) /**< \brief (TC0) Fault Mode Register */
+#define REG_TC0_WPMR  (*(RwReg*)0x400800E4U) /**< \brief (TC0) Write Protect Mode Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_TC0_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_tc1.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_tc1.h
new file mode 100644
index 000000000..f40fcc1b1
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_tc1.h
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_TC1_INSTANCE_
+#define _SAM3XA_TC1_INSTANCE_
+
+/* ========== Register definition for TC1 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_TC1_CCR0           (0x40084000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
+#define REG_TC1_CMR0           (0x40084004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
+#define REG_TC1_SMMR0          (0x40084008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC1_CV0            (0x40084010U) /**< \brief (TC1) Counter Value (channel = 0) */
+#define REG_TC1_RA0            (0x40084014U) /**< \brief (TC1) Register A (channel = 0) */
+#define REG_TC1_RB0            (0x40084018U) /**< \brief (TC1) Register B (channel = 0) */
+#define REG_TC1_RC0            (0x4008401CU) /**< \brief (TC1) Register C (channel = 0) */
+#define REG_TC1_SR0            (0x40084020U) /**< \brief (TC1) Status Register (channel = 0) */
+#define REG_TC1_IER0           (0x40084024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
+#define REG_TC1_IDR0           (0x40084028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
+#define REG_TC1_IMR0           (0x4008402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
+#define REG_TC1_CCR1           (0x40084040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
+#define REG_TC1_CMR1           (0x40084044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
+#define REG_TC1_SMMR1          (0x40084048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC1_CV1            (0x40084050U) /**< \brief (TC1) Counter Value (channel = 1) */
+#define REG_TC1_RA1            (0x40084054U) /**< \brief (TC1) Register A (channel = 1) */
+#define REG_TC1_RB1            (0x40084058U) /**< \brief (TC1) Register B (channel = 1) */
+#define REG_TC1_RC1            (0x4008405CU) /**< \brief (TC1) Register C (channel = 1) */
+#define REG_TC1_SR1            (0x40084060U) /**< \brief (TC1) Status Register (channel = 1) */
+#define REG_TC1_IER1           (0x40084064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
+#define REG_TC1_IDR1           (0x40084068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
+#define REG_TC1_IMR1           (0x4008406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
+#define REG_TC1_CCR2           (0x40084080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
+#define REG_TC1_CMR2           (0x40084084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
+#define REG_TC1_SMMR2          (0x40084088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC1_CV2            (0x40084090U) /**< \brief (TC1) Counter Value (channel = 2) */
+#define REG_TC1_RA2            (0x40084094U) /**< \brief (TC1) Register A (channel = 2) */
+#define REG_TC1_RB2            (0x40084098U) /**< \brief (TC1) Register B (channel = 2) */
+#define REG_TC1_RC2            (0x4008409CU) /**< \brief (TC1) Register C (channel = 2) */
+#define REG_TC1_SR2            (0x400840A0U) /**< \brief (TC1) Status Register (channel = 2) */
+#define REG_TC1_IER2           (0x400840A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
+#define REG_TC1_IDR2           (0x400840A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
+#define REG_TC1_IMR2           (0x400840ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
+#define REG_TC1_BCR            (0x400840C0U) /**< \brief (TC1) Block Control Register */
+#define REG_TC1_BMR            (0x400840C4U) /**< \brief (TC1) Block Mode Register */
+#define REG_TC1_QIER           (0x400840C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
+#define REG_TC1_QIDR           (0x400840CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
+#define REG_TC1_QIMR           (0x400840D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
+#define REG_TC1_QISR           (0x400840D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
+#define REG_TC1_FMR            (0x400840D8U) /**< \brief (TC1) Fault Mode Register */
+#define REG_TC1_WPMR           (0x400840E4U) /**< \brief (TC1) Write Protect Mode Register */
+#else
+#define REG_TC1_CCR0  (*(WoReg*)0x40084000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
+#define REG_TC1_CMR0  (*(RwReg*)0x40084004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
+#define REG_TC1_SMMR0 (*(RwReg*)0x40084008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC1_CV0   (*(RoReg*)0x40084010U) /**< \brief (TC1) Counter Value (channel = 0) */
+#define REG_TC1_RA0   (*(RwReg*)0x40084014U) /**< \brief (TC1) Register A (channel = 0) */
+#define REG_TC1_RB0   (*(RwReg*)0x40084018U) /**< \brief (TC1) Register B (channel = 0) */
+#define REG_TC1_RC0   (*(RwReg*)0x4008401CU) /**< \brief (TC1) Register C (channel = 0) */
+#define REG_TC1_SR0   (*(RoReg*)0x40084020U) /**< \brief (TC1) Status Register (channel = 0) */
+#define REG_TC1_IER0  (*(WoReg*)0x40084024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
+#define REG_TC1_IDR0  (*(WoReg*)0x40084028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
+#define REG_TC1_IMR0  (*(RoReg*)0x4008402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
+#define REG_TC1_CCR1  (*(WoReg*)0x40084040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
+#define REG_TC1_CMR1  (*(RwReg*)0x40084044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
+#define REG_TC1_SMMR1 (*(RwReg*)0x40084048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC1_CV1   (*(RoReg*)0x40084050U) /**< \brief (TC1) Counter Value (channel = 1) */
+#define REG_TC1_RA1   (*(RwReg*)0x40084054U) /**< \brief (TC1) Register A (channel = 1) */
+#define REG_TC1_RB1   (*(RwReg*)0x40084058U) /**< \brief (TC1) Register B (channel = 1) */
+#define REG_TC1_RC1   (*(RwReg*)0x4008405CU) /**< \brief (TC1) Register C (channel = 1) */
+#define REG_TC1_SR1   (*(RoReg*)0x40084060U) /**< \brief (TC1) Status Register (channel = 1) */
+#define REG_TC1_IER1  (*(WoReg*)0x40084064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
+#define REG_TC1_IDR1  (*(WoReg*)0x40084068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
+#define REG_TC1_IMR1  (*(RoReg*)0x4008406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
+#define REG_TC1_CCR2  (*(WoReg*)0x40084080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
+#define REG_TC1_CMR2  (*(RwReg*)0x40084084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
+#define REG_TC1_SMMR2 (*(RwReg*)0x40084088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC1_CV2   (*(RoReg*)0x40084090U) /**< \brief (TC1) Counter Value (channel = 2) */
+#define REG_TC1_RA2   (*(RwReg*)0x40084094U) /**< \brief (TC1) Register A (channel = 2) */
+#define REG_TC1_RB2   (*(RwReg*)0x40084098U) /**< \brief (TC1) Register B (channel = 2) */
+#define REG_TC1_RC2   (*(RwReg*)0x4008409CU) /**< \brief (TC1) Register C (channel = 2) */
+#define REG_TC1_SR2   (*(RoReg*)0x400840A0U) /**< \brief (TC1) Status Register (channel = 2) */
+#define REG_TC1_IER2  (*(WoReg*)0x400840A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
+#define REG_TC1_IDR2  (*(WoReg*)0x400840A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
+#define REG_TC1_IMR2  (*(RoReg*)0x400840ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
+#define REG_TC1_BCR   (*(WoReg*)0x400840C0U) /**< \brief (TC1) Block Control Register */
+#define REG_TC1_BMR   (*(RwReg*)0x400840C4U) /**< \brief (TC1) Block Mode Register */
+#define REG_TC1_QIER  (*(WoReg*)0x400840C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
+#define REG_TC1_QIDR  (*(WoReg*)0x400840CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
+#define REG_TC1_QIMR  (*(RoReg*)0x400840D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
+#define REG_TC1_QISR  (*(RoReg*)0x400840D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
+#define REG_TC1_FMR   (*(RwReg*)0x400840D8U) /**< \brief (TC1) Fault Mode Register */
+#define REG_TC1_WPMR  (*(RwReg*)0x400840E4U) /**< \brief (TC1) Write Protect Mode Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_TC1_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_tc2.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_tc2.h
new file mode 100644
index 000000000..4c4e86112
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_tc2.h
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_TC2_INSTANCE_
+#define _SAM3XA_TC2_INSTANCE_
+
+/* ========== Register definition for TC2 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_TC2_CCR0           (0x40088000U) /**< \brief (TC2) Channel Control Register (channel = 0) */
+#define REG_TC2_CMR0           (0x40088004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */
+#define REG_TC2_SMMR0          (0x40088008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC2_CV0            (0x40088010U) /**< \brief (TC2) Counter Value (channel = 0) */
+#define REG_TC2_RA0            (0x40088014U) /**< \brief (TC2) Register A (channel = 0) */
+#define REG_TC2_RB0            (0x40088018U) /**< \brief (TC2) Register B (channel = 0) */
+#define REG_TC2_RC0            (0x4008801CU) /**< \brief (TC2) Register C (channel = 0) */
+#define REG_TC2_SR0            (0x40088020U) /**< \brief (TC2) Status Register (channel = 0) */
+#define REG_TC2_IER0           (0x40088024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */
+#define REG_TC2_IDR0           (0x40088028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */
+#define REG_TC2_IMR0           (0x4008802CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */
+#define REG_TC2_CCR1           (0x40088040U) /**< \brief (TC2) Channel Control Register (channel = 1) */
+#define REG_TC2_CMR1           (0x40088044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */
+#define REG_TC2_SMMR1          (0x40088048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC2_CV1            (0x40088050U) /**< \brief (TC2) Counter Value (channel = 1) */
+#define REG_TC2_RA1            (0x40088054U) /**< \brief (TC2) Register A (channel = 1) */
+#define REG_TC2_RB1            (0x40088058U) /**< \brief (TC2) Register B (channel = 1) */
+#define REG_TC2_RC1            (0x4008805CU) /**< \brief (TC2) Register C (channel = 1) */
+#define REG_TC2_SR1            (0x40088060U) /**< \brief (TC2) Status Register (channel = 1) */
+#define REG_TC2_IER1           (0x40088064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */
+#define REG_TC2_IDR1           (0x40088068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */
+#define REG_TC2_IMR1           (0x4008806CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */
+#define REG_TC2_CCR2           (0x40088080U) /**< \brief (TC2) Channel Control Register (channel = 2) */
+#define REG_TC2_CMR2           (0x40088084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */
+#define REG_TC2_SMMR2          (0x40088088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC2_CV2            (0x40088090U) /**< \brief (TC2) Counter Value (channel = 2) */
+#define REG_TC2_RA2            (0x40088094U) /**< \brief (TC2) Register A (channel = 2) */
+#define REG_TC2_RB2            (0x40088098U) /**< \brief (TC2) Register B (channel = 2) */
+#define REG_TC2_RC2            (0x4008809CU) /**< \brief (TC2) Register C (channel = 2) */
+#define REG_TC2_SR2            (0x400880A0U) /**< \brief (TC2) Status Register (channel = 2) */
+#define REG_TC2_IER2           (0x400880A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */
+#define REG_TC2_IDR2           (0x400880A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */
+#define REG_TC2_IMR2           (0x400880ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */
+#define REG_TC2_BCR            (0x400880C0U) /**< \brief (TC2) Block Control Register */
+#define REG_TC2_BMR            (0x400880C4U) /**< \brief (TC2) Block Mode Register */
+#define REG_TC2_QIER           (0x400880C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */
+#define REG_TC2_QIDR           (0x400880CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */
+#define REG_TC2_QIMR           (0x400880D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */
+#define REG_TC2_QISR           (0x400880D4U) /**< \brief (TC2) QDEC Interrupt Status Register */
+#define REG_TC2_FMR            (0x400880D8U) /**< \brief (TC2) Fault Mode Register */
+#define REG_TC2_WPMR           (0x400880E4U) /**< \brief (TC2) Write Protect Mode Register */
+#else
+#define REG_TC2_CCR0  (*(WoReg*)0x40088000U) /**< \brief (TC2) Channel Control Register (channel = 0) */
+#define REG_TC2_CMR0  (*(RwReg*)0x40088004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */
+#define REG_TC2_SMMR0 (*(RwReg*)0x40088008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC2_CV0   (*(RoReg*)0x40088010U) /**< \brief (TC2) Counter Value (channel = 0) */
+#define REG_TC2_RA0   (*(RwReg*)0x40088014U) /**< \brief (TC2) Register A (channel = 0) */
+#define REG_TC2_RB0   (*(RwReg*)0x40088018U) /**< \brief (TC2) Register B (channel = 0) */
+#define REG_TC2_RC0   (*(RwReg*)0x4008801CU) /**< \brief (TC2) Register C (channel = 0) */
+#define REG_TC2_SR0   (*(RoReg*)0x40088020U) /**< \brief (TC2) Status Register (channel = 0) */
+#define REG_TC2_IER0  (*(WoReg*)0x40088024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */
+#define REG_TC2_IDR0  (*(WoReg*)0x40088028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */
+#define REG_TC2_IMR0  (*(RoReg*)0x4008802CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */
+#define REG_TC2_CCR1  (*(WoReg*)0x40088040U) /**< \brief (TC2) Channel Control Register (channel = 1) */
+#define REG_TC2_CMR1  (*(RwReg*)0x40088044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */
+#define REG_TC2_SMMR1 (*(RwReg*)0x40088048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC2_CV1   (*(RoReg*)0x40088050U) /**< \brief (TC2) Counter Value (channel = 1) */
+#define REG_TC2_RA1   (*(RwReg*)0x40088054U) /**< \brief (TC2) Register A (channel = 1) */
+#define REG_TC2_RB1   (*(RwReg*)0x40088058U) /**< \brief (TC2) Register B (channel = 1) */
+#define REG_TC2_RC1   (*(RwReg*)0x4008805CU) /**< \brief (TC2) Register C (channel = 1) */
+#define REG_TC2_SR1   (*(RoReg*)0x40088060U) /**< \brief (TC2) Status Register (channel = 1) */
+#define REG_TC2_IER1  (*(WoReg*)0x40088064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */
+#define REG_TC2_IDR1  (*(WoReg*)0x40088068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */
+#define REG_TC2_IMR1  (*(RoReg*)0x4008806CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */
+#define REG_TC2_CCR2  (*(WoReg*)0x40088080U) /**< \brief (TC2) Channel Control Register (channel = 2) */
+#define REG_TC2_CMR2  (*(RwReg*)0x40088084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */
+#define REG_TC2_SMMR2 (*(RwReg*)0x40088088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC2_CV2   (*(RoReg*)0x40088090U) /**< \brief (TC2) Counter Value (channel = 2) */
+#define REG_TC2_RA2   (*(RwReg*)0x40088094U) /**< \brief (TC2) Register A (channel = 2) */
+#define REG_TC2_RB2   (*(RwReg*)0x40088098U) /**< \brief (TC2) Register B (channel = 2) */
+#define REG_TC2_RC2   (*(RwReg*)0x4008809CU) /**< \brief (TC2) Register C (channel = 2) */
+#define REG_TC2_SR2   (*(RoReg*)0x400880A0U) /**< \brief (TC2) Status Register (channel = 2) */
+#define REG_TC2_IER2  (*(WoReg*)0x400880A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */
+#define REG_TC2_IDR2  (*(WoReg*)0x400880A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */
+#define REG_TC2_IMR2  (*(RoReg*)0x400880ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */
+#define REG_TC2_BCR   (*(WoReg*)0x400880C0U) /**< \brief (TC2) Block Control Register */
+#define REG_TC2_BMR   (*(RwReg*)0x400880C4U) /**< \brief (TC2) Block Mode Register */
+#define REG_TC2_QIER  (*(WoReg*)0x400880C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */
+#define REG_TC2_QIDR  (*(WoReg*)0x400880CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */
+#define REG_TC2_QIMR  (*(RoReg*)0x400880D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */
+#define REG_TC2_QISR  (*(RoReg*)0x400880D4U) /**< \brief (TC2) QDEC Interrupt Status Register */
+#define REG_TC2_FMR   (*(RwReg*)0x400880D8U) /**< \brief (TC2) Fault Mode Register */
+#define REG_TC2_WPMR  (*(RwReg*)0x400880E4U) /**< \brief (TC2) Write Protect Mode Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_TC2_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_trng.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_trng.h
new file mode 100644
index 000000000..811cdafcd
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_trng.h
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_TRNG_INSTANCE_
+#define _SAM3XA_TRNG_INSTANCE_
+
+/* ========== Register definition for TRNG peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_TRNG_CR             (0x400BC000U) /**< \brief (TRNG) Control Register */
+#define REG_TRNG_IER            (0x400BC010U) /**< \brief (TRNG) Interrupt Enable Register */
+#define REG_TRNG_IDR            (0x400BC014U) /**< \brief (TRNG) Interrupt Disable Register */
+#define REG_TRNG_IMR            (0x400BC018U) /**< \brief (TRNG) Interrupt Mask Register */
+#define REG_TRNG_ISR            (0x400BC01CU) /**< \brief (TRNG) Interrupt Status Register */
+#define REG_TRNG_ODATA          (0x400BC050U) /**< \brief (TRNG) Output Data Register */
+#else
+#define REG_TRNG_CR    (*(WoReg*)0x400BC000U) /**< \brief (TRNG) Control Register */
+#define REG_TRNG_IER   (*(WoReg*)0x400BC010U) /**< \brief (TRNG) Interrupt Enable Register */
+#define REG_TRNG_IDR   (*(WoReg*)0x400BC014U) /**< \brief (TRNG) Interrupt Disable Register */
+#define REG_TRNG_IMR   (*(RoReg*)0x400BC018U) /**< \brief (TRNG) Interrupt Mask Register */
+#define REG_TRNG_ISR   (*(RoReg*)0x400BC01CU) /**< \brief (TRNG) Interrupt Status Register */
+#define REG_TRNG_ODATA (*(RoReg*)0x400BC050U) /**< \brief (TRNG) Output Data Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_TRNG_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_twi0.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_twi0.h
new file mode 100644
index 000000000..357803339
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_twi0.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_TWI0_INSTANCE_
+#define _SAM3XA_TWI0_INSTANCE_
+
+/* ========== Register definition for TWI0 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_TWI0_CR            (0x4008C000U) /**< \brief (TWI0) Control Register */
+#define REG_TWI0_MMR           (0x4008C004U) /**< \brief (TWI0) Master Mode Register */
+#define REG_TWI0_SMR           (0x4008C008U) /**< \brief (TWI0) Slave Mode Register */
+#define REG_TWI0_IADR          (0x4008C00CU) /**< \brief (TWI0) Internal Address Register */
+#define REG_TWI0_CWGR          (0x4008C010U) /**< \brief (TWI0) Clock Waveform Generator Register */
+#define REG_TWI0_SR            (0x4008C020U) /**< \brief (TWI0) Status Register */
+#define REG_TWI0_IER           (0x4008C024U) /**< \brief (TWI0) Interrupt Enable Register */
+#define REG_TWI0_IDR           (0x4008C028U) /**< \brief (TWI0) Interrupt Disable Register */
+#define REG_TWI0_IMR           (0x4008C02CU) /**< \brief (TWI0) Interrupt Mask Register */
+#define REG_TWI0_RHR           (0x4008C030U) /**< \brief (TWI0) Receive Holding Register */
+#define REG_TWI0_THR           (0x4008C034U) /**< \brief (TWI0) Transmit Holding Register */
+#define REG_TWI0_RPR           (0x4008C100U) /**< \brief (TWI0) Receive Pointer Register */
+#define REG_TWI0_RCR           (0x4008C104U) /**< \brief (TWI0) Receive Counter Register */
+#define REG_TWI0_TPR           (0x4008C108U) /**< \brief (TWI0) Transmit Pointer Register */
+#define REG_TWI0_TCR           (0x4008C10CU) /**< \brief (TWI0) Transmit Counter Register */
+#define REG_TWI0_RNPR          (0x4008C110U) /**< \brief (TWI0) Receive Next Pointer Register */
+#define REG_TWI0_RNCR          (0x4008C114U) /**< \brief (TWI0) Receive Next Counter Register */
+#define REG_TWI0_TNPR          (0x4008C118U) /**< \brief (TWI0) Transmit Next Pointer Register */
+#define REG_TWI0_TNCR          (0x4008C11CU) /**< \brief (TWI0) Transmit Next Counter Register */
+#define REG_TWI0_PTCR          (0x4008C120U) /**< \brief (TWI0) Transfer Control Register */
+#define REG_TWI0_PTSR          (0x4008C124U) /**< \brief (TWI0) Transfer Status Register */
+#else
+#define REG_TWI0_CR   (*(WoReg*)0x4008C000U) /**< \brief (TWI0) Control Register */
+#define REG_TWI0_MMR  (*(RwReg*)0x4008C004U) /**< \brief (TWI0) Master Mode Register */
+#define REG_TWI0_SMR  (*(RwReg*)0x4008C008U) /**< \brief (TWI0) Slave Mode Register */
+#define REG_TWI0_IADR (*(RwReg*)0x4008C00CU) /**< \brief (TWI0) Internal Address Register */
+#define REG_TWI0_CWGR (*(RwReg*)0x4008C010U) /**< \brief (TWI0) Clock Waveform Generator Register */
+#define REG_TWI0_SR   (*(RoReg*)0x4008C020U) /**< \brief (TWI0) Status Register */
+#define REG_TWI0_IER  (*(WoReg*)0x4008C024U) /**< \brief (TWI0) Interrupt Enable Register */
+#define REG_TWI0_IDR  (*(WoReg*)0x4008C028U) /**< \brief (TWI0) Interrupt Disable Register */
+#define REG_TWI0_IMR  (*(RoReg*)0x4008C02CU) /**< \brief (TWI0) Interrupt Mask Register */
+#define REG_TWI0_RHR  (*(RoReg*)0x4008C030U) /**< \brief (TWI0) Receive Holding Register */
+#define REG_TWI0_THR  (*(WoReg*)0x4008C034U) /**< \brief (TWI0) Transmit Holding Register */
+#define REG_TWI0_RPR  (*(RwReg*)0x4008C100U) /**< \brief (TWI0) Receive Pointer Register */
+#define REG_TWI0_RCR  (*(RwReg*)0x4008C104U) /**< \brief (TWI0) Receive Counter Register */
+#define REG_TWI0_TPR  (*(RwReg*)0x4008C108U) /**< \brief (TWI0) Transmit Pointer Register */
+#define REG_TWI0_TCR  (*(RwReg*)0x4008C10CU) /**< \brief (TWI0) Transmit Counter Register */
+#define REG_TWI0_RNPR (*(RwReg*)0x4008C110U) /**< \brief (TWI0) Receive Next Pointer Register */
+#define REG_TWI0_RNCR (*(RwReg*)0x4008C114U) /**< \brief (TWI0) Receive Next Counter Register */
+#define REG_TWI0_TNPR (*(RwReg*)0x4008C118U) /**< \brief (TWI0) Transmit Next Pointer Register */
+#define REG_TWI0_TNCR (*(RwReg*)0x4008C11CU) /**< \brief (TWI0) Transmit Next Counter Register */
+#define REG_TWI0_PTCR (*(WoReg*)0x4008C120U) /**< \brief (TWI0) Transfer Control Register */
+#define REG_TWI0_PTSR (*(RoReg*)0x4008C124U) /**< \brief (TWI0) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_TWI0_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_twi1.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_twi1.h
new file mode 100644
index 000000000..dc4aad851
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_twi1.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_TWI1_INSTANCE_
+#define _SAM3XA_TWI1_INSTANCE_
+
+/* ========== Register definition for TWI1 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_TWI1_CR            (0x40090000U) /**< \brief (TWI1) Control Register */
+#define REG_TWI1_MMR           (0x40090004U) /**< \brief (TWI1) Master Mode Register */
+#define REG_TWI1_SMR           (0x40090008U) /**< \brief (TWI1) Slave Mode Register */
+#define REG_TWI1_IADR          (0x4009000CU) /**< \brief (TWI1) Internal Address Register */
+#define REG_TWI1_CWGR          (0x40090010U) /**< \brief (TWI1) Clock Waveform Generator Register */
+#define REG_TWI1_SR            (0x40090020U) /**< \brief (TWI1) Status Register */
+#define REG_TWI1_IER           (0x40090024U) /**< \brief (TWI1) Interrupt Enable Register */
+#define REG_TWI1_IDR           (0x40090028U) /**< \brief (TWI1) Interrupt Disable Register */
+#define REG_TWI1_IMR           (0x4009002CU) /**< \brief (TWI1) Interrupt Mask Register */
+#define REG_TWI1_RHR           (0x40090030U) /**< \brief (TWI1) Receive Holding Register */
+#define REG_TWI1_THR           (0x40090034U) /**< \brief (TWI1) Transmit Holding Register */
+#define REG_TWI1_RPR           (0x40090100U) /**< \brief (TWI1) Receive Pointer Register */
+#define REG_TWI1_RCR           (0x40090104U) /**< \brief (TWI1) Receive Counter Register */
+#define REG_TWI1_TPR           (0x40090108U) /**< \brief (TWI1) Transmit Pointer Register */
+#define REG_TWI1_TCR           (0x4009010CU) /**< \brief (TWI1) Transmit Counter Register */
+#define REG_TWI1_RNPR          (0x40090110U) /**< \brief (TWI1) Receive Next Pointer Register */
+#define REG_TWI1_RNCR          (0x40090114U) /**< \brief (TWI1) Receive Next Counter Register */
+#define REG_TWI1_TNPR          (0x40090118U) /**< \brief (TWI1) Transmit Next Pointer Register */
+#define REG_TWI1_TNCR          (0x4009011CU) /**< \brief (TWI1) Transmit Next Counter Register */
+#define REG_TWI1_PTCR          (0x40090120U) /**< \brief (TWI1) Transfer Control Register */
+#define REG_TWI1_PTSR          (0x40090124U) /**< \brief (TWI1) Transfer Status Register */
+#else
+#define REG_TWI1_CR   (*(WoReg*)0x40090000U) /**< \brief (TWI1) Control Register */
+#define REG_TWI1_MMR  (*(RwReg*)0x40090004U) /**< \brief (TWI1) Master Mode Register */
+#define REG_TWI1_SMR  (*(RwReg*)0x40090008U) /**< \brief (TWI1) Slave Mode Register */
+#define REG_TWI1_IADR (*(RwReg*)0x4009000CU) /**< \brief (TWI1) Internal Address Register */
+#define REG_TWI1_CWGR (*(RwReg*)0x40090010U) /**< \brief (TWI1) Clock Waveform Generator Register */
+#define REG_TWI1_SR   (*(RoReg*)0x40090020U) /**< \brief (TWI1) Status Register */
+#define REG_TWI1_IER  (*(WoReg*)0x40090024U) /**< \brief (TWI1) Interrupt Enable Register */
+#define REG_TWI1_IDR  (*(WoReg*)0x40090028U) /**< \brief (TWI1) Interrupt Disable Register */
+#define REG_TWI1_IMR  (*(RoReg*)0x4009002CU) /**< \brief (TWI1) Interrupt Mask Register */
+#define REG_TWI1_RHR  (*(RoReg*)0x40090030U) /**< \brief (TWI1) Receive Holding Register */
+#define REG_TWI1_THR  (*(WoReg*)0x40090034U) /**< \brief (TWI1) Transmit Holding Register */
+#define REG_TWI1_RPR  (*(RwReg*)0x40090100U) /**< \brief (TWI1) Receive Pointer Register */
+#define REG_TWI1_RCR  (*(RwReg*)0x40090104U) /**< \brief (TWI1) Receive Counter Register */
+#define REG_TWI1_TPR  (*(RwReg*)0x40090108U) /**< \brief (TWI1) Transmit Pointer Register */
+#define REG_TWI1_TCR  (*(RwReg*)0x4009010CU) /**< \brief (TWI1) Transmit Counter Register */
+#define REG_TWI1_RNPR (*(RwReg*)0x40090110U) /**< \brief (TWI1) Receive Next Pointer Register */
+#define REG_TWI1_RNCR (*(RwReg*)0x40090114U) /**< \brief (TWI1) Receive Next Counter Register */
+#define REG_TWI1_TNPR (*(RwReg*)0x40090118U) /**< \brief (TWI1) Transmit Next Pointer Register */
+#define REG_TWI1_TNCR (*(RwReg*)0x4009011CU) /**< \brief (TWI1) Transmit Next Counter Register */
+#define REG_TWI1_PTCR (*(WoReg*)0x40090120U) /**< \brief (TWI1) Transfer Control Register */
+#define REG_TWI1_PTSR (*(RoReg*)0x40090124U) /**< \brief (TWI1) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_TWI1_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_uart.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_uart.h
new file mode 100644
index 000000000..0bbf0ce65
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_uart.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_UART_INSTANCE_
+#define _SAM3XA_UART_INSTANCE_
+
+/* ========== Register definition for UART peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_UART_CR            (0x400E0800U) /**< \brief (UART) Control Register */
+#define REG_UART_MR            (0x400E0804U) /**< \brief (UART) Mode Register */
+#define REG_UART_IER           (0x400E0808U) /**< \brief (UART) Interrupt Enable Register */
+#define REG_UART_IDR           (0x400E080CU) /**< \brief (UART) Interrupt Disable Register */
+#define REG_UART_IMR           (0x400E0810U) /**< \brief (UART) Interrupt Mask Register */
+#define REG_UART_SR            (0x400E0814U) /**< \brief (UART) Status Register */
+#define REG_UART_RHR           (0x400E0818U) /**< \brief (UART) Receive Holding Register */
+#define REG_UART_THR           (0x400E081CU) /**< \brief (UART) Transmit Holding Register */
+#define REG_UART_BRGR          (0x400E0820U) /**< \brief (UART) Baud Rate Generator Register */
+#define REG_UART_RPR           (0x400E0900U) /**< \brief (UART) Receive Pointer Register */
+#define REG_UART_RCR           (0x400E0904U) /**< \brief (UART) Receive Counter Register */
+#define REG_UART_TPR           (0x400E0908U) /**< \brief (UART) Transmit Pointer Register */
+#define REG_UART_TCR           (0x400E090CU) /**< \brief (UART) Transmit Counter Register */
+#define REG_UART_RNPR          (0x400E0910U) /**< \brief (UART) Receive Next Pointer Register */
+#define REG_UART_RNCR          (0x400E0914U) /**< \brief (UART) Receive Next Counter Register */
+#define REG_UART_TNPR          (0x400E0918U) /**< \brief (UART) Transmit Next Pointer Register */
+#define REG_UART_TNCR          (0x400E091CU) /**< \brief (UART) Transmit Next Counter Register */
+#define REG_UART_PTCR          (0x400E0920U) /**< \brief (UART) Transfer Control Register */
+#define REG_UART_PTSR          (0x400E0924U) /**< \brief (UART) Transfer Status Register */
+#else
+#define REG_UART_CR   (*(WoReg*)0x400E0800U) /**< \brief (UART) Control Register */
+#define REG_UART_MR   (*(RwReg*)0x400E0804U) /**< \brief (UART) Mode Register */
+#define REG_UART_IER  (*(WoReg*)0x400E0808U) /**< \brief (UART) Interrupt Enable Register */
+#define REG_UART_IDR  (*(WoReg*)0x400E080CU) /**< \brief (UART) Interrupt Disable Register */
+#define REG_UART_IMR  (*(RoReg*)0x400E0810U) /**< \brief (UART) Interrupt Mask Register */
+#define REG_UART_SR   (*(RoReg*)0x400E0814U) /**< \brief (UART) Status Register */
+#define REG_UART_RHR  (*(RoReg*)0x400E0818U) /**< \brief (UART) Receive Holding Register */
+#define REG_UART_THR  (*(WoReg*)0x400E081CU) /**< \brief (UART) Transmit Holding Register */
+#define REG_UART_BRGR (*(RwReg*)0x400E0820U) /**< \brief (UART) Baud Rate Generator Register */
+#define REG_UART_RPR  (*(RwReg*)0x400E0900U) /**< \brief (UART) Receive Pointer Register */
+#define REG_UART_RCR  (*(RwReg*)0x400E0904U) /**< \brief (UART) Receive Counter Register */
+#define REG_UART_TPR  (*(RwReg*)0x400E0908U) /**< \brief (UART) Transmit Pointer Register */
+#define REG_UART_TCR  (*(RwReg*)0x400E090CU) /**< \brief (UART) Transmit Counter Register */
+#define REG_UART_RNPR (*(RwReg*)0x400E0910U) /**< \brief (UART) Receive Next Pointer Register */
+#define REG_UART_RNCR (*(RwReg*)0x400E0914U) /**< \brief (UART) Receive Next Counter Register */
+#define REG_UART_TNPR (*(RwReg*)0x400E0918U) /**< \brief (UART) Transmit Next Pointer Register */
+#define REG_UART_TNCR (*(RwReg*)0x400E091CU) /**< \brief (UART) Transmit Next Counter Register */
+#define REG_UART_PTCR (*(WoReg*)0x400E0920U) /**< \brief (UART) Transfer Control Register */
+#define REG_UART_PTSR (*(RoReg*)0x400E0924U) /**< \brief (UART) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_UART_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_uotghs.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_uotghs.h
new file mode 100644
index 000000000..7d40f7601
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_uotghs.h
@@ -0,0 +1,234 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_UOTGHS_INSTANCE_
+#define _SAM3XA_UOTGHS_INSTANCE_
+
+/* ========== Register definition for UOTGHS peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_UOTGHS_DEVCTRL                 (0x400AC000U) /**< \brief (UOTGHS) Device General Control Register */
+#define REG_UOTGHS_DEVISR                  (0x400AC004U) /**< \brief (UOTGHS) Device Global Interrupt Status Register */
+#define REG_UOTGHS_DEVICR                  (0x400AC008U) /**< \brief (UOTGHS) Device Global Interrupt Clear Register */
+#define REG_UOTGHS_DEVIFR                  (0x400AC00CU) /**< \brief (UOTGHS) Device Global Interrupt Set Register */
+#define REG_UOTGHS_DEVIMR                  (0x400AC010U) /**< \brief (UOTGHS) Device Global Interrupt Mask Register */
+#define REG_UOTGHS_DEVIDR                  (0x400AC014U) /**< \brief (UOTGHS) Device Global Interrupt Disable Register */
+#define REG_UOTGHS_DEVIER                  (0x400AC018U) /**< \brief (UOTGHS) Device Global Interrupt Enable Register */
+#define REG_UOTGHS_DEVEPT                  (0x400AC01CU) /**< \brief (UOTGHS) Device Endpoint Register */
+#define REG_UOTGHS_DEVFNUM                 (0x400AC020U) /**< \brief (UOTGHS) Device Frame Number Register */
+#define REG_UOTGHS_DEVEPTCFG               (0x400AC100U) /**< \brief (UOTGHS) Device Endpoint Configuration Register (n = 0) */
+#define REG_UOTGHS_DEVEPTISR               (0x400AC130U) /**< \brief (UOTGHS) Device Endpoint Status Register (n = 0) */
+#define REG_UOTGHS_DEVEPTICR               (0x400AC160U) /**< \brief (UOTGHS) Device Endpoint Clear Register (n = 0) */
+#define REG_UOTGHS_DEVEPTIFR               (0x400AC190U) /**< \brief (UOTGHS) Device Endpoint Set Register (n = 0) */
+#define REG_UOTGHS_DEVEPTIMR               (0x400AC1C0U) /**< \brief (UOTGHS) Device Endpoint Mask Register (n = 0) */
+#define REG_UOTGHS_DEVEPTIER               (0x400AC1F0U) /**< \brief (UOTGHS) Device Endpoint Enable Register (n = 0) */
+#define REG_UOTGHS_DEVEPTIDR               (0x400AC220U) /**< \brief (UOTGHS) Device Endpoint Disable Register (n = 0) */
+#define REG_UOTGHS_DEVDMANXTDSC1           (0x400AC310U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 1) */
+#define REG_UOTGHS_DEVDMAADDRESS1          (0x400AC314U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 1) */
+#define REG_UOTGHS_DEVDMACONTROL1          (0x400AC318U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 1) */
+#define REG_UOTGHS_DEVDMASTATUS1           (0x400AC31CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 1) */
+#define REG_UOTGHS_DEVDMANXTDSC2           (0x400AC320U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 2) */
+#define REG_UOTGHS_DEVDMAADDRESS2          (0x400AC324U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 2) */
+#define REG_UOTGHS_DEVDMACONTROL2          (0x400AC328U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 2) */
+#define REG_UOTGHS_DEVDMASTATUS2           (0x400AC32CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 2) */
+#define REG_UOTGHS_DEVDMANXTDSC3           (0x400AC330U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 3) */
+#define REG_UOTGHS_DEVDMAADDRESS3          (0x400AC334U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 3) */
+#define REG_UOTGHS_DEVDMACONTROL3          (0x400AC338U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 3) */
+#define REG_UOTGHS_DEVDMASTATUS3           (0x400AC33CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 3) */
+#define REG_UOTGHS_DEVDMANXTDSC4           (0x400AC340U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 4) */
+#define REG_UOTGHS_DEVDMAADDRESS4          (0x400AC344U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 4) */
+#define REG_UOTGHS_DEVDMACONTROL4          (0x400AC348U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 4) */
+#define REG_UOTGHS_DEVDMASTATUS4           (0x400AC34CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 4) */
+#define REG_UOTGHS_DEVDMANXTDSC5           (0x400AC350U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 5) */
+#define REG_UOTGHS_DEVDMAADDRESS5          (0x400AC354U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 5) */
+#define REG_UOTGHS_DEVDMACONTROL5          (0x400AC358U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 5) */
+#define REG_UOTGHS_DEVDMASTATUS5           (0x400AC35CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 5) */
+#define REG_UOTGHS_DEVDMANXTDSC6           (0x400AC360U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 6) */
+#define REG_UOTGHS_DEVDMAADDRESS6          (0x400AC364U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 6) */
+#define REG_UOTGHS_DEVDMACONTROL6          (0x400AC368U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 6) */
+#define REG_UOTGHS_DEVDMASTATUS6           (0x400AC36CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 6) */
+#define REG_UOTGHS_DEVDMANXTDSC7           (0x400AC370U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 7) */
+#define REG_UOTGHS_DEVDMAADDRESS7          (0x400AC374U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 7) */
+#define REG_UOTGHS_DEVDMACONTROL7          (0x400AC378U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 7) */
+#define REG_UOTGHS_DEVDMASTATUS7           (0x400AC37CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 7) */
+#define REG_UOTGHS_HSTCTRL                 (0x400AC400U) /**< \brief (UOTGHS) Host General Control Register */
+#define REG_UOTGHS_HSTISR                  (0x400AC404U) /**< \brief (UOTGHS) Host Global Interrupt Status Register */
+#define REG_UOTGHS_HSTICR                  (0x400AC408U) /**< \brief (UOTGHS) Host Global Interrupt Clear Register */
+#define REG_UOTGHS_HSTIFR                  (0x400AC40CU) /**< \brief (UOTGHS) Host Global Interrupt Set Register */
+#define REG_UOTGHS_HSTIMR                  (0x400AC410U) /**< \brief (UOTGHS) Host Global Interrupt Mask Register */
+#define REG_UOTGHS_HSTIDR                  (0x400AC414U) /**< \brief (UOTGHS) Host Global Interrupt Disable Register */
+#define REG_UOTGHS_HSTIER                  (0x400AC418U) /**< \brief (UOTGHS) Host Global Interrupt Enable Register */
+#define REG_UOTGHS_HSTPIP                  (0x400AC41CU) /**< \brief (UOTGHS) Host Pipe Register */
+#define REG_UOTGHS_HSTFNUM                 (0x400AC420U) /**< \brief (UOTGHS) Host Frame Number Register */
+#define REG_UOTGHS_HSTADDR1                (0x400AC424U) /**< \brief (UOTGHS) Host Address 1 Register */
+#define REG_UOTGHS_HSTADDR2                (0x400AC428U) /**< \brief (UOTGHS) Host Address 2 Register */
+#define REG_UOTGHS_HSTADDR3                (0x400AC42CU) /**< \brief (UOTGHS) Host Address 3 Register */
+#define REG_UOTGHS_HSTPIPCFG               (0x400AC500U) /**< \brief (UOTGHS) Host Pipe Configuration Register (n = 0) */
+#define REG_UOTGHS_HSTPIPISR               (0x400AC530U) /**< \brief (UOTGHS) Host Pipe Status Register (n = 0) */
+#define REG_UOTGHS_HSTPIPICR               (0x400AC560U) /**< \brief (UOTGHS) Host Pipe Clear Register (n = 0) */
+#define REG_UOTGHS_HSTPIPIFR               (0x400AC590U) /**< \brief (UOTGHS) Host Pipe Set Register (n = 0) */
+#define REG_UOTGHS_HSTPIPIMR               (0x400AC5C0U) /**< \brief (UOTGHS) Host Pipe Mask Register (n = 0) */
+#define REG_UOTGHS_HSTPIPIER               (0x400AC5F0U) /**< \brief (UOTGHS) Host Pipe Enable Register (n = 0) */
+#define REG_UOTGHS_HSTPIPIDR               (0x400AC620U) /**< \brief (UOTGHS) Host Pipe Disable Register (n = 0) */
+#define REG_UOTGHS_HSTPIPINRQ              (0x400AC650U) /**< \brief (UOTGHS) Host Pipe IN Request Register (n = 0) */
+#define REG_UOTGHS_HSTPIPERR               (0x400AC680U) /**< \brief (UOTGHS) Host Pipe Error Register (n = 0) */
+#define REG_UOTGHS_HSTDMANXTDSC1           (0x400AC710U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 1) */
+#define REG_UOTGHS_HSTDMAADDRESS1          (0x400AC714U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 1) */
+#define REG_UOTGHS_HSTDMACONTROL1          (0x400AC718U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 1) */
+#define REG_UOTGHS_HSTDMASTATUS1           (0x400AC71CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 1) */
+#define REG_UOTGHS_HSTDMANXTDSC2           (0x400AC720U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 2) */
+#define REG_UOTGHS_HSTDMAADDRESS2          (0x400AC724U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 2) */
+#define REG_UOTGHS_HSTDMACONTROL2          (0x400AC728U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 2) */
+#define REG_UOTGHS_HSTDMASTATUS2           (0x400AC72CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 2) */
+#define REG_UOTGHS_HSTDMANXTDSC3           (0x400AC730U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 3) */
+#define REG_UOTGHS_HSTDMAADDRESS3          (0x400AC734U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 3) */
+#define REG_UOTGHS_HSTDMACONTROL3          (0x400AC738U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 3) */
+#define REG_UOTGHS_HSTDMASTATUS3           (0x400AC73CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 3) */
+#define REG_UOTGHS_HSTDMANXTDSC4           (0x400AC740U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 4) */
+#define REG_UOTGHS_HSTDMAADDRESS4          (0x400AC744U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 4) */
+#define REG_UOTGHS_HSTDMACONTROL4          (0x400AC748U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 4) */
+#define REG_UOTGHS_HSTDMASTATUS4           (0x400AC74CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 4) */
+#define REG_UOTGHS_HSTDMANXTDSC5           (0x400AC750U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 5) */
+#define REG_UOTGHS_HSTDMAADDRESS5          (0x400AC754U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 5) */
+#define REG_UOTGHS_HSTDMACONTROL5          (0x400AC758U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 5) */
+#define REG_UOTGHS_HSTDMASTATUS5           (0x400AC75CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 5) */
+#define REG_UOTGHS_HSTDMANXTDSC6           (0x400AC760U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 6) */
+#define REG_UOTGHS_HSTDMAADDRESS6          (0x400AC764U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 6) */
+#define REG_UOTGHS_HSTDMACONTROL6          (0x400AC768U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 6) */
+#define REG_UOTGHS_HSTDMASTATUS6           (0x400AC76CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 6) */
+#define REG_UOTGHS_HSTDMANXTDSC7           (0x400AC770U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 7) */
+#define REG_UOTGHS_HSTDMAADDRESS7          (0x400AC774U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 7) */
+#define REG_UOTGHS_HSTDMACONTROL7          (0x400AC778U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 7) */
+#define REG_UOTGHS_HSTDMASTATUS7           (0x400AC77CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 7) */
+#define REG_UOTGHS_CTRL                    (0x400AC800U) /**< \brief (UOTGHS) General Control Register */
+#define REG_UOTGHS_SR                      (0x400AC804U) /**< \brief (UOTGHS) General Status Register */
+#define REG_UOTGHS_SCR                     (0x400AC808U) /**< \brief (UOTGHS) General Status Clear Register */
+#define REG_UOTGHS_SFR                     (0x400AC80CU) /**< \brief (UOTGHS) General Status Set Register */
+#define REG_UOTGHS_FSM                     (0x400AC82CU) /**< \brief (UOTGHS) General Finite State Machine Register */
+#else
+#define REG_UOTGHS_DEVCTRL        (*(RwReg*)0x400AC000U) /**< \brief (UOTGHS) Device General Control Register */
+#define REG_UOTGHS_DEVISR         (*(RoReg*)0x400AC004U) /**< \brief (UOTGHS) Device Global Interrupt Status Register */
+#define REG_UOTGHS_DEVICR         (*(WoReg*)0x400AC008U) /**< \brief (UOTGHS) Device Global Interrupt Clear Register */
+#define REG_UOTGHS_DEVIFR         (*(WoReg*)0x400AC00CU) /**< \brief (UOTGHS) Device Global Interrupt Set Register */
+#define REG_UOTGHS_DEVIMR         (*(RoReg*)0x400AC010U) /**< \brief (UOTGHS) Device Global Interrupt Mask Register */
+#define REG_UOTGHS_DEVIDR         (*(WoReg*)0x400AC014U) /**< \brief (UOTGHS) Device Global Interrupt Disable Register */
+#define REG_UOTGHS_DEVIER         (*(WoReg*)0x400AC018U) /**< \brief (UOTGHS) Device Global Interrupt Enable Register */
+#define REG_UOTGHS_DEVEPT         (*(RwReg*)0x400AC01CU) /**< \brief (UOTGHS) Device Endpoint Register */
+#define REG_UOTGHS_DEVFNUM        (*(RoReg*)0x400AC020U) /**< \brief (UOTGHS) Device Frame Number Register */
+#define REG_UOTGHS_DEVEPTCFG      (*(RwReg*)0x400AC100U) /**< \brief (UOTGHS) Device Endpoint Configuration Register (n = 0) */
+#define REG_UOTGHS_DEVEPTISR      (*(RoReg*)0x400AC130U) /**< \brief (UOTGHS) Device Endpoint Status Register (n = 0) */
+#define REG_UOTGHS_DEVEPTICR      (*(WoReg*)0x400AC160U) /**< \brief (UOTGHS) Device Endpoint Clear Register (n = 0) */
+#define REG_UOTGHS_DEVEPTIFR      (*(WoReg*)0x400AC190U) /**< \brief (UOTGHS) Device Endpoint Set Register (n = 0) */
+#define REG_UOTGHS_DEVEPTIMR      (*(RoReg*)0x400AC1C0U) /**< \brief (UOTGHS) Device Endpoint Mask Register (n = 0) */
+#define REG_UOTGHS_DEVEPTIER      (*(WoReg*)0x400AC1F0U) /**< \brief (UOTGHS) Device Endpoint Enable Register (n = 0) */
+#define REG_UOTGHS_DEVEPTIDR      (*(WoReg*)0x400AC220U) /**< \brief (UOTGHS) Device Endpoint Disable Register (n = 0) */
+#define REG_UOTGHS_DEVDMANXTDSC1  (*(RwReg*)0x400AC310U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 1) */
+#define REG_UOTGHS_DEVDMAADDRESS1 (*(RwReg*)0x400AC314U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 1) */
+#define REG_UOTGHS_DEVDMACONTROL1 (*(RwReg*)0x400AC318U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 1) */
+#define REG_UOTGHS_DEVDMASTATUS1  (*(RwReg*)0x400AC31CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 1) */
+#define REG_UOTGHS_DEVDMANXTDSC2  (*(RwReg*)0x400AC320U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 2) */
+#define REG_UOTGHS_DEVDMAADDRESS2 (*(RwReg*)0x400AC324U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 2) */
+#define REG_UOTGHS_DEVDMACONTROL2 (*(RwReg*)0x400AC328U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 2) */
+#define REG_UOTGHS_DEVDMASTATUS2  (*(RwReg*)0x400AC32CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 2) */
+#define REG_UOTGHS_DEVDMANXTDSC3  (*(RwReg*)0x400AC330U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 3) */
+#define REG_UOTGHS_DEVDMAADDRESS3 (*(RwReg*)0x400AC334U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 3) */
+#define REG_UOTGHS_DEVDMACONTROL3 (*(RwReg*)0x400AC338U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 3) */
+#define REG_UOTGHS_DEVDMASTATUS3  (*(RwReg*)0x400AC33CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 3) */
+#define REG_UOTGHS_DEVDMANXTDSC4  (*(RwReg*)0x400AC340U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 4) */
+#define REG_UOTGHS_DEVDMAADDRESS4 (*(RwReg*)0x400AC344U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 4) */
+#define REG_UOTGHS_DEVDMACONTROL4 (*(RwReg*)0x400AC348U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 4) */
+#define REG_UOTGHS_DEVDMASTATUS4  (*(RwReg*)0x400AC34CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 4) */
+#define REG_UOTGHS_DEVDMANXTDSC5  (*(RwReg*)0x400AC350U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 5) */
+#define REG_UOTGHS_DEVDMAADDRESS5 (*(RwReg*)0x400AC354U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 5) */
+#define REG_UOTGHS_DEVDMACONTROL5 (*(RwReg*)0x400AC358U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 5) */
+#define REG_UOTGHS_DEVDMASTATUS5  (*(RwReg*)0x400AC35CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 5) */
+#define REG_UOTGHS_DEVDMANXTDSC6  (*(RwReg*)0x400AC360U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 6) */
+#define REG_UOTGHS_DEVDMAADDRESS6 (*(RwReg*)0x400AC364U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 6) */
+#define REG_UOTGHS_DEVDMACONTROL6 (*(RwReg*)0x400AC368U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 6) */
+#define REG_UOTGHS_DEVDMASTATUS6  (*(RwReg*)0x400AC36CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 6) */
+#define REG_UOTGHS_DEVDMANXTDSC7  (*(RwReg*)0x400AC370U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 7) */
+#define REG_UOTGHS_DEVDMAADDRESS7 (*(RwReg*)0x400AC374U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 7) */
+#define REG_UOTGHS_DEVDMACONTROL7 (*(RwReg*)0x400AC378U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 7) */
+#define REG_UOTGHS_DEVDMASTATUS7  (*(RwReg*)0x400AC37CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 7) */
+#define REG_UOTGHS_HSTCTRL        (*(RwReg*)0x400AC400U) /**< \brief (UOTGHS) Host General Control Register */
+#define REG_UOTGHS_HSTISR         (*(RoReg*)0x400AC404U) /**< \brief (UOTGHS) Host Global Interrupt Status Register */
+#define REG_UOTGHS_HSTICR         (*(WoReg*)0x400AC408U) /**< \brief (UOTGHS) Host Global Interrupt Clear Register */
+#define REG_UOTGHS_HSTIFR         (*(WoReg*)0x400AC40CU) /**< \brief (UOTGHS) Host Global Interrupt Set Register */
+#define REG_UOTGHS_HSTIMR         (*(RoReg*)0x400AC410U) /**< \brief (UOTGHS) Host Global Interrupt Mask Register */
+#define REG_UOTGHS_HSTIDR         (*(WoReg*)0x400AC414U) /**< \brief (UOTGHS) Host Global Interrupt Disable Register */
+#define REG_UOTGHS_HSTIER         (*(WoReg*)0x400AC418U) /**< \brief (UOTGHS) Host Global Interrupt Enable Register */
+#define REG_UOTGHS_HSTPIP         (*(RwReg*)0x400AC41CU) /**< \brief (UOTGHS) Host Pipe Register */
+#define REG_UOTGHS_HSTFNUM        (*(RwReg*)0x400AC420U) /**< \brief (UOTGHS) Host Frame Number Register */
+#define REG_UOTGHS_HSTADDR1       (*(RwReg*)0x400AC424U) /**< \brief (UOTGHS) Host Address 1 Register */
+#define REG_UOTGHS_HSTADDR2       (*(RwReg*)0x400AC428U) /**< \brief (UOTGHS) Host Address 2 Register */
+#define REG_UOTGHS_HSTADDR3       (*(RwReg*)0x400AC42CU) /**< \brief (UOTGHS) Host Address 3 Register */
+#define REG_UOTGHS_HSTPIPCFG      (*(RwReg*)0x400AC500U) /**< \brief (UOTGHS) Host Pipe Configuration Register (n = 0) */
+#define REG_UOTGHS_HSTPIPISR      (*(RoReg*)0x400AC530U) /**< \brief (UOTGHS) Host Pipe Status Register (n = 0) */
+#define REG_UOTGHS_HSTPIPICR      (*(WoReg*)0x400AC560U) /**< \brief (UOTGHS) Host Pipe Clear Register (n = 0) */
+#define REG_UOTGHS_HSTPIPIFR      (*(WoReg*)0x400AC590U) /**< \brief (UOTGHS) Host Pipe Set Register (n = 0) */
+#define REG_UOTGHS_HSTPIPIMR      (*(RoReg*)0x400AC5C0U) /**< \brief (UOTGHS) Host Pipe Mask Register (n = 0) */
+#define REG_UOTGHS_HSTPIPIER      (*(WoReg*)0x400AC5F0U) /**< \brief (UOTGHS) Host Pipe Enable Register (n = 0) */
+#define REG_UOTGHS_HSTPIPIDR      (*(WoReg*)0x400AC620U) /**< \brief (UOTGHS) Host Pipe Disable Register (n = 0) */
+#define REG_UOTGHS_HSTPIPINRQ     (*(RwReg*)0x400AC650U) /**< \brief (UOTGHS) Host Pipe IN Request Register (n = 0) */
+#define REG_UOTGHS_HSTPIPERR      (*(RwReg*)0x400AC680U) /**< \brief (UOTGHS) Host Pipe Error Register (n = 0) */
+#define REG_UOTGHS_HSTDMANXTDSC1  (*(RwReg*)0x400AC710U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 1) */
+#define REG_UOTGHS_HSTDMAADDRESS1 (*(RwReg*)0x400AC714U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 1) */
+#define REG_UOTGHS_HSTDMACONTROL1 (*(RwReg*)0x400AC718U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 1) */
+#define REG_UOTGHS_HSTDMASTATUS1  (*(RwReg*)0x400AC71CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 1) */
+#define REG_UOTGHS_HSTDMANXTDSC2  (*(RwReg*)0x400AC720U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 2) */
+#define REG_UOTGHS_HSTDMAADDRESS2 (*(RwReg*)0x400AC724U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 2) */
+#define REG_UOTGHS_HSTDMACONTROL2 (*(RwReg*)0x400AC728U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 2) */
+#define REG_UOTGHS_HSTDMASTATUS2  (*(RwReg*)0x400AC72CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 2) */
+#define REG_UOTGHS_HSTDMANXTDSC3  (*(RwReg*)0x400AC730U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 3) */
+#define REG_UOTGHS_HSTDMAADDRESS3 (*(RwReg*)0x400AC734U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 3) */
+#define REG_UOTGHS_HSTDMACONTROL3 (*(RwReg*)0x400AC738U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 3) */
+#define REG_UOTGHS_HSTDMASTATUS3  (*(RwReg*)0x400AC73CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 3) */
+#define REG_UOTGHS_HSTDMANXTDSC4  (*(RwReg*)0x400AC740U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 4) */
+#define REG_UOTGHS_HSTDMAADDRESS4 (*(RwReg*)0x400AC744U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 4) */
+#define REG_UOTGHS_HSTDMACONTROL4 (*(RwReg*)0x400AC748U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 4) */
+#define REG_UOTGHS_HSTDMASTATUS4  (*(RwReg*)0x400AC74CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 4) */
+#define REG_UOTGHS_HSTDMANXTDSC5  (*(RwReg*)0x400AC750U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 5) */
+#define REG_UOTGHS_HSTDMAADDRESS5 (*(RwReg*)0x400AC754U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 5) */
+#define REG_UOTGHS_HSTDMACONTROL5 (*(RwReg*)0x400AC758U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 5) */
+#define REG_UOTGHS_HSTDMASTATUS5  (*(RwReg*)0x400AC75CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 5) */
+#define REG_UOTGHS_HSTDMANXTDSC6  (*(RwReg*)0x400AC760U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 6) */
+#define REG_UOTGHS_HSTDMAADDRESS6 (*(RwReg*)0x400AC764U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 6) */
+#define REG_UOTGHS_HSTDMACONTROL6 (*(RwReg*)0x400AC768U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 6) */
+#define REG_UOTGHS_HSTDMASTATUS6  (*(RwReg*)0x400AC76CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 6) */
+#define REG_UOTGHS_HSTDMANXTDSC7  (*(RwReg*)0x400AC770U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 7) */
+#define REG_UOTGHS_HSTDMAADDRESS7 (*(RwReg*)0x400AC774U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 7) */
+#define REG_UOTGHS_HSTDMACONTROL7 (*(RwReg*)0x400AC778U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 7) */
+#define REG_UOTGHS_HSTDMASTATUS7  (*(RwReg*)0x400AC77CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 7) */
+#define REG_UOTGHS_CTRL           (*(RwReg*)0x400AC800U) /**< \brief (UOTGHS) General Control Register */
+#define REG_UOTGHS_SR             (*(RoReg*)0x400AC804U) /**< \brief (UOTGHS) General Status Register */
+#define REG_UOTGHS_SCR            (*(WoReg*)0x400AC808U) /**< \brief (UOTGHS) General Status Clear Register */
+#define REG_UOTGHS_SFR            (*(WoReg*)0x400AC80CU) /**< \brief (UOTGHS) General Status Set Register */
+#define REG_UOTGHS_FSM            (*(RoReg*)0x400AC82CU) /**< \brief (UOTGHS) General Finite State Machine Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_UOTGHS_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_usart0.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_usart0.h
new file mode 100644
index 000000000..5f9d8b2b1
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_usart0.h
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_USART0_INSTANCE_
+#define _SAM3XA_USART0_INSTANCE_
+
+/* ========== Register definition for USART0 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_USART0_CR          (0x40098000U) /**< \brief (USART0) Control Register */
+#define REG_USART0_MR          (0x40098004U) /**< \brief (USART0) Mode Register */
+#define REG_USART0_IER          (0x40098008U) /**< \brief (USART0) Interrupt Enable Register */
+#define REG_USART0_IDR          (0x4009800CU) /**< \brief (USART0) Interrupt Disable Register */
+#define REG_USART0_IMR          (0x40098010U) /**< \brief (USART0) Interrupt Mask Register */
+#define REG_USART0_CSR          (0x40098014U) /**< \brief (USART0) Channel Status Register */
+#define REG_USART0_RHR          (0x40098018U) /**< \brief (USART0) Receiver Holding Register */
+#define REG_USART0_THR          (0x4009801CU) /**< \brief (USART0) Transmitter Holding Register */
+#define REG_USART0_BRGR          (0x40098020U) /**< \brief (USART0) Baud Rate Generator Register */
+#define REG_USART0_RTOR          (0x40098024U) /**< \brief (USART0) Receiver Time-out Register */
+#define REG_USART0_TTGR          (0x40098028U) /**< \brief (USART0) Transmitter Timeguard Register */
+#define REG_USART0_FIDI          (0x40098040U) /**< \brief (USART0) FI DI Ratio Register */
+#define REG_USART0_NER          (0x40098044U) /**< \brief (USART0) Number of Errors Register */
+#define REG_USART0_IF          (0x4009804CU) /**< \brief (USART0) IrDA Filter Register */
+#define REG_USART0_MAN          (0x40098050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
+#define REG_USART0_LINMR          (0x40098054U) /**< \brief (USART0) LIN Mode Register */
+#define REG_USART0_LINIR          (0x40098058U) /**< \brief (USART0) LIN Identifier Register */
+#define REG_USART0_WPMR          (0x400980E4U) /**< \brief (USART0) Write Protect Mode Register */
+#define REG_USART0_WPSR          (0x400980E8U) /**< \brief (USART0) Write Protect Status Register */
+#define REG_USART0_RPR          (0x40098100U) /**< \brief (USART0) Receive Pointer Register */
+#define REG_USART0_RCR          (0x40098104U) /**< \brief (USART0) Receive Counter Register */
+#define REG_USART0_TPR          (0x40098108U) /**< \brief (USART0) Transmit Pointer Register */
+#define REG_USART0_TCR          (0x4009810CU) /**< \brief (USART0) Transmit Counter Register */
+#define REG_USART0_RNPR          (0x40098110U) /**< \brief (USART0) Receive Next Pointer Register */
+#define REG_USART0_RNCR          (0x40098114U) /**< \brief (USART0) Receive Next Counter Register */
+#define REG_USART0_TNPR          (0x40098118U) /**< \brief (USART0) Transmit Next Pointer Register */
+#define REG_USART0_TNCR          (0x4009811CU) /**< \brief (USART0) Transmit Next Counter Register */
+#define REG_USART0_PTCR          (0x40098120U) /**< \brief (USART0) Transfer Control Register */
+#define REG_USART0_PTSR          (0x40098124U) /**< \brief (USART0) Transfer Status Register */
+#else
+#define REG_USART0_CR (*(WoReg*)0x40098000U) /**< \brief (USART0) Control Register */
+#define REG_USART0_MR (*(RwReg*)0x40098004U) /**< \brief (USART0) Mode Register */
+#define REG_USART0_IER (*(WoReg*)0x40098008U) /**< \brief (USART0) Interrupt Enable Register */
+#define REG_USART0_IDR (*(WoReg*)0x4009800CU) /**< \brief (USART0) Interrupt Disable Register */
+#define REG_USART0_IMR (*(RoReg*)0x40098010U) /**< \brief (USART0) Interrupt Mask Register */
+#define REG_USART0_CSR (*(RoReg*)0x40098014U) /**< \brief (USART0) Channel Status Register */
+#define REG_USART0_RHR (*(RoReg*)0x40098018U) /**< \brief (USART0) Receiver Holding Register */
+#define REG_USART0_THR (*(WoReg*)0x4009801CU) /**< \brief (USART0) Transmitter Holding Register */
+#define REG_USART0_BRGR (*(RwReg*)0x40098020U) /**< \brief (USART0) Baud Rate Generator Register */
+#define REG_USART0_RTOR (*(RwReg*)0x40098024U) /**< \brief (USART0) Receiver Time-out Register */
+#define REG_USART0_TTGR (*(RwReg*)0x40098028U) /**< \brief (USART0) Transmitter Timeguard Register */
+#define REG_USART0_FIDI (*(RwReg*)0x40098040U) /**< \brief (USART0) FI DI Ratio Register */
+#define REG_USART0_NER (*(RoReg*)0x40098044U) /**< \brief (USART0) Number of Errors Register */
+#define REG_USART0_IF (*(RwReg*)0x4009804CU) /**< \brief (USART0) IrDA Filter Register */
+#define REG_USART0_MAN (*(RwReg*)0x40098050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
+#define REG_USART0_LINMR (*(RwReg*)0x40098054U) /**< \brief (USART0) LIN Mode Register */
+#define REG_USART0_LINIR (*(RwReg*)0x40098058U) /**< \brief (USART0) LIN Identifier Register */
+#define REG_USART0_WPMR (*(RwReg*)0x400980E4U) /**< \brief (USART0) Write Protect Mode Register */
+#define REG_USART0_WPSR (*(RoReg*)0x400980E8U) /**< \brief (USART0) Write Protect Status Register */
+#define REG_USART0_RPR (*(RwReg*)0x40098100U) /**< \brief (USART0) Receive Pointer Register */
+#define REG_USART0_RCR (*(RwReg*)0x40098104U) /**< \brief (USART0) Receive Counter Register */
+#define REG_USART0_TPR (*(RwReg*)0x40098108U) /**< \brief (USART0) Transmit Pointer Register */
+#define REG_USART0_TCR (*(RwReg*)0x4009810CU) /**< \brief (USART0) Transmit Counter Register */
+#define REG_USART0_RNPR (*(RwReg*)0x40098110U) /**< \brief (USART0) Receive Next Pointer Register */
+#define REG_USART0_RNCR (*(RwReg*)0x40098114U) /**< \brief (USART0) Receive Next Counter Register */
+#define REG_USART0_TNPR (*(RwReg*)0x40098118U) /**< \brief (USART0) Transmit Next Pointer Register */
+#define REG_USART0_TNCR (*(RwReg*)0x4009811CU) /**< \brief (USART0) Transmit Next Counter Register */
+#define REG_USART0_PTCR (*(WoReg*)0x40098120U) /**< \brief (USART0) Transfer Control Register */
+#define REG_USART0_PTSR (*(RoReg*)0x40098124U) /**< \brief (USART0) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_USART0_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_usart1.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_usart1.h
new file mode 100644
index 000000000..2574dccd1
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_usart1.h
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_USART1_INSTANCE_
+#define _SAM3XA_USART1_INSTANCE_
+
+/* ========== Register definition for USART1 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_USART1_CR          (0x4009C000U) /**< \brief (USART1) Control Register */
+#define REG_USART1_MR          (0x4009C004U) /**< \brief (USART1) Mode Register */
+#define REG_USART1_IER          (0x4009C008U) /**< \brief (USART1) Interrupt Enable Register */
+#define REG_USART1_IDR          (0x4009C00CU) /**< \brief (USART1) Interrupt Disable Register */
+#define REG_USART1_IMR          (0x4009C010U) /**< \brief (USART1) Interrupt Mask Register */
+#define REG_USART1_CSR          (0x4009C014U) /**< \brief (USART1) Channel Status Register */
+#define REG_USART1_RHR          (0x4009C018U) /**< \brief (USART1) Receiver Holding Register */
+#define REG_USART1_THR          (0x4009C01CU) /**< \brief (USART1) Transmitter Holding Register */
+#define REG_USART1_BRGR          (0x4009C020U) /**< \brief (USART1) Baud Rate Generator Register */
+#define REG_USART1_RTOR          (0x4009C024U) /**< \brief (USART1) Receiver Time-out Register */
+#define REG_USART1_TTGR          (0x4009C028U) /**< \brief (USART1) Transmitter Timeguard Register */
+#define REG_USART1_FIDI          (0x4009C040U) /**< \brief (USART1) FI DI Ratio Register */
+#define REG_USART1_NER          (0x4009C044U) /**< \brief (USART1) Number of Errors Register */
+#define REG_USART1_IF          (0x4009C04CU) /**< \brief (USART1) IrDA Filter Register */
+#define REG_USART1_MAN          (0x4009C050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
+#define REG_USART1_LINMR          (0x4009C054U) /**< \brief (USART1) LIN Mode Register */
+#define REG_USART1_LINIR          (0x4009C058U) /**< \brief (USART1) LIN Identifier Register */
+#define REG_USART1_WPMR          (0x4009C0E4U) /**< \brief (USART1) Write Protect Mode Register */
+#define REG_USART1_WPSR          (0x4009C0E8U) /**< \brief (USART1) Write Protect Status Register */
+#define REG_USART1_RPR          (0x4009C100U) /**< \brief (USART1) Receive Pointer Register */
+#define REG_USART1_RCR          (0x4009C104U) /**< \brief (USART1) Receive Counter Register */
+#define REG_USART1_TPR          (0x4009C108U) /**< \brief (USART1) Transmit Pointer Register */
+#define REG_USART1_TCR          (0x4009C10CU) /**< \brief (USART1) Transmit Counter Register */
+#define REG_USART1_RNPR          (0x4009C110U) /**< \brief (USART1) Receive Next Pointer Register */
+#define REG_USART1_RNCR          (0x4009C114U) /**< \brief (USART1) Receive Next Counter Register */
+#define REG_USART1_TNPR          (0x4009C118U) /**< \brief (USART1) Transmit Next Pointer Register */
+#define REG_USART1_TNCR          (0x4009C11CU) /**< \brief (USART1) Transmit Next Counter Register */
+#define REG_USART1_PTCR          (0x4009C120U) /**< \brief (USART1) Transfer Control Register */
+#define REG_USART1_PTSR          (0x4009C124U) /**< \brief (USART1) Transfer Status Register */
+#else
+#define REG_USART1_CR (*(WoReg*)0x4009C000U) /**< \brief (USART1) Control Register */
+#define REG_USART1_MR (*(RwReg*)0x4009C004U) /**< \brief (USART1) Mode Register */
+#define REG_USART1_IER (*(WoReg*)0x4009C008U) /**< \brief (USART1) Interrupt Enable Register */
+#define REG_USART1_IDR (*(WoReg*)0x4009C00CU) /**< \brief (USART1) Interrupt Disable Register */
+#define REG_USART1_IMR (*(RoReg*)0x4009C010U) /**< \brief (USART1) Interrupt Mask Register */
+#define REG_USART1_CSR (*(RoReg*)0x4009C014U) /**< \brief (USART1) Channel Status Register */
+#define REG_USART1_RHR (*(RoReg*)0x4009C018U) /**< \brief (USART1) Receiver Holding Register */
+#define REG_USART1_THR (*(WoReg*)0x4009C01CU) /**< \brief (USART1) Transmitter Holding Register */
+#define REG_USART1_BRGR (*(RwReg*)0x4009C020U) /**< \brief (USART1) Baud Rate Generator Register */
+#define REG_USART1_RTOR (*(RwReg*)0x4009C024U) /**< \brief (USART1) Receiver Time-out Register */
+#define REG_USART1_TTGR (*(RwReg*)0x4009C028U) /**< \brief (USART1) Transmitter Timeguard Register */
+#define REG_USART1_FIDI (*(RwReg*)0x4009C040U) /**< \brief (USART1) FI DI Ratio Register */
+#define REG_USART1_NER (*(RoReg*)0x4009C044U) /**< \brief (USART1) Number of Errors Register */
+#define REG_USART1_IF (*(RwReg*)0x4009C04CU) /**< \brief (USART1) IrDA Filter Register */
+#define REG_USART1_MAN (*(RwReg*)0x4009C050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
+#define REG_USART1_LINMR (*(RwReg*)0x4009C054U) /**< \brief (USART1) LIN Mode Register */
+#define REG_USART1_LINIR (*(RwReg*)0x4009C058U) /**< \brief (USART1) LIN Identifier Register */
+#define REG_USART1_WPMR (*(RwReg*)0x4009C0E4U) /**< \brief (USART1) Write Protect Mode Register */
+#define REG_USART1_WPSR (*(RoReg*)0x4009C0E8U) /**< \brief (USART1) Write Protect Status Register */
+#define REG_USART1_RPR (*(RwReg*)0x4009C100U) /**< \brief (USART1) Receive Pointer Register */
+#define REG_USART1_RCR (*(RwReg*)0x4009C104U) /**< \brief (USART1) Receive Counter Register */
+#define REG_USART1_TPR (*(RwReg*)0x4009C108U) /**< \brief (USART1) Transmit Pointer Register */
+#define REG_USART1_TCR (*(RwReg*)0x4009C10CU) /**< \brief (USART1) Transmit Counter Register */
+#define REG_USART1_RNPR (*(RwReg*)0x4009C110U) /**< \brief (USART1) Receive Next Pointer Register */
+#define REG_USART1_RNCR (*(RwReg*)0x4009C114U) /**< \brief (USART1) Receive Next Counter Register */
+#define REG_USART1_TNPR (*(RwReg*)0x4009C118U) /**< \brief (USART1) Transmit Next Pointer Register */
+#define REG_USART1_TNCR (*(RwReg*)0x4009C11CU) /**< \brief (USART1) Transmit Next Counter Register */
+#define REG_USART1_PTCR (*(WoReg*)0x4009C120U) /**< \brief (USART1) Transfer Control Register */
+#define REG_USART1_PTSR (*(RoReg*)0x4009C124U) /**< \brief (USART1) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_USART1_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_usart2.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_usart2.h
new file mode 100644
index 000000000..cff7d4bdd
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_usart2.h
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_USART2_INSTANCE_
+#define _SAM3XA_USART2_INSTANCE_
+
+/* ========== Register definition for USART2 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_USART2_CR          (0x400A0000U) /**< \brief (USART2) Control Register */
+#define REG_USART2_MR          (0x400A0004U) /**< \brief (USART2) Mode Register */
+#define REG_USART2_IER          (0x400A0008U) /**< \brief (USART2) Interrupt Enable Register */
+#define REG_USART2_IDR          (0x400A000CU) /**< \brief (USART2) Interrupt Disable Register */
+#define REG_USART2_IMR          (0x400A0010U) /**< \brief (USART2) Interrupt Mask Register */
+#define REG_USART2_CSR          (0x400A0014U) /**< \brief (USART2) Channel Status Register */
+#define REG_USART2_RHR          (0x400A0018U) /**< \brief (USART2) Receiver Holding Register */
+#define REG_USART2_THR          (0x400A001CU) /**< \brief (USART2) Transmitter Holding Register */
+#define REG_USART2_BRGR          (0x400A0020U) /**< \brief (USART2) Baud Rate Generator Register */
+#define REG_USART2_RTOR          (0x400A0024U) /**< \brief (USART2) Receiver Time-out Register */
+#define REG_USART2_TTGR          (0x400A0028U) /**< \brief (USART2) Transmitter Timeguard Register */
+#define REG_USART2_FIDI          (0x400A0040U) /**< \brief (USART2) FI DI Ratio Register */
+#define REG_USART2_NER          (0x400A0044U) /**< \brief (USART2) Number of Errors Register */
+#define REG_USART2_IF          (0x400A004CU) /**< \brief (USART2) IrDA Filter Register */
+#define REG_USART2_MAN          (0x400A0050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
+#define REG_USART2_LINMR          (0x400A0054U) /**< \brief (USART2) LIN Mode Register */
+#define REG_USART2_LINIR          (0x400A0058U) /**< \brief (USART2) LIN Identifier Register */
+#define REG_USART2_WPMR          (0x400A00E4U) /**< \brief (USART2) Write Protect Mode Register */
+#define REG_USART2_WPSR          (0x400A00E8U) /**< \brief (USART2) Write Protect Status Register */
+#define REG_USART2_RPR          (0x400A0100U) /**< \brief (USART2) Receive Pointer Register */
+#define REG_USART2_RCR          (0x400A0104U) /**< \brief (USART2) Receive Counter Register */
+#define REG_USART2_TPR          (0x400A0108U) /**< \brief (USART2) Transmit Pointer Register */
+#define REG_USART2_TCR          (0x400A010CU) /**< \brief (USART2) Transmit Counter Register */
+#define REG_USART2_RNPR          (0x400A0110U) /**< \brief (USART2) Receive Next Pointer Register */
+#define REG_USART2_RNCR          (0x400A0114U) /**< \brief (USART2) Receive Next Counter Register */
+#define REG_USART2_TNPR          (0x400A0118U) /**< \brief (USART2) Transmit Next Pointer Register */
+#define REG_USART2_TNCR          (0x400A011CU) /**< \brief (USART2) Transmit Next Counter Register */
+#define REG_USART2_PTCR          (0x400A0120U) /**< \brief (USART2) Transfer Control Register */
+#define REG_USART2_PTSR          (0x400A0124U) /**< \brief (USART2) Transfer Status Register */
+#else
+#define REG_USART2_CR (*(WoReg*)0x400A0000U) /**< \brief (USART2) Control Register */
+#define REG_USART2_MR (*(RwReg*)0x400A0004U) /**< \brief (USART2) Mode Register */
+#define REG_USART2_IER (*(WoReg*)0x400A0008U) /**< \brief (USART2) Interrupt Enable Register */
+#define REG_USART2_IDR (*(WoReg*)0x400A000CU) /**< \brief (USART2) Interrupt Disable Register */
+#define REG_USART2_IMR (*(RoReg*)0x400A0010U) /**< \brief (USART2) Interrupt Mask Register */
+#define REG_USART2_CSR (*(RoReg*)0x400A0014U) /**< \brief (USART2) Channel Status Register */
+#define REG_USART2_RHR (*(RoReg*)0x400A0018U) /**< \brief (USART2) Receiver Holding Register */
+#define REG_USART2_THR (*(WoReg*)0x400A001CU) /**< \brief (USART2) Transmitter Holding Register */
+#define REG_USART2_BRGR (*(RwReg*)0x400A0020U) /**< \brief (USART2) Baud Rate Generator Register */
+#define REG_USART2_RTOR (*(RwReg*)0x400A0024U) /**< \brief (USART2) Receiver Time-out Register */
+#define REG_USART2_TTGR (*(RwReg*)0x400A0028U) /**< \brief (USART2) Transmitter Timeguard Register */
+#define REG_USART2_FIDI (*(RwReg*)0x400A0040U) /**< \brief (USART2) FI DI Ratio Register */
+#define REG_USART2_NER (*(RoReg*)0x400A0044U) /**< \brief (USART2) Number of Errors Register */
+#define REG_USART2_IF (*(RwReg*)0x400A004CU) /**< \brief (USART2) IrDA Filter Register */
+#define REG_USART2_MAN (*(RwReg*)0x400A0050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
+#define REG_USART2_LINMR (*(RwReg*)0x400A0054U) /**< \brief (USART2) LIN Mode Register */
+#define REG_USART2_LINIR (*(RwReg*)0x400A0058U) /**< \brief (USART2) LIN Identifier Register */
+#define REG_USART2_WPMR (*(RwReg*)0x400A00E4U) /**< \brief (USART2) Write Protect Mode Register */
+#define REG_USART2_WPSR (*(RoReg*)0x400A00E8U) /**< \brief (USART2) Write Protect Status Register */
+#define REG_USART2_RPR (*(RwReg*)0x400A0100U) /**< \brief (USART2) Receive Pointer Register */
+#define REG_USART2_RCR (*(RwReg*)0x400A0104U) /**< \brief (USART2) Receive Counter Register */
+#define REG_USART2_TPR (*(RwReg*)0x400A0108U) /**< \brief (USART2) Transmit Pointer Register */
+#define REG_USART2_TCR (*(RwReg*)0x400A010CU) /**< \brief (USART2) Transmit Counter Register */
+#define REG_USART2_RNPR (*(RwReg*)0x400A0110U) /**< \brief (USART2) Receive Next Pointer Register */
+#define REG_USART2_RNCR (*(RwReg*)0x400A0114U) /**< \brief (USART2) Receive Next Counter Register */
+#define REG_USART2_TNPR (*(RwReg*)0x400A0118U) /**< \brief (USART2) Transmit Next Pointer Register */
+#define REG_USART2_TNCR (*(RwReg*)0x400A011CU) /**< \brief (USART2) Transmit Next Counter Register */
+#define REG_USART2_PTCR (*(WoReg*)0x400A0120U) /**< \brief (USART2) Transfer Control Register */
+#define REG_USART2_PTSR (*(RoReg*)0x400A0124U) /**< \brief (USART2) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_USART2_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_usart3.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_usart3.h
new file mode 100644
index 000000000..357f20fbd
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_usart3.h
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_USART3_INSTANCE_
+#define _SAM3XA_USART3_INSTANCE_
+
+/* ========== Register definition for USART3 peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_USART3_CR          (0x400A4000U) /**< \brief (USART3) Control Register */
+#define REG_USART3_MR          (0x400A4004U) /**< \brief (USART3) Mode Register */
+#define REG_USART3_IER          (0x400A4008U) /**< \brief (USART3) Interrupt Enable Register */
+#define REG_USART3_IDR          (0x400A400CU) /**< \brief (USART3) Interrupt Disable Register */
+#define REG_USART3_IMR          (0x400A4010U) /**< \brief (USART3) Interrupt Mask Register */
+#define REG_USART3_CSR          (0x400A4014U) /**< \brief (USART3) Channel Status Register */
+#define REG_USART3_RHR          (0x400A4018U) /**< \brief (USART3) Receiver Holding Register */
+#define REG_USART3_THR          (0x400A401CU) /**< \brief (USART3) Transmitter Holding Register */
+#define REG_USART3_BRGR          (0x400A4020U) /**< \brief (USART3) Baud Rate Generator Register */
+#define REG_USART3_RTOR          (0x400A4024U) /**< \brief (USART3) Receiver Time-out Register */
+#define REG_USART3_TTGR          (0x400A4028U) /**< \brief (USART3) Transmitter Timeguard Register */
+#define REG_USART3_FIDI          (0x400A4040U) /**< \brief (USART3) FI DI Ratio Register */
+#define REG_USART3_NER          (0x400A4044U) /**< \brief (USART3) Number of Errors Register */
+#define REG_USART3_IF          (0x400A404CU) /**< \brief (USART3) IrDA Filter Register */
+#define REG_USART3_MAN          (0x400A4050U) /**< \brief (USART3) Manchester Encoder Decoder Register */
+#define REG_USART3_LINMR          (0x400A4054U) /**< \brief (USART3) LIN Mode Register */
+#define REG_USART3_LINIR          (0x400A4058U) /**< \brief (USART3) LIN Identifier Register */
+#define REG_USART3_WPMR          (0x400A40E4U) /**< \brief (USART3) Write Protect Mode Register */
+#define REG_USART3_WPSR          (0x400A40E8U) /**< \brief (USART3) Write Protect Status Register */
+#define REG_USART3_RPR          (0x400A4100U) /**< \brief (USART3) Receive Pointer Register */
+#define REG_USART3_RCR          (0x400A4104U) /**< \brief (USART3) Receive Counter Register */
+#define REG_USART3_TPR          (0x400A4108U) /**< \brief (USART3) Transmit Pointer Register */
+#define REG_USART3_TCR          (0x400A410CU) /**< \brief (USART3) Transmit Counter Register */
+#define REG_USART3_RNPR          (0x400A4110U) /**< \brief (USART3) Receive Next Pointer Register */
+#define REG_USART3_RNCR          (0x400A4114U) /**< \brief (USART3) Receive Next Counter Register */
+#define REG_USART3_TNPR          (0x400A4118U) /**< \brief (USART3) Transmit Next Pointer Register */
+#define REG_USART3_TNCR          (0x400A411CU) /**< \brief (USART3) Transmit Next Counter Register */
+#define REG_USART3_PTCR          (0x400A4120U) /**< \brief (USART3) Transfer Control Register */
+#define REG_USART3_PTSR          (0x400A4124U) /**< \brief (USART3) Transfer Status Register */
+#else
+#define REG_USART3_CR (*(WoReg*)0x400A4000U) /**< \brief (USART3) Control Register */
+#define REG_USART3_MR (*(RwReg*)0x400A4004U) /**< \brief (USART3) Mode Register */
+#define REG_USART3_IER (*(WoReg*)0x400A4008U) /**< \brief (USART3) Interrupt Enable Register */
+#define REG_USART3_IDR (*(WoReg*)0x400A400CU) /**< \brief (USART3) Interrupt Disable Register */
+#define REG_USART3_IMR (*(RoReg*)0x400A4010U) /**< \brief (USART3) Interrupt Mask Register */
+#define REG_USART3_CSR (*(RoReg*)0x400A4014U) /**< \brief (USART3) Channel Status Register */
+#define REG_USART3_RHR (*(RoReg*)0x400A4018U) /**< \brief (USART3) Receiver Holding Register */
+#define REG_USART3_THR (*(WoReg*)0x400A401CU) /**< \brief (USART3) Transmitter Holding Register */
+#define REG_USART3_BRGR (*(RwReg*)0x400A4020U) /**< \brief (USART3) Baud Rate Generator Register */
+#define REG_USART3_RTOR (*(RwReg*)0x400A4024U) /**< \brief (USART3) Receiver Time-out Register */
+#define REG_USART3_TTGR (*(RwReg*)0x400A4028U) /**< \brief (USART3) Transmitter Timeguard Register */
+#define REG_USART3_FIDI (*(RwReg*)0x400A4040U) /**< \brief (USART3) FI DI Ratio Register */
+#define REG_USART3_NER (*(RoReg*)0x400A4044U) /**< \brief (USART3) Number of Errors Register */
+#define REG_USART3_IF (*(RwReg*)0x400A404CU) /**< \brief (USART3) IrDA Filter Register */
+#define REG_USART3_MAN (*(RwReg*)0x400A4050U) /**< \brief (USART3) Manchester Encoder Decoder Register */
+#define REG_USART3_LINMR (*(RwReg*)0x400A4054U) /**< \brief (USART3) LIN Mode Register */
+#define REG_USART3_LINIR (*(RwReg*)0x400A4058U) /**< \brief (USART3) LIN Identifier Register */
+#define REG_USART3_WPMR (*(RwReg*)0x400A40E4U) /**< \brief (USART3) Write Protect Mode Register */
+#define REG_USART3_WPSR (*(RoReg*)0x400A40E8U) /**< \brief (USART3) Write Protect Status Register */
+#define REG_USART3_RPR (*(RwReg*)0x400A4100U) /**< \brief (USART3) Receive Pointer Register */
+#define REG_USART3_RCR (*(RwReg*)0x400A4104U) /**< \brief (USART3) Receive Counter Register */
+#define REG_USART3_TPR (*(RwReg*)0x400A4108U) /**< \brief (USART3) Transmit Pointer Register */
+#define REG_USART3_TCR (*(RwReg*)0x400A410CU) /**< \brief (USART3) Transmit Counter Register */
+#define REG_USART3_RNPR (*(RwReg*)0x400A4110U) /**< \brief (USART3) Receive Next Pointer Register */
+#define REG_USART3_RNCR (*(RwReg*)0x400A4114U) /**< \brief (USART3) Receive Next Counter Register */
+#define REG_USART3_TNPR (*(RwReg*)0x400A4118U) /**< \brief (USART3) Transmit Next Pointer Register */
+#define REG_USART3_TNCR (*(RwReg*)0x400A411CU) /**< \brief (USART3) Transmit Next Counter Register */
+#define REG_USART3_PTCR (*(WoReg*)0x400A4120U) /**< \brief (USART3) Transfer Control Register */
+#define REG_USART3_PTSR (*(RoReg*)0x400A4124U) /**< \brief (USART3) Transfer Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_USART3_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_wdt.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_wdt.h
new file mode 100644
index 000000000..e60630056
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/instance/instance_wdt.h
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_WDT_INSTANCE_
+#define _SAM3XA_WDT_INSTANCE_
+
+/* ========== Register definition for WDT peripheral ========== */
+#ifdef __ASSEMBLY__
+#define REG_WDT_CR          (0x400E1A50U) /**< \brief (WDT) Control Register */
+#define REG_WDT_MR          (0x400E1A54U) /**< \brief (WDT) Mode Register */
+#define REG_WDT_SR          (0x400E1A58U) /**< \brief (WDT) Status Register */
+#else
+#define REG_WDT_CR (*(WoReg*)0x400E1A50U) /**< \brief (WDT) Control Register */
+#define REG_WDT_MR (*(RwReg*)0x400E1A54U) /**< \brief (WDT) Mode Register */
+#define REG_WDT_SR (*(RoReg*)0x400E1A58U) /**< \brief (WDT) Status Register */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SAM3XA_WDT_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3a2c.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3a2c.h
new file mode 100644
index 000000000..233a32c43
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3a2c.h
@@ -0,0 +1,338 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3A2C_PIO_
+#define _SAM3A2C_PIO_
+
+#define PIO_PA0              (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1              (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2              (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3              (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4              (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5              (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6              (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7              (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8              (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9              (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10             (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11             (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12             (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13             (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14             (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15             (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16             (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17             (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18             (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19             (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20             (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21             (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22             (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23             (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24             (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25             (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26             (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27             (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28             (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29             (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PB0              (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1              (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2              (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3              (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4              (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5              (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6              (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7              (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8              (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9              (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10             (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11             (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12             (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13             (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14             (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15             (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16             (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17             (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18             (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19             (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20             (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21             (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22             (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23             (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24             (1u << 24) /**< \brief Pin Controlled by PB24 */
+#define PIO_PB25             (1u << 25) /**< \brief Pin Controlled by PB25 */
+#define PIO_PB26             (1u << 26) /**< \brief Pin Controlled by PB26 */
+#define PIO_PB27             (1u << 27) /**< \brief Pin Controlled by PB27 */
+#define PIO_PB28             (1u << 28) /**< \brief Pin Controlled by PB28 */
+#define PIO_PB29             (1u << 29) /**< \brief Pin Controlled by PB29 */
+#define PIO_PB30             (1u << 30) /**< \brief Pin Controlled by PB30 */
+#define PIO_PB31             (1u << 31) /**< \brief Pin Controlled by PB31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA2X1_AD0        (1u << 2)  /**< \brief Adc signal: AD0 */
+#define PIO_PA3X1_AD1        (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PA3X1_WKUP1      (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PB17X1_AD10      (1u << 17) /**< \brief Adc signal: AD10 */
+#define PIO_PB18X1_AD11      (1u << 18) /**< \brief Adc signal: AD11 */
+#define PIO_PB19X1_AD12      (1u << 19) /**< \brief Adc signal: AD12 */
+#define PIO_PB20X1_AD13      (1u << 20) /**< \brief Adc signal: AD13 */
+#define PIO_PB21X1_AD14      (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PB21X1_WKUP13    (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PA4X1_AD2        (1u << 4)  /**< \brief Adc signal: AD2 */
+#define PIO_PA6X1_AD3        (1u << 6)  /**< \brief Adc signal: AD3 */
+#define PIO_PA22X1_AD4       (1u << 22) /**< \brief Adc signal: AD4 */
+#define PIO_PA23X1_AD5       (1u << 23) /**< \brief Adc signal: AD5 */
+#define PIO_PA24X1_AD6       (1u << 24) /**< \brief Adc signal: AD6 */
+#define PIO_PA16X1_AD7       (1u << 16) /**< \brief Adc signal: AD7 */
+#define PIO_PB12X1_AD8       (1u << 12) /**< \brief Adc signal: AD8 */
+#define PIO_PB13X1_AD9       (1u << 13) /**< \brief Adc signal: AD9 */
+#define PIO_PA11B_ADTRG      (1u << 11) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for CAN0 peripheral ========== */
+#define PIO_PA1A_CANRX0      (1u << 1)  /**< \brief Can0 signal: CANRX0 */
+#define PIO_PA0A_CANTX0      (1u << 0)  /**< \brief Can0 signal: CANTX0 */
+/* ========== Pio definition for CAN1 peripheral ========== */
+#define PIO_PB15A_CANRX1     (1u << 15) /**< \brief Can1 signal: CANRX1 */
+#define PIO_PB14A_CANTX1     (1u << 14) /**< \brief Can1 signal: CANTX1 */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB15X1_DAC0      (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB15X1_WKUP12    (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB16X1_DAC1      (1u << 16) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA10B_DATRG      (1u << 10) /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA20A_MCCDA      (1u << 20) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PE20B_MCCDB      (1u << 20) /**< \brief Hsmci signal: MCCDB */
+#define PIO_PA19A_MCCK       (1u << 19) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA21A_MCDA0      (1u << 21) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA22A_MCDA1      (1u << 22) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA23A_MCDA2      (1u << 23) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA24A_MCDA3      (1u << 24) /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PD0B_MCDA4       (1u << 0)  /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PD1B_MCDA5       (1u << 1)  /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PD2B_MCDA6       (1u << 2)  /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PD3B_MCDA7       (1u << 3)  /**< \brief Hsmci signal: MCDA7 */
+#define PIO_PE22B_MCDB0      (1u << 22) /**< \brief Hsmci signal: MCDB0 */
+#define PIO_PE24B_MCDB1      (1u << 24) /**< \brief Hsmci signal: MCDB1 */
+#define PIO_PE26B_MCDB2      (1u << 26) /**< \brief Hsmci signal: MCDB2 */
+#define PIO_PE27B_MCDB3      (1u << 27) /**< \brief Hsmci signal: MCDB3 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA1B_PCK0        (1u << 1)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB22B_PCK0       (1u << 22) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA24B_PCK1       (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA30B_PCK1       (1u << 30) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA28B_PCK2       (1u << 28) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2       (1u << 31) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA5B_PWMFI0      (1u << 5)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA3B_PWMFI1      (1u << 3)  /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PD6B_PWMFI2      (1u << 6)  /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA8B_PWMH0       (1u << 8)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB12B_PWMH0      (1u << 12) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC3B_PWMH0       (1u << 3)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PE15A_PWMH0      (1u << 15) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA19B_PWMH1      (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB13B_PWMH1      (1u << 13) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC5B_PWMH1       (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PE16A_PWMH1      (1u << 16) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA13B_PWMH2      (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB14B_PWMH2      (1u << 14) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC7B_PWMH2       (1u << 7)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB15B_PWMH3      (1u << 15) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PF3A_PWMH3       (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC20B_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PE20A_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PC19B_PWMH5      (1u << 19) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PE22A_PWMH5      (1u << 22) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PC18B_PWMH6      (1u << 18) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE24A_PWMH6      (1u << 24) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE26A_PWMH7      (1u << 26) /**< \brief Pwm signal: PWMH7 */
+#define PIO_PA21B_PWML0      (1u << 21) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB16B_PWML0      (1u << 16) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC2B_PWML0       (1u << 2)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PE18A_PWML0      (1u << 18) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA12B_PWML1      (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB17B_PWML1      (1u << 17) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC4B_PWML1       (1u << 4)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PA20B_PWML2      (1u << 20) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB18B_PWML2      (1u << 18) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC6B_PWML2       (1u << 6)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PE17A_PWML2      (1u << 17) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA0B_PWML3       (1u << 0)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB19B_PWML3      (1u << 19) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC8B_PWML3       (1u << 8)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB6B_PWML4       (1u << 6)  /**< \brief Pwm signal: PWML4 */
+#define PIO_PC21B_PWML4      (1u << 21) /**< \brief Pwm signal: PWML4 */
+#define PIO_PE19A_PWML4      (1u << 19) /**< \brief Pwm signal: PWML4 */
+#define PIO_PB7B_PWML5       (1u << 7)  /**< \brief Pwm signal: PWML5 */
+#define PIO_PC22B_PWML5      (1u << 22) /**< \brief Pwm signal: PWML5 */
+#define PIO_PE21A_PWML5      (1u << 21) /**< \brief Pwm signal: PWML5 */
+#define PIO_PB8B_PWML6       (1u << 8)  /**< \brief Pwm signal: PWML6 */
+#define PIO_PC23B_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PE23A_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PB9B_PWML7       (1u << 9)  /**< \brief Pwm signal: PWML7 */
+#define PIO_PC24B_PWML7      (1u << 24) /**< \brief Pwm signal: PWML7 */
+#define PIO_PE25A_PWML7      (1u << 25) /**< \brief Pwm signal: PWML7 */
+/* ========== Pio definition for SPI0 peripheral ========== */
+#define PIO_PA25A_SPI0_MISO  (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */
+#define PIO_PA26A_SPI0_MOSI  (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */
+#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */
+#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PA27A_SPI0_SPCK  (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PB18A_RD         (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PB17A_RF         (1u << 17) /**< \brief Ssc signal: RF */
+#define PIO_PB19A_RK         (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA16B_TD         (1u << 16) /**< \brief Ssc signal: TD */
+#define PIO_PA15B_TF         (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA14B_TK         (1u << 14) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PB26B_TCLK0      (1u << 26) /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA4A_TCLK1       (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA7A_TCLK2       (1u << 7)  /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PB25B_TIOA0      (1u << 25) /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA2A_TIOA1       (1u << 2)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA5A_TIOA2       (1u << 5)  /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PB27B_TIOB0      (1u << 27) /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA3A_TIOB1       (1u << 3)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA6A_TIOB2       (1u << 6)  /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PA22B_TCLK3      (1u << 22) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PA23B_TCLK4      (1u << 23) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PB16A_TCLK5      (1u << 16) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PB0B_TIOA3       (1u << 0)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PE9A_TIOA3       (1u << 9)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PB2B_TIOA4       (1u << 2)  /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PE11A_TIOA4      (1u << 11) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PB4B_TIOA5       (1u << 4)  /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PE13A_TIOA5      (1u << 13) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PB1B_TIOB3       (1u << 1)  /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PE10A_TIOB3      (1u << 10) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PB3B_TIOB4       (1u << 3)  /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PE12A_TIOB4      (1u << 12) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PB5B_TIOB5       (1u << 5)  /**< \brief Tc1 signal: TIOB5 */
+#define PIO_PE14A_TIOB5      (1u << 14) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA18A_TWCK0      (1u << 18) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA17A_TWD0       (1u << 17) /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB13A_TWCK1      (1u << 13) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB12A_TWD1       (1u << 12) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA8A_URXD        (1u << 8)  /**< \brief Uart signal: URXD */
+#define PIO_PA9A_UTXD        (1u << 9)  /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for UOTGHS peripheral ========== */
+#define PIO_PB11A_UOTGID     (1u << 11) /**< \brief Uotghs signal: UOTGID */
+#define PIO_PB10A_UOTGVBOF   (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB26A_CTS0       (1u << 26) /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB25A_RTS0       (1u << 25) /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA10A_RXD0       (1u << 10) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17B_SCK0       (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA11A_TXD0       (1u << 11) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA15A_CTS1       (1u << 15) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA14A_RTS1       (1u << 14) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA12A_RXD1       (1u << 12) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA16A_SCK1       (1u << 16) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA13A_TXD1       (1u << 13) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB23A_CTS2       (1u << 23) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB22A_RTS2       (1u << 22) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PB21A_RXD2       (1u << 21) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PB24A_SCK2       (1u << 24) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PB20A_TXD2       (1u << 20) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX          0
+#define PIO_PA1_IDX          1
+#define PIO_PA2_IDX          2
+#define PIO_PA3_IDX          3
+#define PIO_PA4_IDX          4
+#define PIO_PA5_IDX          5
+#define PIO_PA6_IDX          6
+#define PIO_PA7_IDX          7
+#define PIO_PA8_IDX          8
+#define PIO_PA9_IDX          9
+#define PIO_PA10_IDX         10
+#define PIO_PA11_IDX         11
+#define PIO_PA12_IDX         12
+#define PIO_PA13_IDX         13
+#define PIO_PA14_IDX         14
+#define PIO_PA15_IDX         15
+#define PIO_PA16_IDX         16
+#define PIO_PA17_IDX         17
+#define PIO_PA18_IDX         18
+#define PIO_PA19_IDX         19
+#define PIO_PA20_IDX         20
+#define PIO_PA21_IDX         21
+#define PIO_PA22_IDX         22
+#define PIO_PA23_IDX         23
+#define PIO_PA24_IDX         24
+#define PIO_PA25_IDX         25
+#define PIO_PA26_IDX         26
+#define PIO_PA27_IDX         27
+#define PIO_PA28_IDX         28
+#define PIO_PA29_IDX         29
+#define PIO_PB0_IDX          32
+#define PIO_PB1_IDX          33
+#define PIO_PB2_IDX          34
+#define PIO_PB3_IDX          35
+#define PIO_PB4_IDX          36
+#define PIO_PB5_IDX          37
+#define PIO_PB6_IDX          38
+#define PIO_PB7_IDX          39
+#define PIO_PB8_IDX          40
+#define PIO_PB9_IDX          41
+#define PIO_PB10_IDX         42
+#define PIO_PB11_IDX         43
+#define PIO_PB12_IDX         44
+#define PIO_PB13_IDX         45
+#define PIO_PB14_IDX         46
+#define PIO_PB15_IDX         47
+#define PIO_PB16_IDX         48
+#define PIO_PB17_IDX         49
+#define PIO_PB18_IDX         50
+#define PIO_PB19_IDX         51
+#define PIO_PB20_IDX         52
+#define PIO_PB21_IDX         53
+#define PIO_PB22_IDX         54
+#define PIO_PB23_IDX         55
+#define PIO_PB24_IDX         56
+#define PIO_PB25_IDX         57
+#define PIO_PB26_IDX         58
+#define PIO_PB27_IDX         59
+#define PIO_PB28_IDX         60
+#define PIO_PB29_IDX         61
+#define PIO_PB30_IDX         62
+#define PIO_PB31_IDX         63
+
+#endif /* _SAM3A2C_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3a4c.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3a4c.h
new file mode 100644
index 000000000..7cd79bbf0
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3a4c.h
@@ -0,0 +1,338 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3A4C_PIO_
+#define _SAM3A4C_PIO_
+
+#define PIO_PA0              (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1              (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2              (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3              (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4              (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5              (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6              (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7              (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8              (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9              (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10             (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11             (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12             (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13             (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14             (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15             (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16             (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17             (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18             (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19             (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20             (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21             (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22             (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23             (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24             (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25             (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26             (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27             (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28             (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29             (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PB0              (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1              (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2              (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3              (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4              (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5              (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6              (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7              (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8              (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9              (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10             (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11             (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12             (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13             (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14             (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15             (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16             (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17             (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18             (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19             (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20             (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21             (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22             (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23             (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24             (1u << 24) /**< \brief Pin Controlled by PB24 */
+#define PIO_PB25             (1u << 25) /**< \brief Pin Controlled by PB25 */
+#define PIO_PB26             (1u << 26) /**< \brief Pin Controlled by PB26 */
+#define PIO_PB27             (1u << 27) /**< \brief Pin Controlled by PB27 */
+#define PIO_PB28             (1u << 28) /**< \brief Pin Controlled by PB28 */
+#define PIO_PB29             (1u << 29) /**< \brief Pin Controlled by PB29 */
+#define PIO_PB30             (1u << 30) /**< \brief Pin Controlled by PB30 */
+#define PIO_PB31             (1u << 31) /**< \brief Pin Controlled by PB31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA2X1_AD0        (1u << 2)  /**< \brief Adc signal: AD0 */
+#define PIO_PA3X1_AD1        (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PA3X1_WKUP1      (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PB17X1_AD10      (1u << 17) /**< \brief Adc signal: AD10 */
+#define PIO_PB18X1_AD11      (1u << 18) /**< \brief Adc signal: AD11 */
+#define PIO_PB19X1_AD12      (1u << 19) /**< \brief Adc signal: AD12 */
+#define PIO_PB20X1_AD13      (1u << 20) /**< \brief Adc signal: AD13 */
+#define PIO_PB21X1_AD14      (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PB21X1_WKUP13    (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PA4X1_AD2        (1u << 4)  /**< \brief Adc signal: AD2 */
+#define PIO_PA6X1_AD3        (1u << 6)  /**< \brief Adc signal: AD3 */
+#define PIO_PA22X1_AD4       (1u << 22) /**< \brief Adc signal: AD4 */
+#define PIO_PA23X1_AD5       (1u << 23) /**< \brief Adc signal: AD5 */
+#define PIO_PA24X1_AD6       (1u << 24) /**< \brief Adc signal: AD6 */
+#define PIO_PA16X1_AD7       (1u << 16) /**< \brief Adc signal: AD7 */
+#define PIO_PB12X1_AD8       (1u << 12) /**< \brief Adc signal: AD8 */
+#define PIO_PB13X1_AD9       (1u << 13) /**< \brief Adc signal: AD9 */
+#define PIO_PA11B_ADTRG      (1u << 11) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for CAN0 peripheral ========== */
+#define PIO_PA1A_CANRX0      (1u << 1)  /**< \brief Can0 signal: CANRX0 */
+#define PIO_PA0A_CANTX0      (1u << 0)  /**< \brief Can0 signal: CANTX0 */
+/* ========== Pio definition for CAN1 peripheral ========== */
+#define PIO_PB15A_CANRX1     (1u << 15) /**< \brief Can1 signal: CANRX1 */
+#define PIO_PB14A_CANTX1     (1u << 14) /**< \brief Can1 signal: CANTX1 */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB15X1_DAC0      (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB15X1_WKUP12    (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB16X1_DAC1      (1u << 16) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA10B_DATRG      (1u << 10) /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA20A_MCCDA      (1u << 20) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PE20B_MCCDB      (1u << 20) /**< \brief Hsmci signal: MCCDB */
+#define PIO_PA19A_MCCK       (1u << 19) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA21A_MCDA0      (1u << 21) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA22A_MCDA1      (1u << 22) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA23A_MCDA2      (1u << 23) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA24A_MCDA3      (1u << 24) /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PD0B_MCDA4       (1u << 0)  /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PD1B_MCDA5       (1u << 1)  /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PD2B_MCDA6       (1u << 2)  /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PD3B_MCDA7       (1u << 3)  /**< \brief Hsmci signal: MCDA7 */
+#define PIO_PE22B_MCDB0      (1u << 22) /**< \brief Hsmci signal: MCDB0 */
+#define PIO_PE24B_MCDB1      (1u << 24) /**< \brief Hsmci signal: MCDB1 */
+#define PIO_PE26B_MCDB2      (1u << 26) /**< \brief Hsmci signal: MCDB2 */
+#define PIO_PE27B_MCDB3      (1u << 27) /**< \brief Hsmci signal: MCDB3 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA1B_PCK0        (1u << 1)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB22B_PCK0       (1u << 22) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA24B_PCK1       (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA30B_PCK1       (1u << 30) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA28B_PCK2       (1u << 28) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2       (1u << 31) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA5B_PWMFI0      (1u << 5)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA3B_PWMFI1      (1u << 3)  /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PD6B_PWMFI2      (1u << 6)  /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA8B_PWMH0       (1u << 8)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB12B_PWMH0      (1u << 12) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC3B_PWMH0       (1u << 3)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PE15A_PWMH0      (1u << 15) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA19B_PWMH1      (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB13B_PWMH1      (1u << 13) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC5B_PWMH1       (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PE16A_PWMH1      (1u << 16) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA13B_PWMH2      (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB14B_PWMH2      (1u << 14) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC7B_PWMH2       (1u << 7)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB15B_PWMH3      (1u << 15) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PF3A_PWMH3       (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC20B_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PE20A_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PC19B_PWMH5      (1u << 19) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PE22A_PWMH5      (1u << 22) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PC18B_PWMH6      (1u << 18) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE24A_PWMH6      (1u << 24) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE26A_PWMH7      (1u << 26) /**< \brief Pwm signal: PWMH7 */
+#define PIO_PA21B_PWML0      (1u << 21) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB16B_PWML0      (1u << 16) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC2B_PWML0       (1u << 2)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PE18A_PWML0      (1u << 18) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA12B_PWML1      (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB17B_PWML1      (1u << 17) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC4B_PWML1       (1u << 4)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PA20B_PWML2      (1u << 20) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB18B_PWML2      (1u << 18) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC6B_PWML2       (1u << 6)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PE17A_PWML2      (1u << 17) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA0B_PWML3       (1u << 0)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB19B_PWML3      (1u << 19) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC8B_PWML3       (1u << 8)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB6B_PWML4       (1u << 6)  /**< \brief Pwm signal: PWML4 */
+#define PIO_PC21B_PWML4      (1u << 21) /**< \brief Pwm signal: PWML4 */
+#define PIO_PE19A_PWML4      (1u << 19) /**< \brief Pwm signal: PWML4 */
+#define PIO_PB7B_PWML5       (1u << 7)  /**< \brief Pwm signal: PWML5 */
+#define PIO_PC22B_PWML5      (1u << 22) /**< \brief Pwm signal: PWML5 */
+#define PIO_PE21A_PWML5      (1u << 21) /**< \brief Pwm signal: PWML5 */
+#define PIO_PB8B_PWML6       (1u << 8)  /**< \brief Pwm signal: PWML6 */
+#define PIO_PC23B_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PE23A_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PB9B_PWML7       (1u << 9)  /**< \brief Pwm signal: PWML7 */
+#define PIO_PC24B_PWML7      (1u << 24) /**< \brief Pwm signal: PWML7 */
+#define PIO_PE25A_PWML7      (1u << 25) /**< \brief Pwm signal: PWML7 */
+/* ========== Pio definition for SPI0 peripheral ========== */
+#define PIO_PA25A_SPI0_MISO  (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */
+#define PIO_PA26A_SPI0_MOSI  (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */
+#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */
+#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PA27A_SPI0_SPCK  (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PB18A_RD         (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PB17A_RF         (1u << 17) /**< \brief Ssc signal: RF */
+#define PIO_PB19A_RK         (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA16B_TD         (1u << 16) /**< \brief Ssc signal: TD */
+#define PIO_PA15B_TF         (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA14B_TK         (1u << 14) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PB26B_TCLK0      (1u << 26) /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA4A_TCLK1       (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA7A_TCLK2       (1u << 7)  /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PB25B_TIOA0      (1u << 25) /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA2A_TIOA1       (1u << 2)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA5A_TIOA2       (1u << 5)  /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PB27B_TIOB0      (1u << 27) /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA3A_TIOB1       (1u << 3)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA6A_TIOB2       (1u << 6)  /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PA22B_TCLK3      (1u << 22) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PA23B_TCLK4      (1u << 23) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PB16A_TCLK5      (1u << 16) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PB0B_TIOA3       (1u << 0)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PE9A_TIOA3       (1u << 9)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PB2B_TIOA4       (1u << 2)  /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PE11A_TIOA4      (1u << 11) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PB4B_TIOA5       (1u << 4)  /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PE13A_TIOA5      (1u << 13) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PB1B_TIOB3       (1u << 1)  /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PE10A_TIOB3      (1u << 10) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PB3B_TIOB4       (1u << 3)  /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PE12A_TIOB4      (1u << 12) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PB5B_TIOB5       (1u << 5)  /**< \brief Tc1 signal: TIOB5 */
+#define PIO_PE14A_TIOB5      (1u << 14) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA18A_TWCK0      (1u << 18) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA17A_TWD0       (1u << 17) /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB13A_TWCK1      (1u << 13) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB12A_TWD1       (1u << 12) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA8A_URXD        (1u << 8)  /**< \brief Uart signal: URXD */
+#define PIO_PA9A_UTXD        (1u << 9)  /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for UOTGHS peripheral ========== */
+#define PIO_PB11A_UOTGID     (1u << 11) /**< \brief Uotghs signal: UOTGID */
+#define PIO_PB10A_UOTGVBOF   (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB26A_CTS0       (1u << 26) /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB25A_RTS0       (1u << 25) /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA10A_RXD0       (1u << 10) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17B_SCK0       (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA11A_TXD0       (1u << 11) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA15A_CTS1       (1u << 15) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA14A_RTS1       (1u << 14) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA12A_RXD1       (1u << 12) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA16A_SCK1       (1u << 16) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA13A_TXD1       (1u << 13) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB23A_CTS2       (1u << 23) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB22A_RTS2       (1u << 22) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PB21A_RXD2       (1u << 21) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PB24A_SCK2       (1u << 24) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PB20A_TXD2       (1u << 20) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX          0
+#define PIO_PA1_IDX          1
+#define PIO_PA2_IDX          2
+#define PIO_PA3_IDX          3
+#define PIO_PA4_IDX          4
+#define PIO_PA5_IDX          5
+#define PIO_PA6_IDX          6
+#define PIO_PA7_IDX          7
+#define PIO_PA8_IDX          8
+#define PIO_PA9_IDX          9
+#define PIO_PA10_IDX         10
+#define PIO_PA11_IDX         11
+#define PIO_PA12_IDX         12
+#define PIO_PA13_IDX         13
+#define PIO_PA14_IDX         14
+#define PIO_PA15_IDX         15
+#define PIO_PA16_IDX         16
+#define PIO_PA17_IDX         17
+#define PIO_PA18_IDX         18
+#define PIO_PA19_IDX         19
+#define PIO_PA20_IDX         20
+#define PIO_PA21_IDX         21
+#define PIO_PA22_IDX         22
+#define PIO_PA23_IDX         23
+#define PIO_PA24_IDX         24
+#define PIO_PA25_IDX         25
+#define PIO_PA26_IDX         26
+#define PIO_PA27_IDX         27
+#define PIO_PA28_IDX         28
+#define PIO_PA29_IDX         29
+#define PIO_PB0_IDX          32
+#define PIO_PB1_IDX          33
+#define PIO_PB2_IDX          34
+#define PIO_PB3_IDX          35
+#define PIO_PB4_IDX          36
+#define PIO_PB5_IDX          37
+#define PIO_PB6_IDX          38
+#define PIO_PB7_IDX          39
+#define PIO_PB8_IDX          40
+#define PIO_PB9_IDX          41
+#define PIO_PB10_IDX         42
+#define PIO_PB11_IDX         43
+#define PIO_PB12_IDX         44
+#define PIO_PB13_IDX         45
+#define PIO_PB14_IDX         46
+#define PIO_PB15_IDX         47
+#define PIO_PB16_IDX         48
+#define PIO_PB17_IDX         49
+#define PIO_PB18_IDX         50
+#define PIO_PB19_IDX         51
+#define PIO_PB20_IDX         52
+#define PIO_PB21_IDX         53
+#define PIO_PB22_IDX         54
+#define PIO_PB23_IDX         55
+#define PIO_PB24_IDX         56
+#define PIO_PB25_IDX         57
+#define PIO_PB26_IDX         58
+#define PIO_PB27_IDX         59
+#define PIO_PB28_IDX         60
+#define PIO_PB29_IDX         61
+#define PIO_PB30_IDX         62
+#define PIO_PB31_IDX         63
+
+#endif /* _SAM3A4C_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3a8c.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3a8c.h
new file mode 100644
index 000000000..a04c6b7ea
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3a8c.h
@@ -0,0 +1,338 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3A8C_PIO_
+#define _SAM3A8C_PIO_
+
+#define PIO_PA0              (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1              (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2              (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3              (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4              (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5              (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6              (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7              (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8              (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9              (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10             (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11             (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12             (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13             (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14             (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15             (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16             (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17             (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18             (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19             (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20             (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21             (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22             (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23             (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24             (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25             (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26             (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27             (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28             (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29             (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PB0              (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1              (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2              (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3              (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4              (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5              (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6              (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7              (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8              (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9              (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10             (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11             (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12             (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13             (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14             (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15             (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16             (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17             (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18             (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19             (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20             (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21             (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22             (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23             (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24             (1u << 24) /**< \brief Pin Controlled by PB24 */
+#define PIO_PB25             (1u << 25) /**< \brief Pin Controlled by PB25 */
+#define PIO_PB26             (1u << 26) /**< \brief Pin Controlled by PB26 */
+#define PIO_PB27             (1u << 27) /**< \brief Pin Controlled by PB27 */
+#define PIO_PB28             (1u << 28) /**< \brief Pin Controlled by PB28 */
+#define PIO_PB29             (1u << 29) /**< \brief Pin Controlled by PB29 */
+#define PIO_PB30             (1u << 30) /**< \brief Pin Controlled by PB30 */
+#define PIO_PB31             (1u << 31) /**< \brief Pin Controlled by PB31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA2X1_AD0        (1u << 2)  /**< \brief Adc signal: AD0 */
+#define PIO_PA3X1_AD1        (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PA3X1_WKUP1      (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PB17X1_AD10      (1u << 17) /**< \brief Adc signal: AD10 */
+#define PIO_PB18X1_AD11      (1u << 18) /**< \brief Adc signal: AD11 */
+#define PIO_PB19X1_AD12      (1u << 19) /**< \brief Adc signal: AD12 */
+#define PIO_PB20X1_AD13      (1u << 20) /**< \brief Adc signal: AD13 */
+#define PIO_PB21X1_AD14      (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PB21X1_WKUP13    (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PA4X1_AD2        (1u << 4)  /**< \brief Adc signal: AD2 */
+#define PIO_PA6X1_AD3        (1u << 6)  /**< \brief Adc signal: AD3 */
+#define PIO_PA22X1_AD4       (1u << 22) /**< \brief Adc signal: AD4 */
+#define PIO_PA23X1_AD5       (1u << 23) /**< \brief Adc signal: AD5 */
+#define PIO_PA24X1_AD6       (1u << 24) /**< \brief Adc signal: AD6 */
+#define PIO_PA16X1_AD7       (1u << 16) /**< \brief Adc signal: AD7 */
+#define PIO_PB12X1_AD8       (1u << 12) /**< \brief Adc signal: AD8 */
+#define PIO_PB13X1_AD9       (1u << 13) /**< \brief Adc signal: AD9 */
+#define PIO_PA11B_ADTRG      (1u << 11) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for CAN0 peripheral ========== */
+#define PIO_PA1A_CANRX0      (1u << 1)  /**< \brief Can0 signal: CANRX0 */
+#define PIO_PA0A_CANTX0      (1u << 0)  /**< \brief Can0 signal: CANTX0 */
+/* ========== Pio definition for CAN1 peripheral ========== */
+#define PIO_PB15A_CANRX1     (1u << 15) /**< \brief Can1 signal: CANRX1 */
+#define PIO_PB14A_CANTX1     (1u << 14) /**< \brief Can1 signal: CANTX1 */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB15X1_DAC0      (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB15X1_WKUP12    (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB16X1_DAC1      (1u << 16) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA10B_DATRG      (1u << 10) /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA20A_MCCDA      (1u << 20) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PE20B_MCCDB      (1u << 20) /**< \brief Hsmci signal: MCCDB */
+#define PIO_PA19A_MCCK       (1u << 19) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA21A_MCDA0      (1u << 21) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA22A_MCDA1      (1u << 22) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA23A_MCDA2      (1u << 23) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA24A_MCDA3      (1u << 24) /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PD0B_MCDA4       (1u << 0)  /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PD1B_MCDA5       (1u << 1)  /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PD2B_MCDA6       (1u << 2)  /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PD3B_MCDA7       (1u << 3)  /**< \brief Hsmci signal: MCDA7 */
+#define PIO_PE22B_MCDB0      (1u << 22) /**< \brief Hsmci signal: MCDB0 */
+#define PIO_PE24B_MCDB1      (1u << 24) /**< \brief Hsmci signal: MCDB1 */
+#define PIO_PE26B_MCDB2      (1u << 26) /**< \brief Hsmci signal: MCDB2 */
+#define PIO_PE27B_MCDB3      (1u << 27) /**< \brief Hsmci signal: MCDB3 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA1B_PCK0        (1u << 1)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB22B_PCK0       (1u << 22) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA24B_PCK1       (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA30B_PCK1       (1u << 30) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA28B_PCK2       (1u << 28) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2       (1u << 31) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA5B_PWMFI0      (1u << 5)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA3B_PWMFI1      (1u << 3)  /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PD6B_PWMFI2      (1u << 6)  /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA8B_PWMH0       (1u << 8)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB12B_PWMH0      (1u << 12) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC3B_PWMH0       (1u << 3)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PE15A_PWMH0      (1u << 15) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA19B_PWMH1      (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB13B_PWMH1      (1u << 13) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC5B_PWMH1       (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PE16A_PWMH1      (1u << 16) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA13B_PWMH2      (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB14B_PWMH2      (1u << 14) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC7B_PWMH2       (1u << 7)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB15B_PWMH3      (1u << 15) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PF3A_PWMH3       (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC20B_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PE20A_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PC19B_PWMH5      (1u << 19) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PE22A_PWMH5      (1u << 22) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PC18B_PWMH6      (1u << 18) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE24A_PWMH6      (1u << 24) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE26A_PWMH7      (1u << 26) /**< \brief Pwm signal: PWMH7 */
+#define PIO_PA21B_PWML0      (1u << 21) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB16B_PWML0      (1u << 16) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC2B_PWML0       (1u << 2)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PE18A_PWML0      (1u << 18) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA12B_PWML1      (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB17B_PWML1      (1u << 17) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC4B_PWML1       (1u << 4)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PA20B_PWML2      (1u << 20) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB18B_PWML2      (1u << 18) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC6B_PWML2       (1u << 6)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PE17A_PWML2      (1u << 17) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA0B_PWML3       (1u << 0)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB19B_PWML3      (1u << 19) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC8B_PWML3       (1u << 8)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB6B_PWML4       (1u << 6)  /**< \brief Pwm signal: PWML4 */
+#define PIO_PC21B_PWML4      (1u << 21) /**< \brief Pwm signal: PWML4 */
+#define PIO_PE19A_PWML4      (1u << 19) /**< \brief Pwm signal: PWML4 */
+#define PIO_PB7B_PWML5       (1u << 7)  /**< \brief Pwm signal: PWML5 */
+#define PIO_PC22B_PWML5      (1u << 22) /**< \brief Pwm signal: PWML5 */
+#define PIO_PE21A_PWML5      (1u << 21) /**< \brief Pwm signal: PWML5 */
+#define PIO_PB8B_PWML6       (1u << 8)  /**< \brief Pwm signal: PWML6 */
+#define PIO_PC23B_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PE23A_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PB9B_PWML7       (1u << 9)  /**< \brief Pwm signal: PWML7 */
+#define PIO_PC24B_PWML7      (1u << 24) /**< \brief Pwm signal: PWML7 */
+#define PIO_PE25A_PWML7      (1u << 25) /**< \brief Pwm signal: PWML7 */
+/* ========== Pio definition for SPI0 peripheral ========== */
+#define PIO_PA25A_SPI0_MISO  (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */
+#define PIO_PA26A_SPI0_MOSI  (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */
+#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */
+#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PA27A_SPI0_SPCK  (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PB18A_RD         (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PB17A_RF         (1u << 17) /**< \brief Ssc signal: RF */
+#define PIO_PB19A_RK         (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA16B_TD         (1u << 16) /**< \brief Ssc signal: TD */
+#define PIO_PA15B_TF         (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA14B_TK         (1u << 14) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PB26B_TCLK0      (1u << 26) /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA4A_TCLK1       (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA7A_TCLK2       (1u << 7)  /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PB25B_TIOA0      (1u << 25) /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA2A_TIOA1       (1u << 2)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA5A_TIOA2       (1u << 5)  /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PB27B_TIOB0      (1u << 27) /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA3A_TIOB1       (1u << 3)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA6A_TIOB2       (1u << 6)  /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PA22B_TCLK3      (1u << 22) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PA23B_TCLK4      (1u << 23) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PB16A_TCLK5      (1u << 16) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PB0B_TIOA3       (1u << 0)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PE9A_TIOA3       (1u << 9)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PB2B_TIOA4       (1u << 2)  /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PE11A_TIOA4      (1u << 11) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PB4B_TIOA5       (1u << 4)  /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PE13A_TIOA5      (1u << 13) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PB1B_TIOB3       (1u << 1)  /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PE10A_TIOB3      (1u << 10) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PB3B_TIOB4       (1u << 3)  /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PE12A_TIOB4      (1u << 12) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PB5B_TIOB5       (1u << 5)  /**< \brief Tc1 signal: TIOB5 */
+#define PIO_PE14A_TIOB5      (1u << 14) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA18A_TWCK0      (1u << 18) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA17A_TWD0       (1u << 17) /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB13A_TWCK1      (1u << 13) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB12A_TWD1       (1u << 12) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA8A_URXD        (1u << 8)  /**< \brief Uart signal: URXD */
+#define PIO_PA9A_UTXD        (1u << 9)  /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for UOTGHS peripheral ========== */
+#define PIO_PB11A_UOTGID     (1u << 11) /**< \brief Uotghs signal: UOTGID */
+#define PIO_PB10A_UOTGVBOF   (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB26A_CTS0       (1u << 26) /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB25A_RTS0       (1u << 25) /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA10A_RXD0       (1u << 10) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17B_SCK0       (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA11A_TXD0       (1u << 11) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA15A_CTS1       (1u << 15) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA14A_RTS1       (1u << 14) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA12A_RXD1       (1u << 12) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA16A_SCK1       (1u << 16) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA13A_TXD1       (1u << 13) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB23A_CTS2       (1u << 23) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB22A_RTS2       (1u << 22) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PB21A_RXD2       (1u << 21) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PB24A_SCK2       (1u << 24) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PB20A_TXD2       (1u << 20) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX          0
+#define PIO_PA1_IDX          1
+#define PIO_PA2_IDX          2
+#define PIO_PA3_IDX          3
+#define PIO_PA4_IDX          4
+#define PIO_PA5_IDX          5
+#define PIO_PA6_IDX          6
+#define PIO_PA7_IDX          7
+#define PIO_PA8_IDX          8
+#define PIO_PA9_IDX          9
+#define PIO_PA10_IDX         10
+#define PIO_PA11_IDX         11
+#define PIO_PA12_IDX         12
+#define PIO_PA13_IDX         13
+#define PIO_PA14_IDX         14
+#define PIO_PA15_IDX         15
+#define PIO_PA16_IDX         16
+#define PIO_PA17_IDX         17
+#define PIO_PA18_IDX         18
+#define PIO_PA19_IDX         19
+#define PIO_PA20_IDX         20
+#define PIO_PA21_IDX         21
+#define PIO_PA22_IDX         22
+#define PIO_PA23_IDX         23
+#define PIO_PA24_IDX         24
+#define PIO_PA25_IDX         25
+#define PIO_PA26_IDX         26
+#define PIO_PA27_IDX         27
+#define PIO_PA28_IDX         28
+#define PIO_PA29_IDX         29
+#define PIO_PB0_IDX          32
+#define PIO_PB1_IDX          33
+#define PIO_PB2_IDX          34
+#define PIO_PB3_IDX          35
+#define PIO_PB4_IDX          36
+#define PIO_PB5_IDX          37
+#define PIO_PB6_IDX          38
+#define PIO_PB7_IDX          39
+#define PIO_PB8_IDX          40
+#define PIO_PB9_IDX          41
+#define PIO_PB10_IDX         42
+#define PIO_PB11_IDX         43
+#define PIO_PB12_IDX         44
+#define PIO_PB13_IDX         45
+#define PIO_PB14_IDX         46
+#define PIO_PB15_IDX         47
+#define PIO_PB16_IDX         48
+#define PIO_PB17_IDX         49
+#define PIO_PB18_IDX         50
+#define PIO_PB19_IDX         51
+#define PIO_PB20_IDX         52
+#define PIO_PB21_IDX         53
+#define PIO_PB22_IDX         54
+#define PIO_PB23_IDX         55
+#define PIO_PB24_IDX         56
+#define PIO_PB25_IDX         57
+#define PIO_PB26_IDX         58
+#define PIO_PB27_IDX         59
+#define PIO_PB28_IDX         60
+#define PIO_PB29_IDX         61
+#define PIO_PB30_IDX         62
+#define PIO_PB31_IDX         63
+
+#endif /* _SAM3A8C_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x4c.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x4c.h
new file mode 100644
index 000000000..4afffcb8f
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x4c.h
@@ -0,0 +1,358 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3X4C_PIO_
+#define _SAM3X4C_PIO_
+
+#define PIO_PA0              (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1              (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2              (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3              (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4              (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5              (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6              (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7              (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8              (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9              (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10             (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11             (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12             (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13             (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14             (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15             (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16             (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17             (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18             (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19             (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20             (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21             (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22             (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23             (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24             (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25             (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26             (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27             (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28             (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29             (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PB0              (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1              (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2              (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3              (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4              (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5              (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6              (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7              (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8              (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9              (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10             (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11             (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12             (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13             (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14             (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15             (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16             (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17             (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18             (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19             (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20             (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21             (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22             (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23             (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24             (1u << 24) /**< \brief Pin Controlled by PB24 */
+#define PIO_PB25             (1u << 25) /**< \brief Pin Controlled by PB25 */
+#define PIO_PB26             (1u << 26) /**< \brief Pin Controlled by PB26 */
+#define PIO_PB27             (1u << 27) /**< \brief Pin Controlled by PB27 */
+#define PIO_PB28             (1u << 28) /**< \brief Pin Controlled by PB28 */
+#define PIO_PB29             (1u << 29) /**< \brief Pin Controlled by PB29 */
+#define PIO_PB30             (1u << 30) /**< \brief Pin Controlled by PB30 */
+#define PIO_PB31             (1u << 31) /**< \brief Pin Controlled by PB31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA2X1_AD0        (1u << 2)  /**< \brief Adc signal: AD0 */
+#define PIO_PA3X1_AD1        (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PA3X1_WKUP1      (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PB17X1_AD10      (1u << 17) /**< \brief Adc signal: AD10 */
+#define PIO_PB18X1_AD11      (1u << 18) /**< \brief Adc signal: AD11 */
+#define PIO_PB19X1_AD12      (1u << 19) /**< \brief Adc signal: AD12 */
+#define PIO_PB20X1_AD13      (1u << 20) /**< \brief Adc signal: AD13 */
+#define PIO_PB21X1_AD14      (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PB21X1_WKUP13    (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PA4X1_AD2        (1u << 4)  /**< \brief Adc signal: AD2 */
+#define PIO_PA6X1_AD3        (1u << 6)  /**< \brief Adc signal: AD3 */
+#define PIO_PA22X1_AD4       (1u << 22) /**< \brief Adc signal: AD4 */
+#define PIO_PA23X1_AD5       (1u << 23) /**< \brief Adc signal: AD5 */
+#define PIO_PA24X1_AD6       (1u << 24) /**< \brief Adc signal: AD6 */
+#define PIO_PA16X1_AD7       (1u << 16) /**< \brief Adc signal: AD7 */
+#define PIO_PB12X1_AD8       (1u << 12) /**< \brief Adc signal: AD8 */
+#define PIO_PB13X1_AD9       (1u << 13) /**< \brief Adc signal: AD9 */
+#define PIO_PA11B_ADTRG      (1u << 11) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for CAN0 peripheral ========== */
+#define PIO_PA1A_CANRX0      (1u << 1)  /**< \brief Can0 signal: CANRX0 */
+#define PIO_PA0A_CANTX0      (1u << 0)  /**< \brief Can0 signal: CANTX0 */
+/* ========== Pio definition for CAN1 peripheral ========== */
+#define PIO_PB15A_CANRX1     (1u << 15) /**< \brief Can1 signal: CANRX1 */
+#define PIO_PB14A_CANTX1     (1u << 14) /**< \brief Can1 signal: CANTX1 */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB15X1_DAC0      (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB15X1_WKUP12    (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB16X1_DAC1      (1u << 16) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA10B_DATRG      (1u << 10) /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for EMAC peripheral ========== */
+#define PIO_PC13B_ECOL       (1u << 13) /**< \brief Emac signal: ECOL */
+#define PIO_PC10B_ECRS       (1u << 10) /**< \brief Emac signal: ECRS */
+#define PIO_PB4A_ECRSDV      (1u << 4)  /**< \brief Emac signal: ECRSDV/ERXDV */
+#define PIO_PB4A_ERXDV       (1u << 4)  /**< \brief Emac signal: ECRSDV/ERXDV */
+#define PIO_PB8A_EMDC        (1u << 8)  /**< \brief Emac signal: EMDC */
+#define PIO_PB9A_EMDIO       (1u << 9)  /**< \brief Emac signal: EMDIO */
+#define PIO_PB5A_ERX0        (1u << 5)  /**< \brief Emac signal: ERX0 */
+#define PIO_PB6A_ERX1        (1u << 6)  /**< \brief Emac signal: ERX1 */
+#define PIO_PC11B_ERX2       (1u << 11) /**< \brief Emac signal: ERX2 */
+#define PIO_PC12B_ERX3       (1u << 12) /**< \brief Emac signal: ERX3 */
+#define PIO_PC14B_ERXCK      (1u << 14) /**< \brief Emac signal: ERXCK */
+#define PIO_PB7A_ERXER       (1u << 7)  /**< \brief Emac signal: ERXER */
+#define PIO_PB2A_ETX0        (1u << 2)  /**< \brief Emac signal: ETX0 */
+#define PIO_PB3A_ETX1        (1u << 3)  /**< \brief Emac signal: ETX1 */
+#define PIO_PC15B_ETX2       (1u << 15) /**< \brief Emac signal: ETX2 */
+#define PIO_PC16B_ETX3       (1u << 16) /**< \brief Emac signal: ETX3 */
+#define PIO_PB0A_ETXCK       (1u << 0)  /**< \brief Emac signal: ETXCK */
+#define PIO_PB1A_ETXEN       (1u << 1)  /**< \brief Emac signal: ETXEN */
+#define PIO_PC17B_ETXER      (1u << 17) /**< \brief Emac signal: ETXER */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA20A_MCCDA      (1u << 20) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PE20B_MCCDB      (1u << 20) /**< \brief Hsmci signal: MCCDB */
+#define PIO_PA19A_MCCK       (1u << 19) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA21A_MCDA0      (1u << 21) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA22A_MCDA1      (1u << 22) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA23A_MCDA2      (1u << 23) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA24A_MCDA3      (1u << 24) /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PD0B_MCDA4       (1u << 0)  /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PD1B_MCDA5       (1u << 1)  /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PD2B_MCDA6       (1u << 2)  /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PD3B_MCDA7       (1u << 3)  /**< \brief Hsmci signal: MCDA7 */
+#define PIO_PE22B_MCDB0      (1u << 22) /**< \brief Hsmci signal: MCDB0 */
+#define PIO_PE24B_MCDB1      (1u << 24) /**< \brief Hsmci signal: MCDB1 */
+#define PIO_PE26B_MCDB2      (1u << 26) /**< \brief Hsmci signal: MCDB2 */
+#define PIO_PE27B_MCDB3      (1u << 27) /**< \brief Hsmci signal: MCDB3 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA1B_PCK0        (1u << 1)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB22B_PCK0       (1u << 22) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA24B_PCK1       (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA30B_PCK1       (1u << 30) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA28B_PCK2       (1u << 28) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2       (1u << 31) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA5B_PWMFI0      (1u << 5)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA3B_PWMFI1      (1u << 3)  /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PD6B_PWMFI2      (1u << 6)  /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA8B_PWMH0       (1u << 8)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB12B_PWMH0      (1u << 12) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC3B_PWMH0       (1u << 3)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PE15A_PWMH0      (1u << 15) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA19B_PWMH1      (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB13B_PWMH1      (1u << 13) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC5B_PWMH1       (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PE16A_PWMH1      (1u << 16) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA13B_PWMH2      (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB14B_PWMH2      (1u << 14) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC7B_PWMH2       (1u << 7)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB15B_PWMH3      (1u << 15) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PF3A_PWMH3       (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC20B_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PE20A_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PC19B_PWMH5      (1u << 19) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PE22A_PWMH5      (1u << 22) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PC18B_PWMH6      (1u << 18) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE24A_PWMH6      (1u << 24) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE26A_PWMH7      (1u << 26) /**< \brief Pwm signal: PWMH7 */
+#define PIO_PA21B_PWML0      (1u << 21) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB16B_PWML0      (1u << 16) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC2B_PWML0       (1u << 2)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PE18A_PWML0      (1u << 18) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA12B_PWML1      (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB17B_PWML1      (1u << 17) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC4B_PWML1       (1u << 4)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PA20B_PWML2      (1u << 20) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB18B_PWML2      (1u << 18) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC6B_PWML2       (1u << 6)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PE17A_PWML2      (1u << 17) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA0B_PWML3       (1u << 0)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB19B_PWML3      (1u << 19) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC8B_PWML3       (1u << 8)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB6B_PWML4       (1u << 6)  /**< \brief Pwm signal: PWML4 */
+#define PIO_PC21B_PWML4      (1u << 21) /**< \brief Pwm signal: PWML4 */
+#define PIO_PE19A_PWML4      (1u << 19) /**< \brief Pwm signal: PWML4 */
+#define PIO_PB7B_PWML5       (1u << 7)  /**< \brief Pwm signal: PWML5 */
+#define PIO_PC22B_PWML5      (1u << 22) /**< \brief Pwm signal: PWML5 */
+#define PIO_PE21A_PWML5      (1u << 21) /**< \brief Pwm signal: PWML5 */
+#define PIO_PB8B_PWML6       (1u << 8)  /**< \brief Pwm signal: PWML6 */
+#define PIO_PC23B_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PE23A_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PB9B_PWML7       (1u << 9)  /**< \brief Pwm signal: PWML7 */
+#define PIO_PC24B_PWML7      (1u << 24) /**< \brief Pwm signal: PWML7 */
+#define PIO_PE25A_PWML7      (1u << 25) /**< \brief Pwm signal: PWML7 */
+/* ========== Pio definition for SPI0 peripheral ========== */
+#define PIO_PA25A_SPI0_MISO  (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */
+#define PIO_PA26A_SPI0_MOSI  (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */
+#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */
+#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PA27A_SPI0_SPCK  (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PB18A_RD         (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PB17A_RF         (1u << 17) /**< \brief Ssc signal: RF */
+#define PIO_PB19A_RK         (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA16B_TD         (1u << 16) /**< \brief Ssc signal: TD */
+#define PIO_PA15B_TF         (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA14B_TK         (1u << 14) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PB26B_TCLK0      (1u << 26) /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA4A_TCLK1       (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA7A_TCLK2       (1u << 7)  /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PB25B_TIOA0      (1u << 25) /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA2A_TIOA1       (1u << 2)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA5A_TIOA2       (1u << 5)  /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PB27B_TIOB0      (1u << 27) /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA3A_TIOB1       (1u << 3)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA6A_TIOB2       (1u << 6)  /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PA22B_TCLK3      (1u << 22) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PA23B_TCLK4      (1u << 23) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PB16A_TCLK5      (1u << 16) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PB0B_TIOA3       (1u << 0)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PE9A_TIOA3       (1u << 9)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PB2B_TIOA4       (1u << 2)  /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PE11A_TIOA4      (1u << 11) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PB4B_TIOA5       (1u << 4)  /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PE13A_TIOA5      (1u << 13) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PB1B_TIOB3       (1u << 1)  /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PE10A_TIOB3      (1u << 10) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PB3B_TIOB4       (1u << 3)  /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PE12A_TIOB4      (1u << 12) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PB5B_TIOB5       (1u << 5)  /**< \brief Tc1 signal: TIOB5 */
+#define PIO_PE14A_TIOB5      (1u << 14) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA18A_TWCK0      (1u << 18) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA17A_TWD0       (1u << 17) /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB13A_TWCK1      (1u << 13) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB12A_TWD1       (1u << 12) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA8A_URXD        (1u << 8)  /**< \brief Uart signal: URXD */
+#define PIO_PA9A_UTXD        (1u << 9)  /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for UOTGHS peripheral ========== */
+#define PIO_PB11A_UOTGID     (1u << 11) /**< \brief Uotghs signal: UOTGID */
+#define PIO_PB10A_UOTGVBOF   (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB26A_CTS0       (1u << 26) /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB25A_RTS0       (1u << 25) /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA10A_RXD0       (1u << 10) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17B_SCK0       (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA11A_TXD0       (1u << 11) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA15A_CTS1       (1u << 15) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA14A_RTS1       (1u << 14) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA12A_RXD1       (1u << 12) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA16A_SCK1       (1u << 16) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA13A_TXD1       (1u << 13) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB23A_CTS2       (1u << 23) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB22A_RTS2       (1u << 22) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PB21A_RXD2       (1u << 21) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PB24A_SCK2       (1u << 24) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PB20A_TXD2       (1u << 20) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX          0
+#define PIO_PA1_IDX          1
+#define PIO_PA2_IDX          2
+#define PIO_PA3_IDX          3
+#define PIO_PA4_IDX          4
+#define PIO_PA5_IDX          5
+#define PIO_PA6_IDX          6
+#define PIO_PA7_IDX          7
+#define PIO_PA8_IDX          8
+#define PIO_PA9_IDX          9
+#define PIO_PA10_IDX         10
+#define PIO_PA11_IDX         11
+#define PIO_PA12_IDX         12
+#define PIO_PA13_IDX         13
+#define PIO_PA14_IDX         14
+#define PIO_PA15_IDX         15
+#define PIO_PA16_IDX         16
+#define PIO_PA17_IDX         17
+#define PIO_PA18_IDX         18
+#define PIO_PA19_IDX         19
+#define PIO_PA20_IDX         20
+#define PIO_PA21_IDX         21
+#define PIO_PA22_IDX         22
+#define PIO_PA23_IDX         23
+#define PIO_PA24_IDX         24
+#define PIO_PA25_IDX         25
+#define PIO_PA26_IDX         26
+#define PIO_PA27_IDX         27
+#define PIO_PA28_IDX         28
+#define PIO_PA29_IDX         29
+#define PIO_PB0_IDX          32
+#define PIO_PB1_IDX          33
+#define PIO_PB2_IDX          34
+#define PIO_PB3_IDX          35
+#define PIO_PB4_IDX          36
+#define PIO_PB5_IDX          37
+#define PIO_PB6_IDX          38
+#define PIO_PB7_IDX          39
+#define PIO_PB8_IDX          40
+#define PIO_PB9_IDX          41
+#define PIO_PB10_IDX         42
+#define PIO_PB11_IDX         43
+#define PIO_PB12_IDX         44
+#define PIO_PB13_IDX         45
+#define PIO_PB14_IDX         46
+#define PIO_PB15_IDX         47
+#define PIO_PB16_IDX         48
+#define PIO_PB17_IDX         49
+#define PIO_PB18_IDX         50
+#define PIO_PB19_IDX         51
+#define PIO_PB20_IDX         52
+#define PIO_PB21_IDX         53
+#define PIO_PB22_IDX         54
+#define PIO_PB23_IDX         55
+#define PIO_PB24_IDX         56
+#define PIO_PB25_IDX         57
+#define PIO_PB26_IDX         58
+#define PIO_PB27_IDX         59
+#define PIO_PB28_IDX         60
+#define PIO_PB29_IDX         61
+#define PIO_PB30_IDX         62
+#define PIO_PB31_IDX         63
+
+#endif /* _SAM3X4C_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x4e.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x4e.h
new file mode 100644
index 000000000..19d8355dc
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x4e.h
@@ -0,0 +1,552 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3X4E_PIO_
+#define _SAM3X4E_PIO_
+
+#define PIO_PA0              (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1              (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2              (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3              (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4              (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5              (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6              (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7              (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8              (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9              (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10             (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11             (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12             (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13             (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14             (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15             (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16             (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17             (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18             (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19             (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20             (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21             (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22             (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23             (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24             (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25             (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26             (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27             (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28             (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29             (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PB0              (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1              (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2              (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3              (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4              (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5              (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6              (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7              (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8              (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9              (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10             (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11             (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12             (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13             (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14             (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15             (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16             (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17             (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18             (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19             (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20             (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21             (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22             (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23             (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24             (1u << 24) /**< \brief Pin Controlled by PB24 */
+#define PIO_PB25             (1u << 25) /**< \brief Pin Controlled by PB25 */
+#define PIO_PB26             (1u << 26) /**< \brief Pin Controlled by PB26 */
+#define PIO_PB27             (1u << 27) /**< \brief Pin Controlled by PB27 */
+#define PIO_PB28             (1u << 28) /**< \brief Pin Controlled by PB28 */
+#define PIO_PB29             (1u << 29) /**< \brief Pin Controlled by PB29 */
+#define PIO_PB30             (1u << 30) /**< \brief Pin Controlled by PB30 */
+#define PIO_PB31             (1u << 31) /**< \brief Pin Controlled by PB31 */
+#define PIO_PC0              (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1              (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2              (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3              (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4              (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5              (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6              (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7              (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8              (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9              (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10             (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11             (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12             (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13             (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14             (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15             (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16             (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17             (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18             (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19             (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20             (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21             (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22             (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23             (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24             (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25             (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26             (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27             (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28             (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29             (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30             (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PD0              (1u << 0)  /**< \brief Pin Controlled by PD0 */
+#define PIO_PD1              (1u << 1)  /**< \brief Pin Controlled by PD1 */
+#define PIO_PD2              (1u << 2)  /**< \brief Pin Controlled by PD2 */
+#define PIO_PD3              (1u << 3)  /**< \brief Pin Controlled by PD3 */
+#define PIO_PD4              (1u << 4)  /**< \brief Pin Controlled by PD4 */
+#define PIO_PD5              (1u << 5)  /**< \brief Pin Controlled by PD5 */
+#define PIO_PD6              (1u << 6)  /**< \brief Pin Controlled by PD6 */
+#define PIO_PD7              (1u << 7)  /**< \brief Pin Controlled by PD7 */
+#define PIO_PD8              (1u << 8)  /**< \brief Pin Controlled by PD8 */
+#define PIO_PD9              (1u << 9)  /**< \brief Pin Controlled by PD9 */
+#define PIO_PD10             (1u << 10) /**< \brief Pin Controlled by PD10 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA2X1_AD0        (1u << 2)  /**< \brief Adc signal: AD0 */
+#define PIO_PA3X1_AD1        (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PA3X1_WKUP1      (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PB17X1_AD10      (1u << 17) /**< \brief Adc signal: AD10 */
+#define PIO_PB18X1_AD11      (1u << 18) /**< \brief Adc signal: AD11 */
+#define PIO_PB19X1_AD12      (1u << 19) /**< \brief Adc signal: AD12 */
+#define PIO_PB20X1_AD13      (1u << 20) /**< \brief Adc signal: AD13 */
+#define PIO_PB21X1_AD14      (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PB21X1_WKUP13    (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PA4X1_AD2        (1u << 4)  /**< \brief Adc signal: AD2 */
+#define PIO_PA6X1_AD3        (1u << 6)  /**< \brief Adc signal: AD3 */
+#define PIO_PA22X1_AD4       (1u << 22) /**< \brief Adc signal: AD4 */
+#define PIO_PA23X1_AD5       (1u << 23) /**< \brief Adc signal: AD5 */
+#define PIO_PA24X1_AD6       (1u << 24) /**< \brief Adc signal: AD6 */
+#define PIO_PA16X1_AD7       (1u << 16) /**< \brief Adc signal: AD7 */
+#define PIO_PB12X1_AD8       (1u << 12) /**< \brief Adc signal: AD8 */
+#define PIO_PB13X1_AD9       (1u << 13) /**< \brief Adc signal: AD9 */
+#define PIO_PA11B_ADTRG      (1u << 11) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for CAN0 peripheral ========== */
+#define PIO_PA1A_CANRX0      (1u << 1)  /**< \brief Can0 signal: CANRX0 */
+#define PIO_PA0A_CANTX0      (1u << 0)  /**< \brief Can0 signal: CANTX0 */
+/* ========== Pio definition for CAN1 peripheral ========== */
+#define PIO_PB15A_CANRX1     (1u << 15) /**< \brief Can1 signal: CANRX1 */
+#define PIO_PB14A_CANTX1     (1u << 14) /**< \brief Can1 signal: CANTX1 */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB15X1_DAC0      (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB15X1_WKUP12    (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB16X1_DAC1      (1u << 16) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA10B_DATRG      (1u << 10) /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PC21A_A0         (1u << 21) /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PC21A_NBS0       (1u << 21) /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PC22A_A1         (1u << 22) /**< \brief Ebi signal: A1 */
+#define PIO_PD0A_A10         (1u << 0)  /**< \brief Ebi signal: A10 */
+#define PIO_PD22A_A10        (1u << 22) /**< \brief Ebi signal: A10 */
+#define PIO_PD1A_A11         (1u << 1)  /**< \brief Ebi signal: A11 */
+#define PIO_PD23A_A11        (1u << 23) /**< \brief Ebi signal: A11 */
+#define PIO_PD2A_A12         (1u << 2)  /**< \brief Ebi signal: A12 */
+#define PIO_PD24A_A12        (1u << 24) /**< \brief Ebi signal: A12 */
+#define PIO_PD3A_A13         (1u << 3)  /**< \brief Ebi signal: A13 */
+#define PIO_PD25A_A13        (1u << 25) /**< \brief Ebi signal: A13 */
+#define PIO_PD4A_A14         (1u << 4)  /**< \brief Ebi signal: A14 */
+#define PIO_PD26A_A14        (1u << 26) /**< \brief Ebi signal: A14 */
+#define PIO_PD5A_A15         (1u << 5)  /**< \brief Ebi signal: A15 */
+#define PIO_PD27A_A15        (1u << 27) /**< \brief Ebi signal: A15 */
+#define PIO_PD6A_A16         (1u << 6)  /**< \brief Ebi signal: A16/BA0 */
+#define PIO_PD6A_BA0         (1u << 6)  /**< \brief Ebi signal: A16/BA0 */
+#define PIO_PD28A_A16        (1u << 28) /**< \brief Ebi signal: A16/BA0 */
+#define PIO_PD28A_BA0        (1u << 28) /**< \brief Ebi signal: A16/BA0 */
+#define PIO_PD7A_A17         (1u << 7)  /**< \brief Ebi signal: A17/BA1 */
+#define PIO_PD7A_BA1         (1u << 7)  /**< \brief Ebi signal: A17/BA1 */
+#define PIO_PD29A_A17        (1u << 29) /**< \brief Ebi signal: A17/BA1 */
+#define PIO_PD29A_BA1        (1u << 29) /**< \brief Ebi signal: A17/BA1 */
+#define PIO_PA25B_A18        (1u << 25) /**< \brief Ebi signal: A18 */
+#define PIO_PB10B_A18        (1u << 10) /**< \brief Ebi signal: A18 */
+#define PIO_PD30A_A18        (1u << 30) /**< \brief Ebi signal: A18 */
+#define PIO_PA26B_A19        (1u << 26) /**< \brief Ebi signal: A19 */
+#define PIO_PB11B_A19        (1u << 11) /**< \brief Ebi signal: A19 */
+#define PIO_PE0A_A19         (1u << 0)  /**< \brief Ebi signal: A19 */
+#define PIO_PC23A_A2         (1u << 23) /**< \brief Ebi signal: A2 */
+#define PIO_PA18B_A20        (1u << 18) /**< \brief Ebi signal: A20 */
+#define PIO_PA27B_A20        (1u << 27) /**< \brief Ebi signal: A20 */
+#define PIO_PE1A_A20         (1u << 1)  /**< \brief Ebi signal: A20 */
+#define PIO_PD8A_A21         (1u << 8)  /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PD8A_NANDALE     (1u << 8)  /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PE2A_A21         (1u << 2)  /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PE2A_NANDALE     (1u << 2)  /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PD9A_A22         (1u << 9)  /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PD9A_NANDCLE     (1u << 9)  /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PE3A_A22         (1u << 3)  /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PE3A_NANDCLE     (1u << 3)  /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PE4A_A23         (1u << 4)  /**< \brief Ebi signal: A23 */
+#define PIO_PC24A_A3         (1u << 24) /**< \brief Ebi signal: A3 */
+#define PIO_PC25A_A4         (1u << 25) /**< \brief Ebi signal: A4 */
+#define PIO_PC26A_A5         (1u << 26) /**< \brief Ebi signal: A5 */
+#define PIO_PD17A_A5         (1u << 17) /**< \brief Ebi signal: A5 */
+#define PIO_PC27A_A6         (1u << 27) /**< \brief Ebi signal: A6 */
+#define PIO_PD18A_A6         (1u << 18) /**< \brief Ebi signal: A6 */
+#define PIO_PC28A_A7         (1u << 28) /**< \brief Ebi signal: A7 */
+#define PIO_PD19A_A7         (1u << 19) /**< \brief Ebi signal: A7 */
+#define PIO_PC29A_A8         (1u << 29) /**< \brief Ebi signal: A8 */
+#define PIO_PD20A_A8         (1u << 20) /**< \brief Ebi signal: A8 */
+#define PIO_PC30A_A9         (1u << 30) /**< \brief Ebi signal: A9 */
+#define PIO_PD21A_A9         (1u << 21) /**< \brief Ebi signal: A9 */
+#define PIO_PD16A_CAS        (1u << 16) /**< \brief Ebi signal: CAS */
+#define PIO_PC2A_D0          (1u << 2)  /**< \brief Ebi signal: D0 */
+#define PIO_PC3A_D1          (1u << 3)  /**< \brief Ebi signal: D1 */
+#define PIO_PC12A_D10        (1u << 12) /**< \brief Ebi signal: D10 */
+#define PIO_PC13A_D11        (1u << 13) /**< \brief Ebi signal: D11 */
+#define PIO_PC14A_D12        (1u << 14) /**< \brief Ebi signal: D12 */
+#define PIO_PC15A_D13        (1u << 15) /**< \brief Ebi signal: D13 */
+#define PIO_PC16A_D14        (1u << 16) /**< \brief Ebi signal: D14 */
+#define PIO_PC17A_D15        (1u << 17) /**< \brief Ebi signal: D15 */
+#define PIO_PC4A_D2          (1u << 4)  /**< \brief Ebi signal: D2 */
+#define PIO_PC5A_D3          (1u << 5)  /**< \brief Ebi signal: D3 */
+#define PIO_PC6A_D4          (1u << 6)  /**< \brief Ebi signal: D4 */
+#define PIO_PC7A_D5          (1u << 7)  /**< \brief Ebi signal: D5 */
+#define PIO_PC8A_D6          (1u << 8)  /**< \brief Ebi signal: D6 */
+#define PIO_PC9A_D7          (1u << 9)  /**< \brief Ebi signal: D7 */
+#define PIO_PC10A_D8         (1u << 10) /**< \brief Ebi signal: D8 */
+#define PIO_PC11A_D9         (1u << 11) /**< \brief Ebi signal: D9 */
+#define PIO_PC19A_NANDOE     (1u << 19) /**< \brief Ebi signal: NANDOE */
+#define PIO_PA2B_NANDRDY     (1u << 2)  /**< \brief Ebi signal: NANDRDY */
+#define PIO_PC20A_NANDWE     (1u << 20) /**< \brief Ebi signal: NANDWE */
+#define PIO_PA6B_NCS0        (1u << 6)  /**< \brief Ebi signal: NCS0 */
+#define PIO_PA7B_NCS1        (1u << 7)  /**< \brief Ebi signal: NCS1 */
+#define PIO_PB24B_NCS2       (1u << 24) /**< \brief Ebi signal: NCS2 */
+#define PIO_PB27A_NCS3       (1u << 27) /**< \brief Ebi signal: NCS3 */
+#define PIO_PE5A_NCS4        (1u << 5)  /**< \brief Ebi signal: NCS4 */
+#define PIO_PE6A_NCS5        (1u << 6)  /**< \brief Ebi signal: NCS5 */
+#define PIO_PE18B_NCS6       (1u << 18) /**< \brief Ebi signal: NCS6 */
+#define PIO_PE27A_NCS7       (1u << 27) /**< \brief Ebi signal: NCS7 */
+#define PIO_PA29B_NRD        (1u << 29) /**< \brief Ebi signal: NRD */
+#define PIO_PA4B_NWAIT       (1u << 4)  /**< \brief Ebi signal: NWAIT */
+#define PIO_PC18A_NWR0       (1u << 18) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PC18A_NWE        (1u << 18) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PD10A_NWR1       (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */
+#define PIO_PD10A_NBS1       (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */
+#define PIO_PD15A_RAS        (1u << 15) /**< \brief Ebi signal: RAS */
+#define PIO_PD11A_SDA10      (1u << 11) /**< \brief Ebi signal: SDA10 */
+#define PIO_PD13A_SDCKE      (1u << 13) /**< \brief Ebi signal: SDCKE */
+#define PIO_PD12A_SDCS       (1u << 12) /**< \brief Ebi signal: SDCS */
+#define PIO_PD14A_SDWE       (1u << 14) /**< \brief Ebi signal: SDWE */
+/* ========== Pio definition for EMAC peripheral ========== */
+#define PIO_PC13B_ECOL       (1u << 13) /**< \brief Emac signal: ECOL */
+#define PIO_PC10B_ECRS       (1u << 10) /**< \brief Emac signal: ECRS */
+#define PIO_PB4A_ECRSDV      (1u << 4)  /**< \brief Emac signal: ECRSDV/ERXDV */
+#define PIO_PB4A_ERXDV       (1u << 4)  /**< \brief Emac signal: ECRSDV/ERXDV */
+#define PIO_PB8A_EMDC        (1u << 8)  /**< \brief Emac signal: EMDC */
+#define PIO_PB9A_EMDIO       (1u << 9)  /**< \brief Emac signal: EMDIO */
+#define PIO_PB5A_ERX0        (1u << 5)  /**< \brief Emac signal: ERX0 */
+#define PIO_PB6A_ERX1        (1u << 6)  /**< \brief Emac signal: ERX1 */
+#define PIO_PC11B_ERX2       (1u << 11) /**< \brief Emac signal: ERX2 */
+#define PIO_PC12B_ERX3       (1u << 12) /**< \brief Emac signal: ERX3 */
+#define PIO_PC14B_ERXCK      (1u << 14) /**< \brief Emac signal: ERXCK */
+#define PIO_PB7A_ERXER       (1u << 7)  /**< \brief Emac signal: ERXER */
+#define PIO_PB2A_ETX0        (1u << 2)  /**< \brief Emac signal: ETX0 */
+#define PIO_PB3A_ETX1        (1u << 3)  /**< \brief Emac signal: ETX1 */
+#define PIO_PC15B_ETX2       (1u << 15) /**< \brief Emac signal: ETX2 */
+#define PIO_PC16B_ETX3       (1u << 16) /**< \brief Emac signal: ETX3 */
+#define PIO_PB0A_ETXCK       (1u << 0)  /**< \brief Emac signal: ETXCK */
+#define PIO_PB1A_ETXEN       (1u << 1)  /**< \brief Emac signal: ETXEN */
+#define PIO_PC17B_ETXER      (1u << 17) /**< \brief Emac signal: ETXER */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA20A_MCCDA      (1u << 20) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PE20B_MCCDB      (1u << 20) /**< \brief Hsmci signal: MCCDB */
+#define PIO_PA19A_MCCK       (1u << 19) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA21A_MCDA0      (1u << 21) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA22A_MCDA1      (1u << 22) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA23A_MCDA2      (1u << 23) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA24A_MCDA3      (1u << 24) /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PD0B_MCDA4       (1u << 0)  /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PD1B_MCDA5       (1u << 1)  /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PD2B_MCDA6       (1u << 2)  /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PD3B_MCDA7       (1u << 3)  /**< \brief Hsmci signal: MCDA7 */
+#define PIO_PE22B_MCDB0      (1u << 22) /**< \brief Hsmci signal: MCDB0 */
+#define PIO_PE24B_MCDB1      (1u << 24) /**< \brief Hsmci signal: MCDB1 */
+#define PIO_PE26B_MCDB2      (1u << 26) /**< \brief Hsmci signal: MCDB2 */
+#define PIO_PE27B_MCDB3      (1u << 27) /**< \brief Hsmci signal: MCDB3 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA1B_PCK0        (1u << 1)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB22B_PCK0       (1u << 22) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA24B_PCK1       (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA30B_PCK1       (1u << 30) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA28B_PCK2       (1u << 28) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2       (1u << 31) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA5B_PWMFI0      (1u << 5)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA3B_PWMFI1      (1u << 3)  /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PD6B_PWMFI2      (1u << 6)  /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA8B_PWMH0       (1u << 8)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB12B_PWMH0      (1u << 12) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC3B_PWMH0       (1u << 3)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PE15A_PWMH0      (1u << 15) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA19B_PWMH1      (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB13B_PWMH1      (1u << 13) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC5B_PWMH1       (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PE16A_PWMH1      (1u << 16) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA13B_PWMH2      (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB14B_PWMH2      (1u << 14) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC7B_PWMH2       (1u << 7)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB15B_PWMH3      (1u << 15) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PF3A_PWMH3       (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC20B_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PE20A_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PC19B_PWMH5      (1u << 19) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PE22A_PWMH5      (1u << 22) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PC18B_PWMH6      (1u << 18) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE24A_PWMH6      (1u << 24) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE26A_PWMH7      (1u << 26) /**< \brief Pwm signal: PWMH7 */
+#define PIO_PA21B_PWML0      (1u << 21) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB16B_PWML0      (1u << 16) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC2B_PWML0       (1u << 2)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PE18A_PWML0      (1u << 18) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA12B_PWML1      (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB17B_PWML1      (1u << 17) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC4B_PWML1       (1u << 4)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PA20B_PWML2      (1u << 20) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB18B_PWML2      (1u << 18) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC6B_PWML2       (1u << 6)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PE17A_PWML2      (1u << 17) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA0B_PWML3       (1u << 0)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB19B_PWML3      (1u << 19) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC8B_PWML3       (1u << 8)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB6B_PWML4       (1u << 6)  /**< \brief Pwm signal: PWML4 */
+#define PIO_PC21B_PWML4      (1u << 21) /**< \brief Pwm signal: PWML4 */
+#define PIO_PE19A_PWML4      (1u << 19) /**< \brief Pwm signal: PWML4 */
+#define PIO_PB7B_PWML5       (1u << 7)  /**< \brief Pwm signal: PWML5 */
+#define PIO_PC22B_PWML5      (1u << 22) /**< \brief Pwm signal: PWML5 */
+#define PIO_PE21A_PWML5      (1u << 21) /**< \brief Pwm signal: PWML5 */
+#define PIO_PB8B_PWML6       (1u << 8)  /**< \brief Pwm signal: PWML6 */
+#define PIO_PC23B_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PE23A_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PB9B_PWML7       (1u << 9)  /**< \brief Pwm signal: PWML7 */
+#define PIO_PC24B_PWML7      (1u << 24) /**< \brief Pwm signal: PWML7 */
+#define PIO_PE25A_PWML7      (1u << 25) /**< \brief Pwm signal: PWML7 */
+/* ========== Pio definition for SPI0 peripheral ========== */
+#define PIO_PA25A_SPI0_MISO  (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */
+#define PIO_PA26A_SPI0_MOSI  (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */
+#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */
+#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PA27A_SPI0_SPCK  (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PB18A_RD         (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PB17A_RF         (1u << 17) /**< \brief Ssc signal: RF */
+#define PIO_PB19A_RK         (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA16B_TD         (1u << 16) /**< \brief Ssc signal: TD */
+#define PIO_PA15B_TF         (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA14B_TK         (1u << 14) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PB26B_TCLK0      (1u << 26) /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA4A_TCLK1       (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA7A_TCLK2       (1u << 7)  /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PB25B_TIOA0      (1u << 25) /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA2A_TIOA1       (1u << 2)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA5A_TIOA2       (1u << 5)  /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PB27B_TIOB0      (1u << 27) /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA3A_TIOB1       (1u << 3)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA6A_TIOB2       (1u << 6)  /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PA22B_TCLK3      (1u << 22) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PA23B_TCLK4      (1u << 23) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PB16A_TCLK5      (1u << 16) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PB0B_TIOA3       (1u << 0)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PE9A_TIOA3       (1u << 9)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PB2B_TIOA4       (1u << 2)  /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PE11A_TIOA4      (1u << 11) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PB4B_TIOA5       (1u << 4)  /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PE13A_TIOA5      (1u << 13) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PB1B_TIOB3       (1u << 1)  /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PE10A_TIOB3      (1u << 10) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PB3B_TIOB4       (1u << 3)  /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PE12A_TIOB4      (1u << 12) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PB5B_TIOB5       (1u << 5)  /**< \brief Tc1 signal: TIOB5 */
+#define PIO_PE14A_TIOB5      (1u << 14) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TC2 peripheral ========== */
+#define PIO_PC27B_TCLK6      (1u << 27) /**< \brief Tc2 signal: TCLK6 */
+#define PIO_PC30B_TCLK7      (1u << 30) /**< \brief Tc2 signal: TCLK7 */
+#define PIO_PD9B_TCLK8       (1u << 9)  /**< \brief Tc2 signal: TCLK8 */
+#define PIO_PC25B_TIOA6      (1u << 25) /**< \brief Tc2 signal: TIOA6 */
+#define PIO_PC28B_TIOA7      (1u << 28) /**< \brief Tc2 signal: TIOA7 */
+#define PIO_PD7B_TIOA8       (1u << 7)  /**< \brief Tc2 signal: TIOA8 */
+#define PIO_PC26B_TIOB6      (1u << 26) /**< \brief Tc2 signal: TIOB6 */
+#define PIO_PC29B_TIOB7      (1u << 29) /**< \brief Tc2 signal: TIOB7 */
+#define PIO_PD8B_TIOB8       (1u << 8)  /**< \brief Tc2 signal: TIOB8 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA18A_TWCK0      (1u << 18) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA17A_TWD0       (1u << 17) /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB13A_TWCK1      (1u << 13) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB12A_TWD1       (1u << 12) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA8A_URXD        (1u << 8)  /**< \brief Uart signal: URXD */
+#define PIO_PA9A_UTXD        (1u << 9)  /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for UOTGHS peripheral ========== */
+#define PIO_PB11A_UOTGID     (1u << 11) /**< \brief Uotghs signal: UOTGID */
+#define PIO_PB10A_UOTGVBOF   (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB26A_CTS0       (1u << 26) /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB25A_RTS0       (1u << 25) /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA10A_RXD0       (1u << 10) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17B_SCK0       (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA11A_TXD0       (1u << 11) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA15A_CTS1       (1u << 15) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA14A_RTS1       (1u << 14) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA12A_RXD1       (1u << 12) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA16A_SCK1       (1u << 16) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA13A_TXD1       (1u << 13) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB23A_CTS2       (1u << 23) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB22A_RTS2       (1u << 22) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PB21A_RXD2       (1u << 21) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PB24A_SCK2       (1u << 24) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PB20A_TXD2       (1u << 20) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio definition for USART3 peripheral ========== */
+#define PIO_PF4A_CTS3        (1u << 4)  /**< \brief Usart3 signal: CTS3 */
+#define PIO_PF5A_RTS3        (1u << 5)  /**< \brief Usart3 signal: RTS3 */
+#define PIO_PD5B_RXD3        (1u << 5)  /**< \brief Usart3 signal: RXD3 */
+#define PIO_PE16B_SCK3       (1u << 16) /**< \brief Usart3 signal: SCK3 */
+#define PIO_PD4B_TXD3        (1u << 4)  /**< \brief Usart3 signal: TXD3 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX          0
+#define PIO_PA1_IDX          1
+#define PIO_PA2_IDX          2
+#define PIO_PA3_IDX          3
+#define PIO_PA4_IDX          4
+#define PIO_PA5_IDX          5
+#define PIO_PA6_IDX          6
+#define PIO_PA7_IDX          7
+#define PIO_PA8_IDX          8
+#define PIO_PA9_IDX          9
+#define PIO_PA10_IDX         10
+#define PIO_PA11_IDX         11
+#define PIO_PA12_IDX         12
+#define PIO_PA13_IDX         13
+#define PIO_PA14_IDX         14
+#define PIO_PA15_IDX         15
+#define PIO_PA16_IDX         16
+#define PIO_PA17_IDX         17
+#define PIO_PA18_IDX         18
+#define PIO_PA19_IDX         19
+#define PIO_PA20_IDX         20
+#define PIO_PA21_IDX         21
+#define PIO_PA22_IDX         22
+#define PIO_PA23_IDX         23
+#define PIO_PA24_IDX         24
+#define PIO_PA25_IDX         25
+#define PIO_PA26_IDX         26
+#define PIO_PA27_IDX         27
+#define PIO_PA28_IDX         28
+#define PIO_PA29_IDX         29
+#define PIO_PB0_IDX          32
+#define PIO_PB1_IDX          33
+#define PIO_PB2_IDX          34
+#define PIO_PB3_IDX          35
+#define PIO_PB4_IDX          36
+#define PIO_PB5_IDX          37
+#define PIO_PB6_IDX          38
+#define PIO_PB7_IDX          39
+#define PIO_PB8_IDX          40
+#define PIO_PB9_IDX          41
+#define PIO_PB10_IDX         42
+#define PIO_PB11_IDX         43
+#define PIO_PB12_IDX         44
+#define PIO_PB13_IDX         45
+#define PIO_PB14_IDX         46
+#define PIO_PB15_IDX         47
+#define PIO_PB16_IDX         48
+#define PIO_PB17_IDX         49
+#define PIO_PB18_IDX         50
+#define PIO_PB19_IDX         51
+#define PIO_PB20_IDX         52
+#define PIO_PB21_IDX         53
+#define PIO_PB22_IDX         54
+#define PIO_PB23_IDX         55
+#define PIO_PB24_IDX         56
+#define PIO_PB25_IDX         57
+#define PIO_PB26_IDX         58
+#define PIO_PB27_IDX         59
+#define PIO_PB28_IDX         60
+#define PIO_PB29_IDX         61
+#define PIO_PB30_IDX         62
+#define PIO_PB31_IDX         63
+#define PIO_PC0_IDX          64
+#define PIO_PC1_IDX          65
+#define PIO_PC2_IDX          66
+#define PIO_PC3_IDX          67
+#define PIO_PC4_IDX          68
+#define PIO_PC5_IDX          69
+#define PIO_PC6_IDX          70
+#define PIO_PC7_IDX          71
+#define PIO_PC8_IDX          72
+#define PIO_PC9_IDX          73
+#define PIO_PC10_IDX         74
+#define PIO_PC11_IDX         75
+#define PIO_PC12_IDX         76
+#define PIO_PC13_IDX         77
+#define PIO_PC14_IDX         78
+#define PIO_PC15_IDX         79
+#define PIO_PC16_IDX         80
+#define PIO_PC17_IDX         81
+#define PIO_PC18_IDX         82
+#define PIO_PC19_IDX         83
+#define PIO_PC20_IDX         84
+#define PIO_PC21_IDX         85
+#define PIO_PC22_IDX         86
+#define PIO_PC23_IDX         87
+#define PIO_PC24_IDX         88
+#define PIO_PC25_IDX         89
+#define PIO_PC26_IDX         90
+#define PIO_PC27_IDX         91
+#define PIO_PC28_IDX         92
+#define PIO_PC29_IDX         93
+#define PIO_PC30_IDX         94
+#define PIO_PD0_IDX          96
+#define PIO_PD1_IDX          97
+#define PIO_PD2_IDX          98
+#define PIO_PD3_IDX          99
+#define PIO_PD4_IDX          100
+#define PIO_PD5_IDX          101
+#define PIO_PD6_IDX          102
+#define PIO_PD7_IDX          103
+#define PIO_PD8_IDX          104
+#define PIO_PD9_IDX          105
+#define PIO_PD10_IDX         106
+
+#endif /* _SAM3X4E_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x8c.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x8c.h
new file mode 100644
index 000000000..023fd5416
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x8c.h
@@ -0,0 +1,358 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3X8C_PIO_
+#define _SAM3X8C_PIO_
+
+#define PIO_PA0              (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1              (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2              (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3              (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4              (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5              (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6              (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7              (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8              (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9              (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10             (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11             (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12             (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13             (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14             (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15             (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16             (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17             (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18             (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19             (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20             (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21             (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22             (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23             (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24             (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25             (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26             (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27             (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28             (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29             (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PB0              (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1              (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2              (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3              (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4              (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5              (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6              (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7              (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8              (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9              (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10             (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11             (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12             (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13             (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14             (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15             (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16             (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17             (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18             (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19             (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20             (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21             (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22             (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23             (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24             (1u << 24) /**< \brief Pin Controlled by PB24 */
+#define PIO_PB25             (1u << 25) /**< \brief Pin Controlled by PB25 */
+#define PIO_PB26             (1u << 26) /**< \brief Pin Controlled by PB26 */
+#define PIO_PB27             (1u << 27) /**< \brief Pin Controlled by PB27 */
+#define PIO_PB28             (1u << 28) /**< \brief Pin Controlled by PB28 */
+#define PIO_PB29             (1u << 29) /**< \brief Pin Controlled by PB29 */
+#define PIO_PB30             (1u << 30) /**< \brief Pin Controlled by PB30 */
+#define PIO_PB31             (1u << 31) /**< \brief Pin Controlled by PB31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA2X1_AD0        (1u << 2)  /**< \brief Adc signal: AD0 */
+#define PIO_PA3X1_AD1        (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PA3X1_WKUP1      (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PB17X1_AD10      (1u << 17) /**< \brief Adc signal: AD10 */
+#define PIO_PB18X1_AD11      (1u << 18) /**< \brief Adc signal: AD11 */
+#define PIO_PB19X1_AD12      (1u << 19) /**< \brief Adc signal: AD12 */
+#define PIO_PB20X1_AD13      (1u << 20) /**< \brief Adc signal: AD13 */
+#define PIO_PB21X1_AD14      (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PB21X1_WKUP13    (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PA4X1_AD2        (1u << 4)  /**< \brief Adc signal: AD2 */
+#define PIO_PA6X1_AD3        (1u << 6)  /**< \brief Adc signal: AD3 */
+#define PIO_PA22X1_AD4       (1u << 22) /**< \brief Adc signal: AD4 */
+#define PIO_PA23X1_AD5       (1u << 23) /**< \brief Adc signal: AD5 */
+#define PIO_PA24X1_AD6       (1u << 24) /**< \brief Adc signal: AD6 */
+#define PIO_PA16X1_AD7       (1u << 16) /**< \brief Adc signal: AD7 */
+#define PIO_PB12X1_AD8       (1u << 12) /**< \brief Adc signal: AD8 */
+#define PIO_PB13X1_AD9       (1u << 13) /**< \brief Adc signal: AD9 */
+#define PIO_PA11B_ADTRG      (1u << 11) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for CAN0 peripheral ========== */
+#define PIO_PA1A_CANRX0      (1u << 1)  /**< \brief Can0 signal: CANRX0 */
+#define PIO_PA0A_CANTX0      (1u << 0)  /**< \brief Can0 signal: CANTX0 */
+/* ========== Pio definition for CAN1 peripheral ========== */
+#define PIO_PB15A_CANRX1     (1u << 15) /**< \brief Can1 signal: CANRX1 */
+#define PIO_PB14A_CANTX1     (1u << 14) /**< \brief Can1 signal: CANTX1 */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB15X1_DAC0      (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB15X1_WKUP12    (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB16X1_DAC1      (1u << 16) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA10B_DATRG      (1u << 10) /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for EMAC peripheral ========== */
+#define PIO_PC13B_ECOL       (1u << 13) /**< \brief Emac signal: ECOL */
+#define PIO_PC10B_ECRS       (1u << 10) /**< \brief Emac signal: ECRS */
+#define PIO_PB4A_ECRSDV      (1u << 4)  /**< \brief Emac signal: ECRSDV/ERXDV */
+#define PIO_PB4A_ERXDV       (1u << 4)  /**< \brief Emac signal: ECRSDV/ERXDV */
+#define PIO_PB8A_EMDC        (1u << 8)  /**< \brief Emac signal: EMDC */
+#define PIO_PB9A_EMDIO       (1u << 9)  /**< \brief Emac signal: EMDIO */
+#define PIO_PB5A_ERX0        (1u << 5)  /**< \brief Emac signal: ERX0 */
+#define PIO_PB6A_ERX1        (1u << 6)  /**< \brief Emac signal: ERX1 */
+#define PIO_PC11B_ERX2       (1u << 11) /**< \brief Emac signal: ERX2 */
+#define PIO_PC12B_ERX3       (1u << 12) /**< \brief Emac signal: ERX3 */
+#define PIO_PC14B_ERXCK      (1u << 14) /**< \brief Emac signal: ERXCK */
+#define PIO_PB7A_ERXER       (1u << 7)  /**< \brief Emac signal: ERXER */
+#define PIO_PB2A_ETX0        (1u << 2)  /**< \brief Emac signal: ETX0 */
+#define PIO_PB3A_ETX1        (1u << 3)  /**< \brief Emac signal: ETX1 */
+#define PIO_PC15B_ETX2       (1u << 15) /**< \brief Emac signal: ETX2 */
+#define PIO_PC16B_ETX3       (1u << 16) /**< \brief Emac signal: ETX3 */
+#define PIO_PB0A_ETXCK       (1u << 0)  /**< \brief Emac signal: ETXCK */
+#define PIO_PB1A_ETXEN       (1u << 1)  /**< \brief Emac signal: ETXEN */
+#define PIO_PC17B_ETXER      (1u << 17) /**< \brief Emac signal: ETXER */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA20A_MCCDA      (1u << 20) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PE20B_MCCDB      (1u << 20) /**< \brief Hsmci signal: MCCDB */
+#define PIO_PA19A_MCCK       (1u << 19) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA21A_MCDA0      (1u << 21) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA22A_MCDA1      (1u << 22) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA23A_MCDA2      (1u << 23) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA24A_MCDA3      (1u << 24) /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PD0B_MCDA4       (1u << 0)  /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PD1B_MCDA5       (1u << 1)  /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PD2B_MCDA6       (1u << 2)  /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PD3B_MCDA7       (1u << 3)  /**< \brief Hsmci signal: MCDA7 */
+#define PIO_PE22B_MCDB0      (1u << 22) /**< \brief Hsmci signal: MCDB0 */
+#define PIO_PE24B_MCDB1      (1u << 24) /**< \brief Hsmci signal: MCDB1 */
+#define PIO_PE26B_MCDB2      (1u << 26) /**< \brief Hsmci signal: MCDB2 */
+#define PIO_PE27B_MCDB3      (1u << 27) /**< \brief Hsmci signal: MCDB3 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA1B_PCK0        (1u << 1)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB22B_PCK0       (1u << 22) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA24B_PCK1       (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA30B_PCK1       (1u << 30) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA28B_PCK2       (1u << 28) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2       (1u << 31) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA5B_PWMFI0      (1u << 5)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA3B_PWMFI1      (1u << 3)  /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PD6B_PWMFI2      (1u << 6)  /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA8B_PWMH0       (1u << 8)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB12B_PWMH0      (1u << 12) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC3B_PWMH0       (1u << 3)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PE15A_PWMH0      (1u << 15) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA19B_PWMH1      (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB13B_PWMH1      (1u << 13) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC5B_PWMH1       (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PE16A_PWMH1      (1u << 16) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA13B_PWMH2      (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB14B_PWMH2      (1u << 14) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC7B_PWMH2       (1u << 7)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB15B_PWMH3      (1u << 15) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PF3A_PWMH3       (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC20B_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PE20A_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PC19B_PWMH5      (1u << 19) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PE22A_PWMH5      (1u << 22) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PC18B_PWMH6      (1u << 18) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE24A_PWMH6      (1u << 24) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE26A_PWMH7      (1u << 26) /**< \brief Pwm signal: PWMH7 */
+#define PIO_PA21B_PWML0      (1u << 21) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB16B_PWML0      (1u << 16) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC2B_PWML0       (1u << 2)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PE18A_PWML0      (1u << 18) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA12B_PWML1      (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB17B_PWML1      (1u << 17) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC4B_PWML1       (1u << 4)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PA20B_PWML2      (1u << 20) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB18B_PWML2      (1u << 18) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC6B_PWML2       (1u << 6)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PE17A_PWML2      (1u << 17) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA0B_PWML3       (1u << 0)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB19B_PWML3      (1u << 19) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC8B_PWML3       (1u << 8)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB6B_PWML4       (1u << 6)  /**< \brief Pwm signal: PWML4 */
+#define PIO_PC21B_PWML4      (1u << 21) /**< \brief Pwm signal: PWML4 */
+#define PIO_PE19A_PWML4      (1u << 19) /**< \brief Pwm signal: PWML4 */
+#define PIO_PB7B_PWML5       (1u << 7)  /**< \brief Pwm signal: PWML5 */
+#define PIO_PC22B_PWML5      (1u << 22) /**< \brief Pwm signal: PWML5 */
+#define PIO_PE21A_PWML5      (1u << 21) /**< \brief Pwm signal: PWML5 */
+#define PIO_PB8B_PWML6       (1u << 8)  /**< \brief Pwm signal: PWML6 */
+#define PIO_PC23B_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PE23A_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PB9B_PWML7       (1u << 9)  /**< \brief Pwm signal: PWML7 */
+#define PIO_PC24B_PWML7      (1u << 24) /**< \brief Pwm signal: PWML7 */
+#define PIO_PE25A_PWML7      (1u << 25) /**< \brief Pwm signal: PWML7 */
+/* ========== Pio definition for SPI0 peripheral ========== */
+#define PIO_PA25A_SPI0_MISO  (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */
+#define PIO_PA26A_SPI0_MOSI  (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */
+#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */
+#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PA27A_SPI0_SPCK  (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PB18A_RD         (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PB17A_RF         (1u << 17) /**< \brief Ssc signal: RF */
+#define PIO_PB19A_RK         (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA16B_TD         (1u << 16) /**< \brief Ssc signal: TD */
+#define PIO_PA15B_TF         (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA14B_TK         (1u << 14) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PB26B_TCLK0      (1u << 26) /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA4A_TCLK1       (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA7A_TCLK2       (1u << 7)  /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PB25B_TIOA0      (1u << 25) /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA2A_TIOA1       (1u << 2)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA5A_TIOA2       (1u << 5)  /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PB27B_TIOB0      (1u << 27) /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA3A_TIOB1       (1u << 3)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA6A_TIOB2       (1u << 6)  /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PA22B_TCLK3      (1u << 22) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PA23B_TCLK4      (1u << 23) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PB16A_TCLK5      (1u << 16) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PB0B_TIOA3       (1u << 0)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PE9A_TIOA3       (1u << 9)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PB2B_TIOA4       (1u << 2)  /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PE11A_TIOA4      (1u << 11) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PB4B_TIOA5       (1u << 4)  /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PE13A_TIOA5      (1u << 13) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PB1B_TIOB3       (1u << 1)  /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PE10A_TIOB3      (1u << 10) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PB3B_TIOB4       (1u << 3)  /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PE12A_TIOB4      (1u << 12) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PB5B_TIOB5       (1u << 5)  /**< \brief Tc1 signal: TIOB5 */
+#define PIO_PE14A_TIOB5      (1u << 14) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA18A_TWCK0      (1u << 18) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA17A_TWD0       (1u << 17) /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB13A_TWCK1      (1u << 13) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB12A_TWD1       (1u << 12) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA8A_URXD        (1u << 8)  /**< \brief Uart signal: URXD */
+#define PIO_PA9A_UTXD        (1u << 9)  /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for UOTGHS peripheral ========== */
+#define PIO_PB11A_UOTGID     (1u << 11) /**< \brief Uotghs signal: UOTGID */
+#define PIO_PB10A_UOTGVBOF   (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB26A_CTS0       (1u << 26) /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB25A_RTS0       (1u << 25) /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA10A_RXD0       (1u << 10) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17B_SCK0       (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA11A_TXD0       (1u << 11) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA15A_CTS1       (1u << 15) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA14A_RTS1       (1u << 14) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA12A_RXD1       (1u << 12) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA16A_SCK1       (1u << 16) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA13A_TXD1       (1u << 13) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB23A_CTS2       (1u << 23) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB22A_RTS2       (1u << 22) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PB21A_RXD2       (1u << 21) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PB24A_SCK2       (1u << 24) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PB20A_TXD2       (1u << 20) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX          0
+#define PIO_PA1_IDX          1
+#define PIO_PA2_IDX          2
+#define PIO_PA3_IDX          3
+#define PIO_PA4_IDX          4
+#define PIO_PA5_IDX          5
+#define PIO_PA6_IDX          6
+#define PIO_PA7_IDX          7
+#define PIO_PA8_IDX          8
+#define PIO_PA9_IDX          9
+#define PIO_PA10_IDX         10
+#define PIO_PA11_IDX         11
+#define PIO_PA12_IDX         12
+#define PIO_PA13_IDX         13
+#define PIO_PA14_IDX         14
+#define PIO_PA15_IDX         15
+#define PIO_PA16_IDX         16
+#define PIO_PA17_IDX         17
+#define PIO_PA18_IDX         18
+#define PIO_PA19_IDX         19
+#define PIO_PA20_IDX         20
+#define PIO_PA21_IDX         21
+#define PIO_PA22_IDX         22
+#define PIO_PA23_IDX         23
+#define PIO_PA24_IDX         24
+#define PIO_PA25_IDX         25
+#define PIO_PA26_IDX         26
+#define PIO_PA27_IDX         27
+#define PIO_PA28_IDX         28
+#define PIO_PA29_IDX         29
+#define PIO_PB0_IDX          32
+#define PIO_PB1_IDX          33
+#define PIO_PB2_IDX          34
+#define PIO_PB3_IDX          35
+#define PIO_PB4_IDX          36
+#define PIO_PB5_IDX          37
+#define PIO_PB6_IDX          38
+#define PIO_PB7_IDX          39
+#define PIO_PB8_IDX          40
+#define PIO_PB9_IDX          41
+#define PIO_PB10_IDX         42
+#define PIO_PB11_IDX         43
+#define PIO_PB12_IDX         44
+#define PIO_PB13_IDX         45
+#define PIO_PB14_IDX         46
+#define PIO_PB15_IDX         47
+#define PIO_PB16_IDX         48
+#define PIO_PB17_IDX         49
+#define PIO_PB18_IDX         50
+#define PIO_PB19_IDX         51
+#define PIO_PB20_IDX         52
+#define PIO_PB21_IDX         53
+#define PIO_PB22_IDX         54
+#define PIO_PB23_IDX         55
+#define PIO_PB24_IDX         56
+#define PIO_PB25_IDX         57
+#define PIO_PB26_IDX         58
+#define PIO_PB27_IDX         59
+#define PIO_PB28_IDX         60
+#define PIO_PB29_IDX         61
+#define PIO_PB30_IDX         62
+#define PIO_PB31_IDX         63
+
+#endif /* _SAM3X8C_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x8e.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x8e.h
new file mode 100644
index 000000000..904349e07
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x8e.h
@@ -0,0 +1,552 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3X8E_PIO_
+#define _SAM3X8E_PIO_
+
+#define PIO_PA0              (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1              (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2              (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3              (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4              (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5              (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6              (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7              (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8              (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9              (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10             (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11             (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12             (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13             (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14             (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15             (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16             (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17             (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18             (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19             (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20             (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21             (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22             (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23             (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24             (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25             (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26             (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27             (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28             (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29             (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PB0              (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1              (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2              (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3              (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4              (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5              (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6              (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7              (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8              (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9              (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10             (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11             (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12             (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13             (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14             (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15             (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16             (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17             (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18             (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19             (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20             (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21             (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22             (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23             (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24             (1u << 24) /**< \brief Pin Controlled by PB24 */
+#define PIO_PB25             (1u << 25) /**< \brief Pin Controlled by PB25 */
+#define PIO_PB26             (1u << 26) /**< \brief Pin Controlled by PB26 */
+#define PIO_PB27             (1u << 27) /**< \brief Pin Controlled by PB27 */
+#define PIO_PB28             (1u << 28) /**< \brief Pin Controlled by PB28 */
+#define PIO_PB29             (1u << 29) /**< \brief Pin Controlled by PB29 */
+#define PIO_PB30             (1u << 30) /**< \brief Pin Controlled by PB30 */
+#define PIO_PB31             (1u << 31) /**< \brief Pin Controlled by PB31 */
+#define PIO_PC0              (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1              (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2              (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3              (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4              (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5              (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6              (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7              (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8              (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9              (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10             (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11             (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12             (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13             (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14             (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15             (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16             (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17             (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18             (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19             (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20             (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21             (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22             (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23             (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24             (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25             (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26             (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27             (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28             (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29             (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30             (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PD0              (1u << 0)  /**< \brief Pin Controlled by PD0 */
+#define PIO_PD1              (1u << 1)  /**< \brief Pin Controlled by PD1 */
+#define PIO_PD2              (1u << 2)  /**< \brief Pin Controlled by PD2 */
+#define PIO_PD3              (1u << 3)  /**< \brief Pin Controlled by PD3 */
+#define PIO_PD4              (1u << 4)  /**< \brief Pin Controlled by PD4 */
+#define PIO_PD5              (1u << 5)  /**< \brief Pin Controlled by PD5 */
+#define PIO_PD6              (1u << 6)  /**< \brief Pin Controlled by PD6 */
+#define PIO_PD7              (1u << 7)  /**< \brief Pin Controlled by PD7 */
+#define PIO_PD8              (1u << 8)  /**< \brief Pin Controlled by PD8 */
+#define PIO_PD9              (1u << 9)  /**< \brief Pin Controlled by PD9 */
+#define PIO_PD10             (1u << 10) /**< \brief Pin Controlled by PD10 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA2X1_AD0        (1u << 2)  /**< \brief Adc signal: AD0 */
+#define PIO_PA3X1_AD1        (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PA3X1_WKUP1      (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PB17X1_AD10      (1u << 17) /**< \brief Adc signal: AD10 */
+#define PIO_PB18X1_AD11      (1u << 18) /**< \brief Adc signal: AD11 */
+#define PIO_PB19X1_AD12      (1u << 19) /**< \brief Adc signal: AD12 */
+#define PIO_PB20X1_AD13      (1u << 20) /**< \brief Adc signal: AD13 */
+#define PIO_PB21X1_AD14      (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PB21X1_WKUP13    (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PA4X1_AD2        (1u << 4)  /**< \brief Adc signal: AD2 */
+#define PIO_PA6X1_AD3        (1u << 6)  /**< \brief Adc signal: AD3 */
+#define PIO_PA22X1_AD4       (1u << 22) /**< \brief Adc signal: AD4 */
+#define PIO_PA23X1_AD5       (1u << 23) /**< \brief Adc signal: AD5 */
+#define PIO_PA24X1_AD6       (1u << 24) /**< \brief Adc signal: AD6 */
+#define PIO_PA16X1_AD7       (1u << 16) /**< \brief Adc signal: AD7 */
+#define PIO_PB12X1_AD8       (1u << 12) /**< \brief Adc signal: AD8 */
+#define PIO_PB13X1_AD9       (1u << 13) /**< \brief Adc signal: AD9 */
+#define PIO_PA11B_ADTRG      (1u << 11) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for CAN0 peripheral ========== */
+#define PIO_PA1A_CANRX0      (1u << 1)  /**< \brief Can0 signal: CANRX0 */
+#define PIO_PA0A_CANTX0      (1u << 0)  /**< \brief Can0 signal: CANTX0 */
+/* ========== Pio definition for CAN1 peripheral ========== */
+#define PIO_PB15A_CANRX1     (1u << 15) /**< \brief Can1 signal: CANRX1 */
+#define PIO_PB14A_CANTX1     (1u << 14) /**< \brief Can1 signal: CANTX1 */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB15X1_DAC0      (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB15X1_WKUP12    (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB16X1_DAC1      (1u << 16) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA10B_DATRG      (1u << 10) /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PC21A_A0         (1u << 21) /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PC21A_NBS0       (1u << 21) /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PC22A_A1         (1u << 22) /**< \brief Ebi signal: A1 */
+#define PIO_PD0A_A10         (1u << 0)  /**< \brief Ebi signal: A10 */
+#define PIO_PD22A_A10        (1u << 22) /**< \brief Ebi signal: A10 */
+#define PIO_PD1A_A11         (1u << 1)  /**< \brief Ebi signal: A11 */
+#define PIO_PD23A_A11        (1u << 23) /**< \brief Ebi signal: A11 */
+#define PIO_PD2A_A12         (1u << 2)  /**< \brief Ebi signal: A12 */
+#define PIO_PD24A_A12        (1u << 24) /**< \brief Ebi signal: A12 */
+#define PIO_PD3A_A13         (1u << 3)  /**< \brief Ebi signal: A13 */
+#define PIO_PD25A_A13        (1u << 25) /**< \brief Ebi signal: A13 */
+#define PIO_PD4A_A14         (1u << 4)  /**< \brief Ebi signal: A14 */
+#define PIO_PD26A_A14        (1u << 26) /**< \brief Ebi signal: A14 */
+#define PIO_PD5A_A15         (1u << 5)  /**< \brief Ebi signal: A15 */
+#define PIO_PD27A_A15        (1u << 27) /**< \brief Ebi signal: A15 */
+#define PIO_PD6A_A16         (1u << 6)  /**< \brief Ebi signal: A16/BA0 */
+#define PIO_PD6A_BA0         (1u << 6)  /**< \brief Ebi signal: A16/BA0 */
+#define PIO_PD28A_A16        (1u << 28) /**< \brief Ebi signal: A16/BA0 */
+#define PIO_PD28A_BA0        (1u << 28) /**< \brief Ebi signal: A16/BA0 */
+#define PIO_PD7A_A17         (1u << 7)  /**< \brief Ebi signal: A17/BA1 */
+#define PIO_PD7A_BA1         (1u << 7)  /**< \brief Ebi signal: A17/BA1 */
+#define PIO_PD29A_A17        (1u << 29) /**< \brief Ebi signal: A17/BA1 */
+#define PIO_PD29A_BA1        (1u << 29) /**< \brief Ebi signal: A17/BA1 */
+#define PIO_PA25B_A18        (1u << 25) /**< \brief Ebi signal: A18 */
+#define PIO_PB10B_A18        (1u << 10) /**< \brief Ebi signal: A18 */
+#define PIO_PD30A_A18        (1u << 30) /**< \brief Ebi signal: A18 */
+#define PIO_PA26B_A19        (1u << 26) /**< \brief Ebi signal: A19 */
+#define PIO_PB11B_A19        (1u << 11) /**< \brief Ebi signal: A19 */
+#define PIO_PE0A_A19         (1u << 0)  /**< \brief Ebi signal: A19 */
+#define PIO_PC23A_A2         (1u << 23) /**< \brief Ebi signal: A2 */
+#define PIO_PA18B_A20        (1u << 18) /**< \brief Ebi signal: A20 */
+#define PIO_PA27B_A20        (1u << 27) /**< \brief Ebi signal: A20 */
+#define PIO_PE1A_A20         (1u << 1)  /**< \brief Ebi signal: A20 */
+#define PIO_PD8A_A21         (1u << 8)  /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PD8A_NANDALE     (1u << 8)  /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PE2A_A21         (1u << 2)  /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PE2A_NANDALE     (1u << 2)  /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PD9A_A22         (1u << 9)  /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PD9A_NANDCLE     (1u << 9)  /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PE3A_A22         (1u << 3)  /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PE3A_NANDCLE     (1u << 3)  /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PE4A_A23         (1u << 4)  /**< \brief Ebi signal: A23 */
+#define PIO_PC24A_A3         (1u << 24) /**< \brief Ebi signal: A3 */
+#define PIO_PC25A_A4         (1u << 25) /**< \brief Ebi signal: A4 */
+#define PIO_PC26A_A5         (1u << 26) /**< \brief Ebi signal: A5 */
+#define PIO_PD17A_A5         (1u << 17) /**< \brief Ebi signal: A5 */
+#define PIO_PC27A_A6         (1u << 27) /**< \brief Ebi signal: A6 */
+#define PIO_PD18A_A6         (1u << 18) /**< \brief Ebi signal: A6 */
+#define PIO_PC28A_A7         (1u << 28) /**< \brief Ebi signal: A7 */
+#define PIO_PD19A_A7         (1u << 19) /**< \brief Ebi signal: A7 */
+#define PIO_PC29A_A8         (1u << 29) /**< \brief Ebi signal: A8 */
+#define PIO_PD20A_A8         (1u << 20) /**< \brief Ebi signal: A8 */
+#define PIO_PC30A_A9         (1u << 30) /**< \brief Ebi signal: A9 */
+#define PIO_PD21A_A9         (1u << 21) /**< \brief Ebi signal: A9 */
+#define PIO_PD16A_CAS        (1u << 16) /**< \brief Ebi signal: CAS */
+#define PIO_PC2A_D0          (1u << 2)  /**< \brief Ebi signal: D0 */
+#define PIO_PC3A_D1          (1u << 3)  /**< \brief Ebi signal: D1 */
+#define PIO_PC12A_D10        (1u << 12) /**< \brief Ebi signal: D10 */
+#define PIO_PC13A_D11        (1u << 13) /**< \brief Ebi signal: D11 */
+#define PIO_PC14A_D12        (1u << 14) /**< \brief Ebi signal: D12 */
+#define PIO_PC15A_D13        (1u << 15) /**< \brief Ebi signal: D13 */
+#define PIO_PC16A_D14        (1u << 16) /**< \brief Ebi signal: D14 */
+#define PIO_PC17A_D15        (1u << 17) /**< \brief Ebi signal: D15 */
+#define PIO_PC4A_D2          (1u << 4)  /**< \brief Ebi signal: D2 */
+#define PIO_PC5A_D3          (1u << 5)  /**< \brief Ebi signal: D3 */
+#define PIO_PC6A_D4          (1u << 6)  /**< \brief Ebi signal: D4 */
+#define PIO_PC7A_D5          (1u << 7)  /**< \brief Ebi signal: D5 */
+#define PIO_PC8A_D6          (1u << 8)  /**< \brief Ebi signal: D6 */
+#define PIO_PC9A_D7          (1u << 9)  /**< \brief Ebi signal: D7 */
+#define PIO_PC10A_D8         (1u << 10) /**< \brief Ebi signal: D8 */
+#define PIO_PC11A_D9         (1u << 11) /**< \brief Ebi signal: D9 */
+#define PIO_PC19A_NANDOE     (1u << 19) /**< \brief Ebi signal: NANDOE */
+#define PIO_PA2B_NANDRDY     (1u << 2)  /**< \brief Ebi signal: NANDRDY */
+#define PIO_PC20A_NANDWE     (1u << 20) /**< \brief Ebi signal: NANDWE */
+#define PIO_PA6B_NCS0        (1u << 6)  /**< \brief Ebi signal: NCS0 */
+#define PIO_PA7B_NCS1        (1u << 7)  /**< \brief Ebi signal: NCS1 */
+#define PIO_PB24B_NCS2       (1u << 24) /**< \brief Ebi signal: NCS2 */
+#define PIO_PB27A_NCS3       (1u << 27) /**< \brief Ebi signal: NCS3 */
+#define PIO_PE5A_NCS4        (1u << 5)  /**< \brief Ebi signal: NCS4 */
+#define PIO_PE6A_NCS5        (1u << 6)  /**< \brief Ebi signal: NCS5 */
+#define PIO_PE18B_NCS6       (1u << 18) /**< \brief Ebi signal: NCS6 */
+#define PIO_PE27A_NCS7       (1u << 27) /**< \brief Ebi signal: NCS7 */
+#define PIO_PA29B_NRD        (1u << 29) /**< \brief Ebi signal: NRD */
+#define PIO_PA4B_NWAIT       (1u << 4)  /**< \brief Ebi signal: NWAIT */
+#define PIO_PC18A_NWR0       (1u << 18) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PC18A_NWE        (1u << 18) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PD10A_NWR1       (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */
+#define PIO_PD10A_NBS1       (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */
+#define PIO_PD15A_RAS        (1u << 15) /**< \brief Ebi signal: RAS */
+#define PIO_PD11A_SDA10      (1u << 11) /**< \brief Ebi signal: SDA10 */
+#define PIO_PD13A_SDCKE      (1u << 13) /**< \brief Ebi signal: SDCKE */
+#define PIO_PD12A_SDCS       (1u << 12) /**< \brief Ebi signal: SDCS */
+#define PIO_PD14A_SDWE       (1u << 14) /**< \brief Ebi signal: SDWE */
+/* ========== Pio definition for EMAC peripheral ========== */
+#define PIO_PC13B_ECOL       (1u << 13) /**< \brief Emac signal: ECOL */
+#define PIO_PC10B_ECRS       (1u << 10) /**< \brief Emac signal: ECRS */
+#define PIO_PB4A_ECRSDV      (1u << 4)  /**< \brief Emac signal: ECRSDV/ERXDV */
+#define PIO_PB4A_ERXDV       (1u << 4)  /**< \brief Emac signal: ECRSDV/ERXDV */
+#define PIO_PB8A_EMDC        (1u << 8)  /**< \brief Emac signal: EMDC */
+#define PIO_PB9A_EMDIO       (1u << 9)  /**< \brief Emac signal: EMDIO */
+#define PIO_PB5A_ERX0        (1u << 5)  /**< \brief Emac signal: ERX0 */
+#define PIO_PB6A_ERX1        (1u << 6)  /**< \brief Emac signal: ERX1 */
+#define PIO_PC11B_ERX2       (1u << 11) /**< \brief Emac signal: ERX2 */
+#define PIO_PC12B_ERX3       (1u << 12) /**< \brief Emac signal: ERX3 */
+#define PIO_PC14B_ERXCK      (1u << 14) /**< \brief Emac signal: ERXCK */
+#define PIO_PB7A_ERXER       (1u << 7)  /**< \brief Emac signal: ERXER */
+#define PIO_PB2A_ETX0        (1u << 2)  /**< \brief Emac signal: ETX0 */
+#define PIO_PB3A_ETX1        (1u << 3)  /**< \brief Emac signal: ETX1 */
+#define PIO_PC15B_ETX2       (1u << 15) /**< \brief Emac signal: ETX2 */
+#define PIO_PC16B_ETX3       (1u << 16) /**< \brief Emac signal: ETX3 */
+#define PIO_PB0A_ETXCK       (1u << 0)  /**< \brief Emac signal: ETXCK */
+#define PIO_PB1A_ETXEN       (1u << 1)  /**< \brief Emac signal: ETXEN */
+#define PIO_PC17B_ETXER      (1u << 17) /**< \brief Emac signal: ETXER */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA20A_MCCDA      (1u << 20) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PE20B_MCCDB      (1u << 20) /**< \brief Hsmci signal: MCCDB */
+#define PIO_PA19A_MCCK       (1u << 19) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA21A_MCDA0      (1u << 21) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA22A_MCDA1      (1u << 22) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA23A_MCDA2      (1u << 23) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA24A_MCDA3      (1u << 24) /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PD0B_MCDA4       (1u << 0)  /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PD1B_MCDA5       (1u << 1)  /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PD2B_MCDA6       (1u << 2)  /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PD3B_MCDA7       (1u << 3)  /**< \brief Hsmci signal: MCDA7 */
+#define PIO_PE22B_MCDB0      (1u << 22) /**< \brief Hsmci signal: MCDB0 */
+#define PIO_PE24B_MCDB1      (1u << 24) /**< \brief Hsmci signal: MCDB1 */
+#define PIO_PE26B_MCDB2      (1u << 26) /**< \brief Hsmci signal: MCDB2 */
+#define PIO_PE27B_MCDB3      (1u << 27) /**< \brief Hsmci signal: MCDB3 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA1B_PCK0        (1u << 1)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB22B_PCK0       (1u << 22) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA24B_PCK1       (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA30B_PCK1       (1u << 30) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA28B_PCK2       (1u << 28) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2       (1u << 31) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA5B_PWMFI0      (1u << 5)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA3B_PWMFI1      (1u << 3)  /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PD6B_PWMFI2      (1u << 6)  /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA8B_PWMH0       (1u << 8)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB12B_PWMH0      (1u << 12) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC3B_PWMH0       (1u << 3)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PE15A_PWMH0      (1u << 15) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA19B_PWMH1      (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB13B_PWMH1      (1u << 13) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC5B_PWMH1       (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PE16A_PWMH1      (1u << 16) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA13B_PWMH2      (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB14B_PWMH2      (1u << 14) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC7B_PWMH2       (1u << 7)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB15B_PWMH3      (1u << 15) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PF3A_PWMH3       (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC20B_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PE20A_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PC19B_PWMH5      (1u << 19) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PE22A_PWMH5      (1u << 22) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PC18B_PWMH6      (1u << 18) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE24A_PWMH6      (1u << 24) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE26A_PWMH7      (1u << 26) /**< \brief Pwm signal: PWMH7 */
+#define PIO_PA21B_PWML0      (1u << 21) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB16B_PWML0      (1u << 16) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC2B_PWML0       (1u << 2)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PE18A_PWML0      (1u << 18) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA12B_PWML1      (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB17B_PWML1      (1u << 17) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC4B_PWML1       (1u << 4)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PA20B_PWML2      (1u << 20) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB18B_PWML2      (1u << 18) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC6B_PWML2       (1u << 6)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PE17A_PWML2      (1u << 17) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA0B_PWML3       (1u << 0)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB19B_PWML3      (1u << 19) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC8B_PWML3       (1u << 8)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB6B_PWML4       (1u << 6)  /**< \brief Pwm signal: PWML4 */
+#define PIO_PC21B_PWML4      (1u << 21) /**< \brief Pwm signal: PWML4 */
+#define PIO_PE19A_PWML4      (1u << 19) /**< \brief Pwm signal: PWML4 */
+#define PIO_PB7B_PWML5       (1u << 7)  /**< \brief Pwm signal: PWML5 */
+#define PIO_PC22B_PWML5      (1u << 22) /**< \brief Pwm signal: PWML5 */
+#define PIO_PE21A_PWML5      (1u << 21) /**< \brief Pwm signal: PWML5 */
+#define PIO_PB8B_PWML6       (1u << 8)  /**< \brief Pwm signal: PWML6 */
+#define PIO_PC23B_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PE23A_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PB9B_PWML7       (1u << 9)  /**< \brief Pwm signal: PWML7 */
+#define PIO_PC24B_PWML7      (1u << 24) /**< \brief Pwm signal: PWML7 */
+#define PIO_PE25A_PWML7      (1u << 25) /**< \brief Pwm signal: PWML7 */
+/* ========== Pio definition for SPI0 peripheral ========== */
+#define PIO_PA25A_SPI0_MISO  (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */
+#define PIO_PA26A_SPI0_MOSI  (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */
+#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */
+#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PA27A_SPI0_SPCK  (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PB18A_RD         (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PB17A_RF         (1u << 17) /**< \brief Ssc signal: RF */
+#define PIO_PB19A_RK         (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA16B_TD         (1u << 16) /**< \brief Ssc signal: TD */
+#define PIO_PA15B_TF         (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA14B_TK         (1u << 14) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PB26B_TCLK0      (1u << 26) /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA4A_TCLK1       (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA7A_TCLK2       (1u << 7)  /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PB25B_TIOA0      (1u << 25) /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA2A_TIOA1       (1u << 2)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA5A_TIOA2       (1u << 5)  /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PB27B_TIOB0      (1u << 27) /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA3A_TIOB1       (1u << 3)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA6A_TIOB2       (1u << 6)  /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PA22B_TCLK3      (1u << 22) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PA23B_TCLK4      (1u << 23) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PB16A_TCLK5      (1u << 16) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PB0B_TIOA3       (1u << 0)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PE9A_TIOA3       (1u << 9)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PB2B_TIOA4       (1u << 2)  /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PE11A_TIOA4      (1u << 11) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PB4B_TIOA5       (1u << 4)  /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PE13A_TIOA5      (1u << 13) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PB1B_TIOB3       (1u << 1)  /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PE10A_TIOB3      (1u << 10) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PB3B_TIOB4       (1u << 3)  /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PE12A_TIOB4      (1u << 12) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PB5B_TIOB5       (1u << 5)  /**< \brief Tc1 signal: TIOB5 */
+#define PIO_PE14A_TIOB5      (1u << 14) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TC2 peripheral ========== */
+#define PIO_PC27B_TCLK6      (1u << 27) /**< \brief Tc2 signal: TCLK6 */
+#define PIO_PC30B_TCLK7      (1u << 30) /**< \brief Tc2 signal: TCLK7 */
+#define PIO_PD9B_TCLK8       (1u << 9)  /**< \brief Tc2 signal: TCLK8 */
+#define PIO_PC25B_TIOA6      (1u << 25) /**< \brief Tc2 signal: TIOA6 */
+#define PIO_PC28B_TIOA7      (1u << 28) /**< \brief Tc2 signal: TIOA7 */
+#define PIO_PD7B_TIOA8       (1u << 7)  /**< \brief Tc2 signal: TIOA8 */
+#define PIO_PC26B_TIOB6      (1u << 26) /**< \brief Tc2 signal: TIOB6 */
+#define PIO_PC29B_TIOB7      (1u << 29) /**< \brief Tc2 signal: TIOB7 */
+#define PIO_PD8B_TIOB8       (1u << 8)  /**< \brief Tc2 signal: TIOB8 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA18A_TWCK0      (1u << 18) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA17A_TWD0       (1u << 17) /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB13A_TWCK1      (1u << 13) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB12A_TWD1       (1u << 12) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA8A_URXD        (1u << 8)  /**< \brief Uart signal: URXD */
+#define PIO_PA9A_UTXD        (1u << 9)  /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for UOTGHS peripheral ========== */
+#define PIO_PB11A_UOTGID     (1u << 11) /**< \brief Uotghs signal: UOTGID */
+#define PIO_PB10A_UOTGVBOF   (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB26A_CTS0       (1u << 26) /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB25A_RTS0       (1u << 25) /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA10A_RXD0       (1u << 10) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17B_SCK0       (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA11A_TXD0       (1u << 11) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA15A_CTS1       (1u << 15) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA14A_RTS1       (1u << 14) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA12A_RXD1       (1u << 12) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA16A_SCK1       (1u << 16) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA13A_TXD1       (1u << 13) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB23A_CTS2       (1u << 23) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB22A_RTS2       (1u << 22) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PB21A_RXD2       (1u << 21) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PB24A_SCK2       (1u << 24) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PB20A_TXD2       (1u << 20) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio definition for USART3 peripheral ========== */
+#define PIO_PF4A_CTS3        (1u << 4)  /**< \brief Usart3 signal: CTS3 */
+#define PIO_PF5A_RTS3        (1u << 5)  /**< \brief Usart3 signal: RTS3 */
+#define PIO_PD5B_RXD3        (1u << 5)  /**< \brief Usart3 signal: RXD3 */
+#define PIO_PE16B_SCK3       (1u << 16) /**< \brief Usart3 signal: SCK3 */
+#define PIO_PD4B_TXD3        (1u << 4)  /**< \brief Usart3 signal: TXD3 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX          0
+#define PIO_PA1_IDX          1
+#define PIO_PA2_IDX          2
+#define PIO_PA3_IDX          3
+#define PIO_PA4_IDX          4
+#define PIO_PA5_IDX          5
+#define PIO_PA6_IDX          6
+#define PIO_PA7_IDX          7
+#define PIO_PA8_IDX          8
+#define PIO_PA9_IDX          9
+#define PIO_PA10_IDX         10
+#define PIO_PA11_IDX         11
+#define PIO_PA12_IDX         12
+#define PIO_PA13_IDX         13
+#define PIO_PA14_IDX         14
+#define PIO_PA15_IDX         15
+#define PIO_PA16_IDX         16
+#define PIO_PA17_IDX         17
+#define PIO_PA18_IDX         18
+#define PIO_PA19_IDX         19
+#define PIO_PA20_IDX         20
+#define PIO_PA21_IDX         21
+#define PIO_PA22_IDX         22
+#define PIO_PA23_IDX         23
+#define PIO_PA24_IDX         24
+#define PIO_PA25_IDX         25
+#define PIO_PA26_IDX         26
+#define PIO_PA27_IDX         27
+#define PIO_PA28_IDX         28
+#define PIO_PA29_IDX         29
+#define PIO_PB0_IDX          32
+#define PIO_PB1_IDX          33
+#define PIO_PB2_IDX          34
+#define PIO_PB3_IDX          35
+#define PIO_PB4_IDX          36
+#define PIO_PB5_IDX          37
+#define PIO_PB6_IDX          38
+#define PIO_PB7_IDX          39
+#define PIO_PB8_IDX          40
+#define PIO_PB9_IDX          41
+#define PIO_PB10_IDX         42
+#define PIO_PB11_IDX         43
+#define PIO_PB12_IDX         44
+#define PIO_PB13_IDX         45
+#define PIO_PB14_IDX         46
+#define PIO_PB15_IDX         47
+#define PIO_PB16_IDX         48
+#define PIO_PB17_IDX         49
+#define PIO_PB18_IDX         50
+#define PIO_PB19_IDX         51
+#define PIO_PB20_IDX         52
+#define PIO_PB21_IDX         53
+#define PIO_PB22_IDX         54
+#define PIO_PB23_IDX         55
+#define PIO_PB24_IDX         56
+#define PIO_PB25_IDX         57
+#define PIO_PB26_IDX         58
+#define PIO_PB27_IDX         59
+#define PIO_PB28_IDX         60
+#define PIO_PB29_IDX         61
+#define PIO_PB30_IDX         62
+#define PIO_PB31_IDX         63
+#define PIO_PC0_IDX          64
+#define PIO_PC1_IDX          65
+#define PIO_PC2_IDX          66
+#define PIO_PC3_IDX          67
+#define PIO_PC4_IDX          68
+#define PIO_PC5_IDX          69
+#define PIO_PC6_IDX          70
+#define PIO_PC7_IDX          71
+#define PIO_PC8_IDX          72
+#define PIO_PC9_IDX          73
+#define PIO_PC10_IDX         74
+#define PIO_PC11_IDX         75
+#define PIO_PC12_IDX         76
+#define PIO_PC13_IDX         77
+#define PIO_PC14_IDX         78
+#define PIO_PC15_IDX         79
+#define PIO_PC16_IDX         80
+#define PIO_PC17_IDX         81
+#define PIO_PC18_IDX         82
+#define PIO_PC19_IDX         83
+#define PIO_PC20_IDX         84
+#define PIO_PC21_IDX         85
+#define PIO_PC22_IDX         86
+#define PIO_PC23_IDX         87
+#define PIO_PC24_IDX         88
+#define PIO_PC25_IDX         89
+#define PIO_PC26_IDX         90
+#define PIO_PC27_IDX         91
+#define PIO_PC28_IDX         92
+#define PIO_PC29_IDX         93
+#define PIO_PC30_IDX         94
+#define PIO_PD0_IDX          96
+#define PIO_PD1_IDX          97
+#define PIO_PD2_IDX          98
+#define PIO_PD3_IDX          99
+#define PIO_PD4_IDX          100
+#define PIO_PD5_IDX          101
+#define PIO_PD6_IDX          102
+#define PIO_PD7_IDX          103
+#define PIO_PD8_IDX          104
+#define PIO_PD9_IDX          105
+#define PIO_PD10_IDX         106
+
+#endif /* _SAM3X8E_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x8h.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x8h.h
new file mode 100644
index 000000000..f438e52c4
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/pio/pio_sam3x8h.h
@@ -0,0 +1,680 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3X8H_PIO_
+#define _SAM3X8H_PIO_
+
+#define PIO_PA0              (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1              (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2              (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3              (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4              (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5              (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6              (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7              (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8              (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9              (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10             (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11             (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12             (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13             (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14             (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15             (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16             (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17             (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18             (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19             (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20             (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21             (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22             (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23             (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24             (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25             (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26             (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27             (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28             (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29             (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30             (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31             (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0              (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1              (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2              (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3              (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4              (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5              (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6              (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7              (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8              (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9              (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10             (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11             (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12             (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13             (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14             (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15             (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16             (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17             (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18             (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19             (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20             (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21             (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22             (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23             (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24             (1u << 24) /**< \brief Pin Controlled by PB24 */
+#define PIO_PB25             (1u << 25) /**< \brief Pin Controlled by PB25 */
+#define PIO_PB26             (1u << 26) /**< \brief Pin Controlled by PB26 */
+#define PIO_PB27             (1u << 27) /**< \brief Pin Controlled by PB27 */
+#define PIO_PB28             (1u << 28) /**< \brief Pin Controlled by PB28 */
+#define PIO_PB29             (1u << 29) /**< \brief Pin Controlled by PB29 */
+#define PIO_PB30             (1u << 30) /**< \brief Pin Controlled by PB30 */
+#define PIO_PB31             (1u << 31) /**< \brief Pin Controlled by PB31 */
+#define PIO_PC0              (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1              (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2              (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3              (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4              (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5              (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6              (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7              (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8              (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9              (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10             (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11             (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12             (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13             (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14             (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15             (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16             (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17             (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18             (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19             (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20             (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21             (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22             (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23             (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24             (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25             (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26             (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27             (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28             (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29             (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30             (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PD0              (1u << 0)  /**< \brief Pin Controlled by PD0 */
+#define PIO_PD1              (1u << 1)  /**< \brief Pin Controlled by PD1 */
+#define PIO_PD2              (1u << 2)  /**< \brief Pin Controlled by PD2 */
+#define PIO_PD3              (1u << 3)  /**< \brief Pin Controlled by PD3 */
+#define PIO_PD4              (1u << 4)  /**< \brief Pin Controlled by PD4 */
+#define PIO_PD5              (1u << 5)  /**< \brief Pin Controlled by PD5 */
+#define PIO_PD6              (1u << 6)  /**< \brief Pin Controlled by PD6 */
+#define PIO_PD7              (1u << 7)  /**< \brief Pin Controlled by PD7 */
+#define PIO_PD8              (1u << 8)  /**< \brief Pin Controlled by PD8 */
+#define PIO_PD9              (1u << 9)  /**< \brief Pin Controlled by PD9 */
+#define PIO_PD10             (1u << 10) /**< \brief Pin Controlled by PD10 */
+#define PIO_PD11             (1u << 11) /**< \brief Pin Controlled by PD11 */
+#define PIO_PD12             (1u << 12) /**< \brief Pin Controlled by PD12 */
+#define PIO_PD13             (1u << 13) /**< \brief Pin Controlled by PD13 */
+#define PIO_PD14             (1u << 14) /**< \brief Pin Controlled by PD14 */
+#define PIO_PD15             (1u << 15) /**< \brief Pin Controlled by PD15 */
+#define PIO_PD16             (1u << 16) /**< \brief Pin Controlled by PD16 */
+#define PIO_PD17             (1u << 17) /**< \brief Pin Controlled by PD17 */
+#define PIO_PD18             (1u << 18) /**< \brief Pin Controlled by PD18 */
+#define PIO_PD19             (1u << 19) /**< \brief Pin Controlled by PD19 */
+#define PIO_PD20             (1u << 20) /**< \brief Pin Controlled by PD20 */
+#define PIO_PD21             (1u << 21) /**< \brief Pin Controlled by PD21 */
+#define PIO_PD22             (1u << 22) /**< \brief Pin Controlled by PD22 */
+#define PIO_PD23             (1u << 23) /**< \brief Pin Controlled by PD23 */
+#define PIO_PD24             (1u << 24) /**< \brief Pin Controlled by PD24 */
+#define PIO_PD25             (1u << 25) /**< \brief Pin Controlled by PD25 */
+#define PIO_PD26             (1u << 26) /**< \brief Pin Controlled by PD26 */
+#define PIO_PD27             (1u << 27) /**< \brief Pin Controlled by PD27 */
+#define PIO_PD28             (1u << 28) /**< \brief Pin Controlled by PD28 */
+#define PIO_PD29             (1u << 29) /**< \brief Pin Controlled by PD29 */
+#define PIO_PD30             (1u << 30) /**< \brief Pin Controlled by PD30 */
+#define PIO_PE0              (1u << 0)  /**< \brief Pin Controlled by PE0 */
+#define PIO_PE1              (1u << 1)  /**< \brief Pin Controlled by PE1 */
+#define PIO_PE2              (1u << 2)  /**< \brief Pin Controlled by PE2 */
+#define PIO_PE3              (1u << 3)  /**< \brief Pin Controlled by PE3 */
+#define PIO_PE4              (1u << 4)  /**< \brief Pin Controlled by PE4 */
+#define PIO_PE5              (1u << 5)  /**< \brief Pin Controlled by PE5 */
+#define PIO_PE6              (1u << 6)  /**< \brief Pin Controlled by PE6 */
+#define PIO_PE7              (1u << 7)  /**< \brief Pin Controlled by PE7 */
+#define PIO_PE8              (1u << 8)  /**< \brief Pin Controlled by PE8 */
+#define PIO_PE9              (1u << 9)  /**< \brief Pin Controlled by PE9 */
+#define PIO_PE10             (1u << 10) /**< \brief Pin Controlled by PE10 */
+#define PIO_PE11             (1u << 11) /**< \brief Pin Controlled by PE11 */
+#define PIO_PE12             (1u << 12) /**< \brief Pin Controlled by PE12 */
+#define PIO_PE13             (1u << 13) /**< \brief Pin Controlled by PE13 */
+#define PIO_PE14             (1u << 14) /**< \brief Pin Controlled by PE14 */
+#define PIO_PE15             (1u << 15) /**< \brief Pin Controlled by PE15 */
+#define PIO_PE16             (1u << 16) /**< \brief Pin Controlled by PE16 */
+#define PIO_PE17             (1u << 17) /**< \brief Pin Controlled by PE17 */
+#define PIO_PE18             (1u << 18) /**< \brief Pin Controlled by PE18 */
+#define PIO_PE19             (1u << 19) /**< \brief Pin Controlled by PE19 */
+#define PIO_PE20             (1u << 20) /**< \brief Pin Controlled by PE20 */
+#define PIO_PE21             (1u << 21) /**< \brief Pin Controlled by PE21 */
+#define PIO_PE22             (1u << 22) /**< \brief Pin Controlled by PE22 */
+#define PIO_PE23             (1u << 23) /**< \brief Pin Controlled by PE23 */
+#define PIO_PE24             (1u << 24) /**< \brief Pin Controlled by PE24 */
+#define PIO_PE25             (1u << 25) /**< \brief Pin Controlled by PE25 */
+#define PIO_PE26             (1u << 26) /**< \brief Pin Controlled by PE26 */
+#define PIO_PE27             (1u << 27) /**< \brief Pin Controlled by PE27 */
+#define PIO_PE28             (1u << 28) /**< \brief Pin Controlled by PE28 */
+#define PIO_PE29             (1u << 29) /**< \brief Pin Controlled by PE29 */
+#define PIO_PE30             (1u << 30) /**< \brief Pin Controlled by PE30 */
+#define PIO_PE31             (1u << 31) /**< \brief Pin Controlled by PE31 */
+#define PIO_PF0              (1u << 0)  /**< \brief Pin Controlled by PF0 */
+#define PIO_PF1              (1u << 1)  /**< \brief Pin Controlled by PF1 */
+#define PIO_PF2              (1u << 2)  /**< \brief Pin Controlled by PF2 */
+#define PIO_PF3              (1u << 3)  /**< \brief Pin Controlled by PF3 */
+#define PIO_PF4              (1u << 4)  /**< \brief Pin Controlled by PF4 */
+#define PIO_PF5              (1u << 5)  /**< \brief Pin Controlled by PF5 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA2X1_AD0        (1u << 2)  /**< \brief Adc signal: AD0 */
+#define PIO_PA3X1_AD1        (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PA3X1_WKUP1      (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PB17X1_AD10      (1u << 17) /**< \brief Adc signal: AD10 */
+#define PIO_PB18X1_AD11      (1u << 18) /**< \brief Adc signal: AD11 */
+#define PIO_PB19X1_AD12      (1u << 19) /**< \brief Adc signal: AD12 */
+#define PIO_PB20X1_AD13      (1u << 20) /**< \brief Adc signal: AD13 */
+#define PIO_PB21X1_AD14      (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PB21X1_WKUP13    (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PA4X1_AD2        (1u << 4)  /**< \brief Adc signal: AD2 */
+#define PIO_PA6X1_AD3        (1u << 6)  /**< \brief Adc signal: AD3 */
+#define PIO_PA22X1_AD4       (1u << 22) /**< \brief Adc signal: AD4 */
+#define PIO_PA23X1_AD5       (1u << 23) /**< \brief Adc signal: AD5 */
+#define PIO_PA24X1_AD6       (1u << 24) /**< \brief Adc signal: AD6 */
+#define PIO_PA16X1_AD7       (1u << 16) /**< \brief Adc signal: AD7 */
+#define PIO_PB12X1_AD8       (1u << 12) /**< \brief Adc signal: AD8 */
+#define PIO_PB13X1_AD9       (1u << 13) /**< \brief Adc signal: AD9 */
+#define PIO_PA11B_ADTRG      (1u << 11) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for CAN0 peripheral ========== */
+#define PIO_PA1A_CANRX0      (1u << 1)  /**< \brief Can0 signal: CANRX0 */
+#define PIO_PA0A_CANTX0      (1u << 0)  /**< \brief Can0 signal: CANTX0 */
+/* ========== Pio definition for CAN1 peripheral ========== */
+#define PIO_PB15A_CANRX1     (1u << 15) /**< \brief Can1 signal: CANRX1 */
+#define PIO_PB14A_CANTX1     (1u << 14) /**< \brief Can1 signal: CANTX1 */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB15X1_DAC0      (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB15X1_WKUP12    (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB16X1_DAC1      (1u << 16) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA10B_DATRG      (1u << 10) /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PC21A_A0         (1u << 21) /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PC21A_NBS0       (1u << 21) /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PC22A_A1         (1u << 22) /**< \brief Ebi signal: A1 */
+#define PIO_PD0A_A10         (1u << 0)  /**< \brief Ebi signal: A10 */
+#define PIO_PD22A_A10        (1u << 22) /**< \brief Ebi signal: A10 */
+#define PIO_PD1A_A11         (1u << 1)  /**< \brief Ebi signal: A11 */
+#define PIO_PD23A_A11        (1u << 23) /**< \brief Ebi signal: A11 */
+#define PIO_PD2A_A12         (1u << 2)  /**< \brief Ebi signal: A12 */
+#define PIO_PD24A_A12        (1u << 24) /**< \brief Ebi signal: A12 */
+#define PIO_PD3A_A13         (1u << 3)  /**< \brief Ebi signal: A13 */
+#define PIO_PD25A_A13        (1u << 25) /**< \brief Ebi signal: A13 */
+#define PIO_PD4A_A14         (1u << 4)  /**< \brief Ebi signal: A14 */
+#define PIO_PD26A_A14        (1u << 26) /**< \brief Ebi signal: A14 */
+#define PIO_PD5A_A15         (1u << 5)  /**< \brief Ebi signal: A15 */
+#define PIO_PD27A_A15        (1u << 27) /**< \brief Ebi signal: A15 */
+#define PIO_PD6A_A16         (1u << 6)  /**< \brief Ebi signal: A16/BA0 */
+#define PIO_PD6A_BA0         (1u << 6)  /**< \brief Ebi signal: A16/BA0 */
+#define PIO_PD28A_A16        (1u << 28) /**< \brief Ebi signal: A16/BA0 */
+#define PIO_PD28A_BA0        (1u << 28) /**< \brief Ebi signal: A16/BA0 */
+#define PIO_PD7A_A17         (1u << 7)  /**< \brief Ebi signal: A17/BA1 */
+#define PIO_PD7A_BA1         (1u << 7)  /**< \brief Ebi signal: A17/BA1 */
+#define PIO_PD29A_A17        (1u << 29) /**< \brief Ebi signal: A17/BA1 */
+#define PIO_PD29A_BA1        (1u << 29) /**< \brief Ebi signal: A17/BA1 */
+#define PIO_PA25B_A18        (1u << 25) /**< \brief Ebi signal: A18 */
+#define PIO_PB10B_A18        (1u << 10) /**< \brief Ebi signal: A18 */
+#define PIO_PD30A_A18        (1u << 30) /**< \brief Ebi signal: A18 */
+#define PIO_PA26B_A19        (1u << 26) /**< \brief Ebi signal: A19 */
+#define PIO_PB11B_A19        (1u << 11) /**< \brief Ebi signal: A19 */
+#define PIO_PE0A_A19         (1u << 0)  /**< \brief Ebi signal: A19 */
+#define PIO_PC23A_A2         (1u << 23) /**< \brief Ebi signal: A2 */
+#define PIO_PA18B_A20        (1u << 18) /**< \brief Ebi signal: A20 */
+#define PIO_PA27B_A20        (1u << 27) /**< \brief Ebi signal: A20 */
+#define PIO_PE1A_A20         (1u << 1)  /**< \brief Ebi signal: A20 */
+#define PIO_PD8A_A21         (1u << 8)  /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PD8A_NANDALE     (1u << 8)  /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PE2A_A21         (1u << 2)  /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PE2A_NANDALE     (1u << 2)  /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PD9A_A22         (1u << 9)  /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PD9A_NANDCLE     (1u << 9)  /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PE3A_A22         (1u << 3)  /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PE3A_NANDCLE     (1u << 3)  /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PE4A_A23         (1u << 4)  /**< \brief Ebi signal: A23 */
+#define PIO_PC24A_A3         (1u << 24) /**< \brief Ebi signal: A3 */
+#define PIO_PC25A_A4         (1u << 25) /**< \brief Ebi signal: A4 */
+#define PIO_PC26A_A5         (1u << 26) /**< \brief Ebi signal: A5 */
+#define PIO_PD17A_A5         (1u << 17) /**< \brief Ebi signal: A5 */
+#define PIO_PC27A_A6         (1u << 27) /**< \brief Ebi signal: A6 */
+#define PIO_PD18A_A6         (1u << 18) /**< \brief Ebi signal: A6 */
+#define PIO_PC28A_A7         (1u << 28) /**< \brief Ebi signal: A7 */
+#define PIO_PD19A_A7         (1u << 19) /**< \brief Ebi signal: A7 */
+#define PIO_PC29A_A8         (1u << 29) /**< \brief Ebi signal: A8 */
+#define PIO_PD20A_A8         (1u << 20) /**< \brief Ebi signal: A8 */
+#define PIO_PC30A_A9         (1u << 30) /**< \brief Ebi signal: A9 */
+#define PIO_PD21A_A9         (1u << 21) /**< \brief Ebi signal: A9 */
+#define PIO_PD16A_CAS        (1u << 16) /**< \brief Ebi signal: CAS */
+#define PIO_PC2A_D0          (1u << 2)  /**< \brief Ebi signal: D0 */
+#define PIO_PC3A_D1          (1u << 3)  /**< \brief Ebi signal: D1 */
+#define PIO_PC12A_D10        (1u << 12) /**< \brief Ebi signal: D10 */
+#define PIO_PC13A_D11        (1u << 13) /**< \brief Ebi signal: D11 */
+#define PIO_PC14A_D12        (1u << 14) /**< \brief Ebi signal: D12 */
+#define PIO_PC15A_D13        (1u << 15) /**< \brief Ebi signal: D13 */
+#define PIO_PC16A_D14        (1u << 16) /**< \brief Ebi signal: D14 */
+#define PIO_PC17A_D15        (1u << 17) /**< \brief Ebi signal: D15 */
+#define PIO_PC4A_D2          (1u << 4)  /**< \brief Ebi signal: D2 */
+#define PIO_PC5A_D3          (1u << 5)  /**< \brief Ebi signal: D3 */
+#define PIO_PC6A_D4          (1u << 6)  /**< \brief Ebi signal: D4 */
+#define PIO_PC7A_D5          (1u << 7)  /**< \brief Ebi signal: D5 */
+#define PIO_PC8A_D6          (1u << 8)  /**< \brief Ebi signal: D6 */
+#define PIO_PC9A_D7          (1u << 9)  /**< \brief Ebi signal: D7 */
+#define PIO_PC10A_D8         (1u << 10) /**< \brief Ebi signal: D8 */
+#define PIO_PC11A_D9         (1u << 11) /**< \brief Ebi signal: D9 */
+#define PIO_PC19A_NANDOE     (1u << 19) /**< \brief Ebi signal: NANDOE */
+#define PIO_PA2B_NANDRDY     (1u << 2)  /**< \brief Ebi signal: NANDRDY */
+#define PIO_PC20A_NANDWE     (1u << 20) /**< \brief Ebi signal: NANDWE */
+#define PIO_PA6B_NCS0        (1u << 6)  /**< \brief Ebi signal: NCS0 */
+#define PIO_PA7B_NCS1        (1u << 7)  /**< \brief Ebi signal: NCS1 */
+#define PIO_PB24B_NCS2       (1u << 24) /**< \brief Ebi signal: NCS2 */
+#define PIO_PB27A_NCS3       (1u << 27) /**< \brief Ebi signal: NCS3 */
+#define PIO_PE5A_NCS4        (1u << 5)  /**< \brief Ebi signal: NCS4 */
+#define PIO_PE6A_NCS5        (1u << 6)  /**< \brief Ebi signal: NCS5 */
+#define PIO_PE18B_NCS6       (1u << 18) /**< \brief Ebi signal: NCS6 */
+#define PIO_PE27A_NCS7       (1u << 27) /**< \brief Ebi signal: NCS7 */
+#define PIO_PA29B_NRD        (1u << 29) /**< \brief Ebi signal: NRD */
+#define PIO_PA4B_NWAIT       (1u << 4)  /**< \brief Ebi signal: NWAIT */
+#define PIO_PC18A_NWR0       (1u << 18) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PC18A_NWE        (1u << 18) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PD10A_NWR1       (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */
+#define PIO_PD10A_NBS1       (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */
+#define PIO_PD15A_RAS        (1u << 15) /**< \brief Ebi signal: RAS */
+#define PIO_PD11A_SDA10      (1u << 11) /**< \brief Ebi signal: SDA10 */
+#define PIO_PD13A_SDCKE      (1u << 13) /**< \brief Ebi signal: SDCKE */
+#define PIO_PD12A_SDCS       (1u << 12) /**< \brief Ebi signal: SDCS */
+#define PIO_PD14A_SDWE       (1u << 14) /**< \brief Ebi signal: SDWE */
+/* ========== Pio definition for EMAC peripheral ========== */
+#define PIO_PC13B_ECOL       (1u << 13) /**< \brief Emac signal: ECOL */
+#define PIO_PC10B_ECRS       (1u << 10) /**< \brief Emac signal: ECRS */
+#define PIO_PB4A_ECRSDV      (1u << 4)  /**< \brief Emac signal: ECRSDV/ERXDV */
+#define PIO_PB4A_ERXDV       (1u << 4)  /**< \brief Emac signal: ECRSDV/ERXDV */
+#define PIO_PB8A_EMDC        (1u << 8)  /**< \brief Emac signal: EMDC */
+#define PIO_PB9A_EMDIO       (1u << 9)  /**< \brief Emac signal: EMDIO */
+#define PIO_PB5A_ERX0        (1u << 5)  /**< \brief Emac signal: ERX0 */
+#define PIO_PB6A_ERX1        (1u << 6)  /**< \brief Emac signal: ERX1 */
+#define PIO_PC11B_ERX2       (1u << 11) /**< \brief Emac signal: ERX2 */
+#define PIO_PC12B_ERX3       (1u << 12) /**< \brief Emac signal: ERX3 */
+#define PIO_PC14B_ERXCK      (1u << 14) /**< \brief Emac signal: ERXCK */
+#define PIO_PB7A_ERXER       (1u << 7)  /**< \brief Emac signal: ERXER */
+#define PIO_PB2A_ETX0        (1u << 2)  /**< \brief Emac signal: ETX0 */
+#define PIO_PB3A_ETX1        (1u << 3)  /**< \brief Emac signal: ETX1 */
+#define PIO_PC15B_ETX2       (1u << 15) /**< \brief Emac signal: ETX2 */
+#define PIO_PC16B_ETX3       (1u << 16) /**< \brief Emac signal: ETX3 */
+#define PIO_PB0A_ETXCK       (1u << 0)  /**< \brief Emac signal: ETXCK */
+#define PIO_PB1A_ETXEN       (1u << 1)  /**< \brief Emac signal: ETXEN */
+#define PIO_PC17B_ETXER      (1u << 17) /**< \brief Emac signal: ETXER */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA20A_MCCDA      (1u << 20) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PE20B_MCCDB      (1u << 20) /**< \brief Hsmci signal: MCCDB */
+#define PIO_PA19A_MCCK       (1u << 19) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA21A_MCDA0      (1u << 21) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA22A_MCDA1      (1u << 22) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA23A_MCDA2      (1u << 23) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA24A_MCDA3      (1u << 24) /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PD0B_MCDA4       (1u << 0)  /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PD1B_MCDA5       (1u << 1)  /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PD2B_MCDA6       (1u << 2)  /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PD3B_MCDA7       (1u << 3)  /**< \brief Hsmci signal: MCDA7 */
+#define PIO_PE22B_MCDB0      (1u << 22) /**< \brief Hsmci signal: MCDB0 */
+#define PIO_PE24B_MCDB1      (1u << 24) /**< \brief Hsmci signal: MCDB1 */
+#define PIO_PE26B_MCDB2      (1u << 26) /**< \brief Hsmci signal: MCDB2 */
+#define PIO_PE27B_MCDB3      (1u << 27) /**< \brief Hsmci signal: MCDB3 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA1B_PCK0        (1u << 1)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB22B_PCK0       (1u << 22) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA24B_PCK1       (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA30B_PCK1       (1u << 30) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA28B_PCK2       (1u << 28) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2       (1u << 31) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA5B_PWMFI0      (1u << 5)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA3B_PWMFI1      (1u << 3)  /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PD6B_PWMFI2      (1u << 6)  /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA8B_PWMH0       (1u << 8)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB12B_PWMH0      (1u << 12) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC3B_PWMH0       (1u << 3)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PE15A_PWMH0      (1u << 15) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA19B_PWMH1      (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB13B_PWMH1      (1u << 13) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC5B_PWMH1       (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PE16A_PWMH1      (1u << 16) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA13B_PWMH2      (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB14B_PWMH2      (1u << 14) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC7B_PWMH2       (1u << 7)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB15B_PWMH3      (1u << 15) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PF3A_PWMH3       (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC20B_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PE20A_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PC19B_PWMH5      (1u << 19) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PE22A_PWMH5      (1u << 22) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PC18B_PWMH6      (1u << 18) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE24A_PWMH6      (1u << 24) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE26A_PWMH7      (1u << 26) /**< \brief Pwm signal: PWMH7 */
+#define PIO_PA21B_PWML0      (1u << 21) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB16B_PWML0      (1u << 16) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC2B_PWML0       (1u << 2)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PE18A_PWML0      (1u << 18) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA12B_PWML1      (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB17B_PWML1      (1u << 17) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC4B_PWML1       (1u << 4)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PA20B_PWML2      (1u << 20) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB18B_PWML2      (1u << 18) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC6B_PWML2       (1u << 6)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PE17A_PWML2      (1u << 17) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA0B_PWML3       (1u << 0)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB19B_PWML3      (1u << 19) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC8B_PWML3       (1u << 8)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB6B_PWML4       (1u << 6)  /**< \brief Pwm signal: PWML4 */
+#define PIO_PC21B_PWML4      (1u << 21) /**< \brief Pwm signal: PWML4 */
+#define PIO_PE19A_PWML4      (1u << 19) /**< \brief Pwm signal: PWML4 */
+#define PIO_PB7B_PWML5       (1u << 7)  /**< \brief Pwm signal: PWML5 */
+#define PIO_PC22B_PWML5      (1u << 22) /**< \brief Pwm signal: PWML5 */
+#define PIO_PE21A_PWML5      (1u << 21) /**< \brief Pwm signal: PWML5 */
+#define PIO_PB8B_PWML6       (1u << 8)  /**< \brief Pwm signal: PWML6 */
+#define PIO_PC23B_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PE23A_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PB9B_PWML7       (1u << 9)  /**< \brief Pwm signal: PWML7 */
+#define PIO_PC24B_PWML7      (1u << 24) /**< \brief Pwm signal: PWML7 */
+#define PIO_PE25A_PWML7      (1u << 25) /**< \brief Pwm signal: PWML7 */
+/* ========== Pio definition for SPI0 peripheral ========== */
+#define PIO_PA25A_SPI0_MISO  (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */
+#define PIO_PA26A_SPI0_MOSI  (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */
+#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */
+#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PA27A_SPI0_SPCK  (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */
+/* ========== Pio definition for SPI1 peripheral ========== */
+#define PIO_PE28A_SPI1_MISO  (1u << 28) /**< \brief Spi1 signal: SPI1_MISO */
+#define PIO_PE29A_SPI1_MOSI  (1u << 29) /**< \brief Spi1 signal: SPI1_MOSI */
+#define PIO_PE31A_SPI1_NPCS0 (1u << 31) /**< \brief Spi1 signal: SPI1_NPCS0 */
+#define PIO_PF0A_SPI1_NPCS1  (1u << 0)  /**< \brief Spi1 signal: SPI1_NPCS1 */
+#define PIO_PF1A_SPI1_NPCS2  (1u << 1)  /**< \brief Spi1 signal: SPI1_NPCS2 */
+#define PIO_PF2A_SPI1_NPCS3  (1u << 2)  /**< \brief Spi1 signal: SPI1_NPCS3 */
+#define PIO_PE30A_SPI1_SPCK  (1u << 30) /**< \brief Spi1 signal: SPI1_SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PB18A_RD         (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PB17A_RF         (1u << 17) /**< \brief Ssc signal: RF */
+#define PIO_PB19A_RK         (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA16B_TD         (1u << 16) /**< \brief Ssc signal: TD */
+#define PIO_PA15B_TF         (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA14B_TK         (1u << 14) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PB26B_TCLK0      (1u << 26) /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA4A_TCLK1       (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA7A_TCLK2       (1u << 7)  /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PB25B_TIOA0      (1u << 25) /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA2A_TIOA1       (1u << 2)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA5A_TIOA2       (1u << 5)  /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PB27B_TIOB0      (1u << 27) /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA3A_TIOB1       (1u << 3)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA6A_TIOB2       (1u << 6)  /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PA22B_TCLK3      (1u << 22) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PA23B_TCLK4      (1u << 23) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PB16A_TCLK5      (1u << 16) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PB0B_TIOA3       (1u << 0)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PE9A_TIOA3       (1u << 9)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PB2B_TIOA4       (1u << 2)  /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PE11A_TIOA4      (1u << 11) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PB4B_TIOA5       (1u << 4)  /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PE13A_TIOA5      (1u << 13) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PB1B_TIOB3       (1u << 1)  /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PE10A_TIOB3      (1u << 10) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PB3B_TIOB4       (1u << 3)  /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PE12A_TIOB4      (1u << 12) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PB5B_TIOB5       (1u << 5)  /**< \brief Tc1 signal: TIOB5 */
+#define PIO_PE14A_TIOB5      (1u << 14) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TC2 peripheral ========== */
+#define PIO_PC27B_TCLK6      (1u << 27) /**< \brief Tc2 signal: TCLK6 */
+#define PIO_PC30B_TCLK7      (1u << 30) /**< \brief Tc2 signal: TCLK7 */
+#define PIO_PD9B_TCLK8       (1u << 9)  /**< \brief Tc2 signal: TCLK8 */
+#define PIO_PC25B_TIOA6      (1u << 25) /**< \brief Tc2 signal: TIOA6 */
+#define PIO_PC28B_TIOA7      (1u << 28) /**< \brief Tc2 signal: TIOA7 */
+#define PIO_PD7B_TIOA8       (1u << 7)  /**< \brief Tc2 signal: TIOA8 */
+#define PIO_PC26B_TIOB6      (1u << 26) /**< \brief Tc2 signal: TIOB6 */
+#define PIO_PC29B_TIOB7      (1u << 29) /**< \brief Tc2 signal: TIOB7 */
+#define PIO_PD8B_TIOB8       (1u << 8)  /**< \brief Tc2 signal: TIOB8 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA18A_TWCK0      (1u << 18) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA17A_TWD0       (1u << 17) /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB13A_TWCK1      (1u << 13) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB12A_TWD1       (1u << 12) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA8A_URXD        (1u << 8)  /**< \brief Uart signal: URXD */
+#define PIO_PA9A_UTXD        (1u << 9)  /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for UOTGHS peripheral ========== */
+#define PIO_PB11A_UOTGID     (1u << 11) /**< \brief Uotghs signal: UOTGID */
+#define PIO_PB10A_UOTGVBOF   (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB26A_CTS0       (1u << 26) /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB25A_RTS0       (1u << 25) /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA10A_RXD0       (1u << 10) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17B_SCK0       (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA11A_TXD0       (1u << 11) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA15A_CTS1       (1u << 15) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA14A_RTS1       (1u << 14) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA12A_RXD1       (1u << 12) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA16A_SCK1       (1u << 16) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA13A_TXD1       (1u << 13) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB23A_CTS2       (1u << 23) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB22A_RTS2       (1u << 22) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PB21A_RXD2       (1u << 21) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PB24A_SCK2       (1u << 24) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PB20A_TXD2       (1u << 20) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio definition for USART3 peripheral ========== */
+#define PIO_PF4A_CTS3        (1u << 4)  /**< \brief Usart3 signal: CTS3 */
+#define PIO_PF5A_RTS3        (1u << 5)  /**< \brief Usart3 signal: RTS3 */
+#define PIO_PD5B_RXD3        (1u << 5)  /**< \brief Usart3 signal: RXD3 */
+#define PIO_PE16B_SCK3       (1u << 16) /**< \brief Usart3 signal: SCK3 */
+#define PIO_PD4B_TXD3        (1u << 4)  /**< \brief Usart3 signal: TXD3 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX          0
+#define PIO_PA1_IDX          1
+#define PIO_PA2_IDX          2
+#define PIO_PA3_IDX          3
+#define PIO_PA4_IDX          4
+#define PIO_PA5_IDX          5
+#define PIO_PA6_IDX          6
+#define PIO_PA7_IDX          7
+#define PIO_PA8_IDX          8
+#define PIO_PA9_IDX          9
+#define PIO_PA10_IDX         10
+#define PIO_PA11_IDX         11
+#define PIO_PA12_IDX         12
+#define PIO_PA13_IDX         13
+#define PIO_PA14_IDX         14
+#define PIO_PA15_IDX         15
+#define PIO_PA16_IDX         16
+#define PIO_PA17_IDX         17
+#define PIO_PA18_IDX         18
+#define PIO_PA19_IDX         19
+#define PIO_PA20_IDX         20
+#define PIO_PA21_IDX         21
+#define PIO_PA22_IDX         22
+#define PIO_PA23_IDX         23
+#define PIO_PA24_IDX         24
+#define PIO_PA25_IDX         25
+#define PIO_PA26_IDX         26
+#define PIO_PA27_IDX         27
+#define PIO_PA28_IDX         28
+#define PIO_PA29_IDX         29
+#define PIO_PA30_IDX         30
+#define PIO_PA31_IDX         31
+#define PIO_PB0_IDX          32
+#define PIO_PB1_IDX          33
+#define PIO_PB2_IDX          34
+#define PIO_PB3_IDX          35
+#define PIO_PB4_IDX          36
+#define PIO_PB5_IDX          37
+#define PIO_PB6_IDX          38
+#define PIO_PB7_IDX          39
+#define PIO_PB8_IDX          40
+#define PIO_PB9_IDX          41
+#define PIO_PB10_IDX         42
+#define PIO_PB11_IDX         43
+#define PIO_PB12_IDX         44
+#define PIO_PB13_IDX         45
+#define PIO_PB14_IDX         46
+#define PIO_PB15_IDX         47
+#define PIO_PB16_IDX         48
+#define PIO_PB17_IDX         49
+#define PIO_PB18_IDX         50
+#define PIO_PB19_IDX         51
+#define PIO_PB20_IDX         52
+#define PIO_PB21_IDX         53
+#define PIO_PB22_IDX         54
+#define PIO_PB23_IDX         55
+#define PIO_PB24_IDX         56
+#define PIO_PB25_IDX         57
+#define PIO_PB26_IDX         58
+#define PIO_PB27_IDX         59
+#define PIO_PB28_IDX         60
+#define PIO_PB29_IDX         61
+#define PIO_PB30_IDX         62
+#define PIO_PB31_IDX         63
+#define PIO_PC0_IDX          64
+#define PIO_PC1_IDX          65
+#define PIO_PC2_IDX          66
+#define PIO_PC3_IDX          67
+#define PIO_PC4_IDX          68
+#define PIO_PC5_IDX          69
+#define PIO_PC6_IDX          70
+#define PIO_PC7_IDX          71
+#define PIO_PC8_IDX          72
+#define PIO_PC9_IDX          73
+#define PIO_PC10_IDX         74
+#define PIO_PC11_IDX         75
+#define PIO_PC12_IDX         76
+#define PIO_PC13_IDX         77
+#define PIO_PC14_IDX         78
+#define PIO_PC15_IDX         79
+#define PIO_PC16_IDX         80
+#define PIO_PC17_IDX         81
+#define PIO_PC18_IDX         82
+#define PIO_PC19_IDX         83
+#define PIO_PC20_IDX         84
+#define PIO_PC21_IDX         85
+#define PIO_PC22_IDX         86
+#define PIO_PC23_IDX         87
+#define PIO_PC24_IDX         88
+#define PIO_PC25_IDX         89
+#define PIO_PC26_IDX         90
+#define PIO_PC27_IDX         91
+#define PIO_PC28_IDX         92
+#define PIO_PC29_IDX         93
+#define PIO_PC30_IDX         94
+#define PIO_PD0_IDX          96
+#define PIO_PD1_IDX          97
+#define PIO_PD2_IDX          98
+#define PIO_PD3_IDX          99
+#define PIO_PD4_IDX          100
+#define PIO_PD5_IDX          101
+#define PIO_PD6_IDX          102
+#define PIO_PD7_IDX          103
+#define PIO_PD8_IDX          104
+#define PIO_PD9_IDX          105
+#define PIO_PD10_IDX         106
+#define PIO_PD11_IDX         107
+#define PIO_PD12_IDX         108
+#define PIO_PD13_IDX         109
+#define PIO_PD14_IDX         110
+#define PIO_PD15_IDX         111
+#define PIO_PD16_IDX         112
+#define PIO_PD17_IDX         113
+#define PIO_PD18_IDX         114
+#define PIO_PD19_IDX         115
+#define PIO_PD20_IDX         116
+#define PIO_PD21_IDX         117
+#define PIO_PD22_IDX         118
+#define PIO_PD23_IDX         119
+#define PIO_PD24_IDX         120
+#define PIO_PD25_IDX         121
+#define PIO_PD26_IDX         122
+#define PIO_PD27_IDX         123
+#define PIO_PD28_IDX         124
+#define PIO_PD29_IDX         125
+#define PIO_PD30_IDX         126
+#define PIO_PE0_IDX          128
+#define PIO_PE1_IDX          129
+#define PIO_PE2_IDX          130
+#define PIO_PE3_IDX          131
+#define PIO_PE4_IDX          132
+#define PIO_PE5_IDX          133
+#define PIO_PE6_IDX          134
+#define PIO_PE7_IDX          135
+#define PIO_PE8_IDX          136
+#define PIO_PE9_IDX          137
+#define PIO_PE10_IDX         138
+#define PIO_PE11_IDX         139
+#define PIO_PE12_IDX         140
+#define PIO_PE13_IDX         141
+#define PIO_PE14_IDX         142
+#define PIO_PE15_IDX         143
+#define PIO_PE16_IDX         144
+#define PIO_PE17_IDX         145
+#define PIO_PE18_IDX         146
+#define PIO_PE19_IDX         147
+#define PIO_PE20_IDX         148
+#define PIO_PE21_IDX         149
+#define PIO_PE22_IDX         150
+#define PIO_PE23_IDX         151
+#define PIO_PE24_IDX         152
+#define PIO_PE25_IDX         153
+#define PIO_PE26_IDX         154
+#define PIO_PE27_IDX         155
+#define PIO_PE28_IDX         156
+#define PIO_PE29_IDX         157
+#define PIO_PE30_IDX         158
+#define PIO_PE31_IDX         159
+#define PIO_PF0_IDX          160
+#define PIO_PF1_IDX          161
+#define PIO_PF2_IDX          162
+#define PIO_PF3_IDX          163
+#define PIO_PF4_IDX          164
+#define PIO_PF5_IDX          165
+
+#endif /* _SAM3X8H_PIO_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3a2c.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3a2c.h
new file mode 100644
index 000000000..47d0b5440
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3a2c.h
@@ -0,0 +1,402 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3A2C_
+#define _SAM3A2C_
+
+/** \addtogroup SAM3A2C_definitions SAM3A2C definitions
+  This file defines all structures and symbols for SAM3A2C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3A2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A2C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3A2C specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3A2C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3A2C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3A2C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3A2C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3A2C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3A2C Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3A2C Enhanced Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3A2C Enhanced Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3A2C Universal Asynchronous Receiver Transceiver (UART) */
+  PIOA_IRQn            = 11, /**< 11 SAM3A2C Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3A2C Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 17, /**< 17 SAM3A2C USART 0 (USART0) */
+  USART1_IRQn          = 18, /**< 18 SAM3A2C USART 1 (USART1) */
+  USART2_IRQn          = 19, /**< 19 SAM3A2C USART 2 (USART2) */
+  HSMCI_IRQn           = 21, /**< 21 SAM3A2C Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 22, /**< 22 SAM3A2C Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 23, /**< 23 SAM3A2C Two-Wire Interface 1 (TWI1) */
+  SPI0_IRQn            = 24, /**< 24 SAM3A2C Serial Peripheral Interface (SPI0) */
+  SSC_IRQn             = 26, /**< 26 SAM3A2C Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 27, /**< 27 SAM3A2C Timer Counter 0 (TC0) */
+  TC1_IRQn             = 28, /**< 28 SAM3A2C Timer Counter 1 (TC1) */
+  TC2_IRQn             = 29, /**< 29 SAM3A2C Timer Counter 2 (TC2) */
+  TC3_IRQn             = 30, /**< 30 SAM3A2C Timer Counter 3 (TC3) */
+  TC4_IRQn             = 31, /**< 31 SAM3A2C Timer Counter 4 (TC4) */
+  TC5_IRQn             = 32, /**< 32 SAM3A2C Timer Counter 5 (TC5) */
+  PWM_IRQn             = 36, /**< 36 SAM3A2C Pulse Width Modulation Controller (PWM) */
+  ADC_IRQn             = 37, /**< 37 SAM3A2C ADC Controller (ADC) */
+  DACC_IRQn            = 38, /**< 38 SAM3A2C DAC Controller (DACC) */
+  DMAC_IRQn            = 39, /**< 39 SAM3A2C DMA Controller (DMAC) */
+  UOTGHS_IRQn          = 40, /**< 40 SAM3A2C USB OTG High Speed (UOTGHS) */
+  TRNG_IRQn            = 41, /**< 41 SAM3A2C True Random Number Generator (TRNG) */
+  CAN0_IRQn            = 43, /**< 43 SAM3A2C CAN Controller 0 (CAN0) */
+  CAN1_IRQn            = 44  /**< 44 SAM3A2C CAN Controller 1 (CAN1) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3A2C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3A2C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3A2C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3A2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A2C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_can.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_trng.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_uotghs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3A2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A2C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi0.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_uotghs.h"
+#include "instance/instance_can0.h"
+#include "instance/instance_can1.h"
+#include "instance/instance_trng.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3A2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A2C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (17) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (18) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (19) /**< \brief USART 2 (USART2) */
+#define ID_HSMCI  (21) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (22) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (23) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI0   (24) /**< \brief Serial Peripheral Interface (SPI0) */
+#define ID_SSC    (26) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (27) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (28) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (29) /**< \brief Timer Counter 2 (TC2) */
+#define ID_TC3    (30) /**< \brief Timer Counter 3 (TC3) */
+#define ID_TC4    (31) /**< \brief Timer Counter 4 (TC4) */
+#define ID_TC5    (32) /**< \brief Timer Counter 5 (TC5) */
+#define ID_PWM    (36) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC    (37) /**< \brief ADC Controller (ADC) */
+#define ID_DACC   (38) /**< \brief DAC Controller (DACC) */
+#define ID_DMAC   (39) /**< \brief DMA Controller (DMAC) */
+#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */
+#define ID_TRNG   (41) /**< \brief True Random Number Generator (TRNG) */
+#define ID_CAN0   (43) /**< \brief CAN Controller 0 (CAN0) */
+#define ID_CAN1   (44) /**< \brief CAN Controller 1 (CAN1) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3A2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A2C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       (0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define UOTGHS     (0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define CAN0       (0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       (0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       (0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        (0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       (0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       ((Spi    *)0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define UOTGHS     ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define CAN0       ((Can    *)0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       ((Can    *)0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       ((Trng   *)0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        ((Adc    *)0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       ((Dacc   *)0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3A2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A2C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3a2c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3A2C */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x10000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (256u)
+#define IFLASH1_SIZE             (0x10000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (256u)
+#define IRAM0_SIZE               (0x4000u)
+#define IRAM1_SIZE               (0x4000u)
+#define IFLASH_SIZE              (0x20000u)
+#define IRAM_SIZE                (0x8000u)
+
+#define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR    (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IROM_ADDR       (0x00100000u) /**< Internal ROM base address */
+#define IRAM0_ADDR      (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR      (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR    (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */
+#define EBI_CS0_ADDR    (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR    (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR    (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR    (0x63000000u) /**< EBI Chip Select 3 base address */
+#define EBI_CS4_ADDR    (0x64000000u) /**< EBI Chip Select 4 base address */
+#define EBI_CS5_ADDR    (0x65000000u) /**< EBI Chip Select 5 base address */
+#define EBI_CS6_ADDR    (0x66000000u) /**< EBI Chip Select 6 base address */
+#define EBI_CS7_ADDR    (0x67000000u) /**< EBI Chip Select 7 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3A2C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (84000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3A2C_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3a4c.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3a4c.h
new file mode 100644
index 000000000..7c95eace8
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3a4c.h
@@ -0,0 +1,402 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3A4C_
+#define _SAM3A4C_
+
+/** \addtogroup SAM3A4C_definitions SAM3A4C definitions
+  This file defines all structures and symbols for SAM3A4C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3A4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A4C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3A4C specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3A4C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3A4C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3A4C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3A4C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3A4C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3A4C Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3A4C Enhanced Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3A4C Enhanced Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3A4C Universal Asynchronous Receiver Transceiver (UART) */
+  PIOA_IRQn            = 11, /**< 11 SAM3A4C Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3A4C Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 17, /**< 17 SAM3A4C USART 0 (USART0) */
+  USART1_IRQn          = 18, /**< 18 SAM3A4C USART 1 (USART1) */
+  USART2_IRQn          = 19, /**< 19 SAM3A4C USART 2 (USART2) */
+  HSMCI_IRQn           = 21, /**< 21 SAM3A4C Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 22, /**< 22 SAM3A4C Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 23, /**< 23 SAM3A4C Two-Wire Interface 1 (TWI1) */
+  SPI0_IRQn            = 24, /**< 24 SAM3A4C Serial Peripheral Interface (SPI0) */
+  SSC_IRQn             = 26, /**< 26 SAM3A4C Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 27, /**< 27 SAM3A4C Timer Counter 0 (TC0) */
+  TC1_IRQn             = 28, /**< 28 SAM3A4C Timer Counter 1 (TC1) */
+  TC2_IRQn             = 29, /**< 29 SAM3A4C Timer Counter 2 (TC2) */
+  TC3_IRQn             = 30, /**< 30 SAM3A4C Timer Counter 3 (TC3) */
+  TC4_IRQn             = 31, /**< 31 SAM3A4C Timer Counter 4 (TC4) */
+  TC5_IRQn             = 32, /**< 32 SAM3A4C Timer Counter 5 (TC5) */
+  PWM_IRQn             = 36, /**< 36 SAM3A4C Pulse Width Modulation Controller (PWM) */
+  ADC_IRQn             = 37, /**< 37 SAM3A4C ADC Controller (ADC) */
+  DACC_IRQn            = 38, /**< 38 SAM3A4C DAC Controller (DACC) */
+  DMAC_IRQn            = 39, /**< 39 SAM3A4C DMA Controller (DMAC) */
+  UOTGHS_IRQn          = 40, /**< 40 SAM3A4C USB OTG High Speed (UOTGHS) */
+  TRNG_IRQn            = 41, /**< 41 SAM3A4C True Random Number Generator (TRNG) */
+  CAN0_IRQn            = 43, /**< 43 SAM3A4C CAN Controller 0 (CAN0) */
+  CAN1_IRQn            = 44  /**< 44 SAM3A4C CAN Controller 1 (CAN1) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3A4C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3A4C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3A4C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3A4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A4C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_can.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_trng.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_uotghs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3A4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A4C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi0.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_uotghs.h"
+#include "instance/instance_can0.h"
+#include "instance/instance_can1.h"
+#include "instance/instance_trng.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3A4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A4C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (17) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (18) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (19) /**< \brief USART 2 (USART2) */
+#define ID_HSMCI  (21) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (22) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (23) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI0   (24) /**< \brief Serial Peripheral Interface (SPI0) */
+#define ID_SSC    (26) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (27) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (28) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (29) /**< \brief Timer Counter 2 (TC2) */
+#define ID_TC3    (30) /**< \brief Timer Counter 3 (TC3) */
+#define ID_TC4    (31) /**< \brief Timer Counter 4 (TC4) */
+#define ID_TC5    (32) /**< \brief Timer Counter 5 (TC5) */
+#define ID_PWM    (36) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC    (37) /**< \brief ADC Controller (ADC) */
+#define ID_DACC   (38) /**< \brief DAC Controller (DACC) */
+#define ID_DMAC   (39) /**< \brief DMA Controller (DMAC) */
+#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */
+#define ID_TRNG   (41) /**< \brief True Random Number Generator (TRNG) */
+#define ID_CAN0   (43) /**< \brief CAN Controller 0 (CAN0) */
+#define ID_CAN1   (44) /**< \brief CAN Controller 1 (CAN1) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3A4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A4C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       (0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define UOTGHS     (0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define CAN0       (0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       (0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       (0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        (0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       (0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       ((Spi    *)0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define UOTGHS     ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define CAN0       ((Can    *)0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       ((Can    *)0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       ((Trng   *)0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        ((Adc    *)0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       ((Dacc   *)0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3A4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A4C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3a4c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3A4C */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x20000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (512u)
+#define IFLASH1_SIZE             (0x20000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (512u)
+#define IRAM0_SIZE               (0x8000u)
+#define IRAM1_SIZE               (0x8000u)
+#define IFLASH_SIZE              (0x40000u)
+#define IRAM_SIZE                (0x10000u)
+
+#define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR    (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IROM_ADDR       (0x00100000u) /**< Internal ROM base address */
+#define IRAM0_ADDR      (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR      (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR    (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */
+#define EBI_CS0_ADDR    (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR    (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR    (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR    (0x63000000u) /**< EBI Chip Select 3 base address */
+#define EBI_CS4_ADDR    (0x64000000u) /**< EBI Chip Select 4 base address */
+#define EBI_CS5_ADDR    (0x65000000u) /**< EBI Chip Select 5 base address */
+#define EBI_CS6_ADDR    (0x66000000u) /**< EBI Chip Select 6 base address */
+#define EBI_CS7_ADDR    (0x67000000u) /**< EBI Chip Select 7 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3A4C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (84000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3A4C_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3a8c.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3a8c.h
new file mode 100644
index 000000000..20ffbb2a7
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3a8c.h
@@ -0,0 +1,402 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3A8C_
+#define _SAM3A8C_
+
+/** \addtogroup SAM3A8C_definitions SAM3A8C definitions
+  This file defines all structures and symbols for SAM3A8C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3A8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A8C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3A8C specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3A8C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3A8C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3A8C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3A8C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3A8C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3A8C Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3A8C Enhanced Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3A8C Enhanced Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3A8C Universal Asynchronous Receiver Transceiver (UART) */
+  PIOA_IRQn            = 11, /**< 11 SAM3A8C Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3A8C Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 17, /**< 17 SAM3A8C USART 0 (USART0) */
+  USART1_IRQn          = 18, /**< 18 SAM3A8C USART 1 (USART1) */
+  USART2_IRQn          = 19, /**< 19 SAM3A8C USART 2 (USART2) */
+  HSMCI_IRQn           = 21, /**< 21 SAM3A8C Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 22, /**< 22 SAM3A8C Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 23, /**< 23 SAM3A8C Two-Wire Interface 1 (TWI1) */
+  SPI0_IRQn            = 24, /**< 24 SAM3A8C Serial Peripheral Interface (SPI0) */
+  SSC_IRQn             = 26, /**< 26 SAM3A8C Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 27, /**< 27 SAM3A8C Timer Counter 0 (TC0) */
+  TC1_IRQn             = 28, /**< 28 SAM3A8C Timer Counter 1 (TC1) */
+  TC2_IRQn             = 29, /**< 29 SAM3A8C Timer Counter 2 (TC2) */
+  TC3_IRQn             = 30, /**< 30 SAM3A8C Timer Counter 3 (TC3) */
+  TC4_IRQn             = 31, /**< 31 SAM3A8C Timer Counter 4 (TC4) */
+  TC5_IRQn             = 32, /**< 32 SAM3A8C Timer Counter 5 (TC5) */
+  PWM_IRQn             = 36, /**< 36 SAM3A8C Pulse Width Modulation Controller (PWM) */
+  ADC_IRQn             = 37, /**< 37 SAM3A8C ADC Controller (ADC) */
+  DACC_IRQn            = 38, /**< 38 SAM3A8C DAC Controller (DACC) */
+  DMAC_IRQn            = 39, /**< 39 SAM3A8C DMA Controller (DMAC) */
+  UOTGHS_IRQn          = 40, /**< 40 SAM3A8C USB OTG High Speed (UOTGHS) */
+  TRNG_IRQn            = 41, /**< 41 SAM3A8C True Random Number Generator (TRNG) */
+  CAN0_IRQn            = 43, /**< 43 SAM3A8C CAN Controller 0 (CAN0) */
+  CAN1_IRQn            = 44  /**< 44 SAM3A8C CAN Controller 1 (CAN1) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3A8C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3A8C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3A8C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3A8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A8C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_can.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_trng.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_uotghs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3A8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A8C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi0.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_uotghs.h"
+#include "instance/instance_can0.h"
+#include "instance/instance_can1.h"
+#include "instance/instance_trng.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3A8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A8C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (17) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (18) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (19) /**< \brief USART 2 (USART2) */
+#define ID_HSMCI  (21) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (22) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (23) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI0   (24) /**< \brief Serial Peripheral Interface (SPI0) */
+#define ID_SSC    (26) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (27) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (28) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (29) /**< \brief Timer Counter 2 (TC2) */
+#define ID_TC3    (30) /**< \brief Timer Counter 3 (TC3) */
+#define ID_TC4    (31) /**< \brief Timer Counter 4 (TC4) */
+#define ID_TC5    (32) /**< \brief Timer Counter 5 (TC5) */
+#define ID_PWM    (36) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC    (37) /**< \brief ADC Controller (ADC) */
+#define ID_DACC   (38) /**< \brief DAC Controller (DACC) */
+#define ID_DMAC   (39) /**< \brief DMA Controller (DMAC) */
+#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */
+#define ID_TRNG   (41) /**< \brief True Random Number Generator (TRNG) */
+#define ID_CAN0   (43) /**< \brief CAN Controller 0 (CAN0) */
+#define ID_CAN1   (44) /**< \brief CAN Controller 1 (CAN1) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3A8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A8C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       (0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define UOTGHS     (0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define CAN0       (0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       (0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       (0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        (0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       (0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       ((Spi    *)0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define UOTGHS     ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define CAN0       ((Can    *)0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       ((Can    *)0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       ((Trng   *)0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        ((Adc    *)0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       ((Dacc   *)0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3A8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A8C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3a8c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3A8C */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x40000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (1024u)
+#define IFLASH1_SIZE             (0x40000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (1024u)
+#define IRAM0_SIZE               (0x10000u)
+#define IRAM1_SIZE               (0x8000u)
+#define IFLASH_SIZE              (0x80000u)
+#define IRAM_SIZE                (0x18000u)
+
+#define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR    (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IROM_ADDR       (0x00100000u) /**< Internal ROM base address */
+#define IRAM0_ADDR      (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR      (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR    (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */
+#define EBI_CS0_ADDR    (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR    (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR    (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR    (0x63000000u) /**< EBI Chip Select 3 base address */
+#define EBI_CS4_ADDR    (0x64000000u) /**< EBI Chip Select 4 base address */
+#define EBI_CS5_ADDR    (0x65000000u) /**< EBI Chip Select 5 base address */
+#define EBI_CS6_ADDR    (0x66000000u) /**< EBI Chip Select 6 base address */
+#define EBI_CS7_ADDR    (0x67000000u) /**< EBI Chip Select 7 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3A8C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (84000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3A8C_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x4c.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x4c.h
new file mode 100644
index 000000000..c539981f9
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x4c.h
@@ -0,0 +1,408 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3X4C_
+#define _SAM3X4C_
+
+/** \addtogroup SAM3X4C_definitions SAM3X4C definitions
+  This file defines all structures and symbols for SAM3X4C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3X4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3X4C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3X4C specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3X4C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3X4C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3X4C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3X4C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3X4C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3X4C Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3X4C Enhanced Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3X4C Enhanced Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3X4C Universal Asynchronous Receiver Transceiver (UART) */
+  PIOA_IRQn            = 11, /**< 11 SAM3X4C Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3X4C Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 17, /**< 17 SAM3X4C USART 0 (USART0) */
+  USART1_IRQn          = 18, /**< 18 SAM3X4C USART 1 (USART1) */
+  USART2_IRQn          = 19, /**< 19 SAM3X4C USART 2 (USART2) */
+  HSMCI_IRQn           = 21, /**< 21 SAM3X4C Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 22, /**< 22 SAM3X4C Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 23, /**< 23 SAM3X4C Two-Wire Interface 1 (TWI1) */
+  SPI0_IRQn            = 24, /**< 24 SAM3X4C Serial Peripheral Interface (SPI0) */
+  SSC_IRQn             = 26, /**< 26 SAM3X4C Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 27, /**< 27 SAM3X4C Timer Counter 0 (TC0) */
+  TC1_IRQn             = 28, /**< 28 SAM3X4C Timer Counter 1 (TC1) */
+  TC2_IRQn             = 29, /**< 29 SAM3X4C Timer Counter 2 (TC2) */
+  TC3_IRQn             = 30, /**< 30 SAM3X4C Timer Counter 3 (TC3) */
+  TC4_IRQn             = 31, /**< 31 SAM3X4C Timer Counter 4 (TC4) */
+  TC5_IRQn             = 32, /**< 32 SAM3X4C Timer Counter 5 (TC5) */
+  PWM_IRQn             = 36, /**< 36 SAM3X4C Pulse Width Modulation Controller (PWM) */
+  ADC_IRQn             = 37, /**< 37 SAM3X4C ADC Controller (ADC) */
+  DACC_IRQn            = 38, /**< 38 SAM3X4C DAC Controller (DACC) */
+  DMAC_IRQn            = 39, /**< 39 SAM3X4C DMA Controller (DMAC) */
+  UOTGHS_IRQn          = 40, /**< 40 SAM3X4C USB OTG High Speed (UOTGHS) */
+  TRNG_IRQn            = 41, /**< 41 SAM3X4C True Random Number Generator (TRNG) */
+  EMAC_IRQn            = 42, /**< 42 SAM3X4C Ethernet MAC (EMAC) */
+  CAN0_IRQn            = 43, /**< 43 SAM3X4C CAN Controller 0 (CAN0) */
+  CAN1_IRQn            = 44  /**< 44 SAM3X4C CAN Controller 1 (CAN1) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3X4C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3X4C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3X4C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3X4C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_can.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_emac.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_trng.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_uotghs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3X4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3X4C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi0.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_uotghs.h"
+#include "instance/instance_emac.h"
+#include "instance/instance_can0.h"
+#include "instance/instance_can1.h"
+#include "instance/instance_trng.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3X4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3X4C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (17) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (18) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (19) /**< \brief USART 2 (USART2) */
+#define ID_HSMCI  (21) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (22) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (23) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI0   (24) /**< \brief Serial Peripheral Interface (SPI0) */
+#define ID_SSC    (26) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (27) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (28) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (29) /**< \brief Timer Counter 2 (TC2) */
+#define ID_TC3    (30) /**< \brief Timer Counter 3 (TC3) */
+#define ID_TC4    (31) /**< \brief Timer Counter 4 (TC4) */
+#define ID_TC5    (32) /**< \brief Timer Counter 5 (TC5) */
+#define ID_PWM    (36) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC    (37) /**< \brief ADC Controller (ADC) */
+#define ID_DACC   (38) /**< \brief DAC Controller (DACC) */
+#define ID_DMAC   (39) /**< \brief DMA Controller (DMAC) */
+#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */
+#define ID_TRNG   (41) /**< \brief True Random Number Generator (TRNG) */
+#define ID_EMAC   (42) /**< \brief Ethernet MAC (EMAC) */
+#define ID_CAN0   (43) /**< \brief CAN Controller 0 (CAN0) */
+#define ID_CAN1   (44) /**< \brief CAN Controller 1 (CAN1) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3X4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3X4C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       (0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define UOTGHS     (0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define EMAC       (0x400B0000U) /**< \brief (EMAC      ) Base Address */
+#define CAN0       (0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       (0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       (0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        (0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       (0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       ((Spi    *)0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define UOTGHS     ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define EMAC       ((Emac   *)0x400B0000U) /**< \brief (EMAC      ) Base Address */
+#define CAN0       ((Can    *)0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       ((Can    *)0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       ((Trng   *)0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        ((Adc    *)0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       ((Dacc   *)0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3X4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3X4C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3x4c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3X4C */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x20000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (512u)
+#define IFLASH1_SIZE             (0x20000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (512u)
+#define IRAM0_SIZE               (0x8000u)
+#define IRAM1_SIZE               (0x8000u)
+#define IFLASH_SIZE              (0x40000u)
+#define IRAM_SIZE                (0x10000u)
+
+#define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR    (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IROM_ADDR       (0x00100000u) /**< Internal ROM base address */
+#define IRAM0_ADDR      (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR      (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR    (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */
+#define EBI_CS0_ADDR    (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR    (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR    (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR    (0x63000000u) /**< EBI Chip Select 3 base address */
+#define EBI_CS4_ADDR    (0x64000000u) /**< EBI Chip Select 4 base address */
+#define EBI_CS5_ADDR    (0x65000000u) /**< EBI Chip Select 5 base address */
+#define EBI_CS6_ADDR    (0x66000000u) /**< EBI Chip Select 6 base address */
+#define EBI_CS7_ADDR    (0x67000000u) /**< EBI Chip Select 7 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3X4C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (84000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3X4C_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x4e.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x4e.h
new file mode 100644
index 000000000..b5a47a36f
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x4e.h
@@ -0,0 +1,441 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3X4E_
+#define _SAM3X4E_
+
+/** \addtogroup SAM3X4E_definitions SAM3X4E definitions
+  This file defines all structures and symbols for SAM3X4E:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3X4E */
+/* ************************************************************************** */
+/** \addtogroup SAM3X4E_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3X4E specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3X4E Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3X4E Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3X4E Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3X4E Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3X4E Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3X4E Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3X4E Enhanced Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3X4E Enhanced Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3X4E Universal Asynchronous Receiver Transceiver (UART) */
+  SMC_IRQn             =  9, /**<  9 SAM3X4E Static Memory Controller (SMC) */
+  PIOA_IRQn            = 11, /**< 11 SAM3X4E Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3X4E Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM3X4E Parallel I/O Controller C (PIOC) */
+  PIOD_IRQn            = 14, /**< 14 SAM3X4E Parallel I/O Controller D (PIOD) */
+  USART0_IRQn          = 17, /**< 17 SAM3X4E USART 0 (USART0) */
+  USART1_IRQn          = 18, /**< 18 SAM3X4E USART 1 (USART1) */
+  USART2_IRQn          = 19, /**< 19 SAM3X4E USART 2 (USART2) */
+  USART3_IRQn          = 20, /**< 20 SAM3X4E USART 3 (USART3) */
+  HSMCI_IRQn           = 21, /**< 21 SAM3X4E Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 22, /**< 22 SAM3X4E Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 23, /**< 23 SAM3X4E Two-Wire Interface 1 (TWI1) */
+  SPI0_IRQn            = 24, /**< 24 SAM3X4E Serial Peripheral Interface (SPI0) */
+  SSC_IRQn             = 26, /**< 26 SAM3X4E Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 27, /**< 27 SAM3X4E Timer Counter 0 (TC0) */
+  TC1_IRQn             = 28, /**< 28 SAM3X4E Timer Counter 1 (TC1) */
+  TC2_IRQn             = 29, /**< 29 SAM3X4E Timer Counter 2 (TC2) */
+  TC3_IRQn             = 30, /**< 30 SAM3X4E Timer Counter 3 (TC3) */
+  TC4_IRQn             = 31, /**< 31 SAM3X4E Timer Counter 4 (TC4) */
+  TC5_IRQn             = 32, /**< 32 SAM3X4E Timer Counter 5 (TC5) */
+  TC6_IRQn             = 33, /**< 33 SAM3X4E Timer Counter 6 (TC6) */
+  TC7_IRQn             = 34, /**< 34 SAM3X4E Timer Counter 7 (TC7) */
+  TC8_IRQn             = 35, /**< 35 SAM3X4E Timer Counter 8 (TC8) */
+  PWM_IRQn             = 36, /**< 36 SAM3X4E Pulse Width Modulation Controller (PWM) */
+  ADC_IRQn             = 37, /**< 37 SAM3X4E ADC Controller (ADC) */
+  DACC_IRQn            = 38, /**< 38 SAM3X4E DAC Controller (DACC) */
+  DMAC_IRQn            = 39, /**< 39 SAM3X4E DMA Controller (DMAC) */
+  UOTGHS_IRQn          = 40, /**< 40 SAM3X4E USB OTG High Speed (UOTGHS) */
+  TRNG_IRQn            = 41, /**< 41 SAM3X4E True Random Number Generator (TRNG) */
+  EMAC_IRQn            = 42, /**< 42 SAM3X4E Ethernet MAC (EMAC) */
+  CAN0_IRQn            = 43, /**< 43 SAM3X4E CAN Controller 0 (CAN0) */
+  CAN1_IRQn            = 44  /**< 44 SAM3X4E CAN Controller 1 (CAN1) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3X4E core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3X4E does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3X4E uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X4E */
+/* ************************************************************************** */
+/** \addtogroup SAM3X4E_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_can.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_emac.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_trng.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_uotghs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3X4E */
+/* ************************************************************************** */
+/** \addtogroup SAM3X4E_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi0.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_tc2.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_usart3.h"
+#include "instance/instance_uotghs.h"
+#include "instance/instance_emac.h"
+#include "instance/instance_can0.h"
+#include "instance/instance_can1.h"
+#include "instance/instance_trng.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_piod.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3X4E */
+/* ************************************************************************** */
+/** \addtogroup SAM3X4E_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */
+#define ID_SMC    ( 9) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_PIOD   (14) /**< \brief Parallel I/O Controller D (PIOD) */
+#define ID_USART0 (17) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (18) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (19) /**< \brief USART 2 (USART2) */
+#define ID_USART3 (20) /**< \brief USART 3 (USART3) */
+#define ID_HSMCI  (21) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (22) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (23) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI0   (24) /**< \brief Serial Peripheral Interface (SPI0) */
+#define ID_SSC    (26) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (27) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (28) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (29) /**< \brief Timer Counter 2 (TC2) */
+#define ID_TC3    (30) /**< \brief Timer Counter 3 (TC3) */
+#define ID_TC4    (31) /**< \brief Timer Counter 4 (TC4) */
+#define ID_TC5    (32) /**< \brief Timer Counter 5 (TC5) */
+#define ID_TC6    (33) /**< \brief Timer Counter 6 (TC6) */
+#define ID_TC7    (34) /**< \brief Timer Counter 7 (TC7) */
+#define ID_TC8    (35) /**< \brief Timer Counter 8 (TC8) */
+#define ID_PWM    (36) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC    (37) /**< \brief ADC Controller (ADC) */
+#define ID_DACC   (38) /**< \brief DAC Controller (DACC) */
+#define ID_DMAC   (39) /**< \brief DMA Controller (DMAC) */
+#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */
+#define ID_TRNG   (41) /**< \brief True Random Number Generator (TRNG) */
+#define ID_EMAC   (42) /**< \brief Ethernet MAC (EMAC) */
+#define ID_CAN0   (43) /**< \brief CAN Controller 0 (CAN0) */
+#define ID_CAN1   (44) /**< \brief CAN Controller 1 (CAN1) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3X4E */
+/* ************************************************************************** */
+/** \addtogroup SAM3X4E_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       (0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TC2        (0x40088000U) /**< \brief (TC2       ) Base Address */
+#define TWI0       (0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define USART3     (0x400A4000U) /**< \brief (USART3    ) Base Address */
+#define PDC_USART3 (0x400A4100U) /**< \brief (PDC_USART3) Base Address */
+#define UOTGHS     (0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define EMAC       (0x400B0000U) /**< \brief (EMAC      ) Base Address */
+#define CAN0       (0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       (0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       (0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        (0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       (0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define PIOD       (0x400E1400U) /**< \brief (PIOD      ) Base Address */
+#define RSTC       (0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       ((Spi    *)0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TC2        ((Tc     *)0x40088000U) /**< \brief (TC2       ) Base Address */
+#define TWI0       ((Twi    *)0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define USART3     ((Usart  *)0x400A4000U) /**< \brief (USART3    ) Base Address */
+#define PDC_USART3 ((Pdc    *)0x400A4100U) /**< \brief (PDC_USART3) Base Address */
+#define UOTGHS     ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define EMAC       ((Emac   *)0x400B0000U) /**< \brief (EMAC      ) Base Address */
+#define CAN0       ((Can    *)0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       ((Can    *)0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       ((Trng   *)0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        ((Adc    *)0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       ((Dacc   *)0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define PIOD       ((Pio    *)0x400E1400U) /**< \brief (PIOD      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3X4E */
+/* ************************************************************************** */
+/** \addtogroup SAM3X4E_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3x4e.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3X4E */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x20000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (512u)
+#define IFLASH1_SIZE             (0x20000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (512u)
+#define IRAM0_SIZE               (0x8000u)
+#define IRAM1_SIZE               (0x8000u)
+#define NFCRAM_SIZE              (0x1000u)
+#define IFLASH_SIZE              (0x40000u)
+#define IRAM_SIZE                (0x10000u)
+
+#define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR    (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IROM_ADDR       (0x00100000u) /**< Internal ROM base address */
+#define IRAM0_ADDR      (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR      (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR    (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */
+#define EBI_CS0_ADDR    (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR    (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR    (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR    (0x63000000u) /**< EBI Chip Select 3 base address */
+#define EBI_CS4_ADDR    (0x64000000u) /**< EBI Chip Select 4 base address */
+#define EBI_CS5_ADDR    (0x65000000u) /**< EBI Chip Select 5 base address */
+#define EBI_CS6_ADDR    (0x66000000u) /**< EBI Chip Select 6 base address */
+#define EBI_CS7_ADDR    (0x67000000u) /**< EBI Chip Select 7 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3X4E */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (84000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3X4E_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x8c.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x8c.h
new file mode 100644
index 000000000..3314d65df
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x8c.h
@@ -0,0 +1,408 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3X8C_
+#define _SAM3X8C_
+
+/** \addtogroup SAM3X8C_definitions SAM3X8C definitions
+  This file defines all structures and symbols for SAM3X8C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3X8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3X8C specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3X8C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3X8C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3X8C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3X8C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3X8C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3X8C Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3X8C Enhanced Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3X8C Enhanced Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3X8C Universal Asynchronous Receiver Transceiver (UART) */
+  PIOA_IRQn            = 11, /**< 11 SAM3X8C Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3X8C Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 17, /**< 17 SAM3X8C USART 0 (USART0) */
+  USART1_IRQn          = 18, /**< 18 SAM3X8C USART 1 (USART1) */
+  USART2_IRQn          = 19, /**< 19 SAM3X8C USART 2 (USART2) */
+  HSMCI_IRQn           = 21, /**< 21 SAM3X8C Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 22, /**< 22 SAM3X8C Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 23, /**< 23 SAM3X8C Two-Wire Interface 1 (TWI1) */
+  SPI0_IRQn            = 24, /**< 24 SAM3X8C Serial Peripheral Interface (SPI0) */
+  SSC_IRQn             = 26, /**< 26 SAM3X8C Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 27, /**< 27 SAM3X8C Timer Counter 0 (TC0) */
+  TC1_IRQn             = 28, /**< 28 SAM3X8C Timer Counter 1 (TC1) */
+  TC2_IRQn             = 29, /**< 29 SAM3X8C Timer Counter 2 (TC2) */
+  TC3_IRQn             = 30, /**< 30 SAM3X8C Timer Counter 3 (TC3) */
+  TC4_IRQn             = 31, /**< 31 SAM3X8C Timer Counter 4 (TC4) */
+  TC5_IRQn             = 32, /**< 32 SAM3X8C Timer Counter 5 (TC5) */
+  PWM_IRQn             = 36, /**< 36 SAM3X8C Pulse Width Modulation Controller (PWM) */
+  ADC_IRQn             = 37, /**< 37 SAM3X8C ADC Controller (ADC) */
+  DACC_IRQn            = 38, /**< 38 SAM3X8C DAC Controller (DACC) */
+  DMAC_IRQn            = 39, /**< 39 SAM3X8C DMA Controller (DMAC) */
+  UOTGHS_IRQn          = 40, /**< 40 SAM3X8C USB OTG High Speed (UOTGHS) */
+  TRNG_IRQn            = 41, /**< 41 SAM3X8C True Random Number Generator (TRNG) */
+  EMAC_IRQn            = 42, /**< 42 SAM3X8C Ethernet MAC (EMAC) */
+  CAN0_IRQn            = 43, /**< 43 SAM3X8C CAN Controller 0 (CAN0) */
+  CAN1_IRQn            = 44  /**< 44 SAM3X8C CAN Controller 1 (CAN1) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3X8C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3X8C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3X8C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_can.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_emac.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_trng.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_uotghs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3X8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi0.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_uotghs.h"
+#include "instance/instance_emac.h"
+#include "instance/instance_can0.h"
+#include "instance/instance_can1.h"
+#include "instance/instance_trng.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3X8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (17) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (18) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (19) /**< \brief USART 2 (USART2) */
+#define ID_HSMCI  (21) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (22) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (23) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI0   (24) /**< \brief Serial Peripheral Interface (SPI0) */
+#define ID_SSC    (26) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (27) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (28) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (29) /**< \brief Timer Counter 2 (TC2) */
+#define ID_TC3    (30) /**< \brief Timer Counter 3 (TC3) */
+#define ID_TC4    (31) /**< \brief Timer Counter 4 (TC4) */
+#define ID_TC5    (32) /**< \brief Timer Counter 5 (TC5) */
+#define ID_PWM    (36) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC    (37) /**< \brief ADC Controller (ADC) */
+#define ID_DACC   (38) /**< \brief DAC Controller (DACC) */
+#define ID_DMAC   (39) /**< \brief DMA Controller (DMAC) */
+#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */
+#define ID_TRNG   (41) /**< \brief True Random Number Generator (TRNG) */
+#define ID_EMAC   (42) /**< \brief Ethernet MAC (EMAC) */
+#define ID_CAN0   (43) /**< \brief CAN Controller 0 (CAN0) */
+#define ID_CAN1   (44) /**< \brief CAN Controller 1 (CAN1) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3X8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       (0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define UOTGHS     (0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define EMAC       (0x400B0000U) /**< \brief (EMAC      ) Base Address */
+#define CAN0       (0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       (0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       (0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        (0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       (0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       ((Spi    *)0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define UOTGHS     ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define EMAC       ((Emac   *)0x400B0000U) /**< \brief (EMAC      ) Base Address */
+#define CAN0       ((Can    *)0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       ((Can    *)0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       ((Trng   *)0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        ((Adc    *)0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       ((Dacc   *)0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3X8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3x8c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3X8C */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x40000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (1024u)
+#define IFLASH1_SIZE             (0x40000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (1024u)
+#define IRAM0_SIZE               (0x10000u)
+#define IRAM1_SIZE               (0x8000u)
+#define IFLASH_SIZE              (0x80000u)
+#define IRAM_SIZE                (0x18000u)
+
+#define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR    (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IROM_ADDR       (0x00100000u) /**< Internal ROM base address */
+#define IRAM0_ADDR      (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR      (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR    (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */
+#define EBI_CS0_ADDR    (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR    (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR    (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR    (0x63000000u) /**< EBI Chip Select 3 base address */
+#define EBI_CS4_ADDR    (0x64000000u) /**< EBI Chip Select 4 base address */
+#define EBI_CS5_ADDR    (0x65000000u) /**< EBI Chip Select 5 base address */
+#define EBI_CS6_ADDR    (0x66000000u) /**< EBI Chip Select 6 base address */
+#define EBI_CS7_ADDR    (0x67000000u) /**< EBI Chip Select 7 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3X8C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (84000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3X8C_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x8e.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x8e.h
new file mode 100644
index 000000000..6d3ba7a5a
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x8e.h
@@ -0,0 +1,441 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3X8E_
+#define _SAM3X8E_
+
+/** \addtogroup SAM3X8E_definitions SAM3X8E definitions
+  This file defines all structures and symbols for SAM3X8E:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3X8E */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8E_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3X8E specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3X8E Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3X8E Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3X8E Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3X8E Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3X8E Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3X8E Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3X8E Enhanced Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3X8E Enhanced Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3X8E Universal Asynchronous Receiver Transceiver (UART) */
+  SMC_IRQn             =  9, /**<  9 SAM3X8E Static Memory Controller (SMC) */
+  PIOA_IRQn            = 11, /**< 11 SAM3X8E Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3X8E Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM3X8E Parallel I/O Controller C (PIOC) */
+  PIOD_IRQn            = 14, /**< 14 SAM3X8E Parallel I/O Controller D (PIOD) */
+  USART0_IRQn          = 17, /**< 17 SAM3X8E USART 0 (USART0) */
+  USART1_IRQn          = 18, /**< 18 SAM3X8E USART 1 (USART1) */
+  USART2_IRQn          = 19, /**< 19 SAM3X8E USART 2 (USART2) */
+  USART3_IRQn          = 20, /**< 20 SAM3X8E USART 3 (USART3) */
+  HSMCI_IRQn           = 21, /**< 21 SAM3X8E Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 22, /**< 22 SAM3X8E Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 23, /**< 23 SAM3X8E Two-Wire Interface 1 (TWI1) */
+  SPI0_IRQn            = 24, /**< 24 SAM3X8E Serial Peripheral Interface (SPI0) */
+  SSC_IRQn             = 26, /**< 26 SAM3X8E Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 27, /**< 27 SAM3X8E Timer Counter 0 (TC0) */
+  TC1_IRQn             = 28, /**< 28 SAM3X8E Timer Counter 1 (TC1) */
+  TC2_IRQn             = 29, /**< 29 SAM3X8E Timer Counter 2 (TC2) */
+  TC3_IRQn             = 30, /**< 30 SAM3X8E Timer Counter 3 (TC3) */
+  TC4_IRQn             = 31, /**< 31 SAM3X8E Timer Counter 4 (TC4) */
+  TC5_IRQn             = 32, /**< 32 SAM3X8E Timer Counter 5 (TC5) */
+  TC6_IRQn             = 33, /**< 33 SAM3X8E Timer Counter 6 (TC6) */
+  TC7_IRQn             = 34, /**< 34 SAM3X8E Timer Counter 7 (TC7) */
+  TC8_IRQn             = 35, /**< 35 SAM3X8E Timer Counter 8 (TC8) */
+  PWM_IRQn             = 36, /**< 36 SAM3X8E Pulse Width Modulation Controller (PWM) */
+  ADC_IRQn             = 37, /**< 37 SAM3X8E ADC Controller (ADC) */
+  DACC_IRQn            = 38, /**< 38 SAM3X8E DAC Controller (DACC) */
+  DMAC_IRQn            = 39, /**< 39 SAM3X8E DMA Controller (DMAC) */
+  UOTGHS_IRQn          = 40, /**< 40 SAM3X8E USB OTG High Speed (UOTGHS) */
+  TRNG_IRQn            = 41, /**< 41 SAM3X8E True Random Number Generator (TRNG) */
+  EMAC_IRQn            = 42, /**< 42 SAM3X8E Ethernet MAC (EMAC) */
+  CAN0_IRQn            = 43, /**< 43 SAM3X8E CAN Controller 0 (CAN0) */
+  CAN1_IRQn            = 44  /**< 44 SAM3X8E CAN Controller 1 (CAN1) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3X8E core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3X8E does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3X8E uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X8E */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8E_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_can.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_emac.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_trng.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_uotghs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3X8E */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8E_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi0.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_tc2.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_usart3.h"
+#include "instance/instance_uotghs.h"
+#include "instance/instance_emac.h"
+#include "instance/instance_can0.h"
+#include "instance/instance_can1.h"
+#include "instance/instance_trng.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_piod.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3X8E */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8E_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */
+#define ID_SMC    ( 9) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_PIOD   (14) /**< \brief Parallel I/O Controller D (PIOD) */
+#define ID_USART0 (17) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (18) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (19) /**< \brief USART 2 (USART2) */
+#define ID_USART3 (20) /**< \brief USART 3 (USART3) */
+#define ID_HSMCI  (21) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (22) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (23) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI0   (24) /**< \brief Serial Peripheral Interface (SPI0) */
+#define ID_SSC    (26) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (27) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (28) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (29) /**< \brief Timer Counter 2 (TC2) */
+#define ID_TC3    (30) /**< \brief Timer Counter 3 (TC3) */
+#define ID_TC4    (31) /**< \brief Timer Counter 4 (TC4) */
+#define ID_TC5    (32) /**< \brief Timer Counter 5 (TC5) */
+#define ID_TC6    (33) /**< \brief Timer Counter 6 (TC6) */
+#define ID_TC7    (34) /**< \brief Timer Counter 7 (TC7) */
+#define ID_TC8    (35) /**< \brief Timer Counter 8 (TC8) */
+#define ID_PWM    (36) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC    (37) /**< \brief ADC Controller (ADC) */
+#define ID_DACC   (38) /**< \brief DAC Controller (DACC) */
+#define ID_DMAC   (39) /**< \brief DMA Controller (DMAC) */
+#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */
+#define ID_TRNG   (41) /**< \brief True Random Number Generator (TRNG) */
+#define ID_EMAC   (42) /**< \brief Ethernet MAC (EMAC) */
+#define ID_CAN0   (43) /**< \brief CAN Controller 0 (CAN0) */
+#define ID_CAN1   (44) /**< \brief CAN Controller 1 (CAN1) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3X8E */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8E_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       (0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TC2        (0x40088000U) /**< \brief (TC2       ) Base Address */
+#define TWI0       (0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define USART3     (0x400A4000U) /**< \brief (USART3    ) Base Address */
+#define PDC_USART3 (0x400A4100U) /**< \brief (PDC_USART3) Base Address */
+#define UOTGHS     (0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define EMAC       (0x400B0000U) /**< \brief (EMAC      ) Base Address */
+#define CAN0       (0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       (0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       (0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        (0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       (0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define PIOD       (0x400E1400U) /**< \brief (PIOD      ) Base Address */
+#define RSTC       (0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       ((Spi    *)0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TC2        ((Tc     *)0x40088000U) /**< \brief (TC2       ) Base Address */
+#define TWI0       ((Twi    *)0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define USART3     ((Usart  *)0x400A4000U) /**< \brief (USART3    ) Base Address */
+#define PDC_USART3 ((Pdc    *)0x400A4100U) /**< \brief (PDC_USART3) Base Address */
+#define UOTGHS     ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define EMAC       ((Emac   *)0x400B0000U) /**< \brief (EMAC      ) Base Address */
+#define CAN0       ((Can    *)0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       ((Can    *)0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       ((Trng   *)0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        ((Adc    *)0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       ((Dacc   *)0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define PIOD       ((Pio    *)0x400E1400U) /**< \brief (PIOD      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3X8E */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8E_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3x8e.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3X8E */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x40000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (1024u)
+#define IFLASH1_SIZE             (0x40000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (1024u)
+#define IRAM0_SIZE               (0x10000u)
+#define IRAM1_SIZE               (0x8000u)
+#define NFCRAM_SIZE              (0x1000u)
+#define IFLASH_SIZE              (0x80000u)
+#define IRAM_SIZE                (0x18000u)
+
+#define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR    (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IROM_ADDR       (0x00100000u) /**< Internal ROM base address */
+#define IRAM0_ADDR      (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR      (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR    (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */
+#define EBI_CS0_ADDR    (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR    (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR    (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR    (0x63000000u) /**< EBI Chip Select 3 base address */
+#define EBI_CS4_ADDR    (0x64000000u) /**< EBI Chip Select 4 base address */
+#define EBI_CS5_ADDR    (0x65000000u) /**< EBI Chip Select 5 base address */
+#define EBI_CS6_ADDR    (0x66000000u) /**< EBI Chip Select 6 base address */
+#define EBI_CS7_ADDR    (0x67000000u) /**< EBI Chip Select 7 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3X8E */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (84000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3X8E_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x8h.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x8h.h
new file mode 100644
index 000000000..1ca0d9d08
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3x8h.h
@@ -0,0 +1,462 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3X8H_
+#define _SAM3X8H_
+
+/** \addtogroup SAM3X8H_definitions SAM3X8H definitions
+  This file defines all structures and symbols for SAM3X8H:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __ASSEMBLY__
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3X8H */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8H_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3X8H specific Interrupt Numbers *********************************/
+  
+  SUPC_IRQn            =  0, /**<  0 SAM3X8H Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3X8H Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3X8H Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3X8H Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3X8H Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3X8H Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3X8H Enhanced Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3X8H Enhanced Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3X8H Universal Asynchronous Receiver Transceiver (UART) */
+  SMC_IRQn             =  9, /**<  9 SAM3X8H Static Memory Controller (SMC) */
+  SDRAMC_IRQn          = 10, /**< 10 SAM3X8H Synchronous Dynamic RAM Controller (SDRAMC) */
+  PIOA_IRQn            = 11, /**< 11 SAM3X8H Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3X8H Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM3X8H Parallel I/O Controller C (PIOC) */
+  PIOD_IRQn            = 14, /**< 14 SAM3X8H Parallel I/O Controller D (PIOD) */
+  PIOE_IRQn            = 15, /**< 15 SAM3X8H Parallel I/O Controller E (PIOE) */
+  PIOF_IRQn            = 16, /**< 16 SAM3X8H Parallel I/O Controller F (PIOF) */
+  USART0_IRQn          = 17, /**< 17 SAM3X8H USART 0 (USART0) */
+  USART1_IRQn          = 18, /**< 18 SAM3X8H USART 1 (USART1) */
+  USART2_IRQn          = 19, /**< 19 SAM3X8H USART 2 (USART2) */
+  USART3_IRQn          = 20, /**< 20 SAM3X8H USART 3 (USART3) */
+  HSMCI_IRQn           = 21, /**< 21 SAM3X8H Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 22, /**< 22 SAM3X8H Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 23, /**< 23 SAM3X8H Two-Wire Interface 1 (TWI1) */
+  SPI0_IRQn            = 24, /**< 24 SAM3X8H Serial Peripheral Interface (SPI0) */
+  SPI1_IRQn            = 25, /**< 25 SAM3X8H Serial Peripheral Interface (SPI1) */
+  SSC_IRQn             = 26, /**< 26 SAM3X8H Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 27, /**< 27 SAM3X8H Timer Counter 0 (TC0) */
+  TC1_IRQn             = 28, /**< 28 SAM3X8H Timer Counter 1 (TC1) */
+  TC2_IRQn             = 29, /**< 29 SAM3X8H Timer Counter 2 (TC2) */
+  TC3_IRQn             = 30, /**< 30 SAM3X8H Timer Counter 3 (TC3) */
+  TC4_IRQn             = 31, /**< 31 SAM3X8H Timer Counter 4 (TC4) */
+  TC5_IRQn             = 32, /**< 32 SAM3X8H Timer Counter 5 (TC5) */
+  TC6_IRQn             = 33, /**< 33 SAM3X8H Timer Counter 6 (TC6) */
+  TC7_IRQn             = 34, /**< 34 SAM3X8H Timer Counter 7 (TC7) */
+  TC8_IRQn             = 35, /**< 35 SAM3X8H Timer Counter 8 (TC8) */
+  PWM_IRQn             = 36, /**< 36 SAM3X8H Pulse Width Modulation Controller (PWM) */
+  ADC_IRQn             = 37, /**< 37 SAM3X8H ADC Controller (ADC) */
+  DACC_IRQn            = 38, /**< 38 SAM3X8H DAC Controller (DACC) */
+  DMAC_IRQn            = 39, /**< 39 SAM3X8H DMA Controller (DMAC) */
+  UOTGHS_IRQn          = 40, /**< 40 SAM3X8H USB OTG High Speed (UOTGHS) */
+  TRNG_IRQn            = 41, /**< 41 SAM3X8H True Random Number Generator (TRNG) */
+  EMAC_IRQn            = 42, /**< 42 SAM3X8H Ethernet MAC (EMAC) */
+  CAN0_IRQn            = 43, /**< 43 SAM3X8H CAN Controller 0 (CAN0) */
+  CAN1_IRQn            = 44  /**< 44 SAM3X8H CAN Controller 1 (CAN1) */
+} IRQn_Type;
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3X8H core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3X8H does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3X8H uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X8H */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8H_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_can.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_emac.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_sdramc.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_trng.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_uotghs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3X8H */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8H_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi0.h"
+#include "instance/instance_spi1.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_tc2.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_usart3.h"
+#include "instance/instance_uotghs.h"
+#include "instance/instance_emac.h"
+#include "instance/instance_can0.h"
+#include "instance/instance_can1.h"
+#include "instance/instance_trng.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_sdramc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_piod.h"
+#include "instance/instance_pioe.h"
+#include "instance/instance_piof.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3X8H */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8H_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */
+#define ID_SMC    ( 9) /**< \brief Static Memory Controller (SMC) */
+#define ID_SDRAMC (10) /**< \brief Synchronous Dynamic RAM Controller (SDRAMC) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_PIOD   (14) /**< \brief Parallel I/O Controller D (PIOD) */
+#define ID_PIOE   (15) /**< \brief Parallel I/O Controller E (PIOE) */
+#define ID_PIOF   (16) /**< \brief Parallel I/O Controller F (PIOF) */
+#define ID_USART0 (17) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (18) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (19) /**< \brief USART 2 (USART2) */
+#define ID_USART3 (20) /**< \brief USART 3 (USART3) */
+#define ID_HSMCI  (21) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (22) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (23) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI0   (24) /**< \brief Serial Peripheral Interface (SPI0) */
+#define ID_SPI1   (25) /**< \brief Serial Peripheral Interface (SPI1) */
+#define ID_SSC    (26) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (27) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (28) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (29) /**< \brief Timer Counter 2 (TC2) */
+#define ID_TC3    (30) /**< \brief Timer Counter 3 (TC3) */
+#define ID_TC4    (31) /**< \brief Timer Counter 4 (TC4) */
+#define ID_TC5    (32) /**< \brief Timer Counter 5 (TC5) */
+#define ID_TC6    (33) /**< \brief Timer Counter 6 (TC6) */
+#define ID_TC7    (34) /**< \brief Timer Counter 7 (TC7) */
+#define ID_TC8    (35) /**< \brief Timer Counter 8 (TC8) */
+#define ID_PWM    (36) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC    (37) /**< \brief ADC Controller (ADC) */
+#define ID_DACC   (38) /**< \brief DAC Controller (DACC) */
+#define ID_DMAC   (39) /**< \brief DMA Controller (DMAC) */
+#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */
+#define ID_TRNG   (41) /**< \brief True Random Number Generator (TRNG) */
+#define ID_EMAC   (42) /**< \brief Ethernet MAC (EMAC) */
+#define ID_CAN0   (43) /**< \brief CAN Controller 0 (CAN0) */
+#define ID_CAN1   (44) /**< \brief CAN Controller 1 (CAN1) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3X8H */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8H_base Peripheral Base Address Definitions */
+/*@{*/
+
+#ifdef __ASSEMBLY__
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       (0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define SPI1       (0x4000C000U) /**< \brief (SPI1      ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TC2        (0x40088000U) /**< \brief (TC2       ) Base Address */
+#define TWI0       (0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define USART3     (0x400A4000U) /**< \brief (USART3    ) Base Address */
+#define PDC_USART3 (0x400A4100U) /**< \brief (PDC_USART3) Base Address */
+#define UOTGHS     (0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define EMAC       (0x400B0000U) /**< \brief (EMAC      ) Base Address */
+#define CAN0       (0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       (0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       (0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        (0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       (0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define SDRAMC     (0x400E0200U) /**< \brief (SDRAMC    ) Base Address */
+#define MATRIX     (0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define PIOD       (0x400E1400U) /**< \brief (PIOD      ) Base Address */
+#define PIOE       (0x400E1600U) /**< \brief (PIOE      ) Base Address */
+#define PIOF       (0x400E1800U) /**< \brief (PIOF      ) Base Address */
+#define RSTC       (0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       ((Spi    *)0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define SPI1       ((Spi    *)0x4000C000U) /**< \brief (SPI1      ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TC2        ((Tc     *)0x40088000U) /**< \brief (TC2       ) Base Address */
+#define TWI0       ((Twi    *)0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define USART3     ((Usart  *)0x400A4000U) /**< \brief (USART3    ) Base Address */
+#define PDC_USART3 ((Pdc    *)0x400A4100U) /**< \brief (PDC_USART3) Base Address */
+#define UOTGHS     ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define EMAC       ((Emac   *)0x400B0000U) /**< \brief (EMAC      ) Base Address */
+#define CAN0       ((Can    *)0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       ((Can    *)0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       ((Trng   *)0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        ((Adc    *)0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       ((Dacc   *)0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define SDRAMC     ((Sdramc *)0x400E0200U) /**< \brief (SDRAMC    ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define PIOD       ((Pio    *)0x400E1400U) /**< \brief (PIOD      ) Base Address */
+#define PIOE       ((Pio    *)0x400E1600U) /**< \brief (PIOE      ) Base Address */
+#define PIOF       ((Pio    *)0x400E1800U) /**< \brief (PIOF      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#endif /* __ASSEMBLY__ */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3X8H */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8H_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3x8h.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3X8H */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x40000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (1024u)
+#define IFLASH1_SIZE             (0x40000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (1024u)
+#define IRAM0_SIZE               (0x10000u)
+#define IRAM1_SIZE               (0x8000u)
+#define NFCRAM_SIZE              (0x1000u)
+#define IFLASH_SIZE              (0x80000u)
+#define IRAM_SIZE                (0x18000u)
+
+#define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR    (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IROM_ADDR       (0x00100000u) /**< Internal ROM base address */
+#define IRAM0_ADDR      (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR      (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR    (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */
+#define EBI_CS0_ADDR    (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR    (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR    (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR    (0x63000000u) /**< EBI Chip Select 3 base address */
+#define EBI_CS4_ADDR    (0x64000000u) /**< EBI Chip Select 4 base address */
+#define EBI_CS5_ADDR    (0x65000000u) /**< EBI Chip Select 5 base address */
+#define EBI_CS6_ADDR    (0x66000000u) /**< EBI Chip Select 6 base address */
+#define EBI_CS7_ADDR    (0x67000000u) /**< EBI Chip Select 7 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3X8H */
+/* ************************************************************************** */
+
+/* Device characteristics */
+
+#define CHIP_FREQ_SLCK_RC_MIN               (20000U)
+#define CHIP_FREQ_SLCK_RC                   (32000U)
+#define CHIP_FREQ_SLCK_RC_MAX               (44000U)
+#define CHIP_FREQ_MAINCK_RC_4MHZ            (4000000U)
+#define CHIP_FREQ_MAINCK_RC_8MHZ            (8000000U)
+#define CHIP_FREQ_MAINCK_RC_12MHZ           (12000000U)
+#define CHIP_FREQ_CPU_MAX                   (84000000U)
+#define CHIP_FLASH_WAIT_STATE               (3U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3X8H_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3xa.h b/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3xa.h
new file mode 100644
index 000000000..73e9ad699
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/include/sam3xa.h
@@ -0,0 +1,53 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_
+#define _SAM3XA_
+
+#if defined __SAM3A2C__
+  #include "sam3a2c.h"
+#elif defined __SAM3A4C__
+  #include "sam3a4c.h"
+#elif defined __SAM3A8C__
+  #include "sam3a8c.h"
+#elif defined __SAM3X4C__
+  #include "sam3x4c.h"
+#elif defined __SAM3X4E__
+  #include "sam3x4e.h"
+#elif defined __SAM3X8C__
+  #include "sam3x8c.h"
+#elif defined __SAM3X8E__
+  #include "sam3x8e.h"
+#elif defined __SAM3X8H__
+  #include "sam3x8h.h"
+#else
+  #error Library does not support the specified device.
+#endif
+
+#endif /* _SAM3XA_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/source/templates/exceptions.c b/hardware/sam/system/libsam/cmsis/sam3xa/source/templates/exceptions.c
new file mode 100644
index 000000000..7206fd681
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/source/templates/exceptions.c
@@ -0,0 +1,173 @@
+/*! \file *********************************************************************
+ *
+ * \brief This file contains the default exception handlers.
+ *
+ * $asf_license$
+ *
+ * \par Purpose
+ *
+ * This file provides basic support for Cortex-M processor based 
+ * microcontrollers.
+ *
+ * \note
+ * The exception handler has weak aliases.
+ * As they are weak aliases, any function with the same name will override
+ * this definition.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+#include "exceptions.h"
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#ifdef __GNUC__
+/* Cortex-M3 core handlers */
+//void Reset_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void NMI_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+//void HardFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void ACC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void ADC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void CAN0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void CAN1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void CRCCU_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void DACC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void DMAC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void EMAC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void HSMCI_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOA_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOD_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOE_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOF_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PWM_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SDRAMC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SMC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SSC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SUPC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC6_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC7_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC8_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TRNG_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void UOTGHS_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART2_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART3_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* __GNUC__ */
+
+#ifdef __ICCARM__
+/* Cortex-M3 core handlers */
+//#pragma weak Reset_Handler=Dummy_Handler
+#pragma weak NMI_Handler=Dummy_Handler
+//#pragma weak HardFault_Handler=Dummy_Handler
+#pragma weak MemManage_Handler=Dummy_Handler
+#pragma weak BusFault_Handler=Dummy_Handler
+#pragma weak UsageFault_Handler=Dummy_Handler
+#pragma weak SVC_Handler=Dummy_Handler
+#pragma weak DebugMon_Handler=Dummy_Handler
+#pragma weak PendSV_Handler=Dummy_Handler
+#pragma weak SysTick_Handler=Dummy_Handler
+
+/* Peripherals handlers */
+#pragma weak ACC_IrqHandler=Dummy_Handler
+#pragma weak ADC_IrqHandler=Dummy_Handler
+#pragma weak CAN0_IrqHandler=Dummy_Handler
+#pragma weak CAN1_IrqHandler=Dummy_Handler
+#pragma weak CRCCU_IrqHandler=Dummy_Handler
+#pragma weak DACC_IrqHandler=Dummy_Handler
+#pragma weak DMAC_IrqHandler=Dummy_Handler
+#pragma weak EFC0_IrqHandler=Dummy_Handler
+#pragma weak EFC1_IrqHandler=Dummy_Handler
+#pragma weak EMAC_IrqHandler=Dummy_Handler
+#pragma weak HSMCI_IrqHandler=Dummy_Handler
+#pragma weak PIOA_IrqHandler=Dummy_Handler
+#pragma weak PIOB_IrqHandler=Dummy_Handler
+#pragma weak PIOC_IrqHandler=Dummy_Handler
+#pragma weak PIOD_IrqHandler=Dummy_Handler
+#pragma weak PIOE_IrqHandler=Dummy_Handler
+#pragma weak PIOF_IrqHandler=Dummy_Handler
+#pragma weak PMC_IrqHandler=Dummy_Handler
+#pragma weak PWM_IrqHandler=Dummy_Handler
+#pragma weak RSTC_IrqHandler=Dummy_Handler
+#pragma weak RTC_IrqHandler=Dummy_Handler
+#pragma weak RTT_IrqHandler=Dummy_Handler
+#pragma weak SDRAMC_IrqHandler=Dummy_Handler
+#pragma weak SMC_IrqHandler=Dummy_Handler
+#pragma weak SPI0_IrqHandler=Dummy_Handler
+#pragma weak SPI1_IrqHandler=Dummy_Handler
+#pragma weak SSC_IrqHandler=Dummy_Handler
+#pragma weak SUPC_IrqHandler=Dummy_Handler
+#pragma weak TC0_IrqHandler=Dummy_Handler
+#pragma weak TC1_IrqHandler=Dummy_Handler
+#pragma weak TC2_IrqHandler=Dummy_Handler
+#pragma weak TC3_IrqHandler=Dummy_Handler
+#pragma weak TC4_IrqHandler=Dummy_Handler
+#pragma weak TC5_IrqHandler=Dummy_Handler
+#pragma weak TC6_IrqHandler=Dummy_Handler
+#pragma weak TC7_IrqHandler=Dummy_Handler
+#pragma weak TC8_IrqHandler=Dummy_Handler
+#pragma weak TRNG_IrqHandler=Dummy_Handler
+#pragma weak TWI0_IrqHandler=Dummy_Handler
+#pragma weak TWI1_IrqHandler=Dummy_Handler
+#pragma weak UART_IrqHandler=Dummy_Handler
+#pragma weak UOTGHS_IrqHandler=Dummy_Handler
+#pragma weak USART0_IrqHandler=Dummy_Handler
+#pragma weak USART1_IrqHandler=Dummy_Handler
+#pragma weak USART2_IrqHandler=Dummy_Handler
+#pragma weak USART3_IrqHandler=Dummy_Handler
+#pragma weak WDT_IrqHandler=Dummy_Handler
+#endif /* __ICCARM__ */
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/source/templates/exceptions.h b/hardware/sam/system/libsam/cmsis/sam3xa/source/templates/exceptions.h
new file mode 100644
index 000000000..1c235b249
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/source/templates/exceptions.h
@@ -0,0 +1,103 @@
+/*! \file *********************************************************************
+ *
+ * \brief This file contains the interface for default exception handlers.
+ *
+ * $asf_license$
+ *
+ * \par Purpose
+ *
+ * This file provides basic support for Cortex-M processor based 
+ * microcontrollers.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+#ifndef EXCEPTIONS_H_INCLUDED
+#define EXCEPTIONS_H_INCLUDED
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+/* Function prototype for exception table items (interrupt handler). */
+typedef void (*IntFunc) (void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+void Reset_Handler(void);
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+
+/* Peripherals handlers */
+void ACC_IrqHandler(void);
+void ADC_IrqHandler(void);
+void CAN0_IrqHandler(void);
+void CAN1_IrqHandler(void);
+void CRCCU_IrqHandler(void);
+void DACC_IrqHandler(void);
+void DMAC_IrqHandler(void);
+void EFC0_IrqHandler(void);
+void EFC1_IrqHandler(void);
+void EMAC_IrqHandler(void);
+void HSMCI_IrqHandler(void);
+void PIOA_IrqHandler(void);
+void PIOB_IrqHandler(void);
+void PIOC_IrqHandler(void);
+void PIOD_IrqHandler(void);
+void PIOE_IrqHandler(void);
+void PIOF_IrqHandler(void);
+void PMC_IrqHandler(void);
+void PWM_IrqHandler(void);
+void RSTC_IrqHandler(void);
+void RTC_IrqHandler(void);
+void RTT_IrqHandler(void);
+void SDRAMC_IrqHandler(void);
+void SMC_IrqHandler(void);
+void SPI0_IrqHandler(void);
+void SPI1_IrqHandler(void);
+void SSC_IrqHandler(void);
+void SUPC_IrqHandler(void);
+void TC0_IrqHandler(void);
+void TC1_IrqHandler(void);
+void TC2_IrqHandler(void);
+void TC3_IrqHandler(void);
+void TC4_IrqHandler(void);
+void TC5_IrqHandler(void);
+void TC6_IrqHandler(void);
+void TC7_IrqHandler(void);
+void TC8_IrqHandler(void);
+void TRNG_IrqHandler(void);
+void TWI0_IrqHandler(void);
+void TWI1_IrqHandler(void);
+void UART_IrqHandler(void);
+void UOTGHS_IrqHandler(void);
+void USART0_IrqHandler(void);
+void USART1_IrqHandler(void);
+void USART2_IrqHandler(void);
+void USART3_IrqHandler(void);
+void WDT_IrqHandler(void);
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#endif /* EXCEPTIONS_H_INCLUDED */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/source/templates/gcc/startup_sam3x.c b/hardware/sam/system/libsam/cmsis/sam3xa/source/templates/gcc/startup_sam3x.c
new file mode 100644
index 000000000..3afa1c96c
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/source/templates/gcc/startup_sam3x.c
@@ -0,0 +1,146 @@
+/*! \file *********************************************************************
+ *
+ * \brief Startup file for SAM3X.
+ *
+ * $asf_license$
+ *
+ * This file defines common SAM series.
+ *
+ * - Compiler:           ARMGCC
+ * - Supported devices:  All SAM3X devices can be used.
+ * - AppNote:
+ *
+ ******************************************************************************/
+
+#include "../exceptions.h"
+#include "sam3.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+IntFunc exception_table[] = {
+
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(IntFunc) (&_estack),
+	Reset_Handler,
+
+	NMI_Handler,
+	HardFault_Handler,
+	MemManage_Handler,
+	BusFault_Handler,
+	UsageFault_Handler,
+	0, 0, 0, 0,         /*  Reserved */
+	SVC_Handler,
+	DebugMon_Handler,
+	0,                  /*  Reserved */
+	PendSV_Handler,
+	SysTick_Handler,
+
+	/* Configurable interrupts */
+	SUPC_IrqHandler,    /*  0  Supply Controller */
+	RSTC_IrqHandler,    /*  1  Reset Controller */
+	RTC_IrqHandler,     /*  2  Real Time Clock */
+	RTT_IrqHandler,     /*  3  Real Time Timer */
+	WDT_IrqHandler,     /*  4  Watchdog Timer */
+	PMC_IrqHandler,     /*  5  PMC */
+	EFC0_IrqHandler,    /*  6  EFC 0 */
+	EFC1_IrqHandler,    /*  7  EFC 1 */
+	UART_IrqHandler,    /*  8  UART */
+	SMC_IrqHandler,     /*  9  SMC */
+	SDRAMC_IrqHandler,  /* 10  SDRAMC */
+	PIOA_IrqHandler,    /* 11 Parallel IO Controller A */
+	PIOB_IrqHandler,    /* 12 Parallel IO Controller B */
+	PIOC_IrqHandler,    /* 13 Parallel IO Controller C */
+	PIOD_IrqHandler,    /* 14 Parallel IO Controller D */
+	PIOE_IrqHandler,    /* 15 Parallel IO Controller E */
+	PIOF_IrqHandler,    /* 16 Parallel IO Controller F */
+	USART0_IrqHandler,  /* 17 USART 0 */
+	USART1_IrqHandler,  /* 18 USART 1 */
+	USART2_IrqHandler,  /* 19 USART 2 */
+	USART3_IrqHandler,  /* 20 USART 3 */
+	HSMCI_IrqHandler,   /* 21 MCI */
+	TWI0_IrqHandler,    /* 22 TWI 0 */
+	TWI1_IrqHandler,    /* 23 TWI 1 */
+	SPI0_IrqHandler,    /* 24 SPI 0 */
+	SPI1_IrqHandler,    /* 25 SPI 1 */
+	SSC_IrqHandler,     /* 26 SSC */
+	TC0_IrqHandler,     /* 27 Timer Counter 0 */
+	TC1_IrqHandler,     /* 28 Timer Counter 1 */
+	TC2_IrqHandler,     /* 29 Timer Counter 2 */
+	TC3_IrqHandler,     /* 30 Timer Counter 3 */
+	TC4_IrqHandler,     /* 31 Timer Counter 4 */
+	TC5_IrqHandler,     /* 32 Timer Counter 5 */
+	TC6_IrqHandler,     /* 33 Timer Counter 6 */
+	TC7_IrqHandler,     /* 34 Timer Counter 7 */
+	TC8_IrqHandler,     /* 35 Timer Counter 8 */
+	PWM_IrqHandler,     /* 36 PWM */
+	ADC_IrqHandler,     /* 37 ADC controller */
+	DACC_IrqHandler,    /* 38 DAC controller */
+	DMAC_IrqHandler,    /* 39 DMA Controller */
+	UOTGHS_IrqHandler,  /* 40 USB OTG High Speed */
+	TRNG_IrqHandler,    /* 41 True Random Number Generator */
+	EMAC_IrqHandler,    /* 42 Ethernet MAC */
+	CAN0_IrqHandler,    /* 43 CAN Controller 0 */
+	CAN1_IrqHandler,    /* 44 CAN Controller 1 */
+};
+
+/* TEMPORARY PATCH FOR SCB */
+#define SCB_VTOR_TBLBASE_Pos               29                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM0_ADDR) && ((uint32_t) pSrc < NFC_RAM_ADDR)) {
+		SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/source/templates/iar/startup_sam3x.c b/hardware/sam/system/libsam/cmsis/sam3xa/source/templates/iar/startup_sam3x.c
new file mode 100644
index 000000000..c72851736
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/source/templates/iar/startup_sam3x.c
@@ -0,0 +1,122 @@
+/*! \file *********************************************************************
+ *
+ * \brief Startup file for SAM3X.
+ *
+ * $asf_license$
+ *
+ * This file defines common SAM series.
+ *
+ * - Compiler:           IAR EWARM
+ * - Supported devices:  All SAM3X devices can be used.
+ * - AppNote:
+ *
+ ******************************************************************************/
+
+#include "../exceptions.h"
+#include "sam3.h"
+
+typedef void (*intfunc) (void);
+typedef union { intfunc __fun; void * __ptr; } intvec_elem;
+
+void __iar_program_start(void);
+int __low_level_init(void);
+
+/* Exception Table */
+#pragma language=extended
+#pragma segment="CSTACK"
+
+/* The name "__vector_table" has special meaning for C-SPY: */
+/* it is where the SP start value is found, and the NVIC vector */
+/* table register (VTOR) is initialized to this address if != 0 */
+
+#pragma section = ".intvec"
+#pragma location = ".intvec"
+const intvec_elem __vector_table[] = {
+	{.__ptr = __sfe("CSTACK")},
+	Reset_Handler,
+
+	NMI_Handler,
+	HardFault_Handler,
+	MemManage_Handler,
+	BusFault_Handler,
+	UsageFault_Handler,
+	0, 0, 0, 0,         /*  Reserved */
+	SVC_Handler,
+	DebugMon_Handler,
+	0,                  /*  Reserved */
+	PendSV_Handler,
+	SysTick_Handler,
+
+	/* Configurable interrupts */
+	SUPC_IrqHandler,    /*  0  Supply Controller */
+	RSTC_IrqHandler,    /*  1  Reset Controller */
+	RTC_IrqHandler,     /*  2  Real Time Clock */
+	RTT_IrqHandler,     /*  3  Real Time Timer */
+	WDT_IrqHandler,     /*  4  Watchdog Timer */
+	PMC_IrqHandler,     /*  5  PMC */
+	EFC0_IrqHandler,    /*  6  EFC 0 */
+	EFC1_IrqHandler,    /*  7  EFC 1 */
+	UART_IrqHandler,    /*  8  UART */
+	SMC_IrqHandler,     /*  9  SMC */
+	SDRAMC_IrqHandler,  /* 10  SDRAMC */
+	PIOA_IrqHandler,    /* 11 Parallel IO Controller A */
+	PIOB_IrqHandler,    /* 12 Parallel IO Controller B */
+	PIOC_IrqHandler,    /* 13 Parallel IO Controller C */
+	PIOD_IrqHandler,    /* 14 Parallel IO Controller D */
+	PIOE_IrqHandler,    /* 15 Parallel IO Controller E */
+	PIOF_IrqHandler,    /* 16 Parallel IO Controller F */
+	USART0_IrqHandler,  /* 17 USART 0 */
+	USART1_IrqHandler,  /* 18 USART 1 */
+	USART2_IrqHandler,  /* 19 USART 2 */
+	USART3_IrqHandler,  /* 20 USART 3 */
+	HSMCI_IrqHandler,   /* 21 MCI */
+	TWI0_IrqHandler,    /* 22 TWI 0 */
+	TWI1_IrqHandler,    /* 23 TWI 1 */
+	SPI0_IrqHandler,    /* 24 SPI 0 */
+	SPI1_IrqHandler,    /* 25 SPI 1 */
+	SSC_IrqHandler,     /* 26 SSC */
+	TC0_IrqHandler,     /* 27 Timer Counter 0 */
+	TC1_IrqHandler,     /* 28 Timer Counter 1 */
+	TC2_IrqHandler,     /* 29 Timer Counter 2 */
+	TC3_IrqHandler,     /* 30 Timer Counter 3 */
+	TC4_IrqHandler,     /* 31 Timer Counter 4 */
+	TC5_IrqHandler,     /* 32 Timer Counter 5 */
+	TC6_IrqHandler,     /* 33 Timer Counter 6 */
+	TC7_IrqHandler,     /* 34 Timer Counter 7 */
+	TC8_IrqHandler,     /* 35 Timer Counter 8 */
+	PWM_IrqHandler,     /* 36 PWM */
+	ADC_IrqHandler,     /* 37 ADC controller */
+	DACC_IrqHandler,    /* 38 DAC controller */
+	DMAC_IrqHandler,    /* 39 DMA Controller */
+	UOTGHS_IrqHandler,  /* 40 USB OTG High Speed */
+	TRNG_IrqHandler,    /* 41 True Random Number Generator */
+	EMAC_IrqHandler,    /* 42 Ethernet MAC */
+	CAN0_IrqHandler,    /* 43 CAN Controller 0 */
+	CAN1_IrqHandler,    /* 44 CAN Controller 1 */
+};
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+int __low_level_init(void)
+{
+	uint32_t *pSrc = __section_begin(".intvec");
+
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM0_ADDR) && ((uint32_t) pSrc < NFC_RAM_ADDR)) {
+		SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	return 1; /* if return 0, the data sections will not be initialized */
+}
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+	__iar_program_start();
+}
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/source/templates/system_sam3x.c b/hardware/sam/system/libsam/cmsis/sam3xa/source/templates/system_sam3x.c
new file mode 100644
index 000000000..27186e512
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/source/templates/system_sam3x.c
@@ -0,0 +1,204 @@
+/*! \file *********************************************************************
+ *
+ * \brief Provides the low-level initialization functions that called 
+ * on chip startup.
+ *
+ * $asf_license$
+ *
+ * \par Purpose
+ *
+ * This file provides basic support for Cortex-M processor based 
+ * microcontrollers.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+#include "system_sam3x.h"
+#include "sam3xa.h"
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+/* Clock settings (84MHz) */
+#define SYS_BOARD_OSCOUNT   (CKGR_MOR_MOSCXTST(0x8))
+#define SYS_BOARD_PLLAR     (CKGR_PLLAR_ONE \
+							| CKGR_PLLAR_MULA(0x6) \
+							| CKGR_PLLAR_PLLACOUNT(0x3f) \
+							| CKGR_PLLAR_DIVA(0x1))
+#define SYS_BOARD_MCKR      (PMC_MCKR_PRES_CLK_1 | PMC_MCKR_CSS_PLLA_CLK)
+
+/* Clock Definitions */
+#define SYS_FREQ_XTAL_32K      	(32768UL)		/* External 32K crystal frequency */
+#define SYS_FREQ_XTAL_XTAL12M	(12000000UL)	/* External 12M crystal frequency */
+#define SYS_UTMIPLL     		(480000000UL)	/* UTMI PLL frequency */
+
+#define SYS_FREQ_FWS_0	(22500000UL)	/* Maximum operating frequency when FWS is 0 */
+#define SYS_FREQ_FWS_1	(34000000UL)	/* Maximum operating frequency when FWS is 1 */
+#define SYS_FREQ_FWS_2	(53000000UL)	/* Maximum operating frequency when FWS is 2 */
+#define SYS_FREQ_FWS_3	(78000000UL)	/* Maximum operating frequency when FWS is 3 */
+
+#define SYS_CKGR_MOR_KEY_VALUE	CKGR_MOR_KEY(0x37) /* Key to unlock MOR register */
+
+/* FIXME: should be generated by sock */
+uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+/**
+ * \brief Setup the microcontroller system.
+ * Initialize the System and update the SystemFrequency variable.
+ */
+void SystemInit(void)
+{
+	/* Set 3 FWS for Embedded Flash Access */
+	EFC0->EEFC_FMR = EEFC_FMR_FWS(CHIP_FLASH_WAIT_STATE);
+	EFC1->EEFC_FMR = EEFC_FMR_FWS(CHIP_FLASH_WAIT_STATE);
+
+	/* Initialize main oscillator */
+	if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {
+		PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | 
+			                     CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
+		while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
+		}
+	}
+
+	/* Switch to 3-20MHz Xtal oscillator */
+	PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | 
+	                           CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
+
+	while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
+	}
+ 	PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | 
+		                     PMC_MCKR_CSS_MAIN_CLK;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	/* Initialize PLLA */
+	PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
+	while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
+	}
+
+	/* Switch to main clock */
+	PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	/* Switch to PLLA */
+	PMC->PMC_MCKR = SYS_BOARD_MCKR;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	SystemCoreClock = CHIP_FREQ_CPU_MAX;
+}
+
+void SystemCoreClockUpdate(void)
+{
+	/* Determine clock frequency according to clock register values */
+	switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {
+	case PMC_MCKR_CSS_SLOW_CLK:	/* Slow clock */
+		if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
+			SystemCoreClock = SYS_FREQ_XTAL_32K;
+		} else {
+			SystemCoreClock = CHIP_FREQ_SLCK_RC;
+		}
+		break;
+	case PMC_MCKR_CSS_MAIN_CLK:	/* Main clock */
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
+			SystemCoreClock = SYS_FREQ_XTAL_XTAL12M;
+		} else {
+			SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+			switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
+			case CKGR_MOR_MOSCRCF_4_MHz:
+				break;
+			case CKGR_MOR_MOSCRCF_8_MHz:
+				SystemCoreClock *= 2U;
+				break;
+			case CKGR_MOR_MOSCRCF_12_MHz:
+				SystemCoreClock *= 3U;
+				break;
+			default:
+				break;
+			}
+		}
+		break;
+	case PMC_MCKR_CSS_PLLA_CLK:	/* PLLA clock */
+	case PMC_MCKR_CSS_UPLL_CLK:	/* UPLL clock */
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
+			SystemCoreClock = SYS_FREQ_XTAL_XTAL12M;
+		} else {
+			SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+			switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
+			case CKGR_MOR_MOSCRCF_4_MHz:
+				break;
+			case CKGR_MOR_MOSCRCF_8_MHz:
+				SystemCoreClock *= 2U;
+				break;
+			case CKGR_MOR_MOSCRCF_12_MHz:
+				SystemCoreClock *= 3U;
+				break;
+			default:
+				break;
+			}
+		}
+		if ((PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {
+			SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> 
+				                            CKGR_PLLAR_MULA_Pos) + 1U);
+			SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >> 
+				                             CKGR_PLLAR_DIVA_Pos));
+		} else {
+			SystemCoreClock = SYS_UTMIPLL / 2U;
+		}
+		break;
+	}
+
+	if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
+		SystemCoreClock /= 3U;
+	} else {
+		SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> 
+			                          PMC_MCKR_PRES_Pos);
+	}
+}
+
+/** 
+ * Initialize flash and watchdog.
+ */
+void system_init_flash_and_watchdog(uint32_t dw_clk)
+{
+	/* Set FWS for embedded Flash access according to operating frequency */
+	if (dw_clk < SYS_FREQ_FWS_0) {
+		EFC0->EEFC_FMR = EEFC_FMR_FWS(0);
+		EFC1->EEFC_FMR = EEFC_FMR_FWS(0);
+	} else if (dw_clk < SYS_FREQ_FWS_1) {
+		EFC0->EEFC_FMR = EEFC_FMR_FWS(1);
+		EFC1->EEFC_FMR = EEFC_FMR_FWS(1);
+	} else if (dw_clk < SYS_FREQ_FWS_2) {
+		EFC0->EEFC_FMR = EEFC_FMR_FWS(2);
+		EFC1->EEFC_FMR = EEFC_FMR_FWS(2);
+	} else if (dw_clk < SYS_FREQ_FWS_3) {
+		EFC0->EEFC_FMR = EEFC_FMR_FWS(3);
+		EFC1->EEFC_FMR = EEFC_FMR_FWS(3);
+	} else {
+		EFC0->EEFC_FMR = EEFC_FMR_FWS(4);
+		EFC1->EEFC_FMR = EEFC_FMR_FWS(4);
+	}
+	
+#ifndef CONFIG_KEEP_WATCHDOG_AFTER_INIT 
+	/* Disable the watchdog */
+	WDT->WDT_MR = WDT_MR_WDDIS;
+#endif
+}
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
diff --git a/hardware/sam/system/libsam/cmsis/sam3xa/source/templates/system_sam3x.h b/hardware/sam/system/libsam/cmsis/sam3xa/source/templates/system_sam3x.h
new file mode 100644
index 000000000..147901ac5
--- /dev/null
+++ b/hardware/sam/system/libsam/cmsis/sam3xa/source/templates/system_sam3x.h
@@ -0,0 +1,58 @@
+/*! \file *********************************************************************
+ *
+ * \brief CMSIS Cortex-M# Device Peripheral Access Layer Header File
+ *           for SAM3 devices.
+ *
+ * $asf_license$
+ *
+ * \par Purpose
+ *
+ * This file provides basic support for Cortex-M processor based 
+ * microcontrollers.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+#ifndef SYSTEM_SAM3X_H_INCLUDED
+#define SYSTEM_SAM3X_H_INCLUDED
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#include 
+
+extern uint32_t SystemCoreClock;	/* System Clock Frequency (Core Clock) */
+
+/**
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+void SystemInit(void);
+
+/** 
+ * Initialize the flash and watchdog setting .
+ */
+void set_flash_and_watchdog(void);
+
+/**
+ * @brief Updates the SystemCoreClock with current core Clock 
+ * retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void);
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#endif /* SYSTEM_SAM3X_H_INCLUDED */
diff --git a/hardware/sam/system/libsam/include/adc.h b/hardware/sam/system/libsam/include/adc.h
new file mode 100644
index 000000000..31534753c
--- /dev/null
+++ b/hardware/sam/system/libsam/include/adc.h
@@ -0,0 +1,139 @@
+/*! \file *********************************************************************
+ *
+ * \brief API for SAM3 Analog-to-Digital Converter (ADC/ADC12B) controller.
+ *
+ * ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * - Compiler:           IAR EWARM and CodeSourcery GCC for ARM
+ * - Supported devices:  All SAM devices with a Analog-to-Digital Converter can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.com/
+ *
+ *******************************************************************************/
+ 
+#ifndef ADC_H_INCLUDED
+#define ADC_H_INCLUDED
+
+#include "../chip.h"
+
+#define ADC_FREQ_MAX      5000000
+#define ADC_STARTUP            20
+
+#define ADC12_FREQ_MAX   20000000
+#define ADC12_FREQ_MIN    1000000
+
+#define ADC12_STARTUP_NORM     40
+#define ADC12_STARTUP_FAST     12
+
+/* Definitions for ADC resolution */
+typedef enum _adc_resolution_t {
+#if SAM3N || SAM3U
+    ADC_8_BITS = ADC_MR_LOWRES_BITS_8,  /* ADC 8-bit resolution */
+#endif /* SAM3N || SAM3U */
+    ADC_10_BITS = ADC_MR_LOWRES_BITS_10,  /* ADC 10-bit resolution */
+#if SAM3S || SAM3XA
+    ADC_12_BITS = ADC_MR_LOWRES_BITS_12,  /* ADC 12-bit resolution */
+#endif /* SAM3S || SAM3XA */
+    ADC_NONE
+} adc_resolution_t;
+
+#if SAM3U
+typedef enum _adc12_resolution_t {
+    ADC12_10_BITS = ADC12B_MR_LOWRES_BITS_10,  /* ADC 10-bit resolution */
+    ADC12_12_BITS = ADC12B_MR_LOWRES_BITS_12  /* ADC 12-bit resolution */
+} adc12_resolution_t;
+#endif /* SAM3U */
+
+/* Definitions for ADC trigger */
+typedef enum _adc_trigger_t {
+    ADC_TRIG_SW               = ADC_MR_TRGEN_DIS,  /* Starting a conversion is only possible by software. */
+    ADC_TRIG_EXT              = ((ADC_MR_TRGSEL_ADC_TRIG0 <
+
+/*
+ *         Global Definitions
+ */
+typedef enum _EPioType
+{
+  PIO_NOT_A_PIN, /* Not under control of a peripheral. */
+  PIO_PERIPH_A, /* The pin is controlled by the associated signal of peripheral A. */
+  PIO_PERIPH_B, /* The pin is controlled by the associated signal of peripheral B. */
+#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_)
+  PIO_PERIPH_C, /* The pin is controlled by the associated signal of peripheral C. */
+  PIO_PERIPH_D, /* The pin is controlled by the associated signal of peripheral D. */
+#endif /* (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_) */
+  PIO_INPUT, /* The pin is an input. */
+  PIO_OUTPUT_0, /* The pin is an output and has a default level of 0. */
+  PIO_OUTPUT_1 /* The pin is an output and has a default level of 1. */
+} EPioType ;
+
+
+/*  Default pin configuration (no attribute). */
+#define PIO_DEFAULT                 (0u << 0)
+/*  The internal pin pull-up is active. */
+#define PIO_PULLUP                  (1u << 0)
+/*  The internal glitch filter is active. */
+#define PIO_DEGLITCH                (1u << 1)
+/*  The pin is open-drain. */
+#define PIO_OPENDRAIN               (1u << 2)
+
+/*  The internal debouncing filter is active. */
+#define PIO_DEBOUNCE                (1u << 3)
+
+/*  Enable additional interrupt modes. */
+#define PIO_IT_AIME                 (1u << 4)
+
+/*  Interrupt High Level/Rising Edge detection is active. */
+#define PIO_IT_RE_OR_HL             (1u << 5)
+/*  Interrupt Edge detection is active. */
+#define PIO_IT_EDGE                 (1u << 6)
+
+/*  Low level interrupt is active */
+#define PIO_IT_LOW_LEVEL            (0               | 0 | PIO_IT_AIME)
+/*  High level interrupt is active */
+#define PIO_IT_HIGH_LEVEL           (PIO_IT_RE_OR_HL | 0 | PIO_IT_AIME)
+/*  Falling edge interrupt is active */
+#define PIO_IT_FALL_EDGE            (0               | PIO_IT_EDGE | PIO_IT_AIME)
+/*  Rising edge interrupt is active */
+#define PIO_IT_RISE_EDGE            (PIO_IT_RE_OR_HL | PIO_IT_EDGE | PIO_IT_AIME)
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*
+ *  The #attribute# field is a bitmask that can either be set to PIO_DEFAULt,
+ *  or combine (using bitwise OR '|') any number of the following constants:
+ *     - PIO_PULLUP
+ *     - PIO_DEGLITCH
+ *     - PIO_DEBOUNCE
+ *     - PIO_OPENDRAIN
+ *     - PIO_IT_LOW_LEVEL
+ *     - PIO_IT_HIGH_LEVEL
+ *     - PIO_IT_FALL_EDGE
+ *     - PIO_IT_RISE_EDGE
+ */
+
+
+/*
+ *         Global Functions
+ */
+extern void PIO_DisableInterrupt( Pio* pPio, const uint32_t dwMask ) ;
+extern void PIO_PullUp( Pio* pPio, const uint32_t dwMask, const uint32_t dwPullUpEnable ) ;
+extern void PIO_SetDebounceFilter( Pio* pPio, const uint32_t dwMask, const uint32_t dwCuttOff ) ;
+
+extern void PIO_Set( Pio* pPio, const uint32_t dwMask ) ;
+extern void PIO_Clear( Pio* pPio, const uint32_t dwMask ) ;
+extern uint32_t PIO_Get( Pio* pPio, const EPioType dwType, const uint32_t dwMask ) ;
+
+extern void PIO_SetPeripheral( Pio* pPio, const EPioType dwType, const uint32_t dwMask ) ;
+extern void PIO_SetInput( Pio* pPio, uint32_t dwMask, uint32_t dwAttribute ) ;
+extern void PIO_SetOutput( Pio* pPio, uint32_t dwMask, uint32_t dwDefaultValue,
+                                      uint32_t dwMultiDriveEnable, uint32_t dwPullUpEnable ) ;
+
+extern uint32_t PIO_Configure( Pio* pPio, const EPioType dwType, const uint32_t dwMask, const uint32_t dwAttribute ) ;
+
+extern uint32_t PIO_GetOutputDataStatus( const Pio* pPio, const uint32_t dwMask ) ;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _PIO_ */
+
diff --git a/hardware/sam/system/libsam/include/pio_it.h b/hardware/sam/system/libsam/include/pio_it.h
new file mode 100644
index 000000000..9d38cd2b2
--- /dev/null
+++ b/hardware/sam/system/libsam/include/pio_it.h
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ *  \file
+ *
+ *  \par Purpose
+ *
+ *  Configuration and handling of interrupts on PIO status changes. The API
+ *  provided here have several advantages over the traditional PIO interrupt
+ *  configuration approach:
+ *     - It is highly portable
+ *     - It automatically demultiplexes interrupts when multiples pins have been
+ *       configured on a single PIO controller
+ *     - It allows a group of pins to share the same interrupt
+ *
+ *  However, it also has several minor drawbacks that may prevent from using it
+ *  in particular applications:
+ *     - It enables the clocks of all PIO controllers
+ *     - PIO controllers all share the same interrupt handler, which does the
+ *       demultiplexing and can be slower than direct configuration
+ *     - It reserves space for a fixed number of interrupts, which can be
+ *       increased by modifying the appropriate constant in pio_it.c.
+ *
+ *  \par Usage
+ *
+ *  -# Initialize the PIO interrupt mechanism using PIO_InitializeInterrupts()
+ *     with the desired priority (0 ... 7).
+ *  -# Configure a status change interrupt on one or more pin(s) with
+ *     PIO_ConfigureIt().
+ *  -# Enable & disable interrupts on pins using PIO_EnableIt() and
+ *     PIO_DisableIt().
+ */
+
+#ifndef _PIO_IT_
+#define _PIO_IT_
+
+/*
+ *         Headers
+ */
+
+#include "pio.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*
+ *         Global functions
+ */
+
+extern void PIO_InitializeInterrupts( uint32_t dwPriority ) ;
+
+extern void PIO_ConfigureIt( const Pin *pPin, void (*handler)( const Pin* ) ) ;
+
+extern void PIO_EnableIt( const Pio* pPio, const uint32_t dwMask ) ;
+extern void PIO_DisableIt( const Pio* pPio, const uint32_t dwMask ) ;
+
+extern void PIO_IT_InterruptHandler( void ) ;
+
+extern void PioInterruptHandler( uint32_t id, Pio *pPio ) ;
+
+extern void PIO_CaptureHandler( void ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _PIO_IT_ */
+
diff --git a/hardware/sam/system/libsam/include/pmc.h b/hardware/sam/system/libsam/include/pmc.h
new file mode 100644
index 000000000..5b82a1f0b
--- /dev/null
+++ b/hardware/sam/system/libsam/include/pmc.h
@@ -0,0 +1,56 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _PMC_
+#define _PMC_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include 
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern void PMC_EnablePeripheral( uint32_t dwId ) ;
+extern void PMC_DisablePeripheral( uint32_t dwId ) ;
+
+extern uint32_t PMC_IsPeripheralEnabled( uint32_t dwId ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _PMC_ */
+
diff --git a/hardware/sam/system/libsam/include/pwmc.h b/hardware/sam/system/libsam/include/pwmc.h
new file mode 100644
index 000000000..4ec6b7883
--- /dev/null
+++ b/hardware/sam/system/libsam/include/pwmc.h
@@ -0,0 +1,127 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * \par Purpose
+ *
+ * Interface for configuration the Pulse Width Modulation Controller (PWM) peripheral.
+ *
+ * \par Usage
+ *
+ *    -# Configures PWM clocks A & B to run at the given frequencies using
+ *       \ref PWMC_ConfigureClocks().
+ *    -# Configure PWMC channel using \ref PWMC_ConfigureChannel(), \ref PWMC_ConfigureChannelExt()
+ *       \ref PWMC_SetPeriod(), \ref PWMC_SetDutyCycle() and \ref PWMC_SetDeadTime().
+ *    -# Enable & disable channel using \ref PWMC_EnableChannel() and
+ *       \ref PWMC_DisableChannel().
+ *    -# Enable & disable the period interrupt for the given PWM channel using
+ *       \ref PWMC_EnableChannelIt() and \ref PWMC_DisableChannelIt().
+ *    -# Enable & disable the selected interrupts sources on a PWMC peripheral
+ *       using  \ref PWMC_EnableIt() and \ref PWMC_DisableIt().
+ *    -# Control syncronous channel using \ref PWMC_ConfigureSyncChannel(),
+ *       \ref PWMC_SetSyncChannelUpdatePeriod() and \ref PWMC_SetSyncChannelUpdateUnlock().
+ *    -# Control PWM override output using \ref PWMC_SetOverrideValue(),
+ *       \ref PWMC_EnableOverrideOutput() and \ref PWMC_DisableOverrideOutput().
+ *    -# Send data through the transmitter using \ref PWMC_WriteBuffer().
+ *
+ */
+
+#ifndef _PWMC_
+#define _PWMC_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "../chip.h"
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+extern void PWMC_ConfigureChannel(
+    Pwm* pPwm,
+    uint8_t channel,
+    uint32_t prescaler,
+    uint32_t alignment,
+    uint32_t polarity);
+extern void PWMC_ConfigureChannelExt(
+    Pwm* pPwm,
+    uint8_t channel,
+    uint32_t prescaler,
+    uint32_t alignment,
+    uint32_t polarity,
+    uint32_t countEventSelect,
+    uint32_t DTEnable,
+    uint32_t DTHInverte,
+    uint32_t DTLInverte);
+extern void PWMC_ConfigureClocks(uint32_t clka, uint32_t clkb, uint32_t mck);
+extern void PWMC_SetPeriod( Pwm* pPwm, uint8_t channel, uint16_t period);
+extern void PWMC_SetDutyCycle( Pwm* pPwm, uint8_t channel, uint16_t duty);
+extern void PWMC_SetDeadTime( Pwm* pPwm, uint8_t channel, uint16_t timeH, uint16_t timeL);
+extern void PWMC_ConfigureSyncChannel( Pwm* pPwm,
+    uint32_t channels,
+    uint32_t updateMode,
+    uint32_t requestMode,
+    uint32_t requestComparisonSelect);
+extern void PWMC_SetSyncChannelUpdatePeriod( Pwm* pPwm, uint8_t period);
+extern void PWMC_SetSyncChannelUpdateUnlock( Pwm* pPwm );
+extern void PWMC_EnableChannel( Pwm* pPwm, uint8_t channel);
+extern void PWMC_DisableChannel( Pwm* pPwm, uint8_t channel);
+extern void PWMC_EnableChannelIt( Pwm* pPwm, uint8_t channel);
+extern void PWMC_DisableChannelIt( Pwm* pPwm, uint8_t channel);
+extern void PWMC_EnableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2);
+extern void PWMC_DisableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2);
+extern uint8_t PWMC_WriteBuffer(Pwm *pwmc,
+    void *buffer,
+    uint32_t length);
+extern void PWMC_SetOverrideValue( Pwm* pPwm, uint32_t value);
+extern void PWMC_EnableOverrideOutput( Pwm* pPwm, uint32_t value, uint32_t sync);
+extern void PWMC_DisableOverrideOutput( Pwm* pPwm, uint32_t value, uint32_t sync);
+extern void PWMC_SetFaultMode( Pwm* pPwm, uint32_t mode);
+extern void PWMC_FaultClear( Pwm* pPwm, uint32_t fault);
+extern void PWMC_SetFaultProtectionValue( Pwm* pPwm, uint32_t value);
+extern void PWMC_EnableFaultProtection( Pwm* pPwm, uint32_t value);
+extern void PWMC_ConfigureComparisonUnit( Pwm* pPwm, uint32_t x, uint32_t value, uint32_t mode);
+extern void PWMC_ConfigureEventLineMode( Pwm* pPwm, uint32_t x, uint32_t mode);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _PWMC_ */
+
diff --git a/hardware/sam/system/libsam/include/rtc.h b/hardware/sam/system/libsam/include/rtc.h
new file mode 100644
index 000000000..6393bccf0
--- /dev/null
+++ b/hardware/sam/system/libsam/include/rtc.h
@@ -0,0 +1,97 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * Interface for Real Time Clock (RTC) controller.
+ *
+ */
+
+#ifndef _RTC_
+#define _RTC_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include "../chip.h"
+
+#include 
+
+/*----------------------------------------------------------------------------
+ *        Definitions
+ *----------------------------------------------------------------------------*/
+
+#define RTC_HOUR_BIT_LEN_MASK   0x3F
+#define RTC_MIN_BIT_LEN_MASK    0x7F
+#define RTC_SEC_BIT_LEN_MASK    0x7F
+#define RTC_CENT_BIT_LEN_MASK   0x7F
+#define RTC_YEAR_BIT_LEN_MASK   0xFF
+#define RTC_MONTH_BIT_LEN_MASK  0x1F
+#define RTC_DATE_BIT_LEN_MASK   0x3F
+#define RTC_WEEK_BIT_LEN_MASK   0x07
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern void RTC_SetHourMode( Rtc* pRtc, uint32_t dwMode ) ;
+
+extern uint32_t RTC_GetHourMode( Rtc* pRtc ) ;
+
+extern void RTC_EnableIt( Rtc* pRtc, uint32_t dwSources ) ;
+
+extern void RTC_DisableIt( Rtc* pRtc, uint32_t dwSources ) ;
+
+extern int RTC_SetTime( Rtc* pRtc, uint8_t ucHour, uint8_t ucMinute, uint8_t ucSecond ) ;
+
+extern void RTC_GetTime( Rtc* pRtc, uint8_t *pucHour, uint8_t *pucMinute, uint8_t *pucSecond ) ;
+
+extern int RTC_SetTimeAlarm( Rtc* pRtc, uint8_t *pucHour, uint8_t *pucMinute, uint8_t *pucSecond ) ;
+
+extern void RTC_GetDate( Rtc* pRtc, uint16_t *pwYear, uint8_t *pucMonth, uint8_t *pucDay, uint8_t *pucWeek ) ;
+
+extern int RTC_SetDate( Rtc* pRtc, uint16_t wYear, uint8_t ucMonth, uint8_t ucDay, uint8_t ucWeek ) ;
+
+extern int RTC_SetDateAlarm( Rtc* pRtc, uint8_t *pucMonth, uint8_t *pucDay ) ;
+
+extern void RTC_ClearSCCR( Rtc* pRtc, uint32_t dwMask ) ;
+
+extern uint32_t RTC_GetSR( Rtc* pRtc, uint32_t dwMask ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _RTC_ */
+
diff --git a/hardware/sam/system/libsam/include/rtt.h b/hardware/sam/system/libsam/include/rtt.h
new file mode 100644
index 000000000..9823d8502
--- /dev/null
+++ b/hardware/sam/system/libsam/include/rtt.h
@@ -0,0 +1,82 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * \par Purpose
+ *
+ * Interface for Real Time Timer (RTT) controller.
+ *
+ * \par Usage
+ *
+ * -# Changes the prescaler value of the given RTT and restarts it
+ *    using \ref RTT_SetPrescaler().
+ * -# Get current value of the RTT using \ref RTT_GetTime().
+ * -# Enables the specified RTT interrupt using \ref RTT_EnableIT().
+ * -# Get the status register value of the given RTT using \ref RTT_GetStatus().
+ * -# Configures the RTT to generate an alarm at the given time
+ *    using \ref RTT_SetAlarm().
+ */
+
+#ifndef _RTT_
+#define _RTT_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "../chip.h"
+
+#include 
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern void RTT_SetPrescaler( Rtt* pRtt, uint16_t wPrescaler ) ;
+
+extern uint32_t RTT_GetTime( Rtt* pRtt ) ;
+
+extern void RTT_EnableIT( Rtt* pRtt, uint32_t dwSources ) ;
+
+extern uint32_t RTT_GetStatus( Rtt *pRtt ) ;
+
+extern void RTT_SetAlarm( Rtt *pRtt, uint32_t dwTime ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef RTT_H */
+
diff --git a/hardware/sam/system/libsam/include/sam.h b/hardware/sam/system/libsam/include/sam.h
new file mode 100644
index 000000000..429bb71b7
--- /dev/null
+++ b/hardware/sam/system/libsam/include/sam.h
@@ -0,0 +1,137 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM_DEFS_
+#define _SAM_DEFS_
+
+#define part_is_defined(part) (defined(__ ## part ## __))
+
+/* SAM3 family */
+
+/* SAM3S series */
+#define SAM3S1 ( \
+    part_is_defined( SAM3S1A ) || \
+    part_is_defined( SAM3S1B ) || \
+    part_is_defined( SAM3S1C ) )
+
+#define SAM3S2 ( \
+    part_is_defined( SAM3S2A ) || \
+    part_is_defined( SAM3S2B ) || \
+    part_is_defined( SAM3S2C ) )
+
+#define SAM3S4 ( \
+    part_is_defined( SAM3S4A ) || \
+    part_is_defined( SAM3S4B ) || \
+    part_is_defined( SAM3S4C ) )
+
+#define SAM3S8 ( \
+    part_is_defined( SAM3S8B ) || \
+    part_is_defined( SAM3S8C ) )
+
+#define SAM3SD8 ( \
+    part_is_defined( SAM3SD8B ) || \
+    part_is_defined( SAM3SD8C ) )
+
+#define SAM3U1 ( \
+    part_is_defined( SAM3U1C ) || \
+    part_is_defined( SAM3U1E ) )
+
+#define SAM3U2 ( \
+    part_is_defined( SAM3U2C ) || \
+    part_is_defined( SAM3U2E ) )
+
+#define SAM3U4 ( \
+    part_is_defined( SAM3U4C ) || \
+    part_is_defined( SAM3U4E ) )
+
+#define SAM3N1 ( \
+    part_is_defined( SAM3N1A ) || \
+    part_is_defined( SAM3N1B ) || \
+    part_is_defined( SAM3N1C ) )
+
+#define SAM3N2 ( \
+    part_is_defined( SAM3N2A ) || \
+    part_is_defined( SAM3N2B ) || \
+    part_is_defined( SAM3N2C ) )
+
+#define SAM3N4 ( \
+    part_is_defined( SAM3N4A ) || \
+    part_is_defined( SAM3N4B ) || \
+    part_is_defined( SAM3N4C ) )
+	
+#define SAM3X2 ( \
+    part_is_defined( SAM3X2C ) || \
+	part_is_defined( SAM3X2E ) || \
+    part_is_defined( SAM3X2G ) || \
+    part_is_defined( SAM3X2H ) )
+
+#define SAM3X4 ( \
+    part_is_defined( SAM3X4C ) || \
+	part_is_defined( SAM3X4E ) || \
+    part_is_defined( SAM3X4G ) || \
+    part_is_defined( SAM3X4H ) )
+
+#define SAM3X8 ( \
+    part_is_defined( SAM3X8C ) || \
+	part_is_defined( SAM3X8E ) || \
+    part_is_defined( SAM3X8G ) || \
+    part_is_defined( SAM3X8H ) )
+
+#define SAM3A2 ( \
+    part_is_defined( SAM3A2C ) )
+
+#define SAM3A4 ( \
+    part_is_defined( SAM3A4C ) )
+
+#define SAM3A8 ( \
+    part_is_defined( SAM3A8C ) )
+
+/* Entire SAM3S Family */
+#define SAM3S (SAM3S1 || SAM3S2 || SAM3S4 || SAM3S8 || SAM3SD8)
+
+/* Entire SAM3U Family */
+#define SAM3U (SAM3U1 || SAM3U2 || SAM3U4)
+
+/* Entire SAM3N Family */
+#define SAM3N (SAM3N1 || SAM3N2 || SAM3N4)
+
+/* Entire SAM3XA Family */
+#define SAM3XA (SAM3X2 || SAM3X4 || SAM3X8 || SAM3A2 || SAM3A4 || SAM3A8)
+
+/* SAM9 family */
+
+/* SAM7 family */
+
+
+/* Global SAM product line */
+#define SAM ( SAM3S || SAM3U || SAM3N || SAM3XA )
+
+#include "include/sam3.h"
+
+#endif /* _SAM_DEFS_ */
diff --git a/hardware/sam/system/libsam/include/sam3.h b/hardware/sam/system/libsam/include/sam3.h
new file mode 100644
index 000000000..4320a9abc
--- /dev/null
+++ b/hardware/sam/system/libsam/include/sam3.h
@@ -0,0 +1,103 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3_
+#define _SAM3_
+
+#if (defined __SAM3S8A__) || (defined __SAM3S8B__) || (defined __SAM3S8C__) /* SAM3S8 */
+  #include "cmsis/sam3s8/include/sam3s8.h"
+  #include "cmsis/sam3s8/source/templates/system_sam3s8.h"
+  #include "cmsis/sam3s8/source/templates/exceptions.h"
+#elif (defined __SAM3SD8A__) || (defined __SAM3SD8B__) || (defined __SAM3SD8C__) /* SAM3SD8 */
+  #include "cmsis/sam3s8/include/sam3s8.h"
+  #include "cmsis/sam3s8/source/templates/system_sam3s8.h"
+  #include "cmsis/sam3s8/source/templates/exceptions.h"
+
+#elif (defined __SAM3S4C__) || (defined __SAM3S4B__) || (defined __SAM3S4A__) /* SAM3S4 */
+  #include "cmsis/sam3s/include/sam3s.h"
+  #include "cmsis/sam3s/source/templates/system_sam3s.h"
+  #include "cmsis/sam3s/source/templates/exceptions.h"
+#elif (defined __SAM3S2C__) || (defined __SAM3S2B__) || (defined __SAM3S2A__) /* SAM3S2 */
+  #include "cmsis/sam3s/include/sam3s.h"
+  #include "cmsis/sam3s/source/templates/system_sam3s.h"
+  #include "cmsis/sam3s/source/templates/exceptions.h"
+#elif (defined __SAM3S1C__) || (defined __SAM3S1B__) || (defined __SAM3S1A__) /* SAM3S1 */
+  #include "cmsis/sam3s/include/sam3s.h"
+  #include "cmsis/sam3s/source/templates/system_sam3s.h"
+  #include "cmsis/sam3s/source/templates/exceptions.h"
+
+#elif (defined __SAM3U4C__) || (defined __SAM3U4E__) /* SAM3U4 */
+  #include "cmsis/sam3u/include/sam3u.h"
+  #include "cmsis/sam3u/source/templates/system_sam3u.h"
+  #include "cmsis/sam3u/source/templates/exceptions.h"
+#elif (defined __SAM3U2C__) || (defined __SAM3U2E__) /* SAM3U2 */
+  #include "cmsis/sam3u/include/sam3u.h"
+  #include "cmsis/sam3u/source/templates/system_sam3u.h"
+  #include "cmsis/sam3u/source/templates/exceptions.h"
+#elif (defined __SAM3U1C__) || (defined __SAM3U1E__) /* SAM3U1 */
+  #include "cmsis/sam3u/include/sam3u.h"
+  #include "cmsis/sam3u/source/templates/system_sam3u.h"
+  #include "cmsis/sam3u/source/templates/exceptions.h"
+
+#elif (defined __SAM3N4C__) || (defined __SAM3N4B__) || (defined __SAM3N4A__) /* SAM3N4 */
+  #include "cmsis/sam3n/include/sam3n.h"
+  #include "cmsis/sam3n/source/templates/system_sam3n.h"
+  #include "cmsis/sam3n/source/templates/exceptions.h"
+#elif (defined __SAM3N2C__) || (defined __SAM3N2B__) || (defined __SAM3N2A__) /* SAM3N2 */
+  #include "cmsis/sam3n/include/sam3n.h"
+  #include "cmsis/sam3n/source/templates/system_sam3n.h"
+  #include "cmsis/sam3n/source/templates/exceptions.h"
+#elif (defined __SAM3N1C__) || (defined __SAM3N1B__) || (defined __SAM3N1A__) /* SAM3N1 */
+  #include "cmsis/sam3n/include/sam3n.h"
+  #include "cmsis/sam3n/source/templates/system_sam3n.h"
+  #include "cmsis/sam3n/source/templates/exceptions.h"
+
+#elif (defined __SAM3A8C__) || (defined __SAM3A4C__) || (defined __SAM3A2C__) /* SAM3A */
+  #include "cmsis/sam3xa/include/sam3xa.h"
+  #include "cmsis/sam3xa/source/templates/system_sam3xa.h"
+  #include "cmsis/sam3xa/source/templates/exceptions.h"
+
+#elif (defined __SAM3X8C__) || (defined __SAM3X8E__) || (defined __SAM3X8G__) || (defined __SAM3X8H__) /* SAM3X8 */
+  #include "cmsis/sam3xa/include/sam3xa.h"
+  #include "cmsis/sam3xa/source/templates/system_sam3xa.h"
+  #include "cmsis/sam3xa/source/templates/exceptions.h"
+#elif (defined __SAM3X4C__) || (defined __SAM3X4E__) || (defined __SAM3X4G__) || (defined __SAM3X4H__) /* SAM3X4 */
+  #include "cmsis/sam3xa/include/sam3xa.h"
+  #include "cmsis/sam3xa/source/templates/system_sam3xa.h"
+  #include "cmsis/sam3xa/source/templates/exceptions.h"
+#elif (defined __SAM3X2C__) || (defined __SAM3X2E__) || (defined __SAM3X2G__) || (defined __SAM3X2H__) /* SAM3X2 */
+  #include "cmsis/sam3xa/include/sam3xa.h"
+  #include "cmsis/sam3xa/source/templates/system_sam3xa.h"
+  #include "cmsis/sam3xa/source/templates/exceptions.h"
+
+#else
+  #error Library does not support the specified device.
+#endif
+
+#endif /* _SAM3_ */
diff --git a/hardware/sam/system/libsam/include/spi.h b/hardware/sam/system/libsam/include/spi.h
new file mode 100644
index 000000000..1fb69addb
--- /dev/null
+++ b/hardware/sam/system/libsam/include/spi.h
@@ -0,0 +1,117 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * Interface for Serial Peripheral Interface (SPI) controller.
+ *
+ */
+
+#ifndef _SPI_
+#define _SPI_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "../chip.h"
+
+/*----------------------------------------------------------------------------
+ *        Macros
+ *----------------------------------------------------------------------------*/
+
+/**
+ *
+ * Here are several macros which should be used when configuring a SPI
+ * peripheral.
+ *
+ * \section spi_configuration_macros SPI Configuration Macros
+ * - \ref SPI_PCS
+ * - \ref SPI_SCBR
+ * - \ref SPI_DLYBS
+ * - \ref SPI_DLYBCT
+ */
+
+/** Calculate the PCS field value given the chip select NPCS value */
+#define SPI_PCS(npcs)       ((~(1 << (npcs)) & 0xF) << 16)
+
+/** Calculates the value of the CSR SCBR field given the baudrate and MCK. */
+#define SPI_SCBR(baudrate, masterClock) ((uint32_t) ((masterClock) / (baudrate)) << 8)
+
+/** Calculates the value of the CSR DLYBS field given the desired delay (in ns) */
+#define SPI_DLYBS(delay, masterClock) ((uint32_t) ((((masterClock) / 1000000) * (delay)) / 1000) << 16)
+
+/** Calculates the value of the CSR DLYBCT field given the desired delay (in ns) */
+#define SPI_DLYBCT(delay, masterClock) ((uint32_t) ((((masterClock) / 1000000) * (delay)) / 32000) << 24)
+
+/*------------------------------------------------------------------------------ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+extern void SPI_Enable( Spi* spi ) ;
+extern void SPI_Disable( Spi* spi ) ;
+extern void SPI_EnableIt( Spi* spi, uint32_t dwSources ) ;
+extern void SPI_DisableIt( Spi* spi, uint32_t dwSources ) ;
+
+extern void SPI_Configure( Spi* spi, uint32_t dwId, uint32_t dwConfiguration ) ;
+extern void SPI_ConfigureNPCS( Spi* spi, uint32_t dwNpcs, uint32_t dwConfiguration ) ;
+
+extern uint32_t SPI_Read( Spi* spi ) ;
+extern void SPI_Write( Spi* spi, uint32_t dwNpcs, uint16_t wData ) ;
+
+extern uint32_t SPI_GetStatus( Spi* spi ) ;
+extern uint32_t SPI_IsFinished( Spi* pSpi ) ;
+
+#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_)
+extern void SPI_PdcEnableTx( Spi* spi ) ;
+extern void SPI_PdcDisableTx( Spi* spi ) ;
+extern void SPI_PdcEnableRx( Spi* spi ) ;
+extern void SPI_PdcDisableRx( Spi* spi ) ;
+
+extern void SPI_PdcSetTx( Spi* spi, void* pvTxBuf, uint32_t dwTxCount, void* pvTxNextBuf, uint32_t dwTxNextCount ) ;
+extern void SPI_PdcSetRx( Spi* spi, void* pvRxBuf, uint32_t dwRxCount, void* pvRxNextBuf, uint32_t dwRxNextCount ) ;
+
+extern uint32_t SPI_WriteBuffer( Spi* spi, void* pvBuffer, uint32_t dwLength ) ;
+
+extern uint32_t SPI_ReadBuffer( Spi* spi, void* pvBuffer, uint32_t dwLength ) ;
+#endif /* (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _SPI_ */
+
diff --git a/hardware/sam/system/libsam/include/tc.h b/hardware/sam/system/libsam/include/tc.h
new file mode 100644
index 000000000..92c0b0367
--- /dev/null
+++ b/hardware/sam/system/libsam/include/tc.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ *  \file
+ *
+ *  \section Purpose
+ *
+ *  Interface for configuring and using Timer Counter (TC) peripherals.
+ *
+ *  \section Usage
+ *  -# Optionally, use TC_FindMckDivisor() to let the program find the best
+ *     TCCLKS field value automatically.
+ *  -# Configure a Timer Counter in the desired mode using TC_Configure().
+ *  -# Start or stop the timer clock using TC_Start() and TC_Stop().
+ */
+
+#ifndef _TC_
+#define _TC_
+
+/*------------------------------------------------------------------------------
+ *         Headers
+ *------------------------------------------------------------------------------*/
+
+#include "../chip.h"
+
+#include 
+
+/*------------------------------------------------------------------------------
+ *         Global functions
+ *------------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern void TC_Configure( Tc *pTc, uint32_t dwChannel, uint32_t dwMode ) ;
+
+extern void TC_Start( Tc *pTc, uint32_t dwChannel ) ;
+
+extern void TC_Stop( Tc *pTc, uint32_t dwChannel ) ;
+
+extern uint32_t TC_FindMckDivisor( uint32_t dwFreq, uint32_t dwMCk, uint32_t *dwDiv, uint32_t *dwTcClks, uint32_t dwBoardMCK ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _TC_ */
+
diff --git a/hardware/sam/system/libsam/include/timetick.h b/hardware/sam/system/libsam/include/timetick.h
new file mode 100644
index 000000000..62bdf2e18
--- /dev/null
+++ b/hardware/sam/system/libsam/include/timetick.h
@@ -0,0 +1,78 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ *  \file
+ *
+ *  \par Purpose
+ *
+ *  Methods and definitions for Global time tick and wait functions.
+ *
+ *  Defines a common and simpliest use of Time Tick, to increase tickCount
+ *  every 1ms, the application can get this value through GetTickCount().
+ *
+ *  \par Usage
+ *
+ *  -# Configure the System Tick with TimeTick_Configure() when MCK changed
+ *     \note
+ *     Must be done before any invoke of GetTickCount(), Wait() or Sleep().
+ *  -# Uses GetTickCount to get current tick value.
+ *  -# Uses Wait to wait several ms.
+ *  -# Uses Sleep to enter wait for interrupt mode to wait several ms.
+ *
+ */
+
+#ifndef _TIMETICK_
+#define _TIMETICK_
+
+/*----------------------------------------------------------------------------
+ *         Headers
+ *----------------------------------------------------------------------------*/
+
+#include 
+
+/*----------------------------------------------------------------------------
+ *         Definitions
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ *         Global functions
+ *----------------------------------------------------------------------------*/
+
+extern uint32_t TimeTick_Configure( uint32_t dwNew_MCK ) ;
+
+extern void TimeTick_Increment( void ) ;
+
+extern uint32_t GetTickCount( void ) ;
+
+extern void Wait( volatile uint32_t dwMs ) ;
+
+extern void Sleep( volatile uint32_t dwMs ) ;
+
+#endif /* _TIMETICK_ */
diff --git a/hardware/sam/system/libsam/include/twi.h b/hardware/sam/system/libsam/include/twi.h
new file mode 100644
index 000000000..c4ef4f009
--- /dev/null
+++ b/hardware/sam/system/libsam/include/twi.h
@@ -0,0 +1,111 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * Interface for configuration the Two Wire Interface (TWI) peripheral.
+ *
+ */
+
+#ifndef _TWI_
+#define _TWI_
+
+/*------------------------------------------------------------------------------
+ *         Headers
+ *------------------------------------------------------------------------------*/
+
+#include "../chip.h"
+
+#include 
+
+/*----------------------------------------------------------------------------
+ *        Macros
+ *----------------------------------------------------------------------------*/
+/* Returns 1 if the TXRDY bit (ready to transmit data) is set in the given status register value.*/
+#define TWI_STATUS_TXRDY(status) (((status) & TWI_SR_TXRDY) == TWI_SR_TXRDY)
+
+/* Returns 1 if the RXRDY bit (ready to receive data) is set in the given status register value.*/
+#define TWI_STATUS_RXRDY(status) (((status) & TWI_SR_RXRDY) == TWI_SR_RXRDY)
+
+/* Returns 1 if the TXCOMP bit (transfer complete) is set in the given status register value.*/
+#define TWI_STATUS_TXCOMP(status) (((status) & TWI_SR_TXCOMP) == TWI_SR_TXCOMP)
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------
+ *        External function
+ *----------------------------------------------------------------------------*/
+
+extern void TWI_ConfigureMaster(Twi *pTwi, uint32_t twck, uint32_t mck);
+
+extern void TWI_ConfigureSlave(Twi *pTwi, uint8_t slaveAddress);
+
+extern void TWI_Stop(Twi *pTwi);
+
+extern void TWI_StartRead(
+    Twi *pTwi,
+    uint8_t address,
+    uint32_t iaddress,
+    uint8_t isize);
+
+extern uint8_t TWI_ReadByte(Twi *pTwi);
+
+extern void TWI_WriteByte(Twi *pTwi, uint8_t byte);
+
+extern void TWI_StartWrite(
+    Twi *pTwi,
+    uint8_t address,
+    uint32_t iaddress,
+    uint8_t isize,
+    uint8_t byte);
+
+extern uint8_t TWI_ByteReceived(Twi *pTwi);
+
+extern uint8_t TWI_ByteSent(Twi *pTwi);
+
+extern uint8_t TWI_TransferComplete(Twi *pTwi);
+
+extern void TWI_EnableIt(Twi *pTwi, uint32_t sources);
+
+extern void TWI_DisableIt(Twi *pTwi, uint32_t sources);
+
+extern uint32_t TWI_GetStatus(Twi *pTwi);
+
+extern uint32_t TWI_GetMaskedStatus(Twi *pTwi);
+
+extern void TWI_SendSTOPCondition(Twi *pTwi);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _TWI_ */
diff --git a/hardware/sam/system/libsam/include/usart.h b/hardware/sam/system/libsam/include/usart.h
new file mode 100644
index 000000000..d20ae07b1
--- /dev/null
+++ b/hardware/sam/system/libsam/include/usart.h
@@ -0,0 +1,133 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * \par Purpose
+ *
+ * This module provides several definitions and methods for using an USART
+ * peripheral.
+ *
+ * \par Usage
+ *
+ * -# Enable the USART peripheral clock in the PMC.
+ * -# Enable the required USART PIOs (see pio.h).
+ * -# Configure the UART by calling USART_Configure.
+ * -# Enable the transmitter and/or the receiver of the USART using
+ *    USART_SetTransmitterEnabled and USART_SetReceiverEnabled.
+ * -# Send data through the USART using the USART_Write and
+ *    USART_WriteBuffer methods.
+ * -# Receive data from the USART using the USART_Read and
+ *    USART_ReadBuffer functions; the availability of data can be polled
+ *    with USART_IsDataAvailable.
+ * -# Disable the transmitter and/or the receiver of the USART with
+ *    USART_SetTransmitterEnabled and USART_SetReceiverEnabled.
+ */
+
+#ifndef _USART_
+#define _USART_
+
+/*------------------------------------------------------------------------------
+ *         Headers
+ *------------------------------------------------------------------------------*/
+
+#include "../chip.h"
+
+#include 
+
+/*------------------------------------------------------------------------------
+ *         Definitions
+ *------------------------------------------------------------------------------*/
+
+/** \section USART_mode USART modes
+ * This section lists several common operating modes for an USART peripheral.
+ *
+ * \b Modes
+ * - USART_MODE_ASYNCHRONOUS
+ * - USART_MODE_IRDA
+ */
+
+/** Basic asynchronous mode, i.e. 8 bits no parity.*/
+#define USART_MODE_ASYNCHRONOUS        (US_MR_CHRL_8_BIT | US_MR_PAR_NO)
+
+/** IRDA mode*/
+#define USART_MODE_IRDA                (AT91C_US_USMODE_IRDA | AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE | AT91C_US_FILTER)
+
+/** SPI mode*/
+#define AT91C_US_USMODE_SPIM     0xE
+#define US_SPI_CPOL_0           (0x0<<16)
+#define US_SPI_CPHA_0            (0x0<<8)
+#define US_SPI_CPOL_1            (0x1<<16)
+#define US_SPI_CPHA_1            (0x1<<8)
+#define US_SPI_BPMODE_0    (US_SPI_CPOL_0|US_SPI_CPHA_1)
+#define US_SPI_BPMODE_1    (US_SPI_CPOL_0|US_SPI_CPHA_0)
+#define US_SPI_BPMODE_2    (US_SPI_CPOL_1|US_SPI_CPHA_1)
+#define US_SPI_BPMODE_3    (US_SPI_CPOL_1|US_SPI_CPHA_0)
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/*         Exported functions                                                   */
+/*------------------------------------------------------------------------------*/
+
+extern void USART_Configure( Usart *usart, uint32_t mode, uint32_t baudrate, uint32_t masterClock ) ;
+extern uint32_t USART_GetStatus( Usart *usart ) ;
+extern void USART_EnableIt( Usart *usart,uint32_t mode ) ;
+extern void USART_DisableIt( Usart *usart,uint32_t mode ) ;
+extern void USART_SetTransmitterEnabled( Usart *usart, uint8_t enabled ) ;
+
+extern void USART_SetReceiverEnabled( Usart *usart, uint8_t enabled ) ;
+
+extern void USART_Write( Usart *usart, uint16_t data, volatile uint32_t timeOut ) ;
+
+extern uint8_t USART_WriteBuffer( Usart *usart, void *buffer, uint32_t size ) ;
+
+extern uint16_t USART_Read( Usart *usart, volatile uint32_t timeOut ) ;
+
+extern uint8_t USART_ReadBuffer( Usart *usart, void *buffer, uint32_t size ) ;
+
+extern uint8_t USART_IsDataAvailable( Usart *usart ) ;
+
+extern void USART_SetIrdaFilter(Usart *pUsart, uint8_t filter);
+
+extern void USART_PutChar( Usart *usart, uint8_t c ) ;
+
+extern uint32_t USART_IsRxReady( Usart *usart ) ;
+
+extern uint8_t USART_GetChar( Usart *usart ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _USART_ */
+
diff --git a/hardware/sam/system/libsam/include/wdt.h b/hardware/sam/system/libsam/include/wdt.h
new file mode 100644
index 000000000..8a3f4a4e5
--- /dev/null
+++ b/hardware/sam/system/libsam/include/wdt.h
@@ -0,0 +1,74 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * \section Purpose
+ * Interface for Watchdog Timer (WDT) controller.
+ *
+ * \section Usage
+ * -# Enable watchdog with given mode using \ref WDT_Enable().
+ * -# Disable watchdog using \ref WDT_Disable()
+ * -# Restart the watchdog using \ref WDT_Restart().
+ * -# Get watchdog status using \ref  WDT_GetStatus().
+ * -# Caculate watchdog period value using \ref WDT_GetPeriod().
+ */
+
+#ifndef _WDT_
+#define _WDT_
+
+#include "../chip.h"
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+extern void WDT_Enable( Wdt* pWDT, uint32_t dwMode ) ;
+
+extern void WDT_Disable( Wdt* pWDT ) ;
+
+extern void WDT_Restart( Wdt* pWDT ) ;
+
+extern uint32_t WDT_GetStatus( Wdt* pWDT ) ;
+
+extern uint32_t WDT_GetPeriod( uint32_t dwMs ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _WDT_ */
+
diff --git a/hardware/sam/system/libsam/readme.txt b/hardware/sam/system/libsam/readme.txt
new file mode 100644
index 000000000..350b3cfe2
--- /dev/null
+++ b/hardware/sam/system/libsam/readme.txt
@@ -0,0 +1,33 @@
+Makefile into build_gcc folder build the SAM peripheral library and put it into ../../../cores/sam Arduino API folder
+
+/*
+ %atmel_license%
+*/
+=
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2010, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
diff --git a/hardware/sam/system/libsam/source/adc10_sam3u.c b/hardware/sam/system/libsam/source/adc10_sam3u.c
new file mode 100644
index 000000000..9531651df
--- /dev/null
+++ b/hardware/sam/system/libsam/source/adc10_sam3u.c
@@ -0,0 +1,331 @@
+/*! \file *********************************************************************
+ *
+ * \brief API for SAM3 Analog-to-Digital Converter (ADC/ADC12B) controller.
+ *
+ * ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * - Compiler:           IAR EWARM and CodeSourcery GCC for ARM
+ * - Supported devices:  All SAM devices with a Analog-to-Digital Converter can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.com/
+ *
+ *******************************************************************************/
+
+#include "../chip.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+/**INDENT-ON**/
+/// @endcond
+
+#if SAM3U
+
+/**
+ * \brief Initializes the given ADC with the specified ADC clock and startup time.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param dw_mck  Main clock of the device (value in Hz).
+ * \param dw_adc_clock  Analog-to-Digital conversion clock (value in Hz).
+ * \param ul_startuptime  ADC start up time value(value in us). Please refer to the product datasheet for details.
+ * \param ul_offmode_startuptime  ADC off mode startup Time value(value in us). Please refer to the product datasheet for details.
+ *
+ * \retval 0  The initialization operation succeeds.
+ * \retval others  The initialization operation fails.
+ */
+uint32_t adc_init(Adc *p_adc, uint32_t ul_mck, uint32_t ul_adc_clock, uint32_t ul_startuptime)
+{
+    p_adc->ADC_CR = ADC_CR_SWRST;
+	
+    /* Reset Mode Register */
+    p_adc->ADC_MR = 0;	
+	
+     /* Reset PDC transfer */
+    p_adc->ADC_PTCR = (ADC_PTCR_RXTDIS | ADC_PTCR_TXTDIS);
+    p_adc->ADC_RCR = 0;
+    p_adc->ADC_RNCR = 0;
+    p_adc->ADC_TCR = 0;
+    p_adc->ADC_TNCR = 0;		
+    uint32_t prescal = ul_mck/(2 * ul_adc_clock) - 1;
+    // check for rounding errors
+    if ( (ul_mck/((prescal+1)*2)) > ul_adc_clock ) {
+    	prescal++;
+    	ul_adc_clock = ul_mck/((prescal+1)*2);
+    }
+    uint32_t startup = ((ul_adc_clock/1000000) * ul_startuptime / 8) - 1;
+    p_adc->ADC_MR |= ADC_MR_PRESCAL(prescal) | ADC_MR_STARTUP(startup);
+    return 0;	
+}
+
+/**
+ * \brief Configures conversion resolution.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param resolution  ADC resolution.
+ */
+void adc_set_resolution(Adc *p_adc, adc_resolution_t resolution)
+{
+    p_adc->ADC_MR |= (resolution<<4) & ADC_MR_LOWRES;
+}
+
+/**
+ * \brief Configures conversion trigger and free run mode.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param trigger  Conversion trigger.
+ */
+void adc_configure_trigger(Adc *p_adc, adc_trigger_t trigger)
+{
+    p_adc->ADC_MR |=  trigger;
+}
+/**
+ * \brief Configures ADC power saving mode.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param uc_sleep  ADC_MR_SLEEP_NORMAL keeps the ADC Core and reference voltage circuitry ON between conversions
+ *                  ADC_MR_SLEEP_SLEEP keeps the ADC Core and reference voltage circuitry OFF between conversions
+ * \param uc_offmode  0 Standby Mode (if Sleep Bit = 1)
+ *                             1 Off Mode
+ */
+void adc_configure_power_save(Adc *p_adc, uint8_t uc_sleep, uint8_t uc_offmode)
+{
+    p_adc->ADC_MR |= ((uc_sleep<<5) & ADC_MR_SLEEP) ;
+}
+
+/**
+ * \brief Configures ADC timing.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param ul_sh  ADC sample and hold time = uc_sh / ADC clock.
+ */
+void adc_configure_timing(Adc *p_adc, uint32_t ul_sh)
+{
+     p_adc->ADC_MR |= ADC_MR_SHTIM( ul_sh ) ;
+}
+
+/**
+ * \brief Starts analog-to-digital conversion.
+ *
+ * \note  If one of the hardware event is selected as ADC trigger, this function can NOT start analog to digital conversion.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ */
+void adc_start(Adc *p_adc)
+{
+    p_adc->ADC_CR = ADC_CR_START;
+}
+
+/**
+ * \brief Stop analog-to-digital conversion.
+ * \param p_adc  Pointer to an ADC instance.
+ */
+void adc_stop(Adc *p_adc)
+{
+    p_adc->ADC_CR = ADC_CR_SWRST;
+}
+/**
+ * \brief Enables the specified ADC channel.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param adc_ch  ADC channel number.
+ */
+void adc_enable_channel(Adc *p_adc, adc_channel_num_t adc_ch)
+{
+    p_adc->ADC_CHER = 1 << adc_ch;
+}
+
+/**
+ * \brief Disables the specified ADC channel.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param adc_ch  ADC channel number.
+ */
+void adc_disable_channel(Adc *p_adc, adc_channel_num_t adc_ch)
+{
+    p_adc->ADC_CHDR = 1 << adc_ch;
+}
+
+/**
+ * \brief Reads the ADC channel status.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param adc_ch  ADC channel number.
+ *
+ * \retval 1 means the specified channel is enabled.
+ *         0 means the specified channel is disabled.
+ */
+uint32_t adc_get_channel_status(Adc *p_adc, adc_channel_num_t adc_ch)
+{
+    return p_adc->ADC_CHSR & (1 << adc_ch);
+}
+
+/**
+ * \brief Reads the ADC status.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ * \retval ADC status register content.
+ */
+uint32_t adc_get_status(Adc *p_adc)
+{
+    return p_adc->ADC_SR;
+}
+
+/**
+ * \brief Reads the ADC result data of the specified channel.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param adc_ch  ADC channel number.
+ *
+ * \retval ADC data of the specified channel.
+ */
+uint32_t adc_get_value(Adc *p_adc, adc_channel_num_t adc_ch)
+{
+    uint32_t dwData = 0;
+
+    if ( 15 >= adc_ch )
+    {
+        dwData=*(p_adc->ADC_CDR+adc_ch) ;
+    }
+
+    return dwData ;
+}
+
+/**
+ * \brief Reads the last ADC result data.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ * \retval ADC data.
+ */
+uint32_t adc_get_latest_value(Adc *p_adc)
+{
+    return p_adc->ADC_LCDR;
+}
+
+/**
+ * \brief Returns the actual ADC clock.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param ul_mck  Main clock of the device (value in Hz).
+ *
+ * \retval 0  The actual ADC clock (value in Hz).
+ */
+uint32_t adc_get_actual_adc_clock(Adc *p_adc, uint32_t  ul_mck)
+{
+    uint32_t ul_adcfreq;
+    uint32_t ul_prescal;
+   
+    /* ADCClock = MCK / ( (PRESCAL+1) * 2 ) */
+    ul_prescal = (( p_adc->ADC_MR & ADC_MR_PRESCAL_Msk) >> ADC_MR_PRESCAL_Pos);
+    ul_adcfreq = ul_mck / ((ul_prescal+1)*2); 
+    return ul_adcfreq;	
+}
+
+/**
+ * \brief Enables ADC interrupt(s).
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param dw_source  Interrupt(s) to be enabled.
+ */
+void adc_enable_interrupt(Adc *p_adc, uint32_t ul_source)
+{
+    p_adc->ADC_IER = ul_source;
+}
+
+/**
+ * \brief Disables ADC interrupt(s).
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param dw_source  Interrupt(s) to be disabled.
+ */
+void adc_disable_interrupt(Adc *p_adc, uint32_t ul_source)
+{
+    p_adc->ADC_IDR = ul_source;
+}
+
+/**
+ * \brief Reads ADC interrupt mask.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ * \retval ADC interrupt status.
+ */
+ uint32_t adc_get_interrupt_status(Adc *p_adc)
+{
+    return p_adc->ADC_SR ;
+}
+
+/** \brief Read ADC interrupt mask.
+ *
+ *  \param p_uart pointer to a UART instance.
+ *
+ *  \return The interrupt mask value.
+ */
+uint32_t adc_get_interrupt_mask(Adc *p_adc)
+{
+	return p_adc->ADC_IMR;
+}
+
+/**
+ * \brief Reads overrun status.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ * \retval ADC overrun status.
+ */
+uint32_t adc_check_ovr(Adc *p_adc,adc_channel_num_t adc_ch)
+{
+    return p_adc->ADC_SR & (0x01u << (adc_ch+8));
+}
+
+/**
+ * \brief Gets PDC registers base address.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ * \retval PDC registers base for PDC driver to access.
+ */
+Pdc *adc_get_pdc_base(Adc *p_adc)
+{
+    return PDC_ADC;
+}
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+/**INDENT-ON**/
+/// @endcond
+
+#endif /* SAM3U */
diff --git a/hardware/sam/system/libsam/source/adc12_sam3u.c b/hardware/sam/system/libsam/source/adc12_sam3u.c
new file mode 100644
index 000000000..2ca25bf7d
--- /dev/null
+++ b/hardware/sam/system/libsam/source/adc12_sam3u.c
@@ -0,0 +1,379 @@
+/*! \file *********************************************************************
+ *
+ * \brief API for SAM3 Analog-to-Digital Converter (ADC/ADC12B) controller.
+ *
+ * ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * - Compiler:           IAR EWARM and CodeSourcery GCC for ARM
+ * - Supported devices:  All SAM devices with a Analog-to-Digital Converter can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.com/
+ *
+ *******************************************************************************/
+
+#include "../chip.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+/**INDENT-ON**/
+/// @endcond
+
+#if SAM3U
+
+/**
+ * \brief Initializes the given ADC with the specified ADC clock and startup time.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param dw_mck  Main clock of the device (value in Hz).
+ * \param dw_adc_clock  Analog-to-Digital conversion clock (value in Hz).
+ * \param ul_startuptime  ADC start up time value(value in us). Please refer to the product datasheet for details.
+ * \param ul_offmode_startuptime  ADC off mode startup Time value(value in us). Please refer to the product datasheet for details.
+ *
+ * \retval 0  The initialization operation succeeds.
+ * \retval others  The initialization operation fails.
+ */
+uint32_t adc12_init(Adc12b *p_adc, uint32_t ul_mck, uint32_t ul_adc_clock, uint32_t ul_startuptime, uint32_t ul_offmode_startuptime)
+{
+    p_adc->ADC12B_CR = ADC12B_CR_SWRST;	
+	
+     /* Reset Mode Register */
+    p_adc->ADC12B_MR = 0;
+	 
+     /* Reset PDC transfer */
+    p_adc->ADC12B_PTCR = (ADC12B_PTCR_RXTDIS | ADC12B_PTCR_TXTDIS);
+    p_adc->ADC12B_RCR = 0;
+    p_adc->ADC12B_RNCR = 0;
+    p_adc->ADC12B_TCR = 0;
+    p_adc->ADC12B_TNCR = 0;		
+    uint32_t prescal = ul_mck/(2 * ul_adc_clock) - 1;
+    // check for rounding errors
+    if ( (ul_mck/((prescal+1)*2)) > ul_adc_clock ) {
+    	prescal++;
+    	ul_adc_clock = ul_mck/((prescal+1)*2);
+    }
+    uint32_t startup = ((ul_adc_clock/1000000) * ul_startuptime / 8) - 1;
+    p_adc->ADC12B_MR |= ADC12B_MR_PRESCAL(prescal) | ADC12B_MR_STARTUP(startup);
+
+    uint32_t offmode = ((ul_adc_clock/1000000) * ul_offmode_startuptime / 8) - 1;
+    p_adc->ADC12B_EMR |= ADC12B_EMR_OFF_MODE_STARTUP_TIME(offmode);
+    return 0;	
+}
+/**
+ * \brief Configures conversion resolution.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param resolution  ADC resolution.
+ */
+void adc12_set_resolution(Adc12b *p_adc, adc_resolution_t resolution)
+{
+    p_adc->ADC12B_MR |= (resolution<<4) & ADC12B_MR_LOWRES;
+}
+/**
+ * \brief Configures conversion trigger and free run mode.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param trigger  Conversion trigger.
+ */
+void adc12_configure_trigger(Adc12b *p_adc, adc_trigger_t trigger)
+{
+    p_adc->ADC12B_MR |=  trigger;
+}
+/**
+ * \brief Configures ADC power saving mode.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param uc_sleep  ADC_MR_SLEEP_NORMAL keeps the ADC Core and reference voltage circuitry ON between conversions
+ *                  ADC_MR_SLEEP_SLEEP keeps the ADC Core and reference voltage circuitry OFF between conversions
+ * \param uc_offmode  0 Standby Mode (if Sleep Bit = 1)
+ *                             1 Off Mode
+ */
+void adc12_configure_power_save(Adc12b *p_adc, uint8_t uc_sleep, uint8_t uc_offmode)
+{
+    p_adc->ADC12B_MR |= ((uc_sleep<<5) & ADC12B_MR_SLEEP) ;
+    p_adc->ADC12B_EMR |= uc_offmode;	
+}
+/**
+ * \brief Configures ADC timing.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param ul_sh  ADC sample and hold time = uc_sh / ADC clock.
+ *
+ */
+void adc12_configure_timing(Adc12b *p_adc, uint32_t ul_sh)
+{
+     p_adc->ADC12B_MR |= ADC12B_MR_SHTIM( ul_sh ) ;
+}
+/**
+ * \brief Starts analog-to-digital conversion.
+ *
+ * \note  If one of the hardware event is selected as ADC trigger, this function can NOT start analog to digital conversion.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ */
+ 
+void adc12_start(Adc12b *p_adc)
+{
+    p_adc->ADC12B_CR = ADC12B_CR_START;
+}
+/**
+ * \brief Stop analog-to-digital conversion.
+ * \param p_adc  Pointer to an ADC instance.
+ */
+void adc12_stop(Adc12b *p_adc)
+{
+    p_adc->ADC12B_CR = ADC12B_CR_SWRST;
+}
+/**
+ * \brief Enables the specified ADC channel.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param adc_ch  ADC channel number.
+ */
+void adc12_enable_channel(Adc12b *p_adc, adc_channel_num_t adc_ch)
+{
+    p_adc->ADC12B_CHER = 1 << adc_ch;
+}
+
+/**
+ * \brief Disables the specified ADC channel.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param adc_ch  ADC channel number.
+ */
+void adc12_disable_channel(Adc12b *p_adc, adc_channel_num_t adc_ch)
+{
+    p_adc->ADC12B_CHDR = 1 << adc_ch;
+}
+
+/**
+ * \brief Reads the ADC channel status.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param adc_ch  ADC channel number.
+ *
+ * \retval 1 means the specified channel is enabled.
+ *         0 means the specified channel is disabled.
+ */
+uint32_t adc12_get_channel_status(Adc12b *p_adc, adc_channel_num_t adc_ch)
+{
+    return p_adc->ADC12B_CHSR & (1 << adc_ch);
+}
+
+/**
+ * \brief Reads the ADC status.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ * \retval ADC status register content.
+ */
+uint32_t adc12_get_status(Adc12b *p_adc)
+{
+    return p_adc->ADC12B_SR;
+}
+
+/**
+ * \brief Reads the ADC result data of the specified channel.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param adc_ch  ADC channel number.
+ *
+ * \retval ADC data of the specified channel.
+ */
+uint32_t adc12_get_value(Adc12b *p_adc, adc_channel_num_t adc_ch)
+{
+    uint32_t dwData = 0;
+
+    if ( 15 >= adc_ch )
+    {
+        dwData=*(p_adc->ADC12B_CDR+adc_ch) ;
+    }
+
+    return dwData ;
+}
+
+/**
+ * \brief Reads the last ADC result data.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ * \retval ADC data.
+ */
+uint32_t adc12_get_latest_value(Adc12b *p_adc)
+{
+    return p_adc->ADC12B_LCDR;
+}
+/**
+ * \brief Enables differential input for all channels.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ */
+ void adc12_enable_differential_input(Adc12b *p_adc)
+{
+    p_adc->ADC12B_ACR |= (0x01u << 16);
+}
+
+/**
+ * \brief Disables differential input for the specified channel.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ */
+void adc12_disable_differential_input(Adc12b*p_adc)
+{
+    p_adc->ADC12B_ACR &= (0x01u << 16);
+}
+
+/**
+ * \brief Enables analog signal offset for the specified channel.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ */
+void adc12_enable_input_offset(Adc12b *p_adc)
+{
+    p_adc->ADC12B_ACR |= (0x01u << 17);
+}
+
+/**
+ * \brief Disables analog signal offset for the specified channel.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ */
+void adc12_disable_input_offset(Adc12b *p_adc)
+{
+    p_adc->ADC12B_ACR &= (0x01u << 17);
+}
+/**
+ * \brief Configures input gain for the specified channel.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param gain  Gain value for the input.
+ */
+void adc12_set_input_gain(Adc12b *p_adc, adc_gainvalue_t gain)
+{
+    p_adc->ADC12B_ACR |= (0x03u & gain);  
+}
+uint32_t adc12_get_actual_adc_clock(Adc12b *p_adc, uint32_t  ul_mck)
+{
+    uint32_t ul_adcfreq;
+    uint32_t ul_prescal;
+   
+    /* ADCClock = MCK / ( (PRESCAL+1) * 2 ) */
+    ul_prescal = (( p_adc->ADC12B_MR & ADC12B_MR_PRESCAL_Msk) >> ADC12B_MR_PRESCAL_Pos);
+    ul_adcfreq = ul_mck / ((ul_prescal+1)*2); 
+    return ul_adcfreq;	
+}
+/**
+ * \brief Enables ADC interrupt(s).
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param dw_source  Interrupt(s) to be enabled.
+ */
+void adc12_enable_interrupt(Adc12b *p_adc, uint32_t ul_source)
+{
+    p_adc->ADC12B_IER = ul_source;
+}
+
+/**
+ * \brief Disables ADC interrupt(s).
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param dw_source  Interrupt(s) to be disabled.
+ */
+void adc12_disable_interrupt(Adc12b *p_adc, uint32_t ul_source)
+{
+    p_adc->ADC12B_IDR = ul_source;
+}
+/** \brief Read ADC interrupt mask.
+ *
+ *  \param p_uart pointer to a UART instance.
+ *
+ *  \return The interrupt mask value.
+ */
+uint32_t adc12_get_interrupt_mask(Adc12b *p_adc)
+{
+	return p_adc->ADC12B_IMR;
+}
+/**
+ * \brief Reads ADC interrupt status.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ * \retval ADC interrupt status.
+ */
+uint32_t adc12_get_interrupt_status(Adc12b *p_adc)
+{
+    return p_adc->ADC12B_SR ;
+}
+/**
+ * \brief Reads overrun status.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ * \retval ADC overrun status.
+ */
+uint32_t adc12_check_ovr(Adc12b *p_adc,adc_channel_num_t adc_ch)
+{
+    return p_adc->ADC12B_SR & (0x01u << (adc_ch+8));
+}
+/**
+ * \brief Adapts performance versus power consumption.
+ *
+ * \note Please refer to ADC Characteristics in the product datasheet for the details.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param ibctl  ADC Bias current control.
+ */
+void adc12_set_bias_current(Adc12b *p_adc, uint8_t uc_ibctl)
+{
+     p_adc->ADC12B_ACR |= ADC12B_ACR_IBCTL(uc_ibctl);
+}
+/**
+ * \brief Gets PDC registers base address.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ * \retval PDC registers base for PDC driver to access.
+ */
+Pdc *adc12_get_pdc_base(Adc12b *p_adc)
+{
+    return PDC_ADC12B;
+}
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+/**INDENT-ON**/
+/// @endcond
+
+#endif /* SAM3U */
diff --git a/hardware/sam/system/libsam/source/adc_sam3snxa.c b/hardware/sam/system/libsam/source/adc_sam3snxa.c
new file mode 100644
index 000000000..f93b57304
--- /dev/null
+++ b/hardware/sam/system/libsam/source/adc_sam3snxa.c
@@ -0,0 +1,806 @@
+/*! \file *********************************************************************
+ *
+ * \brief API for SAM3 Analog-to-Digital Converter (ADC/ADC12B) controller.
+ *
+ * ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * - Compiler:           IAR EWARM and CodeSourcery GCC for ARM
+ * - Supported devices:  All SAM devices with a Analog-to-Digital Converter can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.com/
+ *
+ *******************************************************************************/
+
+#include "../chip.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#if SAM3S || SAM3N || SAM3XA
+
+/**
+ * \brief Initializes the given ADC with the specified ADC clock and startup time.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param dw_mck  Main clock of the device (value in Hz).
+ * \param dw_adc_clock  Analog-to-Digital conversion clock (value in Hz).
+ * \param uc_startup  ADC start up time. Please refer to the product datasheet for details.
+ *
+ * \retval 0  The initialization operation succeeds.
+ * \retval others  The initialization operation fails.
+ */
+uint32_t adc_init(Adc *p_adc, uint32_t ul_mck, uint32_t ul_adc_clock, uint8_t uc_startup)
+{
+    uint32_t ul_prescal;
+	
+    /*  Reset the controller */	
+    p_adc->ADC_CR = ADC_CR_SWRST;
+	
+    /* Reset Mode Register */
+    p_adc->ADC_MR = 0;
+   
+    /* Reset PDC transfer */
+    p_adc->ADC_PTCR = (ADC_PTCR_RXTDIS | ADC_PTCR_TXTDIS);
+    p_adc->ADC_RCR = 0;
+    p_adc->ADC_RNCR = 0;
+    p_adc->ADC_TCR = 0;
+    p_adc->ADC_TNCR = 0;	
+	
+    ul_prescal = ul_mck/(2 * ul_adc_clock) - 1;
+    p_adc->ADC_MR |= ADC_MR_PRESCAL( ul_prescal ) | ( (uc_startup<ADC_MR |= (resolution<<4) & ADC_MR_LOWRES;
+}
+ 
+/**
+ * \brief Configures conversion trigger and free run mode.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param trigger  Conversion trigger.
+ * \param uc_freerun  ADC_MR_FREERUN_ON enables freerun mode
+ *                    ADC_MR_FREERUN_OFF disables freerun mode
+ *
+ */
+void adc_configure_trigger(Adc *p_adc, adc_trigger_t trigger, uint8_t uc_freerun)
+{
+    p_adc->ADC_MR |=  trigger | ((uc_freerun<<7) & ADC_MR_FREERUN);
+}
+
+/**
+ * \brief Configures ADC power saving mode.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param uc_sleep  ADC_MR_SLEEP_NORMAL keeps the ADC Core and reference voltage circuitry ON between conversions
+ *                  ADC_MR_SLEEP_SLEEP keeps the ADC Core and reference voltage circuitry OFF between conversions
+ * \param uc_fwup  ADC_MR_FWUP_OFF configures sleep mode as uc_sleep setting
+ *                 ADC_MR_FWUP_ON keeps voltage reference ON and ADC Core OFF between conversions
+ *
+ */
+void adc_configure_power_save(Adc *p_adc, uint8_t uc_sleep, uint8_t uc_fwup)
+{
+    p_adc->ADC_MR |= ( ((uc_sleep<<5) & ADC_MR_SLEEP) | ((uc_fwup<<6) & ADC_MR_FWUP) );
+}
+
+/**
+ * \brief Configures conversion sequence.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param ch_list  Channel sequence list.
+ * \param number  Number of channels in the list.
+ *
+ */
+void adc_configure_sequence(Adc *p_adc, adc_channel_num_t ch_list[], uint8_t uc_num)
+{
+    uint8_t uc_counter;
+    if(uc_num < 8) 	
+    {
+        for(uc_counter=0;uc_counter < uc_num;uc_counter++)
+	  {
+	        p_adc->ADC_SEQR1 |= ch_list[uc_counter] << (4*uc_counter);
+	  }
+    }
+    else
+    {
+      for(uc_counter=0;uc_counter < 8;uc_counter++)
+	  {
+	        p_adc->ADC_SEQR1 |= ch_list[uc_counter] << (4*uc_counter);
+	  }
+	  for(uc_counter=0;uc_counter < uc_num-8;uc_counter++)
+	  {
+	        p_adc->ADC_SEQR2 |= ch_list[uc_counter] << (4*uc_counter);
+	  }	
+    }
+}
+
+#if SAM3S ||  SAM3XA
+/**
+ * \brief Configures ADC timing.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param uc_tracking  ADC tracking time = uc_tracking / ADC clock.
+ * \param uc_settling  Analog settling time = (uc_settling + 1) / ADC clock.
+ * \param uc_transfer  Data transfer time = (uc_transfer * 2 + 3) / ADC clock.
+ *
+ */
+void adc_configure_timing(Adc *p_adc, uint8_t uc_tracking, adc_settling_time_t settling, uint8_t uc_transfer)
+{
+     p_adc->ADC_MR |= ADC_MR_TRANSFER( uc_transfer )
+                 | settling
+                 | ADC_MR_TRACKTIM( uc_tracking ) ;
+}
+#elif  SAM3N 
+/**
+ * \brief Configures ADC timing.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param uc_tracking  ADC tracking time = uc_tracking / ADC clock.
+ *
+ */
+void adc_configure_timing(Adc *p_adc, uint8_t uc_tracking)
+{
+     p_adc->ADC_MR |= ADC_MR_TRACKTIM( uc_tracking ) ;
+}
+#endif
+
+#if SAM3S || SAM3XA
+/**
+ * \brief enable analog change.
+ *
+ * note  it allows different analog settings for each channel,
+ *
+ * \param pAdc   Pointer to an Adc instance.
+ */
+void adc_enable_anch( Adc *pAdc )
+{
+    pAdc->ADC_MR |=  ADC_MR_ANACH;
+}
+#endif
+
+#if SAM3S || SAM3XA
+/**
+ * \brief disable analog change.
+ * 
+ * note DIFF0, GAIN0 and OFF0 are used for all channels.
+ *
+ * \param pAdc   Pointer to an Adc instance.
+ */
+void adc_disable_anch( Adc *pAdc )
+{
+    pAdc->ADC_MR &= ~ADC_MR_ANACH;
+}
+#endif
+
+/**
+ * \brief Starts analog-to-digital conversion.
+ *
+ * \note  If one of the hardware event is selected as ADC trigger, this function can NOT start analog to digital conversion.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ */
+ 
+void adc_start(Adc *p_adc)
+{
+    p_adc->ADC_CR = ADC_CR_START;
+}
+
+/**
+ * \brief Stop analog-to-digital conversion.
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ */
+void adc_stop(Adc *p_adc)
+{
+    p_adc->ADC_CR = ADC_CR_SWRST;
+}
+
+/**
+ * \brief Enables the specified ADC channel.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param adc_ch  ADC channel number.
+ *
+ */
+void adc_enable_channel(Adc *p_adc, adc_channel_num_t adc_ch)
+{
+    p_adc->ADC_CHER = 1 << adc_ch;
+}
+
+/**
+ * \brief Disables the specified ADC channel.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param adc_ch  ADC channel number.
+ *
+ */
+void adc_disable_channel(Adc *p_adc, adc_channel_num_t adc_ch)
+{
+    p_adc->ADC_CHDR = 1 << adc_ch;
+}
+
+/**
+ * \brief Reads the ADC channel status.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param adc_ch  ADC channel number.
+ *
+ * \retval 1 means the specified channel is enabled.
+ *         0 means the specified channel is disabled.
+ */
+uint32_t adc_get_channnel_status(Adc *p_adc, adc_channel_num_t adc_ch)
+{
+    return p_adc->ADC_CHSR & (1 << adc_ch);
+}
+
+/**
+ * \brief Reads the ADC status.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ * \retval ADC status register content.
+ */
+uint32_t adc_get_status(Adc *p_adc)
+{
+    return p_adc->ADC_ISR;
+}
+
+/**
+ * \brief Reads the ADC overrun status.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ * \retval ADC overrun status register content.
+ */
+uint32_t adc_get_overrun_status(Adc *p_adc)
+{
+    return p_adc->ADC_OVER;
+}
+
+/**
+ * \brief Reads the ADC result data of the specified channel.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param adc_ch  ADC channel number.
+ *
+ * \retval ADC data of the specified channel.
+ */
+uint32_t adc_get_value(Adc *p_adc, adc_channel_num_t adc_ch)
+{
+    uint32_t dwData = 0;
+
+    if ( 15 >= adc_ch )
+    {
+        dwData=*(p_adc->ADC_CDR+adc_ch) ;
+    }
+
+    return dwData ;
+}
+
+/**
+ * \brief Reads the last ADC result data.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ * \retval ADC data.
+ */
+uint32_t adc_get_latest_value(Adc *p_adc)
+{
+    return p_adc->ADC_LCDR;
+}
+
+/**
+ * \brief Enables TAG option so that the number of the last converted channel can be indicated.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ */
+void adc_enable_tag(Adc *p_adc)
+{
+    p_adc->ADC_EMR |= ADC_EMR_TAG;
+}
+
+/**
+ * \brief Disables TAG option.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ */
+void adc_disable_tag(Adc *p_adc)
+{
+    p_adc->ADC_EMR &= ~ADC_EMR_TAG;
+}
+
+/**
+ * \brief Indicates the last converted channel.
+ *
+ * \note If TAG option is NOT enabled before, an incorrect channel number is returned.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ * \retval The last converted channel number.
+ */
+adc_channel_num_t adc_get_tag(Adc *p_adc)
+{
+    return  (p_adc->ADC_LCDR & ADC_LCDR_CHNB_Msk) >> ADC_LCDR_CHNB_Pos;
+}
+
+/**
+ * \brief Enables conversion sequencer.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ */
+void adc_start_sequencer(Adc *p_adc)
+{
+    p_adc->ADC_MR |= ADC_MR_USEQ;
+}
+
+/**
+ * \brief Disables conversion sequencer.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ */
+void adc_stop_sequencer(Adc *p_adc)
+{
+    p_adc->ADC_MR &= ~ADC_MR_USEQ; 
+}
+
+/**
+ * \brief Configures comparsion mode.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param mode  ADC comparsion mode.
+ *
+ */
+void adc_set_comparison_mode(Adc *p_adc, uint8_t uc_mode)
+{
+    p_adc->ADC_EMR &= (uint32_t)~(ADC_EMR_CMPMODE_Msk);
+    p_adc->ADC_EMR |= (uc_mode & ADC_EMR_CMPMODE_Msk);
+}
+
+/**
+ * \brief get comparsion mode.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param mode  ADC comparsion mode.
+ *
+ * \retval compare mode value.
+ */
+uint32_t adc_get_comparison_mode(Adc *p_adc)
+{
+    return p_adc->ADC_EMR & ADC_EMR_CMPMODE_Msk;
+}
+
+/**
+ * \brief Configures ADC compare window.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param w_low_threshold  Low threshold of compare window.
+ * \param w_high_threshold  High threshold of compare window.
+ *
+ */
+void adc_set_comparsion_window(Adc *p_adc, uint16_t us_low_threshold, uint16_t us_high_threshold)
+{
+    p_adc->ADC_CWR = ADC_CWR_LOWTHRES(us_low_threshold) | ADC_CWR_HIGHTHRES(us_high_threshold);
+}
+
+/**
+ * \brief Configures comparison selected channel.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param channel  Comparison selected channel.
+ *
+ */
+void adc_set_comparison_channel(Adc *p_adc, adc_channel_num_t channel)
+{
+    if ( channel < 16 )
+    {
+        p_adc->ADC_EMR &= (uint32_t)~(ADC_EMR_CMPALL);
+        p_adc->ADC_EMR &= (uint32_t)~(ADC_EMR_CMPSEL_Msk);
+        p_adc->ADC_EMR |= (channel << ADC_EMR_CMPSEL_Pos);
+    }
+    else
+    {  
+        p_adc->ADC_EMR |= ADC_EMR_CMPALL;
+    }
+}
+
+#if SAM3S || SAM3XA
+/**
+ * \brief Enables differential input for the specified channel.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param channel  Channel number.
+ *
+ */
+ void adc_enable_differential_input(Adc *p_adc, adc_channel_num_t channel)
+{
+    p_adc->ADC_COR |= 0x01u << (16+ channel);
+}
+
+/**
+ * \brief Disables differential input for the specified channel.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param channel  Channel number.
+ *
+ */
+void adc_disable_differential_input(Adc *p_adc, adc_channel_num_t channel)
+{
+    uint32_t ul_temp;
+    ul_temp = p_adc->ADC_COR;	
+    p_adc->ADC_COR &= 0xfffeffffu << channel;
+    p_adc->ADC_COR |= ul_temp;	
+}
+
+/**
+ * \brief Enables analog signal offset for the specified channel.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param channel  Channel number.
+ *
+ */
+void adc_enable_input_offset(Adc *p_adc, adc_channel_num_t channel)
+{
+    p_adc->ADC_COR |= 0x01u <<  channel;
+}
+
+/**
+ * \brief Disables analog signal offset for the specified channel.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param channel  Channel number.
+ *
+ */
+void adc_disable_input_offset(Adc *p_adc, adc_channel_num_t channel)
+{
+    uint32_t ul_temp;
+    ul_temp = p_adc->ADC_COR;
+    p_adc->ADC_COR &= (0xfffffffeu << channel);
+    p_adc->ADC_COR |= ul_temp;	
+}
+
+/**
+ * \brief Configures input gain for the specified channel.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param channel  Channel number.
+ * \param gain  Gain value for the input.
+ *
+ */
+void adc_set_input_gain(Adc *p_adc, adc_channel_num_t channel, adc_gainvalue_t gain)
+{
+    p_adc->ADC_CGR |= (0x03u << (2*channel)) & (gain << (2*channel));
+}
+#endif /* SAM3S || SAM3XA */
+
+#if SAM3S8 || SAM3SD8
+/**
+ * \brief set adc auto calibration mode.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ */
+void adc_set_calibmode(Adc *p_adc)
+{
+    p_adc->ADC_CR |= ADC_CR_AUTOCAL;
+}
+#endif /* SAM3S8 || SAM3SD8 */
+
+/**
+ * \brief Returns the actual ADC clock.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param ul_mck  Main clock of the device (value in Hz).
+ *
+ * \retval 0  The actual ADC clock (value in Hz).
+ */
+uint32_t adc_get_actual_adc_clock(Adc *p_adc, uint32_t  ul_mck)
+{
+    uint32_t ul_adcfreq;
+    uint32_t ul_prescal;
+   
+    /* ADCClock = MCK / ( (PRESCAL+1) * 2 ) */
+    ul_prescal = (( p_adc->ADC_MR & ADC_MR_PRESCAL_Msk) >> ADC_MR_PRESCAL_Pos);
+    ul_adcfreq = ul_mck / ((ul_prescal+1)*2); 
+    return ul_adcfreq;	
+}
+
+/**
+ * \brief Enables ADC interrupt(s).
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param dw_source  Interrupt(s) to be enabled.
+ *
+ */
+void adc_enable_interrupt(Adc *p_adc, uint32_t ul_source)
+{
+    p_adc->ADC_IER = ul_source;
+}
+
+/**
+ * \brief Disables ADC interrupt(s).
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param dw_source  Interrupt(s) to be disabled.
+ *
+ */
+void adc_disable_interrupt(Adc *p_adc, uint32_t ul_source)
+{
+    p_adc->ADC_IDR = ul_source;
+}
+
+/**
+ * \brief Reads ADC interrupt status.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ * \retval ADC interrupt status.
+ */
+uint32_t adc_get_interrupt_status(Adc *p_adc)
+{
+    return p_adc->ADC_ISR ;
+}
+
+/** \brief Read ADC interrupt mask.
+ *
+ *  \param p_uart pointer to a UART instance.
+ *
+ *  \return The interrupt mask value.
+ */
+uint32_t adc_get_interrupt_mask(Adc *p_adc)
+{
+	return p_adc->ADC_IMR;
+}
+
+/**
+ * \brief Reads overrun status.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ * \retval ADC overrun status.
+ */
+uint32_t adc_check_ovr(Adc *p_adc,adc_channel_num_t adc_ch)
+{
+    return p_adc->ADC_OVER & (0x01u << adc_ch);
+}
+
+#if SAM3S || SAM3XA
+/**
+ * \brief Adapts performance versus power consumption.
+ *
+ * \note Please refer to ADC Characteristics in the product datasheet for the details.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param ibctl  ADC Bias current control.
+ *
+ */
+void adc_set_bias_current(Adc *p_adc, uint8_t uc_ibctl)
+{
+     p_adc->ADC_ACR |= ADC_ACR_IBCTL(uc_ibctl);
+}
+#endif
+
+#if SAM3S ||  SAM3XA
+/**
+ * \brief turn on temperature sensor.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ */
+void adc_enable_ts(Adc *p_adc)
+{
+     p_adc->ADC_ACR |= ADC_ACR_TSON;
+}
+#endif
+
+#if SAM3S ||  SAM3XA
+/**
+ * \brief turn off temperature sensor.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ */
+void adc_disable_ts(Adc *p_adc)
+{
+     p_adc->ADC_ACR &= ~ADC_ACR_TSON;
+}
+#endif
+
+/**
+ * \brief Enables or disables write protection of ADC registers.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param dw_eanble  1 to eanble, 0 to disable.
+ */
+void adc_set_writeprotect(Adc *p_adc, uint32_t ul_enable)
+{
+    p_adc->ADC_WPMR |= ADC_WPMR_WPKEY(ul_enable);
+}
+
+/**
+ * \brief Indicates write protect status.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ * \return 0 if the peripheral is not protected, or 16-bit Write Protect Violation Status.
+ */
+uint32_t adc_get_writeprotect_status(Adc *p_adc)
+{
+    return p_adc->ADC_WPSR & ADC_WPSR_WPVS;
+}
+
+/**
+ * \brief calcul_startup
+ */
+static uint32_t calcul_startup( uint32_t ul_startup )
+{
+    uint32_t ul_startup_value=0;
+
+    if( ul_startup == 0 )
+        ul_startup_value = 0;
+    else if( ul_startup == 1 )
+        ul_startup_value = 8;
+    else if( ul_startup == 2 )
+        ul_startup_value = 16;
+    else if( ul_startup == 3 )
+        ul_startup_value = 24;
+    else if( ul_startup == 4 )
+        ul_startup_value = 64;
+    else if( ul_startup == 5 )
+        ul_startup_value = 80;
+    else if( ul_startup == 6 )
+        ul_startup_value = 96;
+    else if( ul_startup == 7 )
+        ul_startup_value = 112;
+    else if( ul_startup == 8 )
+        ul_startup_value = 512;
+    else if( ul_startup == 9 )
+        ul_startup_value = 576;
+    else if( ul_startup == 10 )
+        ul_startup_value = 640;
+    else if( ul_startup == 11 )
+        ul_startup_value = 704;
+    else if( ul_startup == 12 )
+        ul_startup_value = 768;
+    else if( ul_startup == 13 )
+        ul_startup_value = 832;
+    else if( ul_startup == 14 )
+        ul_startup_value = 896;
+    else if( ul_startup == 15 )
+        ul_startup_value = 960;
+
+    return ul_startup_value;
+}
+
+#if 0
+/**
+ * \brief Checks ADC configurations.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ * \param dw_mck  Main clock of the device (value in Hz).
+ */
+void adc_check(Adc* p_adc, uint32_t ul_mck)
+{
+    uint32_t ul_adcfreq;
+    uint32_t ul_prescal;
+    uint32_t ul_startup;
+
+    /* ADCClock = MCK / ( (PRESCAL+1) * 2 ) */
+    ul_prescal = (( p_adc->ADC_MR & ADC_MR_PRESCAL_Msk) >> ADC_MR_PRESCAL_Pos);
+    ul_adcfreq = ul_mck / ((ul_prescal+1)*2);
+    printf("ADC clock frequency =  %d Hz\r\n", (int)ul_adcfreq );
+
+    if( ul_adcfreq < ADC_FREQ_MIN )
+    {
+        printf("adc frequency too low (out of specification: %d Hz)\r\n", (int)ADC_FREQ_MIN);
+    }
+    if( ul_adcfreq > ADC_FREQ_MAX )
+    {
+        printf("adc frequency too high (out of specification: %d Hz)\r\n", (int)ADC_FREQ_MAX);
+    }
+
+    ul_startup = (( p_adc->ADC_MR & ADC_MR_STARTUP_Msk) >> ADC_MR_STARTUP_Pos);
+    if( !(p_adc->ADC_MR & ADC_MR_SLEEP_SLEEP) )
+    {
+        /* 40ms */
+        if( ADC_STARTUP_NORM * ul_adcfreq / 1000000 > calcul_startup(ul_startup) )
+        {
+            printf("Startup time too small: %d, programmed: %d\r\n", (int)(ADC_STARTUP_NORM * ul_adcfreq / 1000000), (int)calcul_startup(ul_startup));
+        }
+    }
+    else
+    {
+        if(p_adc->ADC_MR & ADC_MR_FREERUN_ON)
+        {
+            printf("FreeRun forbidden in sleep mode\n\r");
+        }
+        if( !(p_adc->ADC_MR & ADC_MR_FWUP_ON) )
+        {
+            /* Sleep 40ms */
+            if( ADC_STARTUP_NORM * ul_adcfreq / 1000000 > calcul_startup(ul_startup) )
+            {
+                printf("Startup time too small: %d, programmed: %d\r\n", (int)(ADC_STARTUP_NORM * ul_adcfreq / 1000000), (int)(calcul_startup(ul_startup)));
+            }
+        }
+        else
+        {
+            if( p_adc->ADC_MR & ADC_MR_FWUP_ON )
+            {
+                /* Fast Wake Up Sleep Mode: 12ms */
+                if( ADC_STARTUP_FAST * ul_adcfreq / 1000000 > calcul_startup(ul_startup) )
+                {
+                    printf("Startup time too small: %d, programmed: %d\r\n", (int)(ADC_STARTUP_NORM * ul_adcfreq / 1000000), (int)(calcul_startup(ul_startup)));
+                }
+            }
+        }
+    }
+}
+#endif /* 0 */
+
+/**
+ * \brief Gets PDC registers base address.
+ *
+ * \param p_adc  Pointer to an ADC instance.
+ *
+ * \retval PDC registers base for PDC driver to access.
+ */
+Pdc *adc_get_pdc_base(Adc *p_adc)
+{
+    return PDC_ADC;
+}
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif // SAM3S || SAM3N || SAM3XA
+/**INDENT-ON**/
+/// @endcond
+
+#endif /* SAM3S || SAM3N || SAM3XA */
+
diff --git a/hardware/sam/system/libsam/source/pio.c b/hardware/sam/system/libsam/source/pio.c
new file mode 100644
index 000000000..3c0597063
--- /dev/null
+++ b/hardware/sam/system/libsam/source/pio.c
@@ -0,0 +1,386 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \file */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include "chip.h"
+
+/**
+ * \brief Configures Pio pin internal pull-up.
+ *
+ * \param pPio            Pointer to a PIO controller.
+ * \param dwMask          Bitmask of one or more pin(s) to configure.
+ * \param dwPullUpEnable  Indicates if the pin(s) internal pull-up shall be configured.
+ */
+extern void PIO_DisableInterrupt( Pio *pPio, const uint32_t dwMask )
+{
+    /* Disable interrupts on the pin */
+    pPio->PIO_IDR = dwMask ;
+}
+
+/**
+ * \brief Configures Pio pin internal pull-up.
+ *
+ * \param pPio            Pointer to a PIO controller.
+ * \param dwMask          Bitmask of one or more pin(s) to configure.
+ * \param dwPullUpEnable  Indicates if the pin(s) internal pull-up shall be configured.
+ */
+extern void PIO_PullUp( Pio *pPio, const uint32_t dwMask, const uint32_t dwPullUpEnable )
+{
+    /* Enable the pull-up(s) if necessary */
+    if ( dwPullUpEnable )
+    {
+        pPio->PIO_PUER = dwMask ;
+    }
+    else
+    {
+        pPio->PIO_PUDR = dwMask ;
+    }
+}
+
+/**
+ * \brief Configures Glitch or Debouncing filter for input.
+ *
+ * \param pin  Pointer to a Pin instance describing one or more pins.
+ * \param cuttoff  Cutt off frequency for debounce filter.
+ */
+extern void PIO_SetDebounceFilter( Pio* pPio, const uint32_t dwMask, const uint32_t dwCuttOff )
+{
+#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_)
+    pPio->PIO_IFSCER = dwMask ; /* set Debouncing, 0 bit field no effect */
+#elif (defined _SAM3XA_) || (defined _SAM3U_)
+    pPio->PIO_DIFSR = dwMask ; /* set Debouncing, 0 bit field no effect */
+#else
+    #error "The specified chip is not supported."
+#endif
+    pPio->PIO_SCDR = ((32678/(2*(dwCuttOff))) - 1) & 0x3FFF; /* the lowest 14 bits work */
+}
+
+/**
+ * \brief Sets a high output level on all the PIOs defined in the given Pin instance.
+ * This has no immediate effects on PIOs that are not output, but the PIO
+ * controller will memorize the value they are changed to outputs.
+ *
+ * \param pin  Pointer to a Pin instance describing one or more pins.
+ */
+extern void PIO_Set( Pio* pPio, const uint32_t dwMask )
+{
+    pPio->PIO_SODR = dwMask ;
+}
+
+/**
+ * \brief Returns 1 if one or more PIO of the given Pin instance currently have
+ * a high level; otherwise returns 0. This method returns the actual value that
+ * is being read on the pin. To return the supposed output value of a pin, use
+ * PIO_GetOutputDataStatus() instead.
+ *
+ * \param pin  Pointer to a Pin instance describing one or more pins.
+ *
+ * \return 1 if the Pin instance contains at least one PIO that currently has
+ * a high level; otherwise 0.
+ */
+extern uint32_t PIO_Get( Pio* pPio, const EPioType dwType, const uint32_t dwMask )
+{
+    uint32_t dwReg ;
+
+    if ( (dwType == PIO_OUTPUT_0) || (dwType == PIO_OUTPUT_1) )
+    {
+        dwReg = pPio->PIO_ODSR ;
+    }
+    else
+    {
+        dwReg = pPio->PIO_PDSR ;
+    }
+
+    if ( (dwReg & dwMask) == 0 )
+    {
+        return 0 ;
+    }
+    else
+    {
+        return 1 ;
+    }
+}
+
+/**
+ * \brief Sets a low output level on all the PIOs defined in the given Pin instance.
+ * This has no immediate effects on PIOs that are not output, but the PIO
+ * controller will memorize the value they are changed to outputs.
+ *
+ * \param pin  Pointer to a Pin instance describing one or more pins.
+ */
+extern void PIO_Clear( Pio* pPio, const uint32_t dwMask )
+{
+    pPio->PIO_CODR = dwMask ;
+}
+
+/**
+ * \brief Configures one pin of a PIO controller as being controlled by specific peripheral.
+ *
+ * \param pPio    Pointer to a PIO controller.
+ * \param dwType  PIO type.
+ * \param dwMask  Bitmask of one or more pin(s) to configure.
+ */
+extern void PIO_SetPeripheral( Pio* pPio, EPioType dwType, uint32_t dwMask )
+{
+    uint32_t dwSR ;
+
+    /* Disable interrupts on the pin(s) */
+    pPio->PIO_IDR = dwMask ;
+
+    switch ( dwType )
+    {
+        case PIO_PERIPH_A :
+#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_)
+            dwSR = pPio->PIO_ABCDSR[0] ;
+            pPio->PIO_ABCDSR[0] &= (~dwMask & dwSR) ;
+
+            dwSR = pPio->PIO_ABCDSR[1];
+            pPio->PIO_ABCDSR[1] &= (~dwMask & dwSR) ;
+#endif /* (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_) */
+
+#if (defined _SAM3U_) || (defined _SAM3XA_)
+            dwSR = pPio->PIO_ABSR ;
+            pPio->PIO_ABSR &= (~dwMask & dwSR) ;
+#endif /* (defined _SAM3U_) || (defined _SAM3XA_) */
+        break ;
+
+        case PIO_PERIPH_B :
+#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_)
+            dwSR = pPio->PIO_ABCDSR[0] ;
+            pPio->PIO_ABCDSR[0] = (dwMask | dwSR) ;
+
+            dwSR = pPio->PIO_ABCDSR[1] ;
+            pPio->PIO_ABCDSR[1] &= (~dwMask & dwSR) ;
+#endif /* (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_) */
+
+#if (defined _SAM3U_) || (defined _SAM3XA_)
+            dwSR = pPio->PIO_ABSR ;
+            pPio->PIO_ABSR = (dwMask | dwSR) ;
+#endif /* (defined _SAM3U_) || (defined _SAM3XA_) */
+        break ;
+
+#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_)
+        case PIO_PERIPH_C :
+            dwSR = pPio->PIO_ABCDSR[0] ;
+            pPio->PIO_ABCDSR[0] &= (~dwMask & dwSR) ;
+
+            dwSR = pPio->PIO_ABCDSR[1] ;
+            pPio->PIO_ABCDSR[1] = (dwMask | dwSR) ;
+        break ;
+
+        case PIO_PERIPH_D :
+            dwSR = pPio->PIO_ABCDSR[0] ;
+            pPio->PIO_ABCDSR[0] = (dwMask | dwSR) ;
+
+            dwSR = pPio->PIO_ABCDSR[1] ;
+            pPio->PIO_ABCDSR[1] = (dwMask | dwSR) ;
+        break ;
+#endif /* (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_) */
+
+        // other types are invalid in this function
+        case PIO_INPUT :
+        case PIO_OUTPUT_0 :
+        case PIO_OUTPUT_1 :
+        case PIO_NOT_A_PIN :
+        return ;
+    }
+
+    // Remove the pins from under the control of PIO
+    pPio->PIO_PDR = dwMask ;
+}
+
+/**
+ * \brief Configures one or more pin(s) or a PIO controller as inputs. Optionally,
+ * the corresponding internal pull-up(s) and glitch filter(s) can be enabled.
+ *
+ * \param pPio        Pointer to a PIO controller.
+ * \param dwMask      Bitmask indicating which pin(s) to configure as input(s).
+ * \param dwAttribute .
+ */
+extern void PIO_SetInput( Pio* pPio, uint32_t dwMask, uint32_t dwAttribute )
+{
+    PIO_DisableInterrupt( pPio, dwMask ) ;
+    PIO_PullUp( pPio, dwMask, dwAttribute & PIO_PULLUP ) ;
+
+    /* Enable Input Filter if necessary */
+    if ( dwAttribute & (PIO_DEGLITCH | PIO_DEBOUNCE) )
+    {
+        pPio->PIO_IFER = dwMask ;
+    }
+    else
+    {
+        pPio->PIO_IFDR = dwMask ;
+    }
+
+    /* Enable de-glitch or de-bounce if necessary */
+#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_)
+    if ( dwAttribute & PIO_DEGLITCH )
+    {
+        pPio->PIO_IFSCDR = dwMask ;
+    }
+    else
+    {
+        if ( dwAttribute & PIO_DEBOUNCE )
+        {
+            pPio->PIO_IFSCER = dwMask ;
+        }
+    }
+#elif (defined _SAM3U_) || (defined _SAM3XA_)
+    if ( dwAttribute & PIO_DEGLITCH )
+    {
+        pPio->PIO_SCIFSR = dwMask ;
+    }
+    else
+    {
+        if ( dwAttribute & PIO_DEBOUNCE )
+        {
+            pPio->PIO_SCIFSR = dwMask ;
+        }
+    }
+#else
+    #error "The specified chip is not supported."
+#endif
+
+    /* Configure pin as input */
+    pPio->PIO_ODR = dwMask ;
+    pPio->PIO_PER = dwMask ;
+}
+
+/**
+ * \brief Configures one or more pin(s) of a PIO controller as outputs, with the
+ * given default value. Optionally, the multi-drive feature can be enabled
+ * on the pin(s).
+ *
+ * \param pPio              Pointer to a PIO controller.
+ * \param dwMask            Bitmask indicating which pin(s) to configure.
+ * \param defaultValue      Default level on the pin(s).
+ * \param enableMultiDrive  Indicates if the pin(s) shall be configured as open-drain.
+ * \param enablePullUp      Indicates if the pin shall have its pull-up activated.
+ */
+extern void PIO_SetOutput( Pio* pPio, uint32_t dwMask, uint32_t dwDefaultValue,
+                                      uint32_t dwMultiDriveEnable, uint32_t dwPullUpEnable )
+{
+    PIO_DisableInterrupt( pPio, dwMask ) ;
+    PIO_PullUp( pPio, dwMask, dwPullUpEnable ) ;
+
+    /* Enable multi-drive if necessary */
+    if ( dwMultiDriveEnable )
+    {
+        pPio->PIO_MDER = dwMask ;
+    }
+    else
+    {
+        pPio->PIO_MDDR = dwMask ;
+    }
+
+    /* Set default value */
+    if ( dwDefaultValue )
+    {
+        pPio->PIO_SODR = dwMask ;
+    }
+    else
+    {
+        pPio->PIO_CODR = dwMask ;
+    }
+
+    /* Configure pin(s) as output(s) */
+    pPio->PIO_OER = dwMask ;
+    pPio->PIO_PER = dwMask ;
+}
+
+/**
+ *
+ * \return 1 if the pins have been configured properly; otherwise 0.
+ */
+extern uint32_t PIO_Configure( Pio* pPio, const EPioType dwType, const uint32_t dwMask, const uint32_t dwAttribute )
+{
+    /* Configure pins */
+    switch ( dwType )
+    {
+        case PIO_PERIPH_A :
+        case PIO_PERIPH_B :
+#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_)
+        case PIO_PERIPH_C :
+        case PIO_PERIPH_D :
+#endif /* (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_) */
+            /* Put the pin under control of peripheral */
+            PIO_SetPeripheral( pPio, dwType, dwMask ) ;
+            /* Disable interrupts on the pin(s) */
+            PIO_DisableInterrupt( pPio, dwMask ) ;
+            /* Enable Pullup */
+            PIO_PullUp( pPio, dwMask, (dwAttribute & PIO_PULLUP) ) ;
+        break;
+
+        case PIO_INPUT :
+            PIO_SetInput( pPio, dwMask, dwAttribute ) ;
+        break;
+
+        case PIO_OUTPUT_0 :
+        case PIO_OUTPUT_1 :
+            PIO_SetOutput( pPio, dwMask, (dwType == PIO_OUTPUT_1),
+                          (dwAttribute & PIO_OPENDRAIN) ? 1 : 0,
+                          (dwAttribute & PIO_PULLUP) ? 1 : 0);
+        break ;
+
+        default :
+        return 0 ;
+    }
+
+    return 1 ;
+}
+
+/**
+ * \brief Returns 1 if one or more PIO of the given Pin are configured to output a
+ * high level (even if they are not output).
+ * To get the actual value of the pin, use PIO_Get() instead.
+ *
+ * \param pPio  Pointer to a Pin instance describing one or more pins.
+ *
+ * \return 1 if the Pin instance contains at least one PIO that is configured
+ * to output a high level; otherwise 0.
+ */
+extern uint32_t PIO_GetOutputDataStatus( const Pio* pPio, const uint32_t dwMask )
+{
+  /* Test if pin is under control of PIO */
+  if ( (pPio->PIO_PSR & dwMask) != 0 )
+  {
+    /* Test if pin is configured as output */
+    if ( (pPio->PIO_OSR & dwMask) != 0 )
+    {
+      return 1 ;
+    }
+  }
+
+  return 0 ;
+}
+
diff --git a/hardware/sam/system/libsam/source/pio_it.c.disabled b/hardware/sam/system/libsam/source/pio_it.c.disabled
new file mode 100644
index 000000000..0a4ebad7c
--- /dev/null
+++ b/hardware/sam/system/libsam/source/pio_it.c.disabled
@@ -0,0 +1,280 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include 
+
+/*----------------------------------------------------------------------------
+ *        Local definitions
+ *----------------------------------------------------------------------------*/
+
+/* Maximum number of interrupt sources that can be defined. This
+ * constant can be increased, but the current value is the smallest possible
+ * that will be compatible with all existing projects. */
+#define MAX_INTERRUPT_SOURCES       7
+
+/*----------------------------------------------------------------------------
+ *        Local types
+ *----------------------------------------------------------------------------*/
+
+/**
+ * Describes a PIO interrupt source, including the PIO instance triggering the
+ * interrupt and the associated interrupt handler.
+ */
+typedef struct _InterruptSource
+{
+    /* Pointer to the source pin instance. */
+    const Pin *pPin ;
+
+    /* Interrupt handler. */
+    void (*handler)( const Pin* ) ;
+} InterruptSource ;
+
+/*----------------------------------------------------------------------------
+ *        Local variables
+ *----------------------------------------------------------------------------*/
+
+/* List of interrupt sources. */
+static InterruptSource _aIntSources[MAX_INTERRUPT_SOURCES] ;
+
+/* Number of currently defined interrupt sources. */
+static uint32_t _dwNumSources = 0;
+
+/*----------------------------------------------------------------------------
+ *        Local Functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Handles all interrupts on the given PIO controller.
+ * \param id  PIO controller ID.
+ * \param pPio  PIO controller base address.
+ */
+extern void PioInterruptHandler( uint32_t id, Pio *pPio )
+{
+    uint32_t status;
+    uint32_t i;
+
+    /* Read PIO controller status */
+    status = pPio->PIO_ISR;
+    status &= pPio->PIO_IMR;
+
+    /* Check pending events */
+    if ( status != 0 )
+    {
+        TRACE_DEBUG( "PIO interrupt on PIO controller #%d\n\r", id ) ;
+
+        /* Find triggering source */
+        i = 0;
+        while ( status != 0 )
+        {
+            /* There cannot be an unconfigured source enabled. */
+            assert(i < _dwNumSources);
+
+            /* Source is configured on the same controller */
+            if (_aIntSources[i].pPin->id == id)
+            {
+                /* Source has PIOs whose statuses have changed */
+                if ( (status & _aIntSources[i].pPin->mask) != 0 )
+                {
+                    TRACE_DEBUG( "Interrupt source #%d triggered\n\r", i ) ;
+
+                    _aIntSources[i].handler(_aIntSources[i].pPin);
+                    status &= ~(_aIntSources[i].pPin->mask);
+                }
+            }
+            i++;
+        }
+    }
+}
+
+/*----------------------------------------------------------------------------
+ *        Global Functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Parallel IO Controller A interrupt handler
+ * \Redefined PIOA interrupt handler for NVIC interrupt table.
+ */
+extern void PIOA_IrqHandler( void )
+{
+    if ( PIOA->PIO_PCISR != 0 )
+    {
+        PIO_CaptureHandler() ;
+    }
+
+    PioInterruptHandler( ID_PIOA, PIOA ) ;
+}
+
+/**
+ * \brief Parallel IO Controller B interrupt handler
+ * \Redefined PIOB interrupt handler for NVIC interrupt table.
+ */
+extern void PIOB_IrqHandler( void )
+{
+    PioInterruptHandler( ID_PIOB, PIOB ) ;
+}
+
+/**
+ * \brief Parallel IO Controller C interrupt handler
+ * \Redefined PIOC interrupt handler for NVIC interrupt table.
+ */
+extern void PIOC_IrqHandler( void )
+{
+    PioInterruptHandler( ID_PIOC, PIOC ) ;
+}
+
+/**
+ * \brief Initializes the PIO interrupt management logic
+ *
+ * The desired priority of PIO interrupts must be provided.
+ * Calling this function multiple times result in the reset of currently
+ * configured interrupts.
+ *
+ * \param priority  PIO controller interrupts priority.
+ */
+extern void PIO_InitializeInterrupts( uint32_t dwPriority )
+{
+    TRACE_DEBUG( "PIO_Initialize()\n\r" ) ;
+
+    /* Reset sources */
+    _dwNumSources = 0 ;
+
+    /* Configure PIO interrupt sources */
+    TRACE_DEBUG( "PIO_Initialize: Configuring PIOA\n\r" ) ;
+    PMC_EnablePeripheral( ID_PIOA ) ;
+    PIOA->PIO_ISR ;
+    PIOA->PIO_IDR = 0xFFFFFFFF ;
+    NVIC_DisableIRQ( PIOA_IRQn ) ;
+    NVIC_ClearPendingIRQ( PIOA_IRQn ) ;
+    NVIC_SetPriority( PIOA_IRQn, dwPriority ) ;
+    NVIC_EnableIRQ( PIOA_IRQn ) ;
+
+    TRACE_DEBUG( "PIO_Initialize: Configuring PIOB\n\r" ) ;
+    PMC_EnablePeripheral( ID_PIOB ) ;
+    PIOB->PIO_ISR ;
+    PIOB->PIO_IDR = 0xFFFFFFFF ;
+    NVIC_DisableIRQ( PIOB_IRQn ) ;
+    NVIC_ClearPendingIRQ( PIOB_IRQn ) ;
+    NVIC_SetPriority( PIOB_IRQn, dwPriority ) ;
+    NVIC_EnableIRQ( PIOB_IRQn ) ;
+
+    TRACE_DEBUG( "PIO_Initialize: Configuring PIOC\n\r" ) ;
+    PMC_EnablePeripheral( ID_PIOC ) ;
+    PIOC->PIO_ISR ;
+    PIOC->PIO_IDR = 0xFFFFFFFF ;
+    NVIC_DisableIRQ( PIOC_IRQn ) ;
+    NVIC_ClearPendingIRQ( PIOC_IRQn ) ;
+    NVIC_SetPriority( PIOC_IRQn, dwPriority ) ;
+    NVIC_EnableIRQ( PIOC_IRQn ) ;
+}
+
+/**
+ * Configures a PIO or a group of PIO to generate an interrupt on status
+ * change. The provided interrupt handler will be called with the triggering
+ * pin as its parameter (enabling different pin instances to share the same
+ * handler).
+ * \param pPin  Pointer to a Pin instance.
+ * \param handler  Interrupt handler function pointer.
+ */
+extern void PIO_ConfigureIt( const Pin *pPin, void (*handler)( const Pin* ) )
+{
+    Pio* pio ;
+    InterruptSource* pSource ;
+
+    TRACE_DEBUG( "PIO_ConfigureIt()\n\r" ) ;
+
+    assert( pPin ) ;
+    pio = pPin->pio ;
+    assert( _dwNumSources < MAX_INTERRUPT_SOURCES ) ;
+
+    /* Define new source */
+    TRACE_DEBUG( "PIO_ConfigureIt: Defining new source #%d.\n\r",  _dwNumSources ) ;
+
+    pSource = &(_aIntSources[_dwNumSources]) ;
+    pSource->pPin = pPin ;
+    pSource->handler = handler ;
+    _dwNumSources++ ;
+
+    /* PIO3 with additional interrupt support
+     * Configure additional interrupt mode registers */
+    if ( pPin->attribute & PIO_IT_AIME )
+    {
+        // enable additional interrupt mode
+        pio->PIO_AIMER       = pPin->mask ;
+
+        // if bit field of selected pin is 1, set as Rising Edge/High level detection event
+        if ( pPin->attribute & PIO_IT_RE_OR_HL )
+        {
+            pio->PIO_REHLSR    = pPin->mask ;
+        }
+        else
+        {
+            pio->PIO_FELLSR     = pPin->mask;
+        }
+
+        /* if bit field of selected pin is 1, set as edge detection source */
+        if (pPin->attribute & PIO_IT_EDGE)
+            pio->PIO_ESR     = pPin->mask;
+        else
+            pio->PIO_LSR     = pPin->mask;
+    }
+    else
+    {
+        /* disable additional interrupt mode */
+        pio->PIO_AIMDR       = pPin->mask;
+    }
+}
+
+/**
+ * Enables the given interrupt source if it has been configured. The status
+ * register of the corresponding PIO controller is cleared prior to enabling
+ * the interrupt.
+ * \param pPin  Interrupt source to enable.
+ */
+extern void PIO_EnableIt( const Pio* pPio, const uint32_t dwMask )
+{
+    pPio->PIO_ISR ;
+    pPio->PIO_IER = dwMask ;
+}
+
+/**
+ * Disables a given interrupt source, with no added side effects.
+ *
+ * \param pPin  Interrupt source to disable.
+ */
+extern void PIO_DisableIt( const Pio* pPio, const uint32_t dwMask )
+{
+    pPio->PIO_IDR = dwMask ;
+}
+
diff --git a/hardware/sam/system/libsam/source/pmc.c b/hardware/sam/system/libsam/source/pmc.c
new file mode 100644
index 000000000..a390d9196
--- /dev/null
+++ b/hardware/sam/system/libsam/source/pmc.c
@@ -0,0 +1,183 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include 
+
+/*----------------------------------------------------------------------------
+ *        Local definitions
+ *----------------------------------------------------------------------------*/
+
+#define MASK_STATUS0 0xFFFFFFFC
+#define MASK_STATUS1 0xFFFFFFFF
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Enables the clock of a peripheral. The peripheral ID is used
+ * to identify which peripheral is targetted.
+ *
+ * \note The ID must NOT be shifted (i.e. 1 << ID_xxx).
+ *
+ * \param id  Peripheral ID (ID_xxx).
+ */
+extern void PMC_EnablePeripheral( uint32_t dwId )
+{
+#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3XA_)
+    assert( dwId < 35 ) ;
+
+    if ( dwId < 32 )
+    {
+        if ( (PMC->PMC_PCSR0 & ((uint32_t)1 << dwId)) == ((uint32_t)1 << dwId) )
+        {
+//            TRACE_DEBUG( "PMC_EnablePeripheral: clock of peripheral"  " %u is already enabled\n\r", dwId ) ;
+        }
+        else
+        {
+            PMC->PMC_PCER0 = 1 << dwId ;
+        }
+    }
+    else
+    {
+        dwId -= 32;
+        if ((PMC->PMC_PCSR1 & ((uint32_t)1 << dwId)) == ((uint32_t)1 << dwId))
+        {
+//            TRACE_DEBUG( "PMC_EnablePeripheral: clock of peripheral"  " %u is already enabled\n\r", dwId + 32 ) ;
+        }
+        else
+        {
+            PMC->PMC_PCER1 = 1 << dwId ;
+        }
+    }
+#elif (defined _SAM3N_) || (defined _SAM3U_)
+    if ( (PMC->PMC_PCSR0 & ((uint32_t)1 << dwId)) != ((uint32_t)1 << dwId) )
+    {
+        PMC->PMC_PCER0 = 1 << dwId ;
+    }
+#else
+    #error "The specified chip is not supported."
+#endif
+}
+
+/**
+ * \brief Disables the clock of a peripheral. The peripheral ID is used
+ * to identify which peripheral is targetted.
+ *
+ * \note The ID must NOT be shifted (i.e. 1 << ID_xxx).
+ *
+ * \param id  Peripheral ID (ID_xxx).
+ */
+extern void PMC_DisablePeripheral( uint32_t dwId )
+{
+#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3XA_)
+    assert( dwId < 35 ) ;
+
+    if ( dwId < 32 )
+    {
+        if ( (PMC->PMC_PCSR0 & ((uint32_t)1 << dwId)) == ((uint32_t)1 << dwId) )
+        {
+            PMC->PMC_PCDR0 = 1 << dwId ;
+        }
+    }
+    else
+    {
+        dwId -= 32 ;
+        if ( (PMC->PMC_PCSR1 & ((uint32_t)1 << dwId)) == ((uint32_t)1 << dwId) )
+        {
+            PMC->PMC_PCDR1 = 1 << dwId ;
+        }
+    }
+#elif (defined _SAM3N_) || (defined _SAM3U_)
+    if ( (PMC->PMC_PCSR0 & ((uint32_t)1 << dwId)) == ((uint32_t)1 << dwId) )
+    {
+        PMC->PMC_PCDR0 = 1 << dwId ;
+    }
+#else
+    #error "The specified chip is not supported."
+#endif
+}
+
+/**
+ * \brief Get the status of the specified peripheral clock.
+ *
+ * \note The ID must NOT be shifted (i.e. 1 << ID_xxx).
+ *
+ * \param dwId Peripheral ID (ID_xxx).
+ *
+ * \retval 0 Clock is active.
+ * \retval 1 Clock is inactive.
+ * \retval 2 Invalid parameter.
+ */
+extern uint32_t PMC_IsPeripheralEnabled( uint32_t dwId )
+{
+#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3XA_)
+    assert( dwId < 35 ) ;
+
+    if ( dwId < 32 )
+    {
+        if ( PMC->PMC_PCSR0 & (1 << dwId) )
+        {
+            return 0 ;
+        }
+        else
+        {
+            return 1 ;
+        }
+    }
+    else
+    {
+        if ( PMC->PMC_PCSR1 & (1 << (dwId - 32)) )
+        {
+            return 0 ;
+        }
+        else
+        {
+            return 1 ;
+        }
+    }
+#elif (defined _SAM3N_) || (defined _SAM3U_)
+    if ( (PMC->PMC_PCSR0 & ((uint32_t)1 << dwId)) )
+    {
+        return 0 ;
+    }
+    else
+    {
+        return 1 ;
+    }    
+#else
+    #error "The specified chip is not supported."
+#endif
+}
diff --git a/hardware/sam/system/libsam/source/pwmc.c b/hardware/sam/system/libsam/source/pwmc.c
new file mode 100644
index 000000000..6b6a3fc11
--- /dev/null
+++ b/hardware/sam/system/libsam/source/pwmc.c
@@ -0,0 +1,614 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup pwm_module Working with PWM
+ * The PWM driver provides the interface to configure and use the PWM
+ * peripheral.
+ *
+ * The PWM macrocell controls square output waveforms of 4 channels.
+ * Characteristics of output waveforms such as period, duty-cycle,
+ * dead-time can be configured.\n
+ * Some of PWM channels can be linked together as synchronous channel and
+ * duty-cycle of synchronous channels can be updated by PDC automaticly.
+ *
+ * Before enabling the channels, they must have been configured first.
+ * The main settings include:
+ * 
    
+ * 
  • Configuration of the clock generator.
    • 
+ * 
  • Selection of the clock for each channel.
    • 
+ * 
  • Configuration of output waveform characteristics, such as period, duty-cycle etc.
    • 
+ * 
  • Configuration for synchronous channels if needed.
    • 
+ *    - Selection of the synchronous channels.
+ *    - Selection of the moment when the WRDY flag and the corresponding PDC
+ *      transfer request are set (PTRM and PTRCS in the PWM_SCM register).
+ *    - Configuration of the update mode (UPDM in the PWM_SCM register).
+ *    - Configuration of the update period (UPR in the PWM_SCUP register).
+ * 

+ *
+ * After the channels is enabled, the user must use respective update registers
+ * to change the wave characteristics to prevent unexpected output waveform.
+ * i.e. PWM_CDTYUPDx register should be used if user want to change duty-cycle
+ * when the channel is enabled.
+ *
+ * For more accurate information, please look at the PWM section of the
+ * Datasheet.
+ *
+ * Related files :\n
+ * \ref pwmc.c\n
+ * \ref pwmc.h.\n
+ */
+/*@{*/
+/*@}*/
+
+/**
+ * \file
+ *
+ * Implementation of the Pulse Width Modulation Controller (PWM) peripheral.
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include 
+#include 
+
+/*----------------------------------------------------------------------------
+ *         Local functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Finds a prescaler/divisor couple to generate the desired frequency
+ * from MCK.
+ *
+ * Returns the value to enter in PWM_CLK or 0 if the configuration cannot be
+ * met.
+ *
+ * \param frequency  Desired frequency in Hz.
+ * \param mck  Master clock frequency in Hz.
+ */
+static uint16_t FindClockConfiguration(
+    uint32_t frequency,
+    uint32_t mck)
+{
+    uint32_t divisors[11] = {1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024};
+    uint8_t divisor = 0;
+    uint32_t prescaler;
+
+    assert(frequency < mck);
+
+    /* Find prescaler and divisor values */
+    prescaler = (mck / divisors[divisor]) / frequency;
+    while ((prescaler > 255) && (divisor < 11)) {
+
+        divisor++;
+        prescaler = (mck / divisors[divisor]) / frequency;
+    }
+
+    /* Return result */
+    if ( divisor < 11 )
+    {
+//        TRACE_DEBUG( "Found divisor=%u and prescaler=%u for freq=%uHz\n\r", divisors[divisor], prescaler, frequency ) ;
+
+        return prescaler | (divisor << 8) ;
+    }
+    else
+    {
+        return 0 ;
+    }
+}
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Configures PWM a channel with the given parameters, basic configure function.
+ *
+ * The PWM controller must have been clocked in the PMC prior to calling this
+ * function.
+ * Beware: this function disables the channel. It waits until disable is effective.
+ *
+ * \param channel  Channel number.
+ * \param prescaler  Channel prescaler.
+ * \param alignment  Channel alignment.
+ * \param polarity  Channel polarity.
+ */
+void PWMC_ConfigureChannel(
+    Pwm* pPwm,
+    uint8_t channel,
+    uint32_t prescaler,
+    uint32_t alignment,
+    uint32_t polarity)
+{
+    pPwm->PWM_CH_NUM[0].PWM_CMR = 1;
+
+//    assert(prescaler < PWM_CMR0_CPRE_MCKB);
+    assert((alignment & (uint32_t)~PWM_CMR_CALG) == 0);
+    assert((polarity & (uint32_t)~PWM_CMR_CPOL) == 0);
+
+    /* Disable channel (effective at the end of the current period) */
+    if ((pPwm->PWM_SR & (1 << channel)) != 0) {
+        pPwm->PWM_DIS = 1 << channel;
+        while ((pPwm->PWM_SR & (1 << channel)) != 0);
+    }
+
+    /* Configure channel */
+    pPwm->PWM_CH_NUM[channel].PWM_CMR = prescaler | alignment | polarity;
+}
+
+/**
+ * \brief Configures PWM a channel with the given parameters, extend configure function.
+ *
+ * The PWM controller must have been clocked in the PMC prior to calling this
+ * function.
+ * Beware: this function disables the channel. It waits until disable is effective.
+ *
+ * \param channel            Channel number.
+ * \param prescaler          Channel prescaler.
+ * \param alignment          Channel alignment.
+ * \param polarity           Channel polarity.
+ * \param countEventSelect   Channel counter event selection.
+ * \param DTEnable           Channel dead time generator enable.
+ * \param DTHInverte         Channel Dead-Time PWMHx output Inverted.
+ * \param DTLInverte         Channel Dead-Time PWMHx output Inverted.
+ */
+void PWMC_ConfigureChannelExt(
+    Pwm* pPwm,
+    uint8_t channel,
+    uint32_t prescaler,
+    uint32_t alignment,
+    uint32_t polarity,
+    uint32_t countEventSelect,
+    uint32_t DTEnable,
+    uint32_t DTHInverte,
+    uint32_t DTLInverte)
+{
+//    assert(prescaler < PWM_CMR0_CPRE_MCKB);
+    assert((alignment & (uint32_t)~PWM_CMR_CALG) == 0);
+    assert((polarity & (uint32_t)~PWM_CMR_CPOL) == 0);
+    assert((countEventSelect & (uint32_t)~PWM_CMR_CES) == 0);
+    assert((DTEnable & (uint32_t)~PWM_CMR_DTE) == 0);
+    assert((DTHInverte & (uint32_t)~PWM_CMR_DTHI) == 0);
+    assert((DTLInverte & (uint32_t)~PWM_CMR_DTLI) == 0);
+
+    /* Disable channel (effective at the end of the current period) */
+    if ((pPwm->PWM_SR & (1 << channel)) != 0) {
+        pPwm->PWM_DIS = 1 << channel;
+        while ((pPwm->PWM_SR & (1 << channel)) != 0);
+    }
+
+    /* Configure channel */
+    pPwm->PWM_CH_NUM[channel].PWM_CMR = prescaler | alignment | polarity |
+        countEventSelect | DTEnable | DTHInverte | DTLInverte;
+}
+
+/**
+ * \brief Configures PWM clocks A & B to run at the given frequencies.
+ *
+ * This function finds the best MCK divisor and prescaler values automatically.
+ *
+ * \param clka  Desired clock A frequency (0 if not used).
+ * \param clkb  Desired clock B frequency (0 if not used).
+ * \param mck  Master clock frequency.
+ */
+void PWMC_ConfigureClocks(uint32_t clka, uint32_t clkb, uint32_t mck)
+{
+    uint32_t mode = 0;
+    uint32_t result;
+
+    /* Clock A */
+    if (clka != 0) {
+
+        result = FindClockConfiguration(clka, mck);
+        assert( result != 0 ) ;
+        mode |= result;
+    }
+
+    /* Clock B */
+    if (clkb != 0) {
+
+        result = FindClockConfiguration(clkb, mck);
+        assert( result != 0 ) ;
+        mode |= (result << 16);
+    }
+
+    /* Configure clocks */
+//    TRACE_DEBUG( "Setting PWM_CLK = 0x%08X\n\r", mode ) ;
+    PWM->PWM_CLK = mode;
+}
+
+/**
+ * \brief Sets the period value used by a PWM channel.
+ *
+ * This function writes directly to the CPRD register if the channel is disabled;
+ * otherwise, it uses the update register CPRDUPD.
+ *
+ * \param channel Channel number.
+ * \param period  Period value.
+ */
+void PWMC_SetPeriod( Pwm* pPwm, uint8_t channel, uint16_t period)
+{
+    /* If channel is disabled, write to CPRD */
+    if ((pPwm->PWM_SR & (1 << channel)) == 0) {
+
+        pPwm->PWM_CH_NUM[channel].PWM_CPRD = period;
+    }
+    /* Otherwise use update register */
+    else {
+
+        pPwm->PWM_CH_NUM[channel].PWM_CPRDUPD = period;
+    }
+}
+
+/**
+ * \brief Sets the duty cycle used by a PWM channel.
+ * This function writes directly to the CDTY register if the channel is disabled;
+ * otherwise it uses the update register CDTYUPD.
+ * Note that the duty cycle must always be inferior or equal to the channel
+ * period.
+ *
+ * \param channel  Channel number.
+ * \param duty     Duty cycle value.
+ */
+void PWMC_SetDutyCycle( Pwm* pPwm, uint8_t channel, uint16_t duty)
+{
+    assert(duty <= pPwm->PWM_CH_NUM[channel].PWM_CPRD);
+
+    /* If channel is disabled, write to CDTY */
+    if ((pPwm->PWM_SR & (1 << channel)) == 0) {
+
+        pPwm->PWM_CH_NUM[channel].PWM_CDTY = duty;
+    }
+    /* Otherwise use update register */
+    else {
+
+        pPwm->PWM_CH_NUM[channel].PWM_CDTYUPD = duty;
+    }
+}
+
+/**
+ * \brief Sets the dead time used by a PWM channel.
+ * This function writes directly to the DT register if the channel is disabled;
+ * otherwise it uses the update register DTUPD.
+ * Note that the dead time must always be inferior or equal to the channel
+ * period.
+ *
+ * \param channel  Channel number.
+ * \param timeH    Dead time value for PWMHx output.
+ * \param timeL    Dead time value for PWMLx output.
+ */
+void PWMC_SetDeadTime( Pwm* pPwm, uint8_t channel, uint16_t timeH, uint16_t timeL)
+{
+    assert(timeH <= pPwm->PWM_CH_NUM[channel].PWM_CPRD);
+    assert(timeL <= pPwm->PWM_CH_NUM[channel].PWM_CPRD);
+
+    /* If channel is disabled, write to DT */
+    if ((pPwm->PWM_SR & (1 << channel)) == 0) {
+
+        pPwm->PWM_CH_NUM[channel].PWM_DT = timeH | (timeL << 16);
+    }
+    /* Otherwise use update register */
+    else {
+        pPwm->PWM_CH_NUM[channel].PWM_DTUPD = timeH | (timeL << 16);
+    }
+}
+
+/**
+ * \brief Configures Syncronous channel with the given parameters.
+ * Beware: At this time, the channels should be disabled.
+ *
+ * \param channels                 Bitwise OR of Syncronous channels.
+ * \param updateMode               Syncronous channel update mode.
+ * \param requestMode              PDC transfer request mode.
+ * \param requestComparisonSelect  PDC transfer request comparison selection.
+ */
+void PWMC_ConfigureSyncChannel( Pwm* pPwm,
+    uint32_t channels,
+    uint32_t updateMode,
+    uint32_t requestMode,
+    uint32_t requestComparisonSelect)
+{
+    pPwm->PWM_SCM = channels | updateMode | requestMode | requestComparisonSelect;
+}
+
+/**
+ * \brief Sets the update period of the synchronous channels.
+ * This function writes directly to the SCUP register if the channel #0 is disabled;
+ * otherwise it uses the update register SCUPUPD.
+ *
+ * \param period   update period.
+ */
+void PWMC_SetSyncChannelUpdatePeriod( Pwm* pPwm, uint8_t period)
+{
+    /* If channel is disabled, write to SCUP */
+    if ((pPwm->PWM_SR & (1 << 0)) == 0) {
+
+        pPwm->PWM_SCUP = period;
+    }
+    /* Otherwise use update register */
+    else {
+
+        pPwm->PWM_SCUPUPD = period;
+    }
+}
+
+/**
+ * \brief Sets synchronous channels update unlock.
+ *
+ * Note: If the UPDM field is set to 0, writing the UPDULOCK bit to 1
+ * triggers the update of the period value, the duty-cycle and
+ * the dead-time values of synchronous channels at the beginning
+ * of the next PWM period. If the field UPDM is set to 1 or 2,
+ * writing the UPDULOCK bit to 1 triggers only the update of
+ * the period value and of the dead-time values of synchronous channels.
+ * This bit is automatically reset when the update is done.
+ */
+void PWMC_SetSyncChannelUpdateUnlock( Pwm* pPwm )
+{
+    pPwm->PWM_SCUC = PWM_SCUC_UPDULOCK;
+}
+
+/**
+ * \brief Enables the given PWM channel.
+ *
+ * This does NOT enable the corresponding pin;this must be done in the user code.
+ *
+ * \param channel  Channel number.
+ */
+void PWMC_EnableChannel( Pwm* pPwm, uint8_t channel)
+{
+    pPwm->PWM_ENA = 1 << channel;
+}
+
+/**
+ * \brief Disables the given PWM channel.
+ *
+ * Beware, channel will be effectively disabled at the end of the current period.
+ * Application can check channel is disabled using the following wait loop:
+ * while ((PWM->PWM_SR & (1 << channel)) != 0);
+ *
+ * \param channel  Channel number.
+ */
+void PWMC_DisableChannel( Pwm* pPwm, uint8_t channel)
+{
+    pPwm->PWM_DIS = 1 << channel;
+}
+
+/**
+ * \brief Enables the period interrupt for the given PWM channel.
+ *
+ * \param channel  Channel number.
+ */
+void PWMC_EnableChannelIt( Pwm* pPwm, uint8_t channel)
+{
+    pPwm->PWM_IER1 = 1 << channel;
+}
+
+/**
+ * \brief Disables the period interrupt for the given PWM channel.
+ *
+ * \param channel  Channel number.
+ */
+void PWMC_DisableChannelIt( Pwm* pPwm, uint8_t channel)
+{
+    pPwm->PWM_IDR1 = 1 << channel;
+}
+
+/**
+ * \brief Enables the selected interrupts sources on a PWMC peripheral.
+ *
+ * \param sources1  Bitwise OR of selected interrupt sources of PWM_IER1.
+ * \param sources2  Bitwise OR of selected interrupt sources of PWM_IER2.
+ */
+void PWMC_EnableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2)
+{
+    pPwm->PWM_IER1 = sources1;
+    pPwm->PWM_IER2 = sources2;
+}
+
+/**
+ * \brief Disables the selected interrupts sources on a PWMC peripheral.
+ *
+ * \param sources1  Bitwise OR of selected interrupt sources of PWM_IDR1.
+ * \param sources2  Bitwise OR of selected interrupt sources of PWM_IDR2.
+ */
+void PWMC_DisableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2)
+{
+    pPwm->PWM_IDR1 = sources1;
+    pPwm->PWM_IDR2 = sources2;
+}
+
+/**
+ * \brief Sends the contents of buffer through a PWMC peripheral, using the PDC to
+ * take care of the transfer.
+ *
+ * Note: Duty cycle of syncronous channels can update by PDC
+ *       when the field UPDM (Update Mode) in the PWM_SCM register is set to 2.
+ *
+ * \param pwmc    Pointer to an Pwm instance.
+ * \param buffer  Data buffer to send.
+ * \param length  Length of the data buffer.
+ */
+uint8_t PWMC_WriteBuffer(Pwm *pwmc,
+    void *buffer,
+    uint32_t length)
+{
+    /* Check if first bank is free */
+    if (pwmc->PWM_TCR == 0) {
+
+        pwmc->PWM_TPR = (uint32_t) buffer;
+        pwmc->PWM_TCR = length;
+        pwmc->PWM_PTCR = PERIPH_PTCR_TXTEN;
+        return 1;
+    }
+    /* Check if second bank is free */
+    else if (pwmc->PWM_TNCR == 0) {
+
+        pwmc->PWM_TNPR = (uint32_t) buffer;
+        pwmc->PWM_TNCR = length;
+        return 1;
+    }
+
+    /* No free banks */
+    return 0;
+}
+
+/**
+ * \brief Set PWM output override value.
+ *
+ * \param value  Bitwise OR of output override value.
+ */
+void PWMC_SetOverrideValue( Pwm* pPwm, uint32_t value)
+{
+    pPwm->PWM_OOV = value;
+}
+
+/**
+ * \brief Enalbe override output.
+ *
+ * \param value  Bitwise OR of output selection.
+ * \param sync   0: enable the output asyncronously, 1: enable it syncronously
+ */
+void PWMC_EnableOverrideOutput( Pwm* pPwm, uint32_t value, uint32_t sync)
+{
+    if (sync) {
+
+        pPwm->PWM_OSSUPD = value;
+    } else {
+
+        pPwm->PWM_OSS = value;
+    }
+}
+
+/**
+ * \brief Disalbe override output.
+ *
+ * \param value  Bitwise OR of output selection.
+ * \param sync   0: enable the output asyncronously, 1: enable it syncronously
+ */
+void PWMC_DisableOverrideOutput( Pwm* pPwm, uint32_t value, uint32_t sync)
+{
+    if (sync) {
+
+        pPwm->PWM_OSCUPD = value;
+    } else {
+
+        pPwm->PWM_OSC = value;
+    }
+}
+
+/**
+ * \brief Set PWM fault mode.
+ *
+ * \param mode  Bitwise OR of fault mode.
+ */
+void PWMC_SetFaultMode( Pwm* pPwm, uint32_t mode)
+{
+    pPwm->PWM_FMR = mode;
+}
+
+/**
+ * \brief PWM fault clear.
+ *
+ * \param fault  Bitwise OR of fault to clear.
+ */
+void PWMC_FaultClear( Pwm* pPwm, uint32_t fault)
+{
+    pPwm->PWM_FCR = fault;
+}
+
+/**
+ * \brief Set PWM fault protection value.
+ *
+ * \param value  Bitwise OR of fault protection value.
+ */
+void PWMC_SetFaultProtectionValue( Pwm* pPwm, uint32_t value)
+{
+    pPwm->PWM_FPV = value;
+}
+
+/**
+ * \brief Enable PWM fault protection.
+ *
+ * \param value  Bitwise OR of FPEx[y].
+ */
+void PWMC_EnableFaultProtection( Pwm* pPwm, uint32_t value)
+{
+    pPwm->PWM_FPE = value;
+}
+
+/**
+ * \brief Configure comparison unit.
+ *
+ * \param x     comparison x index
+ * \param value comparison x value.
+ * \param mode  comparison x mode
+ */
+void PWMC_ConfigureComparisonUnit( Pwm* pPwm, uint32_t x, uint32_t value, uint32_t mode)
+{
+    assert(x < 8);
+
+    /* If channel is disabled, write to CMPxM & CMPxV */
+    if ((pPwm->PWM_SR & (1 << 0)) == 0) {
+        pPwm->PWM_CMP[x].PWM_CMPM = mode;
+        pPwm->PWM_CMP[x].PWM_CMPV = value;
+    }
+    /* Otherwise use update register */
+    else {
+        pPwm->PWM_CMP[x].PWM_CMPMUPD = mode;
+        pPwm->PWM_CMP[x].PWM_CMPVUPD = value;
+    }
+}
+
+/**
+ * \brief Configure event line mode.
+ *
+ * \param x    Line x
+ * \param mode Bitwise OR of line mode selection
+ */
+void PWMC_ConfigureEventLineMode( Pwm* pPwm, uint32_t x, uint32_t mode)
+{
+    assert(x < 2);
+
+    if (x == 0)
+    {
+        pPwm->PWM_ELMR[0] = mode;
+    }
+    else
+    {
+        if (x == 1)
+        {
+            pPwm->PWM_ELMR[1] = mode;
+        }
+    }
+}
diff --git a/hardware/sam/system/libsam/source/rtc.c b/hardware/sam/system/libsam/source/rtc.c
new file mode 100644
index 000000000..185043678
--- /dev/null
+++ b/hardware/sam/system/libsam/source/rtc.c
@@ -0,0 +1,450 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup rtc_module Working with RTC
+ * The RTC driver provides the interface to configure and use the RTC
+ * peripheral.
+ *
+ * It manages date, time, and alarms.\n
+ * This timer is clocked by the 32kHz system clock, and is not impacted by
+ * power management settings (PMC). To be accurate, it is better to use an
+ * external 32kHz crystal instead of the internal 32kHz RC.\n
+ *
+ * It uses BCD format, and time can be set in AM/PM or 24h mode through a
+ * configuration bit in the mode register.\n
+ *
+ * To update date or time, the user has to follow these few steps :
+ * 
    
+ * 
  • Set UPDTIM and/or UPDCAL bit(s) in RTC_CR,
    • 
+ * 
  • Polling or IRQ on the ACKUPD bit of RTC_CR,
    • 
+ * 
  • Clear ACKUPD bit in RTC_SCCR,
    • 
+ * 
  • Update Time and/or Calendar values in RTC_TIMR/RTC_CALR (BCD format),
    • 
+ * 
  • Clear UPDTIM and/or UPDCAL bit in RTC_CR.
    • 
+ * 

+ * An alarm can be set to happen on month, date, hours, minutes or seconds,
+ * by setting the proper "Enable" bit of each of these fields in the Time and
+ * Calendar registers.
+ * This allows a large number of configurations to be available for the user.
+ * Alarm occurence can be detected even by polling or interrupt.
+ *
+ * A check of the validity of the date and time format and values written by the user is automatically done.
+ * Errors are reported through the Valid Entry Register.
+ *
+ * For more accurate information, please look at the RTC section of the
+ * Datasheet.
+ *
+ * Related files :\n
+ * \ref rtc.c\n
+ * \ref rtc.h.\n
+*/
+/*@{*/
+/*@}*/
+
+
+/**
+ * \file
+ *
+ * Implementation of Real Time Clock (RTC) controller.
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include 
+#include 
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Sets the RTC in either 12 or 24 hour mode.
+ *
+ * \param mode  Hour mode.
+ */
+extern void RTC_SetHourMode( Rtc* pRtc, uint32_t dwMode )
+{
+    assert((dwMode & 0xFFFFFFFE) == 0);
+
+    pRtc->RTC_MR = dwMode ;
+}
+
+/**
+ * \brief Gets the RTC mode.
+ *
+ * \return Hour mode.
+ */
+extern uint32_t RTC_GetHourMode( Rtc* pRtc )
+{
+    uint32_t dwMode ;
+
+    dwMode = pRtc->RTC_MR;
+    dwMode &= 0xFFFFFFFE;
+
+    return dwMode ;
+}
+
+/**
+ * \brief Enables the selected interrupt sources of the RTC.
+ *
+ * \param sources  Interrupt sources to enable.
+ */
+extern void RTC_EnableIt( Rtc* pRtc, uint32_t dwSources )
+{
+    assert((dwSources & (uint32_t)(~0x1F)) == 0);
+
+    pRtc->RTC_IER = dwSources ;
+}
+
+/**
+* \brief Disables the selected interrupt sources of the RTC.
+*
+* \param sources  Interrupt sources to disable.
+*/
+extern void RTC_DisableIt( Rtc* pRtc, uint32_t dwSources )
+{
+    assert((dwSources & (uint32_t)(~0x1F)) == 0);
+
+    pRtc->RTC_IDR = dwSources ;
+}
+
+/**
+ * \brief Sets the current time in the RTC.
+ *
+ * \note In successive update operations, the user must wait at least one second
+ * after resetting the UPDTIM/UPDCAL bit in the RTC_CR before setting these
+ * bits again. Please look at the RTC section of the datasheet for detail.
+ *
+ * \param ucHour    Current hour in 12 or 24 hour mode.
+ * \param ucMinute  Current minute.
+ * \param ucSecond  Current second.
+ *
+ * \return 0 sucess, 1 fail to set
+ */
+extern int RTC_SetTime( Rtc* pRtc, uint8_t ucHour, uint8_t ucMinute, uint8_t ucSecond )
+{
+    uint32_t dwTime=0 ;
+    uint8_t ucHour_bcd ;
+    uint8_t ucMin_bcd ;
+    uint8_t ucSec_bcd ;
+
+    /* if 12-hour mode, set AMPM bit */
+    if ( (pRtc->RTC_MR & RTC_MR_HRMOD) == RTC_MR_HRMOD )
+    {
+        if ( ucHour > 12 )
+        {
+            ucHour -= 12 ;
+            dwTime |= RTC_TIMR_AMPM ;
+        }
+    }
+    ucHour_bcd = (ucHour%10)   | ((ucHour/10)<<4) ;
+    ucMin_bcd  = (ucMinute%10) | ((ucMinute/10)<<4) ;
+    ucSec_bcd  = (ucSecond%10) | ((ucSecond/10)<<4) ;
+
+    /* value overflow */
+    if ( (ucHour_bcd & (uint8_t)(~RTC_HOUR_BIT_LEN_MASK)) |
+         (ucMin_bcd & (uint8_t)(~RTC_MIN_BIT_LEN_MASK)) |
+         (ucSec_bcd & (uint8_t)(~RTC_SEC_BIT_LEN_MASK)))
+    {
+        return 1 ;
+    }
+
+    dwTime = ucSec_bcd | (ucMin_bcd << 8) | (ucHour_bcd<<16) ;
+
+    pRtc->RTC_CR |= RTC_CR_UPDTIM ;
+    while ((pRtc->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD) ;
+    pRtc->RTC_SCCR = RTC_SCCR_ACKCLR ;
+    pRtc->RTC_TIMR = dwTime ;
+    pRtc->RTC_CR &= (uint32_t)(~RTC_CR_UPDTIM) ;
+    pRtc->RTC_SCCR |= RTC_SCCR_SECCLR ;
+
+    return (int)(pRtc->RTC_VER & RTC_VER_NVTIM) ;
+}
+
+/**
+ * \brief Retrieves the current time as stored in the RTC in several variables.
+ *
+ * \param pucHour    If not null, current hour is stored in this variable.
+ * \param pucMinute  If not null, current minute is stored in this variable.
+ * \param pucSecond  If not null, current second is stored in this variable.
+ */
+extern void RTC_GetTime( Rtc* pRtc, uint8_t *pucHour, uint8_t *pucMinute, uint8_t *pucSecond )
+{
+    uint32_t dwTime ;
+
+    /* Get current RTC time */
+    dwTime = pRtc->RTC_TIMR ;
+    while ( dwTime != pRtc->RTC_TIMR )
+    {
+        dwTime = pRtc->RTC_TIMR ;
+    }
+
+    /* Hour */
+    if ( pucHour )
+    {
+        *pucHour = ((dwTime & 0x00300000) >> 20) * 10
+                 + ((dwTime & 0x000F0000) >> 16);
+
+        if ( (dwTime & RTC_TIMR_AMPM) == RTC_TIMR_AMPM )
+        {
+            *pucHour += 12 ;
+        }
+    }
+
+    /* Minute */
+    if ( pucMinute )
+    {
+        *pucMinute = ((dwTime & 0x00007000) >> 12) * 10
+                   + ((dwTime & 0x00000F00) >> 8);
+    }
+
+    /* Second */
+    if ( pucSecond )
+    {
+        *pucSecond = ((dwTime & 0x00000070) >> 4) * 10
+                   + (dwTime & 0x0000000F);
+    }
+}
+
+/**
+ * \brief Sets a time alarm on the RTC.
+ * The match is performed only on the provided variables;
+ * Setting all pointers to 0 disables the time alarm.
+ *
+ * \note In AM/PM mode, the hour value must have bit #7 set for PM, cleared for
+ * AM (as expected in the time registers).
+ *
+ * \param pucHour    If not null, the time alarm will hour-match this value.
+ * \param pucMinute  If not null, the time alarm will minute-match this value.
+ * \param pucSecond  If not null, the time alarm will second-match this value.
+ *
+ * \return 0 success, 1 fail to set
+ */
+extern int RTC_SetTimeAlarm( Rtc* pRtc, uint8_t *pucHour, uint8_t *pucMinute, uint8_t *pucSecond )
+{
+    uint32_t dwAlarm=0 ;
+
+    /* Hour */
+    if ( pucHour )
+    {
+        dwAlarm |= RTC_TIMALR_HOUREN | ((*pucHour / 10) << 20) | ((*pucHour % 10) << 16);
+    }
+
+    /* Minute */
+    if ( pucMinute )
+    {
+        dwAlarm |= RTC_TIMALR_MINEN | ((*pucMinute / 10) << 12) | ((*pucMinute % 10) << 8);
+    }
+
+    /* Second */
+    if ( pucSecond )
+    {
+        dwAlarm |= RTC_TIMALR_SECEN | ((*pucSecond / 10) << 4) | (*pucSecond % 10);
+    }
+
+    pRtc->RTC_TIMALR = dwAlarm ;
+
+    return (int)(pRtc->RTC_VER & RTC_VER_NVTIMALR) ;
+}
+
+/**
+ * \brief Retrieves the current year, month and day from the RTC.
+ * Month, day and week values are numbered starting at 1.
+ *
+ * \param pYwear  Current year (optional).
+ * \param pucMonth  Current month (optional).
+ * \param pucDay  Current day (optional).
+ * \param pucWeek  Current day in current week (optional).
+ */
+extern void RTC_GetDate( Rtc* pRtc, uint16_t *pwYear, uint8_t *pucMonth, uint8_t *pucDay, uint8_t *pucWeek )
+{
+    uint32_t dwDate ;
+
+    /* Get current date (multiple reads are necessary to insure a stable value) */
+    do
+    {
+        dwDate = pRtc->RTC_CALR ;
+    }
+    while ( dwDate != pRtc->RTC_CALR ) ;
+
+    /* Retrieve year */
+    if ( pwYear )
+    {
+        *pwYear = (((dwDate  >> 4) & 0x7) * 1000)
+                 + ((dwDate & 0xF) * 100)
+                 + (((dwDate >> 12) & 0xF) * 10)
+                 + ((dwDate >> 8) & 0xF);
+    }
+
+    /* Retrieve month */
+    if ( pucMonth )
+    {
+        *pucMonth = (((dwDate >> 20) & 1) * 10) + ((dwDate >> 16) & 0xF);
+    }
+
+    /* Retrieve day */
+    if ( pucDay )
+    {
+        *pucDay = (((dwDate >> 28) & 0x3) * 10) + ((dwDate >> 24) & 0xF);
+    }
+
+    /* Retrieve week */
+    if ( pucWeek )
+    {
+        *pucWeek = ((dwDate >> 21) & 0x7);
+    }
+}
+
+/**
+ * \brief Sets the current year, month and day in the RTC.
+ * Month, day and week values must be numbered starting from 1.
+ *
+ * \note In successive update operations, the user must wait at least one second
+ * after resetting the UPDTIM/UPDCAL bit in the RTC_CR before setting these
+ * bits again. Please look at the RTC section of the datasheet for detail.
+ *
+ * \param wYear  Current year.
+ * \param ucMonth Current month.
+ * \param ucDay   Current day.
+ * \param ucWeek  Day number in current week.
+ *
+ * \return 0 success, 1 fail to set
+ */
+extern int RTC_SetDate( Rtc* pRtc, uint16_t wYear, uint8_t ucMonth, uint8_t ucDay, uint8_t ucWeek )
+{
+    uint32_t wDate ;
+    uint8_t ucCent_bcd ;
+    uint8_t ucYear_bcd ;
+    uint8_t ucMonth_bcd ;
+    uint8_t ucDay_bcd ;
+    uint8_t ucWeek_bcd ;
+
+    ucCent_bcd  = ((wYear/100)%10) | ((wYear/1000)<<4);
+    ucYear_bcd  = (wYear%10) | (((wYear/10)%10)<<4);
+    ucMonth_bcd = ((ucMonth%10) | (ucMonth/10)<<4);
+    ucDay_bcd   = ((ucDay%10) | (ucDay/10)<<4);
+    ucWeek_bcd  = ((ucWeek%10) | (ucWeek/10)<<4);
+
+    /* value over flow */
+    if ( (ucCent_bcd & (uint8_t)(~RTC_CENT_BIT_LEN_MASK)) |
+         (ucYear_bcd & (uint8_t)(~RTC_YEAR_BIT_LEN_MASK)) |
+         (ucMonth_bcd & (uint8_t)(~RTC_MONTH_BIT_LEN_MASK)) |
+         (ucWeek_bcd & (uint8_t)(~RTC_WEEK_BIT_LEN_MASK)) |
+         (ucDay_bcd & (uint8_t)(~RTC_DATE_BIT_LEN_MASK))
+       )
+    {
+        return 1 ;
+    }
+
+
+    /* Convert values to date register value */
+    wDate = ucCent_bcd |
+            (ucYear_bcd << 8) |
+            (ucMonth_bcd << 16) |
+            (ucWeek_bcd << 21) |
+            (ucDay_bcd << 24);
+
+    /* Update calendar register  */
+    pRtc->RTC_CR |= RTC_CR_UPDCAL ;
+    while ((pRtc->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD) ;
+
+    pRtc->RTC_SCCR = RTC_SCCR_ACKCLR;
+    pRtc->RTC_CALR = wDate ;
+    pRtc->RTC_CR &= (uint32_t)(~RTC_CR_UPDCAL) ;
+    pRtc->RTC_SCCR |= RTC_SCCR_SECCLR; /* clear SECENV in SCCR */
+
+    return (int)(pRtc->RTC_VER & RTC_VER_NVCAL) ;
+}
+
+/**
+ * \brief Sets a date alarm in the RTC.
+ * The alarm will match only the provided values;
+ * Passing a null-pointer disables the corresponding field match.
+ *
+ * \param pucMonth If not null, the RTC alarm will month-match this value.
+ * \param pucDay   If not null, the RTC alarm will day-match this value.
+ *
+ * \return 0 success, 1 fail to set
+ */
+extern int RTC_SetDateAlarm( Rtc* pRtc, uint8_t *pucMonth, uint8_t *pucDay )
+{
+    uint32_t dwAlarm ;
+
+    dwAlarm = ((pucMonth) || (pucDay)) ? (0) : (0x01010000);
+
+    /* Compute alarm field value */
+    if ( pucMonth )
+    {
+        dwAlarm |= RTC_CALALR_MTHEN | ((*pucMonth / 10) << 20) | ((*pucMonth % 10) << 16);
+    }
+
+    if ( pucDay )
+    {
+        dwAlarm |= RTC_CALALR_DATEEN | ((*pucDay / 10) << 28) | ((*pucDay % 10) << 24);
+    }
+
+    /* Set alarm */
+    pRtc->RTC_CALALR = dwAlarm ;
+
+    return (int)(pRtc->RTC_VER & RTC_VER_NVCALALR) ;
+}
+
+/**
+ * \brief Clear flag bits of status clear command register in the RTC.
+ *
+ * \param mask Bits mask of cleared events
+ */
+extern void RTC_ClearSCCR( Rtc* pRtc, uint32_t dwMask )
+{
+    /* Clear all flag bits in status clear command register */
+    dwMask &= RTC_SCCR_ACKCLR | RTC_SCCR_ALRCLR | RTC_SCCR_SECCLR | RTC_SCCR_TIMCLR | RTC_SCCR_CALCLR ;
+
+    pRtc->RTC_SCCR = dwMask ;
+}
+
+/**
+ * \brief Get flag bits of status register in the RTC.
+ *
+ * \param mask Bits mask of Status Register
+ *
+ * \return Status register & mask
+ */
+extern uint32_t RTC_GetSR( Rtc* pRtc, uint32_t dwMask )
+{
+    uint32_t dwEvent ;
+
+    dwEvent = pRtc->RTC_SR ;
+
+    return (dwEvent & dwMask) ;
+}
+
diff --git a/hardware/sam/system/libsam/source/rtt.c b/hardware/sam/system/libsam/source/rtt.c
new file mode 100644
index 000000000..84e7c5121
--- /dev/null
+++ b/hardware/sam/system/libsam/source/rtt.c
@@ -0,0 +1,132 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup rtt_module Working with RTT
+ * The RTT driver provides the interface to configure and use the RTT
+ * peripheral.
+ *
+ * The Real-time Timer is used to count elapsed seconds.\n
+ * This timer is clocked by the 32kHz system clock divided by a programmable
+ * 16-bit balue. To be accurate, it is better to use an
+ * external 32kHz crystal instead of the internal 32kHz RC.\n
+ *
+ * To count elapsed seconds, the user could follow these few steps:
+ * 
    
+ * 
  • Programming PTPRES in RTT_MR to feeding the timer with a 1Hz signal.
    • 
+ * 
  • Writing the bit RTTRST in RTT_MR to restart the timer with new settings.
    • 
+ * 

+ *
+ * An alarm can be set to happen on second by setting alarm value in RTT_AR.
+ * Alarm occurence can be detected by polling or interrupt.
+ *
+ * For more accurate information, please look at the RTT section of the
+ * Datasheet.
+ *
+ * Related files :\n
+ * \ref rtt.c\n
+ * \ref rtt.h.\n
+ */
+/*@{*/
+/*@}*/
+
+/**
+ * \file
+ *
+ * Implementation of Real Time Timer (RTT) controller.
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include "chip.h"
+
+#include 
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Changes the prescaler value of the given RTT and restarts it.
+ *
+ * \note This function disables RTT interrupt sources.
+ *
+ * \param rtt  Pointer to a Rtt instance.
+ * \param prescaler  Prescaler value for the RTT.
+ */
+void RTT_SetPrescaler(Rtt *rtt, uint16_t prescaler)
+{
+    rtt->RTT_MR = (prescaler |  RTT_MR_RTTRST);
+}
+
+/**
+ * \brief Returns the current value of the RTT timer value.
+ *
+ * \param rtt  Pointer to a Rtt instance.
+ */
+uint32_t RTT_GetTime(Rtt *rtt)
+{
+    return rtt->RTT_VR;
+}
+
+/**
+ * \brief Enables the specified RTT interrupt sources.
+ *
+ * \param rtt  Pointer to a Rtt instance.
+ * \param sources  Bitmask of interrupts to enable.
+ */
+void RTT_EnableIT(Rtt *rtt, uint32_t sources)
+{
+    assert( (sources & 0x0004FFFF) == 0 ) ;
+    rtt->RTT_MR |= sources;
+}
+
+/**
+ * \brief Returns the status register value of the given RTT.
+ *
+ * \param rtt  Pointer to an Rtt instance.
+ */
+uint32_t RTT_GetStatus(Rtt *rtt)
+{
+    return rtt->RTT_SR;
+}
+
+/**
+ * \brief Configures the RTT to generate an alarm at the given time.
+ *
+ * \param pRtt  Pointer to an Rtt instance.
+ * \param time  Alarm time.
+ */
+void RTT_SetAlarm(Rtt *pRtt, uint32_t time)
+{
+    assert(time > 0);
+
+    pRtt->RTT_AR = time - 1;
+}
diff --git a/hardware/sam/system/libsam/source/spi.c b/hardware/sam/system/libsam/source/spi.c
new file mode 100644
index 000000000..058f2cd9b
--- /dev/null
+++ b/hardware/sam/system/libsam/source/spi.c
@@ -0,0 +1,352 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup spi_module Working with SPI
+ * The SPI driver provides the interface to configure and use the SPI
+ * peripheral.
+ *
+ * The Serial Peripheral Interface (SPI) circuit is a synchronous serial
+ * data link that provides communication with external devices in Master
+ * or Slave Mode.
+ *
+ * To use the SPI, the user has to follow these few steps:
+ * -# Enable the SPI pins required by the application (see pio.h).
+ * -# Configure the SPI using the \ref SPI_Configure(). This enables the
+ *    peripheral clock. The mode register is loaded with the given value.
+ * -# Configure all the necessary chip selects with \ref SPI_ConfigureNPCS().
+ * -# Enable the SPI by calling \ref SPI_Enable().
+ * -# Send/receive data using \ref SPI_Write() and \ref SPI_Read(). Note that \ref SPI_Read()
+ *    must be called after \ref SPI_Write() to retrieve the last value read.
+ * -# Send/receive data using the PDC with the \ref SPI_WriteBuffer() and
+ *    \ref SPI_ReadBuffer() functions.
+ * -# Disable the SPI by calling \ref SPI_Disable().
+ *
+ * For more accurate information, please look at the SPI section of the
+ * Datasheet.
+ *
+ * Related files :\n
+ * \ref spi.c\n
+ * \ref spi.h.\n
+*/
+/*@{*/
+/*@}*/
+
+/**
+ * \file
+ *
+ * Implementation of Serial Peripheral Interface (SPI) controller.
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include 
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Enables a SPI peripheral.
+ *
+ * \param spi  Pointer to an Spi instance.
+ */
+extern void SPI_Enable( Spi* spi )
+{
+    spi->SPI_CR = SPI_CR_SPIEN ;
+}
+
+/**
+ * \brief Disables a SPI peripheral.
+ *
+ * \param spi  Pointer to an Spi instance.
+ */
+extern void SPI_Disable( Spi* spi )
+{
+    spi->SPI_CR = SPI_CR_SPIDIS ;
+}
+
+/**
+ * \brief Enables one or more interrupt sources of a SPI peripheral.
+ *
+ * \param spi  Pointer to an Spi instance.
+ * \param sources Bitwise OR of selected interrupt sources.
+ */
+extern void SPI_EnableIt( Spi* spi, uint32_t dwSources )
+{
+    spi->SPI_IER = dwSources ;
+}
+
+/**
+ * \brief Disables one or more interrupt sources of a SPI peripheral.
+ *
+ * \param spi  Pointer to an Spi instance.
+ * \param sources Bitwise OR of selected interrupt sources.
+ */
+extern void SPI_DisableIt( Spi* spi, uint32_t dwSources )
+{
+    spi->SPI_IDR = dwSources ;
+}
+
+/**
+ * \brief Configures a SPI peripheral as specified. The configuration can be computed
+ * using several macros (see \ref spi_configuration_macros).
+ *
+ * \param spi  Pointer to an Spi instance.
+ * \param id   Peripheral ID of the SPI.
+ * \param configuration  Value of the SPI configuration register.
+ */
+extern void SPI_Configure( Spi* spi, uint32_t dwId, uint32_t dwConfiguration )
+{
+    PMC_EnablePeripheral( dwId ) ;
+    spi->SPI_CR = SPI_CR_SPIDIS ;
+
+    /* Execute a software reset of the SPI twice */
+    spi->SPI_CR = SPI_CR_SWRST ;
+    spi->SPI_CR = SPI_CR_SWRST ;
+    spi->SPI_MR = dwConfiguration ;
+}
+
+
+/**
+ * \brief Configures a chip select of a SPI peripheral. The chip select configuration
+ * is computed using several macros (see \ref spi_configuration_macros).
+ *
+ * \param spi   Pointer to an Spi instance.
+ * \param npcs  Chip select to configure (0, 1, 2 or 3).
+ * \param configuration  Desired chip select configuration.
+ */
+void SPI_ConfigureNPCS( Spi* spi, uint32_t dwNpcs, uint32_t dwConfiguration )
+{
+    spi->SPI_CSR[dwNpcs] = dwConfiguration ;
+}
+
+/**
+ * \brief Get the current status register of the given SPI peripheral.
+ * \note This resets the internal value of the status register, so further
+ * read may yield different values.
+ * \param spi   Pointer to a Spi instance.
+ * \return  SPI status register.
+ */
+extern uint32_t SPI_GetStatus( Spi* spi )
+{
+    return spi->SPI_SR ;
+}
+
+/**
+ * \brief Reads and returns the last word of data received by a SPI peripheral. This
+ * method must be called after a successful SPI_Write call.
+ *
+ * \param spi  Pointer to an Spi instance.
+ *
+ * \return readed data.
+ */
+extern uint32_t SPI_Read( Spi* spi )
+{
+    while ( (spi->SPI_SR & SPI_SR_RDRF) == 0 ) ;
+
+    return spi->SPI_RDR & 0xFFFF ;
+}
+
+/**
+ * \brief Sends data through a SPI peripheral. If the SPI is configured to use a fixed
+ * peripheral select, the npcs value is meaningless. Otherwise, it identifies
+ * the component which shall be addressed.
+ *
+ * \param spi   Pointer to an Spi instance.
+ * \param npcs  Chip select of the component to address (0, 1, 2 or 3).
+ * \param data  Word of data to send.
+ */
+extern void SPI_Write( Spi* spi, uint32_t dwNpcs, uint16_t wData )
+{
+    /* Send data */
+    while ( (spi->SPI_SR & SPI_SR_TXEMPTY) == 0 ) ;
+    spi->SPI_TDR = wData | SPI_PCS( dwNpcs ) ;
+    while ( (spi->SPI_SR & SPI_SR_TDRE) == 0 ) ;
+}
+
+/**
+ * \brief Check if SPI transfer finish.
+ *
+ * \param spi  Pointer to an Spi instance.
+ *
+ * \return Returns 1 if there is no pending write operation on the SPI; otherwise
+ * returns 0.
+ */
+extern uint32_t SPI_IsFinished( Spi* spi )
+{
+    return ((spi->SPI_SR & SPI_SR_TXEMPTY) != 0) ;
+}
+
+#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_)
+/**
+ * \brief Enable Spi PDC transmit
+ * \param spi  Pointer to an Spi instance.
+*/
+extern void SPI_PdcEnableTx( Spi* spi )
+{
+    spi->SPI_PTCR = SPI_PTCR_TXTEN ;
+}
+
+/**
+ * \brief Disable Spi PDC transmit
+ * \param spi  Pointer to an Spi instance.
+*/
+extern void SPI_PdcDisableTx( Spi* spi )
+{
+    spi->SPI_PTCR = SPI_PTCR_TXTDIS ;
+}
+
+/**
+ * \brief Enable Spi PDC receive
+ * \param spi  Pointer to an Spi instance.
+*/
+extern void SPI_PdcEnableRx( Spi* spi )
+{
+    spi->SPI_PTCR = SPI_PTCR_RXTEN ;
+}
+
+/**
+ * \brief Disable Spi PDC receive
+ * \param spi  Pointer to an Spi instance.
+*/
+extern void SPI_PdcDisableRx( Spi* spi )
+{
+    spi->SPI_PTCR = SPI_PTCR_RXTDIS ;
+}
+
+/**
+ * \brief Set PDC transmit and next transmit buffer address and size.
+ *
+ * \param spi    Pointer to an Spi instance.
+ * \param txBuf  PDC transmit buffer address.
+ * \param txCount  Length in bytes of the transmit buffer.
+ * \param txNextBuf  PDC next transmit buffer address.
+ * \param txNextCount  Length in bytes of the next transmit buffer.
+ */
+extern void SPI_PdcSetTx( Spi* spi, void* pvTxBuf, uint32_t dwTxCount, void* pvTxNextBuf, uint32_t dwTxNextCount )
+{
+    spi->SPI_TPR = (uint32_t)pvTxBuf ;
+    spi->SPI_TCR = dwTxCount ;
+    spi->SPI_TNPR = (uint32_t)pvTxNextBuf ;
+    spi->SPI_TNCR = dwTxNextCount ;
+}
+
+/**
+ * \brief Set PDC receive and next receive buffer address and size.
+ *
+ * \param spi    Pointer to an Spi instance.
+ * \param rxBuf  PDC receive buffer address.
+ * \param rxCount  Length in bytes of the receive buffer.
+ * \param rxNextBuf  PDC next receive buffer address.
+ * \param rxNextCount  Length in bytes of the next receive buffer.
+ */
+extern void SPI_PdcSetRx( Spi* spi, void* pvRxBuf, uint32_t dwRxCount, void* pvRxNextBuf, uint32_t dwRxNextCount )
+{
+    spi->SPI_RPR = (uint32_t)pvRxBuf ;
+    spi->SPI_RCR = dwRxCount ;
+    spi->SPI_RNPR = (uint32_t)pvRxNextBuf ;
+    spi->SPI_RNCR = dwRxNextCount ;
+}
+
+/**
+ * \brief Sends the contents of buffer through a SPI peripheral, using the PDC to
+ * take care of the transfer.
+ *
+ * \param spi     Pointer to an Spi instance.
+ * \param buffer  Data buffer to send.
+ * \param length  Length of the data buffer.
+ */
+extern uint32_t SPI_WriteBuffer( Spi* spi, void* pvBuffer, uint32_t dwLength )
+{
+    /* Check if first bank is free */
+    if ( spi->SPI_TCR == 0 )
+    {
+        spi->SPI_TPR = (uint32_t)pvBuffer ;
+        spi->SPI_TCR = dwLength ;
+        spi->SPI_PTCR = PERIPH_PTCR_TXTEN ;
+
+        return 1 ;
+    }
+    /* Check if second bank is free */
+    else
+    {
+        if ( spi->SPI_TNCR == 0 )
+        {
+            spi->SPI_TNPR = (uint32_t)pvBuffer ;
+            spi->SPI_TNCR = dwLength ;
+
+            return 1 ;
+        }
+    }
+
+    /* No free banks */
+    return 0 ;
+}
+
+/**
+ * \brief Reads data from a SPI peripheral until the provided buffer is filled. This
+ * method does NOT need to be called after SPI_Write or SPI_WriteBuffer.
+ *
+ * \param spi     Pointer to an Spi instance.
+ * \param buffer  Data buffer to store incoming bytes.
+ * \param length  Length in bytes of the data buffer.
+ */
+extern uint32_t SPI_ReadBuffer( Spi* spi, void *pvBuffer, uint32_t dwLength )
+{
+    /* Check if the first bank is free */
+    if ( spi->SPI_RCR == 0 )
+    {
+        spi->SPI_RPR = (uint32_t)pvBuffer ;
+        spi->SPI_RCR = dwLength ;
+        spi->SPI_PTCR = PERIPH_PTCR_RXTEN ;
+
+        return 1 ;
+    }
+    /* Check if second bank is free */
+    else
+    {
+        if ( spi->SPI_RNCR == 0 )
+        {
+            spi->SPI_RNPR = (uint32_t)pvBuffer ;
+            spi->SPI_RNCR = dwLength ;
+            return 1 ;
+        }
+    }
+
+    /* No free bank */
+    return 0 ;
+}
+
+#endif /* (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_) */
+
diff --git a/hardware/sam/system/libsam/source/tc.c b/hardware/sam/system/libsam/source/tc.c
new file mode 100644
index 000000000..35439db5a
--- /dev/null
+++ b/hardware/sam/system/libsam/source/tc.c
@@ -0,0 +1,175 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * Implementation of Timer Counter (TC).
+ *
+ */
+
+/*------------------------------------------------------------------------------
+ *         Headers
+ *------------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include 
+
+/*------------------------------------------------------------------------------
+ *         Global functions
+ *------------------------------------------------------------------------------*/
+
+/**
+ * \brief Configures a Timer Counter Channel
+ *
+ * Configures a Timer Counter to operate in the given mode. Timer is stopped
+ * after configuration and must be restarted with TC_Start(). All the
+ * interrupts of the timer are also disabled.
+ *
+ * \param pTc  Pointer to a Tc instance.
+ * \param channel Channel number.
+ * \param mode  Operating mode (TC_CMR value).
+ */
+extern void TC_Configure( Tc *pTc, uint32_t dwChannel, uint32_t dwMode )
+{
+    TcChannel* pTcCh ;
+
+    assert( dwChannel < (sizeof( pTc->TC_CHANNEL )/sizeof( pTc->TC_CHANNEL[0] )) ) ;
+    pTcCh = pTc->TC_CHANNEL+dwChannel ;
+
+    /*  Disable TC clock */
+    pTcCh->TC_CCR = TC_CCR_CLKDIS ;
+
+    /*  Disable interrupts */
+    pTcCh->TC_IDR = 0xFFFFFFFF ;
+
+    /*  Clear status register */
+    pTcCh->TC_SR ;
+
+    /*  Set mode */
+    pTcCh->TC_CMR = dwMode ;
+}
+
+/**
+ * \brief Reset and Start the TC Channel
+ *
+ * Enables the timer clock and performs a software reset to start the counting.
+ *
+ * \param pTc  Pointer to a Tc instance.
+ * \param dwChannel Channel number.
+ */
+extern void TC_Start( Tc *pTc, uint32_t dwChannel )
+{
+    TcChannel* pTcCh ;
+
+    assert( dwChannel < (sizeof( pTc->TC_CHANNEL )/sizeof( pTc->TC_CHANNEL[0] )) ) ;
+
+    pTcCh = pTc->TC_CHANNEL+dwChannel ;
+    pTcCh->TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG ;
+}
+
+/**
+ * \brief Stop TC Channel
+ *
+ * Disables the timer clock, stopping the counting.
+ *
+ * \param pTc     Pointer to a Tc instance.
+ * \param dwChannel Channel number.
+ */
+extern void TC_Stop(Tc *pTc, uint32_t dwChannel )
+{
+    TcChannel* pTcCh ;
+
+    assert( dwChannel < (sizeof( pTc->TC_CHANNEL )/sizeof( pTc->TC_CHANNEL[0] )) ) ;
+
+    pTcCh = pTc->TC_CHANNEL+dwChannel ;
+    pTcCh->TC_CCR = TC_CCR_CLKDIS ;
+}
+
+/**
+ * \brief Find best MCK divisor
+ *
+ * Finds the best MCK divisor given the timer frequency and MCK. The result
+ * is guaranteed to satisfy the following equation:
+ * \code
+ *   (MCK / (DIV * 65536)) <= freq <= (MCK / DIV)
+ * \endcode
+ * with DIV being the highest possible value.
+ *
+ * \param dwFreq  Desired timer frequency.
+ * \param dwMCk  Master clock frequency.
+ * \param dwDiv  Divisor value.
+ * \param dwTcClks  TCCLKS field value for divisor.
+ * \param dwBoardMCK  Board clock frequency.
+ *
+ * \return 1 if a proper divisor has been found, otherwise 0.
+ */
+extern uint32_t TC_FindMckDivisor( uint32_t dwFreq, uint32_t dwMCk, uint32_t *dwDiv, uint32_t *dwTcClks, uint32_t dwBoardMCK )
+{
+    const uint32_t adwDivisors[5] = { 2, 8, 32, 128, dwBoardMCK / 32768 } ;
+
+    uint32_t dwIndex = 0 ;
+
+    /*  Satisfy lower bound */
+    while ( dwFreq < ((dwMCk / adwDivisors[dwIndex]) / 65536) )
+    {
+        dwIndex++ ;
+
+        /*  If no divisor can be found, return 0 */
+        if ( dwIndex == (sizeof( adwDivisors )/sizeof( adwDivisors[0] ))  )
+        {
+            return 0 ;
+        }
+    }
+
+    /*  Try to maximize DIV while satisfying upper bound */
+    while ( dwIndex < 4 )
+    {
+
+        if ( dwFreq > (dwMCk / adwDivisors[dwIndex + 1]) )
+        {
+            break ;
+        }
+        dwIndex++ ;
+    }
+
+    /*  Store results */
+    if ( dwDiv )
+    {
+        *dwDiv = adwDivisors[dwIndex] ;
+    }
+    if ( dwTcClks )
+    {
+        *dwTcClks = dwIndex ;
+    }
+
+    return 1 ;
+}
+
diff --git a/hardware/sam/system/libsam/source/timetick.c b/hardware/sam/system/libsam/source/timetick.c
new file mode 100644
index 000000000..8522e20a1
--- /dev/null
+++ b/hardware/sam/system/libsam/source/timetick.c
@@ -0,0 +1,118 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ *  \file
+ *  Implement simple system tick usage.
+ */
+
+/*----------------------------------------------------------------------------
+ *         Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+/*----------------------------------------------------------------------------
+ *         Local variables
+ *----------------------------------------------------------------------------*/
+
+/** Tick Counter united by ms */
+static volatile uint32_t _dwTickCount=0 ;
+
+/*----------------------------------------------------------------------------
+ *         Exported Functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ *  \brief Handler for Sytem Tick interrupt.
+ */
+extern void TimeTick_Increment( void )
+{
+    _dwTickCount++ ;
+}
+
+/**
+ *  \brief Configures the SAM3 SysTick & reset tickCount.
+ *  Systick interrupt handler will generates 1ms interrupt and increase a
+ *  tickCount.
+ *  \param dwNew_MCK  Current master clock.
+ */
+extern uint32_t TimeTick_Configure( uint32_t dwNew_MCK )
+{
+    _dwTickCount = 0 ;
+
+    return SysTick_Config( dwNew_MCK/1000 ) ;
+}
+
+/**
+ *  \brief Get current Tick Count, in ms.
+ */
+extern uint32_t GetTickCount( void )
+{
+    return _dwTickCount ;
+}
+
+/**
+ *  \brief Sync Wait for several ms
+ */
+extern void Wait( volatile uint32_t dwMs )
+{
+    uint32_t dwStart ;
+    uint32_t dwCurrent ;
+
+    dwStart = _dwTickCount ;
+    do
+    {
+        dwCurrent = _dwTickCount ;
+    } while ( dwCurrent - dwStart < dwMs ) ;
+}
+
+/**
+ *  \brief Sync Sleep for several ms
+ */
+extern void Sleep( volatile uint32_t dwMs )
+{
+    uint32_t dwStart ;
+    uint32_t dwCurrent ;
+
+    dwStart = _dwTickCount ;
+
+    do
+    {
+        dwCurrent = _dwTickCount ;
+
+        if ( dwCurrent - dwStart > dwMs )
+        {
+            break ;
+        }
+
+        __WFI() ;
+    } while( 1 ) ;
+}
+
diff --git a/hardware/sam/system/libsam/source/twi.c b/hardware/sam/system/libsam/source/twi.c
new file mode 100644
index 000000000..44287680c
--- /dev/null
+++ b/hardware/sam/system/libsam/source/twi.c
@@ -0,0 +1,380 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup twi_module Working with TWI
+ * The TWI driver provides the interface to configure and use the TWI
+ * peripheral.
+ *
+ * \section Usage
+ * 
    
+ * 
  •  Configures a TWI peripheral to operate in master mode, at the given
+ * frequency (in Hz) using TWI_Configure(). 
    • 
+ * 
  •  Sends a STOP condition on the TWI using TWI_Stop().
    • 
+ * 
  •  Starts a read operation on the TWI bus with the specified slave using
+ * TWI_StartRead(). Data must then be read using TWI_ReadByte() whenever
+ * a byte is available (poll using TWI_ByteReceived()).
    • 
+ * 
  •  Starts a write operation on the TWI to access the selected slave using
+ * TWI_StartWrite(). A byte of data must be provided to start the write;
+ * other bytes are written next.
    • 
+ * 
  •  Sends a byte of data to one of the TWI slaves on the bus using TWI_WriteByte().
+ * This function must be called once before TWI_StartWrite() with the first byte of data
+ * to send, then it shall be called repeatedly after that to send the remaining bytes.
    • 
+ * 
  •  Check if a byte has been received and can be read on the given TWI
+ * peripheral using TWI_ByteReceived().<
+ * Check if a byte has been sent using TWI_ByteSent().
    • 
+ * 
  •  Check if the current transmission is complete (the STOP has been sent)
+ * using TWI_TransferComplete().
    • 
+ * 
  •  Enables & disable the selected interrupts sources on a TWI peripheral
+ * using TWI_EnableIt() and TWI_DisableIt().
    • 
+ * 
  •  Get current status register of the given TWI peripheral using
+ * TWI_GetStatus(). Get current status register of the given TWI peripheral, but
+ * masking interrupt sources which are not currently enabled using
+ * TWI_GetMaskedStatus().
    • 
+ * 

+ * For more accurate information, please look at the TWI section of the
+ * Datasheet.
+ *
+ * Related files :\n
+ * \ref twi.c\n
+ * \ref twi.h.\n
+*/
+/*@{*/
+/*@}*/
+
+/**
+ * \file
+ *
+ * Implementation of Two Wire Interface (TWI).
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include 
+#include 
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Configures a TWI peripheral to operate in master mode, at the given
+ * frequency (in Hz). The duty cycle of the TWI clock is set to 50%.
+ * \param pTwi  Pointer to an Twi instance.
+ * \param twck  Desired TWI clock frequency.
+ * \param mck  Master clock frequency.
+ */
+void TWI_ConfigureMaster( Twi* pTwi, uint32_t dwTwCk, uint32_t dwMCk )
+{
+    uint32_t dwCkDiv = 0 ;
+    uint32_t dwClDiv ;
+    uint32_t dwOk = 0 ;
+
+    assert( pTwi ) ;
+
+    /* SVEN: TWI Slave Mode Enabled */
+    pTwi->TWI_CR = TWI_CR_SVEN ;
+    /* Reset the TWI */
+    pTwi->TWI_CR = TWI_CR_SWRST ;
+    pTwi->TWI_RHR ;
+
+    /* TWI Slave Mode Disabled, TWI Master Mode Disabled. */
+    pTwi->TWI_CR = TWI_CR_SVDIS ;
+    pTwi->TWI_CR = TWI_CR_MSDIS ;
+
+    /* Set master mode */
+    pTwi->TWI_CR = TWI_CR_MSEN ;
+
+    /* Configure clock */
+    while ( !dwOk )
+    {
+        dwClDiv = ((dwMCk / (2 * dwTwCk)) - 4) / (1<TWI_CWGR = 0 ;
+    pTwi->TWI_CWGR = (dwCkDiv << 16) | (dwClDiv << 8) | dwClDiv ;
+}
+
+/**
+ * \brief Configures a TWI peripheral to operate in slave mode.
+ * \param pTwi  Pointer to an Twi instance.
+ * \param slaveAddress Slave address.
+ */
+void TWI_ConfigureSlave(Twi *pTwi, uint8_t slaveAddress)
+{
+    uint32_t i;
+
+    /* TWI software reset */
+    pTwi->TWI_CR = TWI_CR_SWRST;
+    pTwi->TWI_RHR;
+
+    /* Wait at least 10 ms */
+    for (i=0; i < 1000000; i++);
+
+    /* TWI Slave Mode Disabled, TWI Master Mode Disabled*/
+    pTwi->TWI_CR = TWI_CR_SVDIS | TWI_CR_MSDIS;
+
+    /* Configure slave address. */
+    pTwi->TWI_SMR = 0;
+    pTwi->TWI_SMR = TWI_SMR_SADR(slaveAddress);
+
+    /* SVEN: TWI Slave Mode Enabled */
+    pTwi->TWI_CR = TWI_CR_SVEN;
+
+    /* Wait at least 10 ms */
+    for (i=0; i < 1000000; i++);
+    assert( (pTwi->TWI_CR & TWI_CR_SVDIS)!= TWI_CR_SVDIS ) ;
+}
+
+/**
+ * \brief Sends a STOP condition on the TWI.
+ * \param pTwi  Pointer to an Twi instance.
+ */
+void TWI_Stop( Twi *pTwi )
+{
+    assert( pTwi != NULL ) ;
+
+    pTwi->TWI_CR = TWI_CR_STOP;
+}
+
+/**
+ * \brief Starts a read operation on the TWI bus with the specified slave, it returns
+ * immediately. Data must then be read using TWI_ReadByte() whenever a byte is
+ * available (poll using TWI_ByteReceived()).
+ * \param pTwi  Pointer to an Twi instance.
+ * \param address  Slave address on the bus.
+ * \param iaddress  Optional internal address bytes.
+ * \param isize  Number of internal address bytes.
+ */
+void TWI_StartRead(
+    Twi *pTwi,
+    uint8_t address,
+    uint32_t iaddress,
+    uint8_t isize)
+{
+    assert( pTwi != NULL ) ;
+    assert( (address & 0x80) == 0 ) ;
+    assert( (iaddress & 0xFF000000) == 0 ) ;
+    assert( isize < 4 ) ;
+
+    /* Set slave address and number of internal address bytes. */
+    pTwi->TWI_MMR = 0;
+    pTwi->TWI_MMR = (isize << 8) | TWI_MMR_MREAD | (address << 16);
+
+    /* Set internal address bytes */
+    pTwi->TWI_IADR = 0;
+    pTwi->TWI_IADR = iaddress;
+
+    /* Send START condition */
+    pTwi->TWI_CR = TWI_CR_START;
+}
+
+/**
+ * \brief Reads a byte from the TWI bus. The read operation must have been started
+ * using TWI_StartRead() and a byte must be available (check with TWI_ByteReceived()).
+ * \param pTwi  Pointer to an Twi instance.
+ * \return byte read.
+ */
+uint8_t TWI_ReadByte(Twi *pTwi)
+{
+    assert( pTwi != NULL ) ;
+
+    return pTwi->TWI_RHR;
+}
+
+/**
+ * \brief Sends a byte of data to one of the TWI slaves on the bus.
+ * \note This function must be called once before TWI_StartWrite() with
+ * the first byte of data  to send, then it shall be called repeatedly
+ * after that to send the remaining bytes.
+ * \param pTwi  Pointer to an Twi instance.
+ * \param byte  Byte to send.
+ */
+void TWI_WriteByte(Twi *pTwi, uint8_t byte)
+{
+    assert( pTwi != NULL ) ;
+
+    pTwi->TWI_THR = byte;
+}
+
+/**
+ * \brief Starts a write operation on the TWI to access the selected slave, then
+ *  returns immediately. A byte of data must be provided to start the write;
+ * other bytes are written next.
+ * after that to send the remaining bytes.
+ * \param pTwi  Pointer to an Twi instance.
+ * \param address  Address of slave to acccess on the bus.
+ * \param iaddress  Optional slave internal address.
+ * \param isize  Number of internal address bytes.
+ * \param byte  First byte to send.
+ */
+void TWI_StartWrite(
+    Twi *pTwi,
+    uint8_t address,
+    uint32_t iaddress,
+    uint8_t isize,
+    uint8_t byte)
+{
+    assert( pTwi != NULL ) ;
+    assert( (address & 0x80) == 0 ) ;
+    assert( (iaddress & 0xFF000000) == 0 ) ;
+    assert( isize < 4 ) ;
+
+    /* Set slave address and number of internal address bytes. */
+    pTwi->TWI_MMR = 0;
+    pTwi->TWI_MMR = (isize << 8) | (address << 16);
+
+    /* Set internal address bytes. */
+    pTwi->TWI_IADR = 0;
+    pTwi->TWI_IADR = iaddress;
+
+    /* Write first byte to send.*/
+    TWI_WriteByte(pTwi, byte);
+}
+
+/**
+ * \brief Check if a byte have been receiced from TWI.
+ * \param pTwi  Pointer to an Twi instance.
+ * \return 1 if a byte has been received and can be read on the given TWI
+ * peripheral; otherwise, returns 0. This function resets the status register.
+ */
+uint8_t TWI_ByteReceived(Twi *pTwi)
+{
+    return ((pTwi->TWI_SR & TWI_SR_RXRDY) == TWI_SR_RXRDY);
+}
+
+/**
+ * \brief Check if a byte have been sent to TWI.
+ * \param pTwi  Pointer to an Twi instance.
+ * \return 1 if a byte has been sent  so another one can be stored for
+ * transmission; otherwise returns 0. This function clears the status register.
+ */
+uint8_t TWI_ByteSent(Twi *pTwi)
+{
+    return ((pTwi->TWI_SR & TWI_SR_TXRDY) == TWI_SR_TXRDY);
+}
+
+/**
+ * \brief Check if current transmission is complet.
+ * \param pTwi  Pointer to an Twi instance.
+ * \return  1 if the current transmission is complete (the STOP has been sent);
+ * otherwise returns 0.
+ */
+uint8_t TWI_TransferComplete(Twi *pTwi)
+{
+    return ((pTwi->TWI_SR & TWI_SR_TXCOMP) == TWI_SR_TXCOMP);
+}
+
+/**
+ * \brief Enables the selected interrupts sources on a TWI peripheral.
+ * \param pTwi  Pointer to an Twi instance.
+ * \param sources  Bitwise OR of selected interrupt sources.
+ */
+void TWI_EnableIt(Twi *pTwi, uint32_t sources)
+{
+    assert( pTwi != NULL ) ;
+    assert( (sources & 0xFFFFF088) == 0 ) ;
+
+    pTwi->TWI_IER = sources;
+}
+
+/**
+ * \brief Disables the selected interrupts sources on a TWI peripheral.
+ * \param pTwi  Pointer to an Twi instance.
+ * \param sources  Bitwise OR of selected interrupt sources.
+ */
+void TWI_DisableIt(Twi *pTwi, uint32_t sources)
+{
+    assert( pTwi != NULL ) ;
+    assert( (sources & 0xFFFFF088) == 0 ) ;
+
+    pTwi->TWI_IDR = sources;
+}
+
+/**
+ * \brief Get the current status register of the given TWI peripheral.
+ * \note This resets the internal value of the status register, so further
+ * read may yield different values.
+ * \param pTwi  Pointer to an Twi instance.
+ * \return  TWI status register.
+ */
+uint32_t TWI_GetStatus(Twi *pTwi)
+{
+    assert( pTwi != NULL ) ;
+
+    return pTwi->TWI_SR;
+}
+
+/**
+ * \brief Returns the current status register of the given TWI peripheral, but
+ * masking interrupt sources which are not currently enabled.
+ * \note This resets the internal value of the status register, so further
+ * read may yield different values.
+ * \param pTwi  Pointer to an Twi instance.
+ */
+uint32_t TWI_GetMaskedStatus(Twi *pTwi)
+{
+    uint32_t status;
+
+    assert( pTwi != NULL ) ;
+
+    status = pTwi->TWI_SR;
+    status &= pTwi->TWI_IMR;
+
+    return status;
+}
+
+/**
+ * \brief  Sends a STOP condition. STOP Condition is sent just after completing
+ *  the current byte transmission in master read mode.
+ * \param pTwi  Pointer to an Twi instance.
+ */
+void TWI_SendSTOPCondition(Twi *pTwi)
+{
+    assert( pTwi != NULL ) ;
+
+    pTwi->TWI_CR |= TWI_CR_STOP;
+}
+
diff --git a/hardware/sam/system/libsam/source/usart.c b/hardware/sam/system/libsam/source/usart.c
new file mode 100644
index 000000000..163b26b21
--- /dev/null
+++ b/hardware/sam/system/libsam/source/usart.c
@@ -0,0 +1,409 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup usart_module Working with USART
+ * The USART driver provides the interface to configure and use the USART peripheral.\n
+ *
+ * The USART supports several kinds of comminication modes such as full-duplex asynchronous/
+ * synchronous serial commnunication,RS485 with driver control signal,ISO7816,SPI and Test modes.
+ *
+ * To start a USART transfer with \ref AT91SAM3S_PDC "PDC" support, the user could follow these steps:
+ * 
    
+ * 
  •  Configure USART with expected mode and baudrate(see \ref USART_Configure), which could be done by:
+ * -# Resetting and disabling transmitter and receiver by setting US_CR(Control Register). 
    • 
+ * -# Conifguring the USART in a specific mode by setting USART_MODE bits in US_MR(Mode Register) 
+ * -# Setting baudrate which is different from mode to mode.
+   
+ * 
  •  Enable transmitter or receiver respectively by set US_CR_TXEN or US_CR_RXEN in US_CR.
    • 
+ * 
  •  Read from or write to the peripheral with  \ref USART_ReadBuffer or \ref USART_WriteBuffer.
+        These operations could be done by polling or interruption. 
    • 
+ * 
  •  For polling, check the status bit US_CSR_ENDRX/US_CSR_RXBUFF (READ) or US_CSR_ENDTX/
+        US_CSR_TXBUFE (WRITE).  
    • 
+ * 
  •  For interruption,"enable" the status bit through US_IER and
+        realize the hanler with USARTx_IrqHandler according to IRQ vector
+        table which is defined in board_cstartup_.c
+        To enable the interruption of USART,it should be configured with priority and enabled first through
+        NVIC .
    • 
+ * 

+ *
+ * For more accurate information, please look at the USART section of the
+ * Datasheet.
+ *
+ * Related files :\n
+ * \ref usart.c\n
+ * \ref usart.h\n
+*/
+
+
+
+/**
+ * \file
+ *
+ * Implementation of USART (Universal Synchronous Asynchronous Receiver Transmitter)
+ * controller.
+ *
+ */
+/*------------------------------------------------------------------------------
+ *         Headers
+ *------------------------------------------------------------------------------*/
+#include "chip.h"
+
+#include 
+#include 
+
+/*----------------------------------------------------------------------------
+ *        Local definitions
+ *----------------------------------------------------------------------------*/
+
+
+/*------------------------------------------------------------------------------
+ *         Exported functions
+ *------------------------------------------------------------------------------*/
+
+/**
+ * \brief Configures an USART peripheral with the specified parameters.
+ *
+ *
+ *  \param usart  Pointer to the USART peripheral to configure.
+ *  \param mode  Desired value for the USART mode register (see the datasheet).
+ *  \param baudrate  Baudrate at which the USART should operate (in Hz).
+ *  \param masterClock  Frequency of the system master clock (in Hz).
+ */
+void USART_Configure(Usart *usart,
+                            uint32_t mode,
+                            uint32_t baudrate,
+                            uint32_t masterClock)
+{
+    /* Reset and disable receiver & transmitter*/
+    usart->US_CR = US_CR_RSTRX | US_CR_RSTTX
+                   | US_CR_RXDIS | US_CR_TXDIS;
+
+    /* Configure mode*/
+    usart->US_MR = mode;
+
+    /* Configure baudrate*/
+    /* Asynchronous, no oversampling*/
+    if ( ((mode & US_MR_SYNC) == 0) && ((mode & US_MR_OVER) == 0) )
+    {
+        usart->US_BRGR = (masterClock / baudrate) / 16;
+    }
+
+    if( ((mode & US_MR_USART_MODE_SPI_MASTER) == US_MR_USART_MODE_SPI_MASTER)
+     || ((mode & US_MR_SYNC) == US_MR_SYNC))
+    {
+        if( (mode & US_MR_USCLKS_Msk) == US_MR_USCLKS_MCK)
+        {
+            usart->US_BRGR = masterClock / baudrate;
+        }
+        else
+        {
+            if ( (mode & US_MR_USCLKS_DIV) == US_MR_USCLKS_DIV)
+            {
+                usart->US_BRGR = masterClock / baudrate / 8;
+            }
+        }
+    }
+    /* TODO other modes*/
+}
+/**
+ * \brief Enables or disables the transmitter of an USART peripheral.
+ *
+ *
+ * \param usart  Pointer to an USART peripheral
+ * \param enabled  If true, the transmitter is enabled; otherwise it is
+ *                disabled.
+ */
+void USART_SetTransmitterEnabled(Usart *usart, uint8_t enabled)
+{
+    if (enabled) {
+
+        usart->US_CR = US_CR_TXEN;
+    }
+    else {
+
+        usart->US_CR = US_CR_TXDIS;
+    }
+}
+
+/**
+ * \brief Enables or disables the receiver of an USART peripheral
+ *
+ *
+ * \param usart  Pointer to an USART peripheral
+ * \param enabled  If true, the receiver is enabled; otherwise it is disabled.
+ */
+void USART_SetReceiverEnabled(Usart *usart,
+                                     uint8_t enabled)
+{
+    if (enabled) {
+
+        usart->US_CR = US_CR_RXEN;
+    }
+    else {
+
+        usart->US_CR = US_CR_RXDIS;
+    }
+}
+
+/**
+ * \brief Sends one packet of data through the specified USART peripheral. This
+ * function operates synchronously, so it only returns when the data has been
+ * actually sent.
+ *
+ *
+ * \param usart  Pointer to an USART peripheral.
+ * \param data  Data to send including 9nth bit and sync field if necessary (in
+ *        the same format as the US_THR register in the datasheet).
+ * \param timeOut  Time out value (0 = no timeout).
+ */
+void USART_Write(
+    Usart *usart,
+    uint16_t data,
+    volatile uint32_t timeOut)
+{
+    if (timeOut == 0) {
+
+        while ((usart->US_CSR & US_CSR_TXEMPTY) == 0);
+    }
+    else {
+
+        while ((usart->US_CSR & US_CSR_TXEMPTY) == 0) {
+
+            if (timeOut == 0) {
+
+//                TRACE_ERROR("USART_Write: Timed out.\n\r");
+                return;
+            }
+            timeOut--;
+        }
+    }
+
+    usart->US_THR = data;
+}
+
+/**
+ * \brief Sends the contents of a data buffer through the specified USART peripheral.
+ * This function returns immediately (1 if the buffer has been queued, 0
+ * otherwise); poll the ENDTX and TXBUFE bits of the USART status register
+ * to check for the transfer completion.
+ *
+ * \param usart  Pointer to an USART peripheral.
+ * \param buffer  Pointer to the data buffer to send.
+ * \param size  Size of the data buffer (in bytes).
+ */
+uint8_t USART_WriteBuffer(
+    Usart *usart,
+    void *buffer,
+    uint32_t size)
+{
+    /* Check if the first PDC bank is free*/
+    if ((usart->US_TCR == 0) && (usart->US_TNCR == 0)) {
+
+        usart->US_TPR = (uint32_t) buffer;
+        usart->US_TCR = size;
+        usart->US_PTCR = US_PTCR_TXTEN;
+
+        return 1;
+    }
+    /* Check if the second PDC bank is free*/
+    else if (usart->US_TNCR == 0) {
+
+        usart->US_TNPR = (uint32_t) buffer;
+        usart->US_TNCR = size;
+
+        return 1;
+    }
+    else {
+
+        return 0;
+    }
+}
+
+
+/**
+ * \brief  Reads and return a packet of data on the specified USART peripheral. This
+ * function operates asynchronously, so it waits until some data has been
+ * received.
+ *
+ * \param usart  Pointer to an USART peripheral.
+ * \param timeOut  Time out value (0 -> no timeout).
+ */
+uint16_t USART_Read(
+    Usart *usart,
+    volatile uint32_t timeOut)
+{
+    if (timeOut == 0) {
+
+        while ((usart->US_CSR & US_CSR_RXRDY) == 0);
+    }
+    else {
+
+        while ((usart->US_CSR & US_CSR_RXRDY) == 0) {
+
+            if (timeOut == 0) {
+
+//                TRACE_ERROR( "USART_Read: Timed out.\n\r" ) ;
+                return 0;
+            }
+            timeOut--;
+        }
+    }
+
+    return usart->US_RHR;
+}
+
+/**
+ * \brief  Reads data from an USART peripheral, filling the provided buffer until it
+ * becomes full. This function returns immediately with 1 if the buffer has
+ * been queued for transmission; otherwise 0.
+ *
+ * \param usart  Pointer to an USART peripheral.
+ * \param buffer  Pointer to the buffer where the received data will be stored.
+ * \param size  Size of the data buffer (in bytes).
+ */
+uint8_t USART_ReadBuffer(Usart *usart,
+                                      void *buffer,
+                                      uint32_t size)
+{
+    /* Check if the first PDC bank is free*/
+    if ((usart->US_RCR == 0) && (usart->US_RNCR == 0)) {
+
+        usart->US_RPR = (uint32_t) buffer;
+        usart->US_RCR = size;
+        usart->US_PTCR = US_PTCR_RXTEN;
+
+        return 1;
+    }
+    /* Check if the second PDC bank is free*/
+    else if (usart->US_RNCR == 0) {
+
+        usart->US_RNPR = (uint32_t) buffer;
+        usart->US_RNCR = size;
+
+        return 1;
+    }
+    else {
+
+        return 0;
+    }
+}
+
+/**
+ * \brief  Returns 1 if some data has been received and can be read from an USART;
+ * otherwise returns 0.
+ *
+ * \param usart  Pointer to an Usart instance.
+ */
+uint8_t USART_IsDataAvailable(Usart *usart)
+{
+    if ((usart->US_CSR & US_CSR_RXRDY) != 0) {
+
+        return 1;
+    }
+    else {
+
+        return 0;
+    }
+}
+
+/**
+ * \brief  Sets the filter value for the IRDA demodulator.
+ *
+ * \param pUsart  Pointer to an Usart instance.
+ * \param filter  Filter value.
+ */
+void USART_SetIrdaFilter(Usart *pUsart, uint8_t filter)
+{
+    assert( pUsart != NULL ) ;
+
+    pUsart->US_IF = filter;
+}
+
+/**
+ * \brief  Sends one packet of data through the specified USART peripheral. This
+ * function operates synchronously, so it only returns when the data has been
+ * actually sent.
+ *
+ * \param usart  Pointer to an USART peripheral.
+ * \param c  Character to send
+ */
+void USART_PutChar(
+    Usart *usart,
+    uint8_t c)
+{
+    /* Wait for the transmitter to be ready*/
+    while ((usart->US_CSR & US_CSR_TXEMPTY) == 0);
+
+    /* Send character*/
+    usart->US_THR = c;
+
+    /* Wait for the transfer to complete*/
+    while ((usart->US_CSR & US_CSR_TXEMPTY) == 0);
+}
+
+/**
+ * \brief   Return 1 if a character can be read in USART
+ */
+uint32_t USART_IsRxReady(Usart *usart)
+{
+    return (usart->US_CSR & US_CSR_RXRDY);
+}
+/**
+ * \brief   Get present status
+ */
+uint32_t USART_GetStatus(Usart *usart)
+{
+    return usart->US_CSR;
+}
+/**
+ * \brief   Enable interrupt
+ */
+void USART_EnableIt(Usart *usart,uint32_t mode)
+{
+    usart->US_IER = mode;
+}
+/**
+ * \brief   Disable interrupt
+ */
+void USART_DisableIt(Usart *usart,uint32_t mode)
+{
+    usart->US_IDR = mode;
+}
+/**
+ * \brief  Reads and returns a character from the USART.
+ *
+ * \note This function is synchronous (i.e. uses polling).
+ * \param usart  Pointer to an USART peripheral.
+ * \return Character received.
+ */
+uint8_t USART_GetChar(Usart *usart)
+{
+    while ((usart->US_CSR & US_CSR_RXRDY) == 0);
+    return usart->US_RHR;
+}
diff --git a/hardware/sam/system/libsam/source/wdt.c b/hardware/sam/system/libsam/source/wdt.c
new file mode 100644
index 000000000..7328042f2
--- /dev/null
+++ b/hardware/sam/system/libsam/source/wdt.c
@@ -0,0 +1,132 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * Implementation of Watchdog Timer (WDT) controller.
+ *
+ */
+
+/** \addtogroup wdt_module Working with WDT
+ * The WDT driver provides the interface to configure and use the WDT
+ * peripheral.
+ *
+ * The WDT can be used to prevent system lock-up if the software becomes
+ * trapped in a deadlock. It can generate a general reset or a processor
+ * reset only. It is clocked by slow clock divided by 128.
+ *
+ * The WDT is running at reset with 16 seconds watchdog period (slow clock at 32.768 kHz)
+ * and external reset generation enabled. The user must either disable it or
+ * reprogram it to meet the application requires.
+ *
+ * To use the WDT, the user could follow these few steps:
+ * 
    
+ * 
  • Enable watchdog with given mode using \ref WDT_Enable().
+ * 
  • Restart the watchdog using \ref WDT_Restart() within the watchdog period.
+ * 

+ *
+ * For more accurate information, please look at the WDT section of the
+ * Datasheet.
+ *
+ * \note
+ * The Watchdog Mode Register (WDT_MR) can be written only once.\n
+ *
+ * Related files :\n
+ * \ref wdt.c\n
+ * \ref wdt.h.\n
+ */
+/*@{*/
+/*@}*/
+
+/*---------------------------------------------------------------------------
+ *        Headers
+ *---------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include 
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Enable watchdog with given mode.
+ *
+ * \note The Watchdog Mode Register (WDT_MR) can be written only once.
+ * Only a processor reset resets it.
+ *
+ * \param dwMode   WDT mode to be set
+ */
+extern void WDT_Enable( Wdt* pWDT, uint32_t dwMode )
+{
+    pWDT->WDT_MR = dwMode ;
+}
+
+/**
+ * \brief Disable watchdog.
+ *
+ * \note The Watchdog Mode Register (WDT_MR) can be written only once.
+ * Only a processor reset resets it.
+ */
+extern void WDT_Disable( Wdt* pWDT )
+{
+    pWDT->WDT_MR = WDT_MR_WDDIS;
+}
+
+/**
+ * \brief Watchdog restart.
+ */
+extern void WDT_Restart( Wdt* pWDT )
+{
+    pWDT->WDT_CR = 0xA5000001;
+}
+
+/**
+ * \brief Watchdog get status.
+ */
+extern uint32_t WDT_GetStatus( Wdt* pWDT )
+{
+    return (pWDT->WDT_SR & 0x3) ;
+}
+
+/**
+ * \brief Watchdog get period.
+ *
+ * \param dwMs   desired watchdog period in millisecond.
+ */
+extern uint32_t WDT_GetPeriod( uint32_t dwMs )
+{
+    if ( (dwMs < 4) || (dwMs > 16000) )
+    {
+        return 0 ;
+    }
+    return ((dwMs << 8) / 1000) ;
+}
diff --git a/hardware/sam/variants/arduino_due/1661fa.pdf b/hardware/sam/variants/arduino_due/1661fa.pdf
new file mode 100644
index 000000000..bda8df4cb
Binary files /dev/null and b/hardware/sam/variants/arduino_due/1661fa.pdf differ
diff --git a/hardware/sam/variants/arduino_due/Arduino_ZZZ_U01.pdf b/hardware/sam/variants/arduino_due/Arduino_ZZZ_U01.pdf
new file mode 100644
index 000000000..0fe138c7a
Binary files /dev/null and b/hardware/sam/variants/arduino_due/Arduino_ZZZ_U01.pdf differ
diff --git a/hardware/sam/variants/arduino_due/build_gcc/Makefile b/hardware/sam/variants/arduino_due/build_gcc/Makefile
new file mode 100644
index 000000000..6851bdaa8
--- /dev/null
+++ b/hardware/sam/variants/arduino_due/build_gcc/Makefile
@@ -0,0 +1,42 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Makefile for compiling libboard
+BOARD = 
+
+SUBMAKE_OPTIONS=--no-builtin-rules --no-builtin-variables
+
+#-------------------------------------------------------------------------------
+# Rules
+#-------------------------------------------------------------------------------
+
+all: arduino_due
+
+.PHONY: arduino_due
+arduino_due:
+	@echo --- Making arduino_due
+	@$(MAKE) DEBUG=1 $(SUBMAKE_OPTIONS) -f libvariant_arduino_due.mk
+#	@$(MAKE) $(SUBMAKE_OPTIONS) -f libvariant_arduino_due.mk
+
+.PHONY: clean
+clean:
+	@echo --- Cleaning arduino_due
+	@$(MAKE) DEBUG=1 $(SUBMAKE_OPTIONS) -f libvariant_arduino_due.mk $@
+#	@$(MAKE) $(SUBMAKE_OPTIONS) -f libvariant_arduino_due.mk $@
+
+
diff --git a/hardware/sam/variants/arduino_due/build_gcc/debug.mk b/hardware/sam/variants/arduino_due/build_gcc/debug.mk
new file mode 100644
index 000000000..d0716744a
--- /dev/null
+++ b/hardware/sam/variants/arduino_due/build_gcc/debug.mk
@@ -0,0 +1,25 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Optimization level
+# -O1 Optimize
+# -O2 Optimize even more
+# -O3 Optimize yet more
+# -O0 Reduce compilation time and make debugging produce the expected results
+# -Os Optimize for size
+OPTIMIZATION = -g -O0 -DDEBUG
diff --git a/hardware/sam/variants/arduino_due/build_gcc/gcc.mk b/hardware/sam/variants/arduino_due/build_gcc/gcc.mk
new file mode 100644
index 000000000..ebbf6d3c0
--- /dev/null
+++ b/hardware/sam/variants/arduino_due/build_gcc/gcc.mk
@@ -0,0 +1,81 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Tool suffix when cross-compiling
+#CROSS_COMPILE = ../../../../tools/CodeSourcery_arm/bin/arm-none-eabi-
+CROSS_COMPILE = $(ARM_GCC_TOOLCHAIN)/arm-none-eabi-
+
+# Compilation tools
+AR = $(CROSS_COMPILE)ar
+CC = $(CROSS_COMPILE)gcc
+CXX = $(CROSS_COMPILE)g++
+AS = $(CROSS_COMPILE)as
+#LD = $(CROSS_COMPILE)ld
+#SIZE = $(CROSS_COMPILE)size
+NM = $(CROSS_COMPILE)nm
+#OBJCOPY = $(CROSS_COMPILE)objcopy
+RM=cs-rm -Rf
+SEP=\\
+
+# ---------------------------------------------------------------------------------------
+# C Flags
+
+CFLAGS += -Wall -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int
+CFLAGS += -Werror-implicit-function-declaration -Wmain -Wparentheses
+CFLAGS += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused
+CFLAGS += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef
+CFLAGS += -Wshadow -Wpointer-arith -Wbad-function-cast -Wwrite-strings
+CFLAGS += -Wsign-compare -Waggregate-return -Wstrict-prototypes
+CFLAGS += -Wmissing-prototypes -Wmissing-declarations
+CFLAGS += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations
+CFLAGS += -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long
+CFLAGS += -Wunreachable-code
+CFLAGS += -Wcast-align
+#CFLAGS += -Wmissing-noreturn
+#CFLAGS += -Wconversion
+
+CFLAGS += --param max-inline-insns-single=500 -mcpu=cortex-m3 -mthumb -mlong-calls -ffunction-sections -nostdlib 
+CFLAGS += $(OPTIMIZATION) $(INCLUDES) -D$(CHIP) -D$(VARIANT)
+
+# To reduce application size use only integer printf function.
+CFLAGS += -Dprintf=iprintf
+
+# ---------------------------------------------------------------------------------------
+# CPP Flags
+
+CPPFLAGS += -Wall -Wchar-subscripts -Wcomment -Wformat=2
+CPPFLAGS += -Wmain -Wparentheses -Wcast-align -Wunreachable-code
+CPPFLAGS += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused
+CPPFLAGS += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef
+CPPFLAGS += -Wshadow -Wpointer-arith -Wwrite-strings
+CPPFLAGS += -Wsign-compare -Waggregate-return -Wmissing-declarations
+CPPFLAGS += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations
+CPPFLAGS += -Wpacked -Wredundant-decls -Winline -Wlong-long
+#CPPFLAGS += -Wmissing-noreturn
+#CPPFLAGS += -Wconversion
+
+CPPFLAGS += --param max-inline-insns-single=500 -mcpu=cortex-m3 -mthumb -mlong-calls -ffunction-sections -fno-rtti -fno-exceptions
+CPPFLAGS += $(OPTIMIZATION) $(INCLUDES) -D$(CHIP)
+
+# To reduce application size use only integer printf function.
+CPPFLAGS += -Dprintf=iprintf
+
+# ---------------------------------------------------------------------------------------
+# ASM Flags
+
+ASFLAGS = -mcpu=cortex-m3 -mthumb -Wall -g $(OPTIMIZATION) $(INCLUDES)
diff --git a/hardware/sam/variants/arduino_due/build_gcc/libvariant_arduino_due.mk b/hardware/sam/variants/arduino_due/build_gcc/libvariant_arduino_due.mk
new file mode 100644
index 000000000..f4d5965f3
--- /dev/null
+++ b/hardware/sam/variants/arduino_due/build_gcc/libvariant_arduino_due.mk
@@ -0,0 +1,174 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Makefile for compiling libArduino
+.SUFFIXES: .o .a .c .s
+
+CHIP=__SAM3U4E__
+VARIANT=arduino_due
+LIBNAME=libvariant_$(VARIANT)
+TOOLCHAIN=gcc
+
+#-------------------------------------------------------------------------------
+# Path
+#-------------------------------------------------------------------------------
+
+# Output directories
+OUTPUT_BIN = ../../../cores/sam
+
+# Libraries
+PROJECT_BASE_PATH = ..
+SYSTEM_PATH = ../../../system
+CMSIS_PATH = $(SYSTEM_PATH)/CMSIS/Include
+ARDUINO_PATH = ../../../cores/sam
+VARIANT_BASE_PATH = ../../../variants
+VARIANT_PATH = ../../../variants/$(VARIANT)
+VARIANT_COMMON_PATH = ../../common
+
+#-------------------------------------------------------------------------------
+# Files
+#-------------------------------------------------------------------------------
+
+vpath %.h $(PROJECT_BASE_PATH) $(SYSTEM_PATH) $(VARIANT_PATH) $(VARIANT_COMMON_PATH)
+#vpath %.c $(PROJECT_BASE_PATH) $(VARIANT_PATH)
+vpath %.cpp $(PROJECT_BASE_PATH) $(PROJECT_BASE_PATH) $(VARIANT_COMMON_PATH)
+
+VPATH+=$(PROJECT_BASE_PATH)
+
+INCLUDES = 
+#INCLUDES += -I$(PROJECT_BASE_PATH)
+INCLUDES += -I$(ARDUINO_PATH)
+INCLUDES += -I$(SYSTEM_PATH)
+INCLUDES += -I$(SYSTEM_PATH)/libsam
+INCLUDES += -I$(VARIANT_BASE_PATH)
+INCLUDES += -I$(VARIANT_PATH)
+INCLUDES += -I$(CMSIS_PATH)
+
+#-------------------------------------------------------------------------------
+ifdef DEBUG
+include debug.mk
+else
+include release.mk
+endif
+
+#-------------------------------------------------------------------------------
+# Tools
+#-------------------------------------------------------------------------------
+
+include $(TOOLCHAIN).mk
+
+#-------------------------------------------------------------------------------
+ifdef DEBUG
+OUTPUT_OBJ=debug
+OUTPUT_LIB_POSTFIX=dbg
+else
+OUTPUT_OBJ=release
+OUTPUT_LIB_POSTFIX=rel
+endif
+
+OUTPUT_LIB=$(LIBNAME)_$(TOOLCHAIN)_$(OUTPUT_LIB_POSTFIX).a
+OUTPUT_PATH=$(OUTPUT_OBJ)_$(VARIANT)
+
+#-------------------------------------------------------------------------------
+# C source files and objects
+#-------------------------------------------------------------------------------
+C_SRC=$(wildcard $(PROJECT_BASE_PATH)/*.c)
+
+C_OBJ_TEMP = $(patsubst %.c, %.o, $(notdir $(C_SRC)))
+
+# during development, remove some files
+C_OBJ_FILTER=
+
+C_OBJ=$(filter-out $(C_OBJ_FILTER), $(C_OBJ_TEMP))
+
+#-------------------------------------------------------------------------------
+# CPP source files and objects
+#-------------------------------------------------------------------------------
+CPP_SRC=$(wildcard $(PROJECT_BASE_PATH)/*.cpp)
+CPP_SRC+=$(wildcard $(VARIANT_COMMON_PATH)/*.cpp)
+
+CPP_OBJ_TEMP = $(patsubst %.cpp, %.o, $(notdir $(CPP_SRC)))
+
+# during development, remove some files
+CPP_OBJ_FILTER=
+
+CPP_OBJ=$(filter-out $(CPP_OBJ_FILTER), $(CPP_OBJ_TEMP))
+
+#-------------------------------------------------------------------------------
+# Assembler source files and objects
+#-------------------------------------------------------------------------------
+A_SRC=$(wildcard $(PROJECT_BASE_PATH)/*.s)
+
+A_OBJ_TEMP=$(patsubst %.s, %.o, $(notdir $(A_SRC)))
+
+# during development, remove some files
+A_OBJ_FILTER=
+
+A_OBJ=$(filter-out $(A_OBJ_FILTER), $(A_OBJ_TEMP))
+
+#-------------------------------------------------------------------------------
+# Rules
+#-------------------------------------------------------------------------------
+all: $(VARIANT)
+
+$(VARIANT): create_output $(OUTPUT_LIB)
+
+.PHONY: create_output
+create_output:
+	@echo --- Preparing $(VARIANT) files in $(OUTPUT_PATH) $(OUTPUT_BIN) 
+	@echo -------------------------
+	@echo *$(INCLUDES)
+	@echo -------------------------
+	@echo *$(C_SRC)
+	@echo -------------------------
+	@echo *$(C_OBJ)
+	@echo -------------------------
+	@echo *$(addprefix $(OUTPUT_PATH)/, $(C_OBJ))
+	@echo -------------------------
+	@echo *$(CPP_SRC)
+	@echo -------------------------
+	@echo *$(CPP_OBJ)
+	@echo -------------------------
+	@echo *$(addprefix $(OUTPUT_PATH)/, $(CPP_OBJ))
+	@echo -------------------------
+	@echo *$(A_SRC)
+	@echo -------------------------
+
+	-@mkdir $(OUTPUT_PATH) 1>NUL 2>&1
+
+$(addprefix $(OUTPUT_PATH)/,$(C_OBJ)): $(OUTPUT_PATH)/%.o: %.c
+#	@$(CC) -v -c $(CFLAGS) $< -o $@
+	@$(CC) -c $(CFLAGS) $< -o $@
+
+$(addprefix $(OUTPUT_PATH)/,$(CPP_OBJ)): $(OUTPUT_PATH)/%.o: %.cpp
+#	@$(CC) -c $(CPPFLAGS) $< -o $@
+	@$(CC) -xc++ -c $(CPPFLAGS) $< -o $@
+
+$(addprefix $(OUTPUT_PATH)/,$(A_OBJ)): $(OUTPUT_PATH)/%.o: %.s
+	@$(AS) -c $(ASFLAGS) $< -o $@
+
+$(OUTPUT_LIB): $(addprefix $(OUTPUT_PATH)/, $(C_OBJ)) $(addprefix $(OUTPUT_PATH)/, $(CPP_OBJ)) $(addprefix $(OUTPUT_PATH)/, $(A_OBJ))
+	@$(AR) -v -r "$(OUTPUT_BIN)/$@" $^
+	@$(NM) "$(OUTPUT_BIN)/$@" > "$(OUTPUT_BIN)/$@.txt"
+
+
+.PHONY: clean
+clean:
+	@echo --- Cleaning $(VARIANT) files [$(OUTPUT_PATH)$(SEP)*.o]
+	-@$(RM) $(OUTPUT_PATH) 1>NUL 2>&1
+	-@$(RM) $(OUTPUT_BIN)/$(OUTPUT_LIB) 1>NUL 2>&1
diff --git a/hardware/sam/variants/arduino_due/build_gcc/release.mk b/hardware/sam/variants/arduino_due/build_gcc/release.mk
new file mode 100644
index 000000000..0d15157f4
--- /dev/null
+++ b/hardware/sam/variants/arduino_due/build_gcc/release.mk
@@ -0,0 +1,25 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Optimization level
+# -O1 Optimize
+# -O2 Optimize even more
+# -O3 Optimize yet more
+# -O0 Reduce compilation time and make debugging produce the expected results
+# -Os Optimize for size
+OPTIMIZATION = -Os
diff --git a/hardware/sam/variants/arduino_due/debug_scripts/gcc/arduino_due_flash.gdb b/hardware/sam/variants/arduino_due/debug_scripts/gcc/arduino_due_flash.gdb
new file mode 100644
index 000000000..c912752bc
--- /dev/null
+++ b/hardware/sam/variants/arduino_due/debug_scripts/gcc/arduino_due_flash.gdb
@@ -0,0 +1,31 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in flash.
+#
+
+# define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+# Reset the chip to get to a known state
+monitor reset
+
+# Select flash device
+monitor flash device = AT91SAM3U4E
+# Enable flash download and flash breakpoints
+monitor flash download = 1
+# Load the program
+load
+
+# Reset peripheral  (RSTC_CR)
+set *0x400e1200 = 0xA5000004
+
+# Initializing PC and stack pointer
+mon reg sp=(0x80000)
+set *0x80004 = *0x80004 & 0xFFFFFFFE
+mon reg pc=(0x80004)
+info reg
+
+# end of 'reset' command
+end
diff --git a/hardware/sam/variants/arduino_due/debug_scripts/gcc/arduino_due_sram.gdb b/hardware/sam/variants/arduino_due/debug_scripts/gcc/arduino_due_sram.gdb
new file mode 100644
index 000000000..c7cc015ba
--- /dev/null
+++ b/hardware/sam/variants/arduino_due/debug_scripts/gcc/arduino_due_sram.gdb
@@ -0,0 +1,23 @@
+#*************************************************
+#
+#  Connect to J-Link and debug application in sram on SAM3U
+#
+# Note:
+#     First,users should do Step1 and Step2 according to your project,
+#     then do Step3.
+
+# Step1: Connect to the J-Link gdb server
+#target remote localhost:2331
+#mon reset
+
+# Step2: Load file(eg. getting-started project)
+#load bin/basic-dhrystone-project-at91sam3u-ek-at91sam3u4-sram.elf
+#symbol-file bin/basic-dhrystone-project-at91sam3u-ek-at91sam3u4-sram.elf
+
+# Step3: Initializing PC and stack pointer
+# Perpheral reset RSTC_CR
+set *0x400e1200 = 0xA5000004
+# Modify pc value to even before writing pc register
+mon reg sp=(0x20000000)
+set *0x20000004 = *0x20000004 & 0xFFFFFFFE
+mon reg pc=(0x20000004)
diff --git a/hardware/sam/variants/arduino_due/debug_scripts/iar/arduino_due_flash.mac b/hardware/sam/variants/arduino_due/debug_scripts/iar/arduino_due_flash.mac
new file mode 100644
index 000000000..959583582
--- /dev/null
+++ b/hardware/sam/variants/arduino_due/debug_scripts/iar/arduino_due_flash.mac
@@ -0,0 +1,44 @@
+// ---------------------------------------------------------
+//   ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ---------------------------------------------------------
+// The software is delivered "AS IS" without warranty or
+// condition of any  kind, either express, implied or
+// statutory. This includes without limitation any warranty
+// or condition with respect to merchantability or fitness
+// for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ---------------------------------------------------------
+//  File: at91sam3u-ek-flash.mac
+//  User setup file for CSPY debugger.
+// ---------------------------------------------------------
+__var __mac_i;
+__var __mac_pt;
+
+/*********************************************************************
+*
+*       execUserReset()
+*/
+execUserReset()
+{
+    __message "------------------------------ execUserReset ---------------------------------";
+    __message "-------------------------------Set PC Reset ----------------------------------";
+
+    __hwReset(0);
+
+    // perpheral reset RSTC_CR
+    __writeMemory32(0xA5000004,0x400e1200,"Memory");
+}
+
+/*********************************************************************
+*
+*       execUserPreload()
+*/
+execUserPreload()
+{
+    __message "------------------------------ execUserPreload ---------------------------------";
+
+    __hwReset(0);                          //* Hardware Reset: CPU is automatically halted after the reset
+
+    // perpheral reset RSTC_CR
+    __writeMemory32(0xA5000004,0x400e1200,"Memory");
+}
diff --git a/hardware/sam/variants/arduino_due/debug_scripts/iar/arduino_due_sram.mac b/hardware/sam/variants/arduino_due/debug_scripts/iar/arduino_due_sram.mac
new file mode 100644
index 000000000..ba86029d3
--- /dev/null
+++ b/hardware/sam/variants/arduino_due/debug_scripts/iar/arduino_due_sram.mac
@@ -0,0 +1,44 @@
+// ---------------------------------------------------------
+//   ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ---------------------------------------------------------
+// The software is delivered "AS IS" without warranty or
+// condition of any  kind, either express, implied or
+// statutory. This includes without limitation any warranty
+// or condition with respect to merchantability or fitness
+// for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ---------------------------------------------------------
+//  File: at91sam3u-ek-sram.mac
+//  User setup file for CSPY debugger.
+// ---------------------------------------------------------
+__var __mac_i;
+__var __mac_pt;
+
+/*********************************************************************
+*
+*       execUserReset()
+*/
+execUserReset()
+{
+    __message "------------------------------ execUserReset ---------------------------------";
+    __message "-------------------------------Set PC Reset ----------------------------------";
+
+     //__hwReset(50);
+
+    // perpheral reset RSTC_CR
+    __writeMemory32(0xA5000004,0x400e1200,"Memory");
+}
+
+/*********************************************************************
+*
+*       execUserPreload()
+*/
+execUserPreload()
+{
+    __message "------------------------------ execUserPreload ---------------------------------";
+
+    __hwReset(0);                          //* Hardware Reset: CPU is automatically halted after the reset
+    
+    // perpheral reset RSTC_CR
+    __writeMemory32(0xA5000004,0x400e1200,"Memory");
+}
diff --git a/hardware/sam/variants/arduino_due/linker_scripts/gcc/flash.ld b/hardware/sam/variants/arduino_due/linker_scripts/gcc/flash.ld
new file mode 100644
index 000000000..c79e630a5
--- /dev/null
+++ b/hardware/sam/variants/arduino_due/linker_scripts/gcc/flash.ld
@@ -0,0 +1,150 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ *      Linker script for running in internal FLASH on the SAM3U4
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (W!RX) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
+	flash1 (W!RX) : ORIGIN = 0x00100000, LENGTH = 0x00020000 /* Flash1, 128K */
+	sram0  (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* Sram0, 32K */
+	sram1  (W!RX) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
+	rom (rx)    : ORIGIN = ORIGIN(flash1)-LENGTH(flash0), LENGTH = LENGTH(flash0)+LENGTH(flash1) /* Flash, 256K */
+	ram (rwx)   : ORIGIN = ORIGIN( sram1)-LENGTH( sram0), LENGTH = LENGTH( sram0)+LENGTH( sram1) /* sram, 48K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = 0x2000;
+
+/* Section Definitions */ 
+SECTIONS 
+{ 
+    .text : 
+    { 
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > flash0
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > flash0
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4); 
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > sram0
+
+    /* .bss section which is used for uninitialized data */ 
+    .bss (NOLOAD) :
+    { 
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > sram0
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+         _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > sram1
+
+    . = ALIGN(4); 
+    _end = . ; 
+}
diff --git a/hardware/sam/variants/arduino_due/linker_scripts/gcc/sram.ld b/hardware/sam/variants/arduino_due/linker_scripts/gcc/sram.ld
new file mode 100644
index 000000000..c8e21ad30
--- /dev/null
+++ b/hardware/sam/variants/arduino_due/linker_scripts/gcc/sram.ld
@@ -0,0 +1,150 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ *      Linker script for running in internal SRAM on the SAM3U4
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (W!RX) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
+	flash1 (W!RX) : ORIGIN = 0x00100000, LENGTH = 0x00020000 /* Flash1, 128K */
+	sram0  (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* Sram0, 32K */
+	sram1  (W!RX) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
+	rom (rx)    : ORIGIN = ORIGIN(flash1)-LENGTH(flash0), LENGTH = LENGTH(flash0)+LENGTH(flash1) /* Flash, 256K */
+	ram (rwx)   : ORIGIN = ORIGIN( sram1)-LENGTH( sram0), LENGTH = LENGTH( sram0)+LENGTH( sram1) /* sram, 48K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = 0x800;
+
+/* Section Definitions */ 
+SECTIONS 
+{ 
+    .text : 
+    { 
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > sram0
+
+    . = ALIGN(4); 
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > sram1
+
+    /* .bss section which is used for uninitialized data */ 
+    .bss (NOLOAD) :
+    { 
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > sram1
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+         _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > sram1
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > sram1
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4); 
+    _end = . ; 
+}
diff --git a/hardware/sam/variants/arduino_due/linker_scripts/iar/flash.icf b/hardware/sam/variants/arduino_due/linker_scripts/iar/flash.icf
new file mode 100644
index 000000000..956230fbd
--- /dev/null
+++ b/hardware/sam/variants/arduino_due/linker_scripts/iar/flash.icf
@@ -0,0 +1,49 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x00080000; /*Add for CMSIS*/
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM0_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM0_end__    = 0x20007FFF;
+define symbol __ICFEDIT_region_RAM1_start__  = 0x20080000;
+define symbol __ICFEDIT_region_RAM1_end__    = 0x20083FFF;
+define symbol __ICFEDIT_region_ROM0_start__  = 0x00080000;
+define symbol __ICFEDIT_region_ROM0_end__    = 0x0009FFFF;
+define symbol __ICFEDIT_region_ROM1_start__  = 0x00100000;
+define symbol __ICFEDIT_region_ROM1_end__    = 0x0011FFFF;
+/*-Sizes-*/
+/*define symbol __ICFEDIT_size_cstack__        = 0x1000;*//*for nandflash*/
+define symbol __ICFEDIT_size_cstack__        = 0x2000;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/*-Specials-*/
+/*define symbol __ICFEDIT_region_RAM_VECT_start__ = __ICFEDIT_region_RAM0_start__;*/ /*Referenced for CMSIS*/
+/*define symbol __ICFEDIT_size_vectors__          = 0x100;*/ /*Referenced for CMSIS*/
+/*-Exports-*/
+/*export symbol __ICFEDIT_region_RAM_VECT_start__;*/
+export symbol __ICFEDIT_vector_start__; /*Add for CMSIS*/
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+/*define region RAM_VECT_region = mem:[from __ICFEDIT_region_RAM_VECT_start__ size __ICFEDIT_size_vectors__];*/ /*Referenced for CMSIS*/
+/*define region RAM0_region     = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__];*/ /*Referenced for CMSIS*/
+define region RAM0_region     = mem:[from __ICFEDIT_region_RAM0_start__ to __ICFEDIT_region_RAM0_end__];
+define region RAM1_region     = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];
+/*define region RAM_region      = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__] |
+                                mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];*/ /*Referenced for CMSIS*/
+define region ROM0_region     = mem:[from __ICFEDIT_region_ROM0_start__ to __ICFEDIT_region_ROM0_end__];
+define region ROM1_region     = mem:[from __ICFEDIT_region_ROM1_start__ to __ICFEDIT_region_ROM1_end__];
+
+/*define block RamVect   with alignment = 8, size = __ICFEDIT_size_vectors__  { };*/
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+/*place at start of ROM0_region { readonly section .vectors };*/ /*Referenced for CMSIS*/
+place at address mem:__ICFEDIT_vector_start__ { readonly section .intvec }; /*Add for CMSIS*/
+place in ROM0_region          { readonly };
+place in RAM0_region          { readwrite, block HEAP };
+place in RAM1_region          { block CSTACK }; /* for nandflash*/
+/*place in RAM_VECT_region      { block RamVect };*/ /*Referenced for CMSIS*/
\ No newline at end of file
diff --git a/hardware/sam/variants/arduino_due/linker_scripts/iar/sram.icf b/hardware/sam/variants/arduino_due/linker_scripts/iar/sram.icf
new file mode 100644
index 000000000..d7d33537a
--- /dev/null
+++ b/hardware/sam/variants/arduino_due/linker_scripts/iar/sram.icf
@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM0_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM0_end__    = 0x20007FFF;
+define symbol __ICFEDIT_region_RAM1_start__  = 0x20080000;
+define symbol __ICFEDIT_region_RAM1_end__    = 0x20083FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x900;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/*-Exports-*/
+export symbol __ICFEDIT_vector_start__;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+define region RAM0_region     = mem:[from __ICFEDIT_region_RAM0_start__ to __ICFEDIT_region_RAM0_end__];
+define region RAM1_region     = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];
+/*define region RAM_region      = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__] |
+                                mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];*/
+
+/* define block RamVect   with alignment = 8, size = __ICFEDIT_size_vectors__  { }; */
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_vector_start__ { readonly section .intvec };
+place in RAM0_region          { readonly };
+place in RAM1_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/sam/variants/arduino_due/pins.xls b/hardware/sam/variants/arduino_due/pins.xls
new file mode 100644
index 000000000..d105ee475
Binary files /dev/null and b/hardware/sam/variants/arduino_due/pins.xls differ
diff --git a/hardware/sam/variants/arduino_due/variant.cpp b/hardware/sam/variants/arduino_due/variant.cpp
new file mode 100644
index 000000000..5e531b9d8
--- /dev/null
+++ b/hardware/sam/variants/arduino_due/variant.cpp
@@ -0,0 +1,377 @@
+/*
+  Copyright (c) 2011 Arduino.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include "variant.h"
+
+/*
+ * DUE Board pin   |  PORT
+ * ----------------+--------
+ *   0   RX0       |  PA11
+ *   1   TX0       |  PA12
+ *   2       PWML3 |  PC9
+ *   3       PWMH3 |  PB16
+ *   4       NPCS0 |  PA16
+ *   5       TIOA2 |  PA30
+ *   6       PWMH2 |  PA6
+ *   7       PWML2 |  PC8
+ *   8       PWML1 |  PC7
+ *   9       PWMH1 |  PA5
+ *  10       TIOA0 |  PA1
+ *  11       PWMH0 |  PA4
+ *  12       PWML0 |  PC6
+ *  13             |  PC21
+ *  14   TX3       |  PA22
+ *  15   RX3       |  PA23
+ *  16   TX2       |  PA20
+ *  17   RX2       |  PA21
+ *  18   TX1       |  PA18
+ *  19   RX1       |  PA19
+ *  20   SDA       |  PA24
+ *  21   SCL       |  PA25
+ *  22             |  PC3
+ *  23             |  PC2
+ *  24             |  PC1
+ *  25             |  PC0
+ *  26             |  PB28
+ *  27             |  PB27
+ *  28             |  PB26
+ *  29             |  PB25
+ *  30             |  PB24
+ *  31             |  PB23
+ *  32             |  PB22
+ *  33             |  PB21
+ *  34             |  PB20
+ *  35             |  PB19
+ *  36             |  PB18
+ *  37             |  PB17
+ *  38             |  PA28
+ *  39             |  PA29
+ *  40             |  PC22
+ *  41             |  PA31
+ *  42             |  PC23
+ *  43             |  PB0
+ *  44             |  PC24
+ *  45             |  PB1
+ *  46             |  PC25
+ *  47             |  PB2
+ *  48             |  PC26
+ *  49             |  PB11
+ *  50             |  PB12
+ *  51             |  PB13
+ *  52             |  PC27
+ *  53             |  PA27
+ *  A0             |  PB5
+ *  A1             |  PB6
+ *  A2             |  PB7
+ *  A3             |  PB8
+ *  A4             |  PC28
+ *  A5             |  PC29
+ *  A6             |  PC30
+ *  A7             |  PC31
+ *  A8             |  PB3
+ *  A9             |  PB4
+ * A10             |  PC15
+ * A11             |  PC16
+ * A12             |  PC17
+ * A13             |  PC18
+ * A14             |  This pin is DAC0 output of LTC1661CMS8
+ * A15             |  This pin is DAC1 output of LTC1661CMS8
+ *      SDA1       |  PA9
+ *      SCL1       |  PA10
+ *
+ *
+ * LTC1661CMS8 pin |  PORT
+ * ----------------+--------
+ * #CS/LD          |  PB9
+ *  SCK            |  PB10
+ *  DIN            |  PB14
+ *
+ *
+ * LEDs            |  PORT
+ * ----------------+--------
+ * "TX"            |  PC19
+ * "RX"            |  PC14
+ * "L"             |  PC21
+ */
+
+
+/*
+ * Pins descriptions
+ */
+extern const PinDescription g_APinDescription[]=
+{
+  // 0 .. 53 - Digital pins
+  // ----------------------
+  // 0/1 - UART (Serial)
+  { PIOA, PIO_PA11A_URXD,    ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT,  PIN_ATTR_DIGITAL,                 NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // URXD
+  { PIOA, PIO_PA12A_UTXD,    ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT,  PIN_ATTR_DIGITAL,                 NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // UTXD
+
+  // 2
+  { PIOC, PIO_PC9B_PWML3,    ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM),   NO_ADC, NO_ADC, PWM_CH3, NO_TC    }, // PWML3
+  { PIOB, PIO_PB16B_PWMH3,   ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM),   NO_ADC, NO_ADC, PWM_CH3, NO_TC    }, // PWMH3
+  { PIOC, PIO_PA16A_NPCS0,   ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT,  PIN_ATTR_DIGITAL,                 NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // NPCS0
+
+  // 5
+  { PIOA, PIO_PA30B_TIOA2,   ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_TIMER), NO_ADC, NO_ADC, NO_PWM,  TC0_CHA2 }, // TIOA2
+  { PIOA, PIO_PA6B_PWMH2,    ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM),   NO_ADC, NO_ADC, PWM_CH2, NO_TC    }, // PWMH2
+  { PIOC, PIO_PC8B_PWML2,    ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM),   NO_ADC, NO_ADC, PWM_CH2, NO_TC    }, // PWML2
+  { PIOC, PIO_PC7B_PWML1,    ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM),   NO_ADC, NO_ADC, PWM_CH1, NO_TC    }, // PWML1
+  { PIOA, PIO_PA5B_PWMH1,    ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM),   NO_ADC, NO_ADC, PWM_CH1, NO_TC    }, // PWMH1
+  // 10
+  { PIOA, PIO_PA1,           ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_TIMER), NO_ADC, NO_ADC, NO_PWM,  TC0_CHA0 }, // TIOA0
+  { PIOA, PIO_PA4B_PWMH0,    ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM),   NO_ADC, NO_ADC, PWM_CH0, NO_TC    }, // PWMH0
+  { PIOC, PIO_PC6B_PWML0,    ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM),   NO_ADC, NO_ADC, PWM_CH0, NO_TC    }, // PWML0
+
+  // 13 - AMBER LED
+  { PIOC, PIO_PC21,          ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 13
+
+  // 14/15 - USART2 (Serial4)
+  { PIOA, PIO_PA22A_TXD2,    ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // TXD2
+  { PIOA, PIO_PA23A_RXD2,    ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // RXD2
+
+  // 16/17 - USART1 (Serial3)
+  { PIOA, PIO_PA20A_TXD1,    ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // TXD1
+  { PIOA, PIO_PA21A_RXD1,    ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // RXD1
+
+  // 18/19 - USART0 (Serial2)
+  { PIOA, PIO_PA18A_TXD0,    ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // TXD0
+  { PIOA, PIO_PA19A_RXD0,    ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // RXD0
+
+  // 20/21 - TWI1
+  { PIOA, PIO_PA24A_TWD1,    ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // TWD1 - SDA0
+  { PIOA, PIO_PA25A_TWCK1,   ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // TWCK1 - SCL0
+
+  // 22
+  { PIOC, PIO_PC3,           ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 22
+  { PIOC, PIO_PC2,           ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 23
+  { PIOC, PIO_PC1,           ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 24
+  { PIOC, PIO_PC0,           ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 25
+
+  // 26
+  { PIOB, PIO_PB28,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 26
+  { PIOB, PIO_PB27,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 27
+  { PIOB, PIO_PB26,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 28
+  { PIOB, PIO_PB25,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 29
+
+  // 30
+  { PIOB, PIO_PB24,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 30
+  { PIOB, PIO_PB23,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 31
+  { PIOB, PIO_PB22,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 32
+  { PIOB, PIO_PB21,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 33
+
+  // 34
+  { PIOB, PIO_PB20,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 34
+  { PIOB, PIO_PB19,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 35
+  { PIOB, PIO_PB18,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 36
+  { PIOB, PIO_PB17,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 37
+
+  // 38
+  { PIOA, PIO_PA28,          ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 38
+  { PIOA, PIO_PA29,          ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 39
+  { PIOC, PIO_PC22,          ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 40
+  { PIOA, PIO_PA31,          ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 41
+
+  // 42
+  { PIOC, PIO_PC23,          ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 42
+  { PIOB, PIO_PB0 ,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 43
+  { PIOC, PIO_PC24,          ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 44
+  { PIOB, PIO_PB1 ,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 45
+
+  // 46
+  { PIOC, PIO_PC25,          ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 46
+  { PIOB, PIO_PB2 ,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 47
+  { PIOC, PIO_PC26,          ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 48
+  { PIOB, PIO_PB11,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 49
+
+  // 50
+  { PIOB, PIO_PB12,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 50
+  { PIOB, PIO_PB13,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 51
+  { PIOC, PIO_PC27,          ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 52
+  { PIOA, PIO_PA27,          ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // PIN 53
+
+  // 54 .. 67 - Analog pins
+  // ----------------------
+  { PIOB, PIO_PB5X1_AD0,     ID_PIOB, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC0,   ADC0,   NO_PWM,  NO_TC    }, // AD0
+  { PIOB, PIO_PB6X1_AD1,     ID_PIOB, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC1,   ADC1,   NO_PWM,  NO_TC    }, // AD1
+  { PIOB, PIO_PB7X1_AD2,     ID_PIOB, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC2,   ADC2,   NO_PWM,  NO_TC    }, // AD2
+  { PIOB, PIO_PB8X1_AD3,     ID_PIOB, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC3,   ADC3,   NO_PWM,  NO_TC    }, // AD3
+  // 58
+  { PIOC, PIO_PC28X1_AD4,    ID_PIOC, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC4,   ADC4,   NO_PWM,  NO_TC    }, // AD4
+  { PIOC, PIO_PC29X1_AD5,    ID_PIOC, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC5,   ADC5,   NO_PWM,  NO_TC    }, // AD5
+  { PIOC, PIO_PC30X1_AD6,    ID_PIOC, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC6,   ADC6,   NO_PWM,  NO_TC    }, // AD6
+  { PIOC, PIO_PC31X1_AD7,    ID_PIOC, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC7,   ADC7,   NO_PWM,  NO_TC    }, // AD7
+  // 62
+  { PIOB, PIO_PB3X1_AD12B2,  ID_PIOB, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC8,   ADC2,   NO_PWM,  NO_TC    }, // AD8
+  { PIOB, PIO_PB4X1_AD12B3,  ID_PIOB, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC9,   ADC3,   NO_PWM,  NO_TC    }, // AD9
+  { PIOC, PIO_PC15X1_AD12B4, ID_PIOC, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC10,  ADC4,   NO_PWM,  NO_TC    }, // AD10
+  { PIOC, PIO_PC16X1_AD12B5, ID_PIOC, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC11,  ADC5,   NO_PWM,  NO_TC    }, // AD11
+  // 66
+  { PIOC, PIO_PC17X1_AD12B6, ID_PIOC, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC12,  ADC6,   NO_PWM,  NO_TC    }, // AD12
+  { PIOC, PIO_PC18X1_AD12B7, ID_PIOC, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC13,  ADC7,   NO_PWM,  NO_TC    }, // AD13
+
+  // 68/69 - TWI0
+  { PIOA, PIO_PA9A_TWD0,     ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // TWD0 - SDA1
+  { PIOA, PIO_PA10A_TWCK0,   ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // TWCK0 - SCL1
+
+  // 70/71/72 - External DAC
+  { PIOB, PIO_PB9,           ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // DAC-CS
+  { PIOB, PIO_PB10,          ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // DAC-SCK
+  { PIOB, PIO_PB14,          ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // DAC-DIN
+
+  // 73/74 - LEDs
+  { PIOC, PIO_PC14,          ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // LED AMBER RXL
+  { PIOC, PIO_PC19,          ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // LED AMBER TXL
+
+  // 75/76/77 - SPI
+  { PIOA, PIO_PA13A_MISO,    ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // MISO
+  { PIOA, PIO_PA14A_MOSI,    ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // MOSI
+  { PIOA, PIO_PA15A_SPCK,    ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NO_PWM,  NO_TC    }, // SPCK
+
+  // 78 .. 83 - "All pins" masks
+
+  // 78 - TWI0 all pins
+  { PIOA, PIO_PA9A_TWD0|PIO_PA10A_TWCK0, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_COMBO), NO_ADC, NO_ADC, NO_PWM, NO_TC },
+  // 79 - TWI1 all pins
+  { PIOA, PIO_PA24A_TWD1|PIO_PA25A_TWCK1, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_COMBO), NO_ADC, NO_ADC, NO_PWM, NO_TC },
+  // 80 - UART (Serial) all pins
+  { PIOA, PIO_PA11A_URXD|PIO_PA12A_UTXD, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_COMBO), NO_ADC, NO_ADC, NO_PWM, NO_TC },
+  // 81 - USART0 (Serial2) all pins
+  { PIOA, PIO_PA19A_RXD0|PIO_PA18A_TXD0, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_COMBO), NO_ADC, NO_ADC, NO_PWM, NO_TC },
+  // 82 - USART1 (Serial3) all pins
+  { PIOA, PIO_PA21A_RXD1|PIO_PA20A_TXD1, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_COMBO), NO_ADC, NO_ADC, NO_PWM, NO_TC },
+  // 83 - USART2 (Serial4) all pins
+  { PIOA, PIO_PA23A_RXD2|PIO_PA22A_TXD2, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_COMBO), NO_ADC, NO_ADC, NO_PWM, NO_TC },
+
+  // END
+  { NULL, 0, 0, PIO_NOT_A_PIN, PIO_DEFAULT, 0, NO_ADC, NO_ADC, NO_PWM, NO_TC }
+} ;
+
+/*
+ * UART objects
+ */
+RingBuffer rx_buffer1 ;
+
+UARTClass Serial( UART, UART_IRQn, ID_UART, &rx_buffer1 ) ;
+
+// IT handlers
+void UART_IrqHandler(void)
+{
+  Serial.IrqHandler() ;
+}
+
+// ----------------------------------------------------------------------------
+/*
+ * USART objects
+ */
+RingBuffer rx_buffer2 ;
+RingBuffer rx_buffer3 ;
+RingBuffer rx_buffer4 ;
+
+USARTClass Serial2( USART0, USART0_IRQn, ID_USART0, &rx_buffer2 ) ;
+USARTClass Serial3( USART1, USART1_IRQn, ID_USART1, &rx_buffer3 ) ;
+USARTClass Serial4( USART2, USART2_IRQn, ID_USART2, &rx_buffer4 ) ;
+
+// IT handlers
+void USART0_IrqHandler( void )
+{
+  Serial2.IrqHandler() ;
+}
+
+void USART1_IrqHandler( void )
+{
+  Serial3.IrqHandler() ;
+}
+
+void USART2_IrqHandler( void )
+{
+  Serial4.IrqHandler() ;
+}
+
+// ----------------------------------------------------------------------------
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Should be made in a better way...
+extern void analogOutputInit(void);
+
+/**
+ *
+ */
+extern void init( void )
+{
+  SystemInit() ;
+
+  // Set Systick to 1ms interval, common to all SAM3 variants
+  if ( SysTick_Config( SystemCoreClock / 1000 ) )
+  {
+    // Capture error
+    while ( 1 ) ;
+  }
+
+  // Disable watchdog, common to all SAM variants
+  WDT_Disable( WDT ) ;
+
+  // Initialize Serial port UART, common to all SAM3 variants
+  PIO_Configure(
+    g_APinDescription[PINS_UART].pPort,
+    g_APinDescription[PINS_UART].ulPinType,
+    g_APinDescription[PINS_UART].ulPin,
+    g_APinDescription[PINS_UART].ulPinConfiguration);
+
+  // Initialize Serial ports USART
+  PIO_Configure(
+    g_APinDescription[PINS_USART0].pPort,
+    g_APinDescription[PINS_USART0].ulPinType,
+    g_APinDescription[PINS_USART0].ulPin,
+    g_APinDescription[PINS_USART0].ulPinConfiguration);
+  PIO_Configure(
+    g_APinDescription[PINS_USART1].pPort,
+    g_APinDescription[PINS_USART1].ulPinType,
+    g_APinDescription[PINS_USART1].ulPin,
+    g_APinDescription[PINS_USART1].ulPinConfiguration);
+  PIO_Configure(
+    g_APinDescription[PINS_USART2].pPort,
+    g_APinDescription[PINS_USART2].ulPinType,
+    g_APinDescription[PINS_USART2].ulPin,
+    g_APinDescription[PINS_USART2].ulPinConfiguration);
+
+  // Initialize 10bit Analog Controller
+  PMC_EnablePeripheral( ID_ADC ) ;
+  adc_init( ADC, SystemCoreClock, ADC_FREQ_MAX, ADC_STARTUP ) ;
+  adc_configure_timing( ADC, 15 ) ;
+  adc_configure_trigger( ADC, ADC_TRIG_SW ) ;	
+  adc_disable_interrupt( ADC, 0xFFFFFFFF ) ; /* Disable all adc interrupt. */	
+  adc_disable_channel( ADC, ADC_ALL_CHANNEL ) ;
+
+  // Initialize 12bit Analog Controller
+  PMC_EnablePeripheral( ID_ADC12B ) ;
+  adc12_init( ADC12B, SystemCoreClock, ADC12_FREQ_MAX, ADC12_STARTUP_FAST, 1 ) ;
+  adc12_configure_timing( ADC12B, 15 ) ;
+  adc12_configure_trigger( ADC12B, ADC_TRIG_SW ) ;	
+  adc12_disable_interrupt( ADC12B, 0xFFFFFFFF ) ; /* Disable all adc interrupt. */
+  adc12_disable_channel( ADC12B, ADC_ALL_CHANNEL ) ;
+
+  // Initialize analogOutput module
+  analogOutputInit();
+}
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/hardware/sam/variants/arduino_due/variant.h b/hardware/sam/variants/arduino_due/variant.h
new file mode 100644
index 000000000..b13eb4a3b
--- /dev/null
+++ b/hardware/sam/variants/arduino_due/variant.h
@@ -0,0 +1,174 @@
+/*
+  Copyright (c) 2011 Arduino.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#ifndef _VARIANT_ARDUINO_DUE_
+#define _VARIANT_ARDUINO_DUE_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "Arduino.h"
+#ifdef __cplusplus
+#include "UARTClass.h"
+#include "USARTClass.h"
+#endif
+
+/**
+ * Libc porting layers
+ */
+#if defined (  __GNUC__  ) /* GCC CS3 */
+#    include  /** RedHat Newlib minimal stub */
+#endif
+
+/*----------------------------------------------------------------------------
+ *        Definitions
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------*/
+
+#ifndef arduino_due
+#define arduino_due
+#endif
+
+/** Name of the board */
+#define VARIANT_NAME "ARDUINO_DUE"
+
+/*
+#define VARIANT_REV_A
+#define VARIANT_REV_B
+*/
+
+/** Frequency of the board main oscillator */
+#define VARIANT_MAINOSC           12000000
+
+/** Master clock frequency */
+#define VARIANT_MCK               96000000
+
+/*----------------------------------------------------------------------------
+ *        Pins
+ *----------------------------------------------------------------------------*/
+
+// Number of pins defined in PinDescription array
+#define PINS_COUNT           (84u)
+
+// LEDs
+#define PIN_LED_13           (13u)
+#define PIN_LED_RXL          (73u)
+#define PIN_LED_TXL          (74u)
+#define PIN_LED              PIN_LED_13
+#define PIN_LED2             PIN_LED_RXL
+#define PIN_LED3             PIN_LED_TXL
+
+/*
+ * SPI Interfaces
+ */
+#define SPI_INTERFACES_COUNT 1
+
+#define SPI_INTERFACE        SPI
+#define SPI_INTERFACE_ID     ID_SPI
+#define PIN_SPI_SS           (4u)
+#define PIN_SPI_MOSI         (76u)
+#define PIN_SPI_MISO         (75u)
+#define PIN_SPI_SCK          (77u)
+
+static const uint8_t SS   = 4 ;
+static const uint8_t MOSI = 76 ;
+static const uint8_t MISO = 75 ;
+static const uint8_t SCK  = 77 ;
+
+/*
+ * Wire Interfaces
+ */
+#define WIRE_INTERFACES_COUNT 2
+
+#define PIN_WIRE_SDA         (20u)
+#define PIN_WIRE_SCL         (21u)
+#define WIRE_INTERFACE       TWI1
+#define WIRE_INTERFACE_ID    ID_TWI1
+#define WIRE_ISR_HANDLER     TWI1_IrqHandler
+
+#define PIN_WIRE1_SDA        (68u)
+#define PIN_WIRE1_SCL        (69u)
+#define WIRE1_INTERFACE      TWI0
+#define WIRE1_INTERFACE_ID   ID_TWI0
+#define WIRE1_ISR_HANDLER    TWI0_IrqHandler
+
+/*
+ * UART/USART Interfaces
+ */
+#define PINS_UART            (80u)
+
+#define PINS_USART0          (81u)
+#define PINS_USART1          (82u)
+#define PINS_USART2          (83u)
+
+/*
+ * Analog pins
+ */
+static const uint8_t A0  = 54;
+static const uint8_t A1  = 55;
+static const uint8_t A2  = 56;
+static const uint8_t A3  = 57;
+static const uint8_t A4  = 58;
+static const uint8_t A5  = 59;
+static const uint8_t A6  = 60;
+static const uint8_t A7  = 61;
+static const uint8_t A8  = 62;
+static const uint8_t A9  = 63;
+static const uint8_t A10 = 64;
+static const uint8_t A11 = 65;
+static const uint8_t A12 = 66;
+static const uint8_t A13 = 67;
+// static const uint8_t A14 = ;
+// static const uint8_t A15 = ;
+
+/*
+ * PWM
+ */
+#define PWM_INTERFACE        PWM
+#define PWM_INTERFACE_ID     ID_PWM
+#define PWM_FREQUENCY        1000
+#define PWM_MAX_DUTY_CYCLE   255
+#define PWM_MIN_DUTY_CYCLE   0
+
+/*
+ * TC
+ */
+#define TC_INTERFACE        TC0
+#define TC_INTERFACE_ID     ID_TC0
+#define TC_FREQUENCY        1000
+#define TC_MAX_DUTY_CYCLE   255
+#define TC_MIN_DUTY_CYCLE   0
+
+/*----------------------------------------------------------------------------
+ *        Arduino objects - C++ only
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+
+extern UARTClass Serial ;
+
+extern USARTClass Serial2 ;
+extern USARTClass Serial3 ;
+extern USARTClass Serial4 ;
+
+#endif
+
+#endif /* _VARIANT_ARDUINO_DUE_ */
+
diff --git a/hardware/sam/variants/sam3s_ek/SAM3S-EK_REVB.pdf b/hardware/sam/variants/sam3s_ek/SAM3S-EK_REVB.pdf
new file mode 100644
index 000000000..6f3f55475
Binary files /dev/null and b/hardware/sam/variants/sam3s_ek/SAM3S-EK_REVB.pdf differ
diff --git a/hardware/sam/variants/sam3s_ek/build_gcc/Makefile b/hardware/sam/variants/sam3s_ek/build_gcc/Makefile
new file mode 100644
index 000000000..80f9cc02c
--- /dev/null
+++ b/hardware/sam/variants/sam3s_ek/build_gcc/Makefile
@@ -0,0 +1,42 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Makefile for compiling libboard
+BOARD = 
+
+SUBMAKE_OPTIONS=--no-builtin-rules --no-builtin-variables
+
+#-------------------------------------------------------------------------------
+# Rules
+#-------------------------------------------------------------------------------
+
+all: sam3s_ek
+
+.PHONY: sam3s_ek
+sam3s_ek:
+	@echo --- Making sam3s_ek
+	@$(MAKE) DEBUG=1 $(SUBMAKE_OPTIONS) -f libvariant_sam3s_ek.mk
+#	@$(MAKE) $(SUBMAKE_OPTIONS) -f libvariant_sam3s_ek.mk
+
+.PHONY: clean
+clean:
+	@echo --- Cleaning sam3s_ek
+	@$(MAKE) DEBUG=1 $(SUBMAKE_OPTIONS) -f libvariant_sam3s_ek.mk $@
+#	@$(MAKE) $(SUBMAKE_OPTIONS) -f libvariant_sam3s_ek.mk $@
+
+
diff --git a/hardware/sam/variants/sam3s_ek/build_gcc/debug.mk b/hardware/sam/variants/sam3s_ek/build_gcc/debug.mk
new file mode 100644
index 000000000..d0716744a
--- /dev/null
+++ b/hardware/sam/variants/sam3s_ek/build_gcc/debug.mk
@@ -0,0 +1,25 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Optimization level
+# -O1 Optimize
+# -O2 Optimize even more
+# -O3 Optimize yet more
+# -O0 Reduce compilation time and make debugging produce the expected results
+# -Os Optimize for size
+OPTIMIZATION = -g -O0 -DDEBUG
diff --git a/hardware/sam/variants/sam3s_ek/build_gcc/gcc.mk b/hardware/sam/variants/sam3s_ek/build_gcc/gcc.mk
new file mode 100644
index 000000000..ebbf6d3c0
--- /dev/null
+++ b/hardware/sam/variants/sam3s_ek/build_gcc/gcc.mk
@@ -0,0 +1,81 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Tool suffix when cross-compiling
+#CROSS_COMPILE = ../../../../tools/CodeSourcery_arm/bin/arm-none-eabi-
+CROSS_COMPILE = $(ARM_GCC_TOOLCHAIN)/arm-none-eabi-
+
+# Compilation tools
+AR = $(CROSS_COMPILE)ar
+CC = $(CROSS_COMPILE)gcc
+CXX = $(CROSS_COMPILE)g++
+AS = $(CROSS_COMPILE)as
+#LD = $(CROSS_COMPILE)ld
+#SIZE = $(CROSS_COMPILE)size
+NM = $(CROSS_COMPILE)nm
+#OBJCOPY = $(CROSS_COMPILE)objcopy
+RM=cs-rm -Rf
+SEP=\\
+
+# ---------------------------------------------------------------------------------------
+# C Flags
+
+CFLAGS += -Wall -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int
+CFLAGS += -Werror-implicit-function-declaration -Wmain -Wparentheses
+CFLAGS += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused
+CFLAGS += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef
+CFLAGS += -Wshadow -Wpointer-arith -Wbad-function-cast -Wwrite-strings
+CFLAGS += -Wsign-compare -Waggregate-return -Wstrict-prototypes
+CFLAGS += -Wmissing-prototypes -Wmissing-declarations
+CFLAGS += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations
+CFLAGS += -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long
+CFLAGS += -Wunreachable-code
+CFLAGS += -Wcast-align
+#CFLAGS += -Wmissing-noreturn
+#CFLAGS += -Wconversion
+
+CFLAGS += --param max-inline-insns-single=500 -mcpu=cortex-m3 -mthumb -mlong-calls -ffunction-sections -nostdlib 
+CFLAGS += $(OPTIMIZATION) $(INCLUDES) -D$(CHIP) -D$(VARIANT)
+
+# To reduce application size use only integer printf function.
+CFLAGS += -Dprintf=iprintf
+
+# ---------------------------------------------------------------------------------------
+# CPP Flags
+
+CPPFLAGS += -Wall -Wchar-subscripts -Wcomment -Wformat=2
+CPPFLAGS += -Wmain -Wparentheses -Wcast-align -Wunreachable-code
+CPPFLAGS += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused
+CPPFLAGS += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef
+CPPFLAGS += -Wshadow -Wpointer-arith -Wwrite-strings
+CPPFLAGS += -Wsign-compare -Waggregate-return -Wmissing-declarations
+CPPFLAGS += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations
+CPPFLAGS += -Wpacked -Wredundant-decls -Winline -Wlong-long
+#CPPFLAGS += -Wmissing-noreturn
+#CPPFLAGS += -Wconversion
+
+CPPFLAGS += --param max-inline-insns-single=500 -mcpu=cortex-m3 -mthumb -mlong-calls -ffunction-sections -fno-rtti -fno-exceptions
+CPPFLAGS += $(OPTIMIZATION) $(INCLUDES) -D$(CHIP)
+
+# To reduce application size use only integer printf function.
+CPPFLAGS += -Dprintf=iprintf
+
+# ---------------------------------------------------------------------------------------
+# ASM Flags
+
+ASFLAGS = -mcpu=cortex-m3 -mthumb -Wall -g $(OPTIMIZATION) $(INCLUDES)
diff --git a/hardware/sam/variants/sam3s_ek/build_gcc/libvariant_sam3s_ek.mk b/hardware/sam/variants/sam3s_ek/build_gcc/libvariant_sam3s_ek.mk
new file mode 100644
index 000000000..1af8f3d32
--- /dev/null
+++ b/hardware/sam/variants/sam3s_ek/build_gcc/libvariant_sam3s_ek.mk
@@ -0,0 +1,174 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Makefile for compiling libArduino
+.SUFFIXES: .o .a .c .s
+
+CHIP=__SAM3S4C__
+VARIANT=sam3s_ek
+LIBNAME=libvariant_$(VARIANT)
+TOOLCHAIN=gcc
+
+#-------------------------------------------------------------------------------
+# Path
+#-------------------------------------------------------------------------------
+
+# Output directories
+OUTPUT_BIN = ../../../cores/sam
+
+# Libraries
+PROJECT_BASE_PATH = ..
+SYSTEM_PATH = ../../../system
+CMSIS_PATH = $(SYSTEM_PATH)/CMSIS/Include
+ARDUINO_PATH = ../../../cores/sam
+VARIANT_BASE_PATH = ../../../variants
+VARIANT_PATH = ../../../variants/$(VARIANT)
+VARIANT_COMMON_PATH = ../../common
+
+#-------------------------------------------------------------------------------
+# Files
+#-------------------------------------------------------------------------------
+
+vpath %.h $(PROJECT_BASE_PATH) $(SYSTEM_PATH) $(VARIANT_PATH) $(VARIANT_COMMON_PATH)
+#vpath %.c $(PROJECT_BASE_PATH) $(VARIANT_PATH)
+vpath %.cpp $(PROJECT_BASE_PATH) $(PROJECT_BASE_PATH) $(VARIANT_COMMON_PATH)
+
+VPATH+=$(PROJECT_BASE_PATH)
+
+INCLUDES = 
+#INCLUDES += -I$(PROJECT_BASE_PATH)
+INCLUDES += -I$(ARDUINO_PATH)
+INCLUDES += -I$(SYSTEM_PATH)
+INCLUDES += -I$(SYSTEM_PATH)/libsam
+INCLUDES += -I$(VARIANT_BASE_PATH)
+INCLUDES += -I$(VARIANT_PATH)
+INCLUDES += -I$(CMSIS_PATH)
+
+#-------------------------------------------------------------------------------
+ifdef DEBUG
+include debug.mk
+else
+include release.mk
+endif
+
+#-------------------------------------------------------------------------------
+# Tools
+#-------------------------------------------------------------------------------
+
+include $(TOOLCHAIN).mk
+
+#-------------------------------------------------------------------------------
+ifdef DEBUG
+OUTPUT_OBJ=debug
+OUTPUT_LIB_POSTFIX=dbg
+else
+OUTPUT_OBJ=release
+OUTPUT_LIB_POSTFIX=rel
+endif
+
+OUTPUT_LIB=$(LIBNAME)_$(TOOLCHAIN)_$(OUTPUT_LIB_POSTFIX).a
+OUTPUT_PATH=$(OUTPUT_OBJ)_$(VARIANT)
+
+#-------------------------------------------------------------------------------
+# C source files and objects
+#-------------------------------------------------------------------------------
+C_SRC=$(wildcard $(PROJECT_BASE_PATH)/*.c)
+
+C_OBJ_TEMP = $(patsubst %.c, %.o, $(notdir $(C_SRC)))
+
+# during development, remove some files
+C_OBJ_FILTER=wiring_analog.o wiring_pulse.o
+
+C_OBJ=$(filter-out $(C_OBJ_FILTER), $(C_OBJ_TEMP))
+
+#-------------------------------------------------------------------------------
+# CPP source files and objects
+#-------------------------------------------------------------------------------
+CPP_SRC=$(wildcard $(PROJECT_BASE_PATH)/*.cpp)
+CPP_SRC+=$(wildcard $(VARIANT_COMMON_PATH)/*.cpp)
+
+CPP_OBJ_TEMP = $(patsubst %.cpp, %.o, $(notdir $(CPP_SRC)))
+
+# during development, remove some files
+CPP_OBJ_FILTER=Tone.o
+
+CPP_OBJ=$(filter-out $(CPP_OBJ_FILTER), $(CPP_OBJ_TEMP))
+
+#-------------------------------------------------------------------------------
+# Assembler source files and objects
+#-------------------------------------------------------------------------------
+A_SRC=$(wildcard $(PROJECT_BASE_PATH)/*.s)
+
+A_OBJ_TEMP=$(patsubst %.s, %.o, $(notdir $(A_SRC)))
+
+# during development, remove some files
+A_OBJ_FILTER=
+
+A_OBJ=$(filter-out $(A_OBJ_FILTER), $(A_OBJ_TEMP))
+
+#-------------------------------------------------------------------------------
+# Rules
+#-------------------------------------------------------------------------------
+all: $(VARIANT)
+
+$(VARIANT): create_output $(OUTPUT_LIB)
+
+.PHONY: create_output
+create_output:
+	@echo --- Preparing $(VARIANT) files in $(OUTPUT_PATH) $(OUTPUT_BIN) 
+	@echo -------------------------
+	@echo *$(INCLUDES)
+	@echo -------------------------
+	@echo *$(C_SRC)
+	@echo -------------------------
+	@echo *$(C_OBJ)
+	@echo -------------------------
+	@echo *$(addprefix $(OUTPUT_PATH)/, $(C_OBJ))
+	@echo -------------------------
+	@echo *$(CPP_SRC)
+	@echo -------------------------
+	@echo *$(CPP_OBJ)
+	@echo -------------------------
+	@echo *$(addprefix $(OUTPUT_PATH)/, $(CPP_OBJ))
+	@echo -------------------------
+	@echo *$(A_SRC)
+	@echo -------------------------
+
+	-@mkdir $(OUTPUT_PATH) 1>NUL 2>&1
+
+$(addprefix $(OUTPUT_PATH)/,$(C_OBJ)): $(OUTPUT_PATH)/%.o: %.c
+#	@$(CC) -v -c $(CFLAGS) $< -o $@
+	@$(CC) -c $(CFLAGS) $< -o $@
+
+$(addprefix $(OUTPUT_PATH)/,$(CPP_OBJ)): $(OUTPUT_PATH)/%.o: %.cpp
+#	@$(CC) -c $(CPPFLAGS) $< -o $@
+	@$(CC) -xc++ -c $(CPPFLAGS) $< -o $@
+
+$(addprefix $(OUTPUT_PATH)/,$(A_OBJ)): $(OUTPUT_PATH)/%.o: %.s
+	@$(AS) -c $(ASFLAGS) $< -o $@
+
+$(OUTPUT_LIB): $(addprefix $(OUTPUT_PATH)/, $(C_OBJ)) $(addprefix $(OUTPUT_PATH)/, $(CPP_OBJ)) $(addprefix $(OUTPUT_PATH)/, $(A_OBJ))
+	@$(AR) -v -r "$(OUTPUT_BIN)/$@" $^
+	@$(NM) "$(OUTPUT_BIN)/$@" > "$(OUTPUT_BIN)/$@.txt"
+
+
+.PHONY: clean
+clean:
+	@echo --- Cleaning $(VARIANT) files [$(OUTPUT_PATH)$(SEP)*.o]
+	-@$(RM) $(OUTPUT_PATH) 1>NUL 2>&1
+	-@$(RM) $(OUTPUT_BIN)/$(OUTPUT_LIB) 1>NUL 2>&1
diff --git a/hardware/sam/variants/sam3s_ek/build_gcc/release.mk b/hardware/sam/variants/sam3s_ek/build_gcc/release.mk
new file mode 100644
index 000000000..0d15157f4
--- /dev/null
+++ b/hardware/sam/variants/sam3s_ek/build_gcc/release.mk
@@ -0,0 +1,25 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Optimization level
+# -O1 Optimize
+# -O2 Optimize even more
+# -O3 Optimize yet more
+# -O0 Reduce compilation time and make debugging produce the expected results
+# -Os Optimize for size
+OPTIMIZATION = -Os
diff --git a/hardware/sam/variants/sam3s_ek/build_iar/libvariant_sam3s_ek.ewd b/hardware/sam/variants/sam3s_ek/build_iar/libvariant_sam3s_ek.ewd
new file mode 100644
index 000000000..3ca049b67
--- /dev/null
+++ b/hardware/sam/variants/sam3s_ek/build_iar/libvariant_sam3s_ek.ewd
@@ -0,0 +1,1769 @@
+
+
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+        1
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+        1
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+        
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+    
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+      2
+      
+        0
+        1
+        1
+        
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+    
+      XDS100_ID
+      2
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+        1
+        1
+        
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+    
+      
+        $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+        0
+      
+      
+        $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+        1
+      
+      
+        $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+        0
+      
+      
+        $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin
+        1
+      
+    
+  
+  
+    Release
+    
+      ARM
+    
+    0
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+      
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+      2
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+      2
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+      
+    
+    
+      GDBSERVER_ID
+      2
+      
+        0
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+    
+      IARROM_ID
+      2
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+        1
+        1
+        0
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+      
+    
+    
+      JLINK_ID
+      2
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+      2
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+        0
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+        $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+        0
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+        0
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+        0
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+        $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+        0
+      
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+        $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+        0
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+        $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+        1
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+        $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+        0
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+        1
+      
+    
+  
+
+
+
diff --git a/hardware/sam/variants/sam3s_ek/build_iar/libvariant_sam3s_ek.ewp b/hardware/sam/variants/sam3s_ek/build_iar/libvariant_sam3s_ek.ewp
new file mode 100644
index 000000000..35a44c755
--- /dev/null
+++ b/hardware/sam/variants/sam3s_ek/build_iar/libvariant_sam3s_ek.ewp
@@ -0,0 +1,1824 @@
+
+
+
+  2
+  
+    Debug
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        21
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
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+        
+        
+        
+        
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+        
+        
+        
+        
+        
+        
+      
+    
+    
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+      2
+      
+        28
+        1
+        1
+        
+        
+        
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+        
+        
+        
+        
+        
+        
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+        
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+        
+        
+        
+        
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+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        8
+        1
+        1
+        
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+        
+        
+        
+        
+        
+        
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+        
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+    
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+      OBJCOPY
+      0
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+        1
+        1
+        1
+        
+        
+        
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+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
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+        13
+        1
+        1
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+        1
+        1
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+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        13
+        1
+        0
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        0
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    common
+    
+      $PROJ_DIR$\..\..\common\cortex_handlers.cpp
+    
+    
+      $PROJ_DIR$\..\..\common\UARTClass.cpp
+    
+    
+      $PROJ_DIR$\..\..\common\UARTClass.h
+    
+    
+      $PROJ_DIR$\..\..\common\USARTClass.cpp
+    
+    
+      $PROJ_DIR$\..\..\common\USARTClass.h
+    
+  
+  
+    $PROJ_DIR$\..\pins_arduino.h
+  
+  
+    $PROJ_DIR$\..\variant.cpp
+  
+  
+    $PROJ_DIR$\..\variant.h
+  
+
+
+
diff --git a/hardware/sam/variants/sam3s_ek/debug_scripts/gcc/sam3s_ek_flash.gdb b/hardware/sam/variants/sam3s_ek/debug_scripts/gcc/sam3s_ek_flash.gdb
new file mode 100644
index 000000000..2ce32081b
--- /dev/null
+++ b/hardware/sam/variants/sam3s_ek/debug_scripts/gcc/sam3s_ek_flash.gdb
@@ -0,0 +1,32 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in flash.
+#
+
+# define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+# Reset the chip to get to a known state
+monitor reset
+
+# Select flash device
+monitor flash device = AT91SAM3S4C
+# Enable flash download and flash breakpoints
+monitor flash download = 1
+# Load the program
+load
+
+# Reset peripheral  (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Initializing PC and stack pointer
+mon reg sp=(0x400000)
+set *0x400004 = *0x400004 & 0xFFFFFFFE
+mon reg pc=(0x400004)
+info reg
+
+# end of 'reset' command
+end
+
diff --git a/hardware/sam/variants/sam3s_ek/debug_scripts/gcc/sam3s_ek_sram.gdb b/hardware/sam/variants/sam3s_ek/debug_scripts/gcc/sam3s_ek_sram.gdb
new file mode 100644
index 000000000..019bd0a94
--- /dev/null
+++ b/hardware/sam/variants/sam3s_ek/debug_scripts/gcc/sam3s_ek_sram.gdb
@@ -0,0 +1,27 @@
+#*************************************************
+#
+#  Connect to J-Link and debug application in sram on SAM3S
+#
+# Note:
+#     First, users should modify Step1 and Step2 according to their project,
+#     then do Step3.
+
+# Step1: Connect to the J-Link gdb server
+define reset
+target remote localhost:2331
+monitor reset
+
+# Step2: Load file(eg. getting-started project)
+load
+
+# Step3: Reset peripheral  (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Step4: Initializing PC and stack pointer
+# Modify pc value to even before writing pc register
+mon reg sp=(0x20000000)
+set *0x20000004 = *0x20000004 & 0xFFFFFFFE
+mon reg pc=(0x20000004)
+info reg
+
+end
diff --git a/hardware/sam/variants/sam3s_ek/debug_scripts/iar/sam3s_ek_flash.mac b/hardware/sam/variants/sam3s_ek/debug_scripts/iar/sam3s_ek_flash.mac
new file mode 100644
index 000000000..786914233
--- /dev/null
+++ b/hardware/sam/variants/sam3s_ek/debug_scripts/iar/sam3s_ek_flash.mac
@@ -0,0 +1,42 @@
+// ---------------------------------------------------------
+//   ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ---------------------------------------------------------
+// The software is delivered "AS IS" without warranty or
+// condition of any  kind, either express, implied or
+// statutory. This includes without limitation any warranty
+// or condition with respect to merchantability or fitness
+// for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ---------------------------------------------------------
+//  File: at91sam3s-ek-flash.mac
+//  User setup file for CSPY debugger.
+// ---------------------------------------------------------
+
+/*********************************************************************
+*
+*       execUserReset()
+*/
+execUserReset()
+{
+    __message "------------------------------ execUserReset ---------------------------------";
+    __message "-------------------------------Set PC Reset ----------------------------------";
+
+    __hwReset(0);
+
+    // peripheral reset RSTC_CR
+    __writeMemory32(0xA5000004,0x400e1400,"Memory");
+}
+
+/*********************************************************************
+*
+*       execUserPreload()
+*/
+execUserPreload()
+{
+    __message "------------------------------ execUserPreload ---------------------------------";
+
+    __hwReset(0);                          //* Hardware Reset: CPU is automatically halted after the reset
+
+    // peripheral reset RSTC_CR
+    __writeMemory32(0xA5000004,0x400e1400,"Memory");
+}
diff --git a/hardware/sam/variants/sam3s_ek/debug_scripts/iar/sam3s_ek_sram.mac b/hardware/sam/variants/sam3s_ek/debug_scripts/iar/sam3s_ek_sram.mac
new file mode 100644
index 000000000..94d385add
--- /dev/null
+++ b/hardware/sam/variants/sam3s_ek/debug_scripts/iar/sam3s_ek_sram.mac
@@ -0,0 +1,42 @@
+// ---------------------------------------------------------
+//   ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ---------------------------------------------------------
+// The software is delivered "AS IS" without warranty or
+// condition of any  kind, either express, implied or
+// statutory. This includes without limitation any warranty
+// or condition with respect to merchantability or fitness
+// for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ---------------------------------------------------------
+//  File: at91sam3s-ek-sram.mac
+//  User setup file for CSPY debugger.
+// ---------------------------------------------------------
+
+/*********************************************************************
+*
+*       execUserReset()
+*/
+execUserReset()
+{
+    __message "------------------------------ execUserReset ---------------------------------";
+    __message "-------------------------------Set PC Reset ----------------------------------";
+
+    __hwReset(0);
+
+    // peripheral reset RSTC_CR
+    __writeMemory32(0xA5000004,0x400e1400,"Memory");
+}
+
+/*********************************************************************
+*
+*       execUserPreload()
+*/
+execUserPreload()
+{
+    __message "------------------------------ execUserPreload ---------------------------------";
+
+    __hwReset(0);                          //* Hardware Reset: CPU is automatically halted after the reset
+
+    // peripheral reset RSTC_CR
+    __writeMemory32(0xA5000004,0x400e1400,"Memory");
+}
diff --git a/hardware/sam/variants/sam3s_ek/linker_scripts/README.txt b/hardware/sam/variants/sam3s_ek/linker_scripts/README.txt
new file mode 100644
index 000000000..c2ce9dbf0
--- /dev/null
+++ b/hardware/sam/variants/sam3s_ek/linker_scripts/README.txt
@@ -0,0 +1,9 @@
+files to be used for Arduino API build:
+flash_arduino.ld
+
+files to be used for Arduino Bootloader build:
+flash_arduino_bootloader.ld
+
+files to be used for other uses of board
+flash.ld
+sram.ld
\ No newline at end of file
diff --git a/hardware/sam/variants/sam3s_ek/linker_scripts/gcc/flash.ld b/hardware/sam/variants/sam3s_ek/linker_scripts/gcc/flash.ld
new file mode 100644
index 000000000..c47a2c508
--- /dev/null
+++ b/hardware/sam/variants/sam3s_ek/linker_scripts/gcc/flash.ld
@@ -0,0 +1,140 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ *      Linker script for running in internal FLASH on the ATSAM3S4
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash, 256K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x0000c000 /* sram, 48K */
+}
+
+/* Section Definitions */ 
+SECTIONS 
+{ 
+    .text : 
+    { 
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*) 	      
+        *(.glue_7t) *(.glue_7)		                
+        *(.rodata .rodata* .gnu.linkonce.r.*)		    	                  
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4); 
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */ 
+    .bss (NOLOAD) :
+    { 
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        *(.stack .stack.*)
+    } > ram
+
+    . = ALIGN(4); 
+    _end = . ; 
+}
diff --git a/hardware/sam/variants/sam3s_ek/linker_scripts/gcc/flash_arduino.ld b/hardware/sam/variants/sam3s_ek/linker_scripts/gcc/flash_arduino.ld
new file mode 100644
index 000000000..1900568e9
--- /dev/null
+++ b/hardware/sam/variants/sam3s_ek/linker_scripts/gcc/flash_arduino.ld
@@ -0,0 +1,140 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ *      Linker script for running in internal FLASH on the ATSAM3S4
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00404000, LENGTH = 0x0003c000 /* flash, 240KB = 256K minus 16KB of bootloader */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x0000c000 /* sram, 48KB */
+}
+
+/* Section Definitions */ 
+SECTIONS 
+{ 
+    .text : 
+    { 
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*) 	      
+        *(.glue_7t) *(.glue_7)		                
+        *(.rodata .rodata* .gnu.linkonce.r.*)		    	                  
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4); 
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */ 
+    .bss (NOLOAD) :
+    { 
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        *(.stack .stack.*)
+    } > ram
+
+    . = ALIGN(4); 
+    _end = . ; 
+}
diff --git a/hardware/sam/variants/sam3s_ek/linker_scripts/gcc/flash_arduino_bootloader.ld b/hardware/sam/variants/sam3s_ek/linker_scripts/gcc/flash_arduino_bootloader.ld
new file mode 100644
index 000000000..b1f362548
--- /dev/null
+++ b/hardware/sam/variants/sam3s_ek/linker_scripts/gcc/flash_arduino_bootloader.ld
@@ -0,0 +1,140 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ *      Linker script for running in internal FLASH on the ATSAM3S4
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00004000 /* flash, 16KB */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x0000c000 /* sram, 48KB */
+}
+
+/* Section Definitions */ 
+SECTIONS 
+{ 
+    .text : 
+    { 
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*) 	      
+        *(.glue_7t) *(.glue_7)		                
+        *(.rodata .rodata* .gnu.linkonce.r.*)		    	                  
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4); 
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */ 
+    .bss (NOLOAD) :
+    { 
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        *(.stack .stack.*)
+    } > ram
+
+    . = ALIGN(4); 
+    _end = . ; 
+}
diff --git a/hardware/sam/variants/sam3s_ek/linker_scripts/gcc/sram.ld b/hardware/sam/variants/sam3s_ek/linker_scripts/gcc/sram.ld
new file mode 100644
index 000000000..9c6875554
--- /dev/null
+++ b/hardware/sam/variants/sam3s_ek/linker_scripts/gcc/sram.ld
@@ -0,0 +1,140 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ *      Linker script for running in internal SRAM on the ATSAM3S4
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash, 256K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x0000c000 /* sram, 48K */
+}
+
+/* Section Definitions */ 
+SECTIONS 
+{ 
+    .text : 
+    { 
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*) 	      
+        *(.glue_7t) *(.glue_7)		                
+        *(.rodata .rodata* .gnu.linkonce.r.*)		    	                  
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4); 
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */ 
+    .bss (NOLOAD) :
+    { 
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        *(.stack .stack.*)
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4); 
+    _end = . ; 
+}
diff --git a/hardware/sam/variants/sam3s_ek/linker_scripts/iar/sam3s_ek_flash.icf b/hardware/sam/variants/sam3s_ek/linker_scripts/iar/sam3s_ek_flash.icf
new file mode 100644
index 000000000..d4bb4deb5
--- /dev/null
+++ b/hardware/sam/variants/sam3s_ek/linker_scripts/iar/sam3s_ek_flash.icf
@@ -0,0 +1,28 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x00400000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__    = 0x2000BFFF;
+define symbol __ICFEDIT_region_ROM_start__  = 0x00400000;
+define symbol __ICFEDIT_region_ROM_end__    = 0x0043FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x4000;
+define symbol __ICFEDIT_size_heap__          = 0x2000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+define region RAM_region     = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region     = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_vector_start__ { readonly section .intvec };
+place in ROM_region          { readonly };
+place in RAM_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/sam/variants/sam3s_ek/linker_scripts/iar/sam3s_ek_sram.icf b/hardware/sam/variants/sam3s_ek/linker_scripts/iar/sam3s_ek_sram.icf
new file mode 100644
index 000000000..1666effb4
--- /dev/null
+++ b/hardware/sam/variants/sam3s_ek/linker_scripts/iar/sam3s_ek_sram.icf
@@ -0,0 +1,25 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__    = 0x2000BFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x2000;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+define region RAM_region     = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+/* define block RamVect   with alignment = 8, size = __ICFEDIT_size_vectors__  { }; */
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_vector_start__ { readonly section .intvec };
+place in RAM_region          { readonly, readwrite, block CSTACK, block HEAP };
diff --git a/hardware/sam/variants/sam3s_ek/variant.cpp b/hardware/sam/variants/sam3s_ek/variant.cpp
new file mode 100644
index 000000000..5352e089b
--- /dev/null
+++ b/hardware/sam/variants/sam3s_ek/variant.cpp
@@ -0,0 +1,229 @@
+/*
+  Copyright (c) 2011 Arduino.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include "variant.h"
+
+/*
+ * Pins descriptions
+ */
+extern const PinDescription g_APinDescription[]=
+{
+  // LEDS, 0..2
+#if defined VARIANT_REV_A
+  { PIOC, PIO_PC20, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT }, // LED BLUE
+  { PIOC, PIO_PC21, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT }, // LED GREEN
+  { PIOC, PIO_PC22, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT }, // LED RED
+#elif defined VARIANT_REV_B
+  { PIOA, PIO_PA19, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT }, // LED BLUE
+  { PIOA, PIO_PA20, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT }, // LED GREEN
+  { PIOC, PIO_PC20, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT }, // LED RED
+#else
+#error "No board revision defined"
+#endif
+
+  // Clock 32KHz, 3..4
+  { PIOA, PIO_PA7, ID_PIOA, PIO_NOT_A_PIN, PIO_DEFAULT }, // XIN32
+  { PIOA, PIO_PA8, ID_PIOA, PIO_NOT_A_PIN, PIO_DEFAULT }, // XOUT32
+
+  // Clock 12MHz, 5..6
+  { PIOB, PIO_PB9, ID_PIOB, PIO_NOT_A_PIN, PIO_DEFAULT }, // XIN
+  { PIOB, PIO_PB8, ID_PIOB, PIO_NOT_A_PIN, PIO_DEFAULT }, // XOUT
+
+  // JTAG, 7..10
+  { PIOB, PIO_PB4, ID_PIOB, PIO_NOT_A_PIN, PIO_DEFAULT }, // TDI
+  { PIOB, PIO_PB5, ID_PIOB, PIO_NOT_A_PIN, PIO_DEFAULT }, // TDO
+  { PIOB, PIO_PB6, ID_PIOB, PIO_NOT_A_PIN, PIO_DEFAULT }, // TMS
+  { PIOB, PIO_PB7, ID_PIOB, PIO_NOT_A_PIN, PIO_DEFAULT }, // TCK
+
+  // USB, 11..13
+  { PIOB, PIO_PB10, ID_PIOB, PIO_NOT_A_PIN, PIO_DEFAULT }, // DDM
+  { PIOB, PIO_PB11, ID_PIOB, PIO_NOT_A_PIN, PIO_DEFAULT }, // DDP
+#if defined VARIANT_REV_A
+  { PIOC, PIO_PC23, ID_PIOC, PIO_INPUT, PIO_PULLUP }, // USB_VBUS
+#elif defined VARIANT_REV_B
+  { PIOC, PIO_PC21, ID_PIOC, PIO_INPUT, PIO_PULLUP }, // USB_VBUS
+#else
+#error "No board revision defined"
+#endif
+
+  // UART0 (Serial), 14..16
+  { PIOA, PIO_PA9, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // URXD0
+  { PIOA, PIO_PA10, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // UTXD0
+  { PIOA, PIO_PA9|PIO_PA10, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // All UART0 pins
+
+  // Push buttons, 17..18
+  { PIOB, PIO_PB3, ID_PIOB, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE }, // PB1
+  { PIOC, PIO_PC12, ID_PIOC, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE }, // PB2
+
+  // QTouch Slider, 19..20
+  { PIOA, (PIO_PA0 | PIO_PA2 | PIO_PA4), ID_PIOA, PIO_INPUT, PIO_DEFAULT }, // QTSLIDR SNS
+  { PIOA, (PIO_PA1 | PIO_PA3 | PIO_PA5), ID_PIOA, PIO_INPUT, PIO_DEFAULT }, // QTSLIDR SNSK
+
+  // QTouch Buttons, 21..22
+  { PIOC, (PIO_PC22 | PIO_PC24 | PIO_PC26 | PIO_PC28 | PIO_PC30), ID_PIOC, PIO_INPUT, PIO_DEFAULT }, // KEYS SNS
+  { PIOC, (PIO_PC23 | PIO_PC25 | PIO_PC27 | PIO_PC29 | PIO_PC31), ID_PIOC, PIO_INPUT, PIO_DEFAULT }, // KEYS SNSK
+
+  // MCI (SDCARD), 23..30
+#if defined VARIANT_REV_A
+  { PIOA, PIO_PA15, ID_PIOA, PIO_INPUT, PIO_PULLUP }, // MCI Card Detect
+#elif defined VARIANT_REV_B
+  { PIOA, PIO_PA6, ID_PIOA, PIO_INPUT, PIO_PULLUP }, // MCI Card Detect
+#else
+#error "No board revision defined"
+#endif
+  { PIOA, PIO_PA30, ID_PIOA, PIO_PERIPH_C, PIO_PULLUP }, // MCDA0
+  { PIOA, PIO_PA31, ID_PIOA, PIO_PERIPH_C, PIO_PULLUP }, // MCDA1
+  { PIOA, PIO_PA26, ID_PIOA, PIO_PERIPH_C, PIO_PULLUP }, // MCDA2
+  { PIOA, PIO_PA27, ID_PIOA, PIO_PERIPH_C, PIO_PULLUP }, // MCDA3
+  { PIOA, PIO_PA28, ID_PIOA, PIO_PERIPH_C, PIO_PULLUP }, // MCCDA
+  { PIOA, PIO_PA29, ID_PIOA, PIO_PERIPH_C, PIO_PULLUP }, // MCCK
+
+  { PIOA, PIO_PA26|PIO_PA27|PIO_PA28|PIO_PA29|PIO_PA30|PIO_PA31, ID_PIOA, PIO_PERIPH_C, PIO_PULLUP }, // All MCI Pins
+
+  // SPI, 31..34
+  { PIOA, PIO_PA12A_MISO, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // MISO
+  { PIOA, PIO_PA13A_MOSI, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // MOSI
+  { PIOA, PIO_PA14A_SPCK, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // SPCK
+  { PIOA, PIO_PA11A_NPCS0, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // NPCS0
+
+  // TouchScreen, 35..36
+#if defined VARIANT_REV_A
+  { PIOA, PIO_PA4, ID_PIOA, PIO_INPUT, PIO_PULLUP }, // IRQ_TSC
+  { PIOA, PIO_PA5, ID_PIOA, PIO_INPUT, PIO_PULLUP }, // BUSY_TSC
+#elif defined VARIANT_REV_B
+  { PIOA, PIO_PA16, ID_PIOA, PIO_INPUT, PIO_PULLUP }, // IRQ_TSC
+  { PIOA, PIO_PA17, ID_PIOA, PIO_INPUT, PIO_PULLUP }, // BUSY_TSC
+#else
+#error "No board revision defined"
+#endif
+
+  // USART1, 37..41
+  { PIOA, PIO_PA21A_RXD1, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // RXD1
+  { PIOA, PIO_PA22A_TXD1, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // TXD1
+  { PIOA, PIO_PA24A_RTS1, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // RTS1
+  { PIOA, PIO_PA25A_CTS1, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // CTS1
+  { PIOA, PIO_PA23A_SCK1, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT }, // COM1 ENABLE (MAX232)
+
+  // LCD, 42..47
+  { PIOC, 0xFF, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP }, // EBI Data bus
+  { PIOC, PIO_PC8, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP }, // EBI_NWE
+  { PIOC, PIO_PC11, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP }, // EBI_NRD
+  { PIOC, PIO_PC15, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP }, // LCD CS
+  { PIOC, PIO_PC19, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP }, // LCD RS
+  { PIOC, PIO_PC13, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT }, // LCD BackLight
+
+  { NULL, 0, 0, PIO_NOT_A_PIN, PIO_DEFAULT } // END
+} ;
+
+/*
+ * UART objects
+ */
+RingBuffer rx_buffer1 ;
+RingBuffer tx_buffer1 ;
+RingBuffer rx_buffer2 ;
+RingBuffer tx_buffer2 ;
+
+UARTClass Serial( UART0, UART0_IRQn, ID_UART0, &rx_buffer1, &tx_buffer1 ) ;
+UARTClass Serial2( UART1, UART1_IRQn, ID_UART1, &rx_buffer2, &tx_buffer2 ) ;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// IT handlers
+extern void UART0_IrqHandler( void )
+{
+  Serial.IrqHandler() ;
+}
+
+extern void UART1_IrqHandler( void )
+{
+  Serial2.IrqHandler() ;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+// ----------------------------------------------------------------------------
+/*
+ * USART objects
+ */
+RingBuffer rx_buffer3 ;
+RingBuffer tx_buffer3 ;
+RingBuffer rx_buffer4 ;
+RingBuffer tx_buffer4 ;
+
+USARTClass Serial3( USART0, USART0_IRQn, ID_USART0, &rx_buffer3, &tx_buffer3 ) ;
+USARTClass Serial4( USART1, USART1_IRQn, ID_USART1, &rx_buffer4, &tx_buffer4 ) ;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// IT handlers
+extern void USART0_IrqHandler( void )
+{
+  Serial3.IrqHandler() ;
+}
+
+extern void USART1_IrqHandler( void )
+{
+  Serial4.IrqHandler() ;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+// ----------------------------------------------------------------------------
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ *
+ */
+extern void init( void )
+{
+	SystemInit() ;
+
+    /* Set Systick to 1ms interval, common to all SAM3 variants */
+	if ( SysTick_Config( SystemCoreClock / 1000 ) )
+  {
+    /* Capture error */
+    while ( 1 ) ;
+	}
+
+  /* Disable watchdog, common to all SAM variants */
+  WDT_Disable( WDT ) ;
+
+  // Initialize Serial port UART0, common to all SAM3 variants
+  PIO_Configure( g_APinDescription[PINS_UART].pPort, g_APinDescription[PINS_UART].ulPinType,
+                 g_APinDescription[PINS_UART].ulPin, g_APinDescription[PINS_UART].ulPinConfiguration ) ;
+
+  // Switch off Power LED
+  PIO_Configure( g_APinDescription[PIN_LED_RED].pPort, g_APinDescription[PIN_LED_RED].ulPinType,
+                 g_APinDescription[PIN_LED_RED].ulPin, g_APinDescription[PIN_LED_RED].ulPinConfiguration ) ;
+  PIO_Clear( g_APinDescription[PIN_LED_RED].pPort, g_APinDescription[PIN_LED_RED].ulPin ) ;
+}
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/hardware/sam/variants/sam3s_ek/variant.h b/hardware/sam/variants/sam3s_ek/variant.h
new file mode 100644
index 000000000..b2cb9256e
--- /dev/null
+++ b/hardware/sam/variants/sam3s_ek/variant.h
@@ -0,0 +1,106 @@
+/*
+  Copyright (c) 2011 Arduino.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#ifndef _VARIANT_SAM3S_EK_
+#define _VARIANT_SAM3S_EK_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "Arduino.h"
+#include "UARTClass.h"
+#include "USARTClass.h"
+
+/**
+ * Libc porting layers
+ */
+#if defined (  __GNUC__  ) /* GCC CS3 */
+#    include  /** RedHat Newlib minimal stub */
+#endif
+
+/*----------------------------------------------------------------------------
+ *        Definitions
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------*/
+
+#ifndef sam3s_ek
+#define sam3s_ek
+#endif
+
+/** Name of the board */
+#define VARIANT_NAME "SAM3S-EK"
+
+#define VARIANT_REV_A
+/*
+#define VARIANT_REV_B
+*/
+
+/** Frequency of the board main oscillator */
+#define VARIANT_MAINOSC           12000000
+
+/** Master clock frequency */
+#define VARIANT_MCK               64000000
+
+/*----------------------------------------------------------------------------
+ *        Pins
+ *----------------------------------------------------------------------------*/
+
+#define PIN_LED_BLUE         (0u)
+#define PIN_LED_GREEN        (1u)
+#define PIN_LED_RED          (2u)
+#define PIN_LED              PIN_LED_BLUE
+
+#define PIN_DAC0             (u)
+
+static const uint8_t SS   = 34 ;
+static const uint8_t MOSI = 32 ;
+static const uint8_t MISO = 31 ;
+static const uint8_t SCK  = 33 ;
+
+#define PINS_UART            (16u)
+
+#if defined VARIANT_REV_A
+#  define PIN_TSC_IRQ_WUP_ID (1UL << 3)
+#elif defined VARIANT_REV_B
+#  define PIN_TSC_IRQ_WUP_ID (1UL << 15)
+#else
+#error "No board revision defined"
+#endif
+
+#define BOARD_LCD_PINS              PIN_EBI_DATA_BUS, PIN_EBI_NRD, PIN_EBI_NWE, PIN_EBI_NCS1, PIN_EBI_LCD_RS
+#define BOARD_LCD_BASE              0x61000000 /** Define ILI9325 base address. */
+#define BOARD_LCD_RS                (1 << 1) /** Define ILI9325 register select signal. */
+
+/*----------------------------------------------------------------------------
+ *        Arduino objects - C++ only
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+
+extern UARTClass Serial ;
+extern UARTClass Serial2 ;
+
+extern USARTClass Serial3 ;
+extern USARTClass Serial4 ;
+
+#endif
+
+#endif /* _VARIANT_SAM3S_EK_ */
+
diff --git a/hardware/sam/variants/sam3u_ek/SAM3U-EK_REVC.pdf b/hardware/sam/variants/sam3u_ek/SAM3U-EK_REVC.pdf
new file mode 100644
index 000000000..4f828cf85
Binary files /dev/null and b/hardware/sam/variants/sam3u_ek/SAM3U-EK_REVC.pdf differ
diff --git a/hardware/sam/variants/sam3u_ek/build_gcc/Makefile b/hardware/sam/variants/sam3u_ek/build_gcc/Makefile
new file mode 100644
index 000000000..024445216
--- /dev/null
+++ b/hardware/sam/variants/sam3u_ek/build_gcc/Makefile
@@ -0,0 +1,42 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Makefile for compiling libboard
+BOARD = 
+
+SUBMAKE_OPTIONS=--no-builtin-rules --no-builtin-variables
+
+#-------------------------------------------------------------------------------
+# Rules
+#-------------------------------------------------------------------------------
+
+all: sam3u_ek
+
+.PHONY: sam3u_ek
+sam3u_ek:
+	@echo --- Making sam3u_ek
+	@$(MAKE) DEBUG=1 $(SUBMAKE_OPTIONS) -f libvariant_sam3u_ek.mk
+#	@$(MAKE) $(SUBMAKE_OPTIONS) -f libvariant_sam3u_ek.mk
+
+.PHONY: clean
+clean:
+	@echo --- Cleaning sam3u_ek
+	@$(MAKE) DEBUG=1 $(SUBMAKE_OPTIONS) -f libvariant_sam3u_ek.mk $@
+#	@$(MAKE) $(SUBMAKE_OPTIONS) -f libvariant_sam3u_ek.mk $@
+
+
diff --git a/hardware/sam/variants/sam3u_ek/build_gcc/debug.mk b/hardware/sam/variants/sam3u_ek/build_gcc/debug.mk
new file mode 100644
index 000000000..d0716744a
--- /dev/null
+++ b/hardware/sam/variants/sam3u_ek/build_gcc/debug.mk
@@ -0,0 +1,25 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Optimization level
+# -O1 Optimize
+# -O2 Optimize even more
+# -O3 Optimize yet more
+# -O0 Reduce compilation time and make debugging produce the expected results
+# -Os Optimize for size
+OPTIMIZATION = -g -O0 -DDEBUG
diff --git a/hardware/sam/variants/sam3u_ek/build_gcc/gcc.mk b/hardware/sam/variants/sam3u_ek/build_gcc/gcc.mk
new file mode 100644
index 000000000..34ceef055
--- /dev/null
+++ b/hardware/sam/variants/sam3u_ek/build_gcc/gcc.mk
@@ -0,0 +1,82 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Tool suffix when cross-compiling
+#CROSS_COMPILE = ../../../../tools/CodeSourcery_arm/bin/arm-none-eabi-
+CROSS_COMPILE = $(ARM_GCC_TOOLCHAIN)/arm-none-eabi-
+
+# Compilation tools
+AR = $(CROSS_COMPILE)ar
+CC = $(CROSS_COMPILE)gcc
+CXX = $(CROSS_COMPILE)g++
+AS = $(CROSS_COMPILE)as
+#LD = $(CROSS_COMPILE)ld
+#SIZE = $(CROSS_COMPILE)size
+NM = $(CROSS_COMPILE)nm
+#OBJCOPY = $(CROSS_COMPILE)objcopy
+RM=cs-rm -Rf
+SEP=\\
+
+# ---------------------------------------------------------------------------------------
+# C Flags
+
+CFLAGS += -Wall -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int
+CFLAGS += -Werror-implicit-function-declaration -Wmain -Wparentheses
+CFLAGS += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused
+CFLAGS += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef
+CFLAGS += -Wshadow -Wpointer-arith -Wbad-function-cast -Wwrite-strings
+CFLAGS += -Wsign-compare -Waggregate-return -Wstrict-prototypes
+CFLAGS += -Wmissing-prototypes -Wmissing-declarations
+CFLAGS += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations
+CFLAGS += -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long
+CFLAGS += -Wunreachable-code
+CFLAGS += -Wcast-align
+#CFLAGS += -Wmissing-noreturn
+#CFLAGS += -Wconversion
+
+CFLAGS += --param max-inline-insns-single=500 -mcpu=cortex-m3 -mthumb -mlong-calls -ffunction-sections -nostdlib 
+CFLAGS += $(OPTIMIZATION) $(INCLUDES) -D$(CHIP) -D$(VARIANT)
+
+# To reduce application size use only integer printf function.
+CFLAGS += -Dprintf=iprintf
+
+# ---------------------------------------------------------------------------------------
+# CPP Flags
+
+CPPFLAGS += -Wall -Wchar-subscripts -Wcomment -Wformat=2
+CPPFLAGS += -Wmain -Wparentheses -Wcast-align -Wunreachable-code
+CPPFLAGS += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused
+CPPFLAGS += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef
+CPPFLAGS += -Wshadow -Wpointer-arith -Wwrite-strings
+CPPFLAGS += -Wsign-compare -Waggregate-return -Wmissing-declarations
+CPPFLAGS += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations
+CPPFLAGS += -Wpacked -Wredundant-decls -Winline -Wlong-long
+#CPPFLAGS += -Wmissing-noreturn
+#CPPFLAGS += -Wconversion
+
+# -fno-rtti -fno-exceptions
+CPPFLAGS += --param max-inline-insns-single=500 -mcpu=cortex-m3 -mthumb -mlong-calls -ffunction-sections
+CPPFLAGS += $(OPTIMIZATION) $(INCLUDES) -D$(CHIP)
+
+# To reduce application size use only integer printf function.
+CPPFLAGS += -Dprintf=iprintf
+
+# ---------------------------------------------------------------------------------------
+# ASM Flags
+
+ASFLAGS = -mcpu=cortex-m3 -mthumb -Wall -g $(OPTIMIZATION) $(INCLUDES)
diff --git a/hardware/sam/variants/sam3u_ek/build_gcc/libvariant_sam3u_ek.mk b/hardware/sam/variants/sam3u_ek/build_gcc/libvariant_sam3u_ek.mk
new file mode 100644
index 000000000..8254f3c52
--- /dev/null
+++ b/hardware/sam/variants/sam3u_ek/build_gcc/libvariant_sam3u_ek.mk
@@ -0,0 +1,176 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Makefile for compiling libArduino
+.SUFFIXES: .o .a .c .s
+
+CHIP=__SAM3U4E__
+VARIANT=sam3u_ek
+LIBNAME=libvariant_$(VARIANT)
+TOOLCHAIN=gcc
+
+#-------------------------------------------------------------------------------
+# Path
+#-------------------------------------------------------------------------------
+
+# Output directories
+OUTPUT_BIN = ../../../cores/sam
+
+# Libraries
+PROJECT_BASE_PATH = ..
+SYSTEM_PATH = ../../../system
+CMSIS_PATH = $(SYSTEM_PATH)/CMSIS/Include
+ARDUINO_PATH = ../../../cores/sam
+VARIANT_BASE_PATH = ../../../variants
+VARIANT_PATH = ../../../variants/$(VARIANT)
+#VARIANT_COMMON_PATH = ../../common
+
+#-------------------------------------------------------------------------------
+# Files
+#-------------------------------------------------------------------------------
+
+vpath %.h $(PROJECT_BASE_PATH) $(SYSTEM_PATH) $(VARIANT_PATH) 
+#$(VARIANT_COMMON_PATH)
+#vpath %.c $(PROJECT_BASE_PATH) $(VARIANT_PATH)
+vpath %.cpp $(PROJECT_BASE_PATH) $(PROJECT_BASE_PATH) 
+#$(VARIANT_COMMON_PATH)
+
+VPATH+=$(PROJECT_BASE_PATH)
+
+INCLUDES = 
+#INCLUDES += -I$(PROJECT_BASE_PATH)
+INCLUDES += -I$(ARDUINO_PATH)
+INCLUDES += -I$(SYSTEM_PATH)
+INCLUDES += -I$(SYSTEM_PATH)/libsam
+INCLUDES += -I$(VARIANT_BASE_PATH)
+INCLUDES += -I$(VARIANT_PATH)
+INCLUDES += -I$(CMSIS_PATH)
+
+#-------------------------------------------------------------------------------
+ifdef DEBUG
+include debug.mk
+else
+include release.mk
+endif
+
+#-------------------------------------------------------------------------------
+# Tools
+#-------------------------------------------------------------------------------
+
+include $(TOOLCHAIN).mk
+
+#-------------------------------------------------------------------------------
+ifdef DEBUG
+OUTPUT_OBJ=debug
+OUTPUT_LIB_POSTFIX=dbg
+else
+OUTPUT_OBJ=release
+OUTPUT_LIB_POSTFIX=rel
+endif
+
+OUTPUT_LIB=$(LIBNAME)_$(TOOLCHAIN)_$(OUTPUT_LIB_POSTFIX).a
+OUTPUT_PATH=$(OUTPUT_OBJ)_$(VARIANT)
+
+#-------------------------------------------------------------------------------
+# C source files and objects
+#-------------------------------------------------------------------------------
+C_SRC=$(wildcard $(PROJECT_BASE_PATH)/*.c)
+
+C_OBJ_TEMP = $(patsubst %.c, %.o, $(notdir $(C_SRC)))
+
+# during development, remove some files
+C_OBJ_FILTER=
+
+C_OBJ=$(filter-out $(C_OBJ_FILTER), $(C_OBJ_TEMP))
+
+#-------------------------------------------------------------------------------
+# CPP source files and objects
+#-------------------------------------------------------------------------------
+CPP_SRC=$(wildcard $(PROJECT_BASE_PATH)/*.cpp)
+#CPP_SRC+=$(wildcard $(VARIANT_COMMON_PATH)/*.cpp)
+
+CPP_OBJ_TEMP = $(patsubst %.cpp, %.o, $(notdir $(CPP_SRC)))
+
+# during development, remove some files
+CPP_OBJ_FILTER=
+
+CPP_OBJ=$(filter-out $(CPP_OBJ_FILTER), $(CPP_OBJ_TEMP))
+
+#-------------------------------------------------------------------------------
+# Assembler source files and objects
+#-------------------------------------------------------------------------------
+A_SRC=$(wildcard $(PROJECT_BASE_PATH)/*.s)
+
+A_OBJ_TEMP=$(patsubst %.s, %.o, $(notdir $(A_SRC)))
+
+# during development, remove some files
+A_OBJ_FILTER=
+
+A_OBJ=$(filter-out $(A_OBJ_FILTER), $(A_OBJ_TEMP))
+
+#-------------------------------------------------------------------------------
+# Rules
+#-------------------------------------------------------------------------------
+all: $(VARIANT)
+
+$(VARIANT): create_output $(OUTPUT_LIB)
+
+.PHONY: create_output
+create_output:
+	@echo --- Preparing $(VARIANT) files in $(OUTPUT_PATH) $(OUTPUT_BIN) 
+	@echo -------------------------
+	@echo *$(INCLUDES)
+	@echo -------------------------
+	@echo *$(C_SRC)
+	@echo -------------------------
+	@echo *$(C_OBJ)
+	@echo -------------------------
+	@echo *$(addprefix $(OUTPUT_PATH)/, $(C_OBJ))
+	@echo -------------------------
+	@echo *$(CPP_SRC)
+	@echo -------------------------
+	@echo *$(CPP_OBJ)
+	@echo -------------------------
+	@echo *$(addprefix $(OUTPUT_PATH)/, $(CPP_OBJ))
+	@echo -------------------------
+	@echo *$(A_SRC)
+	@echo -------------------------
+
+	-@mkdir $(OUTPUT_PATH) 1>NUL 2>&1
+
+$(addprefix $(OUTPUT_PATH)/,$(C_OBJ)): $(OUTPUT_PATH)/%.o: %.c
+#	@$(CC) -v -c $(CFLAGS) $< -o $@
+	@$(CC) -c $(CFLAGS) $< -o $@
+
+$(addprefix $(OUTPUT_PATH)/,$(CPP_OBJ)): $(OUTPUT_PATH)/%.o: %.cpp
+#	@$(CC) -c $(CPPFLAGS) $< -o $@
+	@$(CC) -xc++ -c $(CPPFLAGS) $< -o $@
+
+$(addprefix $(OUTPUT_PATH)/,$(A_OBJ)): $(OUTPUT_PATH)/%.o: %.s
+	@$(AS) -c $(ASFLAGS) $< -o $@
+
+$(OUTPUT_LIB): $(addprefix $(OUTPUT_PATH)/, $(C_OBJ)) $(addprefix $(OUTPUT_PATH)/, $(CPP_OBJ)) $(addprefix $(OUTPUT_PATH)/, $(A_OBJ))
+	@$(AR) -v -r "$(OUTPUT_BIN)/$@" $^
+	@$(NM) "$(OUTPUT_BIN)/$@" > "$(OUTPUT_BIN)/$@.txt"
+
+
+.PHONY: clean
+clean:
+	@echo --- Cleaning $(VARIANT) files [$(OUTPUT_PATH)$(SEP)*.o]
+	-@$(RM) $(OUTPUT_PATH) 1>NUL 2>&1
+	-@$(RM) $(OUTPUT_BIN)/$(OUTPUT_LIB) 1>NUL 2>&1
diff --git a/hardware/sam/variants/sam3u_ek/build_gcc/release.mk b/hardware/sam/variants/sam3u_ek/build_gcc/release.mk
new file mode 100644
index 000000000..0d15157f4
--- /dev/null
+++ b/hardware/sam/variants/sam3u_ek/build_gcc/release.mk
@@ -0,0 +1,25 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Optimization level
+# -O1 Optimize
+# -O2 Optimize even more
+# -O3 Optimize yet more
+# -O0 Reduce compilation time and make debugging produce the expected results
+# -Os Optimize for size
+OPTIMIZATION = -Os
diff --git a/hardware/sam/variants/sam3u_ek/debug_scripts/gcc/sam3u_ek_flash.gdb b/hardware/sam/variants/sam3u_ek/debug_scripts/gcc/sam3u_ek_flash.gdb
new file mode 100644
index 000000000..a0fb3fd20
--- /dev/null
+++ b/hardware/sam/variants/sam3u_ek/debug_scripts/gcc/sam3u_ek_flash.gdb
@@ -0,0 +1,33 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in flash.
+#
+
+# define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+# Reset the chip to get to a known state
+monitor reset
+
+# Select flash device
+monitor flash device = AT91SAM3U4E
+# Enable flash download and flash breakpoints
+monitor flash download = 1
+# Load the program
+load
+
+# Reset peripheral  (RSTC_CR)
+set *0x400e1200 = 0xA5000004
+
+# Initializing PC and stack pointer
+mon reg sp=(0x80000)
+set *0x80004 = *0x80004 & 0xFFFFFFFE
+mon reg pc=(0x80004)
+info reg
+
+break main
+
+# end of 'reset' command
+end
diff --git a/hardware/sam/variants/sam3u_ek/debug_scripts/gcc/sam3u_ek_sram.gdb b/hardware/sam/variants/sam3u_ek/debug_scripts/gcc/sam3u_ek_sram.gdb
new file mode 100644
index 000000000..5fa44e23c
--- /dev/null
+++ b/hardware/sam/variants/sam3u_ek/debug_scripts/gcc/sam3u_ek_sram.gdb
@@ -0,0 +1,29 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in flash.
+#
+
+# define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+# Reset the chip to get to a known state
+monitor reset
+
+# Load the program
+load
+
+# Reset peripheral  (RSTC_CR)
+set *0x400e1200 = 0xA5000004
+
+# Initializing PC and stack pointer
+mon reg sp=(0x20000000)
+set *0x20000004 = *0x20000004 & 0xFFFFFFFE
+mon reg pc=(0x20000004)
+info reg
+
+break main
+
+# end of 'reset' command
+end
diff --git a/hardware/sam/variants/sam3u_ek/debug_scripts/iar/sam3u_ek_flash.mac b/hardware/sam/variants/sam3u_ek/debug_scripts/iar/sam3u_ek_flash.mac
new file mode 100644
index 000000000..959583582
--- /dev/null
+++ b/hardware/sam/variants/sam3u_ek/debug_scripts/iar/sam3u_ek_flash.mac
@@ -0,0 +1,44 @@
+// ---------------------------------------------------------
+//   ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ---------------------------------------------------------
+// The software is delivered "AS IS" without warranty or
+// condition of any  kind, either express, implied or
+// statutory. This includes without limitation any warranty
+// or condition with respect to merchantability or fitness
+// for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ---------------------------------------------------------
+//  File: at91sam3u-ek-flash.mac
+//  User setup file for CSPY debugger.
+// ---------------------------------------------------------
+__var __mac_i;
+__var __mac_pt;
+
+/*********************************************************************
+*
+*       execUserReset()
+*/
+execUserReset()
+{
+    __message "------------------------------ execUserReset ---------------------------------";
+    __message "-------------------------------Set PC Reset ----------------------------------";
+
+    __hwReset(0);
+
+    // perpheral reset RSTC_CR
+    __writeMemory32(0xA5000004,0x400e1200,"Memory");
+}
+
+/*********************************************************************
+*
+*       execUserPreload()
+*/
+execUserPreload()
+{
+    __message "------------------------------ execUserPreload ---------------------------------";
+
+    __hwReset(0);                          //* Hardware Reset: CPU is automatically halted after the reset
+
+    // perpheral reset RSTC_CR
+    __writeMemory32(0xA5000004,0x400e1200,"Memory");
+}
diff --git a/hardware/sam/variants/sam3u_ek/debug_scripts/iar/sam3u_ek_sram.mac b/hardware/sam/variants/sam3u_ek/debug_scripts/iar/sam3u_ek_sram.mac
new file mode 100644
index 000000000..ba86029d3
--- /dev/null
+++ b/hardware/sam/variants/sam3u_ek/debug_scripts/iar/sam3u_ek_sram.mac
@@ -0,0 +1,44 @@
+// ---------------------------------------------------------
+//   ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ---------------------------------------------------------
+// The software is delivered "AS IS" without warranty or
+// condition of any  kind, either express, implied or
+// statutory. This includes without limitation any warranty
+// or condition with respect to merchantability or fitness
+// for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ---------------------------------------------------------
+//  File: at91sam3u-ek-sram.mac
+//  User setup file for CSPY debugger.
+// ---------------------------------------------------------
+__var __mac_i;
+__var __mac_pt;
+
+/*********************************************************************
+*
+*       execUserReset()
+*/
+execUserReset()
+{
+    __message "------------------------------ execUserReset ---------------------------------";
+    __message "-------------------------------Set PC Reset ----------------------------------";
+
+     //__hwReset(50);
+
+    // perpheral reset RSTC_CR
+    __writeMemory32(0xA5000004,0x400e1200,"Memory");
+}
+
+/*********************************************************************
+*
+*       execUserPreload()
+*/
+execUserPreload()
+{
+    __message "------------------------------ execUserPreload ---------------------------------";
+
+    __hwReset(0);                          //* Hardware Reset: CPU is automatically halted after the reset
+    
+    // perpheral reset RSTC_CR
+    __writeMemory32(0xA5000004,0x400e1200,"Memory");
+}
diff --git a/hardware/sam/variants/sam3u_ek/linker_scripts/gcc/flash.ld b/hardware/sam/variants/sam3u_ek/linker_scripts/gcc/flash.ld
new file mode 100644
index 000000000..c79e630a5
--- /dev/null
+++ b/hardware/sam/variants/sam3u_ek/linker_scripts/gcc/flash.ld
@@ -0,0 +1,150 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ *      Linker script for running in internal FLASH on the SAM3U4
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (W!RX) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
+	flash1 (W!RX) : ORIGIN = 0x00100000, LENGTH = 0x00020000 /* Flash1, 128K */
+	sram0  (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* Sram0, 32K */
+	sram1  (W!RX) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
+	rom (rx)    : ORIGIN = ORIGIN(flash1)-LENGTH(flash0), LENGTH = LENGTH(flash0)+LENGTH(flash1) /* Flash, 256K */
+	ram (rwx)   : ORIGIN = ORIGIN( sram1)-LENGTH( sram0), LENGTH = LENGTH( sram0)+LENGTH( sram1) /* sram, 48K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = 0x2000;
+
+/* Section Definitions */ 
+SECTIONS 
+{ 
+    .text : 
+    { 
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > flash0
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > flash0
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4); 
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > sram0
+
+    /* .bss section which is used for uninitialized data */ 
+    .bss (NOLOAD) :
+    { 
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > sram0
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+         _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > sram1
+
+    . = ALIGN(4); 
+    _end = . ; 
+}
diff --git a/hardware/sam/variants/sam3u_ek/linker_scripts/gcc/sram.ld b/hardware/sam/variants/sam3u_ek/linker_scripts/gcc/sram.ld
new file mode 100644
index 000000000..c8e21ad30
--- /dev/null
+++ b/hardware/sam/variants/sam3u_ek/linker_scripts/gcc/sram.ld
@@ -0,0 +1,150 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ *      Linker script for running in internal SRAM on the SAM3U4
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (W!RX) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
+	flash1 (W!RX) : ORIGIN = 0x00100000, LENGTH = 0x00020000 /* Flash1, 128K */
+	sram0  (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* Sram0, 32K */
+	sram1  (W!RX) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
+	rom (rx)    : ORIGIN = ORIGIN(flash1)-LENGTH(flash0), LENGTH = LENGTH(flash0)+LENGTH(flash1) /* Flash, 256K */
+	ram (rwx)   : ORIGIN = ORIGIN( sram1)-LENGTH( sram0), LENGTH = LENGTH( sram0)+LENGTH( sram1) /* sram, 48K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = 0x800;
+
+/* Section Definitions */ 
+SECTIONS 
+{ 
+    .text : 
+    { 
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > sram0
+
+    . = ALIGN(4); 
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > sram1
+
+    /* .bss section which is used for uninitialized data */ 
+    .bss (NOLOAD) :
+    { 
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > sram1
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+         _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > sram1
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > sram1
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4); 
+    _end = . ; 
+}
diff --git a/hardware/sam/variants/sam3u_ek/linker_scripts/iar/flash.icf b/hardware/sam/variants/sam3u_ek/linker_scripts/iar/flash.icf
new file mode 100644
index 000000000..956230fbd
--- /dev/null
+++ b/hardware/sam/variants/sam3u_ek/linker_scripts/iar/flash.icf
@@ -0,0 +1,49 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x00080000; /*Add for CMSIS*/
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM0_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM0_end__    = 0x20007FFF;
+define symbol __ICFEDIT_region_RAM1_start__  = 0x20080000;
+define symbol __ICFEDIT_region_RAM1_end__    = 0x20083FFF;
+define symbol __ICFEDIT_region_ROM0_start__  = 0x00080000;
+define symbol __ICFEDIT_region_ROM0_end__    = 0x0009FFFF;
+define symbol __ICFEDIT_region_ROM1_start__  = 0x00100000;
+define symbol __ICFEDIT_region_ROM1_end__    = 0x0011FFFF;
+/*-Sizes-*/
+/*define symbol __ICFEDIT_size_cstack__        = 0x1000;*//*for nandflash*/
+define symbol __ICFEDIT_size_cstack__        = 0x2000;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/*-Specials-*/
+/*define symbol __ICFEDIT_region_RAM_VECT_start__ = __ICFEDIT_region_RAM0_start__;*/ /*Referenced for CMSIS*/
+/*define symbol __ICFEDIT_size_vectors__          = 0x100;*/ /*Referenced for CMSIS*/
+/*-Exports-*/
+/*export symbol __ICFEDIT_region_RAM_VECT_start__;*/
+export symbol __ICFEDIT_vector_start__; /*Add for CMSIS*/
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+/*define region RAM_VECT_region = mem:[from __ICFEDIT_region_RAM_VECT_start__ size __ICFEDIT_size_vectors__];*/ /*Referenced for CMSIS*/
+/*define region RAM0_region     = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__];*/ /*Referenced for CMSIS*/
+define region RAM0_region     = mem:[from __ICFEDIT_region_RAM0_start__ to __ICFEDIT_region_RAM0_end__];
+define region RAM1_region     = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];
+/*define region RAM_region      = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__] |
+                                mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];*/ /*Referenced for CMSIS*/
+define region ROM0_region     = mem:[from __ICFEDIT_region_ROM0_start__ to __ICFEDIT_region_ROM0_end__];
+define region ROM1_region     = mem:[from __ICFEDIT_region_ROM1_start__ to __ICFEDIT_region_ROM1_end__];
+
+/*define block RamVect   with alignment = 8, size = __ICFEDIT_size_vectors__  { };*/
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+/*place at start of ROM0_region { readonly section .vectors };*/ /*Referenced for CMSIS*/
+place at address mem:__ICFEDIT_vector_start__ { readonly section .intvec }; /*Add for CMSIS*/
+place in ROM0_region          { readonly };
+place in RAM0_region          { readwrite, block HEAP };
+place in RAM1_region          { block CSTACK }; /* for nandflash*/
+/*place in RAM_VECT_region      { block RamVect };*/ /*Referenced for CMSIS*/
\ No newline at end of file
diff --git a/hardware/sam/variants/sam3u_ek/linker_scripts/iar/sram.icf b/hardware/sam/variants/sam3u_ek/linker_scripts/iar/sram.icf
new file mode 100644
index 000000000..d7d33537a
--- /dev/null
+++ b/hardware/sam/variants/sam3u_ek/linker_scripts/iar/sram.icf
@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM0_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM0_end__    = 0x20007FFF;
+define symbol __ICFEDIT_region_RAM1_start__  = 0x20080000;
+define symbol __ICFEDIT_region_RAM1_end__    = 0x20083FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x900;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/*-Exports-*/
+export symbol __ICFEDIT_vector_start__;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+define region RAM0_region     = mem:[from __ICFEDIT_region_RAM0_start__ to __ICFEDIT_region_RAM0_end__];
+define region RAM1_region     = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];
+/*define region RAM_region      = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__] |
+                                mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];*/
+
+/* define block RamVect   with alignment = 8, size = __ICFEDIT_size_vectors__  { }; */
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_vector_start__ { readonly section .intvec };
+place in RAM0_region          { readonly };
+place in RAM1_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/sam/variants/sam3u_ek/pins.xls b/hardware/sam/variants/sam3u_ek/pins.xls
new file mode 100644
index 000000000..4b1389fbf
Binary files /dev/null and b/hardware/sam/variants/sam3u_ek/pins.xls differ
diff --git a/hardware/sam/variants/sam3u_ek/variant.cpp b/hardware/sam/variants/sam3u_ek/variant.cpp
new file mode 100644
index 000000000..f2c160046
--- /dev/null
+++ b/hardware/sam/variants/sam3u_ek/variant.cpp
@@ -0,0 +1,171 @@
+/*
+  Copyright (c) 2011 Arduino.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include "variant.h"
+
+/*
+ * Pins descriptions
+ */
+extern const PinDescription g_APinDescription[]=
+{
+  // LEDS, 0..2
+  { PIOB, PIO_PB0, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT }, // LED BLUE
+  { PIOB, PIO_PB1, ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT }, // LED GREEN
+  { PIOB, PIO_PB2, ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT }, // LED RED
+
+  // USB, 3..3
+  { PIOA, PIO_PA0, ID_PIOA, PIO_INPUT, PIO_PULLUP }, // USB_VBUS
+
+  // UART (Serial), 4..6
+  { PIOA, PIO_PA11A_URXD, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // URXD
+  { PIOA, PIO_PA12A_UTXD, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // UTXD
+  { PIOA, PIO_PA11A_URXD|PIO_PA12A_UTXD, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // All UART pins
+
+  // Push buttons, 7..8
+  { PIOA, PIO_PA18, ID_PIOA, PIO_INPUT, PIO_PULLUP | PIO_DEGLITCH }, // PB_LEFT
+  { PIOA, PIO_PA19, ID_PIOA, PIO_INPUT, PIO_PULLUP | PIO_DEGLITCH }, // PB_RIGHT
+
+  // MCI (SDCARD), 9..19
+  { PIOA, PIO_PA25, ID_PIOA, PIO_INPUT, PIO_PULLUP }, // MCI Card Detect
+  { PIOA, PIO_PA5A_MCDA0, ID_PIOA, PIO_PERIPH_A, PIO_PULLUP }, // MCDA0
+  { PIOA, PIO_PA6A_MCDA1, ID_PIOA, PIO_PERIPH_A, PIO_PULLUP }, // MCDA1
+  { PIOA, PIO_PA7A_MCDA2, ID_PIOA, PIO_PERIPH_A, PIO_PULLUP }, // MCDA2
+  { PIOA, PIO_PA8A_MCDA3, ID_PIOA, PIO_PERIPH_A, PIO_PULLUP }, // MCDA3
+  { PIOC, PIO_PC28B_MCDA4, ID_PIOC, PIO_PERIPH_B, PIO_PULLUP }, // MCDA4
+  { PIOC, PIO_PC29B_MCDA5, ID_PIOC, PIO_PERIPH_B, PIO_PULLUP }, // MCDA5
+  { PIOC, PIO_PC30B_MCDA6, ID_PIOC, PIO_PERIPH_B, PIO_PULLUP }, // MCDA6
+  { PIOC, PIO_PC31B_MCDA7, ID_PIOC, PIO_PERIPH_B, PIO_PULLUP }, // MCDA7
+  { PIOA, PIO_PA4A_MCCDA, ID_PIOA, PIO_PERIPH_A, PIO_PULLUP }, // MCCDA
+  { PIOA, PIO_PA3A_MCCK, ID_PIOA, PIO_PERIPH_A, PIO_PULLUP }, // MCCK
+
+  // SPI, 20..23
+  { PIOA, PIO_PA13A_MISO, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // MISO
+  { PIOA, PIO_PA14A_MOSI, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // MOSI
+  { PIOA, PIO_PA15A_SPCK, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // SPCK
+  { PIOC, PIO_PC14B_NPCS2, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT }, // NPCS2
+
+  // TouchScreen, 24..25
+  { PIOA, PIO_PA24, ID_PIOA, PIO_INPUT, PIO_PULLUP }, // IRQ_TSC
+  { PIOA, PIO_PA2, ID_PIOA, PIO_INPUT, PIO_PULLUP }, // BUSY_TSC
+
+  // USART1, 26..29
+  { PIOA, PIO_PA21A_RXD1, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // RXD1
+  { PIOA, PIO_PA20A_TXD1, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // TXD1
+  { PIOA, PIO_PA22B_RTS1, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // RTS1
+  { PIOA, PIO_PA23B_CTS1, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // CTS1
+
+  // LCD, 30..47
+  { PIOB, 0xFE01FE00, ID_PIOB, PIO_PERIPH_A, PIO_PULLUP }, // EBI Data bus PB9-16 PB25-31
+  { PIOB, PIO_PB23A_NWE, ID_PIOB, PIO_PERIPH_A, PIO_PULLUP }, // EBI_NWE
+  { PIOB, PIO_PB19A_NRD, ID_PIOB, PIO_PERIPH_A, PIO_PULLUP }, // EBI_NRD
+  { PIOC, PIO_PC16A_NCS2, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP }, // LCD CS
+  { PIOB, PIO_PB8, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT }, // LCD RS
+  { PIOC, PIO_PC19, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT }, // LCD BackLight
+
+  { NULL, 0, 0, PIO_NOT_A_PIN, PIO_DEFAULT } // END
+} ;
+
+/*
+ * UART objects
+ */
+RingBuffer rx_buffer1 ;
+RingBuffer tx_buffer1 ;
+
+UARTClass Serial( UART, UART_IRQn, ID_UART, &rx_buffer1, &tx_buffer1 ) ;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// IT handlers
+extern void UART_IrqHandler( void )
+{
+  Serial.IrqHandler() ;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+// ----------------------------------------------------------------------------
+/*
+ * USART objects
+ */
+RingBuffer rx_buffer2 ;
+RingBuffer tx_buffer2 ;
+RingBuffer rx_buffer3 ;
+RingBuffer tx_buffer3 ;
+
+USARTClass Serial2( USART0, USART0_IRQn, ID_USART0, &rx_buffer2, &tx_buffer2 ) ;
+USARTClass Serial3( USART1, USART1_IRQn, ID_USART1, &rx_buffer3, &tx_buffer3 ) ;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// IT handlers
+extern void USART0_IrqHandler( void )
+{
+  Serial2.IrqHandler() ;
+}
+
+extern void USART1_IrqHandler( void )
+{
+  Serial3.IrqHandler() ;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+// ----------------------------------------------------------------------------
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ *
+ */
+extern void init( void )
+{
+	SystemInit() ;
+
+    /* Set Systick to 1ms interval, common to all SAM3 variants */
+	if ( SysTick_Config( SystemCoreClock / 1000 ) )
+  {
+    /* Capture error */
+    while ( 1 ) ;
+	}
+
+  /* Disable watchdog, common to all SAM variants */
+  WDT_Disable( WDT ) ;
+
+  // Initialize UART Serial port 
+  PIO_Configure( g_APinDescription[PINS_UART].pPort, g_APinDescription[PINS_UART].ulPinType,
+                 g_APinDescription[PINS_UART].ulPin, g_APinDescription[PINS_UART].ulPinConfiguration ) ;
+
+  // Switch off Power LED
+  PIO_Configure( g_APinDescription[PIN_LED_RED].pPort, g_APinDescription[PIN_LED_RED].ulPinType,
+                 g_APinDescription[PIN_LED_RED].ulPin, g_APinDescription[PIN_LED_RED].ulPinConfiguration ) ;
+  PIO_Clear( g_APinDescription[PIN_LED_RED].pPort, g_APinDescription[PIN_LED_RED].ulPin ) ;
+}
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/hardware/sam/variants/sam3u_ek/variant.h b/hardware/sam/variants/sam3u_ek/variant.h
new file mode 100644
index 000000000..77b0fe305
--- /dev/null
+++ b/hardware/sam/variants/sam3u_ek/variant.h
@@ -0,0 +1,94 @@
+/*
+  Copyright (c) 2011 Arduino.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#ifndef _VARIANT_SAM3U_EK_
+#define _VARIANT_SAM3U_EK_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "Arduino.h"
+#include "UARTClass.h"
+#include "USARTClass.h"
+
+/**
+ * Libc porting layers
+ */
+#if defined (  __GNUC__  ) /* GCC CS3 */
+#    include  /** RedHat Newlib minimal stub */
+#endif
+
+/*----------------------------------------------------------------------------
+ *        Definitions
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------*/
+
+#ifndef sam3u_ek
+#define sam3u_ek
+#endif
+
+/** Name of the board */
+#define VARIANT_NAME "SAM3U-EK"
+
+/*
+#define VARIANT_REV_A
+#define VARIANT_REV_B
+#define VARIANT_REV_C
+#define VARIANT_REV_D
+*/
+
+/** Frequency of the board main oscillator */
+#define VARIANT_MAINOSC           12000000
+
+/** Master clock frequency */
+#define VARIANT_MCK               96000000
+
+/*----------------------------------------------------------------------------
+ *        Pins
+ *----------------------------------------------------------------------------*/
+
+#define PIN_LED_BLUE         (0u)
+#define PIN_LED_GREEN        (1u)
+#define PIN_LED_RED          (2u)
+#define PIN_LED              PIN_LED_BLUE
+#define PIN_LED2             PIN_LED_GREEN
+
+static const uint8_t SS   = 23 ;
+static const uint8_t MOSI = 21 ;
+static const uint8_t MISO = 20 ;
+static const uint8_t SCK  = 22 ;
+
+#define PINS_UART            (6u)
+
+/*----------------------------------------------------------------------------
+ *        Arduino objects - C++ only
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+
+extern UARTClass Serial ;
+
+extern USARTClass Serial2 ;
+extern USARTClass Serial3 ;
+
+#endif
+
+#endif /* _VARIANT_SAM3U_EK_ */
+
diff --git a/hardware/tools/README.txt b/hardware/tools/README.txt
new file mode 100644
index 000000000..4da5594ad
--- /dev/null
+++ b/hardware/tools/README.txt
@@ -0,0 +1 @@
+Here should be present the CodeSourcery ARM GCC toolchain
\ No newline at end of file